1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the RZ/G2E (R8A774C0) SoC 4 * 5 * Copyright (C) 2018 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/clock/r8a774c0-cpg-mssr.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/power/r8a774c0-sysc.h> 11 12/ { 13 compatible = "renesas,r8a774c0"; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 /* 18 * The external audio clocks are configured as 0 Hz fixed frequency 19 * clocks by default. 20 * Boards that provide audio clocks should override them. 21 */ 22 audio_clk_a: audio_clk_a { 23 compatible = "fixed-clock"; 24 #clock-cells = <0>; 25 clock-frequency = <0>; 26 }; 27 28 audio_clk_b: audio_clk_b { 29 compatible = "fixed-clock"; 30 #clock-cells = <0>; 31 clock-frequency = <0>; 32 }; 33 34 audio_clk_c: audio_clk_c { 35 compatible = "fixed-clock"; 36 #clock-cells = <0>; 37 clock-frequency = <0>; 38 }; 39 40 /* External CAN clock - to be overridden by boards that provide it */ 41 can_clk: can { 42 compatible = "fixed-clock"; 43 #clock-cells = <0>; 44 clock-frequency = <0>; 45 }; 46 47 cpus { 48 #address-cells = <1>; 49 #size-cells = <0>; 50 51 a53_0: cpu@0 { 52 compatible = "arm,cortex-a53", "arm,armv8"; 53 reg = <0>; 54 device_type = "cpu"; 55 power-domains = <&sysc R8A774C0_PD_CA53_CPU0>; 56 next-level-cache = <&L2_CA53>; 57 enable-method = "psci"; 58 }; 59 60 a53_1: cpu@1 { 61 compatible = "arm,cortex-a53", "arm,armv8"; 62 reg = <1>; 63 device_type = "cpu"; 64 power-domains = <&sysc R8A774C0_PD_CA53_CPU1>; 65 next-level-cache = <&L2_CA53>; 66 enable-method = "psci"; 67 }; 68 69 L2_CA53: cache-controller-0 { 70 compatible = "cache"; 71 power-domains = <&sysc R8A774C0_PD_CA53_SCU>; 72 cache-unified; 73 cache-level = <2>; 74 }; 75 }; 76 77 extal_clk: extal { 78 compatible = "fixed-clock"; 79 #clock-cells = <0>; 80 /* This value must be overridden by the board */ 81 clock-frequency = <0>; 82 }; 83 84 /* External PCIe clock - can be overridden by the board */ 85 pcie_bus_clk: pcie_bus { 86 compatible = "fixed-clock"; 87 #clock-cells = <0>; 88 clock-frequency = <0>; 89 }; 90 91 pmu_a53 { 92 compatible = "arm,cortex-a53-pmu"; 93 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 94 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 95 interrupt-affinity = <&a53_0>, <&a53_1>; 96 }; 97 98 psci { 99 compatible = "arm,psci-1.0", "arm,psci-0.2"; 100 method = "smc"; 101 }; 102 103 /* External SCIF clock - to be overridden by boards that provide it */ 104 scif_clk: scif { 105 compatible = "fixed-clock"; 106 #clock-cells = <0>; 107 clock-frequency = <0>; 108 }; 109 110 soc: soc { 111 compatible = "simple-bus"; 112 interrupt-parent = <&gic>; 113 #address-cells = <2>; 114 #size-cells = <2>; 115 ranges; 116 117 rwdt: watchdog@e6020000 { 118 compatible = "renesas,r8a774c0-wdt", 119 "renesas,rcar-gen3-wdt"; 120 reg = <0 0xe6020000 0 0x0c>; 121 clocks = <&cpg CPG_MOD 402>; 122 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 123 resets = <&cpg 402>; 124 status = "disabled"; 125 }; 126 127 gpio0: gpio@e6050000 { 128 compatible = "renesas,gpio-r8a774c0", 129 "renesas,rcar-gen3-gpio"; 130 reg = <0 0xe6050000 0 0x50>; 131 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 132 #gpio-cells = <2>; 133 gpio-controller; 134 gpio-ranges = <&pfc 0 0 18>; 135 #interrupt-cells = <2>; 136 interrupt-controller; 137 clocks = <&cpg CPG_MOD 912>; 138 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 139 resets = <&cpg 912>; 140 }; 141 142 gpio1: gpio@e6051000 { 143 compatible = "renesas,gpio-r8a774c0", 144 "renesas,rcar-gen3-gpio"; 145 reg = <0 0xe6051000 0 0x50>; 146 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 147 #gpio-cells = <2>; 148 gpio-controller; 149 gpio-ranges = <&pfc 0 32 23>; 150 #interrupt-cells = <2>; 151 interrupt-controller; 152 clocks = <&cpg CPG_MOD 911>; 153 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 154 resets = <&cpg 911>; 155 }; 156 157 gpio2: gpio@e6052000 { 158 compatible = "renesas,gpio-r8a774c0", 159 "renesas,rcar-gen3-gpio"; 160 reg = <0 0xe6052000 0 0x50>; 161 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 162 #gpio-cells = <2>; 163 gpio-controller; 164 gpio-ranges = <&pfc 0 64 26>; 165 #interrupt-cells = <2>; 166 interrupt-controller; 167 clocks = <&cpg CPG_MOD 910>; 168 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 169 resets = <&cpg 910>; 170 }; 171 172 gpio3: gpio@e6053000 { 173 compatible = "renesas,gpio-r8a774c0", 174 "renesas,rcar-gen3-gpio"; 175 reg = <0 0xe6053000 0 0x50>; 176 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 177 #gpio-cells = <2>; 178 gpio-controller; 179 gpio-ranges = <&pfc 0 96 16>; 180 #interrupt-cells = <2>; 181 interrupt-controller; 182 clocks = <&cpg CPG_MOD 909>; 183 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 184 resets = <&cpg 909>; 185 }; 186 187 gpio4: gpio@e6054000 { 188 compatible = "renesas,gpio-r8a774c0", 189 "renesas,rcar-gen3-gpio"; 190 reg = <0 0xe6054000 0 0x50>; 191 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 192 #gpio-cells = <2>; 193 gpio-controller; 194 gpio-ranges = <&pfc 0 128 11>; 195 #interrupt-cells = <2>; 196 interrupt-controller; 197 clocks = <&cpg CPG_MOD 908>; 198 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 199 resets = <&cpg 908>; 200 }; 201 202 gpio5: gpio@e6055000 { 203 compatible = "renesas,gpio-r8a774c0", 204 "renesas,rcar-gen3-gpio"; 205 reg = <0 0xe6055000 0 0x50>; 206 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 207 #gpio-cells = <2>; 208 gpio-controller; 209 gpio-ranges = <&pfc 0 160 20>; 210 #interrupt-cells = <2>; 211 interrupt-controller; 212 clocks = <&cpg CPG_MOD 907>; 213 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 214 resets = <&cpg 907>; 215 }; 216 217 gpio6: gpio@e6055400 { 218 compatible = "renesas,gpio-r8a774c0", 219 "renesas,rcar-gen3-gpio"; 220 reg = <0 0xe6055400 0 0x50>; 221 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 222 #gpio-cells = <2>; 223 gpio-controller; 224 gpio-ranges = <&pfc 0 192 18>; 225 #interrupt-cells = <2>; 226 interrupt-controller; 227 clocks = <&cpg CPG_MOD 906>; 228 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 229 resets = <&cpg 906>; 230 }; 231 232 pfc: pin-controller@e6060000 { 233 compatible = "renesas,pfc-r8a774c0"; 234 reg = <0 0xe6060000 0 0x508>; 235 }; 236 237 cpg: clock-controller@e6150000 { 238 compatible = "renesas,r8a774c0-cpg-mssr"; 239 reg = <0 0xe6150000 0 0x1000>; 240 clocks = <&extal_clk>; 241 clock-names = "extal"; 242 #clock-cells = <2>; 243 #power-domain-cells = <0>; 244 #reset-cells = <1>; 245 }; 246 247 rst: reset-controller@e6160000 { 248 compatible = "renesas,r8a774c0-rst"; 249 reg = <0 0xe6160000 0 0x0200>; 250 }; 251 252 sysc: system-controller@e6180000 { 253 compatible = "renesas,r8a774c0-sysc"; 254 reg = <0 0xe6180000 0 0x0400>; 255 #power-domain-cells = <1>; 256 }; 257 258 thermal: thermal@e6190000 { 259 compatible = "renesas,thermal-r8a774c0"; 260 reg = <0 0xe6190000 0 0x10>, <0 0xe6190100 0 0x38>; 261 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 262 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 263 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 264 clocks = <&cpg CPG_MOD 522>; 265 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 266 resets = <&cpg 522>; 267 #thermal-sensor-cells = <0>; 268 }; 269 270 intc_ex: interrupt-controller@e61c0000 { 271 compatible = "renesas,intc-ex-r8a774c0", "renesas,irqc"; 272 #interrupt-cells = <2>; 273 interrupt-controller; 274 reg = <0 0xe61c0000 0 0x200>; 275 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH 276 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 277 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH 278 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH 279 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 280 GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 281 clocks = <&cpg CPG_MOD 407>; 282 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 283 resets = <&cpg 407>; 284 }; 285 286 i2c0: i2c@e6500000 { 287 #address-cells = <1>; 288 #size-cells = <0>; 289 compatible = "renesas,i2c-r8a774c0", 290 "renesas,rcar-gen3-i2c"; 291 reg = <0 0xe6500000 0 0x40>; 292 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 293 clocks = <&cpg CPG_MOD 931>; 294 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 295 resets = <&cpg 931>; 296 dmas = <&dmac1 0x91>, <&dmac1 0x90>, 297 <&dmac2 0x91>, <&dmac2 0x90>; 298 dma-names = "tx", "rx", "tx", "rx"; 299 i2c-scl-internal-delay-ns = <110>; 300 status = "disabled"; 301 }; 302 303 i2c1: i2c@e6508000 { 304 #address-cells = <1>; 305 #size-cells = <0>; 306 compatible = "renesas,i2c-r8a774c0", 307 "renesas,rcar-gen3-i2c"; 308 reg = <0 0xe6508000 0 0x40>; 309 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 310 clocks = <&cpg CPG_MOD 930>; 311 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 312 resets = <&cpg 930>; 313 dmas = <&dmac1 0x93>, <&dmac1 0x92>, 314 <&dmac2 0x93>, <&dmac2 0x92>; 315 dma-names = "tx", "rx", "tx", "rx"; 316 i2c-scl-internal-delay-ns = <6>; 317 status = "disabled"; 318 }; 319 320 i2c2: i2c@e6510000 { 321 #address-cells = <1>; 322 #size-cells = <0>; 323 compatible = "renesas,i2c-r8a774c0", 324 "renesas,rcar-gen3-i2c"; 325 reg = <0 0xe6510000 0 0x40>; 326 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 327 clocks = <&cpg CPG_MOD 929>; 328 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 329 resets = <&cpg 929>; 330 dmas = <&dmac1 0x95>, <&dmac1 0x94>, 331 <&dmac2 0x95>, <&dmac2 0x94>; 332 dma-names = "tx", "rx", "tx", "rx"; 333 i2c-scl-internal-delay-ns = <6>; 334 status = "disabled"; 335 }; 336 337 i2c3: i2c@e66d0000 { 338 #address-cells = <1>; 339 #size-cells = <0>; 340 compatible = "renesas,i2c-r8a774c0", 341 "renesas,rcar-gen3-i2c"; 342 reg = <0 0xe66d0000 0 0x40>; 343 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 344 clocks = <&cpg CPG_MOD 928>; 345 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 346 resets = <&cpg 928>; 347 dmas = <&dmac0 0x97>, <&dmac0 0x96>; 348 dma-names = "tx", "rx"; 349 i2c-scl-internal-delay-ns = <110>; 350 status = "disabled"; 351 }; 352 353 i2c4: i2c@e66d8000 { 354 #address-cells = <1>; 355 #size-cells = <0>; 356 compatible = "renesas,i2c-r8a774c0", 357 "renesas,rcar-gen3-i2c"; 358 reg = <0 0xe66d8000 0 0x40>; 359 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 360 clocks = <&cpg CPG_MOD 927>; 361 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 362 resets = <&cpg 927>; 363 dmas = <&dmac0 0x99>, <&dmac0 0x98>; 364 dma-names = "tx", "rx"; 365 i2c-scl-internal-delay-ns = <6>; 366 status = "disabled"; 367 }; 368 369 i2c5: i2c@e66e0000 { 370 #address-cells = <1>; 371 #size-cells = <0>; 372 compatible = "renesas,i2c-r8a774c0", 373 "renesas,rcar-gen3-i2c"; 374 reg = <0 0xe66e0000 0 0x40>; 375 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 376 clocks = <&cpg CPG_MOD 919>; 377 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 378 resets = <&cpg 919>; 379 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; 380 dma-names = "tx", "rx"; 381 i2c-scl-internal-delay-ns = <6>; 382 status = "disabled"; 383 }; 384 385 i2c6: i2c@e66e8000 { 386 #address-cells = <1>; 387 #size-cells = <0>; 388 compatible = "renesas,i2c-r8a774c0", 389 "renesas,rcar-gen3-i2c"; 390 reg = <0 0xe66e8000 0 0x40>; 391 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 392 clocks = <&cpg CPG_MOD 918>; 393 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 394 resets = <&cpg 918>; 395 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; 396 dma-names = "tx", "rx"; 397 i2c-scl-internal-delay-ns = <6>; 398 status = "disabled"; 399 }; 400 401 i2c7: i2c@e6690000 { 402 #address-cells = <1>; 403 #size-cells = <0>; 404 compatible = "renesas,i2c-r8a774c0", 405 "renesas,rcar-gen3-i2c"; 406 reg = <0 0xe6690000 0 0x40>; 407 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 408 clocks = <&cpg CPG_MOD 1003>; 409 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 410 resets = <&cpg 1003>; 411 i2c-scl-internal-delay-ns = <6>; 412 status = "disabled"; 413 }; 414 415 i2c_dvfs: i2c@e60b0000 { 416 #address-cells = <1>; 417 #size-cells = <0>; 418 compatible = "renesas,iic-r8a774c0"; 419 reg = <0 0xe60b0000 0 0x15>; 420 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 421 clocks = <&cpg CPG_MOD 926>; 422 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 423 resets = <&cpg 926>; 424 dmas = <&dmac0 0x11>, <&dmac0 0x10>; 425 dma-names = "tx", "rx"; 426 status = "disabled"; 427 }; 428 429 hscif0: serial@e6540000 { 430 compatible = "renesas,hscif-r8a774c0", 431 "renesas,rcar-gen3-hscif", 432 "renesas,hscif"; 433 reg = <0 0xe6540000 0 0x60>; 434 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 435 clocks = <&cpg CPG_MOD 520>, 436 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, 437 <&scif_clk>; 438 clock-names = "fck", "brg_int", "scif_clk"; 439 dmas = <&dmac1 0x31>, <&dmac1 0x30>, 440 <&dmac2 0x31>, <&dmac2 0x30>; 441 dma-names = "tx", "rx", "tx", "rx"; 442 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 443 resets = <&cpg 520>; 444 status = "disabled"; 445 }; 446 447 hscif1: serial@e6550000 { 448 compatible = "renesas,hscif-r8a774c0", 449 "renesas,rcar-gen3-hscif", 450 "renesas,hscif"; 451 reg = <0 0xe6550000 0 0x60>; 452 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 453 clocks = <&cpg CPG_MOD 519>, 454 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, 455 <&scif_clk>; 456 clock-names = "fck", "brg_int", "scif_clk"; 457 dmas = <&dmac1 0x33>, <&dmac1 0x32>, 458 <&dmac2 0x33>, <&dmac2 0x32>; 459 dma-names = "tx", "rx", "tx", "rx"; 460 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 461 resets = <&cpg 519>; 462 status = "disabled"; 463 }; 464 465 hscif2: serial@e6560000 { 466 compatible = "renesas,hscif-r8a774c0", 467 "renesas,rcar-gen3-hscif", 468 "renesas,hscif"; 469 reg = <0 0xe6560000 0 0x60>; 470 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 471 clocks = <&cpg CPG_MOD 518>, 472 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, 473 <&scif_clk>; 474 clock-names = "fck", "brg_int", "scif_clk"; 475 dmas = <&dmac1 0x35>, <&dmac1 0x34>, 476 <&dmac2 0x35>, <&dmac2 0x34>; 477 dma-names = "tx", "rx", "tx", "rx"; 478 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 479 resets = <&cpg 518>; 480 status = "disabled"; 481 }; 482 483 hscif3: serial@e66a0000 { 484 compatible = "renesas,hscif-r8a774c0", 485 "renesas,rcar-gen3-hscif", 486 "renesas,hscif"; 487 reg = <0 0xe66a0000 0 0x60>; 488 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 489 clocks = <&cpg CPG_MOD 517>, 490 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, 491 <&scif_clk>; 492 clock-names = "fck", "brg_int", "scif_clk"; 493 dmas = <&dmac0 0x37>, <&dmac0 0x36>; 494 dma-names = "tx", "rx"; 495 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 496 resets = <&cpg 517>; 497 status = "disabled"; 498 }; 499 500 hscif4: serial@e66b0000 { 501 compatible = "renesas,hscif-r8a774c0", 502 "renesas,rcar-gen3-hscif", 503 "renesas,hscif"; 504 reg = <0 0xe66b0000 0 0x60>; 505 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 506 clocks = <&cpg CPG_MOD 516>, 507 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, 508 <&scif_clk>; 509 clock-names = "fck", "brg_int", "scif_clk"; 510 dmas = <&dmac0 0x39>, <&dmac0 0x38>; 511 dma-names = "tx", "rx"; 512 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 513 resets = <&cpg 516>; 514 status = "disabled"; 515 }; 516 517 hsusb: usb@e6590000 { 518 compatible = "renesas,usbhs-r8a774c0", 519 "renesas,rcar-gen3-usbhs"; 520 reg = <0 0xe6590000 0 0x200>; 521 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 522 clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; 523 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, 524 <&usb_dmac1 0>, <&usb_dmac1 1>; 525 dma-names = "ch0", "ch1", "ch2", "ch3"; 526 renesas,buswait = <11>; 527 phys = <&usb2_phy0>; 528 phy-names = "usb"; 529 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 530 resets = <&cpg 704>, <&cpg 703>; 531 status = "disabled"; 532 }; 533 534 usb_dmac0: dma-controller@e65a0000 { 535 compatible = "renesas,r8a774c0-usb-dmac", 536 "renesas,usb-dmac"; 537 reg = <0 0xe65a0000 0 0x100>; 538 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 539 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 540 interrupt-names = "ch0", "ch1"; 541 clocks = <&cpg CPG_MOD 330>; 542 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 543 resets = <&cpg 330>; 544 #dma-cells = <1>; 545 dma-channels = <2>; 546 }; 547 548 usb_dmac1: dma-controller@e65b0000 { 549 compatible = "renesas,r8a774c0-usb-dmac", 550 "renesas,usb-dmac"; 551 reg = <0 0xe65b0000 0 0x100>; 552 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 553 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 554 interrupt-names = "ch0", "ch1"; 555 clocks = <&cpg CPG_MOD 331>; 556 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 557 resets = <&cpg 331>; 558 #dma-cells = <1>; 559 dma-channels = <2>; 560 }; 561 562 dmac0: dma-controller@e6700000 { 563 compatible = "renesas,dmac-r8a774c0", 564 "renesas,rcar-dmac"; 565 reg = <0 0xe6700000 0 0x10000>; 566 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH 567 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH 568 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH 569 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 570 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 571 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 572 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 573 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 574 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH 575 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH 576 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH 577 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH 578 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH 579 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 580 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH 581 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH 582 GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 583 interrupt-names = "error", 584 "ch0", "ch1", "ch2", "ch3", 585 "ch4", "ch5", "ch6", "ch7", 586 "ch8", "ch9", "ch10", "ch11", 587 "ch12", "ch13", "ch14", "ch15"; 588 clocks = <&cpg CPG_MOD 219>; 589 clock-names = "fck"; 590 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 591 resets = <&cpg 219>; 592 #dma-cells = <1>; 593 dma-channels = <16>; 594 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, 595 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, 596 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, 597 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, 598 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, 599 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, 600 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, 601 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; 602 }; 603 604 dmac1: dma-controller@e7300000 { 605 compatible = "renesas,dmac-r8a774c0", 606 "renesas,rcar-dmac"; 607 reg = <0 0xe7300000 0 0x10000>; 608 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 609 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 610 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH 611 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 612 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 613 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH 614 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 615 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH 616 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH 617 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH 618 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 619 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH 620 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 621 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH 622 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 623 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 624 GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; 625 interrupt-names = "error", 626 "ch0", "ch1", "ch2", "ch3", 627 "ch4", "ch5", "ch6", "ch7", 628 "ch8", "ch9", "ch10", "ch11", 629 "ch12", "ch13", "ch14", "ch15"; 630 clocks = <&cpg CPG_MOD 218>; 631 clock-names = "fck"; 632 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 633 resets = <&cpg 218>; 634 #dma-cells = <1>; 635 dma-channels = <16>; 636 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, 637 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, 638 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, 639 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, 640 <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, 641 <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, 642 <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, 643 <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; 644 }; 645 646 dmac2: dma-controller@e7310000 { 647 compatible = "renesas,dmac-r8a774c0", 648 "renesas,rcar-dmac"; 649 reg = <0 0xe7310000 0 0x10000>; 650 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH 651 GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH 652 GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH 653 GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH 654 GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH 655 GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH 656 GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH 657 GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH 658 GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH 659 GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 660 GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 661 GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH 662 GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH 663 GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH 664 GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH 665 GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH 666 GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; 667 interrupt-names = "error", 668 "ch0", "ch1", "ch2", "ch3", 669 "ch4", "ch5", "ch6", "ch7", 670 "ch8", "ch9", "ch10", "ch11", 671 "ch12", "ch13", "ch14", "ch15"; 672 clocks = <&cpg CPG_MOD 217>; 673 clock-names = "fck"; 674 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 675 resets = <&cpg 217>; 676 #dma-cells = <1>; 677 dma-channels = <16>; 678 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, 679 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, 680 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, 681 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, 682 <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, 683 <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, 684 <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, 685 <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; 686 }; 687 688 ipmmu_ds0: mmu@e6740000 { 689 compatible = "renesas,ipmmu-r8a774c0"; 690 reg = <0 0xe6740000 0 0x1000>; 691 renesas,ipmmu-main = <&ipmmu_mm 0>; 692 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 693 #iommu-cells = <1>; 694 }; 695 696 ipmmu_ds1: mmu@e7740000 { 697 compatible = "renesas,ipmmu-r8a774c0"; 698 reg = <0 0xe7740000 0 0x1000>; 699 renesas,ipmmu-main = <&ipmmu_mm 1>; 700 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 701 #iommu-cells = <1>; 702 }; 703 704 ipmmu_hc: mmu@e6570000 { 705 compatible = "renesas,ipmmu-r8a774c0"; 706 reg = <0 0xe6570000 0 0x1000>; 707 renesas,ipmmu-main = <&ipmmu_mm 2>; 708 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 709 #iommu-cells = <1>; 710 }; 711 712 ipmmu_mm: mmu@e67b0000 { 713 compatible = "renesas,ipmmu-r8a774c0"; 714 reg = <0 0xe67b0000 0 0x1000>; 715 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 716 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 717 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 718 #iommu-cells = <1>; 719 }; 720 721 ipmmu_mp: mmu@ec670000 { 722 compatible = "renesas,ipmmu-r8a774c0"; 723 reg = <0 0xec670000 0 0x1000>; 724 renesas,ipmmu-main = <&ipmmu_mm 4>; 725 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 726 #iommu-cells = <1>; 727 }; 728 729 ipmmu_pv0: mmu@fd800000 { 730 compatible = "renesas,ipmmu-r8a774c0"; 731 reg = <0 0xfd800000 0 0x1000>; 732 renesas,ipmmu-main = <&ipmmu_mm 6>; 733 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 734 #iommu-cells = <1>; 735 }; 736 737 ipmmu_vc0: mmu@fe6b0000 { 738 compatible = "renesas,ipmmu-r8a774c0"; 739 reg = <0 0xfe6b0000 0 0x1000>; 740 renesas,ipmmu-main = <&ipmmu_mm 12>; 741 power-domains = <&sysc R8A774C0_PD_A3VC>; 742 #iommu-cells = <1>; 743 }; 744 745 ipmmu_vi0: mmu@febd0000 { 746 compatible = "renesas,ipmmu-r8a774c0"; 747 reg = <0 0xfebd0000 0 0x1000>; 748 renesas,ipmmu-main = <&ipmmu_mm 14>; 749 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 750 #iommu-cells = <1>; 751 }; 752 753 ipmmu_vp0: mmu@fe990000 { 754 compatible = "renesas,ipmmu-r8a774c0"; 755 reg = <0 0xfe990000 0 0x1000>; 756 renesas,ipmmu-main = <&ipmmu_mm 16>; 757 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 758 #iommu-cells = <1>; 759 }; 760 761 avb: ethernet@e6800000 { 762 compatible = "renesas,etheravb-r8a774c0", 763 "renesas,etheravb-rcar-gen3"; 764 reg = <0 0xe6800000 0 0x800>; 765 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 766 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 767 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 768 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 769 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 770 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 771 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 772 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 773 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 774 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 775 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 776 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 777 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 778 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 779 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 780 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 781 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 782 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 783 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 784 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 785 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 786 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 787 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 788 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 789 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 790 interrupt-names = "ch0", "ch1", "ch2", "ch3", 791 "ch4", "ch5", "ch6", "ch7", 792 "ch8", "ch9", "ch10", "ch11", 793 "ch12", "ch13", "ch14", "ch15", 794 "ch16", "ch17", "ch18", "ch19", 795 "ch20", "ch21", "ch22", "ch23", 796 "ch24"; 797 clocks = <&cpg CPG_MOD 812>; 798 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 799 resets = <&cpg 812>; 800 phy-mode = "rgmii"; 801 iommus = <&ipmmu_ds0 16>; 802 #address-cells = <1>; 803 #size-cells = <0>; 804 status = "disabled"; 805 }; 806 807 can0: can@e6c30000 { 808 compatible = "renesas,can-r8a774c0", 809 "renesas,rcar-gen3-can"; 810 reg = <0 0xe6c30000 0 0x1000>; 811 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 812 clocks = <&cpg CPG_MOD 916>, <&can_clk>; 813 clock-names = "clkp1", "can_clk"; 814 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 815 resets = <&cpg 916>; 816 status = "disabled"; 817 }; 818 819 can1: can@e6c38000 { 820 compatible = "renesas,can-r8a774c0", 821 "renesas,rcar-gen3-can"; 822 reg = <0 0xe6c38000 0 0x1000>; 823 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 824 clocks = <&cpg CPG_MOD 915>, <&can_clk>; 825 clock-names = "clkp1", "can_clk"; 826 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 827 resets = <&cpg 915>; 828 status = "disabled"; 829 }; 830 831 pwm0: pwm@e6e30000 { 832 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; 833 reg = <0 0xe6e30000 0 0x8>; 834 clocks = <&cpg CPG_MOD 523>; 835 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 836 resets = <&cpg 523>; 837 #pwm-cells = <2>; 838 status = "disabled"; 839 }; 840 841 pwm1: pwm@e6e31000 { 842 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; 843 reg = <0 0xe6e31000 0 0x8>; 844 clocks = <&cpg CPG_MOD 523>; 845 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 846 resets = <&cpg 523>; 847 #pwm-cells = <2>; 848 status = "disabled"; 849 }; 850 851 pwm2: pwm@e6e32000 { 852 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; 853 reg = <0 0xe6e32000 0 0x8>; 854 clocks = <&cpg CPG_MOD 523>; 855 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 856 resets = <&cpg 523>; 857 #pwm-cells = <2>; 858 status = "disabled"; 859 }; 860 861 pwm3: pwm@e6e33000 { 862 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; 863 reg = <0 0xe6e33000 0 0x8>; 864 clocks = <&cpg CPG_MOD 523>; 865 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 866 resets = <&cpg 523>; 867 #pwm-cells = <2>; 868 status = "disabled"; 869 }; 870 871 pwm4: pwm@e6e34000 { 872 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; 873 reg = <0 0xe6e34000 0 0x8>; 874 clocks = <&cpg CPG_MOD 523>; 875 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 876 resets = <&cpg 523>; 877 #pwm-cells = <2>; 878 status = "disabled"; 879 }; 880 881 pwm5: pwm@e6e35000 { 882 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; 883 reg = <0 0xe6e35000 0 0x8>; 884 clocks = <&cpg CPG_MOD 523>; 885 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 886 resets = <&cpg 523>; 887 #pwm-cells = <2>; 888 status = "disabled"; 889 }; 890 891 pwm6: pwm@e6e36000 { 892 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; 893 reg = <0 0xe6e36000 0 0x8>; 894 clocks = <&cpg CPG_MOD 523>; 895 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 896 resets = <&cpg 523>; 897 #pwm-cells = <2>; 898 status = "disabled"; 899 }; 900 901 scif0: serial@e6e60000 { 902 compatible = "renesas,scif-r8a774c0", 903 "renesas,rcar-gen3-scif", "renesas,scif"; 904 reg = <0 0xe6e60000 0 64>; 905 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 906 clocks = <&cpg CPG_MOD 207>, 907 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, 908 <&scif_clk>; 909 clock-names = "fck", "brg_int", "scif_clk"; 910 dmas = <&dmac1 0x51>, <&dmac1 0x50>, 911 <&dmac2 0x51>, <&dmac2 0x50>; 912 dma-names = "tx", "rx", "tx", "rx"; 913 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 914 resets = <&cpg 207>; 915 status = "disabled"; 916 }; 917 918 scif1: serial@e6e68000 { 919 compatible = "renesas,scif-r8a774c0", 920 "renesas,rcar-gen3-scif", "renesas,scif"; 921 reg = <0 0xe6e68000 0 64>; 922 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 923 clocks = <&cpg CPG_MOD 206>, 924 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, 925 <&scif_clk>; 926 clock-names = "fck", "brg_int", "scif_clk"; 927 dmas = <&dmac1 0x53>, <&dmac1 0x52>, 928 <&dmac2 0x53>, <&dmac2 0x52>; 929 dma-names = "tx", "rx", "tx", "rx"; 930 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 931 resets = <&cpg 206>; 932 status = "disabled"; 933 }; 934 935 scif2: serial@e6e88000 { 936 compatible = "renesas,scif-r8a774c0", 937 "renesas,rcar-gen3-scif", "renesas,scif"; 938 reg = <0 0xe6e88000 0 64>; 939 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 940 clocks = <&cpg CPG_MOD 310>, 941 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, 942 <&scif_clk>; 943 clock-names = "fck", "brg_int", "scif_clk"; 944 dmas = <&dmac1 0x13>, <&dmac1 0x12>, 945 <&dmac2 0x13>, <&dmac2 0x12>; 946 dma-names = "tx", "rx", "tx", "rx"; 947 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 948 resets = <&cpg 310>; 949 status = "disabled"; 950 }; 951 952 scif3: serial@e6c50000 { 953 compatible = "renesas,scif-r8a774c0", 954 "renesas,rcar-gen3-scif", "renesas,scif"; 955 reg = <0 0xe6c50000 0 64>; 956 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 957 clocks = <&cpg CPG_MOD 204>, 958 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, 959 <&scif_clk>; 960 clock-names = "fck", "brg_int", "scif_clk"; 961 dmas = <&dmac0 0x57>, <&dmac0 0x56>; 962 dma-names = "tx", "rx"; 963 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 964 resets = <&cpg 204>; 965 status = "disabled"; 966 }; 967 968 scif4: serial@e6c40000 { 969 compatible = "renesas,scif-r8a774c0", 970 "renesas,rcar-gen3-scif", "renesas,scif"; 971 reg = <0 0xe6c40000 0 64>; 972 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 973 clocks = <&cpg CPG_MOD 203>, 974 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, 975 <&scif_clk>; 976 clock-names = "fck", "brg_int", "scif_clk"; 977 dmas = <&dmac0 0x59>, <&dmac0 0x58>; 978 dma-names = "tx", "rx"; 979 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 980 resets = <&cpg 203>; 981 status = "disabled"; 982 }; 983 984 scif5: serial@e6f30000 { 985 compatible = "renesas,scif-r8a774c0", 986 "renesas,rcar-gen3-scif", "renesas,scif"; 987 reg = <0 0xe6f30000 0 64>; 988 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 989 clocks = <&cpg CPG_MOD 202>, 990 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, 991 <&scif_clk>; 992 clock-names = "fck", "brg_int", "scif_clk"; 993 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, 994 <&dmac2 0x5b>, <&dmac2 0x5a>; 995 dma-names = "tx", "rx", "tx", "rx"; 996 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 997 resets = <&cpg 202>; 998 status = "disabled"; 999 }; 1000 1001 msiof0: spi@e6e90000 { 1002 compatible = "renesas,msiof-r8a774c0", 1003 "renesas,rcar-gen3-msiof"; 1004 reg = <0 0xe6e90000 0 0x0064>; 1005 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 1006 clocks = <&cpg CPG_MOD 211>; 1007 dmas = <&dmac1 0x41>, <&dmac1 0x40>, 1008 <&dmac2 0x41>, <&dmac2 0x40>; 1009 dma-names = "tx", "rx", "tx", "rx"; 1010 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1011 resets = <&cpg 211>; 1012 #address-cells = <1>; 1013 #size-cells = <0>; 1014 status = "disabled"; 1015 }; 1016 1017 msiof1: spi@e6ea0000 { 1018 compatible = "renesas,msiof-r8a774c0", 1019 "renesas,rcar-gen3-msiof"; 1020 reg = <0 0xe6ea0000 0 0x0064>; 1021 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1022 clocks = <&cpg CPG_MOD 210>; 1023 dmas = <&dmac1 0x43>, <&dmac1 0x42>, 1024 <&dmac2 0x43>, <&dmac2 0x42>; 1025 dma-names = "tx", "rx", "tx", "rx"; 1026 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1027 resets = <&cpg 210>; 1028 #address-cells = <1>; 1029 #size-cells = <0>; 1030 status = "disabled"; 1031 }; 1032 1033 msiof2: spi@e6c00000 { 1034 compatible = "renesas,msiof-r8a774c0", 1035 "renesas,rcar-gen3-msiof"; 1036 reg = <0 0xe6c00000 0 0x0064>; 1037 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1038 clocks = <&cpg CPG_MOD 209>; 1039 dmas = <&dmac0 0x45>, <&dmac0 0x44>; 1040 dma-names = "tx", "rx"; 1041 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1042 resets = <&cpg 209>; 1043 #address-cells = <1>; 1044 #size-cells = <0>; 1045 status = "disabled"; 1046 }; 1047 1048 msiof3: spi@e6c10000 { 1049 compatible = "renesas,msiof-r8a774c0", 1050 "renesas,rcar-gen3-msiof"; 1051 reg = <0 0xe6c10000 0 0x0064>; 1052 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1053 clocks = <&cpg CPG_MOD 208>; 1054 dmas = <&dmac0 0x47>, <&dmac0 0x46>; 1055 dma-names = "tx", "rx"; 1056 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1057 resets = <&cpg 208>; 1058 #address-cells = <1>; 1059 #size-cells = <0>; 1060 status = "disabled"; 1061 }; 1062 1063 vin4: video@e6ef4000 { 1064 compatible = "renesas,vin-r8a774c0"; 1065 reg = <0 0xe6ef4000 0 0x1000>; 1066 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1067 clocks = <&cpg CPG_MOD 807>; 1068 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1069 resets = <&cpg 807>; 1070 renesas,id = <4>; 1071 status = "disabled"; 1072 1073 ports { 1074 #address-cells = <1>; 1075 #size-cells = <0>; 1076 1077 port@1 { 1078 #address-cells = <1>; 1079 #size-cells = <0>; 1080 1081 reg = <1>; 1082 1083 vin4csi40: endpoint@2 { 1084 reg = <2>; 1085 remote-endpoint= <&csi40vin4>; 1086 }; 1087 }; 1088 }; 1089 }; 1090 1091 vin5: video@e6ef5000 { 1092 compatible = "renesas,vin-r8a774c0"; 1093 reg = <0 0xe6ef5000 0 0x1000>; 1094 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 1095 clocks = <&cpg CPG_MOD 806>; 1096 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1097 resets = <&cpg 806>; 1098 renesas,id = <5>; 1099 status = "disabled"; 1100 1101 ports { 1102 #address-cells = <1>; 1103 #size-cells = <0>; 1104 1105 port@1 { 1106 #address-cells = <1>; 1107 #size-cells = <0>; 1108 1109 reg = <1>; 1110 1111 vin5csi40: endpoint@2 { 1112 reg = <2>; 1113 remote-endpoint= <&csi40vin5>; 1114 }; 1115 }; 1116 }; 1117 }; 1118 1119 rcar_sound: sound@ec500000 { 1120 /* 1121 * #sound-dai-cells is required 1122 * 1123 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; 1124 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; 1125 */ 1126 /* 1127 * #clock-cells is required for audio_clkout0/1/2/3 1128 * 1129 * clkout : #clock-cells = <0>; <&rcar_sound>; 1130 * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; 1131 */ 1132 compatible = "renesas,rcar_sound-r8a774c0", 1133 "renesas,rcar_sound-gen3"; 1134 reg = <0 0xec500000 0 0x1000>, /* SCU */ 1135 <0 0xec5a0000 0 0x100>, /* ADG */ 1136 <0 0xec540000 0 0x1000>, /* SSIU */ 1137 <0 0xec541000 0 0x280>, /* SSI */ 1138 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ 1139 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; 1140 1141 clocks = <&cpg CPG_MOD 1005>, 1142 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, 1143 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, 1144 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, 1145 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, 1146 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, 1147 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, 1148 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, 1149 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, 1150 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, 1151 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, 1152 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 1153 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 1154 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, 1155 <&audio_clk_a>, <&audio_clk_b>, 1156 <&audio_clk_c>, 1157 <&cpg CPG_CORE R8A774C0_CLK_ZA2>; 1158 clock-names = "ssi-all", 1159 "ssi.9", "ssi.8", "ssi.7", "ssi.6", 1160 "ssi.5", "ssi.4", "ssi.3", "ssi.2", 1161 "ssi.1", "ssi.0", 1162 "src.9", "src.8", "src.7", "src.6", 1163 "src.5", "src.4", "src.3", "src.2", 1164 "src.1", "src.0", 1165 "mix.1", "mix.0", 1166 "ctu.1", "ctu.0", 1167 "dvc.0", "dvc.1", 1168 "clk_a", "clk_b", "clk_c", "clk_i"; 1169 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1170 resets = <&cpg 1005>, 1171 <&cpg 1006>, <&cpg 1007>, 1172 <&cpg 1008>, <&cpg 1009>, 1173 <&cpg 1010>, <&cpg 1011>, 1174 <&cpg 1012>, <&cpg 1013>, 1175 <&cpg 1014>, <&cpg 1015>; 1176 reset-names = "ssi-all", 1177 "ssi.9", "ssi.8", "ssi.7", "ssi.6", 1178 "ssi.5", "ssi.4", "ssi.3", "ssi.2", 1179 "ssi.1", "ssi.0"; 1180 status = "disabled"; 1181 1182 rcar_sound,dvc { 1183 dvc0: dvc-0 { 1184 dmas = <&audma0 0xbc>; 1185 dma-names = "tx"; 1186 }; 1187 dvc1: dvc-1 { 1188 dmas = <&audma0 0xbe>; 1189 dma-names = "tx"; 1190 }; 1191 }; 1192 1193 rcar_sound,mix { 1194 mix0: mix-0 { }; 1195 mix1: mix-1 { }; 1196 }; 1197 1198 rcar_sound,ctu { 1199 ctu00: ctu-0 { }; 1200 ctu01: ctu-1 { }; 1201 ctu02: ctu-2 { }; 1202 ctu03: ctu-3 { }; 1203 ctu10: ctu-4 { }; 1204 ctu11: ctu-5 { }; 1205 ctu12: ctu-6 { }; 1206 ctu13: ctu-7 { }; 1207 }; 1208 1209 rcar_sound,src { 1210 src0: src-0 { 1211 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 1212 dmas = <&audma0 0x85>, <&audma0 0x9a>; 1213 dma-names = "rx", "tx"; 1214 }; 1215 src1: src-1 { 1216 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1217 dmas = <&audma0 0x87>, <&audma0 0x9c>; 1218 dma-names = "rx", "tx"; 1219 }; 1220 src2: src-2 { 1221 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1222 dmas = <&audma0 0x89>, <&audma0 0x9e>; 1223 dma-names = "rx", "tx"; 1224 }; 1225 src3: src-3 { 1226 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1227 dmas = <&audma0 0x8b>, <&audma0 0xa0>; 1228 dma-names = "rx", "tx"; 1229 }; 1230 src4: src-4 { 1231 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1232 dmas = <&audma0 0x8d>, <&audma0 0xb0>; 1233 dma-names = "rx", "tx"; 1234 }; 1235 src5: src-5 { 1236 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1237 dmas = <&audma0 0x8f>, <&audma0 0xb2>; 1238 dma-names = "rx", "tx"; 1239 }; 1240 src6: src-6 { 1241 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1242 dmas = <&audma0 0x91>, <&audma0 0xb4>; 1243 dma-names = "rx", "tx"; 1244 }; 1245 src7: src-7 { 1246 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1247 dmas = <&audma0 0x93>, <&audma0 0xb6>; 1248 dma-names = "rx", "tx"; 1249 }; 1250 src8: src-8 { 1251 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1252 dmas = <&audma0 0x95>, <&audma0 0xb8>; 1253 dma-names = "rx", "tx"; 1254 }; 1255 src9: src-9 { 1256 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; 1257 dmas = <&audma0 0x97>, <&audma0 0xba>; 1258 dma-names = "rx", "tx"; 1259 }; 1260 }; 1261 1262 rcar_sound,ssi { 1263 ssi0: ssi-0 { 1264 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; 1265 dmas = <&audma0 0x01>, <&audma0 0x02>, 1266 <&audma0 0x15>, <&audma0 0x16>; 1267 dma-names = "rx", "tx", "rxu", "txu"; 1268 }; 1269 ssi1: ssi-1 { 1270 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; 1271 dmas = <&audma0 0x03>, <&audma0 0x04>, 1272 <&audma0 0x49>, <&audma0 0x4a>; 1273 dma-names = "rx", "tx", "rxu", "txu"; 1274 }; 1275 ssi2: ssi-2 { 1276 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; 1277 dmas = <&audma0 0x05>, <&audma0 0x06>, 1278 <&audma0 0x63>, <&audma0 0x64>; 1279 dma-names = "rx", "tx", "rxu", "txu"; 1280 }; 1281 ssi3: ssi-3 { 1282 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1283 dmas = <&audma0 0x07>, <&audma0 0x08>, 1284 <&audma0 0x6f>, <&audma0 0x70>; 1285 dma-names = "rx", "tx", "rxu", "txu"; 1286 }; 1287 ssi4: ssi-4 { 1288 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; 1289 dmas = <&audma0 0x09>, <&audma0 0x0a>, 1290 <&audma0 0x71>, <&audma0 0x72>; 1291 dma-names = "rx", "tx", "rxu", "txu"; 1292 }; 1293 ssi5: ssi-5 { 1294 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 1295 dmas = <&audma0 0x0b>, <&audma0 0x0c>, 1296 <&audma0 0x73>, <&audma0 0x74>; 1297 dma-names = "rx", "tx", "rxu", "txu"; 1298 }; 1299 ssi6: ssi-6 { 1300 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; 1301 dmas = <&audma0 0x0d>, <&audma0 0x0e>, 1302 <&audma0 0x75>, <&audma0 0x76>; 1303 dma-names = "rx", "tx", "rxu", "txu"; 1304 }; 1305 ssi7: ssi-7 { 1306 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; 1307 dmas = <&audma0 0x0f>, <&audma0 0x10>, 1308 <&audma0 0x79>, <&audma0 0x7a>; 1309 dma-names = "rx", "tx", "rxu", "txu"; 1310 }; 1311 ssi8: ssi-8 { 1312 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; 1313 dmas = <&audma0 0x11>, <&audma0 0x12>, 1314 <&audma0 0x7b>, <&audma0 0x7c>; 1315 dma-names = "rx", "tx", "rxu", "txu"; 1316 }; 1317 ssi9: ssi-9 { 1318 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; 1319 dmas = <&audma0 0x13>, <&audma0 0x14>, 1320 <&audma0 0x7d>, <&audma0 0x7e>; 1321 dma-names = "rx", "tx", "rxu", "txu"; 1322 }; 1323 }; 1324 }; 1325 1326 audma0: dma-controller@ec700000 { 1327 compatible = "renesas,dmac-r8a774c0", 1328 "renesas,rcar-dmac"; 1329 reg = <0 0xec700000 0 0x10000>; 1330 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH 1331 GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH 1332 GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH 1333 GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH 1334 GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH 1335 GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 1336 GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH 1337 GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH 1338 GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH 1339 GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH 1340 GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH 1341 GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH 1342 GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 1343 GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH 1344 GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH 1345 GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH 1346 GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 1347 interrupt-names = "error", 1348 "ch0", "ch1", "ch2", "ch3", 1349 "ch4", "ch5", "ch6", "ch7", 1350 "ch8", "ch9", "ch10", "ch11", 1351 "ch12", "ch13", "ch14", "ch15"; 1352 clocks = <&cpg CPG_MOD 502>; 1353 clock-names = "fck"; 1354 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1355 resets = <&cpg 502>; 1356 #dma-cells = <1>; 1357 dma-channels = <16>; 1358 iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>, 1359 <&ipmmu_mp 2>, <&ipmmu_mp 3>, 1360 <&ipmmu_mp 4>, <&ipmmu_mp 5>, 1361 <&ipmmu_mp 6>, <&ipmmu_mp 7>, 1362 <&ipmmu_mp 8>, <&ipmmu_mp 9>, 1363 <&ipmmu_mp 10>, <&ipmmu_mp 11>, 1364 <&ipmmu_mp 12>, <&ipmmu_mp 13>, 1365 <&ipmmu_mp 14>, <&ipmmu_mp 15>; 1366 }; 1367 1368 xhci0: usb@ee000000 { 1369 compatible = "renesas,xhci-r8a774c0", 1370 "renesas,rcar-gen3-xhci"; 1371 reg = <0 0xee000000 0 0xc00>; 1372 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 1373 clocks = <&cpg CPG_MOD 328>; 1374 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1375 resets = <&cpg 328>; 1376 status = "disabled"; 1377 }; 1378 1379 usb3_peri0: usb@ee020000 { 1380 compatible = "renesas,r8a774c0-usb3-peri", 1381 "renesas,rcar-gen3-usb3-peri"; 1382 reg = <0 0xee020000 0 0x400>; 1383 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 1384 clocks = <&cpg CPG_MOD 328>; 1385 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1386 resets = <&cpg 328>; 1387 status = "disabled"; 1388 }; 1389 1390 ohci0: usb@ee080000 { 1391 compatible = "generic-ohci"; 1392 reg = <0 0xee080000 0 0x100>; 1393 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1394 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 1395 phys = <&usb2_phy0>; 1396 phy-names = "usb"; 1397 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1398 resets = <&cpg 703>, <&cpg 704>; 1399 status = "disabled"; 1400 }; 1401 1402 ehci0: usb@ee080100 { 1403 compatible = "generic-ehci"; 1404 reg = <0 0xee080100 0 0x100>; 1405 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1406 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 1407 phys = <&usb2_phy0>; 1408 phy-names = "usb"; 1409 companion = <&ohci0>; 1410 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1411 resets = <&cpg 703>, <&cpg 704>; 1412 status = "disabled"; 1413 }; 1414 1415 usb2_phy0: usb-phy@ee080200 { 1416 compatible = "renesas,usb2-phy-r8a774c0", 1417 "renesas,rcar-gen3-usb2-phy"; 1418 reg = <0 0xee080200 0 0x700>; 1419 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1420 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 1421 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1422 resets = <&cpg 703>, <&cpg 704>; 1423 #phy-cells = <0>; 1424 status = "disabled"; 1425 }; 1426 1427 sdhi0: sd@ee100000 { 1428 compatible = "renesas,sdhi-r8a774c0", 1429 "renesas,rcar-gen3-sdhi"; 1430 reg = <0 0xee100000 0 0x2000>; 1431 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 1432 clocks = <&cpg CPG_MOD 314>; 1433 max-frequency = <200000000>; 1434 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1435 resets = <&cpg 314>; 1436 status = "disabled"; 1437 }; 1438 1439 sdhi1: sd@ee120000 { 1440 compatible = "renesas,sdhi-r8a774c0", 1441 "renesas,rcar-gen3-sdhi"; 1442 reg = <0 0xee120000 0 0x2000>; 1443 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1444 clocks = <&cpg CPG_MOD 313>; 1445 max-frequency = <200000000>; 1446 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1447 resets = <&cpg 313>; 1448 status = "disabled"; 1449 }; 1450 1451 sdhi3: sd@ee160000 { 1452 compatible = "renesas,sdhi-r8a774c0", 1453 "renesas,rcar-gen3-sdhi"; 1454 reg = <0 0xee160000 0 0x2000>; 1455 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 1456 clocks = <&cpg CPG_MOD 311>; 1457 max-frequency = <200000000>; 1458 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1459 resets = <&cpg 311>; 1460 status = "disabled"; 1461 }; 1462 1463 gic: interrupt-controller@f1010000 { 1464 compatible = "arm,gic-400"; 1465 #interrupt-cells = <3>; 1466 #address-cells = <0>; 1467 interrupt-controller; 1468 reg = <0x0 0xf1010000 0 0x1000>, 1469 <0x0 0xf1020000 0 0x20000>, 1470 <0x0 0xf1040000 0 0x20000>, 1471 <0x0 0xf1060000 0 0x20000>; 1472 interrupts = <GIC_PPI 9 1473 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 1474 clocks = <&cpg CPG_MOD 408>; 1475 clock-names = "clk"; 1476 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1477 resets = <&cpg 408>; 1478 }; 1479 1480 pciec0: pcie@fe000000 { 1481 compatible = "renesas,pcie-r8a774c0", 1482 "renesas,pcie-rcar-gen3"; 1483 reg = <0 0xfe000000 0 0x80000>; 1484 #address-cells = <3>; 1485 #size-cells = <2>; 1486 bus-range = <0x00 0xff>; 1487 device_type = "pci"; 1488 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000 1489 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000 1490 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000 1491 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; 1492 /* Map all possible DDR as inbound ranges */ 1493 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>; 1494 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1495 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1496 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1497 #interrupt-cells = <1>; 1498 interrupt-map-mask = <0 0 0 0>; 1499 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 1500 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; 1501 clock-names = "pcie", "pcie_bus"; 1502 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1503 resets = <&cpg 319>; 1504 status = "disabled"; 1505 }; 1506 1507 vspb0: vsp@fe960000 { 1508 compatible = "renesas,vsp2"; 1509 reg = <0 0xfe960000 0 0x8000>; 1510 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 1511 clocks = <&cpg CPG_MOD 626>; 1512 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1513 resets = <&cpg 626>; 1514 renesas,fcp = <&fcpvb0>; 1515 }; 1516 1517 fcpvb0: fcp@fe96f000 { 1518 compatible = "renesas,fcpv"; 1519 reg = <0 0xfe96f000 0 0x200>; 1520 clocks = <&cpg CPG_MOD 607>; 1521 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1522 resets = <&cpg 607>; 1523 iommus = <&ipmmu_vp0 5>; 1524 }; 1525 1526 vspi0: vsp@fe9a0000 { 1527 compatible = "renesas,vsp2"; 1528 reg = <0 0xfe9a0000 0 0x8000>; 1529 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>; 1530 clocks = <&cpg CPG_MOD 631>; 1531 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1532 resets = <&cpg 631>; 1533 renesas,fcp = <&fcpvi0>; 1534 }; 1535 1536 fcpvi0: fcp@fe9af000 { 1537 compatible = "renesas,fcpv"; 1538 reg = <0 0xfe9af000 0 0x200>; 1539 clocks = <&cpg CPG_MOD 611>; 1540 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1541 resets = <&cpg 611>; 1542 iommus = <&ipmmu_vp0 8>; 1543 }; 1544 1545 vspd0: vsp@fea20000 { 1546 compatible = "renesas,vsp2"; 1547 reg = <0 0xfea20000 0 0x7000>; 1548 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; 1549 clocks = <&cpg CPG_MOD 623>; 1550 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1551 resets = <&cpg 623>; 1552 renesas,fcp = <&fcpvd0>; 1553 }; 1554 1555 fcpvd0: fcp@fea27000 { 1556 compatible = "renesas,fcpv"; 1557 reg = <0 0xfea27000 0 0x200>; 1558 clocks = <&cpg CPG_MOD 603>; 1559 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1560 resets = <&cpg 603>; 1561 iommus = <&ipmmu_vi0 8>; 1562 }; 1563 1564 vspd1: vsp@fea28000 { 1565 compatible = "renesas,vsp2"; 1566 reg = <0 0xfea28000 0 0x7000>; 1567 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; 1568 clocks = <&cpg CPG_MOD 622>; 1569 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1570 resets = <&cpg 622>; 1571 renesas,fcp = <&fcpvd1>; 1572 }; 1573 1574 fcpvd1: fcp@fea2f000 { 1575 compatible = "renesas,fcpv"; 1576 reg = <0 0xfea2f000 0 0x200>; 1577 clocks = <&cpg CPG_MOD 602>; 1578 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1579 resets = <&cpg 602>; 1580 iommus = <&ipmmu_vi0 9>; 1581 }; 1582 1583 csi40: csi2@feaa0000 { 1584 compatible = "renesas,r8a774c0-csi2", 1585 "renesas,rcar-gen3-csi2"; 1586 reg = <0 0xfeaa0000 0 0x10000>; 1587 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 1588 clocks = <&cpg CPG_MOD 716>; 1589 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1590 resets = <&cpg 716>; 1591 status = "disabled"; 1592 1593 ports { 1594 #address-cells = <1>; 1595 #size-cells = <0>; 1596 1597 port@1 { 1598 #address-cells = <1>; 1599 #size-cells = <0>; 1600 1601 reg = <1>; 1602 1603 csi40vin4: endpoint@0 { 1604 reg = <0>; 1605 remote-endpoint = <&vin4csi40>; 1606 }; 1607 csi40vin5: endpoint@1 { 1608 reg = <1>; 1609 remote-endpoint = <&vin5csi40>; 1610 }; 1611 }; 1612 }; 1613 }; 1614 1615 du: display@feb00000 { 1616 compatible = "renesas,du-r8a774c0"; 1617 reg = <0 0xfeb00000 0 0x80000>; 1618 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 1619 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; 1620 clocks = <&cpg CPG_MOD 724>, 1621 <&cpg CPG_MOD 723>; 1622 clock-names = "du.0", "du.1"; 1623 vsps = <&vspd0 0 &vspd1 0>; 1624 status = "disabled"; 1625 1626 ports { 1627 #address-cells = <1>; 1628 #size-cells = <0>; 1629 1630 port@0 { 1631 reg = <0>; 1632 du_out_rgb: endpoint { 1633 }; 1634 }; 1635 1636 port@1 { 1637 reg = <1>; 1638 du_out_lvds0: endpoint { 1639 remote-endpoint = <&lvds0_in>; 1640 }; 1641 }; 1642 1643 port@2 { 1644 reg = <2>; 1645 du_out_lvds1: endpoint { 1646 remote-endpoint = <&lvds1_in>; 1647 }; 1648 }; 1649 }; 1650 }; 1651 1652 lvds0: lvds-encoder@feb90000 { 1653 compatible = "renesas,r8a774c0-lvds"; 1654 reg = <0 0xfeb90000 0 0x20>; 1655 clocks = <&cpg CPG_MOD 727>; 1656 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1657 resets = <&cpg 727>; 1658 status = "disabled"; 1659 1660 ports { 1661 #address-cells = <1>; 1662 #size-cells = <0>; 1663 1664 port@0 { 1665 reg = <0>; 1666 lvds0_in: endpoint { 1667 remote-endpoint = <&du_out_lvds0>; 1668 }; 1669 }; 1670 1671 port@1 { 1672 reg = <1>; 1673 lvds0_out: endpoint { 1674 }; 1675 }; 1676 }; 1677 }; 1678 1679 lvds1: lvds-encoder@feb90100 { 1680 compatible = "renesas,r8a774c0-lvds"; 1681 reg = <0 0xfeb90100 0 0x20>; 1682 clocks = <&cpg CPG_MOD 727>; 1683 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1684 resets = <&cpg 726>; 1685 status = "disabled"; 1686 1687 ports { 1688 #address-cells = <1>; 1689 #size-cells = <0>; 1690 1691 port@0 { 1692 reg = <0>; 1693 lvds1_in: endpoint { 1694 remote-endpoint = <&du_out_lvds1>; 1695 }; 1696 }; 1697 1698 port@1 { 1699 reg = <1>; 1700 lvds1_out: endpoint { 1701 }; 1702 }; 1703 }; 1704 }; 1705 1706 prr: chipid@fff00044 { 1707 compatible = "renesas,prr"; 1708 reg = <0 0xfff00044 0 4>; 1709 }; 1710 }; 1711 1712 thermal-zones { 1713 cpu-thermal { 1714 polling-delay-passive = <250>; 1715 polling-delay = <1000>; 1716 thermal-sensors = <&thermal>; 1717 1718 trips { 1719 cpu-crit { 1720 temperature = <120000>; 1721 hysteresis = <2000>; 1722 type = "critical"; 1723 }; 1724 }; 1725 1726 cooling-maps { 1727 }; 1728 }; 1729 }; 1730 1731 timer { 1732 compatible = "arm,armv8-timer"; 1733 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 1734 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 1735 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 1736 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 1737 }; 1738 1739 /* External USB clocks - can be overridden by the board */ 1740 usb3s0_clk: usb3s0 { 1741 compatible = "fixed-clock"; 1742 #clock-cells = <0>; 1743 clock-frequency = <0>; 1744 }; 1745 1746 usb_extal_clk: usb_extal { 1747 compatible = "fixed-clock"; 1748 #clock-cells = <0>; 1749 clock-frequency = <0>; 1750 }; 1751}; 1752