1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the RZ/G2E (R8A774C0) SoC 4 * 5 * Copyright (C) 2018-2019 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/clock/r8a774c0-cpg-mssr.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/power/r8a774c0-sysc.h> 11 12/ { 13 compatible = "renesas,r8a774c0"; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 /* 18 * The external audio clocks are configured as 0 Hz fixed frequency 19 * clocks by default. 20 * Boards that provide audio clocks should override them. 21 */ 22 audio_clk_a: audio_clk_a { 23 compatible = "fixed-clock"; 24 #clock-cells = <0>; 25 clock-frequency = <0>; 26 }; 27 28 audio_clk_b: audio_clk_b { 29 compatible = "fixed-clock"; 30 #clock-cells = <0>; 31 clock-frequency = <0>; 32 }; 33 34 audio_clk_c: audio_clk_c { 35 compatible = "fixed-clock"; 36 #clock-cells = <0>; 37 clock-frequency = <0>; 38 }; 39 40 /* External CAN clock - to be overridden by boards that provide it */ 41 can_clk: can { 42 compatible = "fixed-clock"; 43 #clock-cells = <0>; 44 clock-frequency = <0>; 45 }; 46 47 cluster1_opp: opp_table10 { 48 compatible = "operating-points-v2"; 49 opp-shared; 50 opp-800000000 { 51 opp-hz = /bits/ 64 <800000000>; 52 opp-microvolt = <820000>; 53 clock-latency-ns = <300000>; 54 }; 55 opp-1000000000 { 56 opp-hz = /bits/ 64 <1000000000>; 57 opp-microvolt = <820000>; 58 clock-latency-ns = <300000>; 59 }; 60 opp-1200000000 { 61 opp-hz = /bits/ 64 <1200000000>; 62 opp-microvolt = <820000>; 63 clock-latency-ns = <300000>; 64 opp-suspend; 65 }; 66 }; 67 68 cpus { 69 #address-cells = <1>; 70 #size-cells = <0>; 71 72 a53_0: cpu@0 { 73 compatible = "arm,cortex-a53"; 74 reg = <0>; 75 device_type = "cpu"; 76 #cooling-cells = <2>; 77 power-domains = <&sysc R8A774C0_PD_CA53_CPU0>; 78 next-level-cache = <&L2_CA53>; 79 enable-method = "psci"; 80 clocks = <&cpg CPG_CORE R8A774C0_CLK_Z2>; 81 operating-points-v2 = <&cluster1_opp>; 82 }; 83 84 a53_1: cpu@1 { 85 compatible = "arm,cortex-a53"; 86 reg = <1>; 87 device_type = "cpu"; 88 power-domains = <&sysc R8A774C0_PD_CA53_CPU1>; 89 next-level-cache = <&L2_CA53>; 90 enable-method = "psci"; 91 clocks = <&cpg CPG_CORE R8A774C0_CLK_Z2>; 92 operating-points-v2 = <&cluster1_opp>; 93 }; 94 95 L2_CA53: cache-controller-0 { 96 compatible = "cache"; 97 power-domains = <&sysc R8A774C0_PD_CA53_SCU>; 98 cache-unified; 99 cache-level = <2>; 100 }; 101 }; 102 103 extal_clk: extal { 104 compatible = "fixed-clock"; 105 #clock-cells = <0>; 106 /* This value must be overridden by the board */ 107 clock-frequency = <0>; 108 }; 109 110 /* External PCIe clock - can be overridden by the board */ 111 pcie_bus_clk: pcie_bus { 112 compatible = "fixed-clock"; 113 #clock-cells = <0>; 114 clock-frequency = <0>; 115 }; 116 117 pmu_a53 { 118 compatible = "arm,cortex-a53-pmu"; 119 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 120 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 121 interrupt-affinity = <&a53_0>, <&a53_1>; 122 }; 123 124 psci { 125 compatible = "arm,psci-1.0", "arm,psci-0.2"; 126 method = "smc"; 127 }; 128 129 /* External SCIF clock - to be overridden by boards that provide it */ 130 scif_clk: scif { 131 compatible = "fixed-clock"; 132 #clock-cells = <0>; 133 clock-frequency = <0>; 134 }; 135 136 soc: soc { 137 compatible = "simple-bus"; 138 interrupt-parent = <&gic>; 139 #address-cells = <2>; 140 #size-cells = <2>; 141 ranges; 142 143 rwdt: watchdog@e6020000 { 144 compatible = "renesas,r8a774c0-wdt", 145 "renesas,rcar-gen3-wdt"; 146 reg = <0 0xe6020000 0 0x0c>; 147 clocks = <&cpg CPG_MOD 402>; 148 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 149 resets = <&cpg 402>; 150 status = "disabled"; 151 }; 152 153 gpio0: gpio@e6050000 { 154 compatible = "renesas,gpio-r8a774c0", 155 "renesas,rcar-gen3-gpio"; 156 reg = <0 0xe6050000 0 0x50>; 157 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 158 #gpio-cells = <2>; 159 gpio-controller; 160 gpio-ranges = <&pfc 0 0 18>; 161 #interrupt-cells = <2>; 162 interrupt-controller; 163 clocks = <&cpg CPG_MOD 912>; 164 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 165 resets = <&cpg 912>; 166 }; 167 168 gpio1: gpio@e6051000 { 169 compatible = "renesas,gpio-r8a774c0", 170 "renesas,rcar-gen3-gpio"; 171 reg = <0 0xe6051000 0 0x50>; 172 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 173 #gpio-cells = <2>; 174 gpio-controller; 175 gpio-ranges = <&pfc 0 32 23>; 176 #interrupt-cells = <2>; 177 interrupt-controller; 178 clocks = <&cpg CPG_MOD 911>; 179 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 180 resets = <&cpg 911>; 181 }; 182 183 gpio2: gpio@e6052000 { 184 compatible = "renesas,gpio-r8a774c0", 185 "renesas,rcar-gen3-gpio"; 186 reg = <0 0xe6052000 0 0x50>; 187 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 188 #gpio-cells = <2>; 189 gpio-controller; 190 gpio-ranges = <&pfc 0 64 26>; 191 #interrupt-cells = <2>; 192 interrupt-controller; 193 clocks = <&cpg CPG_MOD 910>; 194 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 195 resets = <&cpg 910>; 196 }; 197 198 gpio3: gpio@e6053000 { 199 compatible = "renesas,gpio-r8a774c0", 200 "renesas,rcar-gen3-gpio"; 201 reg = <0 0xe6053000 0 0x50>; 202 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 203 #gpio-cells = <2>; 204 gpio-controller; 205 gpio-ranges = <&pfc 0 96 16>; 206 #interrupt-cells = <2>; 207 interrupt-controller; 208 clocks = <&cpg CPG_MOD 909>; 209 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 210 resets = <&cpg 909>; 211 }; 212 213 gpio4: gpio@e6054000 { 214 compatible = "renesas,gpio-r8a774c0", 215 "renesas,rcar-gen3-gpio"; 216 reg = <0 0xe6054000 0 0x50>; 217 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 218 #gpio-cells = <2>; 219 gpio-controller; 220 gpio-ranges = <&pfc 0 128 11>; 221 #interrupt-cells = <2>; 222 interrupt-controller; 223 clocks = <&cpg CPG_MOD 908>; 224 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 225 resets = <&cpg 908>; 226 }; 227 228 gpio5: gpio@e6055000 { 229 compatible = "renesas,gpio-r8a774c0", 230 "renesas,rcar-gen3-gpio"; 231 reg = <0 0xe6055000 0 0x50>; 232 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 233 #gpio-cells = <2>; 234 gpio-controller; 235 gpio-ranges = <&pfc 0 160 20>; 236 #interrupt-cells = <2>; 237 interrupt-controller; 238 clocks = <&cpg CPG_MOD 907>; 239 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 240 resets = <&cpg 907>; 241 }; 242 243 gpio6: gpio@e6055400 { 244 compatible = "renesas,gpio-r8a774c0", 245 "renesas,rcar-gen3-gpio"; 246 reg = <0 0xe6055400 0 0x50>; 247 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 248 #gpio-cells = <2>; 249 gpio-controller; 250 gpio-ranges = <&pfc 0 192 18>; 251 #interrupt-cells = <2>; 252 interrupt-controller; 253 clocks = <&cpg CPG_MOD 906>; 254 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 255 resets = <&cpg 906>; 256 }; 257 258 pfc: pin-controller@e6060000 { 259 compatible = "renesas,pfc-r8a774c0"; 260 reg = <0 0xe6060000 0 0x508>; 261 }; 262 263 cmt0: timer@e60f0000 { 264 compatible = "renesas,r8a774c0-cmt0", 265 "renesas,rcar-gen3-cmt0"; 266 reg = <0 0xe60f0000 0 0x1004>; 267 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 268 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 269 clocks = <&cpg CPG_MOD 303>; 270 clock-names = "fck"; 271 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 272 resets = <&cpg 303>; 273 status = "disabled"; 274 }; 275 276 cmt1: timer@e6130000 { 277 compatible = "renesas,r8a774c0-cmt1", 278 "renesas,rcar-gen3-cmt1"; 279 reg = <0 0xe6130000 0 0x1004>; 280 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 281 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 282 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 283 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 284 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 285 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 286 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 287 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 288 clocks = <&cpg CPG_MOD 302>; 289 clock-names = "fck"; 290 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 291 resets = <&cpg 302>; 292 status = "disabled"; 293 }; 294 295 cmt2: timer@e6140000 { 296 compatible = "renesas,r8a774c0-cmt1", 297 "renesas,rcar-gen3-cmt1"; 298 reg = <0 0xe6140000 0 0x1004>; 299 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 300 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 301 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 302 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 303 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 304 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 305 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 306 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; 307 clocks = <&cpg CPG_MOD 301>; 308 clock-names = "fck"; 309 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 310 resets = <&cpg 301>; 311 status = "disabled"; 312 }; 313 314 cmt3: timer@e6148000 { 315 compatible = "renesas,r8a774c0-cmt1", 316 "renesas,rcar-gen3-cmt1"; 317 reg = <0 0xe6148000 0 0x1004>; 318 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, 319 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, 320 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, 321 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, 322 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, 323 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>, 324 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, 325 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>; 326 clocks = <&cpg CPG_MOD 300>; 327 clock-names = "fck"; 328 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 329 resets = <&cpg 300>; 330 status = "disabled"; 331 }; 332 333 cpg: clock-controller@e6150000 { 334 compatible = "renesas,r8a774c0-cpg-mssr"; 335 reg = <0 0xe6150000 0 0x1000>; 336 clocks = <&extal_clk>; 337 clock-names = "extal"; 338 #clock-cells = <2>; 339 #power-domain-cells = <0>; 340 #reset-cells = <1>; 341 }; 342 343 rst: reset-controller@e6160000 { 344 compatible = "renesas,r8a774c0-rst"; 345 reg = <0 0xe6160000 0 0x0200>; 346 }; 347 348 sysc: system-controller@e6180000 { 349 compatible = "renesas,r8a774c0-sysc"; 350 reg = <0 0xe6180000 0 0x0400>; 351 #power-domain-cells = <1>; 352 }; 353 354 thermal: thermal@e6190000 { 355 compatible = "renesas,thermal-r8a774c0"; 356 reg = <0 0xe6190000 0 0x10>, <0 0xe6190100 0 0x38>; 357 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 358 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 359 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 360 clocks = <&cpg CPG_MOD 522>; 361 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 362 resets = <&cpg 522>; 363 #thermal-sensor-cells = <0>; 364 }; 365 366 intc_ex: interrupt-controller@e61c0000 { 367 compatible = "renesas,intc-ex-r8a774c0", "renesas,irqc"; 368 #interrupt-cells = <2>; 369 interrupt-controller; 370 reg = <0 0xe61c0000 0 0x200>; 371 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH 372 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 373 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH 374 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH 375 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 376 GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 377 clocks = <&cpg CPG_MOD 407>; 378 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 379 resets = <&cpg 407>; 380 }; 381 382 tmu0: timer@e61e0000 { 383 compatible = "renesas,tmu-r8a774c0", "renesas,tmu"; 384 reg = <0 0xe61e0000 0 0x30>; 385 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 386 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 387 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 388 clocks = <&cpg CPG_MOD 125>; 389 clock-names = "fck"; 390 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 391 resets = <&cpg 125>; 392 status = "disabled"; 393 }; 394 395 tmu1: timer@e6fc0000 { 396 compatible = "renesas,tmu-r8a774c0", "renesas,tmu"; 397 reg = <0 0xe6fc0000 0 0x30>; 398 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 399 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 400 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 401 clocks = <&cpg CPG_MOD 124>; 402 clock-names = "fck"; 403 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 404 resets = <&cpg 124>; 405 status = "disabled"; 406 }; 407 408 tmu2: timer@e6fd0000 { 409 compatible = "renesas,tmu-r8a774c0", "renesas,tmu"; 410 reg = <0 0xe6fd0000 0 0x30>; 411 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 412 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 413 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 414 clocks = <&cpg CPG_MOD 123>; 415 clock-names = "fck"; 416 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 417 resets = <&cpg 123>; 418 status = "disabled"; 419 }; 420 421 tmu3: timer@e6fe0000 { 422 compatible = "renesas,tmu-r8a774c0", "renesas,tmu"; 423 reg = <0 0xe6fe0000 0 0x30>; 424 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 425 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 426 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 427 clocks = <&cpg CPG_MOD 122>; 428 clock-names = "fck"; 429 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 430 resets = <&cpg 122>; 431 status = "disabled"; 432 }; 433 434 tmu4: timer@ffc00000 { 435 compatible = "renesas,tmu-r8a774c0", "renesas,tmu"; 436 reg = <0 0xffc00000 0 0x30>; 437 interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 438 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 439 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 440 clocks = <&cpg CPG_MOD 121>; 441 clock-names = "fck"; 442 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 443 resets = <&cpg 121>; 444 status = "disabled"; 445 }; 446 447 i2c0: i2c@e6500000 { 448 #address-cells = <1>; 449 #size-cells = <0>; 450 compatible = "renesas,i2c-r8a774c0", 451 "renesas,rcar-gen3-i2c"; 452 reg = <0 0xe6500000 0 0x40>; 453 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 454 clocks = <&cpg CPG_MOD 931>; 455 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 456 resets = <&cpg 931>; 457 dmas = <&dmac1 0x91>, <&dmac1 0x90>, 458 <&dmac2 0x91>, <&dmac2 0x90>; 459 dma-names = "tx", "rx", "tx", "rx"; 460 i2c-scl-internal-delay-ns = <110>; 461 status = "disabled"; 462 }; 463 464 i2c1: i2c@e6508000 { 465 #address-cells = <1>; 466 #size-cells = <0>; 467 compatible = "renesas,i2c-r8a774c0", 468 "renesas,rcar-gen3-i2c"; 469 reg = <0 0xe6508000 0 0x40>; 470 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 471 clocks = <&cpg CPG_MOD 930>; 472 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 473 resets = <&cpg 930>; 474 dmas = <&dmac1 0x93>, <&dmac1 0x92>, 475 <&dmac2 0x93>, <&dmac2 0x92>; 476 dma-names = "tx", "rx", "tx", "rx"; 477 i2c-scl-internal-delay-ns = <6>; 478 status = "disabled"; 479 }; 480 481 i2c2: i2c@e6510000 { 482 #address-cells = <1>; 483 #size-cells = <0>; 484 compatible = "renesas,i2c-r8a774c0", 485 "renesas,rcar-gen3-i2c"; 486 reg = <0 0xe6510000 0 0x40>; 487 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 488 clocks = <&cpg CPG_MOD 929>; 489 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 490 resets = <&cpg 929>; 491 dmas = <&dmac1 0x95>, <&dmac1 0x94>, 492 <&dmac2 0x95>, <&dmac2 0x94>; 493 dma-names = "tx", "rx", "tx", "rx"; 494 i2c-scl-internal-delay-ns = <6>; 495 status = "disabled"; 496 }; 497 498 i2c3: i2c@e66d0000 { 499 #address-cells = <1>; 500 #size-cells = <0>; 501 compatible = "renesas,i2c-r8a774c0", 502 "renesas,rcar-gen3-i2c"; 503 reg = <0 0xe66d0000 0 0x40>; 504 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 505 clocks = <&cpg CPG_MOD 928>; 506 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 507 resets = <&cpg 928>; 508 dmas = <&dmac0 0x97>, <&dmac0 0x96>; 509 dma-names = "tx", "rx"; 510 i2c-scl-internal-delay-ns = <110>; 511 status = "disabled"; 512 }; 513 514 i2c4: i2c@e66d8000 { 515 #address-cells = <1>; 516 #size-cells = <0>; 517 compatible = "renesas,i2c-r8a774c0", 518 "renesas,rcar-gen3-i2c"; 519 reg = <0 0xe66d8000 0 0x40>; 520 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 521 clocks = <&cpg CPG_MOD 927>; 522 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 523 resets = <&cpg 927>; 524 dmas = <&dmac0 0x99>, <&dmac0 0x98>; 525 dma-names = "tx", "rx"; 526 i2c-scl-internal-delay-ns = <6>; 527 status = "disabled"; 528 }; 529 530 i2c5: i2c@e66e0000 { 531 #address-cells = <1>; 532 #size-cells = <0>; 533 compatible = "renesas,i2c-r8a774c0", 534 "renesas,rcar-gen3-i2c"; 535 reg = <0 0xe66e0000 0 0x40>; 536 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 537 clocks = <&cpg CPG_MOD 919>; 538 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 539 resets = <&cpg 919>; 540 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; 541 dma-names = "tx", "rx"; 542 i2c-scl-internal-delay-ns = <6>; 543 status = "disabled"; 544 }; 545 546 i2c6: i2c@e66e8000 { 547 #address-cells = <1>; 548 #size-cells = <0>; 549 compatible = "renesas,i2c-r8a774c0", 550 "renesas,rcar-gen3-i2c"; 551 reg = <0 0xe66e8000 0 0x40>; 552 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 553 clocks = <&cpg CPG_MOD 918>; 554 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 555 resets = <&cpg 918>; 556 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; 557 dma-names = "tx", "rx"; 558 i2c-scl-internal-delay-ns = <6>; 559 status = "disabled"; 560 }; 561 562 i2c7: i2c@e6690000 { 563 #address-cells = <1>; 564 #size-cells = <0>; 565 compatible = "renesas,i2c-r8a774c0", 566 "renesas,rcar-gen3-i2c"; 567 reg = <0 0xe6690000 0 0x40>; 568 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 569 clocks = <&cpg CPG_MOD 1003>; 570 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 571 resets = <&cpg 1003>; 572 i2c-scl-internal-delay-ns = <6>; 573 status = "disabled"; 574 }; 575 576 i2c_dvfs: i2c@e60b0000 { 577 #address-cells = <1>; 578 #size-cells = <0>; 579 compatible = "renesas,iic-r8a774c0"; 580 reg = <0 0xe60b0000 0 0x15>; 581 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 582 clocks = <&cpg CPG_MOD 926>; 583 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 584 resets = <&cpg 926>; 585 dmas = <&dmac0 0x11>, <&dmac0 0x10>; 586 dma-names = "tx", "rx"; 587 status = "disabled"; 588 }; 589 590 hscif0: serial@e6540000 { 591 compatible = "renesas,hscif-r8a774c0", 592 "renesas,rcar-gen3-hscif", 593 "renesas,hscif"; 594 reg = <0 0xe6540000 0 0x60>; 595 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 596 clocks = <&cpg CPG_MOD 520>, 597 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, 598 <&scif_clk>; 599 clock-names = "fck", "brg_int", "scif_clk"; 600 dmas = <&dmac1 0x31>, <&dmac1 0x30>, 601 <&dmac2 0x31>, <&dmac2 0x30>; 602 dma-names = "tx", "rx", "tx", "rx"; 603 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 604 resets = <&cpg 520>; 605 status = "disabled"; 606 }; 607 608 hscif1: serial@e6550000 { 609 compatible = "renesas,hscif-r8a774c0", 610 "renesas,rcar-gen3-hscif", 611 "renesas,hscif"; 612 reg = <0 0xe6550000 0 0x60>; 613 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 614 clocks = <&cpg CPG_MOD 519>, 615 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, 616 <&scif_clk>; 617 clock-names = "fck", "brg_int", "scif_clk"; 618 dmas = <&dmac1 0x33>, <&dmac1 0x32>, 619 <&dmac2 0x33>, <&dmac2 0x32>; 620 dma-names = "tx", "rx", "tx", "rx"; 621 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 622 resets = <&cpg 519>; 623 status = "disabled"; 624 }; 625 626 hscif2: serial@e6560000 { 627 compatible = "renesas,hscif-r8a774c0", 628 "renesas,rcar-gen3-hscif", 629 "renesas,hscif"; 630 reg = <0 0xe6560000 0 0x60>; 631 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 632 clocks = <&cpg CPG_MOD 518>, 633 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, 634 <&scif_clk>; 635 clock-names = "fck", "brg_int", "scif_clk"; 636 dmas = <&dmac1 0x35>, <&dmac1 0x34>, 637 <&dmac2 0x35>, <&dmac2 0x34>; 638 dma-names = "tx", "rx", "tx", "rx"; 639 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 640 resets = <&cpg 518>; 641 status = "disabled"; 642 }; 643 644 hscif3: serial@e66a0000 { 645 compatible = "renesas,hscif-r8a774c0", 646 "renesas,rcar-gen3-hscif", 647 "renesas,hscif"; 648 reg = <0 0xe66a0000 0 0x60>; 649 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 650 clocks = <&cpg CPG_MOD 517>, 651 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, 652 <&scif_clk>; 653 clock-names = "fck", "brg_int", "scif_clk"; 654 dmas = <&dmac0 0x37>, <&dmac0 0x36>; 655 dma-names = "tx", "rx"; 656 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 657 resets = <&cpg 517>; 658 status = "disabled"; 659 }; 660 661 hscif4: serial@e66b0000 { 662 compatible = "renesas,hscif-r8a774c0", 663 "renesas,rcar-gen3-hscif", 664 "renesas,hscif"; 665 reg = <0 0xe66b0000 0 0x60>; 666 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 667 clocks = <&cpg CPG_MOD 516>, 668 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, 669 <&scif_clk>; 670 clock-names = "fck", "brg_int", "scif_clk"; 671 dmas = <&dmac0 0x39>, <&dmac0 0x38>; 672 dma-names = "tx", "rx"; 673 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 674 resets = <&cpg 516>; 675 status = "disabled"; 676 }; 677 678 hsusb: usb@e6590000 { 679 compatible = "renesas,usbhs-r8a774c0", 680 "renesas,rcar-gen3-usbhs"; 681 reg = <0 0xe6590000 0 0x200>; 682 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 683 clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; 684 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, 685 <&usb_dmac1 0>, <&usb_dmac1 1>; 686 dma-names = "ch0", "ch1", "ch2", "ch3"; 687 renesas,buswait = <11>; 688 phys = <&usb2_phy0 3>; 689 phy-names = "usb"; 690 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 691 resets = <&cpg 704>, <&cpg 703>; 692 status = "disabled"; 693 }; 694 695 usb_dmac0: dma-controller@e65a0000 { 696 compatible = "renesas,r8a774c0-usb-dmac", 697 "renesas,usb-dmac"; 698 reg = <0 0xe65a0000 0 0x100>; 699 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 700 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 701 interrupt-names = "ch0", "ch1"; 702 clocks = <&cpg CPG_MOD 330>; 703 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 704 resets = <&cpg 330>; 705 #dma-cells = <1>; 706 dma-channels = <2>; 707 }; 708 709 usb_dmac1: dma-controller@e65b0000 { 710 compatible = "renesas,r8a774c0-usb-dmac", 711 "renesas,usb-dmac"; 712 reg = <0 0xe65b0000 0 0x100>; 713 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 714 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 715 interrupt-names = "ch0", "ch1"; 716 clocks = <&cpg CPG_MOD 331>; 717 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 718 resets = <&cpg 331>; 719 #dma-cells = <1>; 720 dma-channels = <2>; 721 }; 722 723 dmac0: dma-controller@e6700000 { 724 compatible = "renesas,dmac-r8a774c0", 725 "renesas,rcar-dmac"; 726 reg = <0 0xe6700000 0 0x10000>; 727 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH 728 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH 729 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH 730 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 731 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 732 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 733 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 734 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 735 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH 736 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH 737 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH 738 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH 739 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH 740 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 741 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH 742 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH 743 GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 744 interrupt-names = "error", 745 "ch0", "ch1", "ch2", "ch3", 746 "ch4", "ch5", "ch6", "ch7", 747 "ch8", "ch9", "ch10", "ch11", 748 "ch12", "ch13", "ch14", "ch15"; 749 clocks = <&cpg CPG_MOD 219>; 750 clock-names = "fck"; 751 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 752 resets = <&cpg 219>; 753 #dma-cells = <1>; 754 dma-channels = <16>; 755 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, 756 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, 757 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, 758 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, 759 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, 760 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, 761 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, 762 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; 763 }; 764 765 dmac1: dma-controller@e7300000 { 766 compatible = "renesas,dmac-r8a774c0", 767 "renesas,rcar-dmac"; 768 reg = <0 0xe7300000 0 0x10000>; 769 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 770 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 771 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH 772 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 773 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 774 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH 775 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 776 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH 777 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH 778 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH 779 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 780 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH 781 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 782 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH 783 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 784 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 785 GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; 786 interrupt-names = "error", 787 "ch0", "ch1", "ch2", "ch3", 788 "ch4", "ch5", "ch6", "ch7", 789 "ch8", "ch9", "ch10", "ch11", 790 "ch12", "ch13", "ch14", "ch15"; 791 clocks = <&cpg CPG_MOD 218>; 792 clock-names = "fck"; 793 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 794 resets = <&cpg 218>; 795 #dma-cells = <1>; 796 dma-channels = <16>; 797 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, 798 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, 799 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, 800 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, 801 <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, 802 <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, 803 <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, 804 <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; 805 }; 806 807 dmac2: dma-controller@e7310000 { 808 compatible = "renesas,dmac-r8a774c0", 809 "renesas,rcar-dmac"; 810 reg = <0 0xe7310000 0 0x10000>; 811 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH 812 GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH 813 GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH 814 GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH 815 GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH 816 GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH 817 GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH 818 GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH 819 GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH 820 GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 821 GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 822 GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH 823 GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH 824 GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH 825 GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH 826 GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH 827 GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; 828 interrupt-names = "error", 829 "ch0", "ch1", "ch2", "ch3", 830 "ch4", "ch5", "ch6", "ch7", 831 "ch8", "ch9", "ch10", "ch11", 832 "ch12", "ch13", "ch14", "ch15"; 833 clocks = <&cpg CPG_MOD 217>; 834 clock-names = "fck"; 835 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 836 resets = <&cpg 217>; 837 #dma-cells = <1>; 838 dma-channels = <16>; 839 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, 840 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, 841 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, 842 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, 843 <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, 844 <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, 845 <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, 846 <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; 847 }; 848 849 ipmmu_ds0: mmu@e6740000 { 850 compatible = "renesas,ipmmu-r8a774c0"; 851 reg = <0 0xe6740000 0 0x1000>; 852 renesas,ipmmu-main = <&ipmmu_mm 0>; 853 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 854 #iommu-cells = <1>; 855 }; 856 857 ipmmu_ds1: mmu@e7740000 { 858 compatible = "renesas,ipmmu-r8a774c0"; 859 reg = <0 0xe7740000 0 0x1000>; 860 renesas,ipmmu-main = <&ipmmu_mm 1>; 861 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 862 #iommu-cells = <1>; 863 }; 864 865 ipmmu_hc: mmu@e6570000 { 866 compatible = "renesas,ipmmu-r8a774c0"; 867 reg = <0 0xe6570000 0 0x1000>; 868 renesas,ipmmu-main = <&ipmmu_mm 2>; 869 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 870 #iommu-cells = <1>; 871 }; 872 873 ipmmu_mm: mmu@e67b0000 { 874 compatible = "renesas,ipmmu-r8a774c0"; 875 reg = <0 0xe67b0000 0 0x1000>; 876 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 877 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 878 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 879 #iommu-cells = <1>; 880 }; 881 882 ipmmu_mp: mmu@ec670000 { 883 compatible = "renesas,ipmmu-r8a774c0"; 884 reg = <0 0xec670000 0 0x1000>; 885 renesas,ipmmu-main = <&ipmmu_mm 4>; 886 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 887 #iommu-cells = <1>; 888 }; 889 890 ipmmu_pv0: mmu@fd800000 { 891 compatible = "renesas,ipmmu-r8a774c0"; 892 reg = <0 0xfd800000 0 0x1000>; 893 renesas,ipmmu-main = <&ipmmu_mm 6>; 894 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 895 #iommu-cells = <1>; 896 }; 897 898 ipmmu_vc0: mmu@fe6b0000 { 899 compatible = "renesas,ipmmu-r8a774c0"; 900 reg = <0 0xfe6b0000 0 0x1000>; 901 renesas,ipmmu-main = <&ipmmu_mm 12>; 902 power-domains = <&sysc R8A774C0_PD_A3VC>; 903 #iommu-cells = <1>; 904 }; 905 906 ipmmu_vi0: mmu@febd0000 { 907 compatible = "renesas,ipmmu-r8a774c0"; 908 reg = <0 0xfebd0000 0 0x1000>; 909 renesas,ipmmu-main = <&ipmmu_mm 14>; 910 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 911 #iommu-cells = <1>; 912 }; 913 914 ipmmu_vp0: mmu@fe990000 { 915 compatible = "renesas,ipmmu-r8a774c0"; 916 reg = <0 0xfe990000 0 0x1000>; 917 renesas,ipmmu-main = <&ipmmu_mm 16>; 918 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 919 #iommu-cells = <1>; 920 }; 921 922 avb: ethernet@e6800000 { 923 compatible = "renesas,etheravb-r8a774c0", 924 "renesas,etheravb-rcar-gen3"; 925 reg = <0 0xe6800000 0 0x800>; 926 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 927 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 928 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 929 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 930 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 931 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 932 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 933 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 934 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 935 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 936 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 937 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 938 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 939 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 940 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 941 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 942 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 943 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 944 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 945 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 946 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 947 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 948 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 949 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 950 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 951 interrupt-names = "ch0", "ch1", "ch2", "ch3", 952 "ch4", "ch5", "ch6", "ch7", 953 "ch8", "ch9", "ch10", "ch11", 954 "ch12", "ch13", "ch14", "ch15", 955 "ch16", "ch17", "ch18", "ch19", 956 "ch20", "ch21", "ch22", "ch23", 957 "ch24"; 958 clocks = <&cpg CPG_MOD 812>; 959 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 960 resets = <&cpg 812>; 961 phy-mode = "rgmii"; 962 iommus = <&ipmmu_ds0 16>; 963 #address-cells = <1>; 964 #size-cells = <0>; 965 status = "disabled"; 966 }; 967 968 can0: can@e6c30000 { 969 compatible = "renesas,can-r8a774c0", 970 "renesas,rcar-gen3-can"; 971 reg = <0 0xe6c30000 0 0x1000>; 972 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 973 clocks = <&cpg CPG_MOD 916>, 974 <&cpg CPG_CORE R8A774C0_CLK_CANFD>, 975 <&can_clk>; 976 clock-names = "clkp1", "clkp2", "can_clk"; 977 assigned-clocks = <&cpg CPG_CORE R8A774C0_CLK_CANFD>; 978 assigned-clock-rates = <40000000>; 979 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 980 resets = <&cpg 916>; 981 status = "disabled"; 982 }; 983 984 can1: can@e6c38000 { 985 compatible = "renesas,can-r8a774c0", 986 "renesas,rcar-gen3-can"; 987 reg = <0 0xe6c38000 0 0x1000>; 988 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 989 clocks = <&cpg CPG_MOD 915>, 990 <&cpg CPG_CORE R8A774C0_CLK_CANFD>, 991 <&can_clk>; 992 clock-names = "clkp1", "clkp2", "can_clk"; 993 assigned-clocks = <&cpg CPG_CORE R8A774C0_CLK_CANFD>; 994 assigned-clock-rates = <40000000>; 995 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 996 resets = <&cpg 915>; 997 status = "disabled"; 998 }; 999 1000 canfd: can@e66c0000 { 1001 compatible = "renesas,r8a774c0-canfd", 1002 "renesas,rcar-gen3-canfd"; 1003 reg = <0 0xe66c0000 0 0x8000>; 1004 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 1005 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 1006 clocks = <&cpg CPG_MOD 914>, 1007 <&cpg CPG_CORE R8A774C0_CLK_CANFD>, 1008 <&can_clk>; 1009 clock-names = "fck", "canfd", "can_clk"; 1010 assigned-clocks = <&cpg CPG_CORE R8A774C0_CLK_CANFD>; 1011 assigned-clock-rates = <40000000>; 1012 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1013 resets = <&cpg 914>; 1014 status = "disabled"; 1015 1016 channel0 { 1017 status = "disabled"; 1018 }; 1019 1020 channel1 { 1021 status = "disabled"; 1022 }; 1023 }; 1024 1025 pwm0: pwm@e6e30000 { 1026 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; 1027 reg = <0 0xe6e30000 0 0x8>; 1028 clocks = <&cpg CPG_MOD 523>; 1029 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1030 resets = <&cpg 523>; 1031 #pwm-cells = <2>; 1032 status = "disabled"; 1033 }; 1034 1035 pwm1: pwm@e6e31000 { 1036 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; 1037 reg = <0 0xe6e31000 0 0x8>; 1038 clocks = <&cpg CPG_MOD 523>; 1039 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1040 resets = <&cpg 523>; 1041 #pwm-cells = <2>; 1042 status = "disabled"; 1043 }; 1044 1045 pwm2: pwm@e6e32000 { 1046 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; 1047 reg = <0 0xe6e32000 0 0x8>; 1048 clocks = <&cpg CPG_MOD 523>; 1049 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1050 resets = <&cpg 523>; 1051 #pwm-cells = <2>; 1052 status = "disabled"; 1053 }; 1054 1055 pwm3: pwm@e6e33000 { 1056 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; 1057 reg = <0 0xe6e33000 0 0x8>; 1058 clocks = <&cpg CPG_MOD 523>; 1059 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1060 resets = <&cpg 523>; 1061 #pwm-cells = <2>; 1062 status = "disabled"; 1063 }; 1064 1065 pwm4: pwm@e6e34000 { 1066 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; 1067 reg = <0 0xe6e34000 0 0x8>; 1068 clocks = <&cpg CPG_MOD 523>; 1069 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1070 resets = <&cpg 523>; 1071 #pwm-cells = <2>; 1072 status = "disabled"; 1073 }; 1074 1075 pwm5: pwm@e6e35000 { 1076 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; 1077 reg = <0 0xe6e35000 0 0x8>; 1078 clocks = <&cpg CPG_MOD 523>; 1079 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1080 resets = <&cpg 523>; 1081 #pwm-cells = <2>; 1082 status = "disabled"; 1083 }; 1084 1085 pwm6: pwm@e6e36000 { 1086 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; 1087 reg = <0 0xe6e36000 0 0x8>; 1088 clocks = <&cpg CPG_MOD 523>; 1089 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1090 resets = <&cpg 523>; 1091 #pwm-cells = <2>; 1092 status = "disabled"; 1093 }; 1094 1095 scif0: serial@e6e60000 { 1096 compatible = "renesas,scif-r8a774c0", 1097 "renesas,rcar-gen3-scif", "renesas,scif"; 1098 reg = <0 0xe6e60000 0 64>; 1099 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 1100 clocks = <&cpg CPG_MOD 207>, 1101 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, 1102 <&scif_clk>; 1103 clock-names = "fck", "brg_int", "scif_clk"; 1104 dmas = <&dmac1 0x51>, <&dmac1 0x50>, 1105 <&dmac2 0x51>, <&dmac2 0x50>; 1106 dma-names = "tx", "rx", "tx", "rx"; 1107 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1108 resets = <&cpg 207>; 1109 status = "disabled"; 1110 }; 1111 1112 scif1: serial@e6e68000 { 1113 compatible = "renesas,scif-r8a774c0", 1114 "renesas,rcar-gen3-scif", "renesas,scif"; 1115 reg = <0 0xe6e68000 0 64>; 1116 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1117 clocks = <&cpg CPG_MOD 206>, 1118 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, 1119 <&scif_clk>; 1120 clock-names = "fck", "brg_int", "scif_clk"; 1121 dmas = <&dmac1 0x53>, <&dmac1 0x52>, 1122 <&dmac2 0x53>, <&dmac2 0x52>; 1123 dma-names = "tx", "rx", "tx", "rx"; 1124 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1125 resets = <&cpg 206>; 1126 status = "disabled"; 1127 }; 1128 1129 scif2: serial@e6e88000 { 1130 compatible = "renesas,scif-r8a774c0", 1131 "renesas,rcar-gen3-scif", "renesas,scif"; 1132 reg = <0 0xe6e88000 0 64>; 1133 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1134 clocks = <&cpg CPG_MOD 310>, 1135 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, 1136 <&scif_clk>; 1137 clock-names = "fck", "brg_int", "scif_clk"; 1138 dmas = <&dmac1 0x13>, <&dmac1 0x12>, 1139 <&dmac2 0x13>, <&dmac2 0x12>; 1140 dma-names = "tx", "rx", "tx", "rx"; 1141 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1142 resets = <&cpg 310>; 1143 status = "disabled"; 1144 }; 1145 1146 scif3: serial@e6c50000 { 1147 compatible = "renesas,scif-r8a774c0", 1148 "renesas,rcar-gen3-scif", "renesas,scif"; 1149 reg = <0 0xe6c50000 0 64>; 1150 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1151 clocks = <&cpg CPG_MOD 204>, 1152 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, 1153 <&scif_clk>; 1154 clock-names = "fck", "brg_int", "scif_clk"; 1155 dmas = <&dmac0 0x57>, <&dmac0 0x56>; 1156 dma-names = "tx", "rx"; 1157 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1158 resets = <&cpg 204>; 1159 status = "disabled"; 1160 }; 1161 1162 scif4: serial@e6c40000 { 1163 compatible = "renesas,scif-r8a774c0", 1164 "renesas,rcar-gen3-scif", "renesas,scif"; 1165 reg = <0 0xe6c40000 0 64>; 1166 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1167 clocks = <&cpg CPG_MOD 203>, 1168 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, 1169 <&scif_clk>; 1170 clock-names = "fck", "brg_int", "scif_clk"; 1171 dmas = <&dmac0 0x59>, <&dmac0 0x58>; 1172 dma-names = "tx", "rx"; 1173 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1174 resets = <&cpg 203>; 1175 status = "disabled"; 1176 }; 1177 1178 scif5: serial@e6f30000 { 1179 compatible = "renesas,scif-r8a774c0", 1180 "renesas,rcar-gen3-scif", "renesas,scif"; 1181 reg = <0 0xe6f30000 0 64>; 1182 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1183 clocks = <&cpg CPG_MOD 202>, 1184 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, 1185 <&scif_clk>; 1186 clock-names = "fck", "brg_int", "scif_clk"; 1187 dmas = <&dmac0 0x5b>, <&dmac0 0x5a>; 1188 dma-names = "tx", "rx"; 1189 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1190 resets = <&cpg 202>; 1191 status = "disabled"; 1192 }; 1193 1194 msiof0: spi@e6e90000 { 1195 compatible = "renesas,msiof-r8a774c0", 1196 "renesas,rcar-gen3-msiof"; 1197 reg = <0 0xe6e90000 0 0x0064>; 1198 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 1199 clocks = <&cpg CPG_MOD 211>; 1200 dmas = <&dmac1 0x41>, <&dmac1 0x40>, 1201 <&dmac2 0x41>, <&dmac2 0x40>; 1202 dma-names = "tx", "rx", "tx", "rx"; 1203 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1204 resets = <&cpg 211>; 1205 #address-cells = <1>; 1206 #size-cells = <0>; 1207 status = "disabled"; 1208 }; 1209 1210 msiof1: spi@e6ea0000 { 1211 compatible = "renesas,msiof-r8a774c0", 1212 "renesas,rcar-gen3-msiof"; 1213 reg = <0 0xe6ea0000 0 0x0064>; 1214 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1215 clocks = <&cpg CPG_MOD 210>; 1216 dmas = <&dmac1 0x43>, <&dmac1 0x42>, 1217 <&dmac2 0x43>, <&dmac2 0x42>; 1218 dma-names = "tx", "rx", "tx", "rx"; 1219 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1220 resets = <&cpg 210>; 1221 #address-cells = <1>; 1222 #size-cells = <0>; 1223 status = "disabled"; 1224 }; 1225 1226 msiof2: spi@e6c00000 { 1227 compatible = "renesas,msiof-r8a774c0", 1228 "renesas,rcar-gen3-msiof"; 1229 reg = <0 0xe6c00000 0 0x0064>; 1230 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1231 clocks = <&cpg CPG_MOD 209>; 1232 dmas = <&dmac0 0x45>, <&dmac0 0x44>; 1233 dma-names = "tx", "rx"; 1234 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1235 resets = <&cpg 209>; 1236 #address-cells = <1>; 1237 #size-cells = <0>; 1238 status = "disabled"; 1239 }; 1240 1241 msiof3: spi@e6c10000 { 1242 compatible = "renesas,msiof-r8a774c0", 1243 "renesas,rcar-gen3-msiof"; 1244 reg = <0 0xe6c10000 0 0x0064>; 1245 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1246 clocks = <&cpg CPG_MOD 208>; 1247 dmas = <&dmac0 0x47>, <&dmac0 0x46>; 1248 dma-names = "tx", "rx"; 1249 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1250 resets = <&cpg 208>; 1251 #address-cells = <1>; 1252 #size-cells = <0>; 1253 status = "disabled"; 1254 }; 1255 1256 vin4: video@e6ef4000 { 1257 compatible = "renesas,vin-r8a774c0"; 1258 reg = <0 0xe6ef4000 0 0x1000>; 1259 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1260 clocks = <&cpg CPG_MOD 807>; 1261 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1262 resets = <&cpg 807>; 1263 renesas,id = <4>; 1264 status = "disabled"; 1265 1266 ports { 1267 #address-cells = <1>; 1268 #size-cells = <0>; 1269 1270 port@1 { 1271 #address-cells = <1>; 1272 #size-cells = <0>; 1273 1274 reg = <1>; 1275 1276 vin4csi40: endpoint@2 { 1277 reg = <2>; 1278 remote-endpoint= <&csi40vin4>; 1279 }; 1280 }; 1281 }; 1282 }; 1283 1284 vin5: video@e6ef5000 { 1285 compatible = "renesas,vin-r8a774c0"; 1286 reg = <0 0xe6ef5000 0 0x1000>; 1287 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 1288 clocks = <&cpg CPG_MOD 806>; 1289 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1290 resets = <&cpg 806>; 1291 renesas,id = <5>; 1292 status = "disabled"; 1293 1294 ports { 1295 #address-cells = <1>; 1296 #size-cells = <0>; 1297 1298 port@1 { 1299 #address-cells = <1>; 1300 #size-cells = <0>; 1301 1302 reg = <1>; 1303 1304 vin5csi40: endpoint@2 { 1305 reg = <2>; 1306 remote-endpoint= <&csi40vin5>; 1307 }; 1308 }; 1309 }; 1310 }; 1311 1312 rcar_sound: sound@ec500000 { 1313 /* 1314 * #sound-dai-cells is required 1315 * 1316 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; 1317 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; 1318 */ 1319 /* 1320 * #clock-cells is required for audio_clkout0/1/2/3 1321 * 1322 * clkout : #clock-cells = <0>; <&rcar_sound>; 1323 * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; 1324 */ 1325 compatible = "renesas,rcar_sound-r8a774c0", 1326 "renesas,rcar_sound-gen3"; 1327 reg = <0 0xec500000 0 0x1000>, /* SCU */ 1328 <0 0xec5a0000 0 0x100>, /* ADG */ 1329 <0 0xec540000 0 0x1000>, /* SSIU */ 1330 <0 0xec541000 0 0x280>, /* SSI */ 1331 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ 1332 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; 1333 1334 clocks = <&cpg CPG_MOD 1005>, 1335 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, 1336 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, 1337 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, 1338 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, 1339 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, 1340 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, 1341 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, 1342 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, 1343 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, 1344 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, 1345 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 1346 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 1347 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, 1348 <&audio_clk_a>, <&audio_clk_b>, 1349 <&audio_clk_c>, 1350 <&cpg CPG_CORE R8A774C0_CLK_ZA2>; 1351 clock-names = "ssi-all", 1352 "ssi.9", "ssi.8", "ssi.7", "ssi.6", 1353 "ssi.5", "ssi.4", "ssi.3", "ssi.2", 1354 "ssi.1", "ssi.0", 1355 "src.9", "src.8", "src.7", "src.6", 1356 "src.5", "src.4", "src.3", "src.2", 1357 "src.1", "src.0", 1358 "mix.1", "mix.0", 1359 "ctu.1", "ctu.0", 1360 "dvc.0", "dvc.1", 1361 "clk_a", "clk_b", "clk_c", "clk_i"; 1362 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1363 resets = <&cpg 1005>, 1364 <&cpg 1006>, <&cpg 1007>, 1365 <&cpg 1008>, <&cpg 1009>, 1366 <&cpg 1010>, <&cpg 1011>, 1367 <&cpg 1012>, <&cpg 1013>, 1368 <&cpg 1014>, <&cpg 1015>; 1369 reset-names = "ssi-all", 1370 "ssi.9", "ssi.8", "ssi.7", "ssi.6", 1371 "ssi.5", "ssi.4", "ssi.3", "ssi.2", 1372 "ssi.1", "ssi.0"; 1373 status = "disabled"; 1374 1375 rcar_sound,ctu { 1376 ctu00: ctu-0 { }; 1377 ctu01: ctu-1 { }; 1378 ctu02: ctu-2 { }; 1379 ctu03: ctu-3 { }; 1380 ctu10: ctu-4 { }; 1381 ctu11: ctu-5 { }; 1382 ctu12: ctu-6 { }; 1383 ctu13: ctu-7 { }; 1384 }; 1385 1386 rcar_sound,dvc { 1387 dvc0: dvc-0 { 1388 dmas = <&audma0 0xbc>; 1389 dma-names = "tx"; 1390 }; 1391 dvc1: dvc-1 { 1392 dmas = <&audma0 0xbe>; 1393 dma-names = "tx"; 1394 }; 1395 }; 1396 1397 rcar_sound,mix { 1398 mix0: mix-0 { }; 1399 mix1: mix-1 { }; 1400 }; 1401 1402 rcar_sound,src { 1403 src0: src-0 { 1404 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 1405 dmas = <&audma0 0x85>, <&audma0 0x9a>; 1406 dma-names = "rx", "tx"; 1407 }; 1408 src1: src-1 { 1409 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1410 dmas = <&audma0 0x87>, <&audma0 0x9c>; 1411 dma-names = "rx", "tx"; 1412 }; 1413 src2: src-2 { 1414 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1415 dmas = <&audma0 0x89>, <&audma0 0x9e>; 1416 dma-names = "rx", "tx"; 1417 }; 1418 src3: src-3 { 1419 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1420 dmas = <&audma0 0x8b>, <&audma0 0xa0>; 1421 dma-names = "rx", "tx"; 1422 }; 1423 src4: src-4 { 1424 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1425 dmas = <&audma0 0x8d>, <&audma0 0xb0>; 1426 dma-names = "rx", "tx"; 1427 }; 1428 src5: src-5 { 1429 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1430 dmas = <&audma0 0x8f>, <&audma0 0xb2>; 1431 dma-names = "rx", "tx"; 1432 }; 1433 src6: src-6 { 1434 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1435 dmas = <&audma0 0x91>, <&audma0 0xb4>; 1436 dma-names = "rx", "tx"; 1437 }; 1438 src7: src-7 { 1439 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1440 dmas = <&audma0 0x93>, <&audma0 0xb6>; 1441 dma-names = "rx", "tx"; 1442 }; 1443 src8: src-8 { 1444 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1445 dmas = <&audma0 0x95>, <&audma0 0xb8>; 1446 dma-names = "rx", "tx"; 1447 }; 1448 src9: src-9 { 1449 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; 1450 dmas = <&audma0 0x97>, <&audma0 0xba>; 1451 dma-names = "rx", "tx"; 1452 }; 1453 }; 1454 1455 rcar_sound,ssi { 1456 ssi0: ssi-0 { 1457 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; 1458 dmas = <&audma0 0x01>, <&audma0 0x02>, 1459 <&audma0 0x15>, <&audma0 0x16>; 1460 dma-names = "rx", "tx", "rxu", "txu"; 1461 }; 1462 ssi1: ssi-1 { 1463 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; 1464 dmas = <&audma0 0x03>, <&audma0 0x04>, 1465 <&audma0 0x49>, <&audma0 0x4a>; 1466 dma-names = "rx", "tx", "rxu", "txu"; 1467 }; 1468 ssi2: ssi-2 { 1469 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; 1470 dmas = <&audma0 0x05>, <&audma0 0x06>, 1471 <&audma0 0x63>, <&audma0 0x64>; 1472 dma-names = "rx", "tx", "rxu", "txu"; 1473 }; 1474 ssi3: ssi-3 { 1475 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1476 dmas = <&audma0 0x07>, <&audma0 0x08>, 1477 <&audma0 0x6f>, <&audma0 0x70>; 1478 dma-names = "rx", "tx", "rxu", "txu"; 1479 }; 1480 ssi4: ssi-4 { 1481 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; 1482 dmas = <&audma0 0x09>, <&audma0 0x0a>, 1483 <&audma0 0x71>, <&audma0 0x72>; 1484 dma-names = "rx", "tx", "rxu", "txu"; 1485 }; 1486 ssi5: ssi-5 { 1487 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 1488 dmas = <&audma0 0x0b>, <&audma0 0x0c>, 1489 <&audma0 0x73>, <&audma0 0x74>; 1490 dma-names = "rx", "tx", "rxu", "txu"; 1491 }; 1492 ssi6: ssi-6 { 1493 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; 1494 dmas = <&audma0 0x0d>, <&audma0 0x0e>, 1495 <&audma0 0x75>, <&audma0 0x76>; 1496 dma-names = "rx", "tx", "rxu", "txu"; 1497 }; 1498 ssi7: ssi-7 { 1499 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; 1500 dmas = <&audma0 0x0f>, <&audma0 0x10>, 1501 <&audma0 0x79>, <&audma0 0x7a>; 1502 dma-names = "rx", "tx", "rxu", "txu"; 1503 }; 1504 ssi8: ssi-8 { 1505 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; 1506 dmas = <&audma0 0x11>, <&audma0 0x12>, 1507 <&audma0 0x7b>, <&audma0 0x7c>; 1508 dma-names = "rx", "tx", "rxu", "txu"; 1509 }; 1510 ssi9: ssi-9 { 1511 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; 1512 dmas = <&audma0 0x13>, <&audma0 0x14>, 1513 <&audma0 0x7d>, <&audma0 0x7e>; 1514 dma-names = "rx", "tx", "rxu", "txu"; 1515 }; 1516 }; 1517 }; 1518 1519 audma0: dma-controller@ec700000 { 1520 compatible = "renesas,dmac-r8a774c0", 1521 "renesas,rcar-dmac"; 1522 reg = <0 0xec700000 0 0x10000>; 1523 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH 1524 GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH 1525 GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH 1526 GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH 1527 GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH 1528 GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 1529 GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH 1530 GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH 1531 GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH 1532 GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH 1533 GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH 1534 GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH 1535 GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 1536 GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH 1537 GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH 1538 GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH 1539 GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 1540 interrupt-names = "error", 1541 "ch0", "ch1", "ch2", "ch3", 1542 "ch4", "ch5", "ch6", "ch7", 1543 "ch8", "ch9", "ch10", "ch11", 1544 "ch12", "ch13", "ch14", "ch15"; 1545 clocks = <&cpg CPG_MOD 502>; 1546 clock-names = "fck"; 1547 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1548 resets = <&cpg 502>; 1549 #dma-cells = <1>; 1550 dma-channels = <16>; 1551 iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>, 1552 <&ipmmu_mp 2>, <&ipmmu_mp 3>, 1553 <&ipmmu_mp 4>, <&ipmmu_mp 5>, 1554 <&ipmmu_mp 6>, <&ipmmu_mp 7>, 1555 <&ipmmu_mp 8>, <&ipmmu_mp 9>, 1556 <&ipmmu_mp 10>, <&ipmmu_mp 11>, 1557 <&ipmmu_mp 12>, <&ipmmu_mp 13>, 1558 <&ipmmu_mp 14>, <&ipmmu_mp 15>; 1559 }; 1560 1561 xhci0: usb@ee000000 { 1562 compatible = "renesas,xhci-r8a774c0", 1563 "renesas,rcar-gen3-xhci"; 1564 reg = <0 0xee000000 0 0xc00>; 1565 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 1566 clocks = <&cpg CPG_MOD 328>; 1567 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1568 resets = <&cpg 328>; 1569 status = "disabled"; 1570 }; 1571 1572 usb3_peri0: usb@ee020000 { 1573 compatible = "renesas,r8a774c0-usb3-peri", 1574 "renesas,rcar-gen3-usb3-peri"; 1575 reg = <0 0xee020000 0 0x400>; 1576 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 1577 clocks = <&cpg CPG_MOD 328>; 1578 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1579 resets = <&cpg 328>; 1580 status = "disabled"; 1581 }; 1582 1583 ohci0: usb@ee080000 { 1584 compatible = "generic-ohci"; 1585 reg = <0 0xee080000 0 0x100>; 1586 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1587 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 1588 phys = <&usb2_phy0 1>; 1589 phy-names = "usb"; 1590 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1591 resets = <&cpg 703>, <&cpg 704>; 1592 status = "disabled"; 1593 }; 1594 1595 ehci0: usb@ee080100 { 1596 compatible = "generic-ehci"; 1597 reg = <0 0xee080100 0 0x100>; 1598 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1599 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 1600 phys = <&usb2_phy0 2>; 1601 phy-names = "usb"; 1602 companion = <&ohci0>; 1603 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1604 resets = <&cpg 703>, <&cpg 704>; 1605 status = "disabled"; 1606 }; 1607 1608 usb2_phy0: usb-phy@ee080200 { 1609 compatible = "renesas,usb2-phy-r8a774c0", 1610 "renesas,rcar-gen3-usb2-phy"; 1611 reg = <0 0xee080200 0 0x700>; 1612 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1613 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 1614 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1615 resets = <&cpg 703>, <&cpg 704>; 1616 #phy-cells = <1>; 1617 status = "disabled"; 1618 }; 1619 1620 sdhi0: sd@ee100000 { 1621 compatible = "renesas,sdhi-r8a774c0", 1622 "renesas,rcar-gen3-sdhi"; 1623 reg = <0 0xee100000 0 0x2000>; 1624 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 1625 clocks = <&cpg CPG_MOD 314>; 1626 max-frequency = <200000000>; 1627 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1628 resets = <&cpg 314>; 1629 status = "disabled"; 1630 }; 1631 1632 sdhi1: sd@ee120000 { 1633 compatible = "renesas,sdhi-r8a774c0", 1634 "renesas,rcar-gen3-sdhi"; 1635 reg = <0 0xee120000 0 0x2000>; 1636 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1637 clocks = <&cpg CPG_MOD 313>; 1638 max-frequency = <200000000>; 1639 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1640 resets = <&cpg 313>; 1641 status = "disabled"; 1642 }; 1643 1644 sdhi3: sd@ee160000 { 1645 compatible = "renesas,sdhi-r8a774c0", 1646 "renesas,rcar-gen3-sdhi"; 1647 reg = <0 0xee160000 0 0x2000>; 1648 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 1649 clocks = <&cpg CPG_MOD 311>; 1650 max-frequency = <200000000>; 1651 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1652 resets = <&cpg 311>; 1653 status = "disabled"; 1654 }; 1655 1656 gic: interrupt-controller@f1010000 { 1657 compatible = "arm,gic-400"; 1658 #interrupt-cells = <3>; 1659 #address-cells = <0>; 1660 interrupt-controller; 1661 reg = <0x0 0xf1010000 0 0x1000>, 1662 <0x0 0xf1020000 0 0x20000>, 1663 <0x0 0xf1040000 0 0x20000>, 1664 <0x0 0xf1060000 0 0x20000>; 1665 interrupts = <GIC_PPI 9 1666 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 1667 clocks = <&cpg CPG_MOD 408>; 1668 clock-names = "clk"; 1669 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1670 resets = <&cpg 408>; 1671 }; 1672 1673 pciec0: pcie@fe000000 { 1674 compatible = "renesas,pcie-r8a774c0", 1675 "renesas,pcie-rcar-gen3"; 1676 reg = <0 0xfe000000 0 0x80000>; 1677 #address-cells = <3>; 1678 #size-cells = <2>; 1679 bus-range = <0x00 0xff>; 1680 device_type = "pci"; 1681 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000 1682 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000 1683 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000 1684 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; 1685 /* Map all possible DDR as inbound ranges */ 1686 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>; 1687 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1688 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1689 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1690 #interrupt-cells = <1>; 1691 interrupt-map-mask = <0 0 0 0>; 1692 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 1693 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; 1694 clock-names = "pcie", "pcie_bus"; 1695 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1696 resets = <&cpg 319>; 1697 status = "disabled"; 1698 }; 1699 1700 vspb0: vsp@fe960000 { 1701 compatible = "renesas,vsp2"; 1702 reg = <0 0xfe960000 0 0x8000>; 1703 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 1704 clocks = <&cpg CPG_MOD 626>; 1705 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1706 resets = <&cpg 626>; 1707 renesas,fcp = <&fcpvb0>; 1708 }; 1709 1710 vspd0: vsp@fea20000 { 1711 compatible = "renesas,vsp2"; 1712 reg = <0 0xfea20000 0 0x7000>; 1713 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; 1714 clocks = <&cpg CPG_MOD 623>; 1715 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1716 resets = <&cpg 623>; 1717 renesas,fcp = <&fcpvd0>; 1718 }; 1719 1720 vspd1: vsp@fea28000 { 1721 compatible = "renesas,vsp2"; 1722 reg = <0 0xfea28000 0 0x7000>; 1723 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; 1724 clocks = <&cpg CPG_MOD 622>; 1725 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1726 resets = <&cpg 622>; 1727 renesas,fcp = <&fcpvd1>; 1728 }; 1729 1730 vspi0: vsp@fe9a0000 { 1731 compatible = "renesas,vsp2"; 1732 reg = <0 0xfe9a0000 0 0x8000>; 1733 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>; 1734 clocks = <&cpg CPG_MOD 631>; 1735 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1736 resets = <&cpg 631>; 1737 renesas,fcp = <&fcpvi0>; 1738 }; 1739 1740 fcpvb0: fcp@fe96f000 { 1741 compatible = "renesas,fcpv"; 1742 reg = <0 0xfe96f000 0 0x200>; 1743 clocks = <&cpg CPG_MOD 607>; 1744 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1745 resets = <&cpg 607>; 1746 iommus = <&ipmmu_vp0 5>; 1747 }; 1748 1749 fcpvd0: fcp@fea27000 { 1750 compatible = "renesas,fcpv"; 1751 reg = <0 0xfea27000 0 0x200>; 1752 clocks = <&cpg CPG_MOD 603>; 1753 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1754 resets = <&cpg 603>; 1755 iommus = <&ipmmu_vi0 8>; 1756 }; 1757 1758 fcpvd1: fcp@fea2f000 { 1759 compatible = "renesas,fcpv"; 1760 reg = <0 0xfea2f000 0 0x200>; 1761 clocks = <&cpg CPG_MOD 602>; 1762 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1763 resets = <&cpg 602>; 1764 iommus = <&ipmmu_vi0 9>; 1765 }; 1766 1767 fcpvi0: fcp@fe9af000 { 1768 compatible = "renesas,fcpv"; 1769 reg = <0 0xfe9af000 0 0x200>; 1770 clocks = <&cpg CPG_MOD 611>; 1771 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1772 resets = <&cpg 611>; 1773 iommus = <&ipmmu_vp0 8>; 1774 }; 1775 1776 csi40: csi2@feaa0000 { 1777 compatible = "renesas,r8a774c0-csi2"; 1778 reg = <0 0xfeaa0000 0 0x10000>; 1779 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 1780 clocks = <&cpg CPG_MOD 716>; 1781 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1782 resets = <&cpg 716>; 1783 status = "disabled"; 1784 1785 ports { 1786 #address-cells = <1>; 1787 #size-cells = <0>; 1788 1789 port@1 { 1790 #address-cells = <1>; 1791 #size-cells = <0>; 1792 1793 reg = <1>; 1794 1795 csi40vin4: endpoint@0 { 1796 reg = <0>; 1797 remote-endpoint = <&vin4csi40>; 1798 }; 1799 csi40vin5: endpoint@1 { 1800 reg = <1>; 1801 remote-endpoint = <&vin5csi40>; 1802 }; 1803 }; 1804 }; 1805 }; 1806 1807 du: display@feb00000 { 1808 compatible = "renesas,du-r8a774c0"; 1809 reg = <0 0xfeb00000 0 0x40000>; 1810 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 1811 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; 1812 clocks = <&cpg CPG_MOD 724>, 1813 <&cpg CPG_MOD 723>; 1814 clock-names = "du.0", "du.1"; 1815 vsps = <&vspd0 0>, <&vspd1 0>; 1816 status = "disabled"; 1817 1818 ports { 1819 #address-cells = <1>; 1820 #size-cells = <0>; 1821 1822 port@0 { 1823 reg = <0>; 1824 du_out_rgb: endpoint { 1825 }; 1826 }; 1827 1828 port@1 { 1829 reg = <1>; 1830 du_out_lvds0: endpoint { 1831 remote-endpoint = <&lvds0_in>; 1832 }; 1833 }; 1834 1835 port@2 { 1836 reg = <2>; 1837 du_out_lvds1: endpoint { 1838 remote-endpoint = <&lvds1_in>; 1839 }; 1840 }; 1841 }; 1842 }; 1843 1844 lvds0: lvds-encoder@feb90000 { 1845 compatible = "renesas,r8a774c0-lvds"; 1846 reg = <0 0xfeb90000 0 0x20>; 1847 clocks = <&cpg CPG_MOD 727>; 1848 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1849 resets = <&cpg 727>; 1850 status = "disabled"; 1851 1852 renesas,companion = <&lvds1>; 1853 1854 ports { 1855 #address-cells = <1>; 1856 #size-cells = <0>; 1857 1858 port@0 { 1859 reg = <0>; 1860 lvds0_in: endpoint { 1861 remote-endpoint = <&du_out_lvds0>; 1862 }; 1863 }; 1864 1865 port@1 { 1866 reg = <1>; 1867 lvds0_out: endpoint { 1868 }; 1869 }; 1870 }; 1871 }; 1872 1873 lvds1: lvds-encoder@feb90100 { 1874 compatible = "renesas,r8a774c0-lvds"; 1875 reg = <0 0xfeb90100 0 0x20>; 1876 clocks = <&cpg CPG_MOD 727>; 1877 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1878 resets = <&cpg 726>; 1879 status = "disabled"; 1880 1881 ports { 1882 #address-cells = <1>; 1883 #size-cells = <0>; 1884 1885 port@0 { 1886 reg = <0>; 1887 lvds1_in: endpoint { 1888 remote-endpoint = <&du_out_lvds1>; 1889 }; 1890 }; 1891 1892 port@1 { 1893 reg = <1>; 1894 lvds1_out: endpoint { 1895 }; 1896 }; 1897 }; 1898 }; 1899 1900 prr: chipid@fff00044 { 1901 compatible = "renesas,prr"; 1902 reg = <0 0xfff00044 0 4>; 1903 }; 1904 }; 1905 1906 thermal-zones { 1907 cpu-thermal { 1908 polling-delay-passive = <250>; 1909 polling-delay = <0>; 1910 thermal-sensors = <&thermal 0>; 1911 sustainable-power = <717>; 1912 1913 cooling-maps { 1914 map0 { 1915 trip = <&target>; 1916 cooling-device = <&a53_0 0 2>; 1917 contribution = <1024>; 1918 }; 1919 }; 1920 1921 trips { 1922 sensor1_crit: sensor1-crit { 1923 temperature = <120000>; 1924 hysteresis = <2000>; 1925 type = "critical"; 1926 }; 1927 1928 target: trip-point1 { 1929 temperature = <100000>; 1930 hysteresis = <2000>; 1931 type = "passive"; 1932 }; 1933 }; 1934 }; 1935 }; 1936 1937 timer { 1938 compatible = "arm,armv8-timer"; 1939 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 1940 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 1941 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 1942 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 1943 }; 1944 1945 /* External USB clocks - can be overridden by the board */ 1946 usb3s0_clk: usb3s0 { 1947 compatible = "fixed-clock"; 1948 #clock-cells = <0>; 1949 clock-frequency = <0>; 1950 }; 1951 1952 usb_extal_clk: usb_extal { 1953 compatible = "fixed-clock"; 1954 #clock-cells = <0>; 1955 clock-frequency = <0>; 1956 }; 1957}; 1958