1faf1ce7fSLad Prabhakar// SPDX-License-Identifier: GPL-2.0 2faf1ce7fSLad Prabhakar/* 3deadcd50SMarian-Cristian Rotariu * Device Tree Source for the HiHope RZ/G2H Rev.4.0 and 4deadcd50SMarian-Cristian Rotariu * HiHope RZ/G2[MN] Rev.3.0/4.0 main board common parts 5faf1ce7fSLad Prabhakar * 6faf1ce7fSLad Prabhakar * Copyright (C) 2020 Renesas Electronics Corp. 7faf1ce7fSLad Prabhakar */ 8faf1ce7fSLad Prabhakar 9faf1ce7fSLad Prabhakar#include <dt-bindings/gpio/gpio.h> 10faf1ce7fSLad Prabhakar#include "hihope-common.dtsi" 11faf1ce7fSLad Prabhakar 12faf1ce7fSLad Prabhakar/ { 13faf1ce7fSLad Prabhakar audio_clkout: audio-clkout { 14faf1ce7fSLad Prabhakar /* 15faf1ce7fSLad Prabhakar * This is same as <&rcar_sound 0> 16faf1ce7fSLad Prabhakar * but needed to avoid cs2000/rcar_sound probe dead-lock 17faf1ce7fSLad Prabhakar */ 18faf1ce7fSLad Prabhakar compatible = "fixed-clock"; 19faf1ce7fSLad Prabhakar #clock-cells = <0>; 20faf1ce7fSLad Prabhakar clock-frequency = <12288000>; 21faf1ce7fSLad Prabhakar }; 22faf1ce7fSLad Prabhakar 23faf1ce7fSLad Prabhakar wlan_en_reg: regulator-wlan_en { 24faf1ce7fSLad Prabhakar compatible = "regulator-fixed"; 25faf1ce7fSLad Prabhakar regulator-name = "wlan-en-regulator"; 26faf1ce7fSLad Prabhakar regulator-min-microvolt = <1800000>; 27faf1ce7fSLad Prabhakar regulator-max-microvolt = <1800000>; 28faf1ce7fSLad Prabhakar startup-delay-us = <70000>; 29faf1ce7fSLad Prabhakar 30faf1ce7fSLad Prabhakar gpio = <&gpio4 6 GPIO_ACTIVE_HIGH>; 31faf1ce7fSLad Prabhakar enable-active-high; 32faf1ce7fSLad Prabhakar }; 33faf1ce7fSLad Prabhakar 34faf1ce7fSLad Prabhakar x1801_clk: x1801-clock { 35faf1ce7fSLad Prabhakar compatible = "fixed-clock"; 36faf1ce7fSLad Prabhakar #clock-cells = <0>; 37faf1ce7fSLad Prabhakar clock-frequency = <24576000>; 38faf1ce7fSLad Prabhakar }; 39faf1ce7fSLad Prabhakar}; 40faf1ce7fSLad Prabhakar 41faf1ce7fSLad Prabhakar&hscif0 { 42faf1ce7fSLad Prabhakar bluetooth { 43faf1ce7fSLad Prabhakar compatible = "ti,wl1837-st"; 44faf1ce7fSLad Prabhakar enable-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; 45faf1ce7fSLad Prabhakar }; 46faf1ce7fSLad Prabhakar}; 47faf1ce7fSLad Prabhakar 48faf1ce7fSLad Prabhakar&i2c2 { 49faf1ce7fSLad Prabhakar pinctrl-0 = <&i2c2_pins>; 50faf1ce7fSLad Prabhakar pinctrl-names = "default"; 51faf1ce7fSLad Prabhakar status = "okay"; 52faf1ce7fSLad Prabhakar 53faf1ce7fSLad Prabhakar cs2000: clk_multiplier@4f { 54faf1ce7fSLad Prabhakar #clock-cells = <0>; 55faf1ce7fSLad Prabhakar compatible = "cirrus,cs2000-cp"; 56faf1ce7fSLad Prabhakar reg = <0x4f>; 57faf1ce7fSLad Prabhakar clocks = <&audio_clkout>, <&x1801_clk>; 58faf1ce7fSLad Prabhakar clock-names = "clk_in", "ref_clk"; 59faf1ce7fSLad Prabhakar 60faf1ce7fSLad Prabhakar assigned-clocks = <&cs2000>; 61faf1ce7fSLad Prabhakar assigned-clock-rates = <24576000>; /* 1/1 divide */ 62faf1ce7fSLad Prabhakar }; 63faf1ce7fSLad Prabhakar}; 64faf1ce7fSLad Prabhakar 65faf1ce7fSLad Prabhakar&pfc { 66faf1ce7fSLad Prabhakar i2c2_pins: i2c2 { 67faf1ce7fSLad Prabhakar groups = "i2c2_a"; 68faf1ce7fSLad Prabhakar function = "i2c2"; 69faf1ce7fSLad Prabhakar }; 70faf1ce7fSLad Prabhakar 71faf1ce7fSLad Prabhakar sound_clk_pins: sound_clk { 72faf1ce7fSLad Prabhakar groups = "audio_clk_a_a", "audio_clk_b_a", "audio_clkout_a"; 73faf1ce7fSLad Prabhakar function = "audio_clk"; 74faf1ce7fSLad Prabhakar }; 75faf1ce7fSLad Prabhakar 76faf1ce7fSLad Prabhakar sound_pins: sound { 77faf1ce7fSLad Prabhakar groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a"; 78faf1ce7fSLad Prabhakar function = "ssi"; 79faf1ce7fSLad Prabhakar }; 80faf1ce7fSLad Prabhakar}; 81faf1ce7fSLad Prabhakar 82faf1ce7fSLad Prabhakar&rcar_sound { 83*3ebf49c0SGeert Uytterhoeven pinctrl-0 = <&sound_pins>, <&sound_clk_pins>; 84faf1ce7fSLad Prabhakar pinctrl-names = "default"; 85faf1ce7fSLad Prabhakar status = "okay"; 86faf1ce7fSLad Prabhakar 87faf1ce7fSLad Prabhakar /* audio_clkout0/1/2/3 */ 88faf1ce7fSLad Prabhakar #clock-cells = <1>; 89faf1ce7fSLad Prabhakar clock-frequency = <12288000 11289600>; 90faf1ce7fSLad Prabhakar 9143bba657SLad Prabhakar /* 9243bba657SLad Prabhakar * Update <audio_clk_b> to <cs2000> 9343bba657SLad Prabhakar * Switch SW2404 should be at position 1 so that clock from 9443bba657SLad Prabhakar * CS2000 is connected to AUDIO_CLKB_A 9543bba657SLad Prabhakar */ 96faf1ce7fSLad Prabhakar clocks = <&cpg CPG_MOD 1005>, 97faf1ce7fSLad Prabhakar <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, 98faf1ce7fSLad Prabhakar <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, 99faf1ce7fSLad Prabhakar <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, 100faf1ce7fSLad Prabhakar <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, 101faf1ce7fSLad Prabhakar <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, 102faf1ce7fSLad Prabhakar <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, 103faf1ce7fSLad Prabhakar <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, 104faf1ce7fSLad Prabhakar <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, 105faf1ce7fSLad Prabhakar <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, 106faf1ce7fSLad Prabhakar <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, 107faf1ce7fSLad Prabhakar <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 108faf1ce7fSLad Prabhakar <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 109faf1ce7fSLad Prabhakar <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, 110faf1ce7fSLad Prabhakar <&audio_clk_a>, <&cs2000>, 111faf1ce7fSLad Prabhakar <&audio_clk_c>, 112faf1ce7fSLad Prabhakar <&cpg CPG_CORE CPG_AUDIO_CLK_I>; 113faf1ce7fSLad Prabhakar 114faf1ce7fSLad Prabhakar rsnd_port: port { 115faf1ce7fSLad Prabhakar rsnd_endpoint: endpoint { 116faf1ce7fSLad Prabhakar remote-endpoint = <&dw_hdmi0_snd_in>; 117faf1ce7fSLad Prabhakar 118faf1ce7fSLad Prabhakar dai-format = "i2s"; 119faf1ce7fSLad Prabhakar bitclock-master = <&rsnd_endpoint>; 120faf1ce7fSLad Prabhakar frame-master = <&rsnd_endpoint>; 121faf1ce7fSLad Prabhakar 122faf1ce7fSLad Prabhakar playback = <&ssi2>; 123faf1ce7fSLad Prabhakar }; 124faf1ce7fSLad Prabhakar }; 125faf1ce7fSLad Prabhakar}; 126