xref: /openbmc/linux/scripts/dtc/include-prefixes/arm64/qcom/sc7180-trogdor-wormdingler.dtsi (revision 060f35a317ef09101b128f399dce7ed13d019461)
1e0ff30b2SJoseph S. Barrera III// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2e0ff30b2SJoseph S. Barrera III/*
3e0ff30b2SJoseph S. Barrera III * Google Wormdingler board device tree source
4e0ff30b2SJoseph S. Barrera III *
5e0ff30b2SJoseph S. Barrera III * Copyright 2021 Google LLC.
6e0ff30b2SJoseph S. Barrera III */
7e0ff30b2SJoseph S. Barrera III
8e0ff30b2SJoseph S. Barrera III/dts-v1/;
9e0ff30b2SJoseph S. Barrera III
10e0ff30b2SJoseph S. Barrera III#include "sc7180-trogdor.dtsi"
11e0ff30b2SJoseph S. Barrera III
12e0ff30b2SJoseph S. Barrera III/ {
13b62dfbf8SKrzysztof Kozlowski	avdd_lcd: avdd-lcd-regulator {
14e0ff30b2SJoseph S. Barrera III		compatible = "regulator-fixed";
15e0ff30b2SJoseph S. Barrera III		regulator-name = "avdd_lcd";
16e0ff30b2SJoseph S. Barrera III
17e0ff30b2SJoseph S. Barrera III		gpio = <&tlmm 88 GPIO_ACTIVE_HIGH>;
18e0ff30b2SJoseph S. Barrera III		enable-active-high;
19e0ff30b2SJoseph S. Barrera III		pinctrl-names = "default";
20e0ff30b2SJoseph S. Barrera III		pinctrl-0 = <&avdd_lcd_en>;
21e0ff30b2SJoseph S. Barrera III
22e0ff30b2SJoseph S. Barrera III		vin-supply = <&pp5000_a>;
23e0ff30b2SJoseph S. Barrera III	};
24e0ff30b2SJoseph S. Barrera III
25b62dfbf8SKrzysztof Kozlowski	avee_lcd: avee-lcd-regulator {
26e0ff30b2SJoseph S. Barrera III		compatible = "regulator-fixed";
27e0ff30b2SJoseph S. Barrera III		regulator-name = "avee_lcd";
28e0ff30b2SJoseph S. Barrera III
29e0ff30b2SJoseph S. Barrera III		gpio = <&tlmm 21 GPIO_ACTIVE_HIGH>;
30e0ff30b2SJoseph S. Barrera III		enable-active-high;
31e0ff30b2SJoseph S. Barrera III		pinctrl-names = "default";
32e0ff30b2SJoseph S. Barrera III		pinctrl-0 = <&avee_lcd_en>;
33e0ff30b2SJoseph S. Barrera III
34e0ff30b2SJoseph S. Barrera III		vin-supply = <&pp5000_a>;
35e0ff30b2SJoseph S. Barrera III	};
36e0ff30b2SJoseph S. Barrera III
37e0ff30b2SJoseph S. Barrera III	pp1800_ts:
38b62dfbf8SKrzysztof Kozlowski	v1p8_mipi: v1p8-mipi-regulator {
39e0ff30b2SJoseph S. Barrera III		compatible = "regulator-fixed";
40e0ff30b2SJoseph S. Barrera III		regulator-name = "v1p8_mipi";
41e0ff30b2SJoseph S. Barrera III
42e0ff30b2SJoseph S. Barrera III		gpio = <&tlmm 86 GPIO_ACTIVE_HIGH>;
43e0ff30b2SJoseph S. Barrera III		enable-active-high;
44e0ff30b2SJoseph S. Barrera III		pinctrl-names = "default";
45e0ff30b2SJoseph S. Barrera III		pinctrl-0 = <&mipi_1800_en>;
46e0ff30b2SJoseph S. Barrera III
47e0ff30b2SJoseph S. Barrera III		vin-supply = <&pp3300_a>;
48e0ff30b2SJoseph S. Barrera III	};
49e0ff30b2SJoseph S. Barrera III
50e0ff30b2SJoseph S. Barrera III	thermal-zones {
51e0ff30b2SJoseph S. Barrera III		skin_temp_thermal: skin-temp-thermal {
52e0ff30b2SJoseph S. Barrera III			polling-delay-passive = <250>;
53e0ff30b2SJoseph S. Barrera III
54e0ff30b2SJoseph S. Barrera III			thermal-sensors = <&pm6150_adc_tm 1>;
55e0ff30b2SJoseph S. Barrera III			sustainable-power = <574>;
56e0ff30b2SJoseph S. Barrera III
57e0ff30b2SJoseph S. Barrera III			trips {
58e0ff30b2SJoseph S. Barrera III				skin_temp_alert0: trip-point0 {
59e0ff30b2SJoseph S. Barrera III					temperature = <58000>;
60e0ff30b2SJoseph S. Barrera III					hysteresis = <1000>;
61e0ff30b2SJoseph S. Barrera III					type = "passive";
62e0ff30b2SJoseph S. Barrera III				};
63e0ff30b2SJoseph S. Barrera III
64e0ff30b2SJoseph S. Barrera III				skin_temp_alert1: trip-point1 {
65e0ff30b2SJoseph S. Barrera III					temperature = <62500>;
66e0ff30b2SJoseph S. Barrera III					hysteresis = <1000>;
67e0ff30b2SJoseph S. Barrera III					type = "passive";
68e0ff30b2SJoseph S. Barrera III				};
69e0ff30b2SJoseph S. Barrera III
70e0ff30b2SJoseph S. Barrera III				skin-temp-crit {
71e0ff30b2SJoseph S. Barrera III					temperature = <68000>;
72e0ff30b2SJoseph S. Barrera III					hysteresis = <1000>;
73e0ff30b2SJoseph S. Barrera III					type = "critical";
74e0ff30b2SJoseph S. Barrera III				};
75e0ff30b2SJoseph S. Barrera III			};
76e0ff30b2SJoseph S. Barrera III
77e0ff30b2SJoseph S. Barrera III			cooling-maps {
78e0ff30b2SJoseph S. Barrera III				map0 {
79e0ff30b2SJoseph S. Barrera III					trip = <&skin_temp_alert0>;
80*1f11e59dSKrzysztof Kozlowski					cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
81*1f11e59dSKrzysztof Kozlowski							 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
82e0ff30b2SJoseph S. Barrera III				};
83e0ff30b2SJoseph S. Barrera III
84e0ff30b2SJoseph S. Barrera III				map1 {
85e0ff30b2SJoseph S. Barrera III					trip = <&skin_temp_alert1>;
86*1f11e59dSKrzysztof Kozlowski					cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
87*1f11e59dSKrzysztof Kozlowski							 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
88e0ff30b2SJoseph S. Barrera III				};
89e0ff30b2SJoseph S. Barrera III			};
90e0ff30b2SJoseph S. Barrera III		};
91e0ff30b2SJoseph S. Barrera III	};
92e0ff30b2SJoseph S. Barrera III};
93e0ff30b2SJoseph S. Barrera III
94e0ff30b2SJoseph S. Barrera III&backlight {
95e0ff30b2SJoseph S. Barrera III	pwms = <&cros_ec_pwm 0>;
96e0ff30b2SJoseph S. Barrera III};
97e0ff30b2SJoseph S. Barrera III
98e0ff30b2SJoseph S. Barrera III&camcc {
99e0ff30b2SJoseph S. Barrera III	status = "okay";
100e0ff30b2SJoseph S. Barrera III};
101e0ff30b2SJoseph S. Barrera III
102e0ff30b2SJoseph S. Barrera III&cros_ec {
103e0ff30b2SJoseph S. Barrera III	base_detection: cbas {
104e0ff30b2SJoseph S. Barrera III		compatible = "google,cros-cbas";
105e0ff30b2SJoseph S. Barrera III	};
106a10b760bSStephen Boyd
107a10b760bSStephen Boyd	keyboard-controller {
108a10b760bSStephen Boyd		compatible = "google,cros-ec-keyb-switches";
109a10b760bSStephen Boyd	};
110e0ff30b2SJoseph S. Barrera III};
111e0ff30b2SJoseph S. Barrera III
112e0ff30b2SJoseph S. Barrera III&i2c4 {
113e0ff30b2SJoseph S. Barrera III	status = "okay";
114e0ff30b2SJoseph S. Barrera III	clock-frequency = <400000>;
115e0ff30b2SJoseph S. Barrera III
116e0ff30b2SJoseph S. Barrera III	ap_ts: touchscreen@1 {
117e0ff30b2SJoseph S. Barrera III		compatible = "hid-over-i2c";
118e0ff30b2SJoseph S. Barrera III		reg = <0x01>;
119e0ff30b2SJoseph S. Barrera III		pinctrl-names = "default";
120e0ff30b2SJoseph S. Barrera III		pinctrl-0 = <&ts_int_l>;
121e0ff30b2SJoseph S. Barrera III
122e0ff30b2SJoseph S. Barrera III		interrupt-parent = <&tlmm>;
123e0ff30b2SJoseph S. Barrera III		interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
124e0ff30b2SJoseph S. Barrera III
125e0ff30b2SJoseph S. Barrera III		post-power-on-delay-ms = <70>;
126e0ff30b2SJoseph S. Barrera III		hid-descr-addr = <0x0001>;
127e0ff30b2SJoseph S. Barrera III
128e0ff30b2SJoseph S. Barrera III		vdd-supply = <&pp3300_ts>;
129e0ff30b2SJoseph S. Barrera III		vddl-supply = <&pp1800_ts>;
130e0ff30b2SJoseph S. Barrera III	};
131e0ff30b2SJoseph S. Barrera III};
132e0ff30b2SJoseph S. Barrera III
1332b616f86SDmitry Baryshkov&mdss_dsi0 {
1342b616f86SDmitry Baryshkov
1352b616f86SDmitry Baryshkov	panel: panel@0 {
1362b616f86SDmitry Baryshkov		reg = <0>;
1372b616f86SDmitry Baryshkov		enable-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>;
1382b616f86SDmitry Baryshkov		pinctrl-names = "default";
1392b616f86SDmitry Baryshkov		pinctrl-0 = <&vdd_reset_1800>;
1402b616f86SDmitry Baryshkov		avdd-supply = <&avdd_lcd>;
1412b616f86SDmitry Baryshkov		avee-supply = <&avee_lcd>;
1422b616f86SDmitry Baryshkov		pp1800-supply = <&v1p8_mipi>;
1432b616f86SDmitry Baryshkov		pp3300-supply = <&pp3300_dx_edp>;
1442b616f86SDmitry Baryshkov		backlight = <&backlight>;
1452b616f86SDmitry Baryshkov		rotation = <270>;
1462b616f86SDmitry Baryshkov
1472b616f86SDmitry Baryshkov		port {
1482b616f86SDmitry Baryshkov			panel_in: endpoint {
1492b616f86SDmitry Baryshkov				remote-endpoint = <&mdss_dsi0_out>;
1502b616f86SDmitry Baryshkov			};
1512b616f86SDmitry Baryshkov		};
1522b616f86SDmitry Baryshkov	};
1532b616f86SDmitry Baryshkov
1542b616f86SDmitry Baryshkov	ports {
1552b616f86SDmitry Baryshkov		port@1 {
1562b616f86SDmitry Baryshkov			endpoint {
1572b616f86SDmitry Baryshkov				remote-endpoint = <&panel_in>;
1582b616f86SDmitry Baryshkov				data-lanes = <0 1 2 3>;
1592b616f86SDmitry Baryshkov			};
1602b616f86SDmitry Baryshkov		};
1612b616f86SDmitry Baryshkov	};
1622b616f86SDmitry Baryshkov};
1632b616f86SDmitry Baryshkov
164e0ff30b2SJoseph S. Barrera III&pm6150_adc {
16541c18552SMarijn Suijten	channel@4d {
166e0ff30b2SJoseph S. Barrera III		reg = <ADC5_AMUX_THM1_100K_PU>;
167e0ff30b2SJoseph S. Barrera III		qcom,ratiometric;
168e0ff30b2SJoseph S. Barrera III		qcom,hw-settle-time = <200>;
16941c18552SMarijn Suijten		label = "skin_therm";
170e0ff30b2SJoseph S. Barrera III	};
171e0ff30b2SJoseph S. Barrera III};
172e0ff30b2SJoseph S. Barrera III
173e0ff30b2SJoseph S. Barrera III&pm6150_adc_tm {
174e0ff30b2SJoseph S. Barrera III	status = "okay";
175e0ff30b2SJoseph S. Barrera III
176e0ff30b2SJoseph S. Barrera III	skin-temp-thermistor@1 {
177e0ff30b2SJoseph S. Barrera III		reg = <1>;
178e0ff30b2SJoseph S. Barrera III		io-channels = <&pm6150_adc ADC5_AMUX_THM1_100K_PU>;
179e0ff30b2SJoseph S. Barrera III		qcom,ratiometric;
180e0ff30b2SJoseph S. Barrera III		qcom,hw-settle-time-us = <200>;
181e0ff30b2SJoseph S. Barrera III	};
182e0ff30b2SJoseph S. Barrera III};
183e0ff30b2SJoseph S. Barrera III
184e0ff30b2SJoseph S. Barrera III&pp1800_uf_cam {
185e0ff30b2SJoseph S. Barrera III	status = "okay";
186e0ff30b2SJoseph S. Barrera III};
187e0ff30b2SJoseph S. Barrera III
188e0ff30b2SJoseph S. Barrera III&pp1800_wf_cam {
189e0ff30b2SJoseph S. Barrera III	status = "okay";
190e0ff30b2SJoseph S. Barrera III};
191e0ff30b2SJoseph S. Barrera III
192e0ff30b2SJoseph S. Barrera III&pp2800_uf_cam {
193e0ff30b2SJoseph S. Barrera III	status = "okay";
194e0ff30b2SJoseph S. Barrera III};
195e0ff30b2SJoseph S. Barrera III
196e0ff30b2SJoseph S. Barrera III&pp2800_wf_cam {
197e0ff30b2SJoseph S. Barrera III	status = "okay";
198e0ff30b2SJoseph S. Barrera III};
199e0ff30b2SJoseph S. Barrera III
200e0ff30b2SJoseph S. Barrera III&wifi {
201e0ff30b2SJoseph S. Barrera III	qcom,ath10k-calibration-variant = "GO_WORMDINGLER";
202e0ff30b2SJoseph S. Barrera III};
203e0ff30b2SJoseph S. Barrera III
204e0ff30b2SJoseph S. Barrera III/*
205e0ff30b2SJoseph S. Barrera III * No eDP on this board but it's logically the same signal so just give it
206e0ff30b2SJoseph S. Barrera III * a new name and assign the proper GPIO.
207e0ff30b2SJoseph S. Barrera III */
208e0ff30b2SJoseph S. Barrera IIIpp3300_disp_on: &pp3300_dx_edp {
209e0ff30b2SJoseph S. Barrera III	gpio = <&tlmm 85 GPIO_ACTIVE_HIGH>;
210e0ff30b2SJoseph S. Barrera III};
211e0ff30b2SJoseph S. Barrera III
212e0ff30b2SJoseph S. Barrera III/* PINCTRL - modifications to sc7180-trogdor.dtsi */
213e0ff30b2SJoseph S. Barrera III
214e0ff30b2SJoseph S. Barrera III/*
215e0ff30b2SJoseph S. Barrera III * No eDP on this board but it's logically the same signal so just give it
216e0ff30b2SJoseph S. Barrera III * a new name and assign the proper GPIO.
217e0ff30b2SJoseph S. Barrera III */
218e0ff30b2SJoseph S. Barrera III
219e0ff30b2SJoseph S. Barrera IIItp_en: &en_pp3300_dx_edp {
220e0ff30b2SJoseph S. Barrera III	pins = "gpio85";
221e0ff30b2SJoseph S. Barrera III};
222e0ff30b2SJoseph S. Barrera III
223e0ff30b2SJoseph S. Barrera III/* PINCTRL - board-specific pinctrl */
224e0ff30b2SJoseph S. Barrera III
225e0ff30b2SJoseph S. Barrera III&tlmm {
226e0ff30b2SJoseph S. Barrera III	gpio-line-names = "HUB_RST_L",
227e0ff30b2SJoseph S. Barrera III			  "AP_RAM_ID0",
228e0ff30b2SJoseph S. Barrera III			  "AP_SKU_ID2",
229e0ff30b2SJoseph S. Barrera III			  "AP_RAM_ID1",
230e0ff30b2SJoseph S. Barrera III			  "",
231e0ff30b2SJoseph S. Barrera III			  "AP_RAM_ID2",
232e0ff30b2SJoseph S. Barrera III			  "UF_CAM_EN",
233e0ff30b2SJoseph S. Barrera III			  "WF_CAM_EN",
234e0ff30b2SJoseph S. Barrera III			  "TS_RESET_L",
235e0ff30b2SJoseph S. Barrera III			  "TS_INT_L",
236e0ff30b2SJoseph S. Barrera III			  "",
237e0ff30b2SJoseph S. Barrera III			  "",
238e0ff30b2SJoseph S. Barrera III			  "AP_EDP_BKLTEN",
239e0ff30b2SJoseph S. Barrera III			  "UF_CAM_MCLK",
240e0ff30b2SJoseph S. Barrera III			  "WF_CAM_CLK",
241e0ff30b2SJoseph S. Barrera III			  "",
242e0ff30b2SJoseph S. Barrera III			  "",
243e0ff30b2SJoseph S. Barrera III			  "UF_CAM_SDA",
244e0ff30b2SJoseph S. Barrera III			  "UF_CAM_SCL",
245e0ff30b2SJoseph S. Barrera III			  "WF_CAM_SDA",
246e0ff30b2SJoseph S. Barrera III			  "WF_CAM_SCL",
247e0ff30b2SJoseph S. Barrera III			  "AVEE_LCD_EN",
248e0ff30b2SJoseph S. Barrera III			  "",
249e0ff30b2SJoseph S. Barrera III			  "AMP_EN",
250e0ff30b2SJoseph S. Barrera III			  "",
251e0ff30b2SJoseph S. Barrera III			  "",
252e0ff30b2SJoseph S. Barrera III			  "",
253e0ff30b2SJoseph S. Barrera III			  "",
254e0ff30b2SJoseph S. Barrera III			  "HP_IRQ",
255e0ff30b2SJoseph S. Barrera III			  "WF_CAM_RST_L",
256e0ff30b2SJoseph S. Barrera III			  "UF_CAM_RST_L",
257e0ff30b2SJoseph S. Barrera III			  "AP_BRD_ID2",
258e0ff30b2SJoseph S. Barrera III			  "",
259e0ff30b2SJoseph S. Barrera III			  "AP_BRD_ID0",
260e0ff30b2SJoseph S. Barrera III			  "AP_H1_SPI_MISO",
261e0ff30b2SJoseph S. Barrera III			  "AP_H1_SPI_MOSI",
262e0ff30b2SJoseph S. Barrera III			  "AP_H1_SPI_CLK",
263e0ff30b2SJoseph S. Barrera III			  "AP_H1_SPI_CS_L",
264e0ff30b2SJoseph S. Barrera III			  "BT_UART_CTS",
265e0ff30b2SJoseph S. Barrera III			  "BT_UART_RTS",
266e0ff30b2SJoseph S. Barrera III			  "BT_UART_TXD",
267e0ff30b2SJoseph S. Barrera III			  "BT_UART_RXD",
268e0ff30b2SJoseph S. Barrera III			  "H1_AP_INT_ODL",
269e0ff30b2SJoseph S. Barrera III			  "",
270e0ff30b2SJoseph S. Barrera III			  "UART_AP_TX_DBG_RX",
271e0ff30b2SJoseph S. Barrera III			  "UART_DBG_TX_AP_RX",
272e0ff30b2SJoseph S. Barrera III			  "HP_I2C_SDA",
273e0ff30b2SJoseph S. Barrera III			  "HP_I2C_SCL",
274e0ff30b2SJoseph S. Barrera III			  "FORCED_USB_BOOT",
275e0ff30b2SJoseph S. Barrera III			  "AMP_BCLK",
276e0ff30b2SJoseph S. Barrera III			  "AMP_LRCLK",
277e0ff30b2SJoseph S. Barrera III			  "AMP_DIN",
278e0ff30b2SJoseph S. Barrera III			  "",
279e0ff30b2SJoseph S. Barrera III			  "HP_BCLK",
280e0ff30b2SJoseph S. Barrera III			  "HP_LRCLK",
281e0ff30b2SJoseph S. Barrera III			  "HP_DOUT",
282e0ff30b2SJoseph S. Barrera III			  "HP_DIN",
283e0ff30b2SJoseph S. Barrera III			  "HP_MCLK",
284e0ff30b2SJoseph S. Barrera III			  "AP_SKU_ID0",
285e0ff30b2SJoseph S. Barrera III			  "AP_EC_SPI_MISO",
286e0ff30b2SJoseph S. Barrera III			  "AP_EC_SPI_MOSI",
287e0ff30b2SJoseph S. Barrera III			  "AP_EC_SPI_CLK",
288e0ff30b2SJoseph S. Barrera III			  "AP_EC_SPI_CS_L",
289e0ff30b2SJoseph S. Barrera III			  "AP_SPI_CLK",
290e0ff30b2SJoseph S. Barrera III			  "AP_SPI_MOSI",
291e0ff30b2SJoseph S. Barrera III			  "AP_SPI_MISO",
292e0ff30b2SJoseph S. Barrera III			  /*
293e0ff30b2SJoseph S. Barrera III			   * AP_FLASH_WP_L is crossystem ABI. Schematics
294e0ff30b2SJoseph S. Barrera III			   * call it BIOS_FLASH_WP_L.
295e0ff30b2SJoseph S. Barrera III			   */
296e0ff30b2SJoseph S. Barrera III			  "AP_FLASH_WP_L",
297e0ff30b2SJoseph S. Barrera III			  "",
298e0ff30b2SJoseph S. Barrera III			  "AP_SPI_CS0_L",
299e0ff30b2SJoseph S. Barrera III			  "",
300e0ff30b2SJoseph S. Barrera III			  "",
301e0ff30b2SJoseph S. Barrera III			  "",
302e0ff30b2SJoseph S. Barrera III			  "",
303e0ff30b2SJoseph S. Barrera III			  "WLAN_SW_CTRL",
304e0ff30b2SJoseph S. Barrera III			  "",
305e0ff30b2SJoseph S. Barrera III			  "REPORT_E",
306e0ff30b2SJoseph S. Barrera III			  "",
307e0ff30b2SJoseph S. Barrera III			  "ID0",
308e0ff30b2SJoseph S. Barrera III			  "",
309e0ff30b2SJoseph S. Barrera III			  "ID1",
310e0ff30b2SJoseph S. Barrera III			  "",
311e0ff30b2SJoseph S. Barrera III			  "",
312e0ff30b2SJoseph S. Barrera III			  "",
313e0ff30b2SJoseph S. Barrera III			  "CODEC_PWR_EN",
314e0ff30b2SJoseph S. Barrera III			  "HUB_EN",
315e0ff30b2SJoseph S. Barrera III			  "TP_EN",
316e0ff30b2SJoseph S. Barrera III			  "MIPI_1.8V_EN",
317e0ff30b2SJoseph S. Barrera III			  "VDD_RESET_1.8V",
318e0ff30b2SJoseph S. Barrera III			  "AVDD_LCD_EN",
319e0ff30b2SJoseph S. Barrera III			  "",
320e0ff30b2SJoseph S. Barrera III			  "AP_SKU_ID1",
321e0ff30b2SJoseph S. Barrera III			  "AP_RST_REQ",
322e0ff30b2SJoseph S. Barrera III			  "",
323e0ff30b2SJoseph S. Barrera III			  "AP_BRD_ID1",
324e0ff30b2SJoseph S. Barrera III			  "AP_EC_INT_L",
325e0ff30b2SJoseph S. Barrera III			  "SDM_GRFC_3",
326e0ff30b2SJoseph S. Barrera III			  "",
327e0ff30b2SJoseph S. Barrera III			  "",
328e0ff30b2SJoseph S. Barrera III			  "BOOT_CONFIG_4",
329e0ff30b2SJoseph S. Barrera III			  "BOOT_CONFIG_2",
330e0ff30b2SJoseph S. Barrera III			  "",
331e0ff30b2SJoseph S. Barrera III			  "",
332e0ff30b2SJoseph S. Barrera III			  "",
333e0ff30b2SJoseph S. Barrera III			  "",
334e0ff30b2SJoseph S. Barrera III			  "",
335e0ff30b2SJoseph S. Barrera III			  "",
336e0ff30b2SJoseph S. Barrera III			  "",
337e0ff30b2SJoseph S. Barrera III			  "BOOT_CONFIG_3",
338e0ff30b2SJoseph S. Barrera III			  "WCI2_LTE_COEX_TXD",
339e0ff30b2SJoseph S. Barrera III			  "WCI2_LTE_COEX_RXD",
340e0ff30b2SJoseph S. Barrera III			  "",
341e0ff30b2SJoseph S. Barrera III			  "",
342e0ff30b2SJoseph S. Barrera III			  "",
343e0ff30b2SJoseph S. Barrera III			  "",
344e0ff30b2SJoseph S. Barrera III			  "FORCED_USB_BOOT_POL",
345e0ff30b2SJoseph S. Barrera III			  "AP_TS_PEN_I2C_SDA",
346e0ff30b2SJoseph S. Barrera III			  "AP_TS_PEN_I2C_SCL",
347e0ff30b2SJoseph S. Barrera III			  "DP_HOT_PLUG_DET",
348e0ff30b2SJoseph S. Barrera III			  "EC_IN_RW_ODL";
349e0ff30b2SJoseph S. Barrera III
3502f0300a6SKrzysztof Kozlowski	avdd_lcd_en: avdd-lcd-en-state {
351e0ff30b2SJoseph S. Barrera III		pins = "gpio88";
352e0ff30b2SJoseph S. Barrera III		function = "gpio";
353e0ff30b2SJoseph S. Barrera III		drive-strength = <2>;
354e0ff30b2SJoseph S. Barrera III		bias-disable;
355e0ff30b2SJoseph S. Barrera III	};
356e0ff30b2SJoseph S. Barrera III
3572f0300a6SKrzysztof Kozlowski	avee_lcd_en: avee-lcd-en-state {
358e0ff30b2SJoseph S. Barrera III		pins = "gpio21";
359e0ff30b2SJoseph S. Barrera III		function = "gpio";
360e0ff30b2SJoseph S. Barrera III		drive-strength = <2>;
361e0ff30b2SJoseph S. Barrera III		bias-disable;
362e0ff30b2SJoseph S. Barrera III	};
363e0ff30b2SJoseph S. Barrera III
3642f0300a6SKrzysztof Kozlowski	mipi_1800_en: mipi-1800-en-state {
365e0ff30b2SJoseph S. Barrera III		pins = "gpio86";
366e0ff30b2SJoseph S. Barrera III		function = "gpio";
367e0ff30b2SJoseph S. Barrera III		drive-strength = <2>;
368e0ff30b2SJoseph S. Barrera III		bias-disable;
369e0ff30b2SJoseph S. Barrera III	};
370e0ff30b2SJoseph S. Barrera III
3712f0300a6SKrzysztof Kozlowski	vdd_reset_1800: vdd-reset-1800-state {
372e0ff30b2SJoseph S. Barrera III		pins = "gpio87";
373e0ff30b2SJoseph S. Barrera III		function = "gpio";
374e0ff30b2SJoseph S. Barrera III		drive-strength = <2>;
375e0ff30b2SJoseph S. Barrera III		bias-disable;
376e0ff30b2SJoseph S. Barrera III	};
377e0ff30b2SJoseph S. Barrera III};
378