xref: /openbmc/linux/scripts/dtc/include-prefixes/arm64/qcom/msm8998.dtsi (revision 280acabb)

// SPDX-License-Identifier: GPL-2.0
/* Copyright (c) 2016, The Linux Foundation. All rights reserved. */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-msm8998.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/gpio/gpio.h>

/ {
	interrupt-parent = <&intc>;

	qcom,msm-id = <292 0x0>;

	#address-cells = <2>;
	#size-cells = <2>;

	chosen { };

	memory {
		device_type = "memory";
		/* We expect the bootloader to fill in the reg */
		reg = <0 0 0 0>;
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		memory@85800000 {
			reg = <0x0 0x85800000 0x0 0x800000>;
			no-map;
		};

		smem_mem: smem-mem@86000000 {
			reg = <0x0 0x86000000 0x0 0x200000>;
			no-map;
		};

		memory@86200000 {
			reg = <0x0 0x86200000 0x0 0x2d00000>;
			no-map;
		};

		rmtfs {
			compatible = "qcom,rmtfs-mem";

			size = <0x0 0x200000>;
			alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>;
			no-map;

			qcom,client-id = <1>;
			qcom,vmid = <15>;
		};
	};

	clocks {
		xo: xo-board {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <19200000>;
			clock-output-names = "xo_board";
		};

		sleep_clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <32764>;
		};
	};

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		CPU0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x0>;
			enable-method = "psci";
			next-level-cache = <&L2_0>;
			L2_0: l2-cache {
				compatible = "arm,arch-cache";
				cache-level = <2>;
			};
			L1_I_0: l1-icache {
				compatible = "arm,arch-cache";
			};
			L1_D_0: l1-dcache {
				compatible = "arm,arch-cache";
			};
		};

		CPU1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x1>;
			enable-method = "psci";
			next-level-cache = <&L2_0>;
			L1_I_1: l1-icache {
				compatible = "arm,arch-cache";
			};
			L1_D_1: l1-dcache {
				compatible = "arm,arch-cache";
			};
		};

		CPU2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x2>;
			enable-method = "psci";
			next-level-cache = <&L2_0>;
			L1_I_2: l1-icache {
				compatible = "arm,arch-cache";
			};
			L1_D_2: l1-dcache {
				compatible = "arm,arch-cache";
			};
		};

		CPU3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x3>;
			enable-method = "psci";
			next-level-cache = <&L2_0>;
			L1_I_3: l1-icache {
				compatible = "arm,arch-cache";
			};
			L1_D_3: l1-dcache {
				compatible = "arm,arch-cache";
			};
		};

		CPU4: cpu@100 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x100>;
			enable-method = "psci";
			next-level-cache = <&L2_1>;
			L2_1: l2-cache {
				compatible = "arm,arch-cache";
				cache-level = <2>;
			};
			L1_I_100: l1-icache {
				compatible = "arm,arch-cache";
			};
			L1_D_100: l1-dcache {
				compatible = "arm,arch-cache";
			};
		};

		CPU5: cpu@101 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x101>;
			enable-method = "psci";
			next-level-cache = <&L2_1>;
			L1_I_101: l1-icache {
				compatible = "arm,arch-cache";
			};
			L1_D_101: l1-dcache {
				compatible = "arm,arch-cache";
			};
		};

		CPU6: cpu@102 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x102>;
			enable-method = "psci";
			next-level-cache = <&L2_1>;
			L1_I_102: l1-icache {
				compatible = "arm,arch-cache";
			};
			L1_D_102: l1-dcache {
				compatible = "arm,arch-cache";
			};
		};

		CPU7: cpu@103 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x103>;
			enable-method = "psci";
			next-level-cache = <&L2_1>;
			L1_I_103: l1-icache {
				compatible = "arm,arch-cache";
			};
			L1_D_103: l1-dcache {
				compatible = "arm,arch-cache";
			};
		};

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&CPU0>;
				};

				core1 {
					cpu = <&CPU1>;
				};

				core2 {
					cpu = <&CPU2>;
				};

				core3 {
					cpu = <&CPU3>;
				};
			};

			cluster1 {
				core0 {
					cpu = <&CPU4>;
				};

				core1 {
					cpu = <&CPU5>;
				};

				core2 {
					cpu = <&CPU6>;
				};

				core3 {
					cpu = <&CPU7>;
				};
			};
		};
	};

	firmware {
		scm {
			compatible = "qcom,scm-msm8998", "qcom,scm";
		};
	};

	tcsr_mutex: hwlock {
		compatible = "qcom,tcsr-mutex";
		syscon = <&tcsr_mutex_regs 0 0x1000>;
		#hwlock-cells = <1>;
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	rpm-glink {
		compatible = "qcom,glink-rpm";

		interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
		qcom,rpm-msg-ram = <&rpm_msg_ram>;
		mboxes = <&apcs_glb 0>;

		rpm_requests: rpm-requests {
			compatible = "qcom,rpm-msm8998";
			qcom,glink-channels = "rpm_requests";

			rpmcc: clock-controller {
				compatible = "qcom,rpmcc-msm8998", "qcom,rpmcc";
				#clock-cells = <1>;
			};
		};
	};

	smem {
		compatible = "qcom,smem";
		memory-region = <&smem_mem>;
		hwlocks = <&tcsr_mutex 3>;
	};

	smp2p-lpass {
		compatible = "qcom,smp2p";
		qcom,smem = <443>, <429>;

		interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;

		mboxes = <&apcs_glb 10>;

		qcom,local-pid = <0>;
		qcom,remote-pid = <2>;

		adsp_smp2p_out: master-kernel {
			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <1>;
		};

		adsp_smp2p_in: slave-kernel {
			qcom,entry-name = "slave-kernel";

			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	smp2p-mpss {
		compatible = "qcom,smp2p";
		qcom,smem = <435>, <428>;
		interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
		mboxes = <&apcs_glb 14>;
		qcom,local-pid = <0>;
		qcom,remote-pid = <1>;

		modem_smp2p_out: master-kernel {
			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <1>;
		};

		modem_smp2p_in: slave-kernel {
			qcom,entry-name = "slave-kernel";
			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	smp2p-slpi {
		compatible = "qcom,smp2p";
		qcom,smem = <481>, <430>;
		interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
		mboxes = <&apcs_glb 26>;
		qcom,local-pid = <0>;
		qcom,remote-pid = <3>;

		slpi_smp2p_out: master-kernel {
			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <1>;
		};

		slpi_smp2p_in: slave-kernel {
			qcom,entry-name = "slave-kernel";
			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	thermal-zones {
		cpu0-thermal {
			polling-delay-passive = <250>;
			polling-delay = <1000>;

			thermal-sensors = <&tsens0 1>;

			trips {
				cpu0_alert0: trip-point@0 {
					temperature = <75000>;
					hysteresis = <2000>;
					type = "passive";
				};

				cpu0_crit: cpu_crit {
					temperature = <110000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
		};

		cpu1-thermal {
			polling-delay-passive = <250>;
			polling-delay = <1000>;

			thermal-sensors = <&tsens0 2>;

			trips {
				cpu1_alert0: trip-point@0 {
					temperature = <75000>;
					hysteresis = <2000>;
					type = "passive";
				};

				cpu1_crit: cpu_crit {
					temperature = <110000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
		};

		cpu2-thermal {
			polling-delay-passive = <250>;
			polling-delay = <1000>;

			thermal-sensors = <&tsens0 3>;

			trips {
				cpu2_alert0: trip-point@0 {
					temperature = <75000>;
					hysteresis = <2000>;
					type = "passive";
				};

				cpu2_crit: cpu_crit {
					temperature = <110000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
		};

		cpu3-thermal {
			polling-delay-passive = <250>;
			polling-delay = <1000>;

			thermal-sensors = <&tsens0 4>;

			trips {
				cpu3_alert0: trip-point@0 {
					temperature = <75000>;
					hysteresis = <2000>;
					type = "passive";
				};

				cpu3_crit: cpu_crit {
					temperature = <110000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
		};

		cpu4-thermal {
			polling-delay-passive = <250>;
			polling-delay = <1000>;

			thermal-sensors = <&tsens0 7>;

			trips {
				cpu4_alert0: trip-point@0 {
					temperature = <75000>;
					hysteresis = <2000>;
					type = "passive";
				};

				cpu4_crit: cpu_crit {
					temperature = <110000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
		};

		cpu5-thermal {
			polling-delay-passive = <250>;
			polling-delay = <1000>;

			thermal-sensors = <&tsens0 8>;

			trips {
				cpu5_alert0: trip-point@0 {
					temperature = <75000>;
					hysteresis = <2000>;
					type = "passive";
				};

				cpu5_crit: cpu_crit {
					temperature = <110000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
		};

		cpu6-thermal {
			polling-delay-passive = <250>;
			polling-delay = <1000>;

			thermal-sensors = <&tsens0 9>;

			trips {
				cpu6_alert0: trip-point@0 {
					temperature = <75000>;
					hysteresis = <2000>;
					type = "passive";
				};

				cpu6_crit: cpu_crit {
					temperature = <110000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
		};

		cpu7-thermal {
			polling-delay-passive = <250>;
			polling-delay = <1000>;

			thermal-sensors = <&tsens0 10>;

			trips {
				cpu7_alert0: trip-point@0 {
					temperature = <75000>;
					hysteresis = <2000>;
					type = "passive";
				};

				cpu7_crit: cpu_crit {
					temperature = <110000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
		};

		gpu-thermal-bottom {
			polling-delay-passive = <250>;
			polling-delay = <1000>;

			thermal-sensors = <&tsens0 12>;

			trips {
				gpu1_alert0: trip-point@0 {
					temperature = <90000>;
					hysteresis = <2000>;
					type = "hot";
				};
			};
		};

		gpu-thermal-top {
			polling-delay-passive = <250>;
			polling-delay = <1000>;

			thermal-sensors = <&tsens0 13>;

			trips {
				gpu2_alert0: trip-point@0 {
					temperature = <90000>;
					hysteresis = <2000>;
					type = "hot";
				};
			};
		};

		cluster0-mhm-thermal {
			polling-delay-passive = <250>;
			polling-delay = <1000>;

			thermal-sensors = <&tsens0 5>;

			trips {
				cluster0_mhm_alert0: trip-point@0 {
					temperature = <90000>;
					hysteresis = <2000>;
					type = "hot";
				};
			};
		};

		cluster1-mhm-thermal {
			polling-delay-passive = <250>;
			polling-delay = <1000>;

			thermal-sensors = <&tsens0 6>;

			trips {
				cluster1_mhm_alert0: trip-point@0 {
					temperature = <90000>;
					hysteresis = <2000>;
					type = "hot";
				};
			};
		};

		cluster1-l2-thermal {
			polling-delay-passive = <250>;
			polling-delay = <1000>;

			thermal-sensors = <&tsens0 11>;

			trips {
				cluster1_l2_alert0: trip-point@0 {
					temperature = <90000>;
					hysteresis = <2000>;
					type = "hot";
				};
			};
		};

		modem-thermal {
			polling-delay-passive = <250>;
			polling-delay = <1000>;

			thermal-sensors = <&tsens1 1>;

			trips {
				modem_alert0: trip-point@0 {
					temperature = <90000>;
					hysteresis = <2000>;
					type = "hot";
				};
			};
		};

		mem-thermal {
			polling-delay-passive = <250>;
			polling-delay = <1000>;

			thermal-sensors = <&tsens1 2>;

			trips {
				mem_alert0: trip-point@0 {
					temperature = <90000>;
					hysteresis = <2000>;
					type = "hot";
				};
			};
		};

		wlan-thermal {
			polling-delay-passive = <250>;
			polling-delay = <1000>;

			thermal-sensors = <&tsens1 3>;

			trips {
				wlan_alert0: trip-point@0 {
					temperature = <90000>;
					hysteresis = <2000>;
					type = "hot";
				};
			};
		};

		q6-dsp-thermal {
			polling-delay-passive = <250>;
			polling-delay = <1000>;

			thermal-sensors = <&tsens1 4>;

			trips {
				q6_dsp_alert0: trip-point@0 {
					temperature = <90000>;
					hysteresis = <2000>;
					type = "hot";
				};
			};
		};

		camera-thermal {
			polling-delay-passive = <250>;
			polling-delay = <1000>;

			thermal-sensors = <&tsens1 5>;

			trips {
				camera_alert0: trip-point@0 {
					temperature = <90000>;
					hysteresis = <2000>;
					type = "hot";
				};
			};
		};

		multimedia-thermal {
			polling-delay-passive = <250>;
			polling-delay = <1000>;

			thermal-sensors = <&tsens1 6>;

			trips {
				multimedia_alert0: trip-point@0 {
					temperature = <90000>;
					hysteresis = <2000>;
					type = "hot";
				};
			};
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
	};

	soc: soc {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0 0 0xffffffff>;
		compatible = "simple-bus";

		rpm_msg_ram: memory@68000 {
			compatible = "qcom,rpm-msg-ram";
			reg = <0x778000 0x7000>;
		};

		qfprom: qfprom@780000 {
			compatible = "qcom,qfprom";
			reg = <0x780000 0x621c>;
			#address-cells = <1>;
			#size-cells = <1>;

			qusb2_hstx_trim: hstx-trim@423a {
				reg = <0x423a 0x1>;
				bits = <0 4>;
			};
		};

		gcc: clock-controller@100000 {
			compatible = "qcom,gcc-msm8998";
			#clock-cells = <1>;
			#reset-cells = <1>;
			#power-domain-cells = <1>;
			reg = <0x100000 0xb0000>;
		};

		tlmm: pinctrl@3400000 {
			compatible = "qcom,msm8998-pinctrl";
			reg = <0x3400000 0xc00000>;
			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <0x2>;
			interrupt-controller;
			#interrupt-cells = <0x2>;
		};

		spmi_bus: spmi@800f000 {
			compatible = "qcom,spmi-pmic-arb";
			reg =	<0x800f000 0x1000>,
				<0x8400000 0x1000000>,
				<0x9400000 0x1000000>,
				<0xa400000 0x220000>,
				<0x800a000 0x3000>;
			reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
			interrupt-names = "periph_irq";
			interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
			qcom,ee = <0>;
			qcom,channel = <0>;
			#address-cells = <2>;
			#size-cells = <0>;
			interrupt-controller;
			#interrupt-cells = <4>;
			cell-index = <0>;
		};

		tsens0: thermal@10ab000 {
			compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
			reg = <0x10ab000 0x1000>, /* TM */
			      <0x10aa000 0x1000>; /* SROT */

			#qcom,sensors = <14>;
			#thermal-sensor-cells = <1>;
		};

		tsens1: thermal@10ae000 {
			compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
			reg = <0x10ae000 0x1000>, /* TM */
			      <0x10ad000 0x1000>; /* SROT */

			#qcom,sensors = <8>;
			#thermal-sensor-cells = <1>;
		};

		tcsr_mutex_regs: syscon@1f40000 {
			compatible = "syscon";
			reg = <0x1f40000 0x20000>;
		};

		apcs_glb: mailbox@9820000 {
			compatible = "qcom,msm8998-apcs-hmss-global";
			reg = <0x17911000 0x1000>;

			#mbox-cells = <1>;
		};

		usb3: usb@a8f8800 {
			compatible = "qcom,msm8998-dwc3", "qcom,dwc3";
			reg = <0x0a8f8800 0x400>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>,
				 <&gcc GCC_USB30_MASTER_CLK>,
				 <&gcc GCC_AGGRE1_USB3_AXI_CLK>,
				 <&gcc GCC_USB30_MOCK_UTMI_CLK>,
				 <&gcc GCC_USB30_SLEEP_CLK>;
			clock-names = "cfg_noc", "core", "iface", "mock_utmi",
				      "sleep";

			assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
					  <&gcc GCC_USB30_MASTER_CLK>;
			assigned-clock-rates = <19200000>, <120000000>;

			interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "hs_phy_irq", "ss_phy_irq";

			power-domains = <&gcc USB_30_GDSC>;

			resets = <&gcc GCC_USB_30_BCR>;

			usb3_dwc3: dwc3@a800000 {
				compatible = "snps,dwc3";
				reg = <0x0a800000 0xcd00>;
				interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
				snps,dis_u2_susphy_quirk;
				snps,dis_enblslpm_quirk;
				phys = <&qusb2phy>, <&usb1_ssphy>;
				phy-names = "usb2-phy", "usb3-phy";
				snps,has-lpm-erratum;
				snps,hird-threshold = /bits/ 8 <0x10>;
			};
		};

		usb3phy: phy@c010000 {
			compatible = "qcom,msm8998-qmp-usb3-phy";
			reg = <0x0c010000 0x18c>;
			status = "disabled";
			#clock-cells = <1>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
				 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
				 <&gcc GCC_USB3_CLKREF_CLK>;
			clock-names = "aux", "cfg_ahb", "ref";

			resets = <&gcc GCC_USB3_PHY_BCR>,
				 <&gcc GCC_USB3PHY_PHY_BCR>;
			reset-names = "phy", "common";

			usb1_ssphy: lane@c010200 {
				reg = <0xc010200 0x128>,
				      <0xc010400 0x200>,
				      <0xc010c00 0x20c>,
				      <0xc010600 0x128>,
				      <0xc010800 0x200>;
				#phy-cells = <0>;
				clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
				clock-names = "pipe0";
				clock-output-names = "usb3_phy_pipe_clk_src";
			};
		};

		qusb2phy: phy@c012000 {
			compatible = "qcom,msm8998-qusb2-phy";
			reg = <0x0c012000 0x2a8>;
			status = "disabled";
			#phy-cells = <0>;

			clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
				 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
			clock-names = "cfg_ahb", "ref";

			resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;

			nvmem-cells = <&qusb2_hstx_trim>;
		};

		sdhc2: sdhci@c0a4900 {
			compatible = "qcom,sdhci-msm-v4";
			reg = <0xc0a4900 0x314>, <0xc0a4000 0x800>;
			reg-names = "hc_mem", "core_mem";

			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "hc_irq", "pwr_irq";

			clock-names = "iface", "core", "xo";
			clocks = <&gcc GCC_SDCC2_AHB_CLK>,
				 <&gcc GCC_SDCC2_APPS_CLK>,
				 <&xo>;
			bus-width = <4>;
			status = "disabled";
		};

		blsp1_i2c1: i2c@c175000 {
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0x0c175000 0x600>;
			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			clock-frequency = <400000>;

			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		blsp1_i2c2: i2c@c176000 {
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0x0c176000 0x600>;
			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			clock-frequency = <400000>;

			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		blsp1_i2c3: i2c@c177000 {
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0x0c177000 0x600>;
			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			clock-frequency = <400000>;

			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		blsp1_i2c4: i2c@c178000 {
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0x0c178000 0x600>;
			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			clock-frequency = <400000>;

			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		blsp1_i2c5: i2c@c179000 {
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0x0c179000 0x600>;
			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			clock-frequency = <400000>;

			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		blsp1_i2c6: i2c@c17a000 {
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0x0c17a000 0x600>;
			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			clock-frequency = <400000>;

			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		blsp2_i2c0: i2c@c1b5000 {
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0x0c1b5000 0x600>;
			interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
				 <&gcc GCC_BLSP2_AHB_CLK>;
			clock-names = "core", "iface";
			clock-frequency = <400000>;

			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		blsp2_i2c1: i2c@c1b6000 {
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0x0c1b6000 0x600>;
			interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
				 <&gcc GCC_BLSP2_AHB_CLK>;
			clock-names = "core", "iface";
			clock-frequency = <400000>;

			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		blsp2_i2c2: i2c@c1b7000 {
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0x0c1b7000 0x600>;
			interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
				 <&gcc GCC_BLSP2_AHB_CLK>;
			clock-names = "core", "iface";
			clock-frequency = <400000>;

			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		blsp2_i2c3: i2c@c1b8000 {
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0x0c1b8000 0x600>;
			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>,
				 <&gcc GCC_BLSP2_AHB_CLK>;
			clock-names = "core", "iface";
			clock-frequency = <400000>;

			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		blsp2_i2c4: i2c@c1b9000 {
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0x0c1b9000 0x600>;
			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>,
				 <&gcc GCC_BLSP2_AHB_CLK>;
			clock-names = "core", "iface";
			clock-frequency = <400000>;

			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		blsp2_i2c5: i2c@c1ba000 {
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0x0c1ba000 0x600>;
			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>,
				 <&gcc GCC_BLSP2_AHB_CLK>;
			clock-names = "core", "iface";
			clock-frequency = <400000>;

			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		blsp2_uart1: serial@c1b0000 {
			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
			reg = <0xc1b0000 0x1000>;
			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
				 <&gcc GCC_BLSP2_AHB_CLK>;
			clock-names = "core", "iface";
			status = "disabled";
		};

		timer@17920000 {
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			compatible = "arm,armv7-timer-mem";
			reg = <0x17920000 0x1000>;

			frame@17921000 {
				frame-number = <0>;
				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x17921000 0x1000>,
				      <0x17922000 0x1000>;
			};

			frame@17923000 {
				frame-number = <1>;
				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x17923000 0x1000>;
				status = "disabled";
			};

			frame@17924000 {
				frame-number = <2>;
				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x17924000 0x1000>;
				status = "disabled";
			};

			frame@17925000 {
				frame-number = <3>;
				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x17925000 0x1000>;
				status = "disabled";
			};

			frame@17926000 {
				frame-number = <4>;
				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x17926000 0x1000>;
				status = "disabled";
			};

			frame@17927000 {
				frame-number = <5>;
				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x17927000 0x1000>;
				status = "disabled";
			};

			frame@17928000 {
				frame-number = <6>;
				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x17928000 0x1000>;
				status = "disabled";
			};
		};

		intc: interrupt-controller@17a00000 {
			compatible = "arm,gic-v3";
			reg = <0x17a00000 0x10000>,       /* GICD */
			      <0x17b00000 0x100000>;      /* GICR * 8 */
			#interrupt-cells = <3>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			interrupt-controller;
			#redistributor-regions = <1>;
			redistributor-stride = <0x0 0x20000>;
			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
		};

		ufshc: ufshc@1da4000 {
			compatible = "qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
			reg = <0x01da4000 0x2500>;
			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
			phys = <&ufsphy_lanes>;
			phy-names = "ufsphy";
			lanes-per-direction = <2>;
			power-domains = <&gcc UFS_GDSC>;
			#reset-cells = <1>;

			clock-names =
				"core_clk",
				"bus_aggr_clk",
				"iface_clk",
				"core_clk_unipro",
				"ref_clk",
				"tx_lane0_sync_clk",
				"rx_lane0_sync_clk",
				"rx_lane1_sync_clk";
			clocks =
				<&gcc GCC_UFS_AXI_CLK>,
				<&gcc GCC_AGGRE1_UFS_AXI_CLK>,
				<&gcc GCC_UFS_AHB_CLK>,
				<&gcc GCC_UFS_UNIPRO_CORE_CLK>,
				<&rpmcc RPM_SMD_LN_BB_CLK1>,
				<&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
				<&gcc GCC_UFS_RX_SYMBOL_0_CLK>,
				<&gcc GCC_UFS_RX_SYMBOL_1_CLK>;
			freq-table-hz =
				<50000000 200000000>,
				<0 0>,
				<0 0>,
				<37500000 150000000>,
				<0 0>,
				<0 0>,
				<0 0>,
				<0 0>;

			resets = <&gcc GCC_UFS_BCR>;
			reset-names = "rst";
		};

		ufsphy: phy@1da7000 {
			compatible = "qcom,msm8998-qmp-ufs-phy";
			reg = <0x01da7000 0x18c>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			clock-names =
				"ref",
				"ref_aux";
			clocks =
				<&gcc GCC_UFS_CLKREF_CLK>,
				<&gcc GCC_UFS_PHY_AUX_CLK>;

			reset-names = "ufsphy";
			resets = <&ufshc 0>;

			ufsphy_lanes: lanes@1da7400 {
				reg = <0x01da7400 0x128>,
				      <0x01da7600 0x1fc>,
				      <0x01da7c00 0x1dc>,
				      <0x01da7800 0x128>,
				      <0x01da7a00 0x1fc>;
				#phy-cells = <0>;
			};
		};
	};
};

#include "msm8998-pins.dtsi"