1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,gcc-ipq8074.h> 8 9/ { 10 #address-cells = <2>; 11 #size-cells = <2>; 12 13 model = "Qualcomm Technologies, Inc. IPQ8074"; 14 compatible = "qcom,ipq8074"; 15 interrupt-parent = <&intc>; 16 17 clocks { 18 sleep_clk: sleep_clk { 19 compatible = "fixed-clock"; 20 clock-frequency = <32768>; 21 #clock-cells = <0>; 22 }; 23 24 xo: xo { 25 compatible = "fixed-clock"; 26 clock-frequency = <19200000>; 27 #clock-cells = <0>; 28 }; 29 }; 30 31 cpus { 32 #address-cells = <1>; 33 #size-cells = <0>; 34 35 CPU0: cpu@0 { 36 device_type = "cpu"; 37 compatible = "arm,cortex-a53"; 38 reg = <0x0>; 39 next-level-cache = <&L2_0>; 40 enable-method = "psci"; 41 }; 42 43 CPU1: cpu@1 { 44 device_type = "cpu"; 45 compatible = "arm,cortex-a53"; 46 enable-method = "psci"; 47 reg = <0x1>; 48 next-level-cache = <&L2_0>; 49 }; 50 51 CPU2: cpu@2 { 52 device_type = "cpu"; 53 compatible = "arm,cortex-a53"; 54 enable-method = "psci"; 55 reg = <0x2>; 56 next-level-cache = <&L2_0>; 57 }; 58 59 CPU3: cpu@3 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a53"; 62 enable-method = "psci"; 63 reg = <0x3>; 64 next-level-cache = <&L2_0>; 65 }; 66 67 L2_0: l2-cache { 68 compatible = "cache"; 69 cache-level = <2>; 70 cache-unified; 71 }; 72 }; 73 74 pmu { 75 compatible = "arm,cortex-a53-pmu"; 76 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 77 }; 78 79 psci { 80 compatible = "arm,psci-1.0"; 81 method = "smc"; 82 }; 83 84 reserved-memory { 85 #address-cells = <2>; 86 #size-cells = <2>; 87 ranges; 88 89 bootloader@4a600000 { 90 reg = <0x0 0x4a600000 0x0 0x400000>; 91 no-map; 92 }; 93 94 sbl@4aa00000 { 95 reg = <0x0 0x4aa00000 0x0 0x100000>; 96 no-map; 97 }; 98 99 smem@4ab00000 { 100 compatible = "qcom,smem"; 101 reg = <0x0 0x4ab00000 0x0 0x100000>; 102 no-map; 103 104 hwlocks = <&tcsr_mutex 3>; 105 }; 106 107 memory@4ac00000 { 108 reg = <0x0 0x4ac00000 0x0 0x400000>; 109 no-map; 110 }; 111 }; 112 113 firmware { 114 scm { 115 compatible = "qcom,scm-ipq8074", "qcom,scm"; 116 qcom,dload-mode = <&tcsr 0x6100>; 117 }; 118 }; 119 120 soc: soc@0 { 121 #address-cells = <1>; 122 #size-cells = <1>; 123 ranges = <0 0 0 0xffffffff>; 124 compatible = "simple-bus"; 125 126 ssphy_1: phy@58000 { 127 compatible = "qcom,ipq8074-qmp-usb3-phy"; 128 reg = <0x00058000 0x1c4>; 129 #address-cells = <1>; 130 #size-cells = <1>; 131 ranges; 132 133 clocks = <&gcc GCC_USB1_AUX_CLK>, 134 <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, 135 <&xo>; 136 clock-names = "aux", "cfg_ahb", "ref"; 137 138 resets = <&gcc GCC_USB1_PHY_BCR>, 139 <&gcc GCC_USB3PHY_1_PHY_BCR>; 140 reset-names = "phy","common"; 141 status = "disabled"; 142 143 usb1_ssphy: phy@58200 { 144 reg = <0x00058200 0x130>, /* Tx */ 145 <0x00058400 0x200>, /* Rx */ 146 <0x00058800 0x1f8>, /* PCS */ 147 <0x00058600 0x044>; /* PCS misc */ 148 #phy-cells = <0>; 149 #clock-cells = <0>; 150 clocks = <&gcc GCC_USB1_PIPE_CLK>; 151 clock-names = "pipe0"; 152 clock-output-names = "usb3phy_1_cc_pipe_clk"; 153 }; 154 }; 155 156 qusb_phy_1: phy@59000 { 157 compatible = "qcom,ipq8074-qusb2-phy"; 158 reg = <0x00059000 0x180>; 159 #phy-cells = <0>; 160 161 clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, 162 <&xo>; 163 clock-names = "cfg_ahb", "ref"; 164 165 resets = <&gcc GCC_QUSB2_1_PHY_BCR>; 166 status = "disabled"; 167 }; 168 169 ssphy_0: phy@78000 { 170 compatible = "qcom,ipq8074-qmp-usb3-phy"; 171 reg = <0x00078000 0x1c4>; 172 #address-cells = <1>; 173 #size-cells = <1>; 174 ranges; 175 176 clocks = <&gcc GCC_USB0_AUX_CLK>, 177 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, 178 <&xo>; 179 clock-names = "aux", "cfg_ahb", "ref"; 180 181 resets = <&gcc GCC_USB0_PHY_BCR>, 182 <&gcc GCC_USB3PHY_0_PHY_BCR>; 183 reset-names = "phy","common"; 184 status = "disabled"; 185 186 usb0_ssphy: phy@78200 { 187 reg = <0x00078200 0x130>, /* Tx */ 188 <0x00078400 0x200>, /* Rx */ 189 <0x00078800 0x1f8>, /* PCS */ 190 <0x00078600 0x044>; /* PCS misc */ 191 #phy-cells = <0>; 192 #clock-cells = <0>; 193 clocks = <&gcc GCC_USB0_PIPE_CLK>; 194 clock-names = "pipe0"; 195 clock-output-names = "usb3phy_0_cc_pipe_clk"; 196 }; 197 }; 198 199 qusb_phy_0: phy@79000 { 200 compatible = "qcom,ipq8074-qusb2-phy"; 201 reg = <0x00079000 0x180>; 202 #phy-cells = <0>; 203 204 clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, 205 <&xo>; 206 clock-names = "cfg_ahb", "ref"; 207 208 resets = <&gcc GCC_QUSB2_0_PHY_BCR>; 209 status = "disabled"; 210 }; 211 212 pcie_qmp0: phy@84000 { 213 compatible = "qcom,ipq8074-qmp-gen3-pcie-phy"; 214 reg = <0x00084000 0x1bc>; 215 #address-cells = <1>; 216 #size-cells = <1>; 217 ranges; 218 219 clocks = <&gcc GCC_PCIE0_AUX_CLK>, 220 <&gcc GCC_PCIE0_AHB_CLK>; 221 clock-names = "aux", "cfg_ahb"; 222 resets = <&gcc GCC_PCIE0_PHY_BCR>, 223 <&gcc GCC_PCIE0PHY_PHY_BCR>; 224 reset-names = "phy", 225 "common"; 226 status = "disabled"; 227 228 pcie_phy0: phy@84200 { 229 reg = <0x84200 0x16c>, 230 <0x84400 0x200>, 231 <0x84800 0x1f0>, 232 <0x84c00 0xf4>; 233 #phy-cells = <0>; 234 #clock-cells = <0>; 235 clocks = <&gcc GCC_PCIE0_PIPE_CLK>; 236 clock-names = "pipe0"; 237 clock-output-names = "pcie20_phy0_pipe_clk"; 238 }; 239 }; 240 241 pcie_qmp1: phy@8e000 { 242 compatible = "qcom,ipq8074-qmp-pcie-phy"; 243 reg = <0x0008e000 0x1c4>; 244 #address-cells = <1>; 245 #size-cells = <1>; 246 ranges; 247 248 clocks = <&gcc GCC_PCIE1_AUX_CLK>, 249 <&gcc GCC_PCIE1_AHB_CLK>; 250 clock-names = "aux", "cfg_ahb"; 251 resets = <&gcc GCC_PCIE1_PHY_BCR>, 252 <&gcc GCC_PCIE1PHY_PHY_BCR>; 253 reset-names = "phy", 254 "common"; 255 status = "disabled"; 256 257 pcie_phy1: phy@8e200 { 258 reg = <0x8e200 0x130>, 259 <0x8e400 0x200>, 260 <0x8e800 0x1f8>; 261 #phy-cells = <0>; 262 #clock-cells = <0>; 263 clocks = <&gcc GCC_PCIE1_PIPE_CLK>; 264 clock-names = "pipe0"; 265 clock-output-names = "pcie20_phy1_pipe_clk"; 266 }; 267 }; 268 269 mdio: mdio@90000 { 270 compatible = "qcom,ipq8074-mdio", "qcom,ipq4019-mdio"; 271 reg = <0x00090000 0x64>; 272 #address-cells = <1>; 273 #size-cells = <0>; 274 275 clocks = <&gcc GCC_MDIO_AHB_CLK>; 276 clock-names = "gcc_mdio_ahb_clk"; 277 278 status = "disabled"; 279 }; 280 281 qfprom: efuse@a4000 { 282 compatible = "qcom,ipq8074-qfprom", "qcom,qfprom"; 283 reg = <0x000a4000 0x2000>; 284 #address-cells = <1>; 285 #size-cells = <1>; 286 }; 287 288 prng: rng@e3000 { 289 compatible = "qcom,prng-ee"; 290 reg = <0x000e3000 0x1000>; 291 clocks = <&gcc GCC_PRNG_AHB_CLK>; 292 clock-names = "core"; 293 status = "disabled"; 294 }; 295 296 tsens: thermal-sensor@4a9000 { 297 compatible = "qcom,ipq8074-tsens"; 298 reg = <0x4a9000 0x1000>, /* TM */ 299 <0x4a8000 0x1000>; /* SROT */ 300 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 301 interrupt-names = "combined"; 302 #qcom,sensors = <16>; 303 #thermal-sensor-cells = <1>; 304 }; 305 306 cryptobam: dma-controller@704000 { 307 compatible = "qcom,bam-v1.7.0"; 308 reg = <0x00704000 0x20000>; 309 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 310 clocks = <&gcc GCC_CRYPTO_AHB_CLK>; 311 clock-names = "bam_clk"; 312 #dma-cells = <1>; 313 qcom,ee = <1>; 314 qcom,controlled-remotely; 315 status = "disabled"; 316 }; 317 318 crypto: crypto@73a000 { 319 compatible = "qcom,crypto-v5.1"; 320 reg = <0x0073a000 0x6000>; 321 clocks = <&gcc GCC_CRYPTO_AHB_CLK>, 322 <&gcc GCC_CRYPTO_AXI_CLK>, 323 <&gcc GCC_CRYPTO_CLK>; 324 clock-names = "iface", "bus", "core"; 325 dmas = <&cryptobam 2>, <&cryptobam 3>; 326 dma-names = "rx", "tx"; 327 status = "disabled"; 328 }; 329 330 tlmm: pinctrl@1000000 { 331 compatible = "qcom,ipq8074-pinctrl"; 332 reg = <0x01000000 0x300000>; 333 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 334 gpio-controller; 335 gpio-ranges = <&tlmm 0 0 70>; 336 #gpio-cells = <2>; 337 interrupt-controller; 338 #interrupt-cells = <2>; 339 340 serial_4_pins: serial4-state { 341 pins = "gpio23", "gpio24"; 342 function = "blsp4_uart1"; 343 drive-strength = <8>; 344 bias-disable; 345 }; 346 347 i2c_0_pins: i2c-0-state { 348 pins = "gpio42", "gpio43"; 349 function = "blsp1_i2c"; 350 drive-strength = <8>; 351 bias-disable; 352 }; 353 354 spi_0_pins: spi-0-state { 355 pins = "gpio38", "gpio39", "gpio40", "gpio41"; 356 function = "blsp0_spi"; 357 drive-strength = <8>; 358 bias-disable; 359 }; 360 361 hsuart_pins: hsuart-state { 362 pins = "gpio46", "gpio47", "gpio48", "gpio49"; 363 function = "blsp2_uart"; 364 drive-strength = <8>; 365 bias-disable; 366 }; 367 368 qpic_pins: qpic-state { 369 pins = "gpio1", "gpio3", "gpio4", 370 "gpio5", "gpio6", "gpio7", 371 "gpio8", "gpio10", "gpio11", 372 "gpio12", "gpio13", "gpio14", 373 "gpio15", "gpio16", "gpio17"; 374 function = "qpic"; 375 drive-strength = <8>; 376 bias-disable; 377 }; 378 }; 379 380 gcc: gcc@1800000 { 381 compatible = "qcom,gcc-ipq8074"; 382 reg = <0x01800000 0x80000>; 383 clocks = <&xo>, <&sleep_clk>; 384 clock-names = "xo", "sleep_clk"; 385 #clock-cells = <1>; 386 #power-domain-cells = <1>; 387 #reset-cells = <1>; 388 }; 389 390 tcsr_mutex: hwlock@1905000 { 391 compatible = "qcom,tcsr-mutex"; 392 reg = <0x01905000 0x20000>; 393 #hwlock-cells = <1>; 394 }; 395 396 tcsr: syscon@1937000 { 397 compatible = "qcom,tcsr-ipq8074", "syscon"; 398 reg = <0x01937000 0x21000>; 399 }; 400 401 spmi_bus: spmi@200f000 { 402 compatible = "qcom,spmi-pmic-arb"; 403 reg = <0x0200f000 0x001000>, 404 <0x02400000 0x800000>, 405 <0x02c00000 0x800000>, 406 <0x03800000 0x200000>, 407 <0x0200a000 0x000700>; 408 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 409 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 410 interrupt-names = "periph_irq"; 411 qcom,ee = <0>; 412 qcom,channel = <0>; 413 #address-cells = <2>; 414 #size-cells = <0>; 415 interrupt-controller; 416 #interrupt-cells = <4>; 417 }; 418 419 sdhc_1: mmc@7824900 { 420 compatible = "qcom,sdhci-msm-v4"; 421 reg = <0x7824900 0x500>, <0x7824000 0x800>; 422 reg-names = "hc", "core"; 423 424 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 425 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 426 interrupt-names = "hc_irq", "pwr_irq"; 427 428 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 429 <&gcc GCC_SDCC1_APPS_CLK>, 430 <&xo>; 431 clock-names = "iface", "core", "xo"; 432 resets = <&gcc GCC_SDCC1_BCR>; 433 max-frequency = <384000000>; 434 mmc-ddr-1_8v; 435 mmc-hs200-1_8v; 436 mmc-hs400-1_8v; 437 bus-width = <8>; 438 439 status = "disabled"; 440 }; 441 442 blsp_dma: dma-controller@7884000 { 443 compatible = "qcom,bam-v1.7.0"; 444 reg = <0x07884000 0x2b000>; 445 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 446 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 447 clock-names = "bam_clk"; 448 #dma-cells = <1>; 449 qcom,ee = <0>; 450 }; 451 452 blsp1_uart1: serial@78af000 { 453 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 454 reg = <0x078af000 0x200>; 455 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 456 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, 457 <&gcc GCC_BLSP1_AHB_CLK>; 458 clock-names = "core", "iface"; 459 status = "disabled"; 460 }; 461 462 blsp1_uart3: serial@78b1000 { 463 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 464 reg = <0x078b1000 0x200>; 465 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 466 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, 467 <&gcc GCC_BLSP1_AHB_CLK>; 468 clock-names = "core", "iface"; 469 dmas = <&blsp_dma 4>, 470 <&blsp_dma 5>; 471 dma-names = "tx", "rx"; 472 pinctrl-0 = <&hsuart_pins>; 473 pinctrl-names = "default"; 474 status = "disabled"; 475 }; 476 477 blsp1_uart5: serial@78b3000 { 478 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 479 reg = <0x078b3000 0x200>; 480 interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>; 481 clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>, 482 <&gcc GCC_BLSP1_AHB_CLK>; 483 clock-names = "core", "iface"; 484 pinctrl-0 = <&serial_4_pins>; 485 pinctrl-names = "default"; 486 status = "disabled"; 487 }; 488 489 blsp1_spi1: spi@78b5000 { 490 compatible = "qcom,spi-qup-v2.2.1"; 491 #address-cells = <1>; 492 #size-cells = <0>; 493 reg = <0x078b5000 0x600>; 494 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 495 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 496 <&gcc GCC_BLSP1_AHB_CLK>; 497 clock-names = "core", "iface"; 498 dmas = <&blsp_dma 12>, <&blsp_dma 13>; 499 dma-names = "tx", "rx"; 500 pinctrl-0 = <&spi_0_pins>; 501 pinctrl-names = "default"; 502 status = "disabled"; 503 }; 504 505 blsp1_i2c2: i2c@78b6000 { 506 compatible = "qcom,i2c-qup-v2.2.1"; 507 #address-cells = <1>; 508 #size-cells = <0>; 509 reg = <0x078b6000 0x600>; 510 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 511 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 512 <&gcc GCC_BLSP1_AHB_CLK>; 513 clock-names = "core", "iface"; 514 clock-frequency = <400000>; 515 dmas = <&blsp_dma 14>, <&blsp_dma 15>; 516 dma-names = "tx", "rx"; 517 pinctrl-0 = <&i2c_0_pins>; 518 pinctrl-names = "default"; 519 status = "disabled"; 520 }; 521 522 blsp1_i2c3: i2c@78b7000 { 523 compatible = "qcom,i2c-qup-v2.2.1"; 524 #address-cells = <1>; 525 #size-cells = <0>; 526 reg = <0x078b7000 0x600>; 527 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 528 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 529 <&gcc GCC_BLSP1_AHB_CLK>; 530 clock-names = "core", "iface"; 531 clock-frequency = <100000>; 532 dmas = <&blsp_dma 16>, <&blsp_dma 17>; 533 dma-names = "tx", "rx"; 534 status = "disabled"; 535 }; 536 537 blsp1_i2c5: i2c@78b9000 { 538 compatible = "qcom,i2c-qup-v2.2.1"; 539 #address-cells = <1>; 540 #size-cells = <0>; 541 reg = <0x78b9000 0x600>; 542 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 543 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, 544 <&gcc GCC_BLSP1_AHB_CLK>; 545 clock-names = "core", "iface"; 546 clock-frequency = <400000>; 547 dmas = <&blsp_dma 20>, <&blsp_dma 21>; 548 dma-names = "tx", "rx"; 549 status = "disabled"; 550 }; 551 552 blsp1_spi5: spi@78b9000 { 553 compatible = "qcom,spi-qup-v2.2.1"; 554 #address-cells = <1>; 555 #size-cells = <0>; 556 reg = <0x78b9000 0x600>; 557 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 558 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>, 559 <&gcc GCC_BLSP1_AHB_CLK>; 560 clock-names = "core", "iface"; 561 dmas = <&blsp_dma 20>, <&blsp_dma 21>; 562 dma-names = "tx", "rx"; 563 status = "disabled"; 564 }; 565 566 blsp1_i2c6: i2c@78ba000 { 567 compatible = "qcom,i2c-qup-v2.2.1"; 568 #address-cells = <1>; 569 #size-cells = <0>; 570 reg = <0x078ba000 0x600>; 571 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 572 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, 573 <&gcc GCC_BLSP1_AHB_CLK>; 574 clock-names = "core", "iface"; 575 clock-frequency = <100000>; 576 dmas = <&blsp_dma 22>, <&blsp_dma 23>; 577 dma-names = "tx", "rx"; 578 status = "disabled"; 579 }; 580 581 qpic_bam: dma-controller@7984000 { 582 compatible = "qcom,bam-v1.7.0"; 583 reg = <0x07984000 0x1a000>; 584 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 585 clocks = <&gcc GCC_QPIC_AHB_CLK>; 586 clock-names = "bam_clk"; 587 #dma-cells = <1>; 588 qcom,ee = <0>; 589 status = "disabled"; 590 }; 591 592 qpic_nand: nand-controller@79b0000 { 593 compatible = "qcom,ipq8074-nand"; 594 reg = <0x079b0000 0x10000>; 595 #address-cells = <1>; 596 #size-cells = <0>; 597 clocks = <&gcc GCC_QPIC_CLK>, 598 <&gcc GCC_QPIC_AHB_CLK>; 599 clock-names = "core", "aon"; 600 601 dmas = <&qpic_bam 0>, 602 <&qpic_bam 1>, 603 <&qpic_bam 2>; 604 dma-names = "tx", "rx", "cmd"; 605 pinctrl-0 = <&qpic_pins>; 606 pinctrl-names = "default"; 607 status = "disabled"; 608 }; 609 610 usb_0: usb@8af8800 { 611 compatible = "qcom,ipq8074-dwc3", "qcom,dwc3"; 612 reg = <0x08af8800 0x400>; 613 #address-cells = <1>; 614 #size-cells = <1>; 615 ranges; 616 617 clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, 618 <&gcc GCC_USB0_MASTER_CLK>, 619 <&gcc GCC_USB0_SLEEP_CLK>, 620 <&gcc GCC_USB0_MOCK_UTMI_CLK>; 621 clock-names = "cfg_noc", 622 "core", 623 "sleep", 624 "mock_utmi"; 625 626 assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, 627 <&gcc GCC_USB0_MASTER_CLK>, 628 <&gcc GCC_USB0_MOCK_UTMI_CLK>; 629 assigned-clock-rates = <133330000>, 630 <133330000>, 631 <19200000>; 632 633 power-domains = <&gcc USB0_GDSC>; 634 635 resets = <&gcc GCC_USB0_BCR>; 636 status = "disabled"; 637 638 dwc_0: usb@8a00000 { 639 compatible = "snps,dwc3"; 640 reg = <0x8a00000 0xcd00>; 641 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 642 phys = <&qusb_phy_0>, <&usb0_ssphy>; 643 phy-names = "usb2-phy", "usb3-phy"; 644 snps,parkmode-disable-ss-quirk; 645 snps,is-utmi-l1-suspend; 646 snps,hird-threshold = /bits/ 8 <0x0>; 647 snps,dis_u2_susphy_quirk; 648 snps,dis_u3_susphy_quirk; 649 dr_mode = "host"; 650 }; 651 }; 652 653 usb_1: usb@8cf8800 { 654 compatible = "qcom,ipq8074-dwc3", "qcom,dwc3"; 655 reg = <0x08cf8800 0x400>; 656 #address-cells = <1>; 657 #size-cells = <1>; 658 ranges; 659 660 clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>, 661 <&gcc GCC_USB1_MASTER_CLK>, 662 <&gcc GCC_USB1_SLEEP_CLK>, 663 <&gcc GCC_USB1_MOCK_UTMI_CLK>; 664 clock-names = "cfg_noc", 665 "core", 666 "sleep", 667 "mock_utmi"; 668 669 assigned-clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>, 670 <&gcc GCC_USB1_MASTER_CLK>, 671 <&gcc GCC_USB1_MOCK_UTMI_CLK>; 672 assigned-clock-rates = <133330000>, 673 <133330000>, 674 <19200000>; 675 676 power-domains = <&gcc USB1_GDSC>; 677 678 resets = <&gcc GCC_USB1_BCR>; 679 status = "disabled"; 680 681 dwc_1: usb@8c00000 { 682 compatible = "snps,dwc3"; 683 reg = <0x8c00000 0xcd00>; 684 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 685 phys = <&qusb_phy_1>, <&usb1_ssphy>; 686 phy-names = "usb2-phy", "usb3-phy"; 687 snps,parkmode-disable-ss-quirk; 688 snps,is-utmi-l1-suspend; 689 snps,hird-threshold = /bits/ 8 <0x0>; 690 snps,dis_u2_susphy_quirk; 691 snps,dis_u3_susphy_quirk; 692 dr_mode = "host"; 693 }; 694 }; 695 696 intc: interrupt-controller@b000000 { 697 compatible = "qcom,msm-qgic2"; 698 #address-cells = <1>; 699 #size-cells = <1>; 700 interrupt-controller; 701 #interrupt-cells = <3>; 702 reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>; 703 ranges = <0 0xb00a000 0xffd>; 704 705 v2m@0 { 706 compatible = "arm,gic-v2m-frame"; 707 msi-controller; 708 reg = <0x0 0xffd>; 709 }; 710 }; 711 712 watchdog: watchdog@b017000 { 713 compatible = "qcom,kpss-wdt"; 714 reg = <0xb017000 0x1000>; 715 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 716 clocks = <&sleep_clk>; 717 timeout-sec = <30>; 718 }; 719 720 apcs_glb: mailbox@b111000 { 721 compatible = "qcom,ipq8074-apcs-apps-global", 722 "qcom,ipq6018-apcs-apps-global"; 723 reg = <0x0b111000 0x1000>; 724 clocks = <&a53pll>, <&xo>; 725 clock-names = "pll", "xo"; 726 727 #clock-cells = <1>; 728 #mbox-cells = <1>; 729 }; 730 731 a53pll: clock@b116000 { 732 compatible = "qcom,ipq8074-a53pll"; 733 reg = <0x0b116000 0x40>; 734 #clock-cells = <0>; 735 clocks = <&xo>; 736 clock-names = "xo"; 737 }; 738 739 timer@b120000 { 740 #address-cells = <1>; 741 #size-cells = <1>; 742 ranges; 743 compatible = "arm,armv7-timer-mem"; 744 reg = <0x0b120000 0x1000>; 745 746 frame@b120000 { 747 frame-number = <0>; 748 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 749 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 750 reg = <0x0b121000 0x1000>, 751 <0x0b122000 0x1000>; 752 }; 753 754 frame@b123000 { 755 frame-number = <1>; 756 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 757 reg = <0x0b123000 0x1000>; 758 status = "disabled"; 759 }; 760 761 frame@b124000 { 762 frame-number = <2>; 763 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 764 reg = <0x0b124000 0x1000>; 765 status = "disabled"; 766 }; 767 768 frame@b125000 { 769 frame-number = <3>; 770 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 771 reg = <0x0b125000 0x1000>; 772 status = "disabled"; 773 }; 774 775 frame@b126000 { 776 frame-number = <4>; 777 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 778 reg = <0x0b126000 0x1000>; 779 status = "disabled"; 780 }; 781 782 frame@b127000 { 783 frame-number = <5>; 784 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 785 reg = <0x0b127000 0x1000>; 786 status = "disabled"; 787 }; 788 789 frame@b128000 { 790 frame-number = <6>; 791 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 792 reg = <0x0b128000 0x1000>; 793 status = "disabled"; 794 }; 795 }; 796 797 pcie1: pci@10000000 { 798 compatible = "qcom,pcie-ipq8074"; 799 reg = <0x10000000 0xf1d>, 800 <0x10000f20 0xa8>, 801 <0x00088000 0x2000>, 802 <0x10100000 0x1000>; 803 reg-names = "dbi", "elbi", "parf", "config"; 804 device_type = "pci"; 805 linux,pci-domain = <1>; 806 bus-range = <0x00 0xff>; 807 num-lanes = <1>; 808 max-link-speed = <2>; 809 #address-cells = <3>; 810 #size-cells = <2>; 811 812 phys = <&pcie_phy1>; 813 phy-names = "pciephy"; 814 815 ranges = <0x81000000 0x0 0x00000000 0x10200000 0x0 0x10000>, /* I/O */ 816 <0x82000000 0x0 0x10220000 0x10220000 0x0 0xfde0000>; /* MEM */ 817 818 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 819 interrupt-names = "msi"; 820 #interrupt-cells = <1>; 821 interrupt-map-mask = <0 0 0 0x7>; 822 interrupt-map = <0 0 0 1 &intc 0 0 142 823 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 824 <0 0 0 2 &intc 0 0 143 825 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 826 <0 0 0 3 &intc 0 0 144 827 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 828 <0 0 0 4 &intc 0 0 145 829 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 830 831 clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>, 832 <&gcc GCC_PCIE1_AXI_M_CLK>, 833 <&gcc GCC_PCIE1_AXI_S_CLK>, 834 <&gcc GCC_PCIE1_AHB_CLK>, 835 <&gcc GCC_PCIE1_AUX_CLK>; 836 clock-names = "iface", 837 "axi_m", 838 "axi_s", 839 "ahb", 840 "aux"; 841 resets = <&gcc GCC_PCIE1_PIPE_ARES>, 842 <&gcc GCC_PCIE1_SLEEP_ARES>, 843 <&gcc GCC_PCIE1_CORE_STICKY_ARES>, 844 <&gcc GCC_PCIE1_AXI_MASTER_ARES>, 845 <&gcc GCC_PCIE1_AXI_SLAVE_ARES>, 846 <&gcc GCC_PCIE1_AHB_ARES>, 847 <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>; 848 reset-names = "pipe", 849 "sleep", 850 "sticky", 851 "axi_m", 852 "axi_s", 853 "ahb", 854 "axi_m_sticky"; 855 status = "disabled"; 856 }; 857 858 pcie0: pci@20000000 { 859 compatible = "qcom,pcie-ipq8074-gen3"; 860 reg = <0x20000000 0xf1d>, 861 <0x20000f20 0xa8>, 862 <0x20001000 0x1000>, 863 <0x00080000 0x4000>, 864 <0x20100000 0x1000>; 865 reg-names = "dbi", "elbi", "atu", "parf", "config"; 866 device_type = "pci"; 867 linux,pci-domain = <0>; 868 bus-range = <0x00 0xff>; 869 num-lanes = <1>; 870 max-link-speed = <3>; 871 #address-cells = <3>; 872 #size-cells = <2>; 873 874 phys = <&pcie_phy0>; 875 phy-names = "pciephy"; 876 877 ranges = <0x81000000 0x0 0x00000000 0x20200000 0x0 0x10000>, /* I/O */ 878 <0x82000000 0x0 0x20220000 0x20220000 0x0 0xfde0000>; /* MEM */ 879 880 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 881 interrupt-names = "msi"; 882 #interrupt-cells = <1>; 883 interrupt-map-mask = <0 0 0 0x7>; 884 interrupt-map = <0 0 0 1 &intc 0 0 75 885 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 886 <0 0 0 2 &intc 0 0 78 887 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 888 <0 0 0 3 &intc 0 0 79 889 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 890 <0 0 0 4 &intc 0 0 83 891 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 892 893 clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>, 894 <&gcc GCC_PCIE0_AXI_M_CLK>, 895 <&gcc GCC_PCIE0_AXI_S_CLK>, 896 <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>, 897 <&gcc GCC_PCIE0_RCHNG_CLK>; 898 clock-names = "iface", 899 "axi_m", 900 "axi_s", 901 "axi_bridge", 902 "rchng"; 903 904 resets = <&gcc GCC_PCIE0_PIPE_ARES>, 905 <&gcc GCC_PCIE0_SLEEP_ARES>, 906 <&gcc GCC_PCIE0_CORE_STICKY_ARES>, 907 <&gcc GCC_PCIE0_AXI_MASTER_ARES>, 908 <&gcc GCC_PCIE0_AXI_SLAVE_ARES>, 909 <&gcc GCC_PCIE0_AHB_ARES>, 910 <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>, 911 <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>; 912 reset-names = "pipe", 913 "sleep", 914 "sticky", 915 "axi_m", 916 "axi_s", 917 "ahb", 918 "axi_m_sticky", 919 "axi_s_sticky"; 920 status = "disabled"; 921 }; 922 }; 923 924 timer { 925 compatible = "arm,armv8-timer"; 926 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 927 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 928 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 929 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 930 }; 931 932 thermal-zones { 933 nss-top-thermal { 934 polling-delay-passive = <250>; 935 polling-delay = <1000>; 936 937 thermal-sensors = <&tsens 4>; 938 939 trips { 940 nss-top-crit { 941 temperature = <110000>; 942 hysteresis = <1000>; 943 type = "critical"; 944 }; 945 }; 946 }; 947 948 nss0-thermal { 949 polling-delay-passive = <250>; 950 polling-delay = <1000>; 951 952 thermal-sensors = <&tsens 5>; 953 954 trips { 955 nss-0-crit { 956 temperature = <110000>; 957 hysteresis = <1000>; 958 type = "critical"; 959 }; 960 }; 961 }; 962 963 nss1-thermal { 964 polling-delay-passive = <250>; 965 polling-delay = <1000>; 966 967 thermal-sensors = <&tsens 6>; 968 969 trips { 970 nss-1-crit { 971 temperature = <110000>; 972 hysteresis = <1000>; 973 type = "critical"; 974 }; 975 }; 976 }; 977 978 wcss-phya0-thermal { 979 polling-delay-passive = <250>; 980 polling-delay = <1000>; 981 982 thermal-sensors = <&tsens 7>; 983 984 trips { 985 wcss-phya0-crit { 986 temperature = <110000>; 987 hysteresis = <1000>; 988 type = "critical"; 989 }; 990 }; 991 }; 992 993 wcss-phya1-thermal { 994 polling-delay-passive = <250>; 995 polling-delay = <1000>; 996 997 thermal-sensors = <&tsens 8>; 998 999 trips { 1000 wcss-phya1-crit { 1001 temperature = <110000>; 1002 hysteresis = <1000>; 1003 type = "critical"; 1004 }; 1005 }; 1006 }; 1007 1008 cpu0_thermal: cpu0-thermal { 1009 polling-delay-passive = <250>; 1010 polling-delay = <1000>; 1011 1012 thermal-sensors = <&tsens 9>; 1013 1014 trips { 1015 cpu0-crit { 1016 temperature = <110000>; 1017 hysteresis = <1000>; 1018 type = "critical"; 1019 }; 1020 }; 1021 }; 1022 1023 cpu1_thermal: cpu1-thermal { 1024 polling-delay-passive = <250>; 1025 polling-delay = <1000>; 1026 1027 thermal-sensors = <&tsens 10>; 1028 1029 trips { 1030 cpu1-crit { 1031 temperature = <110000>; 1032 hysteresis = <1000>; 1033 type = "critical"; 1034 }; 1035 }; 1036 }; 1037 1038 cpu2_thermal: cpu2-thermal { 1039 polling-delay-passive = <250>; 1040 polling-delay = <1000>; 1041 1042 thermal-sensors = <&tsens 11>; 1043 1044 trips { 1045 cpu2-crit { 1046 temperature = <110000>; 1047 hysteresis = <1000>; 1048 type = "critical"; 1049 }; 1050 }; 1051 }; 1052 1053 cpu3_thermal: cpu3-thermal { 1054 polling-delay-passive = <250>; 1055 polling-delay = <1000>; 1056 1057 thermal-sensors = <&tsens 12>; 1058 1059 trips { 1060 cpu3-crit { 1061 temperature = <110000>; 1062 hysteresis = <1000>; 1063 type = "critical"; 1064 }; 1065 }; 1066 }; 1067 1068 cluster_thermal: cluster-thermal { 1069 polling-delay-passive = <250>; 1070 polling-delay = <1000>; 1071 1072 thermal-sensors = <&tsens 13>; 1073 1074 trips { 1075 cluster-crit { 1076 temperature = <110000>; 1077 hysteresis = <1000>; 1078 type = "critical"; 1079 }; 1080 }; 1081 }; 1082 1083 wcss-phyb0-thermal { 1084 polling-delay-passive = <250>; 1085 polling-delay = <1000>; 1086 1087 thermal-sensors = <&tsens 14>; 1088 1089 trips { 1090 wcss-phyb0-crit { 1091 temperature = <110000>; 1092 hysteresis = <1000>; 1093 type = "critical"; 1094 }; 1095 }; 1096 }; 1097 1098 wcss-phyb1-thermal { 1099 polling-delay-passive = <250>; 1100 polling-delay = <1000>; 1101 1102 thermal-sensors = <&tsens 15>; 1103 1104 trips { 1105 wcss-phyb1-crit { 1106 temperature = <110000>; 1107 hysteresis = <1000>; 1108 type = "critical"; 1109 }; 1110 }; 1111 }; 1112 }; 1113}; 1114