1f1d33c90SKathiravan T// SPDX-License-Identifier: BSD-3-Clause 2f1d33c90SKathiravan T/* 3f1d33c90SKathiravan T * IPQ5332 RDP468 board device tree source 4f1d33c90SKathiravan T * 5f1d33c90SKathiravan T * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. 6f1d33c90SKathiravan T */ 7f1d33c90SKathiravan T 8f1d33c90SKathiravan T/dts-v1/; 9f1d33c90SKathiravan T 10*6d5872f2SSridharan S N#include "ipq5332-rdp-common.dtsi" 11f1d33c90SKathiravan T 12f1d33c90SKathiravan T/ { 13f1d33c90SKathiravan T model = "Qualcomm Technologies, Inc. IPQ5332 MI01.6"; 14f1d33c90SKathiravan T compatible = "qcom,ipq5332-ap-mi01.6", "qcom,ipq5332"; 15f1d33c90SKathiravan T}; 16f1d33c90SKathiravan T 17f1d33c90SKathiravan T&blsp1_spi0 { 18f1d33c90SKathiravan T pinctrl-0 = <&spi_0_data_clk_pins &spi_0_cs_pins>; 19f1d33c90SKathiravan T pinctrl-names = "default"; 20f1d33c90SKathiravan T status = "okay"; 21f1d33c90SKathiravan T 22f1d33c90SKathiravan T flash@0 { 23f1d33c90SKathiravan T compatible = "micron,n25q128a11", "jedec,spi-nor"; 24f1d33c90SKathiravan T reg = <0>; 25f1d33c90SKathiravan T #address-cells = <1>; 26f1d33c90SKathiravan T #size-cells = <1>; 27f1d33c90SKathiravan T spi-max-frequency = <50000000>; 28f1d33c90SKathiravan T }; 29f1d33c90SKathiravan T}; 30f1d33c90SKathiravan T 31f1d33c90SKathiravan T&sdhc { 32f1d33c90SKathiravan T bus-width = <4>; 33f1d33c90SKathiravan T max-frequency = <192000000>; 34f1d33c90SKathiravan T mmc-ddr-1_8v; 35f1d33c90SKathiravan T mmc-hs200-1_8v; 36f1d33c90SKathiravan T non-removable; 37f1d33c90SKathiravan T pinctrl-0 = <&sdc_default_state>; 38f1d33c90SKathiravan T pinctrl-names = "default"; 39f1d33c90SKathiravan T status = "okay"; 40f1d33c90SKathiravan T}; 41f1d33c90SKathiravan T 42f1d33c90SKathiravan T/* PINCTRL */ 43f1d33c90SKathiravan T 44f1d33c90SKathiravan T&tlmm { 45f1d33c90SKathiravan T sdc_default_state: sdc-default-state { 46f1d33c90SKathiravan T clk-pins { 47f1d33c90SKathiravan T pins = "gpio13"; 48f1d33c90SKathiravan T function = "sdc_clk"; 49f1d33c90SKathiravan T drive-strength = <8>; 50f1d33c90SKathiravan T bias-disable; 51f1d33c90SKathiravan T }; 52f1d33c90SKathiravan T 53f1d33c90SKathiravan T cmd-pins { 54f1d33c90SKathiravan T pins = "gpio12"; 55f1d33c90SKathiravan T function = "sdc_cmd"; 56f1d33c90SKathiravan T drive-strength = <8>; 57f1d33c90SKathiravan T bias-pull-up; 58f1d33c90SKathiravan T }; 59f1d33c90SKathiravan T 60f1d33c90SKathiravan T data-pins { 61f1d33c90SKathiravan T pins = "gpio8", "gpio9", "gpio10", "gpio11"; 62f1d33c90SKathiravan T function = "sdc_data"; 63f1d33c90SKathiravan T drive-strength = <8>; 64f1d33c90SKathiravan T bias-pull-up; 65f1d33c90SKathiravan T }; 66f1d33c90SKathiravan T }; 67f1d33c90SKathiravan T 68f1d33c90SKathiravan T spi_0_data_clk_pins: spi-0-data-clk-state { 69f1d33c90SKathiravan T pins = "gpio14", "gpio15", "gpio16"; 70f1d33c90SKathiravan T function = "blsp0_spi"; 71f1d33c90SKathiravan T drive-strength = <2>; 72f1d33c90SKathiravan T bias-pull-down; 73f1d33c90SKathiravan T }; 74f1d33c90SKathiravan T 75f1d33c90SKathiravan T spi_0_cs_pins: spi-0-cs-state { 76f1d33c90SKathiravan T pins = "gpio17"; 77f1d33c90SKathiravan T function = "blsp0_spi"; 78f1d33c90SKathiravan T drive-strength = <2>; 79f1d33c90SKathiravan T bias-pull-up; 80f1d33c90SKathiravan T }; 81f1d33c90SKathiravan T}; 82