163944891SThierry Reding// SPDX-License-Identifier: GPL-2.0 263944891SThierry Reding 363944891SThierry Reding#include <dt-bindings/clock/tegra234-clock.h> 463944891SThierry Reding#include <dt-bindings/interrupt-controller/arm-gic.h> 563944891SThierry Reding#include <dt-bindings/mailbox/tegra186-hsp.h> 663944891SThierry Reding#include <dt-bindings/reset/tegra234-reset.h> 763944891SThierry Reding 863944891SThierry Reding/ { 963944891SThierry Reding compatible = "nvidia,tegra234"; 1063944891SThierry Reding interrupt-parent = <&gic>; 1163944891SThierry Reding #address-cells = <2>; 1263944891SThierry Reding #size-cells = <2>; 1363944891SThierry Reding 1463944891SThierry Reding bus@0 { 1563944891SThierry Reding compatible = "simple-bus"; 1663944891SThierry Reding #address-cells = <1>; 1763944891SThierry Reding #size-cells = <1>; 1863944891SThierry Reding 1963944891SThierry Reding ranges = <0x0 0x0 0x0 0x40000000>; 2063944891SThierry Reding 2163944891SThierry Reding misc@100000 { 2263944891SThierry Reding compatible = "nvidia,tegra234-misc"; 2363944891SThierry Reding reg = <0x00100000 0xf000>, 2463944891SThierry Reding <0x0010f000 0x1000>; 2563944891SThierry Reding status = "okay"; 2663944891SThierry Reding }; 2763944891SThierry Reding 28*f0e12668SThierry Reding gpio: gpio@2200000 { 29*f0e12668SThierry Reding compatible = "nvidia,tegra234-gpio"; 30*f0e12668SThierry Reding reg-names = "security", "gpio"; 31*f0e12668SThierry Reding reg = <0x02200000 0x10000>, 32*f0e12668SThierry Reding <0x02210000 0x10000>; 33*f0e12668SThierry Reding interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 34*f0e12668SThierry Reding <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 35*f0e12668SThierry Reding <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 36*f0e12668SThierry Reding <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, 37*f0e12668SThierry Reding <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 38*f0e12668SThierry Reding <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 39*f0e12668SThierry Reding <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 40*f0e12668SThierry Reding <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 41*f0e12668SThierry Reding <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 42*f0e12668SThierry Reding <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 43*f0e12668SThierry Reding <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 44*f0e12668SThierry Reding <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 45*f0e12668SThierry Reding <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 46*f0e12668SThierry Reding <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 47*f0e12668SThierry Reding <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 48*f0e12668SThierry Reding <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 49*f0e12668SThierry Reding <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 50*f0e12668SThierry Reding <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 51*f0e12668SThierry Reding <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 52*f0e12668SThierry Reding <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 53*f0e12668SThierry Reding <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 54*f0e12668SThierry Reding <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 55*f0e12668SThierry Reding <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 56*f0e12668SThierry Reding <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 57*f0e12668SThierry Reding <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 58*f0e12668SThierry Reding <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 59*f0e12668SThierry Reding <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 60*f0e12668SThierry Reding <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 61*f0e12668SThierry Reding <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 62*f0e12668SThierry Reding <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 63*f0e12668SThierry Reding <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 64*f0e12668SThierry Reding <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 65*f0e12668SThierry Reding <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 66*f0e12668SThierry Reding <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 67*f0e12668SThierry Reding <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 68*f0e12668SThierry Reding <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 69*f0e12668SThierry Reding <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 70*f0e12668SThierry Reding <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 71*f0e12668SThierry Reding <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 72*f0e12668SThierry Reding <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 73*f0e12668SThierry Reding <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 74*f0e12668SThierry Reding <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 75*f0e12668SThierry Reding <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 76*f0e12668SThierry Reding <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 77*f0e12668SThierry Reding <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 78*f0e12668SThierry Reding <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 79*f0e12668SThierry Reding <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 80*f0e12668SThierry Reding <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 81*f0e12668SThierry Reding #interrupt-cells = <2>; 82*f0e12668SThierry Reding interrupt-controller; 83*f0e12668SThierry Reding #gpio-cells = <2>; 84*f0e12668SThierry Reding gpio-controller; 85*f0e12668SThierry Reding }; 86*f0e12668SThierry Reding 8763944891SThierry Reding uarta: serial@3100000 { 8863944891SThierry Reding compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart"; 8963944891SThierry Reding reg = <0x03100000 0x10000>; 9063944891SThierry Reding interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 9163944891SThierry Reding clocks = <&bpmp TEGRA234_CLK_UARTA>; 9263944891SThierry Reding clock-names = "serial"; 9363944891SThierry Reding resets = <&bpmp TEGRA234_RESET_UARTA>; 9463944891SThierry Reding reset-names = "serial"; 9563944891SThierry Reding status = "disabled"; 9663944891SThierry Reding }; 9763944891SThierry Reding 9863944891SThierry Reding mmc@3460000 { 9963944891SThierry Reding compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci"; 10063944891SThierry Reding reg = <0x03460000 0x20000>; 10163944891SThierry Reding interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 102e086d82dSMikko Perttunen clocks = <&bpmp TEGRA234_CLK_SDMMC4>, 103e086d82dSMikko Perttunen <&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>; 104e086d82dSMikko Perttunen clock-names = "sdhci", "tmclk"; 105e086d82dSMikko Perttunen assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC4>, 106e086d82dSMikko Perttunen <&bpmp TEGRA234_CLK_PLLC4>; 107e086d82dSMikko Perttunen assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4>; 10863944891SThierry Reding resets = <&bpmp TEGRA234_RESET_SDMMC4>; 10963944891SThierry Reding reset-names = "sdhci"; 110e086d82dSMikko Perttunen nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 111e086d82dSMikko Perttunen nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 112e086d82dSMikko Perttunen nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 113e086d82dSMikko Perttunen nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; 114e086d82dSMikko Perttunen nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 115e086d82dSMikko Perttunen nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>; 116e086d82dSMikko Perttunen nvidia,default-tap = <0x8>; 117e086d82dSMikko Perttunen nvidia,default-trim = <0x14>; 118e086d82dSMikko Perttunen nvidia,dqs-trim = <40>; 119e086d82dSMikko Perttunen supports-cqe; 12063944891SThierry Reding status = "disabled"; 12163944891SThierry Reding }; 12263944891SThierry Reding 12363944891SThierry Reding fuse@3810000 { 12463944891SThierry Reding compatible = "nvidia,tegra234-efuse"; 12563944891SThierry Reding reg = <0x03810000 0x10000>; 12663944891SThierry Reding clocks = <&bpmp TEGRA234_CLK_FUSE>; 12763944891SThierry Reding clock-names = "fuse"; 12863944891SThierry Reding }; 12963944891SThierry Reding 13063944891SThierry Reding hsp_top0: hsp@3c00000 { 13163944891SThierry Reding compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; 13263944891SThierry Reding reg = <0x03c00000 0xa0000>; 13363944891SThierry Reding interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 13463944891SThierry Reding <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 13563944891SThierry Reding <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 13663944891SThierry Reding <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 13763944891SThierry Reding <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 13863944891SThierry Reding <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 13963944891SThierry Reding <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 14063944891SThierry Reding <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 14163944891SThierry Reding <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 14263944891SThierry Reding interrupt-names = "doorbell", "shared0", "shared1", "shared2", 14363944891SThierry Reding "shared3", "shared4", "shared5", "shared6", 14463944891SThierry Reding "shared7"; 14563944891SThierry Reding #mbox-cells = <2>; 14663944891SThierry Reding }; 14763944891SThierry Reding 14863944891SThierry Reding hsp_aon: hsp@c150000 { 14963944891SThierry Reding compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; 15063944891SThierry Reding reg = <0x0c150000 0x90000>; 15163944891SThierry Reding interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 15263944891SThierry Reding <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 15363944891SThierry Reding <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 15463944891SThierry Reding <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 15563944891SThierry Reding /* 15663944891SThierry Reding * Shared interrupt 0 is routed only to AON/SPE, so 15763944891SThierry Reding * we only have 4 shared interrupts for the CCPLEX. 15863944891SThierry Reding */ 15963944891SThierry Reding interrupt-names = "shared1", "shared2", "shared3", "shared4"; 16063944891SThierry Reding #mbox-cells = <2>; 16163944891SThierry Reding }; 16263944891SThierry Reding 16363944891SThierry Reding rtc@c2a0000 { 16463944891SThierry Reding compatible = "nvidia,tegra234-rtc", "nvidia,tegra20-rtc"; 16563944891SThierry Reding reg = <0x0c2a0000 0x10000>; 16663944891SThierry Reding interrupt-parent = <&pmc>; 16763944891SThierry Reding interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 168e537addeSMikko Perttunen clocks = <&bpmp TEGRA234_CLK_CLK_32K>; 169e537addeSMikko Perttunen clock-names = "rtc"; 17063944891SThierry Reding status = "disabled"; 17163944891SThierry Reding }; 17263944891SThierry Reding 173*f0e12668SThierry Reding gpio_aon: gpio@c2f0000 { 174*f0e12668SThierry Reding compatible = "nvidia,tegra234-gpio-aon"; 175*f0e12668SThierry Reding reg-names = "security", "gpio"; 176*f0e12668SThierry Reding reg = <0x0c2f0000 0x1000>, 177*f0e12668SThierry Reding <0x0c2f1000 0x1000>; 178*f0e12668SThierry Reding interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 179*f0e12668SThierry Reding <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 180*f0e12668SThierry Reding <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 181*f0e12668SThierry Reding <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 182*f0e12668SThierry Reding #interrupt-cells = <2>; 183*f0e12668SThierry Reding interrupt-controller; 184*f0e12668SThierry Reding #gpio-cells = <2>; 185*f0e12668SThierry Reding gpio-controller; 186*f0e12668SThierry Reding }; 187*f0e12668SThierry Reding 18863944891SThierry Reding pmc: pmc@c360000 { 18963944891SThierry Reding compatible = "nvidia,tegra234-pmc"; 19063944891SThierry Reding reg = <0x0c360000 0x10000>, 19163944891SThierry Reding <0x0c370000 0x10000>, 19263944891SThierry Reding <0x0c380000 0x10000>, 19363944891SThierry Reding <0x0c390000 0x10000>, 19463944891SThierry Reding <0x0c3a0000 0x10000>; 19563944891SThierry Reding reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 19663944891SThierry Reding 19763944891SThierry Reding #interrupt-cells = <2>; 19863944891SThierry Reding interrupt-controller; 19963944891SThierry Reding }; 20063944891SThierry Reding 20163944891SThierry Reding gic: interrupt-controller@f400000 { 20263944891SThierry Reding compatible = "arm,gic-v3"; 20363944891SThierry Reding reg = <0x0f400000 0x010000>, /* GICD */ 20463944891SThierry Reding <0x0f440000 0x200000>; /* GICR */ 20563944891SThierry Reding interrupt-parent = <&gic>; 20663944891SThierry Reding interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 20763944891SThierry Reding 20863944891SThierry Reding #redistributor-regions = <1>; 20963944891SThierry Reding #interrupt-cells = <3>; 21063944891SThierry Reding interrupt-controller; 21163944891SThierry Reding }; 21263944891SThierry Reding }; 21363944891SThierry Reding 2147fa30752SThierry Reding sram@40000000 { 21563944891SThierry Reding compatible = "nvidia,tegra234-sysram", "mmio-sram"; 21698094be1SMikko Perttunen reg = <0x0 0x40000000 0x0 0x80000>; 21763944891SThierry Reding #address-cells = <1>; 21863944891SThierry Reding #size-cells = <1>; 21998094be1SMikko Perttunen ranges = <0x0 0x0 0x40000000 0x80000>; 22063944891SThierry Reding 22198094be1SMikko Perttunen cpu_bpmp_tx: sram@70000 { 22298094be1SMikko Perttunen reg = <0x70000 0x1000>; 22363944891SThierry Reding label = "cpu-bpmp-tx"; 22463944891SThierry Reding pool; 22563944891SThierry Reding }; 22663944891SThierry Reding 22798094be1SMikko Perttunen cpu_bpmp_rx: sram@71000 { 22898094be1SMikko Perttunen reg = <0x71000 0x1000>; 22963944891SThierry Reding label = "cpu-bpmp-rx"; 23063944891SThierry Reding pool; 23163944891SThierry Reding }; 23263944891SThierry Reding }; 23363944891SThierry Reding 23463944891SThierry Reding bpmp: bpmp { 23563944891SThierry Reding compatible = "nvidia,tegra234-bpmp", "nvidia,tegra186-bpmp"; 23663944891SThierry Reding mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 23763944891SThierry Reding TEGRA_HSP_DB_MASTER_BPMP>; 2387fa30752SThierry Reding shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; 23963944891SThierry Reding #clock-cells = <1>; 24063944891SThierry Reding #reset-cells = <1>; 24163944891SThierry Reding #power-domain-cells = <1>; 24263944891SThierry Reding 24363944891SThierry Reding bpmp_i2c: i2c { 24463944891SThierry Reding compatible = "nvidia,tegra186-bpmp-i2c"; 24563944891SThierry Reding nvidia,bpmp-bus-id = <5>; 24663944891SThierry Reding #address-cells = <1>; 24763944891SThierry Reding #size-cells = <0>; 24863944891SThierry Reding }; 24963944891SThierry Reding }; 25063944891SThierry Reding 25163944891SThierry Reding cpus { 25263944891SThierry Reding #address-cells = <1>; 25363944891SThierry Reding #size-cells = <0>; 25463944891SThierry Reding 25563944891SThierry Reding cpu@0 { 25663944891SThierry Reding device_type = "cpu"; 25763944891SThierry Reding reg = <0x000>; 25863944891SThierry Reding 25963944891SThierry Reding enable-method = "psci"; 26063944891SThierry Reding }; 26163944891SThierry Reding }; 26263944891SThierry Reding 26363944891SThierry Reding psci { 26463944891SThierry Reding compatible = "arm,psci-1.0"; 26563944891SThierry Reding status = "okay"; 26663944891SThierry Reding method = "smc"; 26763944891SThierry Reding }; 26863944891SThierry Reding 26906ad2ec4SMikko Perttunen tcu: serial { 27006ad2ec4SMikko Perttunen compatible = "nvidia,tegra234-tcu", "nvidia,tegra194-tcu"; 27106ad2ec4SMikko Perttunen mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 27206ad2ec4SMikko Perttunen <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 27306ad2ec4SMikko Perttunen mbox-names = "rx", "tx"; 27406ad2ec4SMikko Perttunen status = "disabled"; 27506ad2ec4SMikko Perttunen }; 27606ad2ec4SMikko Perttunen 27763944891SThierry Reding timer { 27863944891SThierry Reding compatible = "arm,armv8-timer"; 27963944891SThierry Reding interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 28063944891SThierry Reding <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 28163944891SThierry Reding <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 28263944891SThierry Reding <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 28363944891SThierry Reding interrupt-parent = <&gic>; 28463944891SThierry Reding always-on; 28563944891SThierry Reding }; 28663944891SThierry Reding}; 287