163944891SThierry Reding// SPDX-License-Identifier: GPL-2.0 263944891SThierry Reding 363944891SThierry Reding#include <dt-bindings/clock/tegra234-clock.h> 463944891SThierry Reding#include <dt-bindings/interrupt-controller/arm-gic.h> 563944891SThierry Reding#include <dt-bindings/mailbox/tegra186-hsp.h> 6*eed280dfSThierry Reding#include <dt-bindings/memory/tegra234-mc.h> 763944891SThierry Reding#include <dt-bindings/reset/tegra234-reset.h> 863944891SThierry Reding 963944891SThierry Reding/ { 1063944891SThierry Reding compatible = "nvidia,tegra234"; 1163944891SThierry Reding interrupt-parent = <&gic>; 1263944891SThierry Reding #address-cells = <2>; 1363944891SThierry Reding #size-cells = <2>; 1463944891SThierry Reding 1563944891SThierry Reding bus@0 { 1663944891SThierry Reding compatible = "simple-bus"; 1763944891SThierry Reding #address-cells = <1>; 1863944891SThierry Reding #size-cells = <1>; 1963944891SThierry Reding 2063944891SThierry Reding ranges = <0x0 0x0 0x0 0x40000000>; 2163944891SThierry Reding 2263944891SThierry Reding misc@100000 { 2363944891SThierry Reding compatible = "nvidia,tegra234-misc"; 2463944891SThierry Reding reg = <0x00100000 0xf000>, 2563944891SThierry Reding <0x0010f000 0x1000>; 2663944891SThierry Reding status = "okay"; 2763944891SThierry Reding }; 2863944891SThierry Reding 29f0e12668SThierry Reding gpio: gpio@2200000 { 30f0e12668SThierry Reding compatible = "nvidia,tegra234-gpio"; 31f0e12668SThierry Reding reg-names = "security", "gpio"; 32f0e12668SThierry Reding reg = <0x02200000 0x10000>, 33f0e12668SThierry Reding <0x02210000 0x10000>; 34f0e12668SThierry Reding interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 35f0e12668SThierry Reding <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 36f0e12668SThierry Reding <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 37f0e12668SThierry Reding <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, 38f0e12668SThierry Reding <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 39f0e12668SThierry Reding <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 40f0e12668SThierry Reding <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 41f0e12668SThierry Reding <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 42f0e12668SThierry Reding <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 43f0e12668SThierry Reding <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 44f0e12668SThierry Reding <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 45f0e12668SThierry Reding <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 46f0e12668SThierry Reding <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 47f0e12668SThierry Reding <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 48f0e12668SThierry Reding <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 49f0e12668SThierry Reding <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 50f0e12668SThierry Reding <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 51f0e12668SThierry Reding <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 52f0e12668SThierry Reding <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 53f0e12668SThierry Reding <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 54f0e12668SThierry Reding <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 55f0e12668SThierry Reding <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 56f0e12668SThierry Reding <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 57f0e12668SThierry Reding <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 58f0e12668SThierry Reding <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 59f0e12668SThierry Reding <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 60f0e12668SThierry Reding <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 61f0e12668SThierry Reding <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 62f0e12668SThierry Reding <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 63f0e12668SThierry Reding <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 64f0e12668SThierry Reding <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 65f0e12668SThierry Reding <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 66f0e12668SThierry Reding <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 67f0e12668SThierry Reding <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 68f0e12668SThierry Reding <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 69f0e12668SThierry Reding <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 70f0e12668SThierry Reding <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 71f0e12668SThierry Reding <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 72f0e12668SThierry Reding <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 73f0e12668SThierry Reding <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 74f0e12668SThierry Reding <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 75f0e12668SThierry Reding <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 76f0e12668SThierry Reding <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 77f0e12668SThierry Reding <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 78f0e12668SThierry Reding <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 79f0e12668SThierry Reding <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 80f0e12668SThierry Reding <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 81f0e12668SThierry Reding <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 82f0e12668SThierry Reding #interrupt-cells = <2>; 83f0e12668SThierry Reding interrupt-controller; 84f0e12668SThierry Reding #gpio-cells = <2>; 85f0e12668SThierry Reding gpio-controller; 86f0e12668SThierry Reding }; 87f0e12668SThierry Reding 88*eed280dfSThierry Reding mc: memory-controller@2c00000 { 89*eed280dfSThierry Reding compatible = "nvidia,tegra234-mc"; 90*eed280dfSThierry Reding reg = <0x02c00000 0x100000>, 91*eed280dfSThierry Reding <0x02b80000 0x040000>, 92*eed280dfSThierry Reding <0x01700000 0x100000>; 93*eed280dfSThierry Reding interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 94*eed280dfSThierry Reding #interconnect-cells = <1>; 95*eed280dfSThierry Reding status = "okay"; 96*eed280dfSThierry Reding 97*eed280dfSThierry Reding #address-cells = <2>; 98*eed280dfSThierry Reding #size-cells = <2>; 99*eed280dfSThierry Reding 100*eed280dfSThierry Reding ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>, 101*eed280dfSThierry Reding <0x02b80000 0x0 0x02b80000 0x0 0x040000>, 102*eed280dfSThierry Reding <0x02c00000 0x0 0x02c00000 0x0 0x100000>; 103*eed280dfSThierry Reding 104*eed280dfSThierry Reding /* 105*eed280dfSThierry Reding * Bit 39 of addresses passing through the memory 106*eed280dfSThierry Reding * controller selects the XBAR format used when memory 107*eed280dfSThierry Reding * is accessed. This is used to transparently access 108*eed280dfSThierry Reding * memory in the XBAR format used by the discrete GPU 109*eed280dfSThierry Reding * (bit 39 set) or Tegra (bit 39 clear). 110*eed280dfSThierry Reding * 111*eed280dfSThierry Reding * As a consequence, the operating system must ensure 112*eed280dfSThierry Reding * that bit 39 is never used implicitly, for example 113*eed280dfSThierry Reding * via an I/O virtual address mapping of an IOMMU. If 114*eed280dfSThierry Reding * devices require access to the XBAR switch, their 115*eed280dfSThierry Reding * drivers must set this bit explicitly. 116*eed280dfSThierry Reding * 117*eed280dfSThierry Reding * Limit the DMA range for memory clients to [38:0]. 118*eed280dfSThierry Reding */ 119*eed280dfSThierry Reding dma-ranges = <0x0 0x0 0x0 0x80 0x0>; 120*eed280dfSThierry Reding 121*eed280dfSThierry Reding emc: external-memory-controller@2c60000 { 122*eed280dfSThierry Reding compatible = "nvidia,tegra234-emc"; 123*eed280dfSThierry Reding reg = <0x0 0x02c60000 0x0 0x90000>, 124*eed280dfSThierry Reding <0x0 0x01780000 0x0 0x80000>; 125*eed280dfSThierry Reding interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 126*eed280dfSThierry Reding clocks = <&bpmp TEGRA234_CLK_EMC>; 127*eed280dfSThierry Reding clock-names = "emc"; 128*eed280dfSThierry Reding status = "okay"; 129*eed280dfSThierry Reding 130*eed280dfSThierry Reding #interconnect-cells = <0>; 131*eed280dfSThierry Reding 132*eed280dfSThierry Reding nvidia,bpmp = <&bpmp>; 133*eed280dfSThierry Reding }; 134*eed280dfSThierry Reding }; 135*eed280dfSThierry Reding 13663944891SThierry Reding uarta: serial@3100000 { 13763944891SThierry Reding compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart"; 13863944891SThierry Reding reg = <0x03100000 0x10000>; 13963944891SThierry Reding interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 14063944891SThierry Reding clocks = <&bpmp TEGRA234_CLK_UARTA>; 14163944891SThierry Reding clock-names = "serial"; 14263944891SThierry Reding resets = <&bpmp TEGRA234_RESET_UARTA>; 14363944891SThierry Reding reset-names = "serial"; 14463944891SThierry Reding status = "disabled"; 14563944891SThierry Reding }; 14663944891SThierry Reding 14763944891SThierry Reding mmc@3460000 { 14863944891SThierry Reding compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci"; 14963944891SThierry Reding reg = <0x03460000 0x20000>; 15063944891SThierry Reding interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 151e086d82dSMikko Perttunen clocks = <&bpmp TEGRA234_CLK_SDMMC4>, 152e086d82dSMikko Perttunen <&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>; 153e086d82dSMikko Perttunen clock-names = "sdhci", "tmclk"; 154e086d82dSMikko Perttunen assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC4>, 155e086d82dSMikko Perttunen <&bpmp TEGRA234_CLK_PLLC4>; 156e086d82dSMikko Perttunen assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4>; 15763944891SThierry Reding resets = <&bpmp TEGRA234_RESET_SDMMC4>; 15863944891SThierry Reding reset-names = "sdhci"; 159e086d82dSMikko Perttunen nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 160e086d82dSMikko Perttunen nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 161e086d82dSMikko Perttunen nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 162e086d82dSMikko Perttunen nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; 163e086d82dSMikko Perttunen nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 164e086d82dSMikko Perttunen nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>; 165e086d82dSMikko Perttunen nvidia,default-tap = <0x8>; 166e086d82dSMikko Perttunen nvidia,default-trim = <0x14>; 167e086d82dSMikko Perttunen nvidia,dqs-trim = <40>; 168e086d82dSMikko Perttunen supports-cqe; 16963944891SThierry Reding status = "disabled"; 17063944891SThierry Reding }; 17163944891SThierry Reding 17263944891SThierry Reding fuse@3810000 { 17363944891SThierry Reding compatible = "nvidia,tegra234-efuse"; 17463944891SThierry Reding reg = <0x03810000 0x10000>; 17563944891SThierry Reding clocks = <&bpmp TEGRA234_CLK_FUSE>; 17663944891SThierry Reding clock-names = "fuse"; 17763944891SThierry Reding }; 17863944891SThierry Reding 17963944891SThierry Reding hsp_top0: hsp@3c00000 { 18063944891SThierry Reding compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; 18163944891SThierry Reding reg = <0x03c00000 0xa0000>; 18263944891SThierry Reding interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 18363944891SThierry Reding <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 18463944891SThierry Reding <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 18563944891SThierry Reding <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 18663944891SThierry Reding <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 18763944891SThierry Reding <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 18863944891SThierry Reding <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 18963944891SThierry Reding <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 19063944891SThierry Reding <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 19163944891SThierry Reding interrupt-names = "doorbell", "shared0", "shared1", "shared2", 19263944891SThierry Reding "shared3", "shared4", "shared5", "shared6", 19363944891SThierry Reding "shared7"; 19463944891SThierry Reding #mbox-cells = <2>; 19563944891SThierry Reding }; 19663944891SThierry Reding 19763944891SThierry Reding hsp_aon: hsp@c150000 { 19863944891SThierry Reding compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; 19963944891SThierry Reding reg = <0x0c150000 0x90000>; 20063944891SThierry Reding interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 20163944891SThierry Reding <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 20263944891SThierry Reding <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 20363944891SThierry Reding <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 20463944891SThierry Reding /* 20563944891SThierry Reding * Shared interrupt 0 is routed only to AON/SPE, so 20663944891SThierry Reding * we only have 4 shared interrupts for the CCPLEX. 20763944891SThierry Reding */ 20863944891SThierry Reding interrupt-names = "shared1", "shared2", "shared3", "shared4"; 20963944891SThierry Reding #mbox-cells = <2>; 21063944891SThierry Reding }; 21163944891SThierry Reding 21263944891SThierry Reding rtc@c2a0000 { 21363944891SThierry Reding compatible = "nvidia,tegra234-rtc", "nvidia,tegra20-rtc"; 21463944891SThierry Reding reg = <0x0c2a0000 0x10000>; 21563944891SThierry Reding interrupt-parent = <&pmc>; 21663944891SThierry Reding interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 217e537addeSMikko Perttunen clocks = <&bpmp TEGRA234_CLK_CLK_32K>; 218e537addeSMikko Perttunen clock-names = "rtc"; 21963944891SThierry Reding status = "disabled"; 22063944891SThierry Reding }; 22163944891SThierry Reding 222f0e12668SThierry Reding gpio_aon: gpio@c2f0000 { 223f0e12668SThierry Reding compatible = "nvidia,tegra234-gpio-aon"; 224f0e12668SThierry Reding reg-names = "security", "gpio"; 225f0e12668SThierry Reding reg = <0x0c2f0000 0x1000>, 226f0e12668SThierry Reding <0x0c2f1000 0x1000>; 227f0e12668SThierry Reding interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 228f0e12668SThierry Reding <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 229f0e12668SThierry Reding <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 230f0e12668SThierry Reding <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 231f0e12668SThierry Reding #interrupt-cells = <2>; 232f0e12668SThierry Reding interrupt-controller; 233f0e12668SThierry Reding #gpio-cells = <2>; 234f0e12668SThierry Reding gpio-controller; 235f0e12668SThierry Reding }; 236f0e12668SThierry Reding 23763944891SThierry Reding pmc: pmc@c360000 { 23863944891SThierry Reding compatible = "nvidia,tegra234-pmc"; 23963944891SThierry Reding reg = <0x0c360000 0x10000>, 24063944891SThierry Reding <0x0c370000 0x10000>, 24163944891SThierry Reding <0x0c380000 0x10000>, 24263944891SThierry Reding <0x0c390000 0x10000>, 24363944891SThierry Reding <0x0c3a0000 0x10000>; 24463944891SThierry Reding reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 24563944891SThierry Reding 24663944891SThierry Reding #interrupt-cells = <2>; 24763944891SThierry Reding interrupt-controller; 24863944891SThierry Reding }; 24963944891SThierry Reding 25063944891SThierry Reding gic: interrupt-controller@f400000 { 25163944891SThierry Reding compatible = "arm,gic-v3"; 25263944891SThierry Reding reg = <0x0f400000 0x010000>, /* GICD */ 25363944891SThierry Reding <0x0f440000 0x200000>; /* GICR */ 25463944891SThierry Reding interrupt-parent = <&gic>; 25563944891SThierry Reding interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 25663944891SThierry Reding 25763944891SThierry Reding #redistributor-regions = <1>; 25863944891SThierry Reding #interrupt-cells = <3>; 25963944891SThierry Reding interrupt-controller; 26063944891SThierry Reding }; 26163944891SThierry Reding }; 26263944891SThierry Reding 2637fa30752SThierry Reding sram@40000000 { 26463944891SThierry Reding compatible = "nvidia,tegra234-sysram", "mmio-sram"; 26598094be1SMikko Perttunen reg = <0x0 0x40000000 0x0 0x80000>; 26663944891SThierry Reding #address-cells = <1>; 26763944891SThierry Reding #size-cells = <1>; 26898094be1SMikko Perttunen ranges = <0x0 0x0 0x40000000 0x80000>; 26963944891SThierry Reding 27098094be1SMikko Perttunen cpu_bpmp_tx: sram@70000 { 27198094be1SMikko Perttunen reg = <0x70000 0x1000>; 27263944891SThierry Reding label = "cpu-bpmp-tx"; 27363944891SThierry Reding pool; 27463944891SThierry Reding }; 27563944891SThierry Reding 27698094be1SMikko Perttunen cpu_bpmp_rx: sram@71000 { 27798094be1SMikko Perttunen reg = <0x71000 0x1000>; 27863944891SThierry Reding label = "cpu-bpmp-rx"; 27963944891SThierry Reding pool; 28063944891SThierry Reding }; 28163944891SThierry Reding }; 28263944891SThierry Reding 28363944891SThierry Reding bpmp: bpmp { 28463944891SThierry Reding compatible = "nvidia,tegra234-bpmp", "nvidia,tegra186-bpmp"; 28563944891SThierry Reding mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 28663944891SThierry Reding TEGRA_HSP_DB_MASTER_BPMP>; 2877fa30752SThierry Reding shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; 28863944891SThierry Reding #clock-cells = <1>; 28963944891SThierry Reding #reset-cells = <1>; 29063944891SThierry Reding #power-domain-cells = <1>; 29163944891SThierry Reding 29263944891SThierry Reding bpmp_i2c: i2c { 29363944891SThierry Reding compatible = "nvidia,tegra186-bpmp-i2c"; 29463944891SThierry Reding nvidia,bpmp-bus-id = <5>; 29563944891SThierry Reding #address-cells = <1>; 29663944891SThierry Reding #size-cells = <0>; 29763944891SThierry Reding }; 29863944891SThierry Reding }; 29963944891SThierry Reding 30063944891SThierry Reding cpus { 30163944891SThierry Reding #address-cells = <1>; 30263944891SThierry Reding #size-cells = <0>; 30363944891SThierry Reding 304a12cf5c3SThierry Reding cpu0_0: cpu@0 { 305a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 30663944891SThierry Reding device_type = "cpu"; 307a12cf5c3SThierry Reding reg = <0x00000>; 30863944891SThierry Reding 30963944891SThierry Reding enable-method = "psci"; 310a12cf5c3SThierry Reding 311a12cf5c3SThierry Reding i-cache-size = <65536>; 312a12cf5c3SThierry Reding i-cache-line-size = <64>; 313a12cf5c3SThierry Reding i-cache-sets = <256>; 314a12cf5c3SThierry Reding d-cache-size = <65536>; 315a12cf5c3SThierry Reding d-cache-line-size = <64>; 316a12cf5c3SThierry Reding d-cache-sets = <256>; 317a12cf5c3SThierry Reding next-level-cache = <&l2c0_0>; 31863944891SThierry Reding }; 319a12cf5c3SThierry Reding 320a12cf5c3SThierry Reding cpu0_1: cpu@100 { 321a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 322a12cf5c3SThierry Reding device_type = "cpu"; 323a12cf5c3SThierry Reding reg = <0x00100>; 324a12cf5c3SThierry Reding 325a12cf5c3SThierry Reding enable-method = "psci"; 326a12cf5c3SThierry Reding 327a12cf5c3SThierry Reding i-cache-size = <65536>; 328a12cf5c3SThierry Reding i-cache-line-size = <64>; 329a12cf5c3SThierry Reding i-cache-sets = <256>; 330a12cf5c3SThierry Reding d-cache-size = <65536>; 331a12cf5c3SThierry Reding d-cache-line-size = <64>; 332a12cf5c3SThierry Reding d-cache-sets = <256>; 333a12cf5c3SThierry Reding next-level-cache = <&l2c0_1>; 334a12cf5c3SThierry Reding }; 335a12cf5c3SThierry Reding 336a12cf5c3SThierry Reding cpu0_2: cpu@200 { 337a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 338a12cf5c3SThierry Reding device_type = "cpu"; 339a12cf5c3SThierry Reding reg = <0x00200>; 340a12cf5c3SThierry Reding 341a12cf5c3SThierry Reding enable-method = "psci"; 342a12cf5c3SThierry Reding 343a12cf5c3SThierry Reding i-cache-size = <65536>; 344a12cf5c3SThierry Reding i-cache-line-size = <64>; 345a12cf5c3SThierry Reding i-cache-sets = <256>; 346a12cf5c3SThierry Reding d-cache-size = <65536>; 347a12cf5c3SThierry Reding d-cache-line-size = <64>; 348a12cf5c3SThierry Reding d-cache-sets = <256>; 349a12cf5c3SThierry Reding next-level-cache = <&l2c0_2>; 350a12cf5c3SThierry Reding }; 351a12cf5c3SThierry Reding 352a12cf5c3SThierry Reding cpu0_3: cpu@300 { 353a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 354a12cf5c3SThierry Reding device_type = "cpu"; 355a12cf5c3SThierry Reding reg = <0x00300>; 356a12cf5c3SThierry Reding 357a12cf5c3SThierry Reding enable-method = "psci"; 358a12cf5c3SThierry Reding 359a12cf5c3SThierry Reding i-cache-size = <65536>; 360a12cf5c3SThierry Reding i-cache-line-size = <64>; 361a12cf5c3SThierry Reding i-cache-sets = <256>; 362a12cf5c3SThierry Reding d-cache-size = <65536>; 363a12cf5c3SThierry Reding d-cache-line-size = <64>; 364a12cf5c3SThierry Reding d-cache-sets = <256>; 365a12cf5c3SThierry Reding next-level-cache = <&l2c0_3>; 366a12cf5c3SThierry Reding }; 367a12cf5c3SThierry Reding 368a12cf5c3SThierry Reding cpu1_0: cpu@10000 { 369a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 370a12cf5c3SThierry Reding device_type = "cpu"; 371a12cf5c3SThierry Reding reg = <0x10000>; 372a12cf5c3SThierry Reding 373a12cf5c3SThierry Reding enable-method = "psci"; 374a12cf5c3SThierry Reding 375a12cf5c3SThierry Reding i-cache-size = <65536>; 376a12cf5c3SThierry Reding i-cache-line-size = <64>; 377a12cf5c3SThierry Reding i-cache-sets = <256>; 378a12cf5c3SThierry Reding d-cache-size = <65536>; 379a12cf5c3SThierry Reding d-cache-line-size = <64>; 380a12cf5c3SThierry Reding d-cache-sets = <256>; 381a12cf5c3SThierry Reding next-level-cache = <&l2c1_0>; 382a12cf5c3SThierry Reding }; 383a12cf5c3SThierry Reding 384a12cf5c3SThierry Reding cpu1_1: cpu@10100 { 385a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 386a12cf5c3SThierry Reding device_type = "cpu"; 387a12cf5c3SThierry Reding reg = <0x10100>; 388a12cf5c3SThierry Reding 389a12cf5c3SThierry Reding enable-method = "psci"; 390a12cf5c3SThierry Reding 391a12cf5c3SThierry Reding i-cache-size = <65536>; 392a12cf5c3SThierry Reding i-cache-line-size = <64>; 393a12cf5c3SThierry Reding i-cache-sets = <256>; 394a12cf5c3SThierry Reding d-cache-size = <65536>; 395a12cf5c3SThierry Reding d-cache-line-size = <64>; 396a12cf5c3SThierry Reding d-cache-sets = <256>; 397a12cf5c3SThierry Reding next-level-cache = <&l2c1_1>; 398a12cf5c3SThierry Reding }; 399a12cf5c3SThierry Reding 400a12cf5c3SThierry Reding cpu1_2: cpu@10200 { 401a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 402a12cf5c3SThierry Reding device_type = "cpu"; 403a12cf5c3SThierry Reding reg = <0x10200>; 404a12cf5c3SThierry Reding 405a12cf5c3SThierry Reding enable-method = "psci"; 406a12cf5c3SThierry Reding 407a12cf5c3SThierry Reding i-cache-size = <65536>; 408a12cf5c3SThierry Reding i-cache-line-size = <64>; 409a12cf5c3SThierry Reding i-cache-sets = <256>; 410a12cf5c3SThierry Reding d-cache-size = <65536>; 411a12cf5c3SThierry Reding d-cache-line-size = <64>; 412a12cf5c3SThierry Reding d-cache-sets = <256>; 413a12cf5c3SThierry Reding next-level-cache = <&l2c1_2>; 414a12cf5c3SThierry Reding }; 415a12cf5c3SThierry Reding 416a12cf5c3SThierry Reding cpu1_3: cpu@10300 { 417a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 418a12cf5c3SThierry Reding device_type = "cpu"; 419a12cf5c3SThierry Reding reg = <0x10300>; 420a12cf5c3SThierry Reding 421a12cf5c3SThierry Reding enable-method = "psci"; 422a12cf5c3SThierry Reding 423a12cf5c3SThierry Reding i-cache-size = <65536>; 424a12cf5c3SThierry Reding i-cache-line-size = <64>; 425a12cf5c3SThierry Reding i-cache-sets = <256>; 426a12cf5c3SThierry Reding d-cache-size = <65536>; 427a12cf5c3SThierry Reding d-cache-line-size = <64>; 428a12cf5c3SThierry Reding d-cache-sets = <256>; 429a12cf5c3SThierry Reding next-level-cache = <&l2c1_3>; 430a12cf5c3SThierry Reding }; 431a12cf5c3SThierry Reding 432a12cf5c3SThierry Reding cpu2_0: cpu@20000 { 433a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 434a12cf5c3SThierry Reding device_type = "cpu"; 435a12cf5c3SThierry Reding reg = <0x20000>; 436a12cf5c3SThierry Reding 437a12cf5c3SThierry Reding enable-method = "psci"; 438a12cf5c3SThierry Reding 439a12cf5c3SThierry Reding i-cache-size = <65536>; 440a12cf5c3SThierry Reding i-cache-line-size = <64>; 441a12cf5c3SThierry Reding i-cache-sets = <256>; 442a12cf5c3SThierry Reding d-cache-size = <65536>; 443a12cf5c3SThierry Reding d-cache-line-size = <64>; 444a12cf5c3SThierry Reding d-cache-sets = <256>; 445a12cf5c3SThierry Reding next-level-cache = <&l2c2_0>; 446a12cf5c3SThierry Reding }; 447a12cf5c3SThierry Reding 448a12cf5c3SThierry Reding cpu2_1: cpu@20100 { 449a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 450a12cf5c3SThierry Reding device_type = "cpu"; 451a12cf5c3SThierry Reding reg = <0x20100>; 452a12cf5c3SThierry Reding 453a12cf5c3SThierry Reding enable-method = "psci"; 454a12cf5c3SThierry Reding 455a12cf5c3SThierry Reding i-cache-size = <65536>; 456a12cf5c3SThierry Reding i-cache-line-size = <64>; 457a12cf5c3SThierry Reding i-cache-sets = <256>; 458a12cf5c3SThierry Reding d-cache-size = <65536>; 459a12cf5c3SThierry Reding d-cache-line-size = <64>; 460a12cf5c3SThierry Reding d-cache-sets = <256>; 461a12cf5c3SThierry Reding next-level-cache = <&l2c2_1>; 462a12cf5c3SThierry Reding }; 463a12cf5c3SThierry Reding 464a12cf5c3SThierry Reding cpu2_2: cpu@20200 { 465a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 466a12cf5c3SThierry Reding device_type = "cpu"; 467a12cf5c3SThierry Reding reg = <0x20200>; 468a12cf5c3SThierry Reding 469a12cf5c3SThierry Reding enable-method = "psci"; 470a12cf5c3SThierry Reding 471a12cf5c3SThierry Reding i-cache-size = <65536>; 472a12cf5c3SThierry Reding i-cache-line-size = <64>; 473a12cf5c3SThierry Reding i-cache-sets = <256>; 474a12cf5c3SThierry Reding d-cache-size = <65536>; 475a12cf5c3SThierry Reding d-cache-line-size = <64>; 476a12cf5c3SThierry Reding d-cache-sets = <256>; 477a12cf5c3SThierry Reding next-level-cache = <&l2c2_2>; 478a12cf5c3SThierry Reding }; 479a12cf5c3SThierry Reding 480a12cf5c3SThierry Reding cpu2_3: cpu@20300 { 481a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 482a12cf5c3SThierry Reding device_type = "cpu"; 483a12cf5c3SThierry Reding reg = <0x20300>; 484a12cf5c3SThierry Reding 485a12cf5c3SThierry Reding enable-method = "psci"; 486a12cf5c3SThierry Reding 487a12cf5c3SThierry Reding i-cache-size = <65536>; 488a12cf5c3SThierry Reding i-cache-line-size = <64>; 489a12cf5c3SThierry Reding i-cache-sets = <256>; 490a12cf5c3SThierry Reding d-cache-size = <65536>; 491a12cf5c3SThierry Reding d-cache-line-size = <64>; 492a12cf5c3SThierry Reding d-cache-sets = <256>; 493a12cf5c3SThierry Reding next-level-cache = <&l2c2_3>; 494a12cf5c3SThierry Reding }; 495a12cf5c3SThierry Reding 496a12cf5c3SThierry Reding cpu-map { 497a12cf5c3SThierry Reding cluster0 { 498a12cf5c3SThierry Reding core0 { 499a12cf5c3SThierry Reding cpu = <&cpu0_0>; 500a12cf5c3SThierry Reding }; 501a12cf5c3SThierry Reding 502a12cf5c3SThierry Reding core1 { 503a12cf5c3SThierry Reding cpu = <&cpu0_1>; 504a12cf5c3SThierry Reding }; 505a12cf5c3SThierry Reding 506a12cf5c3SThierry Reding core2 { 507a12cf5c3SThierry Reding cpu = <&cpu0_2>; 508a12cf5c3SThierry Reding }; 509a12cf5c3SThierry Reding 510a12cf5c3SThierry Reding core3 { 511a12cf5c3SThierry Reding cpu = <&cpu0_3>; 512a12cf5c3SThierry Reding }; 513a12cf5c3SThierry Reding }; 514a12cf5c3SThierry Reding 515a12cf5c3SThierry Reding cluster1 { 516a12cf5c3SThierry Reding core0 { 517a12cf5c3SThierry Reding cpu = <&cpu1_0>; 518a12cf5c3SThierry Reding }; 519a12cf5c3SThierry Reding 520a12cf5c3SThierry Reding core1 { 521a12cf5c3SThierry Reding cpu = <&cpu1_1>; 522a12cf5c3SThierry Reding }; 523a12cf5c3SThierry Reding 524a12cf5c3SThierry Reding core2 { 525a12cf5c3SThierry Reding cpu = <&cpu1_2>; 526a12cf5c3SThierry Reding }; 527a12cf5c3SThierry Reding 528a12cf5c3SThierry Reding core3 { 529a12cf5c3SThierry Reding cpu = <&cpu1_3>; 530a12cf5c3SThierry Reding }; 531a12cf5c3SThierry Reding }; 532a12cf5c3SThierry Reding 533a12cf5c3SThierry Reding cluster2 { 534a12cf5c3SThierry Reding core0 { 535a12cf5c3SThierry Reding cpu = <&cpu2_0>; 536a12cf5c3SThierry Reding }; 537a12cf5c3SThierry Reding 538a12cf5c3SThierry Reding core1 { 539a12cf5c3SThierry Reding cpu = <&cpu2_1>; 540a12cf5c3SThierry Reding }; 541a12cf5c3SThierry Reding 542a12cf5c3SThierry Reding core2 { 543a12cf5c3SThierry Reding cpu = <&cpu2_2>; 544a12cf5c3SThierry Reding }; 545a12cf5c3SThierry Reding 546a12cf5c3SThierry Reding core3 { 547a12cf5c3SThierry Reding cpu = <&cpu2_3>; 548a12cf5c3SThierry Reding }; 549a12cf5c3SThierry Reding }; 550a12cf5c3SThierry Reding }; 551a12cf5c3SThierry Reding 552a12cf5c3SThierry Reding l2c0_0: l2-cache00 { 553a12cf5c3SThierry Reding cache-size = <262144>; 554a12cf5c3SThierry Reding cache-line-size = <64>; 555a12cf5c3SThierry Reding cache-sets = <512>; 556a12cf5c3SThierry Reding cache-unified; 557a12cf5c3SThierry Reding next-level-cache = <&l3c0>; 558a12cf5c3SThierry Reding }; 559a12cf5c3SThierry Reding 560a12cf5c3SThierry Reding l2c0_1: l2-cache01 { 561a12cf5c3SThierry Reding cache-size = <262144>; 562a12cf5c3SThierry Reding cache-line-size = <64>; 563a12cf5c3SThierry Reding cache-sets = <512>; 564a12cf5c3SThierry Reding cache-unified; 565a12cf5c3SThierry Reding next-level-cache = <&l3c0>; 566a12cf5c3SThierry Reding }; 567a12cf5c3SThierry Reding 568a12cf5c3SThierry Reding l2c0_2: l2-cache02 { 569a12cf5c3SThierry Reding cache-size = <262144>; 570a12cf5c3SThierry Reding cache-line-size = <64>; 571a12cf5c3SThierry Reding cache-sets = <512>; 572a12cf5c3SThierry Reding cache-unified; 573a12cf5c3SThierry Reding next-level-cache = <&l3c0>; 574a12cf5c3SThierry Reding }; 575a12cf5c3SThierry Reding 576a12cf5c3SThierry Reding l2c0_3: l2-cache03 { 577a12cf5c3SThierry Reding cache-size = <262144>; 578a12cf5c3SThierry Reding cache-line-size = <64>; 579a12cf5c3SThierry Reding cache-sets = <512>; 580a12cf5c3SThierry Reding cache-unified; 581a12cf5c3SThierry Reding next-level-cache = <&l3c0>; 582a12cf5c3SThierry Reding }; 583a12cf5c3SThierry Reding 584a12cf5c3SThierry Reding l2c1_0: l2-cache10 { 585a12cf5c3SThierry Reding cache-size = <262144>; 586a12cf5c3SThierry Reding cache-line-size = <64>; 587a12cf5c3SThierry Reding cache-sets = <512>; 588a12cf5c3SThierry Reding cache-unified; 589a12cf5c3SThierry Reding next-level-cache = <&l3c1>; 590a12cf5c3SThierry Reding }; 591a12cf5c3SThierry Reding 592a12cf5c3SThierry Reding l2c1_1: l2-cache11 { 593a12cf5c3SThierry Reding cache-size = <262144>; 594a12cf5c3SThierry Reding cache-line-size = <64>; 595a12cf5c3SThierry Reding cache-sets = <512>; 596a12cf5c3SThierry Reding cache-unified; 597a12cf5c3SThierry Reding next-level-cache = <&l3c1>; 598a12cf5c3SThierry Reding }; 599a12cf5c3SThierry Reding 600a12cf5c3SThierry Reding l2c1_2: l2-cache12 { 601a12cf5c3SThierry Reding cache-size = <262144>; 602a12cf5c3SThierry Reding cache-line-size = <64>; 603a12cf5c3SThierry Reding cache-sets = <512>; 604a12cf5c3SThierry Reding cache-unified; 605a12cf5c3SThierry Reding next-level-cache = <&l3c1>; 606a12cf5c3SThierry Reding }; 607a12cf5c3SThierry Reding 608a12cf5c3SThierry Reding l2c1_3: l2-cache13 { 609a12cf5c3SThierry Reding cache-size = <262144>; 610a12cf5c3SThierry Reding cache-line-size = <64>; 611a12cf5c3SThierry Reding cache-sets = <512>; 612a12cf5c3SThierry Reding cache-unified; 613a12cf5c3SThierry Reding next-level-cache = <&l3c1>; 614a12cf5c3SThierry Reding }; 615a12cf5c3SThierry Reding 616a12cf5c3SThierry Reding l2c2_0: l2-cache20 { 617a12cf5c3SThierry Reding cache-size = <262144>; 618a12cf5c3SThierry Reding cache-line-size = <64>; 619a12cf5c3SThierry Reding cache-sets = <512>; 620a12cf5c3SThierry Reding cache-unified; 621a12cf5c3SThierry Reding next-level-cache = <&l3c2>; 622a12cf5c3SThierry Reding }; 623a12cf5c3SThierry Reding 624a12cf5c3SThierry Reding l2c2_1: l2-cache21 { 625a12cf5c3SThierry Reding cache-size = <262144>; 626a12cf5c3SThierry Reding cache-line-size = <64>; 627a12cf5c3SThierry Reding cache-sets = <512>; 628a12cf5c3SThierry Reding cache-unified; 629a12cf5c3SThierry Reding next-level-cache = <&l3c2>; 630a12cf5c3SThierry Reding }; 631a12cf5c3SThierry Reding 632a12cf5c3SThierry Reding l2c2_2: l2-cache22 { 633a12cf5c3SThierry Reding cache-size = <262144>; 634a12cf5c3SThierry Reding cache-line-size = <64>; 635a12cf5c3SThierry Reding cache-sets = <512>; 636a12cf5c3SThierry Reding cache-unified; 637a12cf5c3SThierry Reding next-level-cache = <&l3c2>; 638a12cf5c3SThierry Reding }; 639a12cf5c3SThierry Reding 640a12cf5c3SThierry Reding l2c2_3: l2-cache23 { 641a12cf5c3SThierry Reding cache-size = <262144>; 642a12cf5c3SThierry Reding cache-line-size = <64>; 643a12cf5c3SThierry Reding cache-sets = <512>; 644a12cf5c3SThierry Reding cache-unified; 645a12cf5c3SThierry Reding next-level-cache = <&l3c2>; 646a12cf5c3SThierry Reding }; 647a12cf5c3SThierry Reding 648a12cf5c3SThierry Reding l3c0: l3-cache0 { 649a12cf5c3SThierry Reding cache-size = <2097152>; 650a12cf5c3SThierry Reding cache-line-size = <64>; 651a12cf5c3SThierry Reding cache-sets = <2048>; 652a12cf5c3SThierry Reding }; 653a12cf5c3SThierry Reding 654a12cf5c3SThierry Reding l3c1: l3-cache1 { 655a12cf5c3SThierry Reding cache-size = <2097152>; 656a12cf5c3SThierry Reding cache-line-size = <64>; 657a12cf5c3SThierry Reding cache-sets = <2048>; 658a12cf5c3SThierry Reding }; 659a12cf5c3SThierry Reding 660a12cf5c3SThierry Reding l3c2: l3-cache2 { 661a12cf5c3SThierry Reding cache-size = <2097152>; 662a12cf5c3SThierry Reding cache-line-size = <64>; 663a12cf5c3SThierry Reding cache-sets = <2048>; 664a12cf5c3SThierry Reding }; 665a12cf5c3SThierry Reding }; 666a12cf5c3SThierry Reding 667a12cf5c3SThierry Reding pmu { 668a12cf5c3SThierry Reding compatible = "arm,cortex-a78-pmu"; 669a12cf5c3SThierry Reding interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 670a12cf5c3SThierry Reding status = "okay"; 67163944891SThierry Reding }; 67263944891SThierry Reding 67363944891SThierry Reding psci { 67463944891SThierry Reding compatible = "arm,psci-1.0"; 67563944891SThierry Reding status = "okay"; 67663944891SThierry Reding method = "smc"; 67763944891SThierry Reding }; 67863944891SThierry Reding 67906ad2ec4SMikko Perttunen tcu: serial { 68006ad2ec4SMikko Perttunen compatible = "nvidia,tegra234-tcu", "nvidia,tegra194-tcu"; 68106ad2ec4SMikko Perttunen mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 68206ad2ec4SMikko Perttunen <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 68306ad2ec4SMikko Perttunen mbox-names = "rx", "tx"; 68406ad2ec4SMikko Perttunen status = "disabled"; 68506ad2ec4SMikko Perttunen }; 68606ad2ec4SMikko Perttunen 68763944891SThierry Reding timer { 68863944891SThierry Reding compatible = "arm,armv8-timer"; 68963944891SThierry Reding interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 69063944891SThierry Reding <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 69163944891SThierry Reding <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 69263944891SThierry Reding <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 69363944891SThierry Reding interrupt-parent = <&gic>; 69463944891SThierry Reding always-on; 69563944891SThierry Reding }; 69663944891SThierry Reding}; 697