163944891SThierry Reding// SPDX-License-Identifier: GPL-2.0 263944891SThierry Reding 363944891SThierry Reding#include <dt-bindings/clock/tegra234-clock.h> 4699349e0SThierry Reding#include <dt-bindings/gpio/tegra234-gpio.h> 563944891SThierry Reding#include <dt-bindings/interrupt-controller/arm-gic.h> 663944891SThierry Reding#include <dt-bindings/mailbox/tegra186-hsp.h> 7eed280dfSThierry Reding#include <dt-bindings/memory/tegra234-mc.h> 8dc94a94dSSameer Pujar#include <dt-bindings/power/tegra234-powergate.h> 963944891SThierry Reding#include <dt-bindings/reset/tegra234-reset.h> 1063944891SThierry Reding 1163944891SThierry Reding/ { 1263944891SThierry Reding compatible = "nvidia,tegra234"; 1363944891SThierry Reding interrupt-parent = <&gic>; 1463944891SThierry Reding #address-cells = <2>; 1563944891SThierry Reding #size-cells = <2>; 1663944891SThierry Reding 1763944891SThierry Reding bus@0 { 1863944891SThierry Reding compatible = "simple-bus"; 1963944891SThierry Reding #address-cells = <1>; 2063944891SThierry Reding #size-cells = <1>; 2163944891SThierry Reding 2263944891SThierry Reding ranges = <0x0 0x0 0x0 0x40000000>; 2363944891SThierry Reding 2460d2016aSAkhil R gpcdma: dma-controller@2600000 { 25f7b93a08SAkhil R compatible = "nvidia,tegra234-gpcdma", 26f7b93a08SAkhil R "nvidia,tegra194-gpcdma", 2760d2016aSAkhil R "nvidia,tegra186-gpcdma"; 2860d2016aSAkhil R reg = <0x2600000 0x210000>; 2960d2016aSAkhil R resets = <&bpmp TEGRA234_RESET_GPCDMA>; 3060d2016aSAkhil R reset-names = "gpcdma"; 3160d2016aSAkhil R interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 3260d2016aSAkhil R <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 3360d2016aSAkhil R <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 3460d2016aSAkhil R <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 3560d2016aSAkhil R <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 3660d2016aSAkhil R <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 3760d2016aSAkhil R <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 3860d2016aSAkhil R <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 3960d2016aSAkhil R <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 4060d2016aSAkhil R <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 4160d2016aSAkhil R <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 4260d2016aSAkhil R <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 4360d2016aSAkhil R <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 4460d2016aSAkhil R <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 4560d2016aSAkhil R <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 4660d2016aSAkhil R <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 4760d2016aSAkhil R <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 4860d2016aSAkhil R <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 4960d2016aSAkhil R <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 5060d2016aSAkhil R <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 5160d2016aSAkhil R <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 5260d2016aSAkhil R <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 5360d2016aSAkhil R <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 5460d2016aSAkhil R <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 5560d2016aSAkhil R <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 5660d2016aSAkhil R <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 5760d2016aSAkhil R <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 5860d2016aSAkhil R <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 5960d2016aSAkhil R <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 6060d2016aSAkhil R <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 6160d2016aSAkhil R <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 6260d2016aSAkhil R #dma-cells = <1>; 6360d2016aSAkhil R iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 6460d2016aSAkhil R dma-coherent; 6560d2016aSAkhil R }; 6660d2016aSAkhil R 67dc94a94dSSameer Pujar aconnect@2900000 { 68dc94a94dSSameer Pujar compatible = "nvidia,tegra234-aconnect", 69dc94a94dSSameer Pujar "nvidia,tegra210-aconnect"; 70dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_APE>, 71dc94a94dSSameer Pujar <&bpmp TEGRA234_CLK_APB2APE>; 72dc94a94dSSameer Pujar clock-names = "ape", "apb2ape"; 73dc94a94dSSameer Pujar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_AUD>; 74dc94a94dSSameer Pujar #address-cells = <1>; 75dc94a94dSSameer Pujar #size-cells = <1>; 76dc94a94dSSameer Pujar ranges = <0x02900000 0x02900000 0x200000>; 77dc94a94dSSameer Pujar status = "disabled"; 78dc94a94dSSameer Pujar 79dc94a94dSSameer Pujar tegra_ahub: ahub@2900800 { 80dc94a94dSSameer Pujar compatible = "nvidia,tegra234-ahub"; 81dc94a94dSSameer Pujar reg = <0x02900800 0x800>; 82dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_AHUB>; 83dc94a94dSSameer Pujar clock-names = "ahub"; 84dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_AHUB>; 85dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 86dc94a94dSSameer Pujar #address-cells = <1>; 87dc94a94dSSameer Pujar #size-cells = <1>; 88dc94a94dSSameer Pujar ranges = <0x02900800 0x02900800 0x11800>; 89dc94a94dSSameer Pujar status = "disabled"; 90dc94a94dSSameer Pujar 91dc94a94dSSameer Pujar tegra_i2s1: i2s@2901000 { 92dc94a94dSSameer Pujar compatible = "nvidia,tegra234-i2s", 93dc94a94dSSameer Pujar "nvidia,tegra210-i2s"; 94dc94a94dSSameer Pujar reg = <0x2901000 0x100>; 95dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_I2S1>, 96dc94a94dSSameer Pujar <&bpmp TEGRA234_CLK_I2S1_SYNC_INPUT>; 97dc94a94dSSameer Pujar clock-names = "i2s", "sync_input"; 98dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_I2S1>; 99dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 100dc94a94dSSameer Pujar assigned-clock-rates = <1536000>; 101dc94a94dSSameer Pujar sound-name-prefix = "I2S1"; 102dc94a94dSSameer Pujar status = "disabled"; 103dc94a94dSSameer Pujar }; 104dc94a94dSSameer Pujar 105dc94a94dSSameer Pujar tegra_i2s2: i2s@2901100 { 106dc94a94dSSameer Pujar compatible = "nvidia,tegra234-i2s", 107dc94a94dSSameer Pujar "nvidia,tegra210-i2s"; 108dc94a94dSSameer Pujar reg = <0x2901100 0x100>; 109dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_I2S2>, 110dc94a94dSSameer Pujar <&bpmp TEGRA234_CLK_I2S2_SYNC_INPUT>; 111dc94a94dSSameer Pujar clock-names = "i2s", "sync_input"; 112dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_I2S2>; 113dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 114dc94a94dSSameer Pujar assigned-clock-rates = <1536000>; 115dc94a94dSSameer Pujar sound-name-prefix = "I2S2"; 116dc94a94dSSameer Pujar status = "disabled"; 117dc94a94dSSameer Pujar }; 118dc94a94dSSameer Pujar 119dc94a94dSSameer Pujar tegra_i2s3: i2s@2901200 { 120dc94a94dSSameer Pujar compatible = "nvidia,tegra234-i2s", 121dc94a94dSSameer Pujar "nvidia,tegra210-i2s"; 122dc94a94dSSameer Pujar reg = <0x2901200 0x100>; 123dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_I2S3>, 124dc94a94dSSameer Pujar <&bpmp TEGRA234_CLK_I2S3_SYNC_INPUT>; 125dc94a94dSSameer Pujar clock-names = "i2s", "sync_input"; 126dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_I2S3>; 127dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 128dc94a94dSSameer Pujar assigned-clock-rates = <1536000>; 129dc94a94dSSameer Pujar sound-name-prefix = "I2S3"; 130dc94a94dSSameer Pujar status = "disabled"; 131dc94a94dSSameer Pujar }; 132dc94a94dSSameer Pujar 133dc94a94dSSameer Pujar tegra_i2s4: i2s@2901300 { 134dc94a94dSSameer Pujar compatible = "nvidia,tegra234-i2s", 135dc94a94dSSameer Pujar "nvidia,tegra210-i2s"; 136dc94a94dSSameer Pujar reg = <0x2901300 0x100>; 137dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_I2S4>, 138dc94a94dSSameer Pujar <&bpmp TEGRA234_CLK_I2S4_SYNC_INPUT>; 139dc94a94dSSameer Pujar clock-names = "i2s", "sync_input"; 140dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_I2S4>; 141dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 142dc94a94dSSameer Pujar assigned-clock-rates = <1536000>; 143dc94a94dSSameer Pujar sound-name-prefix = "I2S4"; 144dc94a94dSSameer Pujar status = "disabled"; 145dc94a94dSSameer Pujar }; 146dc94a94dSSameer Pujar 147dc94a94dSSameer Pujar tegra_i2s5: i2s@2901400 { 148dc94a94dSSameer Pujar compatible = "nvidia,tegra234-i2s", 149dc94a94dSSameer Pujar "nvidia,tegra210-i2s"; 150dc94a94dSSameer Pujar reg = <0x2901400 0x100>; 151dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_I2S5>, 152dc94a94dSSameer Pujar <&bpmp TEGRA234_CLK_I2S5_SYNC_INPUT>; 153dc94a94dSSameer Pujar clock-names = "i2s", "sync_input"; 154dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_I2S5>; 155dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 156dc94a94dSSameer Pujar assigned-clock-rates = <1536000>; 157dc94a94dSSameer Pujar sound-name-prefix = "I2S5"; 158dc94a94dSSameer Pujar status = "disabled"; 159dc94a94dSSameer Pujar }; 160dc94a94dSSameer Pujar 161dc94a94dSSameer Pujar tegra_i2s6: i2s@2901500 { 162dc94a94dSSameer Pujar compatible = "nvidia,tegra234-i2s", 163dc94a94dSSameer Pujar "nvidia,tegra210-i2s"; 164dc94a94dSSameer Pujar reg = <0x2901500 0x100>; 165dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_I2S6>, 166dc94a94dSSameer Pujar <&bpmp TEGRA234_CLK_I2S6_SYNC_INPUT>; 167dc94a94dSSameer Pujar clock-names = "i2s", "sync_input"; 168dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_I2S6>; 169dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 170dc94a94dSSameer Pujar assigned-clock-rates = <1536000>; 171dc94a94dSSameer Pujar sound-name-prefix = "I2S6"; 172dc94a94dSSameer Pujar status = "disabled"; 173dc94a94dSSameer Pujar }; 174dc94a94dSSameer Pujar 175dc94a94dSSameer Pujar tegra_sfc1: sfc@2902000 { 176dc94a94dSSameer Pujar compatible = "nvidia,tegra234-sfc", 177dc94a94dSSameer Pujar "nvidia,tegra210-sfc"; 178dc94a94dSSameer Pujar reg = <0x2902000 0x200>; 179dc94a94dSSameer Pujar sound-name-prefix = "SFC1"; 180dc94a94dSSameer Pujar status = "disabled"; 181dc94a94dSSameer Pujar }; 182dc94a94dSSameer Pujar 183dc94a94dSSameer Pujar tegra_sfc2: sfc@2902200 { 184dc94a94dSSameer Pujar compatible = "nvidia,tegra234-sfc", 185dc94a94dSSameer Pujar "nvidia,tegra210-sfc"; 186dc94a94dSSameer Pujar reg = <0x2902200 0x200>; 187dc94a94dSSameer Pujar sound-name-prefix = "SFC2"; 188dc94a94dSSameer Pujar status = "disabled"; 189dc94a94dSSameer Pujar }; 190dc94a94dSSameer Pujar 191dc94a94dSSameer Pujar tegra_sfc3: sfc@2902400 { 192dc94a94dSSameer Pujar compatible = "nvidia,tegra234-sfc", 193dc94a94dSSameer Pujar "nvidia,tegra210-sfc"; 194dc94a94dSSameer Pujar reg = <0x2902400 0x200>; 195dc94a94dSSameer Pujar sound-name-prefix = "SFC3"; 196dc94a94dSSameer Pujar status = "disabled"; 197dc94a94dSSameer Pujar }; 198dc94a94dSSameer Pujar 199dc94a94dSSameer Pujar tegra_sfc4: sfc@2902600 { 200dc94a94dSSameer Pujar compatible = "nvidia,tegra234-sfc", 201dc94a94dSSameer Pujar "nvidia,tegra210-sfc"; 202dc94a94dSSameer Pujar reg = <0x2902600 0x200>; 203dc94a94dSSameer Pujar sound-name-prefix = "SFC4"; 204dc94a94dSSameer Pujar status = "disabled"; 205dc94a94dSSameer Pujar }; 206dc94a94dSSameer Pujar 207dc94a94dSSameer Pujar tegra_amx1: amx@2903000 { 208dc94a94dSSameer Pujar compatible = "nvidia,tegra234-amx", 209dc94a94dSSameer Pujar "nvidia,tegra194-amx"; 210dc94a94dSSameer Pujar reg = <0x2903000 0x100>; 211dc94a94dSSameer Pujar sound-name-prefix = "AMX1"; 212dc94a94dSSameer Pujar status = "disabled"; 213dc94a94dSSameer Pujar }; 214dc94a94dSSameer Pujar 215dc94a94dSSameer Pujar tegra_amx2: amx@2903100 { 216dc94a94dSSameer Pujar compatible = "nvidia,tegra234-amx", 217dc94a94dSSameer Pujar "nvidia,tegra194-amx"; 218dc94a94dSSameer Pujar reg = <0x2903100 0x100>; 219dc94a94dSSameer Pujar sound-name-prefix = "AMX2"; 220dc94a94dSSameer Pujar status = "disabled"; 221dc94a94dSSameer Pujar }; 222dc94a94dSSameer Pujar 223dc94a94dSSameer Pujar tegra_amx3: amx@2903200 { 224dc94a94dSSameer Pujar compatible = "nvidia,tegra234-amx", 225dc94a94dSSameer Pujar "nvidia,tegra194-amx"; 226dc94a94dSSameer Pujar reg = <0x2903200 0x100>; 227dc94a94dSSameer Pujar sound-name-prefix = "AMX3"; 228dc94a94dSSameer Pujar status = "disabled"; 229dc94a94dSSameer Pujar }; 230dc94a94dSSameer Pujar 231dc94a94dSSameer Pujar tegra_amx4: amx@2903300 { 232dc94a94dSSameer Pujar compatible = "nvidia,tegra234-amx", 233dc94a94dSSameer Pujar "nvidia,tegra194-amx"; 234dc94a94dSSameer Pujar reg = <0x2903300 0x100>; 235dc94a94dSSameer Pujar sound-name-prefix = "AMX4"; 236dc94a94dSSameer Pujar status = "disabled"; 237dc94a94dSSameer Pujar }; 238dc94a94dSSameer Pujar 239dc94a94dSSameer Pujar tegra_adx1: adx@2903800 { 240dc94a94dSSameer Pujar compatible = "nvidia,tegra234-adx", 241dc94a94dSSameer Pujar "nvidia,tegra210-adx"; 242dc94a94dSSameer Pujar reg = <0x2903800 0x100>; 243dc94a94dSSameer Pujar sound-name-prefix = "ADX1"; 244dc94a94dSSameer Pujar status = "disabled"; 245dc94a94dSSameer Pujar }; 246dc94a94dSSameer Pujar 247dc94a94dSSameer Pujar tegra_adx2: adx@2903900 { 248dc94a94dSSameer Pujar compatible = "nvidia,tegra234-adx", 249dc94a94dSSameer Pujar "nvidia,tegra210-adx"; 250dc94a94dSSameer Pujar reg = <0x2903900 0x100>; 251dc94a94dSSameer Pujar sound-name-prefix = "ADX2"; 252dc94a94dSSameer Pujar status = "disabled"; 253dc94a94dSSameer Pujar }; 254dc94a94dSSameer Pujar 255dc94a94dSSameer Pujar tegra_adx3: adx@2903a00 { 256dc94a94dSSameer Pujar compatible = "nvidia,tegra234-adx", 257dc94a94dSSameer Pujar "nvidia,tegra210-adx"; 258dc94a94dSSameer Pujar reg = <0x2903a00 0x100>; 259dc94a94dSSameer Pujar sound-name-prefix = "ADX3"; 260dc94a94dSSameer Pujar status = "disabled"; 261dc94a94dSSameer Pujar }; 262dc94a94dSSameer Pujar 263dc94a94dSSameer Pujar tegra_adx4: adx@2903b00 { 264dc94a94dSSameer Pujar compatible = "nvidia,tegra234-adx", 265dc94a94dSSameer Pujar "nvidia,tegra210-adx"; 266dc94a94dSSameer Pujar reg = <0x2903b00 0x100>; 267dc94a94dSSameer Pujar sound-name-prefix = "ADX4"; 268dc94a94dSSameer Pujar status = "disabled"; 269dc94a94dSSameer Pujar }; 270dc94a94dSSameer Pujar 271dc94a94dSSameer Pujar 272dc94a94dSSameer Pujar tegra_dmic1: dmic@2904000 { 273dc94a94dSSameer Pujar compatible = "nvidia,tegra234-dmic", 274dc94a94dSSameer Pujar "nvidia,tegra210-dmic"; 275dc94a94dSSameer Pujar reg = <0x2904000 0x100>; 276dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_DMIC1>; 277dc94a94dSSameer Pujar clock-names = "dmic"; 278dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_DMIC1>; 279dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 280dc94a94dSSameer Pujar assigned-clock-rates = <3072000>; 281dc94a94dSSameer Pujar sound-name-prefix = "DMIC1"; 282dc94a94dSSameer Pujar status = "disabled"; 283dc94a94dSSameer Pujar }; 284dc94a94dSSameer Pujar 285dc94a94dSSameer Pujar tegra_dmic2: dmic@2904100 { 286dc94a94dSSameer Pujar compatible = "nvidia,tegra234-dmic", 287dc94a94dSSameer Pujar "nvidia,tegra210-dmic"; 288dc94a94dSSameer Pujar reg = <0x2904100 0x100>; 289dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_DMIC2>; 290dc94a94dSSameer Pujar clock-names = "dmic"; 291dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_DMIC2>; 292dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 293dc94a94dSSameer Pujar assigned-clock-rates = <3072000>; 294dc94a94dSSameer Pujar sound-name-prefix = "DMIC2"; 295dc94a94dSSameer Pujar status = "disabled"; 296dc94a94dSSameer Pujar }; 297dc94a94dSSameer Pujar 298dc94a94dSSameer Pujar tegra_dmic3: dmic@2904200 { 299dc94a94dSSameer Pujar compatible = "nvidia,tegra234-dmic", 300dc94a94dSSameer Pujar "nvidia,tegra210-dmic"; 301dc94a94dSSameer Pujar reg = <0x2904200 0x100>; 302dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_DMIC3>; 303dc94a94dSSameer Pujar clock-names = "dmic"; 304dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_DMIC3>; 305dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 306dc94a94dSSameer Pujar assigned-clock-rates = <3072000>; 307dc94a94dSSameer Pujar sound-name-prefix = "DMIC3"; 308dc94a94dSSameer Pujar status = "disabled"; 309dc94a94dSSameer Pujar }; 310dc94a94dSSameer Pujar 311dc94a94dSSameer Pujar tegra_dmic4: dmic@2904300 { 312dc94a94dSSameer Pujar compatible = "nvidia,tegra234-dmic", 313dc94a94dSSameer Pujar "nvidia,tegra210-dmic"; 314dc94a94dSSameer Pujar reg = <0x2904300 0x100>; 315dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_DMIC4>; 316dc94a94dSSameer Pujar clock-names = "dmic"; 317dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_DMIC4>; 318dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 319dc94a94dSSameer Pujar assigned-clock-rates = <3072000>; 320dc94a94dSSameer Pujar sound-name-prefix = "DMIC4"; 321dc94a94dSSameer Pujar status = "disabled"; 322dc94a94dSSameer Pujar }; 323dc94a94dSSameer Pujar 324dc94a94dSSameer Pujar tegra_dspk1: dspk@2905000 { 325dc94a94dSSameer Pujar compatible = "nvidia,tegra234-dspk", 326dc94a94dSSameer Pujar "nvidia,tegra186-dspk"; 327dc94a94dSSameer Pujar reg = <0x2905000 0x100>; 328dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_DSPK1>; 329dc94a94dSSameer Pujar clock-names = "dspk"; 330dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_DSPK1>; 331dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 332dc94a94dSSameer Pujar assigned-clock-rates = <12288000>; 333dc94a94dSSameer Pujar sound-name-prefix = "DSPK1"; 334dc94a94dSSameer Pujar status = "disabled"; 335dc94a94dSSameer Pujar }; 336dc94a94dSSameer Pujar 337dc94a94dSSameer Pujar tegra_dspk2: dspk@2905100 { 338dc94a94dSSameer Pujar compatible = "nvidia,tegra234-dspk", 339dc94a94dSSameer Pujar "nvidia,tegra186-dspk"; 340dc94a94dSSameer Pujar reg = <0x2905100 0x100>; 341dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_DSPK2>; 342dc94a94dSSameer Pujar clock-names = "dspk"; 343dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_DSPK2>; 344dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 345dc94a94dSSameer Pujar assigned-clock-rates = <12288000>; 346dc94a94dSSameer Pujar sound-name-prefix = "DSPK2"; 347dc94a94dSSameer Pujar status = "disabled"; 348dc94a94dSSameer Pujar }; 349dc94a94dSSameer Pujar 3504b6a1b7cSSameer Pujar tegra_ope1: processing-engine@2908000 { 3514b6a1b7cSSameer Pujar compatible = "nvidia,tegra234-ope", 3524b6a1b7cSSameer Pujar "nvidia,tegra210-ope"; 3534b6a1b7cSSameer Pujar reg = <0x2908000 0x100>; 3544b6a1b7cSSameer Pujar #address-cells = <1>; 3554b6a1b7cSSameer Pujar #size-cells = <1>; 3564b6a1b7cSSameer Pujar ranges; 3574b6a1b7cSSameer Pujar sound-name-prefix = "OPE1"; 3584b6a1b7cSSameer Pujar status = "disabled"; 3594b6a1b7cSSameer Pujar 3604b6a1b7cSSameer Pujar equalizer@2908100 { 3614b6a1b7cSSameer Pujar compatible = "nvidia,tegra234-peq", 3624b6a1b7cSSameer Pujar "nvidia,tegra210-peq"; 3634b6a1b7cSSameer Pujar reg = <0x2908100 0x100>; 3644b6a1b7cSSameer Pujar }; 3654b6a1b7cSSameer Pujar 3664b6a1b7cSSameer Pujar dynamic-range-compressor@2908200 { 3674b6a1b7cSSameer Pujar compatible = "nvidia,tegra234-mbdrc", 3684b6a1b7cSSameer Pujar "nvidia,tegra210-mbdrc"; 3694b6a1b7cSSameer Pujar reg = <0x2908200 0x200>; 3704b6a1b7cSSameer Pujar }; 3714b6a1b7cSSameer Pujar }; 3724b6a1b7cSSameer Pujar 373dc94a94dSSameer Pujar tegra_mvc1: mvc@290a000 { 374dc94a94dSSameer Pujar compatible = "nvidia,tegra234-mvc", 375dc94a94dSSameer Pujar "nvidia,tegra210-mvc"; 376dc94a94dSSameer Pujar reg = <0x290a000 0x200>; 377dc94a94dSSameer Pujar sound-name-prefix = "MVC1"; 378dc94a94dSSameer Pujar status = "disabled"; 379dc94a94dSSameer Pujar }; 380dc94a94dSSameer Pujar 381dc94a94dSSameer Pujar tegra_mvc2: mvc@290a200 { 382dc94a94dSSameer Pujar compatible = "nvidia,tegra234-mvc", 383dc94a94dSSameer Pujar "nvidia,tegra210-mvc"; 384dc94a94dSSameer Pujar reg = <0x290a200 0x200>; 385dc94a94dSSameer Pujar sound-name-prefix = "MVC2"; 386dc94a94dSSameer Pujar status = "disabled"; 387dc94a94dSSameer Pujar }; 388dc94a94dSSameer Pujar 389dc94a94dSSameer Pujar tegra_amixer: amixer@290bb00 { 390dc94a94dSSameer Pujar compatible = "nvidia,tegra234-amixer", 391dc94a94dSSameer Pujar "nvidia,tegra210-amixer"; 392dc94a94dSSameer Pujar reg = <0x290bb00 0x800>; 393dc94a94dSSameer Pujar sound-name-prefix = "MIXER1"; 394dc94a94dSSameer Pujar status = "disabled"; 395dc94a94dSSameer Pujar }; 396dc94a94dSSameer Pujar 397dc94a94dSSameer Pujar tegra_admaif: admaif@290f000 { 398dc94a94dSSameer Pujar compatible = "nvidia,tegra234-admaif", 399dc94a94dSSameer Pujar "nvidia,tegra186-admaif"; 400dc94a94dSSameer Pujar reg = <0x0290f000 0x1000>; 401dc94a94dSSameer Pujar dmas = <&adma 1>, <&adma 1>, 402dc94a94dSSameer Pujar <&adma 2>, <&adma 2>, 403dc94a94dSSameer Pujar <&adma 3>, <&adma 3>, 404dc94a94dSSameer Pujar <&adma 4>, <&adma 4>, 405dc94a94dSSameer Pujar <&adma 5>, <&adma 5>, 406dc94a94dSSameer Pujar <&adma 6>, <&adma 6>, 407dc94a94dSSameer Pujar <&adma 7>, <&adma 7>, 408dc94a94dSSameer Pujar <&adma 8>, <&adma 8>, 409dc94a94dSSameer Pujar <&adma 9>, <&adma 9>, 410dc94a94dSSameer Pujar <&adma 10>, <&adma 10>, 411dc94a94dSSameer Pujar <&adma 11>, <&adma 11>, 412dc94a94dSSameer Pujar <&adma 12>, <&adma 12>, 413dc94a94dSSameer Pujar <&adma 13>, <&adma 13>, 414dc94a94dSSameer Pujar <&adma 14>, <&adma 14>, 415dc94a94dSSameer Pujar <&adma 15>, <&adma 15>, 416dc94a94dSSameer Pujar <&adma 16>, <&adma 16>, 417dc94a94dSSameer Pujar <&adma 17>, <&adma 17>, 418dc94a94dSSameer Pujar <&adma 18>, <&adma 18>, 419dc94a94dSSameer Pujar <&adma 19>, <&adma 19>, 420dc94a94dSSameer Pujar <&adma 20>, <&adma 20>; 421dc94a94dSSameer Pujar dma-names = "rx1", "tx1", 422dc94a94dSSameer Pujar "rx2", "tx2", 423dc94a94dSSameer Pujar "rx3", "tx3", 424dc94a94dSSameer Pujar "rx4", "tx4", 425dc94a94dSSameer Pujar "rx5", "tx5", 426dc94a94dSSameer Pujar "rx6", "tx6", 427dc94a94dSSameer Pujar "rx7", "tx7", 428dc94a94dSSameer Pujar "rx8", "tx8", 429dc94a94dSSameer Pujar "rx9", "tx9", 430dc94a94dSSameer Pujar "rx10", "tx10", 431dc94a94dSSameer Pujar "rx11", "tx11", 432dc94a94dSSameer Pujar "rx12", "tx12", 433dc94a94dSSameer Pujar "rx13", "tx13", 434dc94a94dSSameer Pujar "rx14", "tx14", 435dc94a94dSSameer Pujar "rx15", "tx15", 436dc94a94dSSameer Pujar "rx16", "tx16", 437dc94a94dSSameer Pujar "rx17", "tx17", 438dc94a94dSSameer Pujar "rx18", "tx18", 439dc94a94dSSameer Pujar "rx19", "tx19", 440dc94a94dSSameer Pujar "rx20", "tx20"; 441dc94a94dSSameer Pujar interconnects = <&mc TEGRA234_MEMORY_CLIENT_APEDMAR &emc>, 442dc94a94dSSameer Pujar <&mc TEGRA234_MEMORY_CLIENT_APEDMAW &emc>; 443dc94a94dSSameer Pujar interconnect-names = "dma-mem", "write"; 444dc94a94dSSameer Pujar iommus = <&smmu_niso0 TEGRA234_SID_APE>; 445dc94a94dSSameer Pujar status = "disabled"; 446dc94a94dSSameer Pujar }; 44747a08153SSameer Pujar 44847a08153SSameer Pujar tegra_asrc: asrc@2910000 { 44947a08153SSameer Pujar compatible = "nvidia,tegra234-asrc", 45047a08153SSameer Pujar "nvidia,tegra186-asrc"; 45147a08153SSameer Pujar reg = <0x2910000 0x2000>; 45247a08153SSameer Pujar sound-name-prefix = "ASRC1"; 45347a08153SSameer Pujar status = "disabled"; 45447a08153SSameer Pujar }; 455dc94a94dSSameer Pujar }; 456dc94a94dSSameer Pujar 457dc94a94dSSameer Pujar adma: dma-controller@2930000 { 458dc94a94dSSameer Pujar compatible = "nvidia,tegra234-adma", 459dc94a94dSSameer Pujar "nvidia,tegra186-adma"; 460dc94a94dSSameer Pujar reg = <0x02930000 0x20000>; 461dc94a94dSSameer Pujar interrupt-parent = <&agic>; 462dc94a94dSSameer Pujar interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 463dc94a94dSSameer Pujar <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 464dc94a94dSSameer Pujar <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 465dc94a94dSSameer Pujar <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 466dc94a94dSSameer Pujar <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 467dc94a94dSSameer Pujar <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 468dc94a94dSSameer Pujar <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 469dc94a94dSSameer Pujar <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 470dc94a94dSSameer Pujar <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 471dc94a94dSSameer Pujar <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 472dc94a94dSSameer Pujar <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 473dc94a94dSSameer Pujar <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 474dc94a94dSSameer Pujar <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 475dc94a94dSSameer Pujar <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 476dc94a94dSSameer Pujar <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 477dc94a94dSSameer Pujar <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 478dc94a94dSSameer Pujar <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 479dc94a94dSSameer Pujar <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 480dc94a94dSSameer Pujar <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 481dc94a94dSSameer Pujar <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 482dc94a94dSSameer Pujar <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 483dc94a94dSSameer Pujar <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 484dc94a94dSSameer Pujar <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 485dc94a94dSSameer Pujar <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 486dc94a94dSSameer Pujar <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 487dc94a94dSSameer Pujar <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 488dc94a94dSSameer Pujar <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 489dc94a94dSSameer Pujar <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 490dc94a94dSSameer Pujar <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 491dc94a94dSSameer Pujar <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 492dc94a94dSSameer Pujar <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 493dc94a94dSSameer Pujar <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 494dc94a94dSSameer Pujar #dma-cells = <1>; 495dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_AHUB>; 496dc94a94dSSameer Pujar clock-names = "d_audio"; 497dc94a94dSSameer Pujar status = "disabled"; 498dc94a94dSSameer Pujar }; 499dc94a94dSSameer Pujar 500dc94a94dSSameer Pujar agic: interrupt-controller@2a40000 { 501dc94a94dSSameer Pujar compatible = "nvidia,tegra234-agic", 502dc94a94dSSameer Pujar "nvidia,tegra210-agic"; 503dc94a94dSSameer Pujar #interrupt-cells = <3>; 504dc94a94dSSameer Pujar interrupt-controller; 505dc94a94dSSameer Pujar reg = <0x02a41000 0x1000>, 506dc94a94dSSameer Pujar <0x02a42000 0x2000>; 507dc94a94dSSameer Pujar interrupts = <GIC_SPI 145 508dc94a94dSSameer Pujar (GIC_CPU_MASK_SIMPLE(4) | 509dc94a94dSSameer Pujar IRQ_TYPE_LEVEL_HIGH)>; 510dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_APE>; 511dc94a94dSSameer Pujar clock-names = "clk"; 512dc94a94dSSameer Pujar status = "disabled"; 513dc94a94dSSameer Pujar }; 514dc94a94dSSameer Pujar }; 515dc94a94dSSameer Pujar 51663944891SThierry Reding misc@100000 { 51763944891SThierry Reding compatible = "nvidia,tegra234-misc"; 51863944891SThierry Reding reg = <0x00100000 0xf000>, 51963944891SThierry Reding <0x0010f000 0x1000>; 52063944891SThierry Reding status = "okay"; 52163944891SThierry Reding }; 52263944891SThierry Reding 52328d860edSKartik timer@2080000 { 52428d860edSKartik compatible = "nvidia,tegra234-timer"; 52528d860edSKartik reg = <0x02080000 0x00121000>; 52628d860edSKartik interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 52728d860edSKartik <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 52828d860edSKartik <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 52928d860edSKartik <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 53028d860edSKartik <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 53128d860edSKartik <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 53228d860edSKartik <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 53328d860edSKartik <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 53428d860edSKartik <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 53528d860edSKartik <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 53628d860edSKartik <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 53728d860edSKartik <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 53828d860edSKartik <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 53928d860edSKartik <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 54028d860edSKartik <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 54128d860edSKartik <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 54228d860edSKartik status = "okay"; 54328d860edSKartik }; 54428d860edSKartik 5454bb39ca2SMikko Perttunen host1x@13e00000 { 5464bb39ca2SMikko Perttunen compatible = "nvidia,tegra234-host1x"; 5474bb39ca2SMikko Perttunen reg = <0x13e00000 0x10000>, 5484bb39ca2SMikko Perttunen <0x13e10000 0x10000>, 5494bb39ca2SMikko Perttunen <0x13e40000 0x10000>; 5504bb39ca2SMikko Perttunen reg-names = "common", "hypervisor", "vm"; 5514bb39ca2SMikko Perttunen interrupts = <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, 5524bb39ca2SMikko Perttunen <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, 5534bb39ca2SMikko Perttunen <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, 5544bb39ca2SMikko Perttunen <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, 5554bb39ca2SMikko Perttunen <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, 5564bb39ca2SMikko Perttunen <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>, 5574bb39ca2SMikko Perttunen <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>, 5584bb39ca2SMikko Perttunen <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>, 5594bb39ca2SMikko Perttunen <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 5604bb39ca2SMikko Perttunen interrupt-names = "syncpt0", "syncpt1", "syncpt2", "syncpt3", "syncpt4", 5614bb39ca2SMikko Perttunen "syncpt5", "syncpt6", "syncpt7", "host1x"; 5624bb39ca2SMikko Perttunen clocks = <&bpmp TEGRA234_CLK_HOST1X>; 5634bb39ca2SMikko Perttunen clock-names = "host1x"; 5644bb39ca2SMikko Perttunen 5654bb39ca2SMikko Perttunen #address-cells = <1>; 5664bb39ca2SMikko Perttunen #size-cells = <1>; 5674bb39ca2SMikko Perttunen 5684bb39ca2SMikko Perttunen ranges = <0x15000000 0x15000000 0x01000000>; 5694bb39ca2SMikko Perttunen interconnects = <&mc TEGRA234_MEMORY_CLIENT_HOST1XDMAR &emc>; 5704bb39ca2SMikko Perttunen interconnect-names = "dma-mem"; 5714bb39ca2SMikko Perttunen iommus = <&smmu_niso1 TEGRA234_SID_HOST1X>; 5724bb39ca2SMikko Perttunen 5734bb39ca2SMikko Perttunen vic@15340000 { 5744bb39ca2SMikko Perttunen compatible = "nvidia,tegra234-vic"; 5754bb39ca2SMikko Perttunen reg = <0x15340000 0x00040000>; 5764bb39ca2SMikko Perttunen interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 5774bb39ca2SMikko Perttunen clocks = <&bpmp TEGRA234_CLK_VIC>; 5784bb39ca2SMikko Perttunen clock-names = "vic"; 5794bb39ca2SMikko Perttunen resets = <&bpmp TEGRA234_RESET_VIC>; 5804bb39ca2SMikko Perttunen reset-names = "vic"; 5814bb39ca2SMikko Perttunen 5824bb39ca2SMikko Perttunen power-domains = <&bpmp TEGRA234_POWER_DOMAIN_VIC>; 5834bb39ca2SMikko Perttunen interconnects = <&mc TEGRA234_MEMORY_CLIENT_VICSRD &emc>, 5844bb39ca2SMikko Perttunen <&mc TEGRA234_MEMORY_CLIENT_VICSWR &emc>; 5854bb39ca2SMikko Perttunen interconnect-names = "dma-mem", "write"; 5864bb39ca2SMikko Perttunen iommus = <&smmu_niso1 TEGRA234_SID_VIC>; 5874bb39ca2SMikko Perttunen dma-coherent; 5884bb39ca2SMikko Perttunen }; 5894bb39ca2SMikko Perttunen }; 5904bb39ca2SMikko Perttunen 591f0e12668SThierry Reding gpio: gpio@2200000 { 592f0e12668SThierry Reding compatible = "nvidia,tegra234-gpio"; 593f0e12668SThierry Reding reg-names = "security", "gpio"; 594f0e12668SThierry Reding reg = <0x02200000 0x10000>, 595f0e12668SThierry Reding <0x02210000 0x10000>; 596f0e12668SThierry Reding interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 597f0e12668SThierry Reding <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 598f0e12668SThierry Reding <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 599f0e12668SThierry Reding <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, 600f0e12668SThierry Reding <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 601f0e12668SThierry Reding <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 602f0e12668SThierry Reding <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 603f0e12668SThierry Reding <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 604f0e12668SThierry Reding <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 605f0e12668SThierry Reding <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 606f0e12668SThierry Reding <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 607f0e12668SThierry Reding <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 608f0e12668SThierry Reding <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 609f0e12668SThierry Reding <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 610f0e12668SThierry Reding <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 611f0e12668SThierry Reding <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 612f0e12668SThierry Reding <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 613f0e12668SThierry Reding <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 614f0e12668SThierry Reding <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 615f0e12668SThierry Reding <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 616f0e12668SThierry Reding <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 617f0e12668SThierry Reding <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 618f0e12668SThierry Reding <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 619f0e12668SThierry Reding <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 620f0e12668SThierry Reding <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 621f0e12668SThierry Reding <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 622f0e12668SThierry Reding <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 623f0e12668SThierry Reding <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 624f0e12668SThierry Reding <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 625f0e12668SThierry Reding <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 626f0e12668SThierry Reding <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 627f0e12668SThierry Reding <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 628f0e12668SThierry Reding <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 629f0e12668SThierry Reding <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 630f0e12668SThierry Reding <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 631f0e12668SThierry Reding <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 632f0e12668SThierry Reding <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 633f0e12668SThierry Reding <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 634f0e12668SThierry Reding <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 635f0e12668SThierry Reding <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 636f0e12668SThierry Reding <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 637f0e12668SThierry Reding <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 638f0e12668SThierry Reding <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 639f0e12668SThierry Reding <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 640f0e12668SThierry Reding <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 641f0e12668SThierry Reding <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 642f0e12668SThierry Reding <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 643f0e12668SThierry Reding <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 644f0e12668SThierry Reding #interrupt-cells = <2>; 645f0e12668SThierry Reding interrupt-controller; 646f0e12668SThierry Reding #gpio-cells = <2>; 647f0e12668SThierry Reding gpio-controller; 648f0e12668SThierry Reding }; 649f0e12668SThierry Reding 650eed280dfSThierry Reding mc: memory-controller@2c00000 { 651eed280dfSThierry Reding compatible = "nvidia,tegra234-mc"; 652000b99e5SAshish Mhetre reg = <0x02c00000 0x10000>, /* MC-SID */ 653000b99e5SAshish Mhetre <0x02c10000 0x10000>, /* MC Broadcast*/ 654000b99e5SAshish Mhetre <0x02c20000 0x10000>, /* MC0 */ 655000b99e5SAshish Mhetre <0x02c30000 0x10000>, /* MC1 */ 656000b99e5SAshish Mhetre <0x02c40000 0x10000>, /* MC2 */ 657000b99e5SAshish Mhetre <0x02c50000 0x10000>, /* MC3 */ 658000b99e5SAshish Mhetre <0x02b80000 0x10000>, /* MC4 */ 659000b99e5SAshish Mhetre <0x02b90000 0x10000>, /* MC5 */ 660000b99e5SAshish Mhetre <0x02ba0000 0x10000>, /* MC6 */ 661000b99e5SAshish Mhetre <0x02bb0000 0x10000>, /* MC7 */ 662000b99e5SAshish Mhetre <0x01700000 0x10000>, /* MC8 */ 663000b99e5SAshish Mhetre <0x01710000 0x10000>, /* MC9 */ 664000b99e5SAshish Mhetre <0x01720000 0x10000>, /* MC10 */ 665000b99e5SAshish Mhetre <0x01730000 0x10000>, /* MC11 */ 666000b99e5SAshish Mhetre <0x01740000 0x10000>, /* MC12 */ 667000b99e5SAshish Mhetre <0x01750000 0x10000>, /* MC13 */ 668000b99e5SAshish Mhetre <0x01760000 0x10000>, /* MC14 */ 669000b99e5SAshish Mhetre <0x01770000 0x10000>; /* MC15 */ 670000b99e5SAshish Mhetre reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3", 671000b99e5SAshish Mhetre "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", 672000b99e5SAshish Mhetre "ch11", "ch12", "ch13", "ch14", "ch15"; 673eed280dfSThierry Reding interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 674eed280dfSThierry Reding #interconnect-cells = <1>; 675eed280dfSThierry Reding status = "okay"; 676eed280dfSThierry Reding 677eed280dfSThierry Reding #address-cells = <2>; 678eed280dfSThierry Reding #size-cells = <2>; 679eed280dfSThierry Reding 680eed280dfSThierry Reding ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>, 681eed280dfSThierry Reding <0x02b80000 0x0 0x02b80000 0x0 0x040000>, 682eed280dfSThierry Reding <0x02c00000 0x0 0x02c00000 0x0 0x100000>; 683eed280dfSThierry Reding 684eed280dfSThierry Reding /* 685eed280dfSThierry Reding * Bit 39 of addresses passing through the memory 686eed280dfSThierry Reding * controller selects the XBAR format used when memory 687eed280dfSThierry Reding * is accessed. This is used to transparently access 688eed280dfSThierry Reding * memory in the XBAR format used by the discrete GPU 689eed280dfSThierry Reding * (bit 39 set) or Tegra (bit 39 clear). 690eed280dfSThierry Reding * 691eed280dfSThierry Reding * As a consequence, the operating system must ensure 692eed280dfSThierry Reding * that bit 39 is never used implicitly, for example 693eed280dfSThierry Reding * via an I/O virtual address mapping of an IOMMU. If 694eed280dfSThierry Reding * devices require access to the XBAR switch, their 695eed280dfSThierry Reding * drivers must set this bit explicitly. 696eed280dfSThierry Reding * 697eed280dfSThierry Reding * Limit the DMA range for memory clients to [38:0]. 698eed280dfSThierry Reding */ 699eed280dfSThierry Reding dma-ranges = <0x0 0x0 0x0 0x80 0x0>; 700eed280dfSThierry Reding 701eed280dfSThierry Reding emc: external-memory-controller@2c60000 { 702eed280dfSThierry Reding compatible = "nvidia,tegra234-emc"; 703eed280dfSThierry Reding reg = <0x0 0x02c60000 0x0 0x90000>, 704eed280dfSThierry Reding <0x0 0x01780000 0x0 0x80000>; 705eed280dfSThierry Reding interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 706eed280dfSThierry Reding clocks = <&bpmp TEGRA234_CLK_EMC>; 707eed280dfSThierry Reding clock-names = "emc"; 708eed280dfSThierry Reding status = "okay"; 709eed280dfSThierry Reding 710eed280dfSThierry Reding #interconnect-cells = <0>; 711eed280dfSThierry Reding 712eed280dfSThierry Reding nvidia,bpmp = <&bpmp>; 713eed280dfSThierry Reding }; 714eed280dfSThierry Reding }; 715eed280dfSThierry Reding 71663944891SThierry Reding uarta: serial@3100000 { 71763944891SThierry Reding compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart"; 71863944891SThierry Reding reg = <0x03100000 0x10000>; 71963944891SThierry Reding interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 72063944891SThierry Reding clocks = <&bpmp TEGRA234_CLK_UARTA>; 72163944891SThierry Reding clock-names = "serial"; 72263944891SThierry Reding resets = <&bpmp TEGRA234_RESET_UARTA>; 72363944891SThierry Reding reset-names = "serial"; 72463944891SThierry Reding status = "disabled"; 72563944891SThierry Reding }; 72663944891SThierry Reding 727156af9deSAkhil R gen1_i2c: i2c@3160000 { 728156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 729156af9deSAkhil R reg = <0x3160000 0x100>; 730156af9deSAkhil R status = "disabled"; 731156af9deSAkhil R interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 732156af9deSAkhil R clock-frequency = <400000>; 733156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C1 734156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 735156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C1>; 736156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 737156af9deSAkhil R clock-names = "div-clk", "parent"; 738156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C1>; 739156af9deSAkhil R reset-names = "i2c"; 740156af9deSAkhil R }; 741156af9deSAkhil R 742156af9deSAkhil R cam_i2c: i2c@3180000 { 743156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 744156af9deSAkhil R reg = <0x3180000 0x100>; 745156af9deSAkhil R interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 746156af9deSAkhil R status = "disabled"; 747156af9deSAkhil R clock-frequency = <400000>; 748156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C3 749156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 750156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C3>; 751156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 752156af9deSAkhil R clock-names = "div-clk", "parent"; 753156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C3>; 754156af9deSAkhil R reset-names = "i2c"; 755156af9deSAkhil R }; 756156af9deSAkhil R 757156af9deSAkhil R dp_aux_ch1_i2c: i2c@3190000 { 758156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 759156af9deSAkhil R reg = <0x3190000 0x100>; 760156af9deSAkhil R interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 761156af9deSAkhil R status = "disabled"; 762156af9deSAkhil R clock-frequency = <100000>; 763156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C4 764156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 765156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C4>; 766156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 767156af9deSAkhil R clock-names = "div-clk", "parent"; 768156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C4>; 769156af9deSAkhil R reset-names = "i2c"; 770156af9deSAkhil R }; 771156af9deSAkhil R 772156af9deSAkhil R dp_aux_ch0_i2c: i2c@31b0000 { 773156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 774156af9deSAkhil R reg = <0x31b0000 0x100>; 775156af9deSAkhil R interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 776156af9deSAkhil R status = "disabled"; 777156af9deSAkhil R clock-frequency = <100000>; 778156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C6 779156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 780156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C6>; 781156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 782156af9deSAkhil R clock-names = "div-clk", "parent"; 783156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C6>; 784156af9deSAkhil R reset-names = "i2c"; 785156af9deSAkhil R }; 786156af9deSAkhil R 787156af9deSAkhil R dp_aux_ch2_i2c: i2c@31c0000 { 788156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 789156af9deSAkhil R reg = <0x31c0000 0x100>; 790156af9deSAkhil R interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 791156af9deSAkhil R status = "disabled"; 792156af9deSAkhil R clock-frequency = <100000>; 793156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C7 794156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 795156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C7>; 796156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 797156af9deSAkhil R clock-names = "div-clk", "parent"; 798156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C7>; 799156af9deSAkhil R reset-names = "i2c"; 800156af9deSAkhil R }; 801156af9deSAkhil R 802156af9deSAkhil R dp_aux_ch3_i2c: i2c@31e0000 { 803156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 804156af9deSAkhil R reg = <0x31e0000 0x100>; 805156af9deSAkhil R interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 806156af9deSAkhil R status = "disabled"; 807156af9deSAkhil R clock-frequency = <100000>; 808156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C9 809156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 810156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C9>; 811156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 812156af9deSAkhil R clock-names = "div-clk", "parent"; 813156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C9>; 814156af9deSAkhil R reset-names = "i2c"; 815156af9deSAkhil R }; 816156af9deSAkhil R 81771f69ffaSAshish Singhal spi@3270000 { 81871f69ffaSAshish Singhal compatible = "nvidia,tegra234-qspi"; 81971f69ffaSAshish Singhal reg = <0x3270000 0x1000>; 82071f69ffaSAshish Singhal interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 82171f69ffaSAshish Singhal #address-cells = <1>; 82271f69ffaSAshish Singhal #size-cells = <0>; 82371f69ffaSAshish Singhal clocks = <&bpmp TEGRA234_CLK_QSPI0_2X_PM>, 82471f69ffaSAshish Singhal <&bpmp TEGRA234_CLK_QSPI0_PM>; 82571f69ffaSAshish Singhal clock-names = "qspi", "qspi_out"; 82671f69ffaSAshish Singhal resets = <&bpmp TEGRA234_RESET_QSPI0>; 82771f69ffaSAshish Singhal reset-names = "qspi"; 82871f69ffaSAshish Singhal status = "disabled"; 82971f69ffaSAshish Singhal }; 83071f69ffaSAshish Singhal 8315e69088dSAkhil R pwm1: pwm@3280000 { 8325e69088dSAkhil R compatible = "nvidia,tegra194-pwm", 8335e69088dSAkhil R "nvidia,tegra186-pwm"; 8345e69088dSAkhil R reg = <0x3280000 0x10000>; 8355e69088dSAkhil R clocks = <&bpmp TEGRA234_CLK_PWM1>; 8365e69088dSAkhil R clock-names = "pwm"; 8375e69088dSAkhil R resets = <&bpmp TEGRA234_RESET_PWM1>; 8385e69088dSAkhil R reset-names = "pwm"; 8395e69088dSAkhil R status = "disabled"; 8405e69088dSAkhil R #pwm-cells = <2>; 8415e69088dSAkhil R }; 8425e69088dSAkhil R 84371f69ffaSAshish Singhal spi@3300000 { 84471f69ffaSAshish Singhal compatible = "nvidia,tegra234-qspi"; 84571f69ffaSAshish Singhal reg = <0x3300000 0x1000>; 84671f69ffaSAshish Singhal interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 84771f69ffaSAshish Singhal #address-cells = <1>; 84871f69ffaSAshish Singhal #size-cells = <0>; 84971f69ffaSAshish Singhal clocks = <&bpmp TEGRA234_CLK_QSPI1_2X_PM>, 85071f69ffaSAshish Singhal <&bpmp TEGRA234_CLK_QSPI1_PM>; 85171f69ffaSAshish Singhal clock-names = "qspi", "qspi_out"; 85271f69ffaSAshish Singhal resets = <&bpmp TEGRA234_RESET_QSPI1>; 85371f69ffaSAshish Singhal reset-names = "qspi"; 85471f69ffaSAshish Singhal status = "disabled"; 85571f69ffaSAshish Singhal }; 85671f69ffaSAshish Singhal 85763944891SThierry Reding mmc@3460000 { 85863944891SThierry Reding compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci"; 85963944891SThierry Reding reg = <0x03460000 0x20000>; 86063944891SThierry Reding interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 861e086d82dSMikko Perttunen clocks = <&bpmp TEGRA234_CLK_SDMMC4>, 862e086d82dSMikko Perttunen <&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>; 863e086d82dSMikko Perttunen clock-names = "sdhci", "tmclk"; 864e086d82dSMikko Perttunen assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC4>, 865e086d82dSMikko Perttunen <&bpmp TEGRA234_CLK_PLLC4>; 866e086d82dSMikko Perttunen assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4>; 86763944891SThierry Reding resets = <&bpmp TEGRA234_RESET_SDMMC4>; 86863944891SThierry Reding reset-names = "sdhci"; 8696de481e5SThierry Reding interconnects = <&mc TEGRA234_MEMORY_CLIENT_SDMMCRAB &emc>, 8706de481e5SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_SDMMCWAB &emc>; 8716de481e5SThierry Reding interconnect-names = "dma-mem", "write"; 8725710e16aSThierry Reding iommus = <&smmu_niso1 TEGRA234_SID_SDMMC4>; 873e086d82dSMikko Perttunen nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 874e086d82dSMikko Perttunen nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 875e086d82dSMikko Perttunen nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 876e086d82dSMikko Perttunen nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; 877e086d82dSMikko Perttunen nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 878e086d82dSMikko Perttunen nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>; 879e086d82dSMikko Perttunen nvidia,default-tap = <0x8>; 880e086d82dSMikko Perttunen nvidia,default-trim = <0x14>; 881e086d82dSMikko Perttunen nvidia,dqs-trim = <40>; 882e086d82dSMikko Perttunen supports-cqe; 88363944891SThierry Reding status = "disabled"; 88463944891SThierry Reding }; 88563944891SThierry Reding 886621e12a1SMohan Kumar hda@3510000 { 887621e12a1SMohan Kumar compatible = "nvidia,tegra234-hda", "nvidia,tegra30-hda"; 888621e12a1SMohan Kumar reg = <0x3510000 0x10000>; 889621e12a1SMohan Kumar interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 890621e12a1SMohan Kumar clocks = <&bpmp TEGRA234_CLK_AZA_BIT>, 891621e12a1SMohan Kumar <&bpmp TEGRA234_CLK_AZA_2XBIT>; 892621e12a1SMohan Kumar clock-names = "hda", "hda2codec_2x"; 893621e12a1SMohan Kumar resets = <&bpmp TEGRA234_RESET_HDA>, 894621e12a1SMohan Kumar <&bpmp TEGRA234_RESET_HDACODEC>; 895621e12a1SMohan Kumar reset-names = "hda", "hda2codec_2x"; 896621e12a1SMohan Kumar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_DISP>; 897621e12a1SMohan Kumar interconnects = <&mc TEGRA234_MEMORY_CLIENT_HDAR &emc>, 898621e12a1SMohan Kumar <&mc TEGRA234_MEMORY_CLIENT_HDAW &emc>; 899621e12a1SMohan Kumar interconnect-names = "dma-mem", "write"; 900621e12a1SMohan Kumar status = "disabled"; 901621e12a1SMohan Kumar }; 902621e12a1SMohan Kumar 90363944891SThierry Reding fuse@3810000 { 90463944891SThierry Reding compatible = "nvidia,tegra234-efuse"; 90563944891SThierry Reding reg = <0x03810000 0x10000>; 90663944891SThierry Reding clocks = <&bpmp TEGRA234_CLK_FUSE>; 90763944891SThierry Reding clock-names = "fuse"; 90863944891SThierry Reding }; 90963944891SThierry Reding 91063944891SThierry Reding hsp_top0: hsp@3c00000 { 91163944891SThierry Reding compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; 91263944891SThierry Reding reg = <0x03c00000 0xa0000>; 91363944891SThierry Reding interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 91463944891SThierry Reding <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 91563944891SThierry Reding <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 91663944891SThierry Reding <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 91763944891SThierry Reding <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 91863944891SThierry Reding <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 91963944891SThierry Reding <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 92063944891SThierry Reding <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 92163944891SThierry Reding <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 92263944891SThierry Reding interrupt-names = "doorbell", "shared0", "shared1", "shared2", 92363944891SThierry Reding "shared3", "shared4", "shared5", "shared6", 92463944891SThierry Reding "shared7"; 92563944891SThierry Reding #mbox-cells = <2>; 92663944891SThierry Reding }; 92763944891SThierry Reding 9285710e16aSThierry Reding smmu_niso1: iommu@8000000 { 9295710e16aSThierry Reding compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; 9305710e16aSThierry Reding reg = <0x8000000 0x1000000>, 9315710e16aSThierry Reding <0x7000000 0x1000000>; 9325710e16aSThierry Reding interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 9335710e16aSThierry Reding <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, 9345710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 9355710e16aSThierry Reding <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, 9365710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 9375710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 9385710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 9395710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 9405710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 9415710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 9425710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 9435710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 9445710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 9455710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 9465710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 9475710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 9485710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 9495710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 9505710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 9515710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 9525710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 9535710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 9545710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 9555710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 9565710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 9575710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 9585710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 9595710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 9605710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 9615710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 9625710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 9635710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 9645710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 9655710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 9665710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 9675710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 9685710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 9695710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 9705710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 9715710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 9725710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 9735710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 9745710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 9755710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 9765710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 9775710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 9785710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 9795710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 9805710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 9815710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 9825710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 9835710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 9845710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 9855710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 9865710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 9875710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 9885710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 9895710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 9905710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 9915710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 9925710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 9935710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 9945710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 9955710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 9965710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 9975710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 9985710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 9995710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 10005710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 10015710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 10025710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 10035710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 10045710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 10055710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 10065710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 10075710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 10085710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 10095710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 10105710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 10115710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 10125710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 10135710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 10145710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 10155710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 10165710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 10175710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 10185710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 10195710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 10205710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 10215710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 10225710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 10235710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 10245710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 10255710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 10265710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 10275710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 10285710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 10295710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 10305710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 10315710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 10325710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 10335710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 10345710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 10355710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 10365710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 10375710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 10385710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 10395710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 10405710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 10415710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 10425710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 10435710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 10445710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 10455710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 10465710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 10475710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 10485710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 10495710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 10505710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 10515710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 10525710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 10535710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 10545710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 10555710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 10565710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 10575710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 10585710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 10595710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 10605710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 10615710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 10625710e16aSThierry Reding stream-match-mask = <0x7f80>; 10635710e16aSThierry Reding #global-interrupts = <2>; 10645710e16aSThierry Reding #iommu-cells = <1>; 10655710e16aSThierry Reding 10665710e16aSThierry Reding nvidia,memory-controller = <&mc>; 10675710e16aSThierry Reding status = "okay"; 10685710e16aSThierry Reding }; 10695710e16aSThierry Reding 1070302e1540SSumit Gupta sce-fabric@b600000 { 1071302e1540SSumit Gupta compatible = "nvidia,tegra234-sce-fabric"; 1072302e1540SSumit Gupta reg = <0xb600000 0x40000>; 1073302e1540SSumit Gupta interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 1074302e1540SSumit Gupta status = "okay"; 1075302e1540SSumit Gupta }; 1076302e1540SSumit Gupta 1077302e1540SSumit Gupta rce-fabric@be00000 { 1078302e1540SSumit Gupta compatible = "nvidia,tegra234-rce-fabric"; 1079302e1540SSumit Gupta reg = <0xbe00000 0x40000>; 1080302e1540SSumit Gupta interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 1081302e1540SSumit Gupta status = "okay"; 1082302e1540SSumit Gupta }; 1083302e1540SSumit Gupta 1084*ec142c44SVidya Sagar p2u_hsio_0: phy@3e00000 { 1085*ec142c44SVidya Sagar compatible = "nvidia,tegra234-p2u"; 1086*ec142c44SVidya Sagar reg = <0x03e00000 0x10000>; 1087*ec142c44SVidya Sagar reg-names = "ctl"; 1088*ec142c44SVidya Sagar 1089*ec142c44SVidya Sagar #phy-cells = <0>; 1090*ec142c44SVidya Sagar }; 1091*ec142c44SVidya Sagar 1092*ec142c44SVidya Sagar p2u_hsio_1: phy@3e10000 { 1093*ec142c44SVidya Sagar compatible = "nvidia,tegra234-p2u"; 1094*ec142c44SVidya Sagar reg = <0x03e10000 0x10000>; 1095*ec142c44SVidya Sagar reg-names = "ctl"; 1096*ec142c44SVidya Sagar 1097*ec142c44SVidya Sagar #phy-cells = <0>; 1098*ec142c44SVidya Sagar }; 1099*ec142c44SVidya Sagar 1100*ec142c44SVidya Sagar p2u_hsio_2: phy@3e20000 { 1101*ec142c44SVidya Sagar compatible = "nvidia,tegra234-p2u"; 1102*ec142c44SVidya Sagar reg = <0x03e20000 0x10000>; 1103*ec142c44SVidya Sagar reg-names = "ctl"; 1104*ec142c44SVidya Sagar 1105*ec142c44SVidya Sagar #phy-cells = <0>; 1106*ec142c44SVidya Sagar }; 1107*ec142c44SVidya Sagar 1108*ec142c44SVidya Sagar p2u_hsio_3: phy@3e30000 { 1109*ec142c44SVidya Sagar compatible = "nvidia,tegra234-p2u"; 1110*ec142c44SVidya Sagar reg = <0x03e30000 0x10000>; 1111*ec142c44SVidya Sagar reg-names = "ctl"; 1112*ec142c44SVidya Sagar 1113*ec142c44SVidya Sagar #phy-cells = <0>; 1114*ec142c44SVidya Sagar }; 1115*ec142c44SVidya Sagar 1116*ec142c44SVidya Sagar p2u_hsio_4: phy@3e40000 { 1117*ec142c44SVidya Sagar compatible = "nvidia,tegra234-p2u"; 1118*ec142c44SVidya Sagar reg = <0x03e40000 0x10000>; 1119*ec142c44SVidya Sagar reg-names = "ctl"; 1120*ec142c44SVidya Sagar 1121*ec142c44SVidya Sagar #phy-cells = <0>; 1122*ec142c44SVidya Sagar }; 1123*ec142c44SVidya Sagar 1124*ec142c44SVidya Sagar p2u_hsio_5: phy@3e50000 { 1125*ec142c44SVidya Sagar compatible = "nvidia,tegra234-p2u"; 1126*ec142c44SVidya Sagar reg = <0x03e50000 0x10000>; 1127*ec142c44SVidya Sagar reg-names = "ctl"; 1128*ec142c44SVidya Sagar 1129*ec142c44SVidya Sagar #phy-cells = <0>; 1130*ec142c44SVidya Sagar }; 1131*ec142c44SVidya Sagar 1132*ec142c44SVidya Sagar p2u_hsio_6: phy@3e60000 { 1133*ec142c44SVidya Sagar compatible = "nvidia,tegra234-p2u"; 1134*ec142c44SVidya Sagar reg = <0x03e60000 0x10000>; 1135*ec142c44SVidya Sagar reg-names = "ctl"; 1136*ec142c44SVidya Sagar 1137*ec142c44SVidya Sagar #phy-cells = <0>; 1138*ec142c44SVidya Sagar }; 1139*ec142c44SVidya Sagar 1140*ec142c44SVidya Sagar p2u_hsio_7: phy@3e70000 { 1141*ec142c44SVidya Sagar compatible = "nvidia,tegra234-p2u"; 1142*ec142c44SVidya Sagar reg = <0x03e70000 0x10000>; 1143*ec142c44SVidya Sagar reg-names = "ctl"; 1144*ec142c44SVidya Sagar 1145*ec142c44SVidya Sagar #phy-cells = <0>; 1146*ec142c44SVidya Sagar }; 1147*ec142c44SVidya Sagar 1148*ec142c44SVidya Sagar p2u_nvhs_0: phy@3e90000 { 1149*ec142c44SVidya Sagar compatible = "nvidia,tegra234-p2u"; 1150*ec142c44SVidya Sagar reg = <0x03e90000 0x10000>; 1151*ec142c44SVidya Sagar reg-names = "ctl"; 1152*ec142c44SVidya Sagar 1153*ec142c44SVidya Sagar #phy-cells = <0>; 1154*ec142c44SVidya Sagar }; 1155*ec142c44SVidya Sagar 1156*ec142c44SVidya Sagar p2u_nvhs_1: phy@3ea0000 { 1157*ec142c44SVidya Sagar compatible = "nvidia,tegra234-p2u"; 1158*ec142c44SVidya Sagar reg = <0x03ea0000 0x10000>; 1159*ec142c44SVidya Sagar reg-names = "ctl"; 1160*ec142c44SVidya Sagar 1161*ec142c44SVidya Sagar #phy-cells = <0>; 1162*ec142c44SVidya Sagar }; 1163*ec142c44SVidya Sagar 1164*ec142c44SVidya Sagar p2u_nvhs_2: phy@3eb0000 { 1165*ec142c44SVidya Sagar compatible = "nvidia,tegra234-p2u"; 1166*ec142c44SVidya Sagar reg = <0x03eb0000 0x10000>; 1167*ec142c44SVidya Sagar reg-names = "ctl"; 1168*ec142c44SVidya Sagar 1169*ec142c44SVidya Sagar #phy-cells = <0>; 1170*ec142c44SVidya Sagar }; 1171*ec142c44SVidya Sagar 1172*ec142c44SVidya Sagar p2u_nvhs_3: phy@3ec0000 { 1173*ec142c44SVidya Sagar compatible = "nvidia,tegra234-p2u"; 1174*ec142c44SVidya Sagar reg = <0x03ec0000 0x10000>; 1175*ec142c44SVidya Sagar reg-names = "ctl"; 1176*ec142c44SVidya Sagar 1177*ec142c44SVidya Sagar #phy-cells = <0>; 1178*ec142c44SVidya Sagar }; 1179*ec142c44SVidya Sagar 1180*ec142c44SVidya Sagar p2u_nvhs_4: phy@3ed0000 { 1181*ec142c44SVidya Sagar compatible = "nvidia,tegra234-p2u"; 1182*ec142c44SVidya Sagar reg = <0x03ed0000 0x10000>; 1183*ec142c44SVidya Sagar reg-names = "ctl"; 1184*ec142c44SVidya Sagar 1185*ec142c44SVidya Sagar #phy-cells = <0>; 1186*ec142c44SVidya Sagar }; 1187*ec142c44SVidya Sagar 1188*ec142c44SVidya Sagar p2u_nvhs_5: phy@3ee0000 { 1189*ec142c44SVidya Sagar compatible = "nvidia,tegra234-p2u"; 1190*ec142c44SVidya Sagar reg = <0x03ee0000 0x10000>; 1191*ec142c44SVidya Sagar reg-names = "ctl"; 1192*ec142c44SVidya Sagar 1193*ec142c44SVidya Sagar #phy-cells = <0>; 1194*ec142c44SVidya Sagar }; 1195*ec142c44SVidya Sagar 1196*ec142c44SVidya Sagar p2u_nvhs_6: phy@3ef0000 { 1197*ec142c44SVidya Sagar compatible = "nvidia,tegra234-p2u"; 1198*ec142c44SVidya Sagar reg = <0x03ef0000 0x10000>; 1199*ec142c44SVidya Sagar reg-names = "ctl"; 1200*ec142c44SVidya Sagar 1201*ec142c44SVidya Sagar #phy-cells = <0>; 1202*ec142c44SVidya Sagar }; 1203*ec142c44SVidya Sagar 1204*ec142c44SVidya Sagar p2u_nvhs_7: phy@3f00000 { 1205*ec142c44SVidya Sagar compatible = "nvidia,tegra234-p2u"; 1206*ec142c44SVidya Sagar reg = <0x03f00000 0x10000>; 1207*ec142c44SVidya Sagar reg-names = "ctl"; 1208*ec142c44SVidya Sagar 1209*ec142c44SVidya Sagar #phy-cells = <0>; 1210*ec142c44SVidya Sagar }; 1211*ec142c44SVidya Sagar 1212*ec142c44SVidya Sagar p2u_gbe_0: phy@3f20000 { 1213*ec142c44SVidya Sagar compatible = "nvidia,tegra234-p2u"; 1214*ec142c44SVidya Sagar reg = <0x03f20000 0x10000>; 1215*ec142c44SVidya Sagar reg-names = "ctl"; 1216*ec142c44SVidya Sagar 1217*ec142c44SVidya Sagar #phy-cells = <0>; 1218*ec142c44SVidya Sagar }; 1219*ec142c44SVidya Sagar 1220*ec142c44SVidya Sagar p2u_gbe_1: phy@3f30000 { 1221*ec142c44SVidya Sagar compatible = "nvidia,tegra234-p2u"; 1222*ec142c44SVidya Sagar reg = <0x03f30000 0x10000>; 1223*ec142c44SVidya Sagar reg-names = "ctl"; 1224*ec142c44SVidya Sagar 1225*ec142c44SVidya Sagar #phy-cells = <0>; 1226*ec142c44SVidya Sagar }; 1227*ec142c44SVidya Sagar 1228*ec142c44SVidya Sagar p2u_gbe_2: phy@3f40000 { 1229*ec142c44SVidya Sagar compatible = "nvidia,tegra234-p2u"; 1230*ec142c44SVidya Sagar reg = <0x03f40000 0x10000>; 1231*ec142c44SVidya Sagar reg-names = "ctl"; 1232*ec142c44SVidya Sagar 1233*ec142c44SVidya Sagar #phy-cells = <0>; 1234*ec142c44SVidya Sagar }; 1235*ec142c44SVidya Sagar 1236*ec142c44SVidya Sagar p2u_gbe_3: phy@3f50000 { 1237*ec142c44SVidya Sagar compatible = "nvidia,tegra234-p2u"; 1238*ec142c44SVidya Sagar reg = <0x03f50000 0x10000>; 1239*ec142c44SVidya Sagar reg-names = "ctl"; 1240*ec142c44SVidya Sagar 1241*ec142c44SVidya Sagar #phy-cells = <0>; 1242*ec142c44SVidya Sagar }; 1243*ec142c44SVidya Sagar 1244*ec142c44SVidya Sagar p2u_gbe_4: phy@3f60000 { 1245*ec142c44SVidya Sagar compatible = "nvidia,tegra234-p2u"; 1246*ec142c44SVidya Sagar reg = <0x03f60000 0x10000>; 1247*ec142c44SVidya Sagar reg-names = "ctl"; 1248*ec142c44SVidya Sagar 1249*ec142c44SVidya Sagar #phy-cells = <0>; 1250*ec142c44SVidya Sagar }; 1251*ec142c44SVidya Sagar 1252*ec142c44SVidya Sagar p2u_gbe_5: phy@3f70000 { 1253*ec142c44SVidya Sagar compatible = "nvidia,tegra234-p2u"; 1254*ec142c44SVidya Sagar reg = <0x03f70000 0x10000>; 1255*ec142c44SVidya Sagar reg-names = "ctl"; 1256*ec142c44SVidya Sagar 1257*ec142c44SVidya Sagar #phy-cells = <0>; 1258*ec142c44SVidya Sagar }; 1259*ec142c44SVidya Sagar 1260*ec142c44SVidya Sagar p2u_gbe_6: phy@3f80000 { 1261*ec142c44SVidya Sagar compatible = "nvidia,tegra234-p2u"; 1262*ec142c44SVidya Sagar reg = <0x03f80000 0x10000>; 1263*ec142c44SVidya Sagar reg-names = "ctl"; 1264*ec142c44SVidya Sagar 1265*ec142c44SVidya Sagar #phy-cells = <0>; 1266*ec142c44SVidya Sagar }; 1267*ec142c44SVidya Sagar 1268*ec142c44SVidya Sagar p2u_gbe_7: phy@3f90000 { 1269*ec142c44SVidya Sagar compatible = "nvidia,tegra234-p2u"; 1270*ec142c44SVidya Sagar reg = <0x03f90000 0x10000>; 1271*ec142c44SVidya Sagar reg-names = "ctl"; 1272*ec142c44SVidya Sagar 1273*ec142c44SVidya Sagar #phy-cells = <0>; 1274*ec142c44SVidya Sagar }; 1275*ec142c44SVidya Sagar 127663944891SThierry Reding hsp_aon: hsp@c150000 { 127763944891SThierry Reding compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; 127863944891SThierry Reding reg = <0x0c150000 0x90000>; 127963944891SThierry Reding interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 128063944891SThierry Reding <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 128163944891SThierry Reding <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 128263944891SThierry Reding <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 128363944891SThierry Reding /* 128463944891SThierry Reding * Shared interrupt 0 is routed only to AON/SPE, so 128563944891SThierry Reding * we only have 4 shared interrupts for the CCPLEX. 128663944891SThierry Reding */ 128763944891SThierry Reding interrupt-names = "shared1", "shared2", "shared3", "shared4"; 128863944891SThierry Reding #mbox-cells = <2>; 128963944891SThierry Reding }; 129063944891SThierry Reding 1291156af9deSAkhil R gen2_i2c: i2c@c240000 { 1292156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 1293156af9deSAkhil R reg = <0xc240000 0x100>; 1294156af9deSAkhil R interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1295156af9deSAkhil R status = "disabled"; 1296156af9deSAkhil R clock-frequency = <100000>; 1297156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C2 1298156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 1299156af9deSAkhil R clock-names = "div-clk", "parent"; 1300156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C2>; 1301156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 1302156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C2>; 1303156af9deSAkhil R reset-names = "i2c"; 1304156af9deSAkhil R }; 1305156af9deSAkhil R 1306156af9deSAkhil R gen8_i2c: i2c@c250000 { 1307156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 1308156af9deSAkhil R reg = <0xc250000 0x100>; 1309156af9deSAkhil R nvidia,hw-instance-id = <0x7>; 1310156af9deSAkhil R interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1311156af9deSAkhil R status = "disabled"; 1312156af9deSAkhil R clock-frequency = <400000>; 1313156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C8 1314156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 1315156af9deSAkhil R clock-names = "div-clk", "parent"; 1316156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C8>; 1317156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 1318156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C8>; 1319156af9deSAkhil R reset-names = "i2c"; 1320156af9deSAkhil R }; 1321156af9deSAkhil R 132263944891SThierry Reding rtc@c2a0000 { 132363944891SThierry Reding compatible = "nvidia,tegra234-rtc", "nvidia,tegra20-rtc"; 132463944891SThierry Reding reg = <0x0c2a0000 0x10000>; 132563944891SThierry Reding interrupt-parent = <&pmc>; 132663944891SThierry Reding interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 1327e537addeSMikko Perttunen clocks = <&bpmp TEGRA234_CLK_CLK_32K>; 1328e537addeSMikko Perttunen clock-names = "rtc"; 132963944891SThierry Reding status = "disabled"; 133063944891SThierry Reding }; 133163944891SThierry Reding 1332f0e12668SThierry Reding gpio_aon: gpio@c2f0000 { 1333f0e12668SThierry Reding compatible = "nvidia,tegra234-gpio-aon"; 1334f0e12668SThierry Reding reg-names = "security", "gpio"; 1335f0e12668SThierry Reding reg = <0x0c2f0000 0x1000>, 1336f0e12668SThierry Reding <0x0c2f1000 0x1000>; 1337f0e12668SThierry Reding interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1338f0e12668SThierry Reding <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1339f0e12668SThierry Reding <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1340f0e12668SThierry Reding <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 1341f0e12668SThierry Reding #interrupt-cells = <2>; 1342f0e12668SThierry Reding interrupt-controller; 1343f0e12668SThierry Reding #gpio-cells = <2>; 1344f0e12668SThierry Reding gpio-controller; 1345f0e12668SThierry Reding }; 1346f0e12668SThierry Reding 134763944891SThierry Reding pmc: pmc@c360000 { 134863944891SThierry Reding compatible = "nvidia,tegra234-pmc"; 134963944891SThierry Reding reg = <0x0c360000 0x10000>, 135063944891SThierry Reding <0x0c370000 0x10000>, 135163944891SThierry Reding <0x0c380000 0x10000>, 135263944891SThierry Reding <0x0c390000 0x10000>, 135363944891SThierry Reding <0x0c3a0000 0x10000>; 135463944891SThierry Reding reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 135563944891SThierry Reding 135663944891SThierry Reding #interrupt-cells = <2>; 135763944891SThierry Reding interrupt-controller; 135863944891SThierry Reding }; 135963944891SThierry Reding 1360302e1540SSumit Gupta aon-fabric@c600000 { 1361302e1540SSumit Gupta compatible = "nvidia,tegra234-aon-fabric"; 1362302e1540SSumit Gupta reg = <0xc600000 0x40000>; 1363302e1540SSumit Gupta interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 1364302e1540SSumit Gupta status = "okay"; 1365302e1540SSumit Gupta }; 1366302e1540SSumit Gupta 1367302e1540SSumit Gupta bpmp-fabric@d600000 { 1368302e1540SSumit Gupta compatible = "nvidia,tegra234-bpmp-fabric"; 1369302e1540SSumit Gupta reg = <0xd600000 0x40000>; 1370302e1540SSumit Gupta interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1371302e1540SSumit Gupta status = "okay"; 1372302e1540SSumit Gupta }; 1373302e1540SSumit Gupta 1374302e1540SSumit Gupta dce-fabric@de00000 { 1375302e1540SSumit Gupta compatible = "nvidia,tegra234-sce-fabric"; 1376302e1540SSumit Gupta reg = <0xde00000 0x40000>; 1377302e1540SSumit Gupta interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>; 1378302e1540SSumit Gupta status = "okay"; 1379302e1540SSumit Gupta }; 1380302e1540SSumit Gupta 138163944891SThierry Reding gic: interrupt-controller@f400000 { 138263944891SThierry Reding compatible = "arm,gic-v3"; 138363944891SThierry Reding reg = <0x0f400000 0x010000>, /* GICD */ 138463944891SThierry Reding <0x0f440000 0x200000>; /* GICR */ 138563944891SThierry Reding interrupt-parent = <&gic>; 138663944891SThierry Reding interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 138763944891SThierry Reding 138863944891SThierry Reding #redistributor-regions = <1>; 138963944891SThierry Reding #interrupt-cells = <3>; 139063944891SThierry Reding interrupt-controller; 139163944891SThierry Reding }; 13925710e16aSThierry Reding 13935710e16aSThierry Reding smmu_iso: iommu@10000000{ 13945710e16aSThierry Reding compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; 13955710e16aSThierry Reding reg = <0x10000000 0x1000000>; 13965710e16aSThierry Reding interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 13975710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 13985710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 13995710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14005710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14015710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14025710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14035710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14045710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14055710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14065710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14075710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14085710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14095710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14105710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14115710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14125710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14135710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14145710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14155710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14165710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14175710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14185710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14195710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14205710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14215710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14225710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14235710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14245710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14255710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14265710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14275710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14285710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14295710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14305710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14315710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14325710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14335710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14345710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14355710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14365710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14375710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14385710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14395710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14405710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14415710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14425710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14435710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14445710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14455710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14465710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14475710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14485710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14495710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14505710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14515710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14525710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14535710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14545710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14555710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14565710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14575710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14585710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14595710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14605710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14615710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14625710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14635710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14645710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14655710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14665710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14675710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14685710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14695710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14705710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14715710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14725710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14735710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14745710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14755710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14765710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14775710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14785710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14795710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14805710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14815710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14825710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14835710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14845710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14855710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14865710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14875710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14885710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14895710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14905710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14915710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14925710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14935710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14945710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14955710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14965710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14975710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14985710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 14995710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 15005710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 15015710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 15025710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 15035710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 15045710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 15055710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 15065710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 15075710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 15085710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 15095710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 15105710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 15115710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 15125710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 15135710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 15145710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 15155710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 15165710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 15175710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 15185710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 15195710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 15205710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 15215710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 15225710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 15235710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 15245710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 15255710e16aSThierry Reding stream-match-mask = <0x7f80>; 15265710e16aSThierry Reding #global-interrupts = <1>; 15275710e16aSThierry Reding #iommu-cells = <1>; 15285710e16aSThierry Reding 15295710e16aSThierry Reding nvidia,memory-controller = <&mc>; 15305710e16aSThierry Reding status = "okay"; 15315710e16aSThierry Reding }; 15325710e16aSThierry Reding 15335710e16aSThierry Reding smmu_niso0: iommu@12000000 { 15345710e16aSThierry Reding compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; 15355710e16aSThierry Reding reg = <0x12000000 0x1000000>, 15365710e16aSThierry Reding <0x11000000 0x1000000>; 15375710e16aSThierry Reding interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 15385710e16aSThierry Reding <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 15395710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 15405710e16aSThierry Reding <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 15415710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 15425710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 15435710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 15445710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 15455710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 15465710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 15475710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 15485710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 15495710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 15505710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 15515710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 15525710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 15535710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 15545710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 15555710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 15565710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 15575710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 15585710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 15595710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 15605710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 15615710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 15625710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 15635710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 15645710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 15655710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 15665710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 15675710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 15685710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 15695710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 15705710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 15715710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 15725710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 15735710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 15745710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 15755710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 15765710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 15775710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 15785710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 15795710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 15805710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 15815710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 15825710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 15835710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 15845710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 15855710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 15865710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 15875710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 15885710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 15895710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 15905710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 15915710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 15925710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 15935710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 15945710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 15955710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 15965710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 15975710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 15985710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 15995710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 16005710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 16015710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 16025710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 16035710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 16045710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 16055710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 16065710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 16075710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 16085710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 16095710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 16105710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 16115710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 16125710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 16135710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 16145710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 16155710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 16165710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 16175710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 16185710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 16195710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 16205710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 16215710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 16225710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 16235710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 16245710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 16255710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 16265710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 16275710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 16285710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 16295710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 16305710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 16315710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 16325710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 16335710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 16345710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 16355710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 16365710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 16375710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 16385710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 16395710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 16405710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 16415710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 16425710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 16435710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 16445710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 16455710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 16465710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 16475710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 16485710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 16495710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 16505710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 16515710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 16525710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 16535710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 16545710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 16555710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 16565710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 16575710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 16585710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 16595710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 16605710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 16615710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 16625710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 16635710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 16645710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 16655710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 16665710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 16675710e16aSThierry Reding stream-match-mask = <0x7f80>; 16685710e16aSThierry Reding #global-interrupts = <2>; 16695710e16aSThierry Reding #iommu-cells = <1>; 16705710e16aSThierry Reding 16715710e16aSThierry Reding nvidia,memory-controller = <&mc>; 16725710e16aSThierry Reding status = "okay"; 16735710e16aSThierry Reding }; 1674302e1540SSumit Gupta 1675302e1540SSumit Gupta cbb-fabric@13a00000 { 1676302e1540SSumit Gupta compatible = "nvidia,tegra234-cbb-fabric"; 1677302e1540SSumit Gupta reg = <0x13a00000 0x400000>; 1678302e1540SSumit Gupta interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 1679302e1540SSumit Gupta status = "okay"; 1680302e1540SSumit Gupta }; 168163944891SThierry Reding }; 168263944891SThierry Reding 1683962c400dSSumit Gupta ccplex@e000000 { 1684962c400dSSumit Gupta compatible = "nvidia,tegra234-ccplex-cluster"; 1685962c400dSSumit Gupta reg = <0x0 0x0e000000 0x0 0x5ffff>; 1686962c400dSSumit Gupta nvidia,bpmp = <&bpmp>; 1687962c400dSSumit Gupta status = "okay"; 1688962c400dSSumit Gupta }; 1689962c400dSSumit Gupta 1690*ec142c44SVidya Sagar pcie@140a0000 { 1691*ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie"; 1692*ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CA>; 1693*ec142c44SVidya Sagar reg = <0x00 0x140a0000 0x0 0x00020000>, /* appl registers (128K) */ 1694*ec142c44SVidya Sagar <0x00 0x2a000000 0x0 0x00040000>, /* configuration space (256K) */ 1695*ec142c44SVidya Sagar <0x00 0x2a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1696*ec142c44SVidya Sagar <0x00 0x2a080000 0x0 0x00040000>; /* DBI reg space (256K) */ 1697*ec142c44SVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 1698*ec142c44SVidya Sagar 1699*ec142c44SVidya Sagar #address-cells = <3>; 1700*ec142c44SVidya Sagar #size-cells = <2>; 1701*ec142c44SVidya Sagar device_type = "pci"; 1702*ec142c44SVidya Sagar num-lanes = <4>; 1703*ec142c44SVidya Sagar num-viewport = <8>; 1704*ec142c44SVidya Sagar linux,pci-domain = <8>; 1705*ec142c44SVidya Sagar 1706*ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX2_C8_CORE>; 1707*ec142c44SVidya Sagar clock-names = "core"; 1708*ec142c44SVidya Sagar 1709*ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX2_CORE_8_APB>, 1710*ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX2_CORE_8>; 1711*ec142c44SVidya Sagar reset-names = "apb", "core"; 1712*ec142c44SVidya Sagar 1713*ec142c44SVidya Sagar interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1714*ec142c44SVidya Sagar <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1715*ec142c44SVidya Sagar interrupt-names = "intr", "msi"; 1716*ec142c44SVidya Sagar 1717*ec142c44SVidya Sagar #interrupt-cells = <1>; 1718*ec142c44SVidya Sagar interrupt-map-mask = <0 0 0 0>; 1719*ec142c44SVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1720*ec142c44SVidya Sagar 1721*ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 8>; 1722*ec142c44SVidya Sagar 1723*ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 1724*ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 1725*ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 1726*ec142c44SVidya Sagar 1727*ec142c44SVidya Sagar bus-range = <0x0 0xff>; 1728*ec142c44SVidya Sagar 1729*ec142c44SVidya Sagar ranges = <0x43000000 0x32 0x40000000 0x32 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 1730*ec142c44SVidya Sagar <0x02000000 0x0 0x40000000 0x35 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 1731*ec142c44SVidya Sagar <0x01000000 0x0 0x2a100000 0x00 0x2a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 1732*ec142c44SVidya Sagar 1733*ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE8AR &emc>, 1734*ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE8AW &emc>; 1735*ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 1736*ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE8 0x1000>; 1737*ec142c44SVidya Sagar iommu-map-mask = <0x0>; 1738*ec142c44SVidya Sagar dma-coherent; 1739*ec142c44SVidya Sagar 1740*ec142c44SVidya Sagar status = "disabled"; 1741*ec142c44SVidya Sagar }; 1742*ec142c44SVidya Sagar 1743*ec142c44SVidya Sagar pcie@140c0000 { 1744*ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie"; 1745*ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CB>; 1746*ec142c44SVidya Sagar reg = <0x00 0x140c0000 0x0 0x00020000>, /* appl registers (128K) */ 1747*ec142c44SVidya Sagar <0x00 0x2c000000 0x0 0x00040000>, /* configuration space (256K) */ 1748*ec142c44SVidya Sagar <0x00 0x2c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1749*ec142c44SVidya Sagar <0x00 0x2c080000 0x0 0x00040000>; /* DBI reg space (256K) */ 1750*ec142c44SVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 1751*ec142c44SVidya Sagar 1752*ec142c44SVidya Sagar #address-cells = <3>; 1753*ec142c44SVidya Sagar #size-cells = <2>; 1754*ec142c44SVidya Sagar device_type = "pci"; 1755*ec142c44SVidya Sagar num-lanes = <4>; 1756*ec142c44SVidya Sagar num-viewport = <8>; 1757*ec142c44SVidya Sagar linux,pci-domain = <9>; 1758*ec142c44SVidya Sagar 1759*ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX2_C9_CORE>; 1760*ec142c44SVidya Sagar clock-names = "core"; 1761*ec142c44SVidya Sagar 1762*ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX2_CORE_9_APB>, 1763*ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX2_CORE_9>; 1764*ec142c44SVidya Sagar reset-names = "apb", "core"; 1765*ec142c44SVidya Sagar 1766*ec142c44SVidya Sagar interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1767*ec142c44SVidya Sagar <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1768*ec142c44SVidya Sagar interrupt-names = "intr", "msi"; 1769*ec142c44SVidya Sagar 1770*ec142c44SVidya Sagar #interrupt-cells = <1>; 1771*ec142c44SVidya Sagar interrupt-map-mask = <0 0 0 0>; 1772*ec142c44SVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1773*ec142c44SVidya Sagar 1774*ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 9>; 1775*ec142c44SVidya Sagar 1776*ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 1777*ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 1778*ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 1779*ec142c44SVidya Sagar 1780*ec142c44SVidya Sagar bus-range = <0x0 0xff>; 1781*ec142c44SVidya Sagar 1782*ec142c44SVidya Sagar ranges = <0x43000000 0x35 0x40000000 0x35 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 1783*ec142c44SVidya Sagar <0x02000000 0x0 0x40000000 0x38 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 1784*ec142c44SVidya Sagar <0x01000000 0x0 0x2c100000 0x00 0x2c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 1785*ec142c44SVidya Sagar 1786*ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE9AR &emc>, 1787*ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE9AW &emc>; 1788*ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 1789*ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE9 0x1000>; 1790*ec142c44SVidya Sagar iommu-map-mask = <0x0>; 1791*ec142c44SVidya Sagar dma-coherent; 1792*ec142c44SVidya Sagar 1793*ec142c44SVidya Sagar status = "disabled"; 1794*ec142c44SVidya Sagar }; 1795*ec142c44SVidya Sagar 1796*ec142c44SVidya Sagar pcie@140e0000 { 1797*ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie"; 1798*ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CC>; 1799*ec142c44SVidya Sagar reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K) */ 1800*ec142c44SVidya Sagar <0x00 0x2e000000 0x0 0x00040000>, /* configuration space (256K) */ 1801*ec142c44SVidya Sagar <0x00 0x2e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1802*ec142c44SVidya Sagar <0x00 0x2e080000 0x0 0x00040000>; /* DBI reg space (256K) */ 1803*ec142c44SVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 1804*ec142c44SVidya Sagar 1805*ec142c44SVidya Sagar #address-cells = <3>; 1806*ec142c44SVidya Sagar #size-cells = <2>; 1807*ec142c44SVidya Sagar device_type = "pci"; 1808*ec142c44SVidya Sagar num-lanes = <4>; 1809*ec142c44SVidya Sagar num-viewport = <8>; 1810*ec142c44SVidya Sagar linux,pci-domain = <10>; 1811*ec142c44SVidya Sagar 1812*ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX2_C10_CORE>; 1813*ec142c44SVidya Sagar clock-names = "core"; 1814*ec142c44SVidya Sagar 1815*ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX2_CORE_10_APB>, 1816*ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX2_CORE_10>; 1817*ec142c44SVidya Sagar reset-names = "apb", "core"; 1818*ec142c44SVidya Sagar 1819*ec142c44SVidya Sagar interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1820*ec142c44SVidya Sagar <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1821*ec142c44SVidya Sagar interrupt-names = "intr", "msi"; 1822*ec142c44SVidya Sagar 1823*ec142c44SVidya Sagar #interrupt-cells = <1>; 1824*ec142c44SVidya Sagar interrupt-map-mask = <0 0 0 0>; 1825*ec142c44SVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1826*ec142c44SVidya Sagar 1827*ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 10>; 1828*ec142c44SVidya Sagar 1829*ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 1830*ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 1831*ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 1832*ec142c44SVidya Sagar 1833*ec142c44SVidya Sagar bus-range = <0x0 0xff>; 1834*ec142c44SVidya Sagar 1835*ec142c44SVidya Sagar ranges = <0x43000000 0x38 0x40000000 0x38 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 1836*ec142c44SVidya Sagar <0x02000000 0x0 0x40000000 0x3b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 1837*ec142c44SVidya Sagar <0x01000000 0x0 0x2e100000 0x00 0x2e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 1838*ec142c44SVidya Sagar 1839*ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE10AR &emc>, 1840*ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE10AW &emc>; 1841*ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 1842*ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>; 1843*ec142c44SVidya Sagar iommu-map-mask = <0x0>; 1844*ec142c44SVidya Sagar dma-coherent; 1845*ec142c44SVidya Sagar 1846*ec142c44SVidya Sagar status = "disabled"; 1847*ec142c44SVidya Sagar }; 1848*ec142c44SVidya Sagar 1849*ec142c44SVidya Sagar pcie@14100000 { 1850*ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie"; 1851*ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>; 1852*ec142c44SVidya Sagar reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */ 1853*ec142c44SVidya Sagar <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */ 1854*ec142c44SVidya Sagar <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1855*ec142c44SVidya Sagar <0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */ 1856*ec142c44SVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 1857*ec142c44SVidya Sagar 1858*ec142c44SVidya Sagar #address-cells = <3>; 1859*ec142c44SVidya Sagar #size-cells = <2>; 1860*ec142c44SVidya Sagar device_type = "pci"; 1861*ec142c44SVidya Sagar num-lanes = <1>; 1862*ec142c44SVidya Sagar num-viewport = <8>; 1863*ec142c44SVidya Sagar linux,pci-domain = <1>; 1864*ec142c44SVidya Sagar 1865*ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX0_C1_CORE>; 1866*ec142c44SVidya Sagar clock-names = "core"; 1867*ec142c44SVidya Sagar 1868*ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX0_CORE_1_APB>, 1869*ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX0_CORE_1>; 1870*ec142c44SVidya Sagar reset-names = "apb", "core"; 1871*ec142c44SVidya Sagar 1872*ec142c44SVidya Sagar interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1873*ec142c44SVidya Sagar <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1874*ec142c44SVidya Sagar interrupt-names = "intr", "msi"; 1875*ec142c44SVidya Sagar 1876*ec142c44SVidya Sagar #interrupt-cells = <1>; 1877*ec142c44SVidya Sagar interrupt-map-mask = <0 0 0 0>; 1878*ec142c44SVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1879*ec142c44SVidya Sagar 1880*ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 1>; 1881*ec142c44SVidya Sagar 1882*ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 1883*ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 1884*ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 1885*ec142c44SVidya Sagar 1886*ec142c44SVidya Sagar bus-range = <0x0 0xff>; 1887*ec142c44SVidya Sagar 1888*ec142c44SVidya Sagar ranges = <0x43000000 0x20 0x80000000 0x20 0x80000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ 1889*ec142c44SVidya Sagar <0x02000000 0x0 0x40000000 0x20 0xa8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 1890*ec142c44SVidya Sagar <0x01000000 0x0 0x30100000 0x00 0x30100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 1891*ec142c44SVidya Sagar 1892*ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE1R &emc>, 1893*ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE1W &emc>; 1894*ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 1895*ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE1 0x1000>; 1896*ec142c44SVidya Sagar iommu-map-mask = <0x0>; 1897*ec142c44SVidya Sagar dma-coherent; 1898*ec142c44SVidya Sagar 1899*ec142c44SVidya Sagar status = "disabled"; 1900*ec142c44SVidya Sagar }; 1901*ec142c44SVidya Sagar 1902*ec142c44SVidya Sagar pcie@14120000 { 1903*ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie"; 1904*ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>; 1905*ec142c44SVidya Sagar reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */ 1906*ec142c44SVidya Sagar <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */ 1907*ec142c44SVidya Sagar <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1908*ec142c44SVidya Sagar <0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */ 1909*ec142c44SVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 1910*ec142c44SVidya Sagar 1911*ec142c44SVidya Sagar #address-cells = <3>; 1912*ec142c44SVidya Sagar #size-cells = <2>; 1913*ec142c44SVidya Sagar device_type = "pci"; 1914*ec142c44SVidya Sagar num-lanes = <1>; 1915*ec142c44SVidya Sagar num-viewport = <8>; 1916*ec142c44SVidya Sagar linux,pci-domain = <2>; 1917*ec142c44SVidya Sagar 1918*ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX0_C2_CORE>; 1919*ec142c44SVidya Sagar clock-names = "core"; 1920*ec142c44SVidya Sagar 1921*ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX0_CORE_2_APB>, 1922*ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX0_CORE_2>; 1923*ec142c44SVidya Sagar reset-names = "apb", "core"; 1924*ec142c44SVidya Sagar 1925*ec142c44SVidya Sagar interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1926*ec142c44SVidya Sagar <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1927*ec142c44SVidya Sagar interrupt-names = "intr", "msi"; 1928*ec142c44SVidya Sagar 1929*ec142c44SVidya Sagar #interrupt-cells = <1>; 1930*ec142c44SVidya Sagar interrupt-map-mask = <0 0 0 0>; 1931*ec142c44SVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 1932*ec142c44SVidya Sagar 1933*ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 2>; 1934*ec142c44SVidya Sagar 1935*ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 1936*ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 1937*ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 1938*ec142c44SVidya Sagar 1939*ec142c44SVidya Sagar bus-range = <0x0 0xff>; 1940*ec142c44SVidya Sagar 1941*ec142c44SVidya Sagar ranges = <0x43000000 0x20 0xc0000000 0x20 0xc0000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ 1942*ec142c44SVidya Sagar <0x02000000 0x0 0x40000000 0x20 0xe8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 1943*ec142c44SVidya Sagar <0x01000000 0x0 0x32100000 0x00 0x32100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 1944*ec142c44SVidya Sagar 1945*ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE2AR &emc>, 1946*ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE2AW &emc>; 1947*ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 1948*ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE2 0x1000>; 1949*ec142c44SVidya Sagar iommu-map-mask = <0x0>; 1950*ec142c44SVidya Sagar dma-coherent; 1951*ec142c44SVidya Sagar 1952*ec142c44SVidya Sagar status = "disabled"; 1953*ec142c44SVidya Sagar }; 1954*ec142c44SVidya Sagar 1955*ec142c44SVidya Sagar pcie@14140000 { 1956*ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie"; 1957*ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>; 1958*ec142c44SVidya Sagar reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */ 1959*ec142c44SVidya Sagar <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */ 1960*ec142c44SVidya Sagar <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1961*ec142c44SVidya Sagar <0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */ 1962*ec142c44SVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 1963*ec142c44SVidya Sagar 1964*ec142c44SVidya Sagar #address-cells = <3>; 1965*ec142c44SVidya Sagar #size-cells = <2>; 1966*ec142c44SVidya Sagar device_type = "pci"; 1967*ec142c44SVidya Sagar num-lanes = <1>; 1968*ec142c44SVidya Sagar num-viewport = <8>; 1969*ec142c44SVidya Sagar linux,pci-domain = <3>; 1970*ec142c44SVidya Sagar 1971*ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX0_C3_CORE>; 1972*ec142c44SVidya Sagar clock-names = "core"; 1973*ec142c44SVidya Sagar 1974*ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX0_CORE_3_APB>, 1975*ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX0_CORE_3>; 1976*ec142c44SVidya Sagar reset-names = "apb", "core"; 1977*ec142c44SVidya Sagar 1978*ec142c44SVidya Sagar interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1979*ec142c44SVidya Sagar <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1980*ec142c44SVidya Sagar interrupt-names = "intr", "msi"; 1981*ec142c44SVidya Sagar 1982*ec142c44SVidya Sagar #interrupt-cells = <1>; 1983*ec142c44SVidya Sagar interrupt-map-mask = <0 0 0 0>; 1984*ec142c44SVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 1985*ec142c44SVidya Sagar 1986*ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 3>; 1987*ec142c44SVidya Sagar 1988*ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 1989*ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 1990*ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 1991*ec142c44SVidya Sagar 1992*ec142c44SVidya Sagar bus-range = <0x0 0xff>; 1993*ec142c44SVidya Sagar 1994*ec142c44SVidya Sagar ranges = <0x43000000 0x21 0x00000000 0x21 0x00000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ 1995*ec142c44SVidya Sagar <0x02000000 0x0 0x40000000 0x21 0xe8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 1996*ec142c44SVidya Sagar <0x01000000 0x0 0x34100000 0x00 0x34100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 1997*ec142c44SVidya Sagar 1998*ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE3R &emc>, 1999*ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE3W &emc>; 2000*ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2001*ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE3 0x1000>; 2002*ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2003*ec142c44SVidya Sagar dma-coherent; 2004*ec142c44SVidya Sagar 2005*ec142c44SVidya Sagar status = "disabled"; 2006*ec142c44SVidya Sagar }; 2007*ec142c44SVidya Sagar 2008*ec142c44SVidya Sagar pcie@14160000 { 2009*ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie"; 2010*ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BB>; 2011*ec142c44SVidya Sagar reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2012*ec142c44SVidya Sagar <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ 2013*ec142c44SVidya Sagar <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2014*ec142c44SVidya Sagar <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2015*ec142c44SVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 2016*ec142c44SVidya Sagar 2017*ec142c44SVidya Sagar #address-cells = <3>; 2018*ec142c44SVidya Sagar #size-cells = <2>; 2019*ec142c44SVidya Sagar device_type = "pci"; 2020*ec142c44SVidya Sagar num-lanes = <4>; 2021*ec142c44SVidya Sagar num-viewport = <8>; 2022*ec142c44SVidya Sagar linux,pci-domain = <4>; 2023*ec142c44SVidya Sagar 2024*ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX0_C4_CORE>; 2025*ec142c44SVidya Sagar clock-names = "core"; 2026*ec142c44SVidya Sagar 2027*ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX0_CORE_4_APB>, 2028*ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX0_CORE_4>; 2029*ec142c44SVidya Sagar reset-names = "apb", "core"; 2030*ec142c44SVidya Sagar 2031*ec142c44SVidya Sagar interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2032*ec142c44SVidya Sagar <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2033*ec142c44SVidya Sagar interrupt-names = "intr", "msi"; 2034*ec142c44SVidya Sagar 2035*ec142c44SVidya Sagar #interrupt-cells = <1>; 2036*ec142c44SVidya Sagar interrupt-map-mask = <0 0 0 0>; 2037*ec142c44SVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 2038*ec142c44SVidya Sagar 2039*ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 4>; 2040*ec142c44SVidya Sagar 2041*ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2042*ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2043*ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2044*ec142c44SVidya Sagar 2045*ec142c44SVidya Sagar bus-range = <0x0 0xff>; 2046*ec142c44SVidya Sagar 2047*ec142c44SVidya Sagar ranges = <0x43000000 0x21 0x40000000 0x21 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2048*ec142c44SVidya Sagar <0x02000000 0x0 0x40000000 0x24 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2049*ec142c44SVidya Sagar <0x01000000 0x0 0x36100000 0x00 0x36100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2050*ec142c44SVidya Sagar 2051*ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE4R &emc>, 2052*ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE4W &emc>; 2053*ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2054*ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE4 0x1000>; 2055*ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2056*ec142c44SVidya Sagar dma-coherent; 2057*ec142c44SVidya Sagar 2058*ec142c44SVidya Sagar status = "disabled"; 2059*ec142c44SVidya Sagar }; 2060*ec142c44SVidya Sagar 2061*ec142c44SVidya Sagar pcie@14180000 { 2062*ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie"; 2063*ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BA>; 2064*ec142c44SVidya Sagar reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2065*ec142c44SVidya Sagar <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ 2066*ec142c44SVidya Sagar <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2067*ec142c44SVidya Sagar <0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2068*ec142c44SVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 2069*ec142c44SVidya Sagar 2070*ec142c44SVidya Sagar #address-cells = <3>; 2071*ec142c44SVidya Sagar #size-cells = <2>; 2072*ec142c44SVidya Sagar device_type = "pci"; 2073*ec142c44SVidya Sagar num-lanes = <4>; 2074*ec142c44SVidya Sagar num-viewport = <8>; 2075*ec142c44SVidya Sagar linux,pci-domain = <0>; 2076*ec142c44SVidya Sagar 2077*ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX0_C0_CORE>; 2078*ec142c44SVidya Sagar clock-names = "core"; 2079*ec142c44SVidya Sagar 2080*ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX0_CORE_0_APB>, 2081*ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX0_CORE_0>; 2082*ec142c44SVidya Sagar reset-names = "apb", "core"; 2083*ec142c44SVidya Sagar 2084*ec142c44SVidya Sagar interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2085*ec142c44SVidya Sagar <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2086*ec142c44SVidya Sagar interrupt-names = "intr", "msi"; 2087*ec142c44SVidya Sagar 2088*ec142c44SVidya Sagar #interrupt-cells = <1>; 2089*ec142c44SVidya Sagar interrupt-map-mask = <0 0 0 0>; 2090*ec142c44SVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 2091*ec142c44SVidya Sagar 2092*ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 0>; 2093*ec142c44SVidya Sagar 2094*ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2095*ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2096*ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2097*ec142c44SVidya Sagar 2098*ec142c44SVidya Sagar bus-range = <0x0 0xff>; 2099*ec142c44SVidya Sagar 2100*ec142c44SVidya Sagar ranges = <0x43000000 0x24 0x40000000 0x24 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2101*ec142c44SVidya Sagar <0x02000000 0x0 0x40000000 0x27 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2102*ec142c44SVidya Sagar <0x01000000 0x0 0x38100000 0x00 0x38100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2103*ec142c44SVidya Sagar 2104*ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE0R &emc>, 2105*ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE0W &emc>; 2106*ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2107*ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE0 0x1000>; 2108*ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2109*ec142c44SVidya Sagar dma-coherent; 2110*ec142c44SVidya Sagar 2111*ec142c44SVidya Sagar status = "disabled"; 2112*ec142c44SVidya Sagar }; 2113*ec142c44SVidya Sagar 2114*ec142c44SVidya Sagar pcie@141a0000 { 2115*ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie"; 2116*ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>; 2117*ec142c44SVidya Sagar reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2118*ec142c44SVidya Sagar <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */ 2119*ec142c44SVidya Sagar <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2120*ec142c44SVidya Sagar <0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2121*ec142c44SVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 2122*ec142c44SVidya Sagar 2123*ec142c44SVidya Sagar #address-cells = <3>; 2124*ec142c44SVidya Sagar #size-cells = <2>; 2125*ec142c44SVidya Sagar device_type = "pci"; 2126*ec142c44SVidya Sagar num-lanes = <8>; 2127*ec142c44SVidya Sagar num-viewport = <8>; 2128*ec142c44SVidya Sagar linux,pci-domain = <5>; 2129*ec142c44SVidya Sagar 2130*ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>; 2131*ec142c44SVidya Sagar clock-names = "core"; 2132*ec142c44SVidya Sagar 2133*ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>, 2134*ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX1_CORE_5>; 2135*ec142c44SVidya Sagar reset-names = "apb", "core"; 2136*ec142c44SVidya Sagar 2137*ec142c44SVidya Sagar interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2138*ec142c44SVidya Sagar <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2139*ec142c44SVidya Sagar interrupt-names = "intr", "msi"; 2140*ec142c44SVidya Sagar 2141*ec142c44SVidya Sagar #interrupt-cells = <1>; 2142*ec142c44SVidya Sagar interrupt-map-mask = <0 0 0 0>; 2143*ec142c44SVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 2144*ec142c44SVidya Sagar 2145*ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 5>; 2146*ec142c44SVidya Sagar 2147*ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2148*ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2149*ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2150*ec142c44SVidya Sagar 2151*ec142c44SVidya Sagar bus-range = <0x0 0xff>; 2152*ec142c44SVidya Sagar 2153*ec142c44SVidya Sagar ranges = <0x43000000 0x27 0x40000000 0x27 0x40000000 0x3 0xe8000000>, /* prefetchable memory (16000 MB) */ 2154*ec142c44SVidya Sagar <0x02000000 0x0 0x40000000 0x2b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2155*ec142c44SVidya Sagar <0x01000000 0x0 0x3a100000 0x00 0x3a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2156*ec142c44SVidya Sagar 2157*ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE5R &emc>, 2158*ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE5W &emc>; 2159*ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2160*ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>; 2161*ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2162*ec142c44SVidya Sagar dma-coherent; 2163*ec142c44SVidya Sagar 2164*ec142c44SVidya Sagar status = "disabled"; 2165*ec142c44SVidya Sagar }; 2166*ec142c44SVidya Sagar 2167*ec142c44SVidya Sagar pcie@141c0000 { 2168*ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie"; 2169*ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4A>; 2170*ec142c44SVidya Sagar reg = <0x00 0x141c0000 0x0 0x00020000>, /* appl registers (128K) */ 2171*ec142c44SVidya Sagar <0x00 0x3c000000 0x0 0x00040000>, /* configuration space (256K) */ 2172*ec142c44SVidya Sagar <0x00 0x3c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2173*ec142c44SVidya Sagar <0x00 0x3c080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2174*ec142c44SVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 2175*ec142c44SVidya Sagar 2176*ec142c44SVidya Sagar #address-cells = <3>; 2177*ec142c44SVidya Sagar #size-cells = <2>; 2178*ec142c44SVidya Sagar device_type = "pci"; 2179*ec142c44SVidya Sagar num-lanes = <4>; 2180*ec142c44SVidya Sagar num-viewport = <8>; 2181*ec142c44SVidya Sagar linux,pci-domain = <6>; 2182*ec142c44SVidya Sagar 2183*ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX1_C6_CORE>; 2184*ec142c44SVidya Sagar clock-names = "core"; 2185*ec142c44SVidya Sagar 2186*ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX1_CORE_6_APB>, 2187*ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX1_CORE_6>; 2188*ec142c44SVidya Sagar reset-names = "apb", "core"; 2189*ec142c44SVidya Sagar 2190*ec142c44SVidya Sagar interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2191*ec142c44SVidya Sagar <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2192*ec142c44SVidya Sagar interrupt-names = "intr", "msi"; 2193*ec142c44SVidya Sagar 2194*ec142c44SVidya Sagar #interrupt-cells = <1>; 2195*ec142c44SVidya Sagar interrupt-map-mask = <0 0 0 0>; 2196*ec142c44SVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 2197*ec142c44SVidya Sagar 2198*ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 6>; 2199*ec142c44SVidya Sagar 2200*ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2201*ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2202*ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2203*ec142c44SVidya Sagar 2204*ec142c44SVidya Sagar bus-range = <0x0 0xff>; 2205*ec142c44SVidya Sagar 2206*ec142c44SVidya Sagar ranges = <0x43000000 0x2b 0x40000000 0x2b 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2207*ec142c44SVidya Sagar <0x02000000 0x0 0x40000000 0x2e 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2208*ec142c44SVidya Sagar <0x01000000 0x0 0x3c100000 0x00 0x3c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2209*ec142c44SVidya Sagar 2210*ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE6AR &emc>, 2211*ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE6AW &emc>; 2212*ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2213*ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>; 2214*ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2215*ec142c44SVidya Sagar dma-coherent; 2216*ec142c44SVidya Sagar 2217*ec142c44SVidya Sagar status = "disabled"; 2218*ec142c44SVidya Sagar }; 2219*ec142c44SVidya Sagar 2220*ec142c44SVidya Sagar pcie@141e0000 { 2221*ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie"; 2222*ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8B>; 2223*ec142c44SVidya Sagar reg = <0x00 0x141e0000 0x0 0x00020000>, /* appl registers (128K) */ 2224*ec142c44SVidya Sagar <0x00 0x3e000000 0x0 0x00040000>, /* configuration space (256K) */ 2225*ec142c44SVidya Sagar <0x00 0x3e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2226*ec142c44SVidya Sagar <0x00 0x3e080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2227*ec142c44SVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 2228*ec142c44SVidya Sagar 2229*ec142c44SVidya Sagar #address-cells = <3>; 2230*ec142c44SVidya Sagar #size-cells = <2>; 2231*ec142c44SVidya Sagar device_type = "pci"; 2232*ec142c44SVidya Sagar num-lanes = <8>; 2233*ec142c44SVidya Sagar num-viewport = <8>; 2234*ec142c44SVidya Sagar linux,pci-domain = <7>; 2235*ec142c44SVidya Sagar 2236*ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX2_C7_CORE>; 2237*ec142c44SVidya Sagar clock-names = "core"; 2238*ec142c44SVidya Sagar 2239*ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX2_CORE_7_APB>, 2240*ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX2_CORE_7>; 2241*ec142c44SVidya Sagar reset-names = "apb", "core"; 2242*ec142c44SVidya Sagar 2243*ec142c44SVidya Sagar interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2244*ec142c44SVidya Sagar <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2245*ec142c44SVidya Sagar interrupt-names = "intr", "msi"; 2246*ec142c44SVidya Sagar 2247*ec142c44SVidya Sagar #interrupt-cells = <1>; 2248*ec142c44SVidya Sagar interrupt-map-mask = <0 0 0 0>; 2249*ec142c44SVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 2250*ec142c44SVidya Sagar 2251*ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 7>; 2252*ec142c44SVidya Sagar 2253*ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2254*ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2255*ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2256*ec142c44SVidya Sagar 2257*ec142c44SVidya Sagar bus-range = <0x0 0xff>; 2258*ec142c44SVidya Sagar 2259*ec142c44SVidya Sagar ranges = <0x43000000 0x2e 0x40000000 0x2e 0x40000000 0x3 0xe8000000>, /* prefetchable memory (16000 MB) */ 2260*ec142c44SVidya Sagar <0x02000000 0x0 0x40000000 0x32 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2261*ec142c44SVidya Sagar <0x01000000 0x0 0x3e100000 0x00 0x3e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2262*ec142c44SVidya Sagar 2263*ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE7AR &emc>, 2264*ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE7AW &emc>; 2265*ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2266*ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>; 2267*ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2268*ec142c44SVidya Sagar dma-coherent; 2269*ec142c44SVidya Sagar 2270*ec142c44SVidya Sagar status = "disabled"; 2271*ec142c44SVidya Sagar }; 2272*ec142c44SVidya Sagar 2273*ec142c44SVidya Sagar pcie-ep@141a0000 { 2274*ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie-ep"; 2275*ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>; 2276*ec142c44SVidya Sagar reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2277*ec142c44SVidya Sagar <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2278*ec142c44SVidya Sagar <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2279*ec142c44SVidya Sagar <0x27 0x40000000 0x4 0x00000000>; /* Address Space (16G) */ 2280*ec142c44SVidya Sagar reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2281*ec142c44SVidya Sagar 2282*ec142c44SVidya Sagar num-lanes = <8>; 2283*ec142c44SVidya Sagar 2284*ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>; 2285*ec142c44SVidya Sagar clock-names = "core"; 2286*ec142c44SVidya Sagar 2287*ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>, 2288*ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX1_CORE_5>; 2289*ec142c44SVidya Sagar reset-names = "apb", "core"; 2290*ec142c44SVidya Sagar 2291*ec142c44SVidya Sagar interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2292*ec142c44SVidya Sagar interrupt-names = "intr"; 2293*ec142c44SVidya Sagar 2294*ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 5>; 2295*ec142c44SVidya Sagar 2296*ec142c44SVidya Sagar nvidia,enable-ext-refclk; 2297*ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2298*ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2299*ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2300*ec142c44SVidya Sagar 2301*ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE5R &emc>, 2302*ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE5W &emc>; 2303*ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2304*ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>; 2305*ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2306*ec142c44SVidya Sagar dma-coherent; 2307*ec142c44SVidya Sagar 2308*ec142c44SVidya Sagar status = "disabled"; 2309*ec142c44SVidya Sagar }; 2310*ec142c44SVidya Sagar 2311*ec142c44SVidya Sagar pcie-ep@141c0000{ 2312*ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie-ep"; 2313*ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4A>; 2314*ec142c44SVidya Sagar reg = <0x00 0x141c0000 0x0 0x00020000>, /* appl registers (128K) */ 2315*ec142c44SVidya Sagar <0x00 0x3c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2316*ec142c44SVidya Sagar <0x00 0x3c080000 0x0 0x00040000>, /* DBI space (256K) */ 2317*ec142c44SVidya Sagar <0x2b 0x40000000 0x3 0x00000000>; /* Address Space (12G) */ 2318*ec142c44SVidya Sagar reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2319*ec142c44SVidya Sagar 2320*ec142c44SVidya Sagar num-lanes = <4>; 2321*ec142c44SVidya Sagar 2322*ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX1_C6_CORE>; 2323*ec142c44SVidya Sagar clock-names = "core"; 2324*ec142c44SVidya Sagar 2325*ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX1_CORE_6_APB>, 2326*ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX1_CORE_6>; 2327*ec142c44SVidya Sagar reset-names = "apb", "core"; 2328*ec142c44SVidya Sagar 2329*ec142c44SVidya Sagar interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2330*ec142c44SVidya Sagar interrupt-names = "intr"; 2331*ec142c44SVidya Sagar 2332*ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 6>; 2333*ec142c44SVidya Sagar 2334*ec142c44SVidya Sagar nvidia,enable-ext-refclk; 2335*ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2336*ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2337*ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2338*ec142c44SVidya Sagar 2339*ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE6AR &emc>, 2340*ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE6AW &emc>; 2341*ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2342*ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>; 2343*ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2344*ec142c44SVidya Sagar dma-coherent; 2345*ec142c44SVidya Sagar 2346*ec142c44SVidya Sagar status = "disabled"; 2347*ec142c44SVidya Sagar }; 2348*ec142c44SVidya Sagar 2349*ec142c44SVidya Sagar pcie-ep@141e0000{ 2350*ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie-ep"; 2351*ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8B>; 2352*ec142c44SVidya Sagar reg = <0x00 0x141e0000 0x0 0x00020000>, /* appl registers (128K) */ 2353*ec142c44SVidya Sagar <0x00 0x3e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2354*ec142c44SVidya Sagar <0x00 0x3e080000 0x0 0x00040000>, /* DBI space (256K) */ 2355*ec142c44SVidya Sagar <0x2e 0x40000000 0x4 0x00000000>; /* Address Space (16G) */ 2356*ec142c44SVidya Sagar reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2357*ec142c44SVidya Sagar 2358*ec142c44SVidya Sagar num-lanes = <8>; 2359*ec142c44SVidya Sagar 2360*ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX2_C7_CORE>; 2361*ec142c44SVidya Sagar clock-names = "core"; 2362*ec142c44SVidya Sagar 2363*ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX2_CORE_7_APB>, 2364*ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX2_CORE_7>; 2365*ec142c44SVidya Sagar reset-names = "apb", "core"; 2366*ec142c44SVidya Sagar 2367*ec142c44SVidya Sagar interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2368*ec142c44SVidya Sagar interrupt-names = "intr"; 2369*ec142c44SVidya Sagar 2370*ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 7>; 2371*ec142c44SVidya Sagar 2372*ec142c44SVidya Sagar nvidia,enable-ext-refclk; 2373*ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2374*ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2375*ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2376*ec142c44SVidya Sagar 2377*ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE7AR &emc>, 2378*ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE7AW &emc>; 2379*ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2380*ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>; 2381*ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2382*ec142c44SVidya Sagar dma-coherent; 2383*ec142c44SVidya Sagar 2384*ec142c44SVidya Sagar status = "disabled"; 2385*ec142c44SVidya Sagar }; 2386*ec142c44SVidya Sagar 2387*ec142c44SVidya Sagar pcie-ep@140e0000{ 2388*ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie-ep"; 2389*ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CC>; 2390*ec142c44SVidya Sagar reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K) */ 2391*ec142c44SVidya Sagar <0x00 0x2e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2392*ec142c44SVidya Sagar <0x00 0x2e080000 0x0 0x00040000>, /* DBI space (256K) */ 2393*ec142c44SVidya Sagar <0x38 0x40000000 0x3 0x00000000>; /* Address Space (12G) */ 2394*ec142c44SVidya Sagar reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2395*ec142c44SVidya Sagar 2396*ec142c44SVidya Sagar num-lanes = <4>; 2397*ec142c44SVidya Sagar 2398*ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX2_C10_CORE>; 2399*ec142c44SVidya Sagar clock-names = "core"; 2400*ec142c44SVidya Sagar 2401*ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX2_CORE_10_APB>, 2402*ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX2_CORE_10>; 2403*ec142c44SVidya Sagar reset-names = "apb", "core"; 2404*ec142c44SVidya Sagar 2405*ec142c44SVidya Sagar interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2406*ec142c44SVidya Sagar interrupt-names = "intr"; 2407*ec142c44SVidya Sagar 2408*ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 10>; 2409*ec142c44SVidya Sagar 2410*ec142c44SVidya Sagar nvidia,enable-ext-refclk; 2411*ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2412*ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2413*ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2414*ec142c44SVidya Sagar 2415*ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE10AR &emc>, 2416*ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE10AW &emc>; 2417*ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2418*ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>; 2419*ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2420*ec142c44SVidya Sagar dma-coherent; 2421*ec142c44SVidya Sagar 2422*ec142c44SVidya Sagar status = "disabled"; 2423*ec142c44SVidya Sagar }; 2424*ec142c44SVidya Sagar 24257fa30752SThierry Reding sram@40000000 { 242663944891SThierry Reding compatible = "nvidia,tegra234-sysram", "mmio-sram"; 242798094be1SMikko Perttunen reg = <0x0 0x40000000 0x0 0x80000>; 242863944891SThierry Reding #address-cells = <1>; 242963944891SThierry Reding #size-cells = <1>; 243098094be1SMikko Perttunen ranges = <0x0 0x0 0x40000000 0x80000>; 243161192a9dSMikko Perttunen no-memory-wc; 243263944891SThierry Reding 243398094be1SMikko Perttunen cpu_bpmp_tx: sram@70000 { 243498094be1SMikko Perttunen reg = <0x70000 0x1000>; 243563944891SThierry Reding label = "cpu-bpmp-tx"; 243663944891SThierry Reding pool; 243763944891SThierry Reding }; 243863944891SThierry Reding 243998094be1SMikko Perttunen cpu_bpmp_rx: sram@71000 { 244098094be1SMikko Perttunen reg = <0x71000 0x1000>; 244163944891SThierry Reding label = "cpu-bpmp-rx"; 244263944891SThierry Reding pool; 244363944891SThierry Reding }; 244463944891SThierry Reding }; 244563944891SThierry Reding 244663944891SThierry Reding bpmp: bpmp { 244763944891SThierry Reding compatible = "nvidia,tegra234-bpmp", "nvidia,tegra186-bpmp"; 244863944891SThierry Reding mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 244963944891SThierry Reding TEGRA_HSP_DB_MASTER_BPMP>; 24507fa30752SThierry Reding shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; 245163944891SThierry Reding #clock-cells = <1>; 245263944891SThierry Reding #reset-cells = <1>; 245363944891SThierry Reding #power-domain-cells = <1>; 24546de481e5SThierry Reding interconnects = <&mc TEGRA234_MEMORY_CLIENT_BPMPR &emc>, 24556de481e5SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_BPMPW &emc>, 24566de481e5SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAR &emc>, 24576de481e5SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAW &emc>; 24586de481e5SThierry Reding interconnect-names = "read", "write", "dma-mem", "dma-write"; 24595710e16aSThierry Reding iommus = <&smmu_niso1 TEGRA234_SID_BPMP>; 246063944891SThierry Reding 246163944891SThierry Reding bpmp_i2c: i2c { 246263944891SThierry Reding compatible = "nvidia,tegra186-bpmp-i2c"; 246363944891SThierry Reding nvidia,bpmp-bus-id = <5>; 246463944891SThierry Reding #address-cells = <1>; 246563944891SThierry Reding #size-cells = <0>; 246663944891SThierry Reding }; 246763944891SThierry Reding }; 246863944891SThierry Reding 246963944891SThierry Reding cpus { 247063944891SThierry Reding #address-cells = <1>; 247163944891SThierry Reding #size-cells = <0>; 247263944891SThierry Reding 2473a12cf5c3SThierry Reding cpu0_0: cpu@0 { 2474a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 247563944891SThierry Reding device_type = "cpu"; 2476a12cf5c3SThierry Reding reg = <0x00000>; 247763944891SThierry Reding 247863944891SThierry Reding enable-method = "psci"; 2479a12cf5c3SThierry Reding 2480a12cf5c3SThierry Reding i-cache-size = <65536>; 2481a12cf5c3SThierry Reding i-cache-line-size = <64>; 2482a12cf5c3SThierry Reding i-cache-sets = <256>; 2483a12cf5c3SThierry Reding d-cache-size = <65536>; 2484a12cf5c3SThierry Reding d-cache-line-size = <64>; 2485a12cf5c3SThierry Reding d-cache-sets = <256>; 2486a12cf5c3SThierry Reding next-level-cache = <&l2c0_0>; 248763944891SThierry Reding }; 2488a12cf5c3SThierry Reding 2489a12cf5c3SThierry Reding cpu0_1: cpu@100 { 2490a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 2491a12cf5c3SThierry Reding device_type = "cpu"; 2492a12cf5c3SThierry Reding reg = <0x00100>; 2493a12cf5c3SThierry Reding 2494a12cf5c3SThierry Reding enable-method = "psci"; 2495a12cf5c3SThierry Reding 2496a12cf5c3SThierry Reding i-cache-size = <65536>; 2497a12cf5c3SThierry Reding i-cache-line-size = <64>; 2498a12cf5c3SThierry Reding i-cache-sets = <256>; 2499a12cf5c3SThierry Reding d-cache-size = <65536>; 2500a12cf5c3SThierry Reding d-cache-line-size = <64>; 2501a12cf5c3SThierry Reding d-cache-sets = <256>; 2502a12cf5c3SThierry Reding next-level-cache = <&l2c0_1>; 2503a12cf5c3SThierry Reding }; 2504a12cf5c3SThierry Reding 2505a12cf5c3SThierry Reding cpu0_2: cpu@200 { 2506a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 2507a12cf5c3SThierry Reding device_type = "cpu"; 2508a12cf5c3SThierry Reding reg = <0x00200>; 2509a12cf5c3SThierry Reding 2510a12cf5c3SThierry Reding enable-method = "psci"; 2511a12cf5c3SThierry Reding 2512a12cf5c3SThierry Reding i-cache-size = <65536>; 2513a12cf5c3SThierry Reding i-cache-line-size = <64>; 2514a12cf5c3SThierry Reding i-cache-sets = <256>; 2515a12cf5c3SThierry Reding d-cache-size = <65536>; 2516a12cf5c3SThierry Reding d-cache-line-size = <64>; 2517a12cf5c3SThierry Reding d-cache-sets = <256>; 2518a12cf5c3SThierry Reding next-level-cache = <&l2c0_2>; 2519a12cf5c3SThierry Reding }; 2520a12cf5c3SThierry Reding 2521a12cf5c3SThierry Reding cpu0_3: cpu@300 { 2522a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 2523a12cf5c3SThierry Reding device_type = "cpu"; 2524a12cf5c3SThierry Reding reg = <0x00300>; 2525a12cf5c3SThierry Reding 2526a12cf5c3SThierry Reding enable-method = "psci"; 2527a12cf5c3SThierry Reding 2528a12cf5c3SThierry Reding i-cache-size = <65536>; 2529a12cf5c3SThierry Reding i-cache-line-size = <64>; 2530a12cf5c3SThierry Reding i-cache-sets = <256>; 2531a12cf5c3SThierry Reding d-cache-size = <65536>; 2532a12cf5c3SThierry Reding d-cache-line-size = <64>; 2533a12cf5c3SThierry Reding d-cache-sets = <256>; 2534a12cf5c3SThierry Reding next-level-cache = <&l2c0_3>; 2535a12cf5c3SThierry Reding }; 2536a12cf5c3SThierry Reding 2537a12cf5c3SThierry Reding cpu1_0: cpu@10000 { 2538a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 2539a12cf5c3SThierry Reding device_type = "cpu"; 2540a12cf5c3SThierry Reding reg = <0x10000>; 2541a12cf5c3SThierry Reding 2542a12cf5c3SThierry Reding enable-method = "psci"; 2543a12cf5c3SThierry Reding 2544a12cf5c3SThierry Reding i-cache-size = <65536>; 2545a12cf5c3SThierry Reding i-cache-line-size = <64>; 2546a12cf5c3SThierry Reding i-cache-sets = <256>; 2547a12cf5c3SThierry Reding d-cache-size = <65536>; 2548a12cf5c3SThierry Reding d-cache-line-size = <64>; 2549a12cf5c3SThierry Reding d-cache-sets = <256>; 2550a12cf5c3SThierry Reding next-level-cache = <&l2c1_0>; 2551a12cf5c3SThierry Reding }; 2552a12cf5c3SThierry Reding 2553a12cf5c3SThierry Reding cpu1_1: cpu@10100 { 2554a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 2555a12cf5c3SThierry Reding device_type = "cpu"; 2556a12cf5c3SThierry Reding reg = <0x10100>; 2557a12cf5c3SThierry Reding 2558a12cf5c3SThierry Reding enable-method = "psci"; 2559a12cf5c3SThierry Reding 2560a12cf5c3SThierry Reding i-cache-size = <65536>; 2561a12cf5c3SThierry Reding i-cache-line-size = <64>; 2562a12cf5c3SThierry Reding i-cache-sets = <256>; 2563a12cf5c3SThierry Reding d-cache-size = <65536>; 2564a12cf5c3SThierry Reding d-cache-line-size = <64>; 2565a12cf5c3SThierry Reding d-cache-sets = <256>; 2566a12cf5c3SThierry Reding next-level-cache = <&l2c1_1>; 2567a12cf5c3SThierry Reding }; 2568a12cf5c3SThierry Reding 2569a12cf5c3SThierry Reding cpu1_2: cpu@10200 { 2570a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 2571a12cf5c3SThierry Reding device_type = "cpu"; 2572a12cf5c3SThierry Reding reg = <0x10200>; 2573a12cf5c3SThierry Reding 2574a12cf5c3SThierry Reding enable-method = "psci"; 2575a12cf5c3SThierry Reding 2576a12cf5c3SThierry Reding i-cache-size = <65536>; 2577a12cf5c3SThierry Reding i-cache-line-size = <64>; 2578a12cf5c3SThierry Reding i-cache-sets = <256>; 2579a12cf5c3SThierry Reding d-cache-size = <65536>; 2580a12cf5c3SThierry Reding d-cache-line-size = <64>; 2581a12cf5c3SThierry Reding d-cache-sets = <256>; 2582a12cf5c3SThierry Reding next-level-cache = <&l2c1_2>; 2583a12cf5c3SThierry Reding }; 2584a12cf5c3SThierry Reding 2585a12cf5c3SThierry Reding cpu1_3: cpu@10300 { 2586a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 2587a12cf5c3SThierry Reding device_type = "cpu"; 2588a12cf5c3SThierry Reding reg = <0x10300>; 2589a12cf5c3SThierry Reding 2590a12cf5c3SThierry Reding enable-method = "psci"; 2591a12cf5c3SThierry Reding 2592a12cf5c3SThierry Reding i-cache-size = <65536>; 2593a12cf5c3SThierry Reding i-cache-line-size = <64>; 2594a12cf5c3SThierry Reding i-cache-sets = <256>; 2595a12cf5c3SThierry Reding d-cache-size = <65536>; 2596a12cf5c3SThierry Reding d-cache-line-size = <64>; 2597a12cf5c3SThierry Reding d-cache-sets = <256>; 2598a12cf5c3SThierry Reding next-level-cache = <&l2c1_3>; 2599a12cf5c3SThierry Reding }; 2600a12cf5c3SThierry Reding 2601a12cf5c3SThierry Reding cpu2_0: cpu@20000 { 2602a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 2603a12cf5c3SThierry Reding device_type = "cpu"; 2604a12cf5c3SThierry Reding reg = <0x20000>; 2605a12cf5c3SThierry Reding 2606a12cf5c3SThierry Reding enable-method = "psci"; 2607a12cf5c3SThierry Reding 2608a12cf5c3SThierry Reding i-cache-size = <65536>; 2609a12cf5c3SThierry Reding i-cache-line-size = <64>; 2610a12cf5c3SThierry Reding i-cache-sets = <256>; 2611a12cf5c3SThierry Reding d-cache-size = <65536>; 2612a12cf5c3SThierry Reding d-cache-line-size = <64>; 2613a12cf5c3SThierry Reding d-cache-sets = <256>; 2614a12cf5c3SThierry Reding next-level-cache = <&l2c2_0>; 2615a12cf5c3SThierry Reding }; 2616a12cf5c3SThierry Reding 2617a12cf5c3SThierry Reding cpu2_1: cpu@20100 { 2618a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 2619a12cf5c3SThierry Reding device_type = "cpu"; 2620a12cf5c3SThierry Reding reg = <0x20100>; 2621a12cf5c3SThierry Reding 2622a12cf5c3SThierry Reding enable-method = "psci"; 2623a12cf5c3SThierry Reding 2624a12cf5c3SThierry Reding i-cache-size = <65536>; 2625a12cf5c3SThierry Reding i-cache-line-size = <64>; 2626a12cf5c3SThierry Reding i-cache-sets = <256>; 2627a12cf5c3SThierry Reding d-cache-size = <65536>; 2628a12cf5c3SThierry Reding d-cache-line-size = <64>; 2629a12cf5c3SThierry Reding d-cache-sets = <256>; 2630a12cf5c3SThierry Reding next-level-cache = <&l2c2_1>; 2631a12cf5c3SThierry Reding }; 2632a12cf5c3SThierry Reding 2633a12cf5c3SThierry Reding cpu2_2: cpu@20200 { 2634a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 2635a12cf5c3SThierry Reding device_type = "cpu"; 2636a12cf5c3SThierry Reding reg = <0x20200>; 2637a12cf5c3SThierry Reding 2638a12cf5c3SThierry Reding enable-method = "psci"; 2639a12cf5c3SThierry Reding 2640a12cf5c3SThierry Reding i-cache-size = <65536>; 2641a12cf5c3SThierry Reding i-cache-line-size = <64>; 2642a12cf5c3SThierry Reding i-cache-sets = <256>; 2643a12cf5c3SThierry Reding d-cache-size = <65536>; 2644a12cf5c3SThierry Reding d-cache-line-size = <64>; 2645a12cf5c3SThierry Reding d-cache-sets = <256>; 2646a12cf5c3SThierry Reding next-level-cache = <&l2c2_2>; 2647a12cf5c3SThierry Reding }; 2648a12cf5c3SThierry Reding 2649a12cf5c3SThierry Reding cpu2_3: cpu@20300 { 2650a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 2651a12cf5c3SThierry Reding device_type = "cpu"; 2652a12cf5c3SThierry Reding reg = <0x20300>; 2653a12cf5c3SThierry Reding 2654a12cf5c3SThierry Reding enable-method = "psci"; 2655a12cf5c3SThierry Reding 2656a12cf5c3SThierry Reding i-cache-size = <65536>; 2657a12cf5c3SThierry Reding i-cache-line-size = <64>; 2658a12cf5c3SThierry Reding i-cache-sets = <256>; 2659a12cf5c3SThierry Reding d-cache-size = <65536>; 2660a12cf5c3SThierry Reding d-cache-line-size = <64>; 2661a12cf5c3SThierry Reding d-cache-sets = <256>; 2662a12cf5c3SThierry Reding next-level-cache = <&l2c2_3>; 2663a12cf5c3SThierry Reding }; 2664a12cf5c3SThierry Reding 2665a12cf5c3SThierry Reding cpu-map { 2666a12cf5c3SThierry Reding cluster0 { 2667a12cf5c3SThierry Reding core0 { 2668a12cf5c3SThierry Reding cpu = <&cpu0_0>; 2669a12cf5c3SThierry Reding }; 2670a12cf5c3SThierry Reding 2671a12cf5c3SThierry Reding core1 { 2672a12cf5c3SThierry Reding cpu = <&cpu0_1>; 2673a12cf5c3SThierry Reding }; 2674a12cf5c3SThierry Reding 2675a12cf5c3SThierry Reding core2 { 2676a12cf5c3SThierry Reding cpu = <&cpu0_2>; 2677a12cf5c3SThierry Reding }; 2678a12cf5c3SThierry Reding 2679a12cf5c3SThierry Reding core3 { 2680a12cf5c3SThierry Reding cpu = <&cpu0_3>; 2681a12cf5c3SThierry Reding }; 2682a12cf5c3SThierry Reding }; 2683a12cf5c3SThierry Reding 2684a12cf5c3SThierry Reding cluster1 { 2685a12cf5c3SThierry Reding core0 { 2686a12cf5c3SThierry Reding cpu = <&cpu1_0>; 2687a12cf5c3SThierry Reding }; 2688a12cf5c3SThierry Reding 2689a12cf5c3SThierry Reding core1 { 2690a12cf5c3SThierry Reding cpu = <&cpu1_1>; 2691a12cf5c3SThierry Reding }; 2692a12cf5c3SThierry Reding 2693a12cf5c3SThierry Reding core2 { 2694a12cf5c3SThierry Reding cpu = <&cpu1_2>; 2695a12cf5c3SThierry Reding }; 2696a12cf5c3SThierry Reding 2697a12cf5c3SThierry Reding core3 { 2698a12cf5c3SThierry Reding cpu = <&cpu1_3>; 2699a12cf5c3SThierry Reding }; 2700a12cf5c3SThierry Reding }; 2701a12cf5c3SThierry Reding 2702a12cf5c3SThierry Reding cluster2 { 2703a12cf5c3SThierry Reding core0 { 2704a12cf5c3SThierry Reding cpu = <&cpu2_0>; 2705a12cf5c3SThierry Reding }; 2706a12cf5c3SThierry Reding 2707a12cf5c3SThierry Reding core1 { 2708a12cf5c3SThierry Reding cpu = <&cpu2_1>; 2709a12cf5c3SThierry Reding }; 2710a12cf5c3SThierry Reding 2711a12cf5c3SThierry Reding core2 { 2712a12cf5c3SThierry Reding cpu = <&cpu2_2>; 2713a12cf5c3SThierry Reding }; 2714a12cf5c3SThierry Reding 2715a12cf5c3SThierry Reding core3 { 2716a12cf5c3SThierry Reding cpu = <&cpu2_3>; 2717a12cf5c3SThierry Reding }; 2718a12cf5c3SThierry Reding }; 2719a12cf5c3SThierry Reding }; 2720a12cf5c3SThierry Reding 2721a12cf5c3SThierry Reding l2c0_0: l2-cache00 { 2722a12cf5c3SThierry Reding cache-size = <262144>; 2723a12cf5c3SThierry Reding cache-line-size = <64>; 2724a12cf5c3SThierry Reding cache-sets = <512>; 2725a12cf5c3SThierry Reding cache-unified; 2726a12cf5c3SThierry Reding next-level-cache = <&l3c0>; 2727a12cf5c3SThierry Reding }; 2728a12cf5c3SThierry Reding 2729a12cf5c3SThierry Reding l2c0_1: l2-cache01 { 2730a12cf5c3SThierry Reding cache-size = <262144>; 2731a12cf5c3SThierry Reding cache-line-size = <64>; 2732a12cf5c3SThierry Reding cache-sets = <512>; 2733a12cf5c3SThierry Reding cache-unified; 2734a12cf5c3SThierry Reding next-level-cache = <&l3c0>; 2735a12cf5c3SThierry Reding }; 2736a12cf5c3SThierry Reding 2737a12cf5c3SThierry Reding l2c0_2: l2-cache02 { 2738a12cf5c3SThierry Reding cache-size = <262144>; 2739a12cf5c3SThierry Reding cache-line-size = <64>; 2740a12cf5c3SThierry Reding cache-sets = <512>; 2741a12cf5c3SThierry Reding cache-unified; 2742a12cf5c3SThierry Reding next-level-cache = <&l3c0>; 2743a12cf5c3SThierry Reding }; 2744a12cf5c3SThierry Reding 2745a12cf5c3SThierry Reding l2c0_3: l2-cache03 { 2746a12cf5c3SThierry Reding cache-size = <262144>; 2747a12cf5c3SThierry Reding cache-line-size = <64>; 2748a12cf5c3SThierry Reding cache-sets = <512>; 2749a12cf5c3SThierry Reding cache-unified; 2750a12cf5c3SThierry Reding next-level-cache = <&l3c0>; 2751a12cf5c3SThierry Reding }; 2752a12cf5c3SThierry Reding 2753a12cf5c3SThierry Reding l2c1_0: l2-cache10 { 2754a12cf5c3SThierry Reding cache-size = <262144>; 2755a12cf5c3SThierry Reding cache-line-size = <64>; 2756a12cf5c3SThierry Reding cache-sets = <512>; 2757a12cf5c3SThierry Reding cache-unified; 2758a12cf5c3SThierry Reding next-level-cache = <&l3c1>; 2759a12cf5c3SThierry Reding }; 2760a12cf5c3SThierry Reding 2761a12cf5c3SThierry Reding l2c1_1: l2-cache11 { 2762a12cf5c3SThierry Reding cache-size = <262144>; 2763a12cf5c3SThierry Reding cache-line-size = <64>; 2764a12cf5c3SThierry Reding cache-sets = <512>; 2765a12cf5c3SThierry Reding cache-unified; 2766a12cf5c3SThierry Reding next-level-cache = <&l3c1>; 2767a12cf5c3SThierry Reding }; 2768a12cf5c3SThierry Reding 2769a12cf5c3SThierry Reding l2c1_2: l2-cache12 { 2770a12cf5c3SThierry Reding cache-size = <262144>; 2771a12cf5c3SThierry Reding cache-line-size = <64>; 2772a12cf5c3SThierry Reding cache-sets = <512>; 2773a12cf5c3SThierry Reding cache-unified; 2774a12cf5c3SThierry Reding next-level-cache = <&l3c1>; 2775a12cf5c3SThierry Reding }; 2776a12cf5c3SThierry Reding 2777a12cf5c3SThierry Reding l2c1_3: l2-cache13 { 2778a12cf5c3SThierry Reding cache-size = <262144>; 2779a12cf5c3SThierry Reding cache-line-size = <64>; 2780a12cf5c3SThierry Reding cache-sets = <512>; 2781a12cf5c3SThierry Reding cache-unified; 2782a12cf5c3SThierry Reding next-level-cache = <&l3c1>; 2783a12cf5c3SThierry Reding }; 2784a12cf5c3SThierry Reding 2785a12cf5c3SThierry Reding l2c2_0: l2-cache20 { 2786a12cf5c3SThierry Reding cache-size = <262144>; 2787a12cf5c3SThierry Reding cache-line-size = <64>; 2788a12cf5c3SThierry Reding cache-sets = <512>; 2789a12cf5c3SThierry Reding cache-unified; 2790a12cf5c3SThierry Reding next-level-cache = <&l3c2>; 2791a12cf5c3SThierry Reding }; 2792a12cf5c3SThierry Reding 2793a12cf5c3SThierry Reding l2c2_1: l2-cache21 { 2794a12cf5c3SThierry Reding cache-size = <262144>; 2795a12cf5c3SThierry Reding cache-line-size = <64>; 2796a12cf5c3SThierry Reding cache-sets = <512>; 2797a12cf5c3SThierry Reding cache-unified; 2798a12cf5c3SThierry Reding next-level-cache = <&l3c2>; 2799a12cf5c3SThierry Reding }; 2800a12cf5c3SThierry Reding 2801a12cf5c3SThierry Reding l2c2_2: l2-cache22 { 2802a12cf5c3SThierry Reding cache-size = <262144>; 2803a12cf5c3SThierry Reding cache-line-size = <64>; 2804a12cf5c3SThierry Reding cache-sets = <512>; 2805a12cf5c3SThierry Reding cache-unified; 2806a12cf5c3SThierry Reding next-level-cache = <&l3c2>; 2807a12cf5c3SThierry Reding }; 2808a12cf5c3SThierry Reding 2809a12cf5c3SThierry Reding l2c2_3: l2-cache23 { 2810a12cf5c3SThierry Reding cache-size = <262144>; 2811a12cf5c3SThierry Reding cache-line-size = <64>; 2812a12cf5c3SThierry Reding cache-sets = <512>; 2813a12cf5c3SThierry Reding cache-unified; 2814a12cf5c3SThierry Reding next-level-cache = <&l3c2>; 2815a12cf5c3SThierry Reding }; 2816a12cf5c3SThierry Reding 2817a12cf5c3SThierry Reding l3c0: l3-cache0 { 2818a12cf5c3SThierry Reding cache-size = <2097152>; 2819a12cf5c3SThierry Reding cache-line-size = <64>; 2820a12cf5c3SThierry Reding cache-sets = <2048>; 2821a12cf5c3SThierry Reding }; 2822a12cf5c3SThierry Reding 2823a12cf5c3SThierry Reding l3c1: l3-cache1 { 2824a12cf5c3SThierry Reding cache-size = <2097152>; 2825a12cf5c3SThierry Reding cache-line-size = <64>; 2826a12cf5c3SThierry Reding cache-sets = <2048>; 2827a12cf5c3SThierry Reding }; 2828a12cf5c3SThierry Reding 2829a12cf5c3SThierry Reding l3c2: l3-cache2 { 2830a12cf5c3SThierry Reding cache-size = <2097152>; 2831a12cf5c3SThierry Reding cache-line-size = <64>; 2832a12cf5c3SThierry Reding cache-sets = <2048>; 2833a12cf5c3SThierry Reding }; 2834a12cf5c3SThierry Reding }; 2835a12cf5c3SThierry Reding 2836a12cf5c3SThierry Reding pmu { 2837a12cf5c3SThierry Reding compatible = "arm,cortex-a78-pmu"; 2838a12cf5c3SThierry Reding interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 2839a12cf5c3SThierry Reding status = "okay"; 284063944891SThierry Reding }; 284163944891SThierry Reding 284263944891SThierry Reding psci { 284363944891SThierry Reding compatible = "arm,psci-1.0"; 284463944891SThierry Reding status = "okay"; 284563944891SThierry Reding method = "smc"; 284663944891SThierry Reding }; 284763944891SThierry Reding 284806ad2ec4SMikko Perttunen tcu: serial { 284906ad2ec4SMikko Perttunen compatible = "nvidia,tegra234-tcu", "nvidia,tegra194-tcu"; 285006ad2ec4SMikko Perttunen mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 285106ad2ec4SMikko Perttunen <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 285206ad2ec4SMikko Perttunen mbox-names = "rx", "tx"; 285306ad2ec4SMikko Perttunen status = "disabled"; 285406ad2ec4SMikko Perttunen }; 285506ad2ec4SMikko Perttunen 285609614acdSSameer Pujar sound { 285709614acdSSameer Pujar status = "disabled"; 285809614acdSSameer Pujar 285909614acdSSameer Pujar clocks = <&bpmp TEGRA234_CLK_PLLA>, 286009614acdSSameer Pujar <&bpmp TEGRA234_CLK_PLLA_OUT0>; 286109614acdSSameer Pujar clock-names = "pll_a", "plla_out0"; 286209614acdSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_PLLA>, 286309614acdSSameer Pujar <&bpmp TEGRA234_CLK_PLLA_OUT0>, 286409614acdSSameer Pujar <&bpmp TEGRA234_CLK_AUD_MCLK>; 286509614acdSSameer Pujar assigned-clock-parents = <0>, 286609614acdSSameer Pujar <&bpmp TEGRA234_CLK_PLLA>, 286709614acdSSameer Pujar <&bpmp TEGRA234_CLK_PLLA_OUT0>; 286809614acdSSameer Pujar }; 286909614acdSSameer Pujar 287063944891SThierry Reding timer { 287163944891SThierry Reding compatible = "arm,armv8-timer"; 287263944891SThierry Reding interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 287363944891SThierry Reding <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 287463944891SThierry Reding <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 287563944891SThierry Reding <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 287663944891SThierry Reding interrupt-parent = <&gic>; 287763944891SThierry Reding always-on; 287863944891SThierry Reding }; 287963944891SThierry Reding}; 2880