163944891SThierry Reding// SPDX-License-Identifier: GPL-2.0 263944891SThierry Reding 363944891SThierry Reding#include <dt-bindings/clock/tegra234-clock.h> 463944891SThierry Reding#include <dt-bindings/interrupt-controller/arm-gic.h> 563944891SThierry Reding#include <dt-bindings/mailbox/tegra186-hsp.h> 663944891SThierry Reding#include <dt-bindings/reset/tegra234-reset.h> 763944891SThierry Reding 863944891SThierry Reding/ { 963944891SThierry Reding compatible = "nvidia,tegra234"; 1063944891SThierry Reding interrupt-parent = <&gic>; 1163944891SThierry Reding #address-cells = <2>; 1263944891SThierry Reding #size-cells = <2>; 1363944891SThierry Reding 1463944891SThierry Reding bus@0 { 1563944891SThierry Reding compatible = "simple-bus"; 1663944891SThierry Reding #address-cells = <1>; 1763944891SThierry Reding #size-cells = <1>; 1863944891SThierry Reding 1963944891SThierry Reding ranges = <0x0 0x0 0x0 0x40000000>; 2063944891SThierry Reding 2163944891SThierry Reding misc@100000 { 2263944891SThierry Reding compatible = "nvidia,tegra234-misc"; 2363944891SThierry Reding reg = <0x00100000 0xf000>, 2463944891SThierry Reding <0x0010f000 0x1000>; 2563944891SThierry Reding status = "okay"; 2663944891SThierry Reding }; 2763944891SThierry Reding 2863944891SThierry Reding uarta: serial@3100000 { 2963944891SThierry Reding compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart"; 3063944891SThierry Reding reg = <0x03100000 0x10000>; 3163944891SThierry Reding interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 3263944891SThierry Reding clocks = <&bpmp TEGRA234_CLK_UARTA>; 3363944891SThierry Reding clock-names = "serial"; 3463944891SThierry Reding resets = <&bpmp TEGRA234_RESET_UARTA>; 3563944891SThierry Reding reset-names = "serial"; 3663944891SThierry Reding status = "disabled"; 3763944891SThierry Reding }; 3863944891SThierry Reding 3963944891SThierry Reding mmc@3460000 { 4063944891SThierry Reding compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci"; 4163944891SThierry Reding reg = <0x03460000 0x20000>; 4263944891SThierry Reding interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 4363944891SThierry Reding clocks = <&bpmp TEGRA234_CLK_SDMMC4>; 4463944891SThierry Reding clock-names = "sdhci"; 4563944891SThierry Reding resets = <&bpmp TEGRA234_RESET_SDMMC4>; 4663944891SThierry Reding reset-names = "sdhci"; 4763944891SThierry Reding dma-coherent; 4863944891SThierry Reding status = "disabled"; 4963944891SThierry Reding }; 5063944891SThierry Reding 5163944891SThierry Reding fuse@3810000 { 5263944891SThierry Reding compatible = "nvidia,tegra234-efuse"; 5363944891SThierry Reding reg = <0x03810000 0x10000>; 5463944891SThierry Reding clocks = <&bpmp TEGRA234_CLK_FUSE>; 5563944891SThierry Reding clock-names = "fuse"; 5663944891SThierry Reding }; 5763944891SThierry Reding 5863944891SThierry Reding hsp_top0: hsp@3c00000 { 5963944891SThierry Reding compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; 6063944891SThierry Reding reg = <0x03c00000 0xa0000>; 6163944891SThierry Reding interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 6263944891SThierry Reding <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 6363944891SThierry Reding <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 6463944891SThierry Reding <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 6563944891SThierry Reding <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 6663944891SThierry Reding <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 6763944891SThierry Reding <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 6863944891SThierry Reding <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 6963944891SThierry Reding <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 7063944891SThierry Reding interrupt-names = "doorbell", "shared0", "shared1", "shared2", 7163944891SThierry Reding "shared3", "shared4", "shared5", "shared6", 7263944891SThierry Reding "shared7"; 7363944891SThierry Reding #mbox-cells = <2>; 7463944891SThierry Reding }; 7563944891SThierry Reding 7663944891SThierry Reding hsp_aon: hsp@c150000 { 7763944891SThierry Reding compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; 7863944891SThierry Reding reg = <0x0c150000 0x90000>; 7963944891SThierry Reding interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 8063944891SThierry Reding <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 8163944891SThierry Reding <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 8263944891SThierry Reding <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 8363944891SThierry Reding /* 8463944891SThierry Reding * Shared interrupt 0 is routed only to AON/SPE, so 8563944891SThierry Reding * we only have 4 shared interrupts for the CCPLEX. 8663944891SThierry Reding */ 8763944891SThierry Reding interrupt-names = "shared1", "shared2", "shared3", "shared4"; 8863944891SThierry Reding #mbox-cells = <2>; 8963944891SThierry Reding }; 9063944891SThierry Reding 9163944891SThierry Reding rtc@c2a0000 { 9263944891SThierry Reding compatible = "nvidia,tegra234-rtc", "nvidia,tegra20-rtc"; 9363944891SThierry Reding reg = <0x0c2a0000 0x10000>; 9463944891SThierry Reding interrupt-parent = <&pmc>; 9563944891SThierry Reding interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 96*e537addeSMikko Perttunen clocks = <&bpmp TEGRA234_CLK_CLK_32K>; 97*e537addeSMikko Perttunen clock-names = "rtc"; 9863944891SThierry Reding status = "disabled"; 9963944891SThierry Reding }; 10063944891SThierry Reding 10163944891SThierry Reding pmc: pmc@c360000 { 10263944891SThierry Reding compatible = "nvidia,tegra234-pmc"; 10363944891SThierry Reding reg = <0x0c360000 0x10000>, 10463944891SThierry Reding <0x0c370000 0x10000>, 10563944891SThierry Reding <0x0c380000 0x10000>, 10663944891SThierry Reding <0x0c390000 0x10000>, 10763944891SThierry Reding <0x0c3a0000 0x10000>; 10863944891SThierry Reding reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 10963944891SThierry Reding 11063944891SThierry Reding #interrupt-cells = <2>; 11163944891SThierry Reding interrupt-controller; 11263944891SThierry Reding }; 11363944891SThierry Reding 11463944891SThierry Reding gic: interrupt-controller@f400000 { 11563944891SThierry Reding compatible = "arm,gic-v3"; 11663944891SThierry Reding reg = <0x0f400000 0x010000>, /* GICD */ 11763944891SThierry Reding <0x0f440000 0x200000>; /* GICR */ 11863944891SThierry Reding interrupt-parent = <&gic>; 11963944891SThierry Reding interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 12063944891SThierry Reding 12163944891SThierry Reding #redistributor-regions = <1>; 12263944891SThierry Reding #interrupt-cells = <3>; 12363944891SThierry Reding interrupt-controller; 12463944891SThierry Reding }; 12563944891SThierry Reding }; 12663944891SThierry Reding 1277fa30752SThierry Reding sram@40000000 { 12863944891SThierry Reding compatible = "nvidia,tegra234-sysram", "mmio-sram"; 12963944891SThierry Reding reg = <0x0 0x40000000 0x0 0x50000>; 13063944891SThierry Reding #address-cells = <1>; 13163944891SThierry Reding #size-cells = <1>; 13263944891SThierry Reding ranges = <0x0 0x0 0x40000000 0x50000>; 13363944891SThierry Reding 1347fa30752SThierry Reding cpu_bpmp_tx: sram@4e000 { 13563944891SThierry Reding reg = <0x4e000 0x1000>; 13663944891SThierry Reding label = "cpu-bpmp-tx"; 13763944891SThierry Reding pool; 13863944891SThierry Reding }; 13963944891SThierry Reding 1407fa30752SThierry Reding cpu_bpmp_rx: sram@4f000 { 14163944891SThierry Reding reg = <0x4f000 0x1000>; 14263944891SThierry Reding label = "cpu-bpmp-rx"; 14363944891SThierry Reding pool; 14463944891SThierry Reding }; 14563944891SThierry Reding }; 14663944891SThierry Reding 14763944891SThierry Reding bpmp: bpmp { 14863944891SThierry Reding compatible = "nvidia,tegra234-bpmp", "nvidia,tegra186-bpmp"; 14963944891SThierry Reding mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 15063944891SThierry Reding TEGRA_HSP_DB_MASTER_BPMP>; 1517fa30752SThierry Reding shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; 15263944891SThierry Reding #clock-cells = <1>; 15363944891SThierry Reding #reset-cells = <1>; 15463944891SThierry Reding #power-domain-cells = <1>; 15563944891SThierry Reding 15663944891SThierry Reding bpmp_i2c: i2c { 15763944891SThierry Reding compatible = "nvidia,tegra186-bpmp-i2c"; 15863944891SThierry Reding nvidia,bpmp-bus-id = <5>; 15963944891SThierry Reding #address-cells = <1>; 16063944891SThierry Reding #size-cells = <0>; 16163944891SThierry Reding }; 16263944891SThierry Reding }; 16363944891SThierry Reding 16463944891SThierry Reding cpus { 16563944891SThierry Reding #address-cells = <1>; 16663944891SThierry Reding #size-cells = <0>; 16763944891SThierry Reding 16863944891SThierry Reding cpu@0 { 16963944891SThierry Reding device_type = "cpu"; 17063944891SThierry Reding reg = <0x000>; 17163944891SThierry Reding 17263944891SThierry Reding enable-method = "psci"; 17363944891SThierry Reding }; 17463944891SThierry Reding }; 17563944891SThierry Reding 17663944891SThierry Reding psci { 17763944891SThierry Reding compatible = "arm,psci-1.0"; 17863944891SThierry Reding status = "okay"; 17963944891SThierry Reding method = "smc"; 18063944891SThierry Reding }; 18163944891SThierry Reding 18263944891SThierry Reding timer { 18363944891SThierry Reding compatible = "arm,armv8-timer"; 18463944891SThierry Reding interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 18563944891SThierry Reding <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 18663944891SThierry Reding <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 18763944891SThierry Reding <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 18863944891SThierry Reding interrupt-parent = <&gic>; 18963944891SThierry Reding always-on; 19063944891SThierry Reding }; 19163944891SThierry Reding}; 192