163944891SThierry Reding// SPDX-License-Identifier: GPL-2.0 263944891SThierry Reding 363944891SThierry Reding#include <dt-bindings/clock/tegra234-clock.h> 4699349e0SThierry Reding#include <dt-bindings/gpio/tegra234-gpio.h> 563944891SThierry Reding#include <dt-bindings/interrupt-controller/arm-gic.h> 663944891SThierry Reding#include <dt-bindings/mailbox/tegra186-hsp.h> 7eed280dfSThierry Reding#include <dt-bindings/memory/tegra234-mc.h> 8c71e1897SThierry Reding#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 9dc94a94dSSameer Pujar#include <dt-bindings/power/tegra234-powergate.h> 1063944891SThierry Reding#include <dt-bindings/reset/tegra234-reset.h> 1109d99078SThierry Reding#include <dt-bindings/thermal/tegra234-bpmp-thermal.h> 1263944891SThierry Reding 1363944891SThierry Reding/ { 1463944891SThierry Reding compatible = "nvidia,tegra234"; 1563944891SThierry Reding interrupt-parent = <&gic>; 1663944891SThierry Reding #address-cells = <2>; 1763944891SThierry Reding #size-cells = <2>; 1863944891SThierry Reding 1963944891SThierry Reding bus@0 { 2063944891SThierry Reding compatible = "simple-bus"; 2163944891SThierry Reding 222838cfddSThierry Reding #address-cells = <2>; 232838cfddSThierry Reding #size-cells = <2>; 244bb54c2cSThierry Reding ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; 2563944891SThierry Reding 2679ed18d9SThierry Reding misc@100000 { 2779ed18d9SThierry Reding compatible = "nvidia,tegra234-misc"; 2879ed18d9SThierry Reding reg = <0x0 0x00100000 0x0 0xf000>, 2979ed18d9SThierry Reding <0x0 0x0010f000 0x0 0x1000>; 3079ed18d9SThierry Reding status = "okay"; 3179ed18d9SThierry Reding }; 3279ed18d9SThierry Reding 3379ed18d9SThierry Reding timer@2080000 { 3479ed18d9SThierry Reding compatible = "nvidia,tegra234-timer"; 3579ed18d9SThierry Reding reg = <0x0 0x02080000 0x0 0x00121000>; 3679ed18d9SThierry Reding interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 3779ed18d9SThierry Reding <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 3879ed18d9SThierry Reding <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 3979ed18d9SThierry Reding <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 4079ed18d9SThierry Reding <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 4179ed18d9SThierry Reding <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 4279ed18d9SThierry Reding <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 4379ed18d9SThierry Reding <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 4479ed18d9SThierry Reding <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 4579ed18d9SThierry Reding <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 4679ed18d9SThierry Reding <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 4779ed18d9SThierry Reding <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 4879ed18d9SThierry Reding <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 4979ed18d9SThierry Reding <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 5079ed18d9SThierry Reding <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 5179ed18d9SThierry Reding <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 5279ed18d9SThierry Reding status = "okay"; 5379ed18d9SThierry Reding }; 5479ed18d9SThierry Reding 5579ed18d9SThierry Reding gpio: gpio@2200000 { 5679ed18d9SThierry Reding compatible = "nvidia,tegra234-gpio"; 5779ed18d9SThierry Reding reg-names = "security", "gpio"; 5879ed18d9SThierry Reding reg = <0x0 0x02200000 0x0 0x10000>, 5979ed18d9SThierry Reding <0x0 0x02210000 0x0 0x10000>; 6079ed18d9SThierry Reding interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 6179ed18d9SThierry Reding <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 6279ed18d9SThierry Reding <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 6379ed18d9SThierry Reding <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, 6479ed18d9SThierry Reding <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 6579ed18d9SThierry Reding <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 6679ed18d9SThierry Reding <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 6779ed18d9SThierry Reding <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 6879ed18d9SThierry Reding <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 6979ed18d9SThierry Reding <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 7079ed18d9SThierry Reding <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 7179ed18d9SThierry Reding <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 7279ed18d9SThierry Reding <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 7379ed18d9SThierry Reding <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 7479ed18d9SThierry Reding <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 7579ed18d9SThierry Reding <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 7679ed18d9SThierry Reding <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 7779ed18d9SThierry Reding <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 7879ed18d9SThierry Reding <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 7979ed18d9SThierry Reding <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 8079ed18d9SThierry Reding <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 8179ed18d9SThierry Reding <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 8279ed18d9SThierry Reding <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 8379ed18d9SThierry Reding <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 8479ed18d9SThierry Reding <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 8579ed18d9SThierry Reding <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 8679ed18d9SThierry Reding <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 8779ed18d9SThierry Reding <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 8879ed18d9SThierry Reding <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 8979ed18d9SThierry Reding <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 9079ed18d9SThierry Reding <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 9179ed18d9SThierry Reding <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 9279ed18d9SThierry Reding <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 9379ed18d9SThierry Reding <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 9479ed18d9SThierry Reding <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 9579ed18d9SThierry Reding <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 9679ed18d9SThierry Reding <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 9779ed18d9SThierry Reding <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 9879ed18d9SThierry Reding <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 9979ed18d9SThierry Reding <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 10079ed18d9SThierry Reding <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 10179ed18d9SThierry Reding <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 10279ed18d9SThierry Reding <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 10379ed18d9SThierry Reding <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 10479ed18d9SThierry Reding <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 10579ed18d9SThierry Reding <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 10679ed18d9SThierry Reding <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 10779ed18d9SThierry Reding <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 10879ed18d9SThierry Reding #interrupt-cells = <2>; 10979ed18d9SThierry Reding interrupt-controller; 11079ed18d9SThierry Reding #gpio-cells = <2>; 11179ed18d9SThierry Reding gpio-controller; 112282fde00SPrathamesh Shete gpio-ranges = <&pinmux 0 0 164>; 113282fde00SPrathamesh Shete }; 114282fde00SPrathamesh Shete 115282fde00SPrathamesh Shete pinmux: pinmux@2430000 { 116282fde00SPrathamesh Shete compatible = "nvidia,tegra234-pinmux"; 117282fde00SPrathamesh Shete reg = <0x0 0x2430000 0x0 0x19100>; 11879ed18d9SThierry Reding }; 11979ed18d9SThierry Reding 12060d2016aSAkhil R gpcdma: dma-controller@2600000 { 121f7b93a08SAkhil R compatible = "nvidia,tegra234-gpcdma", 12260d2016aSAkhil R "nvidia,tegra186-gpcdma"; 1232838cfddSThierry Reding reg = <0x0 0x2600000 0x0 0x210000>; 12460d2016aSAkhil R resets = <&bpmp TEGRA234_RESET_GPCDMA>; 12560d2016aSAkhil R reset-names = "gpcdma"; 126dd0be827SAkhil R interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 127dd0be827SAkhil R <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 12860d2016aSAkhil R <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 12960d2016aSAkhil R <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 13060d2016aSAkhil R <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 13160d2016aSAkhil R <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 13260d2016aSAkhil R <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 13360d2016aSAkhil R <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 13460d2016aSAkhil R <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 13560d2016aSAkhil R <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 13660d2016aSAkhil R <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 13760d2016aSAkhil R <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 13860d2016aSAkhil R <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 13960d2016aSAkhil R <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 14060d2016aSAkhil R <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 14160d2016aSAkhil R <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 14260d2016aSAkhil R <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 14360d2016aSAkhil R <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 14460d2016aSAkhil R <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 14560d2016aSAkhil R <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 14660d2016aSAkhil R <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 14760d2016aSAkhil R <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 14860d2016aSAkhil R <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 14960d2016aSAkhil R <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 15060d2016aSAkhil R <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 15160d2016aSAkhil R <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 15260d2016aSAkhil R <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 15360d2016aSAkhil R <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 15460d2016aSAkhil R <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 15560d2016aSAkhil R <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 15660d2016aSAkhil R <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 15760d2016aSAkhil R <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 15860d2016aSAkhil R #dma-cells = <1>; 15960d2016aSAkhil R iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 160dd0be827SAkhil R dma-channel-mask = <0xfffffffe>; 16160d2016aSAkhil R dma-coherent; 16260d2016aSAkhil R }; 16360d2016aSAkhil R 164dc94a94dSSameer Pujar aconnect@2900000 { 165dc94a94dSSameer Pujar compatible = "nvidia,tegra234-aconnect", 166dc94a94dSSameer Pujar "nvidia,tegra210-aconnect"; 167dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_APE>, 168dc94a94dSSameer Pujar <&bpmp TEGRA234_CLK_APB2APE>; 169dc94a94dSSameer Pujar clock-names = "ape", "apb2ape"; 170dc94a94dSSameer Pujar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_AUD>; 171dc94a94dSSameer Pujar status = "disabled"; 172dc94a94dSSameer Pujar 1732838cfddSThierry Reding #address-cells = <2>; 1742838cfddSThierry Reding #size-cells = <2>; 1752838cfddSThierry Reding ranges = <0x0 0x02900000 0x0 0x02900000 0x0 0x200000>; 1762838cfddSThierry Reding 177dc94a94dSSameer Pujar tegra_ahub: ahub@2900800 { 178dc94a94dSSameer Pujar compatible = "nvidia,tegra234-ahub"; 1792838cfddSThierry Reding reg = <0x0 0x02900800 0x0 0x800>; 180dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_AHUB>; 181dc94a94dSSameer Pujar clock-names = "ahub"; 182dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_AHUB>; 183*e483fe34SSheetal assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 184*e483fe34SSheetal assigned-clock-rates = <81600000>; 185dc94a94dSSameer Pujar status = "disabled"; 186dc94a94dSSameer Pujar 1872838cfddSThierry Reding #address-cells = <2>; 1882838cfddSThierry Reding #size-cells = <2>; 1892838cfddSThierry Reding ranges = <0x0 0x02900800 0x0 0x02900800 0x0 0x11800>; 1902838cfddSThierry Reding 191dc94a94dSSameer Pujar tegra_i2s1: i2s@2901000 { 192dc94a94dSSameer Pujar compatible = "nvidia,tegra234-i2s", 193dc94a94dSSameer Pujar "nvidia,tegra210-i2s"; 1942838cfddSThierry Reding reg = <0x0 0x2901000 0x0 0x100>; 195dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_I2S1>, 196dc94a94dSSameer Pujar <&bpmp TEGRA234_CLK_I2S1_SYNC_INPUT>; 197dc94a94dSSameer Pujar clock-names = "i2s", "sync_input"; 198dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_I2S1>; 199dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 200dc94a94dSSameer Pujar assigned-clock-rates = <1536000>; 201dc94a94dSSameer Pujar sound-name-prefix = "I2S1"; 202dc94a94dSSameer Pujar status = "disabled"; 203dc94a94dSSameer Pujar }; 204dc94a94dSSameer Pujar 205dc94a94dSSameer Pujar tegra_i2s2: i2s@2901100 { 206dc94a94dSSameer Pujar compatible = "nvidia,tegra234-i2s", 207dc94a94dSSameer Pujar "nvidia,tegra210-i2s"; 2082838cfddSThierry Reding reg = <0x0 0x2901100 0x0 0x100>; 209dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_I2S2>, 210dc94a94dSSameer Pujar <&bpmp TEGRA234_CLK_I2S2_SYNC_INPUT>; 211dc94a94dSSameer Pujar clock-names = "i2s", "sync_input"; 212dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_I2S2>; 213dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 214dc94a94dSSameer Pujar assigned-clock-rates = <1536000>; 215dc94a94dSSameer Pujar sound-name-prefix = "I2S2"; 216dc94a94dSSameer Pujar status = "disabled"; 217dc94a94dSSameer Pujar }; 218dc94a94dSSameer Pujar 219dc94a94dSSameer Pujar tegra_i2s3: i2s@2901200 { 220dc94a94dSSameer Pujar compatible = "nvidia,tegra234-i2s", 221dc94a94dSSameer Pujar "nvidia,tegra210-i2s"; 2222838cfddSThierry Reding reg = <0x0 0x2901200 0x0 0x100>; 223dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_I2S3>, 224dc94a94dSSameer Pujar <&bpmp TEGRA234_CLK_I2S3_SYNC_INPUT>; 225dc94a94dSSameer Pujar clock-names = "i2s", "sync_input"; 226dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_I2S3>; 227dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 228dc94a94dSSameer Pujar assigned-clock-rates = <1536000>; 229dc94a94dSSameer Pujar sound-name-prefix = "I2S3"; 230dc94a94dSSameer Pujar status = "disabled"; 231dc94a94dSSameer Pujar }; 232dc94a94dSSameer Pujar 233dc94a94dSSameer Pujar tegra_i2s4: i2s@2901300 { 234dc94a94dSSameer Pujar compatible = "nvidia,tegra234-i2s", 235dc94a94dSSameer Pujar "nvidia,tegra210-i2s"; 2362838cfddSThierry Reding reg = <0x0 0x2901300 0x0 0x100>; 237dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_I2S4>, 238dc94a94dSSameer Pujar <&bpmp TEGRA234_CLK_I2S4_SYNC_INPUT>; 239dc94a94dSSameer Pujar clock-names = "i2s", "sync_input"; 240dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_I2S4>; 241dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 242dc94a94dSSameer Pujar assigned-clock-rates = <1536000>; 243dc94a94dSSameer Pujar sound-name-prefix = "I2S4"; 244dc94a94dSSameer Pujar status = "disabled"; 245dc94a94dSSameer Pujar }; 246dc94a94dSSameer Pujar 247dc94a94dSSameer Pujar tegra_i2s5: i2s@2901400 { 248dc94a94dSSameer Pujar compatible = "nvidia,tegra234-i2s", 249dc94a94dSSameer Pujar "nvidia,tegra210-i2s"; 2502838cfddSThierry Reding reg = <0x0 0x2901400 0x0 0x100>; 251dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_I2S5>, 252dc94a94dSSameer Pujar <&bpmp TEGRA234_CLK_I2S5_SYNC_INPUT>; 253dc94a94dSSameer Pujar clock-names = "i2s", "sync_input"; 254dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_I2S5>; 255dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 256dc94a94dSSameer Pujar assigned-clock-rates = <1536000>; 257dc94a94dSSameer Pujar sound-name-prefix = "I2S5"; 258dc94a94dSSameer Pujar status = "disabled"; 259dc94a94dSSameer Pujar }; 260dc94a94dSSameer Pujar 261dc94a94dSSameer Pujar tegra_i2s6: i2s@2901500 { 262dc94a94dSSameer Pujar compatible = "nvidia,tegra234-i2s", 263dc94a94dSSameer Pujar "nvidia,tegra210-i2s"; 2642838cfddSThierry Reding reg = <0x0 0x2901500 0x0 0x100>; 265dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_I2S6>, 266dc94a94dSSameer Pujar <&bpmp TEGRA234_CLK_I2S6_SYNC_INPUT>; 267dc94a94dSSameer Pujar clock-names = "i2s", "sync_input"; 268dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_I2S6>; 269dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 270dc94a94dSSameer Pujar assigned-clock-rates = <1536000>; 271dc94a94dSSameer Pujar sound-name-prefix = "I2S6"; 272dc94a94dSSameer Pujar status = "disabled"; 273dc94a94dSSameer Pujar }; 274dc94a94dSSameer Pujar 275dc94a94dSSameer Pujar tegra_sfc1: sfc@2902000 { 276dc94a94dSSameer Pujar compatible = "nvidia,tegra234-sfc", 277dc94a94dSSameer Pujar "nvidia,tegra210-sfc"; 2782838cfddSThierry Reding reg = <0x0 0x2902000 0x0 0x200>; 279dc94a94dSSameer Pujar sound-name-prefix = "SFC1"; 280dc94a94dSSameer Pujar status = "disabled"; 281dc94a94dSSameer Pujar }; 282dc94a94dSSameer Pujar 283dc94a94dSSameer Pujar tegra_sfc2: sfc@2902200 { 284dc94a94dSSameer Pujar compatible = "nvidia,tegra234-sfc", 285dc94a94dSSameer Pujar "nvidia,tegra210-sfc"; 2862838cfddSThierry Reding reg = <0x0 0x2902200 0x0 0x200>; 287dc94a94dSSameer Pujar sound-name-prefix = "SFC2"; 288dc94a94dSSameer Pujar status = "disabled"; 289dc94a94dSSameer Pujar }; 290dc94a94dSSameer Pujar 291dc94a94dSSameer Pujar tegra_sfc3: sfc@2902400 { 292dc94a94dSSameer Pujar compatible = "nvidia,tegra234-sfc", 293dc94a94dSSameer Pujar "nvidia,tegra210-sfc"; 2942838cfddSThierry Reding reg = <0x0 0x2902400 0x0 0x200>; 295dc94a94dSSameer Pujar sound-name-prefix = "SFC3"; 296dc94a94dSSameer Pujar status = "disabled"; 297dc94a94dSSameer Pujar }; 298dc94a94dSSameer Pujar 299dc94a94dSSameer Pujar tegra_sfc4: sfc@2902600 { 300dc94a94dSSameer Pujar compatible = "nvidia,tegra234-sfc", 301dc94a94dSSameer Pujar "nvidia,tegra210-sfc"; 3022838cfddSThierry Reding reg = <0x0 0x2902600 0x0 0x200>; 303dc94a94dSSameer Pujar sound-name-prefix = "SFC4"; 304dc94a94dSSameer Pujar status = "disabled"; 305dc94a94dSSameer Pujar }; 306dc94a94dSSameer Pujar 307dc94a94dSSameer Pujar tegra_amx1: amx@2903000 { 308dc94a94dSSameer Pujar compatible = "nvidia,tegra234-amx", 309dc94a94dSSameer Pujar "nvidia,tegra194-amx"; 3102838cfddSThierry Reding reg = <0x0 0x2903000 0x0 0x100>; 311dc94a94dSSameer Pujar sound-name-prefix = "AMX1"; 312dc94a94dSSameer Pujar status = "disabled"; 313dc94a94dSSameer Pujar }; 314dc94a94dSSameer Pujar 315dc94a94dSSameer Pujar tegra_amx2: amx@2903100 { 316dc94a94dSSameer Pujar compatible = "nvidia,tegra234-amx", 317dc94a94dSSameer Pujar "nvidia,tegra194-amx"; 3182838cfddSThierry Reding reg = <0x0 0x2903100 0x0 0x100>; 319dc94a94dSSameer Pujar sound-name-prefix = "AMX2"; 320dc94a94dSSameer Pujar status = "disabled"; 321dc94a94dSSameer Pujar }; 322dc94a94dSSameer Pujar 323dc94a94dSSameer Pujar tegra_amx3: amx@2903200 { 324dc94a94dSSameer Pujar compatible = "nvidia,tegra234-amx", 325dc94a94dSSameer Pujar "nvidia,tegra194-amx"; 3262838cfddSThierry Reding reg = <0x0 0x2903200 0x0 0x100>; 327dc94a94dSSameer Pujar sound-name-prefix = "AMX3"; 328dc94a94dSSameer Pujar status = "disabled"; 329dc94a94dSSameer Pujar }; 330dc94a94dSSameer Pujar 331dc94a94dSSameer Pujar tegra_amx4: amx@2903300 { 332dc94a94dSSameer Pujar compatible = "nvidia,tegra234-amx", 333dc94a94dSSameer Pujar "nvidia,tegra194-amx"; 3342838cfddSThierry Reding reg = <0x0 0x2903300 0x0 0x100>; 335dc94a94dSSameer Pujar sound-name-prefix = "AMX4"; 336dc94a94dSSameer Pujar status = "disabled"; 337dc94a94dSSameer Pujar }; 338dc94a94dSSameer Pujar 339dc94a94dSSameer Pujar tegra_adx1: adx@2903800 { 340dc94a94dSSameer Pujar compatible = "nvidia,tegra234-adx", 341dc94a94dSSameer Pujar "nvidia,tegra210-adx"; 3422838cfddSThierry Reding reg = <0x0 0x2903800 0x0 0x100>; 343dc94a94dSSameer Pujar sound-name-prefix = "ADX1"; 344dc94a94dSSameer Pujar status = "disabled"; 345dc94a94dSSameer Pujar }; 346dc94a94dSSameer Pujar 347dc94a94dSSameer Pujar tegra_adx2: adx@2903900 { 348dc94a94dSSameer Pujar compatible = "nvidia,tegra234-adx", 349dc94a94dSSameer Pujar "nvidia,tegra210-adx"; 3502838cfddSThierry Reding reg = <0x0 0x2903900 0x0 0x100>; 351dc94a94dSSameer Pujar sound-name-prefix = "ADX2"; 352dc94a94dSSameer Pujar status = "disabled"; 353dc94a94dSSameer Pujar }; 354dc94a94dSSameer Pujar 355dc94a94dSSameer Pujar tegra_adx3: adx@2903a00 { 356dc94a94dSSameer Pujar compatible = "nvidia,tegra234-adx", 357dc94a94dSSameer Pujar "nvidia,tegra210-adx"; 3582838cfddSThierry Reding reg = <0x0 0x2903a00 0x0 0x100>; 359dc94a94dSSameer Pujar sound-name-prefix = "ADX3"; 360dc94a94dSSameer Pujar status = "disabled"; 361dc94a94dSSameer Pujar }; 362dc94a94dSSameer Pujar 363dc94a94dSSameer Pujar tegra_adx4: adx@2903b00 { 364dc94a94dSSameer Pujar compatible = "nvidia,tegra234-adx", 365dc94a94dSSameer Pujar "nvidia,tegra210-adx"; 3662838cfddSThierry Reding reg = <0x0 0x2903b00 0x0 0x100>; 367dc94a94dSSameer Pujar sound-name-prefix = "ADX4"; 368dc94a94dSSameer Pujar status = "disabled"; 369dc94a94dSSameer Pujar }; 370dc94a94dSSameer Pujar 371dc94a94dSSameer Pujar 372dc94a94dSSameer Pujar tegra_dmic1: dmic@2904000 { 373dc94a94dSSameer Pujar compatible = "nvidia,tegra234-dmic", 374dc94a94dSSameer Pujar "nvidia,tegra210-dmic"; 3752838cfddSThierry Reding reg = <0x0 0x2904000 0x0 0x100>; 376dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_DMIC1>; 377dc94a94dSSameer Pujar clock-names = "dmic"; 378dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_DMIC1>; 379dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 380dc94a94dSSameer Pujar assigned-clock-rates = <3072000>; 381dc94a94dSSameer Pujar sound-name-prefix = "DMIC1"; 382dc94a94dSSameer Pujar status = "disabled"; 383dc94a94dSSameer Pujar }; 384dc94a94dSSameer Pujar 385dc94a94dSSameer Pujar tegra_dmic2: dmic@2904100 { 386dc94a94dSSameer Pujar compatible = "nvidia,tegra234-dmic", 387dc94a94dSSameer Pujar "nvidia,tegra210-dmic"; 3882838cfddSThierry Reding reg = <0x0 0x2904100 0x0 0x100>; 389dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_DMIC2>; 390dc94a94dSSameer Pujar clock-names = "dmic"; 391dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_DMIC2>; 392dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 393dc94a94dSSameer Pujar assigned-clock-rates = <3072000>; 394dc94a94dSSameer Pujar sound-name-prefix = "DMIC2"; 395dc94a94dSSameer Pujar status = "disabled"; 396dc94a94dSSameer Pujar }; 397dc94a94dSSameer Pujar 398dc94a94dSSameer Pujar tegra_dmic3: dmic@2904200 { 399dc94a94dSSameer Pujar compatible = "nvidia,tegra234-dmic", 400dc94a94dSSameer Pujar "nvidia,tegra210-dmic"; 4012838cfddSThierry Reding reg = <0x0 0x2904200 0x0 0x100>; 402dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_DMIC3>; 403dc94a94dSSameer Pujar clock-names = "dmic"; 404dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_DMIC3>; 405dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 406dc94a94dSSameer Pujar assigned-clock-rates = <3072000>; 407dc94a94dSSameer Pujar sound-name-prefix = "DMIC3"; 408dc94a94dSSameer Pujar status = "disabled"; 409dc94a94dSSameer Pujar }; 410dc94a94dSSameer Pujar 411dc94a94dSSameer Pujar tegra_dmic4: dmic@2904300 { 412dc94a94dSSameer Pujar compatible = "nvidia,tegra234-dmic", 413dc94a94dSSameer Pujar "nvidia,tegra210-dmic"; 4142838cfddSThierry Reding reg = <0x0 0x2904300 0x0 0x100>; 415dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_DMIC4>; 416dc94a94dSSameer Pujar clock-names = "dmic"; 417dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_DMIC4>; 418dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 419dc94a94dSSameer Pujar assigned-clock-rates = <3072000>; 420dc94a94dSSameer Pujar sound-name-prefix = "DMIC4"; 421dc94a94dSSameer Pujar status = "disabled"; 422dc94a94dSSameer Pujar }; 423dc94a94dSSameer Pujar 424dc94a94dSSameer Pujar tegra_dspk1: dspk@2905000 { 425dc94a94dSSameer Pujar compatible = "nvidia,tegra234-dspk", 426dc94a94dSSameer Pujar "nvidia,tegra186-dspk"; 4272838cfddSThierry Reding reg = <0x0 0x2905000 0x0 0x100>; 428dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_DSPK1>; 429dc94a94dSSameer Pujar clock-names = "dspk"; 430dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_DSPK1>; 431dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 432dc94a94dSSameer Pujar assigned-clock-rates = <12288000>; 433dc94a94dSSameer Pujar sound-name-prefix = "DSPK1"; 434dc94a94dSSameer Pujar status = "disabled"; 435dc94a94dSSameer Pujar }; 436dc94a94dSSameer Pujar 437dc94a94dSSameer Pujar tegra_dspk2: dspk@2905100 { 438dc94a94dSSameer Pujar compatible = "nvidia,tegra234-dspk", 439dc94a94dSSameer Pujar "nvidia,tegra186-dspk"; 4402838cfddSThierry Reding reg = <0x0 0x2905100 0x0 0x100>; 441dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_DSPK2>; 442dc94a94dSSameer Pujar clock-names = "dspk"; 443dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_DSPK2>; 444dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 445dc94a94dSSameer Pujar assigned-clock-rates = <12288000>; 446dc94a94dSSameer Pujar sound-name-prefix = "DSPK2"; 447dc94a94dSSameer Pujar status = "disabled"; 448dc94a94dSSameer Pujar }; 449dc94a94dSSameer Pujar 4504b6a1b7cSSameer Pujar tegra_ope1: processing-engine@2908000 { 4514b6a1b7cSSameer Pujar compatible = "nvidia,tegra234-ope", 4524b6a1b7cSSameer Pujar "nvidia,tegra210-ope"; 4532838cfddSThierry Reding reg = <0x0 0x2908000 0x0 0x100>; 4544b6a1b7cSSameer Pujar sound-name-prefix = "OPE1"; 4554b6a1b7cSSameer Pujar status = "disabled"; 4564b6a1b7cSSameer Pujar 4572838cfddSThierry Reding #address-cells = <2>; 4582838cfddSThierry Reding #size-cells = <2>; 4592838cfddSThierry Reding ranges; 4602838cfddSThierry Reding 4614b6a1b7cSSameer Pujar equalizer@2908100 { 4624b6a1b7cSSameer Pujar compatible = "nvidia,tegra234-peq", 4634b6a1b7cSSameer Pujar "nvidia,tegra210-peq"; 4642838cfddSThierry Reding reg = <0x0 0x2908100 0x0 0x100>; 4654b6a1b7cSSameer Pujar }; 4664b6a1b7cSSameer Pujar 4674b6a1b7cSSameer Pujar dynamic-range-compressor@2908200 { 4684b6a1b7cSSameer Pujar compatible = "nvidia,tegra234-mbdrc", 4694b6a1b7cSSameer Pujar "nvidia,tegra210-mbdrc"; 4702838cfddSThierry Reding reg = <0x0 0x2908200 0x0 0x200>; 4714b6a1b7cSSameer Pujar }; 4724b6a1b7cSSameer Pujar }; 4734b6a1b7cSSameer Pujar 474dc94a94dSSameer Pujar tegra_mvc1: mvc@290a000 { 475dc94a94dSSameer Pujar compatible = "nvidia,tegra234-mvc", 476dc94a94dSSameer Pujar "nvidia,tegra210-mvc"; 4772838cfddSThierry Reding reg = <0x0 0x290a000 0x0 0x200>; 478dc94a94dSSameer Pujar sound-name-prefix = "MVC1"; 479dc94a94dSSameer Pujar status = "disabled"; 480dc94a94dSSameer Pujar }; 481dc94a94dSSameer Pujar 482dc94a94dSSameer Pujar tegra_mvc2: mvc@290a200 { 483dc94a94dSSameer Pujar compatible = "nvidia,tegra234-mvc", 484dc94a94dSSameer Pujar "nvidia,tegra210-mvc"; 4852838cfddSThierry Reding reg = <0x0 0x290a200 0x0 0x200>; 486dc94a94dSSameer Pujar sound-name-prefix = "MVC2"; 487dc94a94dSSameer Pujar status = "disabled"; 488dc94a94dSSameer Pujar }; 489dc94a94dSSameer Pujar 490dc94a94dSSameer Pujar tegra_amixer: amixer@290bb00 { 491dc94a94dSSameer Pujar compatible = "nvidia,tegra234-amixer", 492dc94a94dSSameer Pujar "nvidia,tegra210-amixer"; 4932838cfddSThierry Reding reg = <0x0 0x290bb00 0x0 0x800>; 494dc94a94dSSameer Pujar sound-name-prefix = "MIXER1"; 495dc94a94dSSameer Pujar status = "disabled"; 496dc94a94dSSameer Pujar }; 497dc94a94dSSameer Pujar 498dc94a94dSSameer Pujar tegra_admaif: admaif@290f000 { 499dc94a94dSSameer Pujar compatible = "nvidia,tegra234-admaif", 500dc94a94dSSameer Pujar "nvidia,tegra186-admaif"; 5012838cfddSThierry Reding reg = <0x0 0x0290f000 0x0 0x1000>; 502dc94a94dSSameer Pujar dmas = <&adma 1>, <&adma 1>, 503dc94a94dSSameer Pujar <&adma 2>, <&adma 2>, 504dc94a94dSSameer Pujar <&adma 3>, <&adma 3>, 505dc94a94dSSameer Pujar <&adma 4>, <&adma 4>, 506dc94a94dSSameer Pujar <&adma 5>, <&adma 5>, 507dc94a94dSSameer Pujar <&adma 6>, <&adma 6>, 508dc94a94dSSameer Pujar <&adma 7>, <&adma 7>, 509dc94a94dSSameer Pujar <&adma 8>, <&adma 8>, 510dc94a94dSSameer Pujar <&adma 9>, <&adma 9>, 511dc94a94dSSameer Pujar <&adma 10>, <&adma 10>, 512dc94a94dSSameer Pujar <&adma 11>, <&adma 11>, 513dc94a94dSSameer Pujar <&adma 12>, <&adma 12>, 514dc94a94dSSameer Pujar <&adma 13>, <&adma 13>, 515dc94a94dSSameer Pujar <&adma 14>, <&adma 14>, 516dc94a94dSSameer Pujar <&adma 15>, <&adma 15>, 517dc94a94dSSameer Pujar <&adma 16>, <&adma 16>, 518dc94a94dSSameer Pujar <&adma 17>, <&adma 17>, 519dc94a94dSSameer Pujar <&adma 18>, <&adma 18>, 520dc94a94dSSameer Pujar <&adma 19>, <&adma 19>, 521dc94a94dSSameer Pujar <&adma 20>, <&adma 20>; 522dc94a94dSSameer Pujar dma-names = "rx1", "tx1", 523dc94a94dSSameer Pujar "rx2", "tx2", 524dc94a94dSSameer Pujar "rx3", "tx3", 525dc94a94dSSameer Pujar "rx4", "tx4", 526dc94a94dSSameer Pujar "rx5", "tx5", 527dc94a94dSSameer Pujar "rx6", "tx6", 528dc94a94dSSameer Pujar "rx7", "tx7", 529dc94a94dSSameer Pujar "rx8", "tx8", 530dc94a94dSSameer Pujar "rx9", "tx9", 531dc94a94dSSameer Pujar "rx10", "tx10", 532dc94a94dSSameer Pujar "rx11", "tx11", 533dc94a94dSSameer Pujar "rx12", "tx12", 534dc94a94dSSameer Pujar "rx13", "tx13", 535dc94a94dSSameer Pujar "rx14", "tx14", 536dc94a94dSSameer Pujar "rx15", "tx15", 537dc94a94dSSameer Pujar "rx16", "tx16", 538dc94a94dSSameer Pujar "rx17", "tx17", 539dc94a94dSSameer Pujar "rx18", "tx18", 540dc94a94dSSameer Pujar "rx19", "tx19", 541dc94a94dSSameer Pujar "rx20", "tx20"; 542dc94a94dSSameer Pujar interconnects = <&mc TEGRA234_MEMORY_CLIENT_APEDMAR &emc>, 543dc94a94dSSameer Pujar <&mc TEGRA234_MEMORY_CLIENT_APEDMAW &emc>; 544dc94a94dSSameer Pujar interconnect-names = "dma-mem", "write"; 545dc94a94dSSameer Pujar iommus = <&smmu_niso0 TEGRA234_SID_APE>; 546dc94a94dSSameer Pujar status = "disabled"; 547dc94a94dSSameer Pujar }; 54847a08153SSameer Pujar 54947a08153SSameer Pujar tegra_asrc: asrc@2910000 { 55047a08153SSameer Pujar compatible = "nvidia,tegra234-asrc", 55147a08153SSameer Pujar "nvidia,tegra186-asrc"; 5522838cfddSThierry Reding reg = <0x0 0x2910000 0x0 0x2000>; 55347a08153SSameer Pujar sound-name-prefix = "ASRC1"; 55447a08153SSameer Pujar status = "disabled"; 55547a08153SSameer Pujar }; 556dc94a94dSSameer Pujar }; 557dc94a94dSSameer Pujar 558dc94a94dSSameer Pujar adma: dma-controller@2930000 { 559dc94a94dSSameer Pujar compatible = "nvidia,tegra234-adma", 560dc94a94dSSameer Pujar "nvidia,tegra186-adma"; 5612838cfddSThierry Reding reg = <0x0 0x02930000 0x0 0x20000>; 562dc94a94dSSameer Pujar interrupt-parent = <&agic>; 563dc94a94dSSameer Pujar interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 564dc94a94dSSameer Pujar <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 565dc94a94dSSameer Pujar <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 566dc94a94dSSameer Pujar <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 567dc94a94dSSameer Pujar <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 568dc94a94dSSameer Pujar <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 569dc94a94dSSameer Pujar <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 570dc94a94dSSameer Pujar <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 571dc94a94dSSameer Pujar <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 572dc94a94dSSameer Pujar <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 573dc94a94dSSameer Pujar <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 574dc94a94dSSameer Pujar <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 575dc94a94dSSameer Pujar <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 576dc94a94dSSameer Pujar <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 577dc94a94dSSameer Pujar <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 578dc94a94dSSameer Pujar <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 579dc94a94dSSameer Pujar <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 580dc94a94dSSameer Pujar <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 581dc94a94dSSameer Pujar <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 582dc94a94dSSameer Pujar <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 583dc94a94dSSameer Pujar <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 584dc94a94dSSameer Pujar <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 585dc94a94dSSameer Pujar <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 586dc94a94dSSameer Pujar <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 587dc94a94dSSameer Pujar <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 588dc94a94dSSameer Pujar <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 589dc94a94dSSameer Pujar <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 590dc94a94dSSameer Pujar <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 591dc94a94dSSameer Pujar <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 592dc94a94dSSameer Pujar <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 593dc94a94dSSameer Pujar <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 594dc94a94dSSameer Pujar <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 595dc94a94dSSameer Pujar #dma-cells = <1>; 596dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_AHUB>; 597dc94a94dSSameer Pujar clock-names = "d_audio"; 598dc94a94dSSameer Pujar status = "disabled"; 599dc94a94dSSameer Pujar }; 600dc94a94dSSameer Pujar 601dc94a94dSSameer Pujar agic: interrupt-controller@2a40000 { 602dc94a94dSSameer Pujar compatible = "nvidia,tegra234-agic", 603dc94a94dSSameer Pujar "nvidia,tegra210-agic"; 604dc94a94dSSameer Pujar #interrupt-cells = <3>; 605dc94a94dSSameer Pujar interrupt-controller; 6062838cfddSThierry Reding reg = <0x0 0x02a41000 0x0 0x1000>, 6072838cfddSThierry Reding <0x0 0x02a42000 0x0 0x2000>; 608dc94a94dSSameer Pujar interrupts = <GIC_SPI 145 609dc94a94dSSameer Pujar (GIC_CPU_MASK_SIMPLE(4) | 610dc94a94dSSameer Pujar IRQ_TYPE_LEVEL_HIGH)>; 611dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_APE>; 612dc94a94dSSameer Pujar clock-names = "clk"; 613dc94a94dSSameer Pujar status = "disabled"; 614dc94a94dSSameer Pujar }; 615dc94a94dSSameer Pujar }; 616dc94a94dSSameer Pujar 617eed280dfSThierry Reding mc: memory-controller@2c00000 { 618eed280dfSThierry Reding compatible = "nvidia,tegra234-mc"; 6192838cfddSThierry Reding reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */ 6202838cfddSThierry Reding <0x0 0x02c10000 0x0 0x10000>, /* MC Broadcast*/ 6212838cfddSThierry Reding <0x0 0x02c20000 0x0 0x10000>, /* MC0 */ 6222838cfddSThierry Reding <0x0 0x02c30000 0x0 0x10000>, /* MC1 */ 6232838cfddSThierry Reding <0x0 0x02c40000 0x0 0x10000>, /* MC2 */ 6242838cfddSThierry Reding <0x0 0x02c50000 0x0 0x10000>, /* MC3 */ 6252838cfddSThierry Reding <0x0 0x02b80000 0x0 0x10000>, /* MC4 */ 6262838cfddSThierry Reding <0x0 0x02b90000 0x0 0x10000>, /* MC5 */ 6272838cfddSThierry Reding <0x0 0x02ba0000 0x0 0x10000>, /* MC6 */ 6282838cfddSThierry Reding <0x0 0x02bb0000 0x0 0x10000>, /* MC7 */ 6292838cfddSThierry Reding <0x0 0x01700000 0x0 0x10000>, /* MC8 */ 6302838cfddSThierry Reding <0x0 0x01710000 0x0 0x10000>, /* MC9 */ 6312838cfddSThierry Reding <0x0 0x01720000 0x0 0x10000>, /* MC10 */ 6322838cfddSThierry Reding <0x0 0x01730000 0x0 0x10000>, /* MC11 */ 6332838cfddSThierry Reding <0x0 0x01740000 0x0 0x10000>, /* MC12 */ 6342838cfddSThierry Reding <0x0 0x01750000 0x0 0x10000>, /* MC13 */ 6352838cfddSThierry Reding <0x0 0x01760000 0x0 0x10000>, /* MC14 */ 6362838cfddSThierry Reding <0x0 0x01770000 0x0 0x10000>; /* MC15 */ 637000b99e5SAshish Mhetre reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3", 638000b99e5SAshish Mhetre "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", 639000b99e5SAshish Mhetre "ch11", "ch12", "ch13", "ch14", "ch15"; 640eed280dfSThierry Reding interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 641eed280dfSThierry Reding #interconnect-cells = <1>; 642eed280dfSThierry Reding status = "okay"; 643eed280dfSThierry Reding 644eed280dfSThierry Reding #address-cells = <2>; 645eed280dfSThierry Reding #size-cells = <2>; 6462838cfddSThierry Reding ranges = <0x0 0x01700000 0x0 0x01700000 0x0 0x100000>, 6472838cfddSThierry Reding <0x0 0x02b80000 0x0 0x02b80000 0x0 0x040000>, 6482838cfddSThierry Reding <0x0 0x02c00000 0x0 0x02c00000 0x0 0x100000>; 649eed280dfSThierry Reding 650eed280dfSThierry Reding /* 651eed280dfSThierry Reding * Bit 39 of addresses passing through the memory 652eed280dfSThierry Reding * controller selects the XBAR format used when memory 653eed280dfSThierry Reding * is accessed. This is used to transparently access 654eed280dfSThierry Reding * memory in the XBAR format used by the discrete GPU 655eed280dfSThierry Reding * (bit 39 set) or Tegra (bit 39 clear). 656eed280dfSThierry Reding * 657eed280dfSThierry Reding * As a consequence, the operating system must ensure 658eed280dfSThierry Reding * that bit 39 is never used implicitly, for example 659eed280dfSThierry Reding * via an I/O virtual address mapping of an IOMMU. If 660eed280dfSThierry Reding * devices require access to the XBAR switch, their 661eed280dfSThierry Reding * drivers must set this bit explicitly. 662eed280dfSThierry Reding * 663eed280dfSThierry Reding * Limit the DMA range for memory clients to [38:0]. 664eed280dfSThierry Reding */ 6652838cfddSThierry Reding dma-ranges = <0x0 0x0 0x0 0x0 0x80 0x0>; 666eed280dfSThierry Reding 667eed280dfSThierry Reding emc: external-memory-controller@2c60000 { 668eed280dfSThierry Reding compatible = "nvidia,tegra234-emc"; 669eed280dfSThierry Reding reg = <0x0 0x02c60000 0x0 0x90000>, 670eed280dfSThierry Reding <0x0 0x01780000 0x0 0x80000>; 671eed280dfSThierry Reding interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 672eed280dfSThierry Reding clocks = <&bpmp TEGRA234_CLK_EMC>; 673eed280dfSThierry Reding clock-names = "emc"; 674eed280dfSThierry Reding status = "okay"; 675eed280dfSThierry Reding 676eed280dfSThierry Reding #interconnect-cells = <0>; 677eed280dfSThierry Reding 678eed280dfSThierry Reding nvidia,bpmp = <&bpmp>; 679eed280dfSThierry Reding }; 680eed280dfSThierry Reding }; 681eed280dfSThierry Reding 68263944891SThierry Reding uarta: serial@3100000 { 68363944891SThierry Reding compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart"; 6842838cfddSThierry Reding reg = <0x0 0x03100000 0x0 0x10000>; 68563944891SThierry Reding interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 68663944891SThierry Reding clocks = <&bpmp TEGRA234_CLK_UARTA>; 68763944891SThierry Reding resets = <&bpmp TEGRA234_RESET_UARTA>; 68863944891SThierry Reding status = "disabled"; 68963944891SThierry Reding }; 69063944891SThierry Reding 691156af9deSAkhil R gen1_i2c: i2c@3160000 { 692156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 6932838cfddSThierry Reding reg = <0x0 0x3160000 0x0 0x100>; 694156af9deSAkhil R status = "disabled"; 695156af9deSAkhil R interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 696260e8d42SJon Hunter #address-cells = <1>; 697260e8d42SJon Hunter #size-cells = <0>; 698156af9deSAkhil R clock-frequency = <400000>; 699156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C1 700156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 701156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C1>; 702156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 703156af9deSAkhil R clock-names = "div-clk", "parent"; 704156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C1>; 705156af9deSAkhil R reset-names = "i2c"; 7068e442805SAkhil R dmas = <&gpcdma 21>, <&gpcdma 21>; 7078e442805SAkhil R dma-names = "rx", "tx"; 708156af9deSAkhil R }; 709156af9deSAkhil R 710156af9deSAkhil R cam_i2c: i2c@3180000 { 711156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 7122838cfddSThierry Reding reg = <0x0 0x3180000 0x0 0x100>; 713156af9deSAkhil R interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 714260e8d42SJon Hunter #address-cells = <1>; 715260e8d42SJon Hunter #size-cells = <0>; 716156af9deSAkhil R status = "disabled"; 717156af9deSAkhil R clock-frequency = <400000>; 718156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C3 719156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 720156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C3>; 721156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 722156af9deSAkhil R clock-names = "div-clk", "parent"; 723156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C3>; 724156af9deSAkhil R reset-names = "i2c"; 7258e442805SAkhil R dmas = <&gpcdma 23>, <&gpcdma 23>; 7268e442805SAkhil R dma-names = "rx", "tx"; 727156af9deSAkhil R }; 728156af9deSAkhil R 729156af9deSAkhil R dp_aux_ch1_i2c: i2c@3190000 { 730156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 7312838cfddSThierry Reding reg = <0x0 0x3190000 0x0 0x100>; 732156af9deSAkhil R interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 733260e8d42SJon Hunter #address-cells = <1>; 734260e8d42SJon Hunter #size-cells = <0>; 735156af9deSAkhil R status = "disabled"; 736156af9deSAkhil R clock-frequency = <100000>; 737156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C4 738156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 739156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C4>; 740156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 741156af9deSAkhil R clock-names = "div-clk", "parent"; 742156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C4>; 743156af9deSAkhil R reset-names = "i2c"; 7448e442805SAkhil R dmas = <&gpcdma 26>, <&gpcdma 26>; 7458e442805SAkhil R dma-names = "rx", "tx"; 746156af9deSAkhil R }; 747156af9deSAkhil R 748156af9deSAkhil R dp_aux_ch0_i2c: i2c@31b0000 { 749156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 7502838cfddSThierry Reding reg = <0x0 0x31b0000 0x0 0x100>; 751156af9deSAkhil R interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 752260e8d42SJon Hunter #address-cells = <1>; 753260e8d42SJon Hunter #size-cells = <0>; 754156af9deSAkhil R status = "disabled"; 755156af9deSAkhil R clock-frequency = <100000>; 756156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C6 757156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 758156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C6>; 759156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 760156af9deSAkhil R clock-names = "div-clk", "parent"; 761156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C6>; 762156af9deSAkhil R reset-names = "i2c"; 7638e442805SAkhil R dmas = <&gpcdma 30>, <&gpcdma 30>; 7648e442805SAkhil R dma-names = "rx", "tx"; 765156af9deSAkhil R }; 766156af9deSAkhil R 767156af9deSAkhil R dp_aux_ch2_i2c: i2c@31c0000 { 768156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 7692838cfddSThierry Reding reg = <0x0 0x31c0000 0x0 0x100>; 770156af9deSAkhil R interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 771260e8d42SJon Hunter #address-cells = <1>; 772260e8d42SJon Hunter #size-cells = <0>; 773156af9deSAkhil R status = "disabled"; 774156af9deSAkhil R clock-frequency = <100000>; 775156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C7 776156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 777156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C7>; 778156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 779156af9deSAkhil R clock-names = "div-clk", "parent"; 780156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C7>; 781156af9deSAkhil R reset-names = "i2c"; 7828e442805SAkhil R dmas = <&gpcdma 27>, <&gpcdma 27>; 7838e442805SAkhil R dma-names = "rx", "tx"; 784156af9deSAkhil R }; 785156af9deSAkhil R 7861bbba854SJon Hunter uarti: serial@31d0000 { 7871bbba854SJon Hunter compatible = "arm,sbsa-uart"; 7882838cfddSThierry Reding reg = <0x0 0x31d0000 0x0 0x10000>; 7891bbba854SJon Hunter interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; 7901bbba854SJon Hunter status = "disabled"; 7911bbba854SJon Hunter }; 7921bbba854SJon Hunter 793156af9deSAkhil R dp_aux_ch3_i2c: i2c@31e0000 { 794156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 7952838cfddSThierry Reding reg = <0x0 0x31e0000 0x0 0x100>; 796156af9deSAkhil R interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 797260e8d42SJon Hunter #address-cells = <1>; 798260e8d42SJon Hunter #size-cells = <0>; 799156af9deSAkhil R status = "disabled"; 800156af9deSAkhil R clock-frequency = <100000>; 801156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C9 802156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 803156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C9>; 804156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 805156af9deSAkhil R clock-names = "div-clk", "parent"; 806156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C9>; 807156af9deSAkhil R reset-names = "i2c"; 8088e442805SAkhil R dmas = <&gpcdma 31>, <&gpcdma 31>; 8098e442805SAkhil R dma-names = "rx", "tx"; 810156af9deSAkhil R }; 811156af9deSAkhil R 81271f69ffaSAshish Singhal spi@3270000 { 81371f69ffaSAshish Singhal compatible = "nvidia,tegra234-qspi"; 8142838cfddSThierry Reding reg = <0x0 0x3270000 0x0 0x1000>; 81571f69ffaSAshish Singhal interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 81671f69ffaSAshish Singhal #address-cells = <1>; 81771f69ffaSAshish Singhal #size-cells = <0>; 81871f69ffaSAshish Singhal clocks = <&bpmp TEGRA234_CLK_QSPI0_2X_PM>, 81971f69ffaSAshish Singhal <&bpmp TEGRA234_CLK_QSPI0_PM>; 82071f69ffaSAshish Singhal clock-names = "qspi", "qspi_out"; 82171f69ffaSAshish Singhal resets = <&bpmp TEGRA234_RESET_QSPI0>; 82271f69ffaSAshish Singhal status = "disabled"; 82371f69ffaSAshish Singhal }; 82471f69ffaSAshish Singhal 8255e69088dSAkhil R pwm1: pwm@3280000 { 8262566d28cSJon Hunter compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 8272838cfddSThierry Reding reg = <0x0 0x3280000 0x0 0x10000>; 8285e69088dSAkhil R clocks = <&bpmp TEGRA234_CLK_PWM1>; 8295e69088dSAkhil R resets = <&bpmp TEGRA234_RESET_PWM1>; 8305e69088dSAkhil R reset-names = "pwm"; 8315e69088dSAkhil R status = "disabled"; 8325e69088dSAkhil R #pwm-cells = <2>; 8335e69088dSAkhil R }; 8345e69088dSAkhil R 8352566d28cSJon Hunter pwm2: pwm@3290000 { 8362566d28cSJon Hunter compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 8372838cfddSThierry Reding reg = <0x0 0x3290000 0x0 0x10000>; 8382566d28cSJon Hunter clocks = <&bpmp TEGRA234_CLK_PWM2>; 8392566d28cSJon Hunter resets = <&bpmp TEGRA234_RESET_PWM2>; 8402566d28cSJon Hunter reset-names = "pwm"; 8412566d28cSJon Hunter status = "disabled"; 8422566d28cSJon Hunter #pwm-cells = <2>; 8432566d28cSJon Hunter }; 8442566d28cSJon Hunter 8452566d28cSJon Hunter pwm3: pwm@32a0000 { 8462566d28cSJon Hunter compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 8472838cfddSThierry Reding reg = <0x0 0x32a0000 0x0 0x10000>; 8482566d28cSJon Hunter clocks = <&bpmp TEGRA234_CLK_PWM3>; 8492566d28cSJon Hunter resets = <&bpmp TEGRA234_RESET_PWM3>; 8502566d28cSJon Hunter reset-names = "pwm"; 8512566d28cSJon Hunter status = "disabled"; 8522566d28cSJon Hunter #pwm-cells = <2>; 8532566d28cSJon Hunter }; 8542566d28cSJon Hunter 8552566d28cSJon Hunter pwm5: pwm@32c0000 { 8562566d28cSJon Hunter compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 8572838cfddSThierry Reding reg = <0x0 0x32c0000 0x0 0x10000>; 8582566d28cSJon Hunter clocks = <&bpmp TEGRA234_CLK_PWM5>; 8592566d28cSJon Hunter resets = <&bpmp TEGRA234_RESET_PWM5>; 8602566d28cSJon Hunter reset-names = "pwm"; 8612566d28cSJon Hunter status = "disabled"; 8622566d28cSJon Hunter #pwm-cells = <2>; 8632566d28cSJon Hunter }; 8642566d28cSJon Hunter 8652566d28cSJon Hunter pwm6: pwm@32d0000 { 8662566d28cSJon Hunter compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 8672838cfddSThierry Reding reg = <0x0 0x32d0000 0x0 0x10000>; 8682566d28cSJon Hunter clocks = <&bpmp TEGRA234_CLK_PWM6>; 8692566d28cSJon Hunter resets = <&bpmp TEGRA234_RESET_PWM6>; 8702566d28cSJon Hunter reset-names = "pwm"; 8712566d28cSJon Hunter status = "disabled"; 8722566d28cSJon Hunter #pwm-cells = <2>; 8732566d28cSJon Hunter }; 8742566d28cSJon Hunter 8752566d28cSJon Hunter pwm7: pwm@32e0000 { 8762566d28cSJon Hunter compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 8772838cfddSThierry Reding reg = <0x0 0x32e0000 0x0 0x10000>; 8782566d28cSJon Hunter clocks = <&bpmp TEGRA234_CLK_PWM7>; 8792566d28cSJon Hunter resets = <&bpmp TEGRA234_RESET_PWM7>; 8802566d28cSJon Hunter reset-names = "pwm"; 8812566d28cSJon Hunter status = "disabled"; 8822566d28cSJon Hunter #pwm-cells = <2>; 8832566d28cSJon Hunter }; 8842566d28cSJon Hunter 8852566d28cSJon Hunter pwm8: pwm@32f0000 { 8862566d28cSJon Hunter compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 8872838cfddSThierry Reding reg = <0x0 0x32f0000 0x0 0x10000>; 8882566d28cSJon Hunter clocks = <&bpmp TEGRA234_CLK_PWM8>; 8892566d28cSJon Hunter resets = <&bpmp TEGRA234_RESET_PWM8>; 8902566d28cSJon Hunter reset-names = "pwm"; 8912566d28cSJon Hunter status = "disabled"; 8922566d28cSJon Hunter #pwm-cells = <2>; 8932566d28cSJon Hunter }; 8942566d28cSJon Hunter 89571f69ffaSAshish Singhal spi@3300000 { 89671f69ffaSAshish Singhal compatible = "nvidia,tegra234-qspi"; 8972838cfddSThierry Reding reg = <0x0 0x3300000 0x0 0x1000>; 89871f69ffaSAshish Singhal interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 89971f69ffaSAshish Singhal #address-cells = <1>; 90071f69ffaSAshish Singhal #size-cells = <0>; 90171f69ffaSAshish Singhal clocks = <&bpmp TEGRA234_CLK_QSPI1_2X_PM>, 90271f69ffaSAshish Singhal <&bpmp TEGRA234_CLK_QSPI1_PM>; 90371f69ffaSAshish Singhal clock-names = "qspi", "qspi_out"; 90471f69ffaSAshish Singhal resets = <&bpmp TEGRA234_RESET_QSPI1>; 90571f69ffaSAshish Singhal status = "disabled"; 90671f69ffaSAshish Singhal }; 90771f69ffaSAshish Singhal 908d71b893aSPrathamesh Shete mmc@3400000 { 909132b552cSThierry Reding compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci"; 9102838cfddSThierry Reding reg = <0x0 0x03400000 0x0 0x20000>; 911d71b893aSPrathamesh Shete interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 912d71b893aSPrathamesh Shete clocks = <&bpmp TEGRA234_CLK_SDMMC1>, 913d71b893aSPrathamesh Shete <&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>; 914d71b893aSPrathamesh Shete clock-names = "sdhci", "tmclk"; 915d71b893aSPrathamesh Shete assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC1>, 916d71b893aSPrathamesh Shete <&bpmp TEGRA234_CLK_PLLC4_MUXED>; 917d71b893aSPrathamesh Shete assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4_MUXED>, 918d71b893aSPrathamesh Shete <&bpmp TEGRA234_CLK_PLLC4_VCO_DIV2>; 919d71b893aSPrathamesh Shete resets = <&bpmp TEGRA234_RESET_SDMMC1>; 920d71b893aSPrathamesh Shete reset-names = "sdhci"; 921d71b893aSPrathamesh Shete interconnects = <&mc TEGRA234_MEMORY_CLIENT_SDMMCRA &emc>, 922d71b893aSPrathamesh Shete <&mc TEGRA234_MEMORY_CLIENT_SDMMCWA &emc>; 923d71b893aSPrathamesh Shete interconnect-names = "dma-mem", "write"; 924d71b893aSPrathamesh Shete iommus = <&smmu_niso1 TEGRA234_SID_SDMMC1A>; 925d71b893aSPrathamesh Shete pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 926d71b893aSPrathamesh Shete pinctrl-0 = <&sdmmc1_3v3>; 927d71b893aSPrathamesh Shete pinctrl-1 = <&sdmmc1_1v8>; 928d71b893aSPrathamesh Shete nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 929d71b893aSPrathamesh Shete nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x07>; 930d71b893aSPrathamesh Shete nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 931d71b893aSPrathamesh Shete nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 932d71b893aSPrathamesh Shete nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 933d71b893aSPrathamesh Shete nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 934d71b893aSPrathamesh Shete nvidia,default-tap = <14>; 935d71b893aSPrathamesh Shete nvidia,default-trim = <0x8>; 936d71b893aSPrathamesh Shete sd-uhs-sdr25; 937d71b893aSPrathamesh Shete sd-uhs-sdr50; 938d71b893aSPrathamesh Shete sd-uhs-ddr50; 939d71b893aSPrathamesh Shete sd-uhs-sdr104; 940d71b893aSPrathamesh Shete status = "disabled"; 941d71b893aSPrathamesh Shete }; 942d71b893aSPrathamesh Shete 94363944891SThierry Reding mmc@3460000 { 94463944891SThierry Reding compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci"; 9452838cfddSThierry Reding reg = <0x0 0x03460000 0x0 0x20000>; 94663944891SThierry Reding interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 947e086d82dSMikko Perttunen clocks = <&bpmp TEGRA234_CLK_SDMMC4>, 948e086d82dSMikko Perttunen <&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>; 949e086d82dSMikko Perttunen clock-names = "sdhci", "tmclk"; 950e086d82dSMikko Perttunen assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC4>, 951e086d82dSMikko Perttunen <&bpmp TEGRA234_CLK_PLLC4>; 952e086d82dSMikko Perttunen assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4>; 95363944891SThierry Reding resets = <&bpmp TEGRA234_RESET_SDMMC4>; 95463944891SThierry Reding reset-names = "sdhci"; 9556de481e5SThierry Reding interconnects = <&mc TEGRA234_MEMORY_CLIENT_SDMMCRAB &emc>, 9566de481e5SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_SDMMCWAB &emc>; 9576de481e5SThierry Reding interconnect-names = "dma-mem", "write"; 9585710e16aSThierry Reding iommus = <&smmu_niso1 TEGRA234_SID_SDMMC4>; 959e086d82dSMikko Perttunen nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 960e086d82dSMikko Perttunen nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 961e086d82dSMikko Perttunen nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 962e086d82dSMikko Perttunen nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; 963e086d82dSMikko Perttunen nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 964e086d82dSMikko Perttunen nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>; 965e086d82dSMikko Perttunen nvidia,default-tap = <0x8>; 966e086d82dSMikko Perttunen nvidia,default-trim = <0x14>; 967e086d82dSMikko Perttunen nvidia,dqs-trim = <40>; 968e086d82dSMikko Perttunen supports-cqe; 96963944891SThierry Reding status = "disabled"; 97063944891SThierry Reding }; 97163944891SThierry Reding 972621e12a1SMohan Kumar hda@3510000 { 973b2fbcbe1SThierry Reding compatible = "nvidia,tegra234-hda"; 9742838cfddSThierry Reding reg = <0x0 0x3510000 0x0 0x10000>; 975621e12a1SMohan Kumar interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 976621e12a1SMohan Kumar clocks = <&bpmp TEGRA234_CLK_AZA_BIT>, 977621e12a1SMohan Kumar <&bpmp TEGRA234_CLK_AZA_2XBIT>; 978621e12a1SMohan Kumar clock-names = "hda", "hda2codec_2x"; 979621e12a1SMohan Kumar resets = <&bpmp TEGRA234_RESET_HDA>, 980621e12a1SMohan Kumar <&bpmp TEGRA234_RESET_HDACODEC>; 981621e12a1SMohan Kumar reset-names = "hda", "hda2codec_2x"; 982621e12a1SMohan Kumar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_DISP>; 983621e12a1SMohan Kumar interconnects = <&mc TEGRA234_MEMORY_CLIENT_HDAR &emc>, 984621e12a1SMohan Kumar <&mc TEGRA234_MEMORY_CLIENT_HDAW &emc>; 985621e12a1SMohan Kumar interconnect-names = "dma-mem", "write"; 986af4c2773SMohan Kumar iommus = <&smmu_niso0 TEGRA234_SID_HDA>; 987621e12a1SMohan Kumar status = "disabled"; 988621e12a1SMohan Kumar }; 989621e12a1SMohan Kumar 9906e505dd6SWayne Chang xusb_padctl: padctl@3520000 { 9916e505dd6SWayne Chang compatible = "nvidia,tegra234-xusb-padctl"; 9926e505dd6SWayne Chang reg = <0x0 0x03520000 0x0 0x20000>, 9936e505dd6SWayne Chang <0x0 0x03540000 0x0 0x10000>; 9946e505dd6SWayne Chang reg-names = "padctl", "ao"; 9956e505dd6SWayne Chang interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 9966e505dd6SWayne Chang 9976e505dd6SWayne Chang resets = <&bpmp TEGRA234_RESET_XUSB_PADCTL>; 9986e505dd6SWayne Chang reset-names = "padctl"; 9996e505dd6SWayne Chang 10006e505dd6SWayne Chang status = "disabled"; 10016e505dd6SWayne Chang 10026e505dd6SWayne Chang pads { 10036e505dd6SWayne Chang usb2 { 10046e505dd6SWayne Chang clocks = <&bpmp TEGRA234_CLK_USB2_TRK>; 10056e505dd6SWayne Chang clock-names = "trk"; 10066e505dd6SWayne Chang 10076e505dd6SWayne Chang lanes { 10086e505dd6SWayne Chang usb2-0 { 10096e505dd6SWayne Chang nvidia,function = "xusb"; 10106e505dd6SWayne Chang status = "disabled"; 10116e505dd6SWayne Chang #phy-cells = <0>; 10126e505dd6SWayne Chang }; 10136e505dd6SWayne Chang 10146e505dd6SWayne Chang usb2-1 { 10156e505dd6SWayne Chang nvidia,function = "xusb"; 10166e505dd6SWayne Chang status = "disabled"; 10176e505dd6SWayne Chang #phy-cells = <0>; 10186e505dd6SWayne Chang }; 10196e505dd6SWayne Chang 10206e505dd6SWayne Chang usb2-2 { 10216e505dd6SWayne Chang nvidia,function = "xusb"; 10226e505dd6SWayne Chang status = "disabled"; 10236e505dd6SWayne Chang #phy-cells = <0>; 10246e505dd6SWayne Chang }; 10256e505dd6SWayne Chang 10266e505dd6SWayne Chang usb2-3 { 10276e505dd6SWayne Chang nvidia,function = "xusb"; 10286e505dd6SWayne Chang status = "disabled"; 10296e505dd6SWayne Chang #phy-cells = <0>; 10306e505dd6SWayne Chang }; 10316e505dd6SWayne Chang }; 10326e505dd6SWayne Chang }; 10336e505dd6SWayne Chang 10346e505dd6SWayne Chang usb3 { 10356e505dd6SWayne Chang lanes { 10366e505dd6SWayne Chang usb3-0 { 10376e505dd6SWayne Chang nvidia,function = "xusb"; 10386e505dd6SWayne Chang status = "disabled"; 10396e505dd6SWayne Chang #phy-cells = <0>; 10406e505dd6SWayne Chang }; 10416e505dd6SWayne Chang 10426e505dd6SWayne Chang usb3-1 { 10436e505dd6SWayne Chang nvidia,function = "xusb"; 10446e505dd6SWayne Chang status = "disabled"; 10456e505dd6SWayne Chang #phy-cells = <0>; 10466e505dd6SWayne Chang }; 10476e505dd6SWayne Chang 10486e505dd6SWayne Chang usb3-2 { 10496e505dd6SWayne Chang nvidia,function = "xusb"; 10506e505dd6SWayne Chang status = "disabled"; 10516e505dd6SWayne Chang #phy-cells = <0>; 10526e505dd6SWayne Chang }; 10536e505dd6SWayne Chang 10546e505dd6SWayne Chang usb3-3 { 10556e505dd6SWayne Chang nvidia,function = "xusb"; 10566e505dd6SWayne Chang status = "disabled"; 10576e505dd6SWayne Chang #phy-cells = <0>; 10586e505dd6SWayne Chang }; 10596e505dd6SWayne Chang }; 10606e505dd6SWayne Chang }; 10616e505dd6SWayne Chang }; 10626e505dd6SWayne Chang 10636e505dd6SWayne Chang ports { 10646e505dd6SWayne Chang usb2-0 { 10656e505dd6SWayne Chang status = "disabled"; 10666e505dd6SWayne Chang }; 10676e505dd6SWayne Chang 10686e505dd6SWayne Chang usb2-1 { 10696e505dd6SWayne Chang status = "disabled"; 10706e505dd6SWayne Chang }; 10716e505dd6SWayne Chang 10726e505dd6SWayne Chang usb2-2 { 10736e505dd6SWayne Chang status = "disabled"; 10746e505dd6SWayne Chang }; 10756e505dd6SWayne Chang 10766e505dd6SWayne Chang usb2-3 { 10776e505dd6SWayne Chang status = "disabled"; 10786e505dd6SWayne Chang }; 10796e505dd6SWayne Chang 10806e505dd6SWayne Chang usb3-0 { 10816e505dd6SWayne Chang status = "disabled"; 10826e505dd6SWayne Chang }; 10836e505dd6SWayne Chang 10846e505dd6SWayne Chang usb3-1 { 10856e505dd6SWayne Chang status = "disabled"; 10866e505dd6SWayne Chang }; 10876e505dd6SWayne Chang 10886e505dd6SWayne Chang usb3-2 { 10896e505dd6SWayne Chang status = "disabled"; 10906e505dd6SWayne Chang }; 10916e505dd6SWayne Chang 10926e505dd6SWayne Chang usb3-3 { 10936e505dd6SWayne Chang status = "disabled"; 10946e505dd6SWayne Chang }; 10956e505dd6SWayne Chang }; 10966e505dd6SWayne Chang }; 10976e505dd6SWayne Chang 1098320e0a70SJon Hunter usb@3550000 { 1099320e0a70SJon Hunter compatible = "nvidia,tegra234-xudc"; 1100320e0a70SJon Hunter reg = <0x0 0x03550000 0x0 0x8000>, 1101320e0a70SJon Hunter <0x0 0x03558000 0x0 0x8000>; 1102320e0a70SJon Hunter reg-names = "base", "fpci"; 1103320e0a70SJon Hunter interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1104320e0a70SJon Hunter clocks = <&bpmp TEGRA234_CLK_XUSB_CORE_DEV>, 1105320e0a70SJon Hunter <&bpmp TEGRA234_CLK_XUSB_CORE_SS>, 1106320e0a70SJon Hunter <&bpmp TEGRA234_CLK_XUSB_SS>, 1107320e0a70SJon Hunter <&bpmp TEGRA234_CLK_XUSB_FS>; 1108320e0a70SJon Hunter clock-names = "dev", "ss", "ss_src", "fs_src"; 1109320e0a70SJon Hunter interconnects = <&mc TEGRA234_MEMORY_CLIENT_XUSB_DEVR &emc>, 1110320e0a70SJon Hunter <&mc TEGRA234_MEMORY_CLIENT_XUSB_DEVW &emc>; 1111320e0a70SJon Hunter interconnect-names = "dma-mem", "write"; 1112320e0a70SJon Hunter iommus = <&smmu_niso1 TEGRA234_SID_XUSB_DEV>; 1113320e0a70SJon Hunter power-domains = <&bpmp TEGRA234_POWER_DOMAIN_XUSBB>, 1114320e0a70SJon Hunter <&bpmp TEGRA234_POWER_DOMAIN_XUSBA>; 1115320e0a70SJon Hunter power-domain-names = "dev", "ss"; 1116320e0a70SJon Hunter nvidia,xusb-padctl = <&xusb_padctl>; 1117320e0a70SJon Hunter dma-coherent; 1118320e0a70SJon Hunter status = "disabled"; 1119320e0a70SJon Hunter }; 1120320e0a70SJon Hunter 11216e505dd6SWayne Chang usb@3610000 { 11226e505dd6SWayne Chang compatible = "nvidia,tegra234-xusb"; 11236e505dd6SWayne Chang reg = <0x0 0x03610000 0x0 0x40000>, 11246e505dd6SWayne Chang <0x0 0x03600000 0x0 0x10000>, 11256e505dd6SWayne Chang <0x0 0x03650000 0x0 0x10000>; 11266e505dd6SWayne Chang reg-names = "hcd", "fpci", "bar2"; 11276e505dd6SWayne Chang 11286e505dd6SWayne Chang interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 11296e505dd6SWayne Chang <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 11306e505dd6SWayne Chang 11316e505dd6SWayne Chang clocks = <&bpmp TEGRA234_CLK_XUSB_CORE_HOST>, 11326e505dd6SWayne Chang <&bpmp TEGRA234_CLK_XUSB_FALCON>, 11336e505dd6SWayne Chang <&bpmp TEGRA234_CLK_XUSB_CORE_SS>, 11346e505dd6SWayne Chang <&bpmp TEGRA234_CLK_XUSB_SS>, 11356e505dd6SWayne Chang <&bpmp TEGRA234_CLK_CLK_M>, 11366e505dd6SWayne Chang <&bpmp TEGRA234_CLK_XUSB_FS>, 11376e505dd6SWayne Chang <&bpmp TEGRA234_CLK_UTMIP_PLL>, 11386e505dd6SWayne Chang <&bpmp TEGRA234_CLK_CLK_M>, 11396e505dd6SWayne Chang <&bpmp TEGRA234_CLK_PLLE>; 11406e505dd6SWayne Chang clock-names = "xusb_host", "xusb_falcon_src", 11416e505dd6SWayne Chang "xusb_ss", "xusb_ss_src", "xusb_hs_src", 11426e505dd6SWayne Chang "xusb_fs_src", "pll_u_480m", "clk_m", 11436e505dd6SWayne Chang "pll_e"; 11446e505dd6SWayne Chang interconnects = <&mc TEGRA234_MEMORY_CLIENT_XUSB_HOSTR &emc>, 11456e505dd6SWayne Chang <&mc TEGRA234_MEMORY_CLIENT_XUSB_HOSTW &emc>; 11466e505dd6SWayne Chang interconnect-names = "dma-mem", "write"; 11476e505dd6SWayne Chang iommus = <&smmu_niso1 TEGRA234_SID_XUSB_HOST>; 11486e505dd6SWayne Chang 11496e505dd6SWayne Chang power-domains = <&bpmp TEGRA234_POWER_DOMAIN_XUSBC>, 11506e505dd6SWayne Chang <&bpmp TEGRA234_POWER_DOMAIN_XUSBA>; 11516e505dd6SWayne Chang power-domain-names = "xusb_host", "xusb_ss"; 11526e505dd6SWayne Chang 11536e505dd6SWayne Chang nvidia,xusb-padctl = <&xusb_padctl>; 11546e505dd6SWayne Chang dma-coherent; 11556e505dd6SWayne Chang status = "disabled"; 11566e505dd6SWayne Chang }; 11576e505dd6SWayne Chang 115863944891SThierry Reding fuse@3810000 { 115963944891SThierry Reding compatible = "nvidia,tegra234-efuse"; 11602838cfddSThierry Reding reg = <0x0 0x03810000 0x0 0x10000>; 116163944891SThierry Reding clocks = <&bpmp TEGRA234_CLK_FUSE>; 116263944891SThierry Reding clock-names = "fuse"; 116363944891SThierry Reding }; 116463944891SThierry Reding 116529662d62SDipen Patel hte_lic: hardware-timestamp@3aa0000 { 116629662d62SDipen Patel compatible = "nvidia,tegra234-gte-lic"; 116729662d62SDipen Patel reg = <0x0 0x3aa0000 0x0 0x10000>; 116829662d62SDipen Patel interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 116929662d62SDipen Patel nvidia,int-threshold = <1>; 117029662d62SDipen Patel #timestamp-cells = <1>; 117129662d62SDipen Patel }; 117229662d62SDipen Patel 117363944891SThierry Reding hsp_top0: hsp@3c00000 { 117463944891SThierry Reding compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; 11752838cfddSThierry Reding reg = <0x0 0x03c00000 0x0 0xa0000>; 117663944891SThierry Reding interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 117763944891SThierry Reding <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 117863944891SThierry Reding <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 117963944891SThierry Reding <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 118063944891SThierry Reding <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 118163944891SThierry Reding <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 118263944891SThierry Reding <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 118363944891SThierry Reding <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 118463944891SThierry Reding <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 118563944891SThierry Reding interrupt-names = "doorbell", "shared0", "shared1", "shared2", 118663944891SThierry Reding "shared3", "shared4", "shared5", "shared6", 118763944891SThierry Reding "shared7"; 118863944891SThierry Reding #mbox-cells = <2>; 118963944891SThierry Reding }; 119063944891SThierry Reding 119178159542SThierry Reding p2u_hsio_0: phy@3e00000 { 119278159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 11932838cfddSThierry Reding reg = <0x0 0x03e00000 0x0 0x10000>; 119478159542SThierry Reding reg-names = "ctl"; 119578159542SThierry Reding 119678159542SThierry Reding #phy-cells = <0>; 119778159542SThierry Reding }; 119878159542SThierry Reding 119978159542SThierry Reding p2u_hsio_1: phy@3e10000 { 120078159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 12012838cfddSThierry Reding reg = <0x0 0x03e10000 0x0 0x10000>; 120278159542SThierry Reding reg-names = "ctl"; 120378159542SThierry Reding 120478159542SThierry Reding #phy-cells = <0>; 120578159542SThierry Reding }; 120678159542SThierry Reding 120778159542SThierry Reding p2u_hsio_2: phy@3e20000 { 120878159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 12092838cfddSThierry Reding reg = <0x0 0x03e20000 0x0 0x10000>; 121078159542SThierry Reding reg-names = "ctl"; 121178159542SThierry Reding 121278159542SThierry Reding #phy-cells = <0>; 121378159542SThierry Reding }; 121478159542SThierry Reding 121578159542SThierry Reding p2u_hsio_3: phy@3e30000 { 121678159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 12172838cfddSThierry Reding reg = <0x0 0x03e30000 0x0 0x10000>; 121878159542SThierry Reding reg-names = "ctl"; 121978159542SThierry Reding 122078159542SThierry Reding #phy-cells = <0>; 122178159542SThierry Reding }; 122278159542SThierry Reding 122378159542SThierry Reding p2u_hsio_4: phy@3e40000 { 122478159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 12252838cfddSThierry Reding reg = <0x0 0x03e40000 0x0 0x10000>; 122678159542SThierry Reding reg-names = "ctl"; 122778159542SThierry Reding 122878159542SThierry Reding #phy-cells = <0>; 122978159542SThierry Reding }; 123078159542SThierry Reding 123178159542SThierry Reding p2u_hsio_5: phy@3e50000 { 123278159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 12332838cfddSThierry Reding reg = <0x0 0x03e50000 0x0 0x10000>; 123478159542SThierry Reding reg-names = "ctl"; 123578159542SThierry Reding 123678159542SThierry Reding #phy-cells = <0>; 123778159542SThierry Reding }; 123878159542SThierry Reding 123978159542SThierry Reding p2u_hsio_6: phy@3e60000 { 124078159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 12412838cfddSThierry Reding reg = <0x0 0x03e60000 0x0 0x10000>; 124278159542SThierry Reding reg-names = "ctl"; 124378159542SThierry Reding 124478159542SThierry Reding #phy-cells = <0>; 124578159542SThierry Reding }; 124678159542SThierry Reding 124778159542SThierry Reding p2u_hsio_7: phy@3e70000 { 124878159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 12492838cfddSThierry Reding reg = <0x0 0x03e70000 0x0 0x10000>; 125078159542SThierry Reding reg-names = "ctl"; 125178159542SThierry Reding 125278159542SThierry Reding #phy-cells = <0>; 125378159542SThierry Reding }; 125478159542SThierry Reding 125578159542SThierry Reding p2u_nvhs_0: phy@3e90000 { 125678159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 12572838cfddSThierry Reding reg = <0x0 0x03e90000 0x0 0x10000>; 125878159542SThierry Reding reg-names = "ctl"; 125978159542SThierry Reding 126078159542SThierry Reding #phy-cells = <0>; 126178159542SThierry Reding }; 126278159542SThierry Reding 126378159542SThierry Reding p2u_nvhs_1: phy@3ea0000 { 126478159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 12652838cfddSThierry Reding reg = <0x0 0x03ea0000 0x0 0x10000>; 126678159542SThierry Reding reg-names = "ctl"; 126778159542SThierry Reding 126878159542SThierry Reding #phy-cells = <0>; 126978159542SThierry Reding }; 127078159542SThierry Reding 127178159542SThierry Reding p2u_nvhs_2: phy@3eb0000 { 127278159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 12732838cfddSThierry Reding reg = <0x0 0x03eb0000 0x0 0x10000>; 127478159542SThierry Reding reg-names = "ctl"; 127578159542SThierry Reding 127678159542SThierry Reding #phy-cells = <0>; 127778159542SThierry Reding }; 127878159542SThierry Reding 127978159542SThierry Reding p2u_nvhs_3: phy@3ec0000 { 128078159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 12812838cfddSThierry Reding reg = <0x0 0x03ec0000 0x0 0x10000>; 128278159542SThierry Reding reg-names = "ctl"; 128378159542SThierry Reding 128478159542SThierry Reding #phy-cells = <0>; 128578159542SThierry Reding }; 128678159542SThierry Reding 128778159542SThierry Reding p2u_nvhs_4: phy@3ed0000 { 128878159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 12892838cfddSThierry Reding reg = <0x0 0x03ed0000 0x0 0x10000>; 129078159542SThierry Reding reg-names = "ctl"; 129178159542SThierry Reding 129278159542SThierry Reding #phy-cells = <0>; 129378159542SThierry Reding }; 129478159542SThierry Reding 129578159542SThierry Reding p2u_nvhs_5: phy@3ee0000 { 129678159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 12972838cfddSThierry Reding reg = <0x0 0x03ee0000 0x0 0x10000>; 129878159542SThierry Reding reg-names = "ctl"; 129978159542SThierry Reding 130078159542SThierry Reding #phy-cells = <0>; 130178159542SThierry Reding }; 130278159542SThierry Reding 130378159542SThierry Reding p2u_nvhs_6: phy@3ef0000 { 130478159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 13052838cfddSThierry Reding reg = <0x0 0x03ef0000 0x0 0x10000>; 130678159542SThierry Reding reg-names = "ctl"; 130778159542SThierry Reding 130878159542SThierry Reding #phy-cells = <0>; 130978159542SThierry Reding }; 131078159542SThierry Reding 131178159542SThierry Reding p2u_nvhs_7: phy@3f00000 { 131278159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 13132838cfddSThierry Reding reg = <0x0 0x03f00000 0x0 0x10000>; 131478159542SThierry Reding reg-names = "ctl"; 131578159542SThierry Reding 131678159542SThierry Reding #phy-cells = <0>; 131778159542SThierry Reding }; 131878159542SThierry Reding 131978159542SThierry Reding p2u_gbe_0: phy@3f20000 { 132078159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 13212838cfddSThierry Reding reg = <0x0 0x03f20000 0x0 0x10000>; 132278159542SThierry Reding reg-names = "ctl"; 132378159542SThierry Reding 132478159542SThierry Reding #phy-cells = <0>; 132578159542SThierry Reding }; 132678159542SThierry Reding 132778159542SThierry Reding p2u_gbe_1: phy@3f30000 { 132878159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 13292838cfddSThierry Reding reg = <0x0 0x03f30000 0x0 0x10000>; 133078159542SThierry Reding reg-names = "ctl"; 133178159542SThierry Reding 133278159542SThierry Reding #phy-cells = <0>; 133378159542SThierry Reding }; 133478159542SThierry Reding 133578159542SThierry Reding p2u_gbe_2: phy@3f40000 { 133678159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 13372838cfddSThierry Reding reg = <0x0 0x03f40000 0x0 0x10000>; 133878159542SThierry Reding reg-names = "ctl"; 133978159542SThierry Reding 134078159542SThierry Reding #phy-cells = <0>; 134178159542SThierry Reding }; 134278159542SThierry Reding 134378159542SThierry Reding p2u_gbe_3: phy@3f50000 { 134478159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 13452838cfddSThierry Reding reg = <0x0 0x03f50000 0x0 0x10000>; 134678159542SThierry Reding reg-names = "ctl"; 134778159542SThierry Reding 134878159542SThierry Reding #phy-cells = <0>; 134978159542SThierry Reding }; 135078159542SThierry Reding 135178159542SThierry Reding p2u_gbe_4: phy@3f60000 { 135278159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 13532838cfddSThierry Reding reg = <0x0 0x03f60000 0x0 0x10000>; 135478159542SThierry Reding reg-names = "ctl"; 135578159542SThierry Reding 135678159542SThierry Reding #phy-cells = <0>; 135778159542SThierry Reding }; 135878159542SThierry Reding 135978159542SThierry Reding p2u_gbe_5: phy@3f70000 { 136078159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 13612838cfddSThierry Reding reg = <0x0 0x03f70000 0x0 0x10000>; 136278159542SThierry Reding reg-names = "ctl"; 136378159542SThierry Reding 136478159542SThierry Reding #phy-cells = <0>; 136578159542SThierry Reding }; 136678159542SThierry Reding 136778159542SThierry Reding p2u_gbe_6: phy@3f80000 { 136878159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 13692838cfddSThierry Reding reg = <0x0 0x03f80000 0x0 0x10000>; 137078159542SThierry Reding reg-names = "ctl"; 137178159542SThierry Reding 137278159542SThierry Reding #phy-cells = <0>; 137378159542SThierry Reding }; 137478159542SThierry Reding 137578159542SThierry Reding p2u_gbe_7: phy@3f90000 { 137678159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 13772838cfddSThierry Reding reg = <0x0 0x03f90000 0x0 0x10000>; 137878159542SThierry Reding reg-names = "ctl"; 137978159542SThierry Reding 138078159542SThierry Reding #phy-cells = <0>; 138178159542SThierry Reding }; 138278159542SThierry Reding 1383610cdf31SThierry Reding ethernet@6800000 { 1384610cdf31SThierry Reding compatible = "nvidia,tegra234-mgbe"; 13852838cfddSThierry Reding reg = <0x0 0x06800000 0x0 0x10000>, 13862838cfddSThierry Reding <0x0 0x06810000 0x0 0x10000>, 13872838cfddSThierry Reding <0x0 0x068a0000 0x0 0x10000>; 1388610cdf31SThierry Reding reg-names = "hypervisor", "mac", "xpcs"; 1389610cdf31SThierry Reding interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>; 1390610cdf31SThierry Reding interrupt-names = "common"; 1391610cdf31SThierry Reding clocks = <&bpmp TEGRA234_CLK_MGBE0_APP>, 1392610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE0_MAC>, 1393610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE0_MAC_DIVIDER>, 1394610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE0_PTP_REF>, 1395610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT_M>, 1396610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT>, 1397610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE0_TX>, 1398610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE0_EEE_PCS>, 1399610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_INPUT>, 1400610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_M>, 1401610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE0_RX_PCS>, 1402610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE0_TX_PCS>; 1403610cdf31SThierry Reding clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", 1404610cdf31SThierry Reding "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", 1405610cdf31SThierry Reding "rx-pcs", "tx-pcs"; 1406610cdf31SThierry Reding resets = <&bpmp TEGRA234_RESET_MGBE0_MAC>, 1407610cdf31SThierry Reding <&bpmp TEGRA234_RESET_MGBE0_PCS>; 1408610cdf31SThierry Reding reset-names = "mac", "pcs"; 1409610cdf31SThierry Reding interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEARD &emc>, 1410610cdf31SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_MGBEAWR &emc>; 1411610cdf31SThierry Reding interconnect-names = "dma-mem", "write"; 1412610cdf31SThierry Reding iommus = <&smmu_niso0 TEGRA234_SID_MGBE>; 1413610cdf31SThierry Reding power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEA>; 1414610cdf31SThierry Reding status = "disabled"; 1415610cdf31SThierry Reding }; 1416610cdf31SThierry Reding 1417610cdf31SThierry Reding ethernet@6900000 { 1418610cdf31SThierry Reding compatible = "nvidia,tegra234-mgbe"; 14192838cfddSThierry Reding reg = <0x0 0x06900000 0x0 0x10000>, 14202838cfddSThierry Reding <0x0 0x06910000 0x0 0x10000>, 14212838cfddSThierry Reding <0x0 0x069a0000 0x0 0x10000>; 1422610cdf31SThierry Reding reg-names = "hypervisor", "mac", "xpcs"; 1423610cdf31SThierry Reding interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>; 1424610cdf31SThierry Reding interrupt-names = "common"; 1425610cdf31SThierry Reding clocks = <&bpmp TEGRA234_CLK_MGBE1_APP>, 1426610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE1_MAC>, 1427610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE1_MAC_DIVIDER>, 1428610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE1_PTP_REF>, 1429610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE1_RX_INPUT_M>, 1430610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE1_RX_INPUT>, 1431610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE1_TX>, 1432610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE1_EEE_PCS>, 1433610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE1_RX_PCS_INPUT>, 1434610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE1_RX_PCS_M>, 1435610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE1_RX_PCS>, 1436610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE1_TX_PCS>; 1437610cdf31SThierry Reding clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", 1438610cdf31SThierry Reding "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", 1439610cdf31SThierry Reding "rx-pcs", "tx-pcs"; 1440610cdf31SThierry Reding resets = <&bpmp TEGRA234_RESET_MGBE1_MAC>, 1441610cdf31SThierry Reding <&bpmp TEGRA234_RESET_MGBE1_PCS>; 1442610cdf31SThierry Reding reset-names = "mac", "pcs"; 1443610cdf31SThierry Reding interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEBRD &emc>, 1444610cdf31SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_MGBEBWR &emc>; 1445610cdf31SThierry Reding interconnect-names = "dma-mem", "write"; 1446610cdf31SThierry Reding iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF1>; 1447610cdf31SThierry Reding power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEB>; 1448610cdf31SThierry Reding status = "disabled"; 1449610cdf31SThierry Reding }; 1450610cdf31SThierry Reding 1451610cdf31SThierry Reding ethernet@6a00000 { 1452610cdf31SThierry Reding compatible = "nvidia,tegra234-mgbe"; 14532838cfddSThierry Reding reg = <0x0 0x06a00000 0x0 0x10000>, 14542838cfddSThierry Reding <0x0 0x06a10000 0x0 0x10000>, 14552838cfddSThierry Reding <0x0 0x06aa0000 0x0 0x10000>; 1456610cdf31SThierry Reding reg-names = "hypervisor", "mac", "xpcs"; 1457610cdf31SThierry Reding interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>; 1458610cdf31SThierry Reding interrupt-names = "common"; 1459610cdf31SThierry Reding clocks = <&bpmp TEGRA234_CLK_MGBE2_APP>, 1460610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE2_MAC>, 1461610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE2_MAC_DIVIDER>, 1462610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE2_PTP_REF>, 1463610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE2_RX_INPUT_M>, 1464610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE2_RX_INPUT>, 1465610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE2_TX>, 1466610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE2_EEE_PCS>, 1467610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE2_RX_PCS_INPUT>, 1468610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE2_RX_PCS_M>, 1469610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE2_RX_PCS>, 1470610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE2_TX_PCS>; 1471610cdf31SThierry Reding clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", 1472610cdf31SThierry Reding "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", 1473610cdf31SThierry Reding "rx-pcs", "tx-pcs"; 1474610cdf31SThierry Reding resets = <&bpmp TEGRA234_RESET_MGBE2_MAC>, 1475610cdf31SThierry Reding <&bpmp TEGRA234_RESET_MGBE2_PCS>; 1476610cdf31SThierry Reding reset-names = "mac", "pcs"; 1477610cdf31SThierry Reding interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBECRD &emc>, 1478610cdf31SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_MGBECWR &emc>; 1479610cdf31SThierry Reding interconnect-names = "dma-mem", "write"; 1480610cdf31SThierry Reding iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF2>; 1481610cdf31SThierry Reding power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEC>; 1482610cdf31SThierry Reding status = "disabled"; 1483610cdf31SThierry Reding }; 1484610cdf31SThierry Reding 1485610cdf31SThierry Reding ethernet@6b00000 { 1486610cdf31SThierry Reding compatible = "nvidia,tegra234-mgbe"; 14872838cfddSThierry Reding reg = <0x0 0x06b00000 0x0 0x10000>, 14882838cfddSThierry Reding <0x0 0x06b10000 0x0 0x10000>, 14892838cfddSThierry Reding <0x0 0x06ba0000 0x0 0x10000>; 1490610cdf31SThierry Reding reg-names = "hypervisor", "mac", "xpcs"; 1491610cdf31SThierry Reding interrupts = <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 1492610cdf31SThierry Reding interrupt-names = "common"; 1493610cdf31SThierry Reding clocks = <&bpmp TEGRA234_CLK_MGBE3_APP>, 1494610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE3_MAC>, 1495610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE3_MAC_DIVIDER>, 1496610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE3_PTP_REF>, 1497610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE3_RX_INPUT_M>, 1498610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE3_RX_INPUT>, 1499610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE3_TX>, 1500610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE3_EEE_PCS>, 1501610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE3_RX_PCS_INPUT>, 1502610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE3_RX_PCS_M>, 1503610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE3_RX_PCS>, 1504610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE3_TX_PCS>; 1505610cdf31SThierry Reding clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", 1506610cdf31SThierry Reding "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", 1507610cdf31SThierry Reding "rx-pcs", "tx-pcs"; 1508610cdf31SThierry Reding resets = <&bpmp TEGRA234_RESET_MGBE3_MAC>, 1509610cdf31SThierry Reding <&bpmp TEGRA234_RESET_MGBE3_PCS>; 1510610cdf31SThierry Reding reset-names = "mac", "pcs"; 1511610cdf31SThierry Reding interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEDRD &emc>, 1512610cdf31SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_MGBEDWR &emc>; 1513610cdf31SThierry Reding interconnect-names = "dma-mem", "write"; 1514610cdf31SThierry Reding iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF3>; 1515610cdf31SThierry Reding power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBED>; 1516610cdf31SThierry Reding status = "disabled"; 1517610cdf31SThierry Reding }; 1518610cdf31SThierry Reding 15195710e16aSThierry Reding smmu_niso1: iommu@8000000 { 15205710e16aSThierry Reding compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; 15212838cfddSThierry Reding reg = <0x0 0x8000000 0x0 0x1000000>, 15222838cfddSThierry Reding <0x0 0x7000000 0x0 0x1000000>; 15235710e16aSThierry Reding interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15245710e16aSThierry Reding <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, 15255710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15265710e16aSThierry Reding <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, 15275710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15285710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15295710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15305710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15315710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15325710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15335710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15345710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15355710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15365710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15375710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15385710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15395710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15405710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15415710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15425710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15435710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15445710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15455710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15465710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15475710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15485710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15495710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15505710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15515710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15525710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15535710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15545710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15555710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15565710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15575710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15585710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15595710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15605710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15615710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15625710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15635710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15645710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15655710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15665710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15675710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15685710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15695710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15705710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15715710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15725710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15735710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15745710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15755710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15765710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15775710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15785710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15795710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15805710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15815710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15825710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15835710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15845710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15855710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15865710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15875710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15885710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15895710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15905710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15915710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15925710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15935710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15945710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15955710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15965710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15975710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15985710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15995710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16005710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16015710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16025710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16035710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16045710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16055710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16065710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16075710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16085710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16095710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16105710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16115710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16125710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16135710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16145710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16155710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16165710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16175710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16185710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16195710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16205710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16215710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16225710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16235710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16245710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16255710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16265710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16275710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16285710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16295710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16305710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16315710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16325710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16335710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16345710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16355710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16365710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16375710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16385710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16395710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16405710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16415710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16425710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16435710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16445710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16455710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16465710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16475710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16485710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16495710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16505710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16515710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16525710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 16535710e16aSThierry Reding stream-match-mask = <0x7f80>; 16545710e16aSThierry Reding #global-interrupts = <2>; 16555710e16aSThierry Reding #iommu-cells = <1>; 16565710e16aSThierry Reding 16575710e16aSThierry Reding nvidia,memory-controller = <&mc>; 16585710e16aSThierry Reding status = "okay"; 16595710e16aSThierry Reding }; 16605710e16aSThierry Reding 1661302e1540SSumit Gupta sce-fabric@b600000 { 1662302e1540SSumit Gupta compatible = "nvidia,tegra234-sce-fabric"; 16632838cfddSThierry Reding reg = <0x0 0xb600000 0x0 0x40000>; 1664302e1540SSumit Gupta interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 1665302e1540SSumit Gupta status = "okay"; 1666302e1540SSumit Gupta }; 1667302e1540SSumit Gupta 1668302e1540SSumit Gupta rce-fabric@be00000 { 1669302e1540SSumit Gupta compatible = "nvidia,tegra234-rce-fabric"; 16702838cfddSThierry Reding reg = <0x0 0xbe00000 0x0 0x40000>; 1671302e1540SSumit Gupta interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 1672302e1540SSumit Gupta status = "okay"; 1673302e1540SSumit Gupta }; 1674302e1540SSumit Gupta 167563944891SThierry Reding hsp_aon: hsp@c150000 { 167663944891SThierry Reding compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; 16772838cfddSThierry Reding reg = <0x0 0x0c150000 0x0 0x90000>; 167863944891SThierry Reding interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 167963944891SThierry Reding <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 168063944891SThierry Reding <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 168163944891SThierry Reding <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 168263944891SThierry Reding /* 168363944891SThierry Reding * Shared interrupt 0 is routed only to AON/SPE, so 168463944891SThierry Reding * we only have 4 shared interrupts for the CCPLEX. 168563944891SThierry Reding */ 168663944891SThierry Reding interrupt-names = "shared1", "shared2", "shared3", "shared4"; 168763944891SThierry Reding #mbox-cells = <2>; 168863944891SThierry Reding }; 168963944891SThierry Reding 169029662d62SDipen Patel hte_aon: hardware-timestamp@c1e0000 { 169129662d62SDipen Patel compatible = "nvidia,tegra234-gte-aon"; 169229662d62SDipen Patel reg = <0x0 0xc1e0000 0x0 0x10000>; 169329662d62SDipen Patel interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 169429662d62SDipen Patel nvidia,int-threshold = <1>; 169529662d62SDipen Patel nvidia,gpio-controller = <&gpio_aon>; 169629662d62SDipen Patel #timestamp-cells = <1>; 169729662d62SDipen Patel }; 169829662d62SDipen Patel 1699156af9deSAkhil R gen2_i2c: i2c@c240000 { 1700156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 17012838cfddSThierry Reding reg = <0x0 0xc240000 0x0 0x100>; 1702156af9deSAkhil R interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1703260e8d42SJon Hunter #address-cells = <1>; 1704260e8d42SJon Hunter #size-cells = <0>; 1705156af9deSAkhil R status = "disabled"; 1706156af9deSAkhil R clock-frequency = <100000>; 1707156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C2 1708156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 1709156af9deSAkhil R clock-names = "div-clk", "parent"; 1710156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C2>; 1711156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 1712156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C2>; 1713156af9deSAkhil R reset-names = "i2c"; 17148e442805SAkhil R dmas = <&gpcdma 22>, <&gpcdma 22>; 17158e442805SAkhil R dma-names = "rx", "tx"; 1716156af9deSAkhil R }; 1717156af9deSAkhil R 1718156af9deSAkhil R gen8_i2c: i2c@c250000 { 1719156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 17202838cfddSThierry Reding reg = <0x0 0xc250000 0x0 0x100>; 1721156af9deSAkhil R interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1722260e8d42SJon Hunter #address-cells = <1>; 1723260e8d42SJon Hunter #size-cells = <0>; 1724156af9deSAkhil R status = "disabled"; 1725156af9deSAkhil R clock-frequency = <400000>; 1726156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C8 1727156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 1728156af9deSAkhil R clock-names = "div-clk", "parent"; 1729156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C8>; 1730156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 1731156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C8>; 1732156af9deSAkhil R reset-names = "i2c"; 17338e442805SAkhil R dmas = <&gpcdma 0>, <&gpcdma 0>; 17348e442805SAkhil R dma-names = "rx", "tx"; 1735156af9deSAkhil R }; 1736156af9deSAkhil R 173763944891SThierry Reding rtc@c2a0000 { 173863944891SThierry Reding compatible = "nvidia,tegra234-rtc", "nvidia,tegra20-rtc"; 17392838cfddSThierry Reding reg = <0x0 0x0c2a0000 0x0 0x10000>; 174063944891SThierry Reding interrupt-parent = <&pmc>; 174163944891SThierry Reding interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 1742e537addeSMikko Perttunen clocks = <&bpmp TEGRA234_CLK_CLK_32K>; 1743e537addeSMikko Perttunen clock-names = "rtc"; 174463944891SThierry Reding status = "disabled"; 174563944891SThierry Reding }; 174663944891SThierry Reding 1747f0e12668SThierry Reding gpio_aon: gpio@c2f0000 { 1748f0e12668SThierry Reding compatible = "nvidia,tegra234-gpio-aon"; 1749f0e12668SThierry Reding reg-names = "security", "gpio"; 17502838cfddSThierry Reding reg = <0x0 0x0c2f0000 0x0 0x1000>, 17512838cfddSThierry Reding <0x0 0x0c2f1000 0x0 0x1000>; 1752f0e12668SThierry Reding interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1753f0e12668SThierry Reding <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1754f0e12668SThierry Reding <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1755f0e12668SThierry Reding <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 1756f0e12668SThierry Reding #interrupt-cells = <2>; 1757f0e12668SThierry Reding interrupt-controller; 1758f0e12668SThierry Reding #gpio-cells = <2>; 1759f0e12668SThierry Reding gpio-controller; 1760282fde00SPrathamesh Shete gpio-ranges = <&pinmux_aon 0 0 32>; 1761282fde00SPrathamesh Shete }; 1762282fde00SPrathamesh Shete 1763282fde00SPrathamesh Shete pinmux_aon: pinmux@c300000 { 1764282fde00SPrathamesh Shete compatible = "nvidia,tegra234-pinmux-aon"; 1765282fde00SPrathamesh Shete reg = <0x0 0xc300000 0x0 0x4000>; 1766f0e12668SThierry Reding }; 1767f0e12668SThierry Reding 17682566d28cSJon Hunter pwm4: pwm@c340000 { 17692566d28cSJon Hunter compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 17702838cfddSThierry Reding reg = <0x0 0xc340000 0x0 0x10000>; 17712566d28cSJon Hunter clocks = <&bpmp TEGRA234_CLK_PWM4>; 17722566d28cSJon Hunter resets = <&bpmp TEGRA234_RESET_PWM4>; 17732566d28cSJon Hunter reset-names = "pwm"; 17742566d28cSJon Hunter status = "disabled"; 17752566d28cSJon Hunter #pwm-cells = <2>; 17762566d28cSJon Hunter }; 17772566d28cSJon Hunter 177863944891SThierry Reding pmc: pmc@c360000 { 177963944891SThierry Reding compatible = "nvidia,tegra234-pmc"; 17802838cfddSThierry Reding reg = <0x0 0x0c360000 0x0 0x10000>, 17812838cfddSThierry Reding <0x0 0x0c370000 0x0 0x10000>, 17822838cfddSThierry Reding <0x0 0x0c380000 0x0 0x10000>, 17832838cfddSThierry Reding <0x0 0x0c390000 0x0 0x10000>, 17842838cfddSThierry Reding <0x0 0x0c3a0000 0x0 0x10000>; 178563944891SThierry Reding reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 178663944891SThierry Reding 178763944891SThierry Reding #interrupt-cells = <2>; 178863944891SThierry Reding interrupt-controller; 1789d71b893aSPrathamesh Shete 1790d71b893aSPrathamesh Shete sdmmc1_1v8: sdmmc1-1v8 { 1791d71b893aSPrathamesh Shete pins = "sdmmc1-hv"; 1792d71b893aSPrathamesh Shete power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1793d71b893aSPrathamesh Shete }; 1794d71b893aSPrathamesh Shete 179579ed18d9SThierry Reding sdmmc1_3v3: sdmmc1-3v3 { 179679ed18d9SThierry Reding pins = "sdmmc1-hv"; 1797d71b893aSPrathamesh Shete power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1798d71b893aSPrathamesh Shete }; 1799d71b893aSPrathamesh Shete 1800d71b893aSPrathamesh Shete sdmmc3_1v8: sdmmc3-1v8 { 1801d71b893aSPrathamesh Shete pins = "sdmmc3-hv"; 1802d71b893aSPrathamesh Shete power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1803d71b893aSPrathamesh Shete }; 180479ed18d9SThierry Reding 180579ed18d9SThierry Reding sdmmc3_3v3: sdmmc3-3v3 { 180679ed18d9SThierry Reding pins = "sdmmc3-hv"; 180779ed18d9SThierry Reding power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 180879ed18d9SThierry Reding }; 180963944891SThierry Reding }; 181063944891SThierry Reding 1811302e1540SSumit Gupta aon-fabric@c600000 { 1812302e1540SSumit Gupta compatible = "nvidia,tegra234-aon-fabric"; 18132838cfddSThierry Reding reg = <0x0 0xc600000 0x0 0x40000>; 1814302e1540SSumit Gupta interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 1815302e1540SSumit Gupta status = "okay"; 1816302e1540SSumit Gupta }; 1817302e1540SSumit Gupta 1818302e1540SSumit Gupta bpmp-fabric@d600000 { 1819302e1540SSumit Gupta compatible = "nvidia,tegra234-bpmp-fabric"; 18202838cfddSThierry Reding reg = <0x0 0xd600000 0x0 0x40000>; 1821302e1540SSumit Gupta interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1822302e1540SSumit Gupta status = "okay"; 1823302e1540SSumit Gupta }; 1824302e1540SSumit Gupta 1825302e1540SSumit Gupta dce-fabric@de00000 { 1826302e1540SSumit Gupta compatible = "nvidia,tegra234-sce-fabric"; 18272838cfddSThierry Reding reg = <0x0 0xde00000 0x0 0x40000>; 1828302e1540SSumit Gupta interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>; 1829302e1540SSumit Gupta status = "okay"; 1830302e1540SSumit Gupta }; 1831302e1540SSumit Gupta 18322838cfddSThierry Reding ccplex@e000000 { 18332838cfddSThierry Reding compatible = "nvidia,tegra234-ccplex-cluster"; 18342838cfddSThierry Reding reg = <0x0 0x0e000000 0x0 0x5ffff>; 18352838cfddSThierry Reding nvidia,bpmp = <&bpmp>; 18362838cfddSThierry Reding status = "okay"; 18372838cfddSThierry Reding }; 18382838cfddSThierry Reding 183963944891SThierry Reding gic: interrupt-controller@f400000 { 184063944891SThierry Reding compatible = "arm,gic-v3"; 18412838cfddSThierry Reding reg = <0x0 0x0f400000 0x0 0x010000>, /* GICD */ 18422838cfddSThierry Reding <0x0 0x0f440000 0x0 0x200000>; /* GICR */ 184363944891SThierry Reding interrupt-parent = <&gic>; 184463944891SThierry Reding interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 184563944891SThierry Reding 184663944891SThierry Reding #redistributor-regions = <1>; 184763944891SThierry Reding #interrupt-cells = <3>; 184863944891SThierry Reding interrupt-controller; 184963944891SThierry Reding }; 18505710e16aSThierry Reding 18515710e16aSThierry Reding smmu_iso: iommu@10000000 { 18525710e16aSThierry Reding compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; 18532838cfddSThierry Reding reg = <0x0 0x10000000 0x0 0x1000000>; 18545710e16aSThierry Reding interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18555710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18565710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18575710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18585710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18595710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18605710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18615710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18625710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18635710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18645710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18655710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18665710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18675710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18685710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18695710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18705710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18715710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18725710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18735710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18745710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18755710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18765710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18775710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18785710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18795710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18805710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18815710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18825710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18835710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18845710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18855710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18865710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18875710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18885710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18895710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18905710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18915710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18925710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18935710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18945710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18955710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18965710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18975710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18985710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18995710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19005710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19015710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19025710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19035710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19045710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19055710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19065710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19075710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19085710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19095710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19105710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19115710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19125710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19135710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19145710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19155710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19165710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19175710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19185710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19195710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19205710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19215710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19225710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19235710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19245710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19255710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19265710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19275710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19285710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19295710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19305710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19315710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19325710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19335710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19345710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19355710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19365710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19375710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19385710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19395710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19405710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19415710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19425710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19435710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19445710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19455710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19465710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19475710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19485710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19495710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19505710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19515710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19525710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19535710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19545710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19555710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19565710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19575710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19585710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19595710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19605710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19615710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19625710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19635710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19645710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19655710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19665710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19675710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19685710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19695710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19705710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19715710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19725710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19735710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19745710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19755710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19765710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19775710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19785710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19795710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19805710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19815710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19825710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 19835710e16aSThierry Reding stream-match-mask = <0x7f80>; 19845710e16aSThierry Reding #global-interrupts = <1>; 19855710e16aSThierry Reding #iommu-cells = <1>; 19865710e16aSThierry Reding 19875710e16aSThierry Reding nvidia,memory-controller = <&mc>; 19885710e16aSThierry Reding status = "okay"; 19895710e16aSThierry Reding }; 19905710e16aSThierry Reding 19915710e16aSThierry Reding smmu_niso0: iommu@12000000 { 19925710e16aSThierry Reding compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; 19932838cfddSThierry Reding reg = <0x0 0x12000000 0x0 0x1000000>, 19942838cfddSThierry Reding <0x0 0x11000000 0x0 0x1000000>; 19955710e16aSThierry Reding interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19965710e16aSThierry Reding <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 19975710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19985710e16aSThierry Reding <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 19995710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20005710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20015710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20025710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20035710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20045710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20055710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20065710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20075710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20085710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20095710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20105710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20115710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20125710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20135710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20145710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20155710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20165710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20175710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20185710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20195710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20205710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20215710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20225710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20235710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20245710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20255710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20265710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20275710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20285710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20295710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20305710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20315710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20325710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20335710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20345710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20355710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20365710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20375710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20385710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20395710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20405710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20415710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20425710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20435710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20445710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20455710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20465710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20475710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20485710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20495710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20505710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20515710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20525710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20535710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20545710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20555710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20565710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20575710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20585710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20595710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20605710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20615710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20625710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20635710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20645710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20655710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20665710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20675710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20685710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20695710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20705710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20715710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20725710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20735710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20745710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20755710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20765710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20775710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20785710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20795710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20805710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20815710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20825710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20835710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20845710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20855710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20865710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20875710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20885710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20895710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20905710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20915710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20925710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20935710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20945710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20955710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20965710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20975710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20985710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20995710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21005710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21015710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21025710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21035710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21045710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21055710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21065710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21075710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21085710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21095710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21105710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21115710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21125710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21135710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21145710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21155710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21165710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21175710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21185710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21195710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21205710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21215710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21225710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21235710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21245710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 21255710e16aSThierry Reding stream-match-mask = <0x7f80>; 21265710e16aSThierry Reding #global-interrupts = <2>; 21275710e16aSThierry Reding #iommu-cells = <1>; 21285710e16aSThierry Reding 21295710e16aSThierry Reding nvidia,memory-controller = <&mc>; 21305710e16aSThierry Reding status = "okay"; 21315710e16aSThierry Reding }; 2132302e1540SSumit Gupta 2133302e1540SSumit Gupta cbb-fabric@13a00000 { 2134302e1540SSumit Gupta compatible = "nvidia,tegra234-cbb-fabric"; 21352838cfddSThierry Reding reg = <0x0 0x13a00000 0x0 0x400000>; 2136302e1540SSumit Gupta interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 2137302e1540SSumit Gupta status = "okay"; 2138302e1540SSumit Gupta }; 2139962c400dSSumit Gupta 214079ed18d9SThierry Reding host1x@13e00000 { 214179ed18d9SThierry Reding compatible = "nvidia,tegra234-host1x"; 214279ed18d9SThierry Reding reg = <0x0 0x13e00000 0x0 0x10000>, 214379ed18d9SThierry Reding <0x0 0x13e10000 0x0 0x10000>, 214479ed18d9SThierry Reding <0x0 0x13e40000 0x0 0x10000>; 214579ed18d9SThierry Reding reg-names = "common", "hypervisor", "vm"; 214679ed18d9SThierry Reding interrupts = <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, 214779ed18d9SThierry Reding <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, 214879ed18d9SThierry Reding <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, 214979ed18d9SThierry Reding <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, 215079ed18d9SThierry Reding <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, 215179ed18d9SThierry Reding <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>, 215279ed18d9SThierry Reding <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>, 215379ed18d9SThierry Reding <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>, 215479ed18d9SThierry Reding <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 215579ed18d9SThierry Reding interrupt-names = "syncpt0", "syncpt1", "syncpt2", "syncpt3", "syncpt4", 215679ed18d9SThierry Reding "syncpt5", "syncpt6", "syncpt7", "host1x"; 215779ed18d9SThierry Reding clocks = <&bpmp TEGRA234_CLK_HOST1X>; 215879ed18d9SThierry Reding clock-names = "host1x"; 215979ed18d9SThierry Reding 216079ed18d9SThierry Reding #address-cells = <2>; 216179ed18d9SThierry Reding #size-cells = <2>; 216279ed18d9SThierry Reding ranges = <0x0 0x14800000 0x0 0x14800000 0x0 0x02000000>; 216379ed18d9SThierry Reding 216479ed18d9SThierry Reding interconnects = <&mc TEGRA234_MEMORY_CLIENT_HOST1XDMAR &emc>; 216579ed18d9SThierry Reding interconnect-names = "dma-mem"; 216679ed18d9SThierry Reding iommus = <&smmu_niso1 TEGRA234_SID_HOST1X>; 2167361238cdSMikko Perttunen dma-coherent; 216879ed18d9SThierry Reding 216979ed18d9SThierry Reding /* Context isolation domains */ 217079ed18d9SThierry Reding iommu-map = <0 &smmu_niso0 TEGRA234_SID_HOST1X_CTX0 1>, 217179ed18d9SThierry Reding <1 &smmu_niso0 TEGRA234_SID_HOST1X_CTX1 1>, 217279ed18d9SThierry Reding <2 &smmu_niso0 TEGRA234_SID_HOST1X_CTX2 1>, 217379ed18d9SThierry Reding <3 &smmu_niso0 TEGRA234_SID_HOST1X_CTX3 1>, 217479ed18d9SThierry Reding <4 &smmu_niso0 TEGRA234_SID_HOST1X_CTX4 1>, 217579ed18d9SThierry Reding <5 &smmu_niso0 TEGRA234_SID_HOST1X_CTX5 1>, 217679ed18d9SThierry Reding <6 &smmu_niso0 TEGRA234_SID_HOST1X_CTX6 1>, 217779ed18d9SThierry Reding <7 &smmu_niso0 TEGRA234_SID_HOST1X_CTX7 1>, 217879ed18d9SThierry Reding <8 &smmu_niso1 TEGRA234_SID_HOST1X_CTX0 1>, 217979ed18d9SThierry Reding <9 &smmu_niso1 TEGRA234_SID_HOST1X_CTX1 1>, 218079ed18d9SThierry Reding <10 &smmu_niso1 TEGRA234_SID_HOST1X_CTX2 1>, 218179ed18d9SThierry Reding <11 &smmu_niso1 TEGRA234_SID_HOST1X_CTX3 1>, 218279ed18d9SThierry Reding <12 &smmu_niso1 TEGRA234_SID_HOST1X_CTX4 1>, 218379ed18d9SThierry Reding <13 &smmu_niso1 TEGRA234_SID_HOST1X_CTX5 1>, 218479ed18d9SThierry Reding <14 &smmu_niso1 TEGRA234_SID_HOST1X_CTX6 1>, 218579ed18d9SThierry Reding <15 &smmu_niso1 TEGRA234_SID_HOST1X_CTX7 1>; 218679ed18d9SThierry Reding 218779ed18d9SThierry Reding vic@15340000 { 218879ed18d9SThierry Reding compatible = "nvidia,tegra234-vic"; 218979ed18d9SThierry Reding reg = <0x0 0x15340000 0x0 0x00040000>; 219079ed18d9SThierry Reding interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 219179ed18d9SThierry Reding clocks = <&bpmp TEGRA234_CLK_VIC>; 219279ed18d9SThierry Reding clock-names = "vic"; 219379ed18d9SThierry Reding resets = <&bpmp TEGRA234_RESET_VIC>; 219479ed18d9SThierry Reding reset-names = "vic"; 219579ed18d9SThierry Reding 219679ed18d9SThierry Reding power-domains = <&bpmp TEGRA234_POWER_DOMAIN_VIC>; 219779ed18d9SThierry Reding interconnects = <&mc TEGRA234_MEMORY_CLIENT_VICSRD &emc>, 219879ed18d9SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_VICSWR &emc>; 219979ed18d9SThierry Reding interconnect-names = "dma-mem", "write"; 220079ed18d9SThierry Reding iommus = <&smmu_niso1 TEGRA234_SID_VIC>; 220179ed18d9SThierry Reding dma-coherent; 220279ed18d9SThierry Reding }; 220379ed18d9SThierry Reding 220479ed18d9SThierry Reding nvdec@15480000 { 220579ed18d9SThierry Reding compatible = "nvidia,tegra234-nvdec"; 220679ed18d9SThierry Reding reg = <0x0 0x15480000 0x0 0x00040000>; 220779ed18d9SThierry Reding clocks = <&bpmp TEGRA234_CLK_NVDEC>, 220879ed18d9SThierry Reding <&bpmp TEGRA234_CLK_FUSE>, 220979ed18d9SThierry Reding <&bpmp TEGRA234_CLK_TSEC_PKA>; 221079ed18d9SThierry Reding clock-names = "nvdec", "fuse", "tsec_pka"; 221179ed18d9SThierry Reding resets = <&bpmp TEGRA234_RESET_NVDEC>; 221279ed18d9SThierry Reding reset-names = "nvdec"; 221379ed18d9SThierry Reding power-domains = <&bpmp TEGRA234_POWER_DOMAIN_NVDEC>; 221479ed18d9SThierry Reding interconnects = <&mc TEGRA234_MEMORY_CLIENT_NVDECSRD &emc>, 221579ed18d9SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_NVDECSWR &emc>; 221679ed18d9SThierry Reding interconnect-names = "dma-mem", "write"; 221779ed18d9SThierry Reding iommus = <&smmu_niso1 TEGRA234_SID_NVDEC>; 221879ed18d9SThierry Reding dma-coherent; 221979ed18d9SThierry Reding 222079ed18d9SThierry Reding nvidia,memory-controller = <&mc>; 222179ed18d9SThierry Reding 222279ed18d9SThierry Reding /* 222379ed18d9SThierry Reding * Placeholder values that firmware needs to update with the real 222479ed18d9SThierry Reding * offsets parsed from the microcode headers. 222579ed18d9SThierry Reding */ 222679ed18d9SThierry Reding nvidia,bl-manifest-offset = <0>; 222779ed18d9SThierry Reding nvidia,bl-data-offset = <0>; 222879ed18d9SThierry Reding nvidia,bl-code-offset = <0>; 222979ed18d9SThierry Reding nvidia,os-manifest-offset = <0>; 223079ed18d9SThierry Reding nvidia,os-data-offset = <0>; 223179ed18d9SThierry Reding nvidia,os-code-offset = <0>; 223279ed18d9SThierry Reding 223379ed18d9SThierry Reding /* 223479ed18d9SThierry Reding * Firmware needs to set this to "okay" once the above values have 223579ed18d9SThierry Reding * been updated. 223679ed18d9SThierry Reding */ 223779ed18d9SThierry Reding status = "disabled"; 223879ed18d9SThierry Reding }; 223979ed18d9SThierry Reding }; 224079ed18d9SThierry Reding 2241ec142c44SVidya Sagar pcie@140a0000 { 2242ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie"; 2243ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CA>; 2244ec142c44SVidya Sagar reg = <0x00 0x140a0000 0x0 0x00020000>, /* appl registers (128K) */ 2245ec142c44SVidya Sagar <0x00 0x2a000000 0x0 0x00040000>, /* configuration space (256K) */ 2246ec142c44SVidya Sagar <0x00 0x2a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2247794b834dSVidya Sagar <0x00 0x2a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2248794b834dSVidya Sagar <0x35 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2249794b834dSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2250ec142c44SVidya Sagar 2251ec142c44SVidya Sagar #address-cells = <3>; 2252ec142c44SVidya Sagar #size-cells = <2>; 2253ec142c44SVidya Sagar device_type = "pci"; 2254ec142c44SVidya Sagar num-lanes = <4>; 2255ec142c44SVidya Sagar num-viewport = <8>; 2256ec142c44SVidya Sagar linux,pci-domain = <8>; 2257ec142c44SVidya Sagar 2258ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX2_C8_CORE>; 2259ec142c44SVidya Sagar clock-names = "core"; 2260ec142c44SVidya Sagar 2261ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX2_CORE_8_APB>, 2262ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX2_CORE_8>; 2263ec142c44SVidya Sagar reset-names = "apb", "core"; 2264ec142c44SVidya Sagar 2265ec142c44SVidya Sagar interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2266ec142c44SVidya Sagar <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2267ec142c44SVidya Sagar interrupt-names = "intr", "msi"; 2268ec142c44SVidya Sagar 2269ec142c44SVidya Sagar #interrupt-cells = <1>; 2270ec142c44SVidya Sagar interrupt-map-mask = <0 0 0 0>; 2271ec142c44SVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 2272ec142c44SVidya Sagar 2273ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 8>; 2274ec142c44SVidya Sagar 2275ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2276ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2277ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2278ec142c44SVidya Sagar 2279ec142c44SVidya Sagar bus-range = <0x0 0xff>; 2280ec142c44SVidya Sagar 2281ec142c44SVidya Sagar ranges = <0x43000000 0x32 0x40000000 0x32 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2282ec142c44SVidya Sagar <0x02000000 0x0 0x40000000 0x35 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2283ec142c44SVidya Sagar <0x01000000 0x0 0x2a100000 0x00 0x2a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2284ec142c44SVidya Sagar 2285ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE8AR &emc>, 2286ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE8AW &emc>; 2287ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2288ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE8 0x1000>; 2289ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2290ec142c44SVidya Sagar dma-coherent; 2291ec142c44SVidya Sagar 2292ec142c44SVidya Sagar status = "disabled"; 2293ec142c44SVidya Sagar }; 2294ec142c44SVidya Sagar 2295ec142c44SVidya Sagar pcie@140c0000 { 2296ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie"; 2297ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CB>; 2298ec142c44SVidya Sagar reg = <0x00 0x140c0000 0x0 0x00020000>, /* appl registers (128K) */ 2299ec142c44SVidya Sagar <0x00 0x2c000000 0x0 0x00040000>, /* configuration space (256K) */ 2300ec142c44SVidya Sagar <0x00 0x2c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2301794b834dSVidya Sagar <0x00 0x2c080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2302794b834dSVidya Sagar <0x38 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2303794b834dSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2304ec142c44SVidya Sagar 2305ec142c44SVidya Sagar #address-cells = <3>; 2306ec142c44SVidya Sagar #size-cells = <2>; 2307ec142c44SVidya Sagar device_type = "pci"; 2308ec142c44SVidya Sagar num-lanes = <4>; 2309ec142c44SVidya Sagar num-viewport = <8>; 2310ec142c44SVidya Sagar linux,pci-domain = <9>; 2311ec142c44SVidya Sagar 2312ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX2_C9_CORE>; 2313ec142c44SVidya Sagar clock-names = "core"; 2314ec142c44SVidya Sagar 2315ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX2_CORE_9_APB>, 2316ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX2_CORE_9>; 2317ec142c44SVidya Sagar reset-names = "apb", "core"; 2318ec142c44SVidya Sagar 2319ec142c44SVidya Sagar interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2320ec142c44SVidya Sagar <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2321ec142c44SVidya Sagar interrupt-names = "intr", "msi"; 2322ec142c44SVidya Sagar 2323ec142c44SVidya Sagar #interrupt-cells = <1>; 2324ec142c44SVidya Sagar interrupt-map-mask = <0 0 0 0>; 2325ec142c44SVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2326ec142c44SVidya Sagar 2327ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 9>; 2328ec142c44SVidya Sagar 2329ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2330ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2331ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2332ec142c44SVidya Sagar 2333ec142c44SVidya Sagar bus-range = <0x0 0xff>; 2334ec142c44SVidya Sagar 233524840065SVidya Sagar ranges = <0x43000000 0x35 0x40000000 0x35 0x40000000 0x2 0xc0000000>, /* prefetchable memory (11264 MB) */ 2336ec142c44SVidya Sagar <0x02000000 0x0 0x40000000 0x38 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2337ec142c44SVidya Sagar <0x01000000 0x0 0x2c100000 0x00 0x2c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2338ec142c44SVidya Sagar 2339ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE9AR &emc>, 2340ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE9AW &emc>; 2341ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2342ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE9 0x1000>; 2343ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2344ec142c44SVidya Sagar dma-coherent; 2345ec142c44SVidya Sagar 2346ec142c44SVidya Sagar status = "disabled"; 2347ec142c44SVidya Sagar }; 2348ec142c44SVidya Sagar 2349ec142c44SVidya Sagar pcie@140e0000 { 2350ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie"; 2351ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CC>; 2352ec142c44SVidya Sagar reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K) */ 2353ec142c44SVidya Sagar <0x00 0x2e000000 0x0 0x00040000>, /* configuration space (256K) */ 2354ec142c44SVidya Sagar <0x00 0x2e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2355794b834dSVidya Sagar <0x00 0x2e080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2356794b834dSVidya Sagar <0x3b 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2357794b834dSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2358ec142c44SVidya Sagar 2359ec142c44SVidya Sagar #address-cells = <3>; 2360ec142c44SVidya Sagar #size-cells = <2>; 2361ec142c44SVidya Sagar device_type = "pci"; 2362ec142c44SVidya Sagar num-lanes = <4>; 2363ec142c44SVidya Sagar num-viewport = <8>; 2364ec142c44SVidya Sagar linux,pci-domain = <10>; 2365ec142c44SVidya Sagar 2366ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX2_C10_CORE>; 2367ec142c44SVidya Sagar clock-names = "core"; 2368ec142c44SVidya Sagar 2369ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX2_CORE_10_APB>, 2370ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX2_CORE_10>; 2371ec142c44SVidya Sagar reset-names = "apb", "core"; 2372ec142c44SVidya Sagar 2373ec142c44SVidya Sagar interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2374ec142c44SVidya Sagar <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2375ec142c44SVidya Sagar interrupt-names = "intr", "msi"; 2376ec142c44SVidya Sagar 2377ec142c44SVidya Sagar #interrupt-cells = <1>; 2378ec142c44SVidya Sagar interrupt-map-mask = <0 0 0 0>; 2379ec142c44SVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 2380ec142c44SVidya Sagar 2381ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 10>; 2382ec142c44SVidya Sagar 2383ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2384ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2385ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2386ec142c44SVidya Sagar 2387ec142c44SVidya Sagar bus-range = <0x0 0xff>; 2388ec142c44SVidya Sagar 2389ec142c44SVidya Sagar ranges = <0x43000000 0x38 0x40000000 0x38 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2390ec142c44SVidya Sagar <0x02000000 0x0 0x40000000 0x3b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2391ec142c44SVidya Sagar <0x01000000 0x0 0x2e100000 0x00 0x2e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2392ec142c44SVidya Sagar 2393ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE10AR &emc>, 2394ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE10AW &emc>; 2395ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2396ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>; 2397ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2398ec142c44SVidya Sagar dma-coherent; 2399ec142c44SVidya Sagar 2400ec142c44SVidya Sagar status = "disabled"; 2401ec142c44SVidya Sagar }; 2402ec142c44SVidya Sagar 24032838cfddSThierry Reding pcie-ep@140e0000 { 24042838cfddSThierry Reding compatible = "nvidia,tegra234-pcie-ep"; 24052838cfddSThierry Reding power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CC>; 24062838cfddSThierry Reding reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K) */ 24072838cfddSThierry Reding <0x00 0x2e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 24082838cfddSThierry Reding <0x00 0x2e080000 0x0 0x00040000>, /* DBI space (256K) */ 24092838cfddSThierry Reding <0x38 0x40000000 0x3 0x00000000>; /* Address Space (12G) */ 24102838cfddSThierry Reding reg-names = "appl", "atu_dma", "dbi", "addr_space"; 24112838cfddSThierry Reding 24122838cfddSThierry Reding num-lanes = <4>; 24132838cfddSThierry Reding 24142838cfddSThierry Reding clocks = <&bpmp TEGRA234_CLK_PEX2_C10_CORE>; 24152838cfddSThierry Reding clock-names = "core"; 24162838cfddSThierry Reding 24172838cfddSThierry Reding resets = <&bpmp TEGRA234_RESET_PEX2_CORE_10_APB>, 24182838cfddSThierry Reding <&bpmp TEGRA234_RESET_PEX2_CORE_10>; 24192838cfddSThierry Reding reset-names = "apb", "core"; 24202838cfddSThierry Reding 24212838cfddSThierry Reding interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 24222838cfddSThierry Reding interrupt-names = "intr"; 24232838cfddSThierry Reding 24242838cfddSThierry Reding nvidia,bpmp = <&bpmp 10>; 24252838cfddSThierry Reding 24262838cfddSThierry Reding nvidia,enable-ext-refclk; 24272838cfddSThierry Reding nvidia,aspm-cmrt-us = <60>; 24282838cfddSThierry Reding nvidia,aspm-pwr-on-t-us = <20>; 24292838cfddSThierry Reding nvidia,aspm-l0s-entrance-latency-us = <3>; 24302838cfddSThierry Reding 24312838cfddSThierry Reding interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE10AR &emc>, 24322838cfddSThierry Reding <&mc TEGRA234_MEMORY_CLIENT_PCIE10AW &emc>; 24332838cfddSThierry Reding interconnect-names = "dma-mem", "write"; 24342838cfddSThierry Reding iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>; 24352838cfddSThierry Reding iommu-map-mask = <0x0>; 24362838cfddSThierry Reding dma-coherent; 24372838cfddSThierry Reding 24382838cfddSThierry Reding status = "disabled"; 24392838cfddSThierry Reding }; 24402838cfddSThierry Reding 2441ec142c44SVidya Sagar pcie@14100000 { 2442ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie"; 2443ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>; 2444ec142c44SVidya Sagar reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */ 2445ec142c44SVidya Sagar <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */ 2446ec142c44SVidya Sagar <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2447794b834dSVidya Sagar <0x00 0x30080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2448794b834dSVidya Sagar <0x20 0xb0000000 0x0 0x10000000>; /* ECAM (256MB) */ 2449794b834dSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2450ec142c44SVidya Sagar 2451ec142c44SVidya Sagar #address-cells = <3>; 2452ec142c44SVidya Sagar #size-cells = <2>; 2453ec142c44SVidya Sagar device_type = "pci"; 2454ec142c44SVidya Sagar num-lanes = <1>; 2455ec142c44SVidya Sagar num-viewport = <8>; 2456ec142c44SVidya Sagar linux,pci-domain = <1>; 2457ec142c44SVidya Sagar 2458ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX0_C1_CORE>; 2459ec142c44SVidya Sagar clock-names = "core"; 2460ec142c44SVidya Sagar 2461ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX0_CORE_1_APB>, 2462ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX0_CORE_1>; 2463ec142c44SVidya Sagar reset-names = "apb", "core"; 2464ec142c44SVidya Sagar 2465ec142c44SVidya Sagar interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2466ec142c44SVidya Sagar <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2467ec142c44SVidya Sagar interrupt-names = "intr", "msi"; 2468ec142c44SVidya Sagar 2469ec142c44SVidya Sagar #interrupt-cells = <1>; 2470ec142c44SVidya Sagar interrupt-map-mask = <0 0 0 0>; 2471ec142c44SVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 2472ec142c44SVidya Sagar 2473ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 1>; 2474ec142c44SVidya Sagar 2475ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2476ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2477ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2478ec142c44SVidya Sagar 2479ec142c44SVidya Sagar bus-range = <0x0 0xff>; 2480ec142c44SVidya Sagar 2481ec142c44SVidya Sagar ranges = <0x43000000 0x20 0x80000000 0x20 0x80000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ 2482ec142c44SVidya Sagar <0x02000000 0x0 0x40000000 0x20 0xa8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2483ec142c44SVidya Sagar <0x01000000 0x0 0x30100000 0x00 0x30100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2484ec142c44SVidya Sagar 2485ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE1R &emc>, 2486ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE1W &emc>; 2487ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2488ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE1 0x1000>; 2489ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2490ec142c44SVidya Sagar dma-coherent; 2491ec142c44SVidya Sagar 2492ec142c44SVidya Sagar status = "disabled"; 2493ec142c44SVidya Sagar }; 2494ec142c44SVidya Sagar 2495ec142c44SVidya Sagar pcie@14120000 { 2496ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie"; 2497ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>; 2498ec142c44SVidya Sagar reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */ 2499ec142c44SVidya Sagar <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */ 2500ec142c44SVidya Sagar <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2501794b834dSVidya Sagar <0x00 0x32080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2502794b834dSVidya Sagar <0x20 0xf0000000 0x0 0x10000000>; /* ECAM (256MB) */ 2503794b834dSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2504ec142c44SVidya Sagar 2505ec142c44SVidya Sagar #address-cells = <3>; 2506ec142c44SVidya Sagar #size-cells = <2>; 2507ec142c44SVidya Sagar device_type = "pci"; 2508ec142c44SVidya Sagar num-lanes = <1>; 2509ec142c44SVidya Sagar num-viewport = <8>; 2510ec142c44SVidya Sagar linux,pci-domain = <2>; 2511ec142c44SVidya Sagar 2512ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX0_C2_CORE>; 2513ec142c44SVidya Sagar clock-names = "core"; 2514ec142c44SVidya Sagar 2515ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX0_CORE_2_APB>, 2516ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX0_CORE_2>; 2517ec142c44SVidya Sagar reset-names = "apb", "core"; 2518ec142c44SVidya Sagar 2519ec142c44SVidya Sagar interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2520ec142c44SVidya Sagar <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2521ec142c44SVidya Sagar interrupt-names = "intr", "msi"; 2522ec142c44SVidya Sagar 2523ec142c44SVidya Sagar #interrupt-cells = <1>; 2524ec142c44SVidya Sagar interrupt-map-mask = <0 0 0 0>; 2525ec142c44SVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 2526ec142c44SVidya Sagar 2527ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 2>; 2528ec142c44SVidya Sagar 2529ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2530ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2531ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2532ec142c44SVidya Sagar 2533ec142c44SVidya Sagar bus-range = <0x0 0xff>; 2534ec142c44SVidya Sagar 2535ec142c44SVidya Sagar ranges = <0x43000000 0x20 0xc0000000 0x20 0xc0000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ 2536ec142c44SVidya Sagar <0x02000000 0x0 0x40000000 0x20 0xe8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2537ec142c44SVidya Sagar <0x01000000 0x0 0x32100000 0x00 0x32100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2538ec142c44SVidya Sagar 2539ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE2AR &emc>, 2540ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE2AW &emc>; 2541ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2542ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE2 0x1000>; 2543ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2544ec142c44SVidya Sagar dma-coherent; 2545ec142c44SVidya Sagar 2546ec142c44SVidya Sagar status = "disabled"; 2547ec142c44SVidya Sagar }; 2548ec142c44SVidya Sagar 2549ec142c44SVidya Sagar pcie@14140000 { 2550ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie"; 2551ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>; 2552ec142c44SVidya Sagar reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */ 2553ec142c44SVidya Sagar <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */ 2554ec142c44SVidya Sagar <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2555794b834dSVidya Sagar <0x00 0x34080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2556794b834dSVidya Sagar <0x21 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2557794b834dSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2558ec142c44SVidya Sagar 2559ec142c44SVidya Sagar #address-cells = <3>; 2560ec142c44SVidya Sagar #size-cells = <2>; 2561ec142c44SVidya Sagar device_type = "pci"; 2562ec142c44SVidya Sagar num-lanes = <1>; 2563ec142c44SVidya Sagar num-viewport = <8>; 2564ec142c44SVidya Sagar linux,pci-domain = <3>; 2565ec142c44SVidya Sagar 2566ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX0_C3_CORE>; 2567ec142c44SVidya Sagar clock-names = "core"; 2568ec142c44SVidya Sagar 2569ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX0_CORE_3_APB>, 2570ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX0_CORE_3>; 2571ec142c44SVidya Sagar reset-names = "apb", "core"; 2572ec142c44SVidya Sagar 2573ec142c44SVidya Sagar interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2574ec142c44SVidya Sagar <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2575ec142c44SVidya Sagar interrupt-names = "intr", "msi"; 2576ec142c44SVidya Sagar 2577ec142c44SVidya Sagar #interrupt-cells = <1>; 2578ec142c44SVidya Sagar interrupt-map-mask = <0 0 0 0>; 2579ec142c44SVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 2580ec142c44SVidya Sagar 2581ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 3>; 2582ec142c44SVidya Sagar 2583ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2584ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2585ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2586ec142c44SVidya Sagar 2587ec142c44SVidya Sagar bus-range = <0x0 0xff>; 2588ec142c44SVidya Sagar 2589ec142c44SVidya Sagar ranges = <0x43000000 0x21 0x00000000 0x21 0x00000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ 259047a2f35dSVidya Sagar <0x02000000 0x0 0x40000000 0x21 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2591ec142c44SVidya Sagar <0x01000000 0x0 0x34100000 0x00 0x34100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2592ec142c44SVidya Sagar 2593ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE3R &emc>, 2594ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE3W &emc>; 2595ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2596ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE3 0x1000>; 2597ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2598ec142c44SVidya Sagar dma-coherent; 2599ec142c44SVidya Sagar 2600ec142c44SVidya Sagar status = "disabled"; 2601ec142c44SVidya Sagar }; 2602ec142c44SVidya Sagar 2603ec142c44SVidya Sagar pcie@14160000 { 2604ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie"; 2605ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BB>; 2606ec142c44SVidya Sagar reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2607ec142c44SVidya Sagar <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ 2608ec142c44SVidya Sagar <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2609794b834dSVidya Sagar <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2610794b834dSVidya Sagar <0x24 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2611794b834dSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2612ec142c44SVidya Sagar 2613ec142c44SVidya Sagar #address-cells = <3>; 2614ec142c44SVidya Sagar #size-cells = <2>; 2615ec142c44SVidya Sagar device_type = "pci"; 2616ec142c44SVidya Sagar num-lanes = <4>; 2617ec142c44SVidya Sagar num-viewport = <8>; 2618ec142c44SVidya Sagar linux,pci-domain = <4>; 2619ec142c44SVidya Sagar 2620ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX0_C4_CORE>; 2621ec142c44SVidya Sagar clock-names = "core"; 2622ec142c44SVidya Sagar 2623ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX0_CORE_4_APB>, 2624ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX0_CORE_4>; 2625ec142c44SVidya Sagar reset-names = "apb", "core"; 2626ec142c44SVidya Sagar 2627ec142c44SVidya Sagar interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2628ec142c44SVidya Sagar <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2629ec142c44SVidya Sagar interrupt-names = "intr", "msi"; 2630ec142c44SVidya Sagar 2631ec142c44SVidya Sagar #interrupt-cells = <1>; 2632ec142c44SVidya Sagar interrupt-map-mask = <0 0 0 0>; 2633ec142c44SVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 2634ec142c44SVidya Sagar 2635ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 4>; 2636ec142c44SVidya Sagar 2637ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2638ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2639ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2640ec142c44SVidya Sagar 2641ec142c44SVidya Sagar bus-range = <0x0 0xff>; 2642ec142c44SVidya Sagar 2643ec142c44SVidya Sagar ranges = <0x43000000 0x21 0x40000000 0x21 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2644ec142c44SVidya Sagar <0x02000000 0x0 0x40000000 0x24 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2645ec142c44SVidya Sagar <0x01000000 0x0 0x36100000 0x00 0x36100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2646ec142c44SVidya Sagar 2647ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE4R &emc>, 2648ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE4W &emc>; 2649ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2650ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE4 0x1000>; 2651ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2652ec142c44SVidya Sagar dma-coherent; 2653ec142c44SVidya Sagar 2654ec142c44SVidya Sagar status = "disabled"; 2655ec142c44SVidya Sagar }; 2656ec142c44SVidya Sagar 2657ec142c44SVidya Sagar pcie@14180000 { 2658ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie"; 2659ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BA>; 2660ec142c44SVidya Sagar reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2661ec142c44SVidya Sagar <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ 2662ec142c44SVidya Sagar <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2663794b834dSVidya Sagar <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2664794b834dSVidya Sagar <0x27 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2665794b834dSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2666ec142c44SVidya Sagar 2667ec142c44SVidya Sagar #address-cells = <3>; 2668ec142c44SVidya Sagar #size-cells = <2>; 2669ec142c44SVidya Sagar device_type = "pci"; 2670ec142c44SVidya Sagar num-lanes = <4>; 2671ec142c44SVidya Sagar num-viewport = <8>; 2672ec142c44SVidya Sagar linux,pci-domain = <0>; 2673ec142c44SVidya Sagar 2674ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX0_C0_CORE>; 2675ec142c44SVidya Sagar clock-names = "core"; 2676ec142c44SVidya Sagar 2677ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX0_CORE_0_APB>, 2678ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX0_CORE_0>; 2679ec142c44SVidya Sagar reset-names = "apb", "core"; 2680ec142c44SVidya Sagar 2681ec142c44SVidya Sagar interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2682ec142c44SVidya Sagar <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2683ec142c44SVidya Sagar interrupt-names = "intr", "msi"; 2684ec142c44SVidya Sagar 2685ec142c44SVidya Sagar #interrupt-cells = <1>; 2686ec142c44SVidya Sagar interrupt-map-mask = <0 0 0 0>; 2687ec142c44SVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 2688ec142c44SVidya Sagar 2689ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 0>; 2690ec142c44SVidya Sagar 2691ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2692ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2693ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2694ec142c44SVidya Sagar 2695ec142c44SVidya Sagar bus-range = <0x0 0xff>; 2696ec142c44SVidya Sagar 2697ec142c44SVidya Sagar ranges = <0x43000000 0x24 0x40000000 0x24 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2698ec142c44SVidya Sagar <0x02000000 0x0 0x40000000 0x27 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2699ec142c44SVidya Sagar <0x01000000 0x0 0x38100000 0x00 0x38100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2700ec142c44SVidya Sagar 2701ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE0R &emc>, 2702ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE0W &emc>; 2703ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2704ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE0 0x1000>; 2705ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2706ec142c44SVidya Sagar dma-coherent; 2707ec142c44SVidya Sagar 2708ec142c44SVidya Sagar status = "disabled"; 2709ec142c44SVidya Sagar }; 2710ec142c44SVidya Sagar 2711ec142c44SVidya Sagar pcie@141a0000 { 2712ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie"; 2713ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>; 2714ec142c44SVidya Sagar reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2715ec142c44SVidya Sagar <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */ 2716ec142c44SVidya Sagar <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2717794b834dSVidya Sagar <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2718794b834dSVidya Sagar <0x2b 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2719794b834dSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2720ec142c44SVidya Sagar 2721ec142c44SVidya Sagar #address-cells = <3>; 2722ec142c44SVidya Sagar #size-cells = <2>; 2723ec142c44SVidya Sagar device_type = "pci"; 2724ec142c44SVidya Sagar num-lanes = <8>; 2725ec142c44SVidya Sagar num-viewport = <8>; 2726ec142c44SVidya Sagar linux,pci-domain = <5>; 2727ec142c44SVidya Sagar 2728ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>; 2729ec142c44SVidya Sagar clock-names = "core"; 2730ec142c44SVidya Sagar 2731ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>, 2732ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX1_CORE_5>; 2733ec142c44SVidya Sagar reset-names = "apb", "core"; 2734ec142c44SVidya Sagar 2735ec142c44SVidya Sagar interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2736ec142c44SVidya Sagar <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2737ec142c44SVidya Sagar interrupt-names = "intr", "msi"; 2738ec142c44SVidya Sagar 2739ec142c44SVidya Sagar #interrupt-cells = <1>; 2740ec142c44SVidya Sagar interrupt-map-mask = <0 0 0 0>; 2741ec142c44SVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 2742ec142c44SVidya Sagar 2743ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 5>; 2744ec142c44SVidya Sagar 2745ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2746ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2747ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2748ec142c44SVidya Sagar 2749ec142c44SVidya Sagar bus-range = <0x0 0xff>; 2750ec142c44SVidya Sagar 275124840065SVidya Sagar ranges = <0x43000000 0x28 0x00000000 0x28 0x00000000 0x3 0x28000000>, /* prefetchable memory (12928 MB) */ 2752ec142c44SVidya Sagar <0x02000000 0x0 0x40000000 0x2b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2753ec142c44SVidya Sagar <0x01000000 0x0 0x3a100000 0x00 0x3a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2754ec142c44SVidya Sagar 2755ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE5R &emc>, 2756ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE5W &emc>; 2757ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2758ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>; 2759ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2760ec142c44SVidya Sagar dma-coherent; 2761ec142c44SVidya Sagar 2762ec142c44SVidya Sagar status = "disabled"; 2763ec142c44SVidya Sagar }; 2764ec142c44SVidya Sagar 27652838cfddSThierry Reding pcie-ep@141a0000 { 27662838cfddSThierry Reding compatible = "nvidia,tegra234-pcie-ep"; 27672838cfddSThierry Reding power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>; 27682838cfddSThierry Reding reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 27692838cfddSThierry Reding <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 27702838cfddSThierry Reding <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 27712838cfddSThierry Reding <0x27 0x40000000 0x4 0x00000000>; /* Address Space (16G) */ 27722838cfddSThierry Reding reg-names = "appl", "atu_dma", "dbi", "addr_space"; 27732838cfddSThierry Reding 27742838cfddSThierry Reding num-lanes = <8>; 27752838cfddSThierry Reding 27762838cfddSThierry Reding clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>; 27772838cfddSThierry Reding clock-names = "core"; 27782838cfddSThierry Reding 27792838cfddSThierry Reding resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>, 27802838cfddSThierry Reding <&bpmp TEGRA234_RESET_PEX1_CORE_5>; 27812838cfddSThierry Reding reset-names = "apb", "core"; 27822838cfddSThierry Reding 27832838cfddSThierry Reding interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 27842838cfddSThierry Reding interrupt-names = "intr"; 27852838cfddSThierry Reding 27862838cfddSThierry Reding nvidia,bpmp = <&bpmp 5>; 27872838cfddSThierry Reding 27882838cfddSThierry Reding nvidia,enable-ext-refclk; 27892838cfddSThierry Reding nvidia,aspm-cmrt-us = <60>; 27902838cfddSThierry Reding nvidia,aspm-pwr-on-t-us = <20>; 27912838cfddSThierry Reding nvidia,aspm-l0s-entrance-latency-us = <3>; 27922838cfddSThierry Reding 27932838cfddSThierry Reding interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE5R &emc>, 27942838cfddSThierry Reding <&mc TEGRA234_MEMORY_CLIENT_PCIE5W &emc>; 27952838cfddSThierry Reding interconnect-names = "dma-mem", "write"; 27962838cfddSThierry Reding iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>; 27972838cfddSThierry Reding iommu-map-mask = <0x0>; 27982838cfddSThierry Reding dma-coherent; 27992838cfddSThierry Reding 28002838cfddSThierry Reding status = "disabled"; 28012838cfddSThierry Reding }; 28022838cfddSThierry Reding 2803ec142c44SVidya Sagar pcie@141c0000 { 2804ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie"; 2805ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4A>; 2806ec142c44SVidya Sagar reg = <0x00 0x141c0000 0x0 0x00020000>, /* appl registers (128K) */ 2807ec142c44SVidya Sagar <0x00 0x3c000000 0x0 0x00040000>, /* configuration space (256K) */ 2808ec142c44SVidya Sagar <0x00 0x3c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2809794b834dSVidya Sagar <0x00 0x3c080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2810794b834dSVidya Sagar <0x2e 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2811794b834dSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2812ec142c44SVidya Sagar 2813ec142c44SVidya Sagar #address-cells = <3>; 2814ec142c44SVidya Sagar #size-cells = <2>; 2815ec142c44SVidya Sagar device_type = "pci"; 2816ec142c44SVidya Sagar num-lanes = <4>; 2817ec142c44SVidya Sagar num-viewport = <8>; 2818ec142c44SVidya Sagar linux,pci-domain = <6>; 2819ec142c44SVidya Sagar 2820ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX1_C6_CORE>; 2821ec142c44SVidya Sagar clock-names = "core"; 2822ec142c44SVidya Sagar 2823ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX1_CORE_6_APB>, 2824ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX1_CORE_6>; 2825ec142c44SVidya Sagar reset-names = "apb", "core"; 2826ec142c44SVidya Sagar 2827ec142c44SVidya Sagar interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2828ec142c44SVidya Sagar <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2829ec142c44SVidya Sagar interrupt-names = "intr", "msi"; 2830ec142c44SVidya Sagar 2831ec142c44SVidya Sagar #interrupt-cells = <1>; 2832ec142c44SVidya Sagar interrupt-map-mask = <0 0 0 0>; 2833ec142c44SVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 2834ec142c44SVidya Sagar 2835ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 6>; 2836ec142c44SVidya Sagar 2837ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2838ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2839ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2840ec142c44SVidya Sagar 2841ec142c44SVidya Sagar bus-range = <0x0 0xff>; 2842ec142c44SVidya Sagar 2843ec142c44SVidya Sagar ranges = <0x43000000 0x2b 0x40000000 0x2b 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2844ec142c44SVidya Sagar <0x02000000 0x0 0x40000000 0x2e 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2845ec142c44SVidya Sagar <0x01000000 0x0 0x3c100000 0x00 0x3c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2846ec142c44SVidya Sagar 2847ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE6AR &emc>, 2848ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE6AW &emc>; 2849ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2850ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>; 2851ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2852ec142c44SVidya Sagar dma-coherent; 2853ec142c44SVidya Sagar 2854ec142c44SVidya Sagar status = "disabled"; 2855ec142c44SVidya Sagar }; 2856ec142c44SVidya Sagar 28572838cfddSThierry Reding pcie-ep@141c0000 { 28582838cfddSThierry Reding compatible = "nvidia,tegra234-pcie-ep"; 28592838cfddSThierry Reding power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4A>; 28602838cfddSThierry Reding reg = <0x00 0x141c0000 0x0 0x00020000>, /* appl registers (128K) */ 28612838cfddSThierry Reding <0x00 0x3c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 28622838cfddSThierry Reding <0x00 0x3c080000 0x0 0x00040000>, /* DBI space (256K) */ 28632838cfddSThierry Reding <0x2b 0x40000000 0x3 0x00000000>; /* Address Space (12G) */ 28642838cfddSThierry Reding reg-names = "appl", "atu_dma", "dbi", "addr_space"; 28652838cfddSThierry Reding 28662838cfddSThierry Reding num-lanes = <4>; 28672838cfddSThierry Reding 28682838cfddSThierry Reding clocks = <&bpmp TEGRA234_CLK_PEX1_C6_CORE>; 28692838cfddSThierry Reding clock-names = "core"; 28702838cfddSThierry Reding 28712838cfddSThierry Reding resets = <&bpmp TEGRA234_RESET_PEX1_CORE_6_APB>, 28722838cfddSThierry Reding <&bpmp TEGRA234_RESET_PEX1_CORE_6>; 28732838cfddSThierry Reding reset-names = "apb", "core"; 28742838cfddSThierry Reding 28752838cfddSThierry Reding interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 28762838cfddSThierry Reding interrupt-names = "intr"; 28772838cfddSThierry Reding 28782838cfddSThierry Reding nvidia,bpmp = <&bpmp 6>; 28792838cfddSThierry Reding 28802838cfddSThierry Reding nvidia,enable-ext-refclk; 28812838cfddSThierry Reding nvidia,aspm-cmrt-us = <60>; 28822838cfddSThierry Reding nvidia,aspm-pwr-on-t-us = <20>; 28832838cfddSThierry Reding nvidia,aspm-l0s-entrance-latency-us = <3>; 28842838cfddSThierry Reding 28852838cfddSThierry Reding interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE6AR &emc>, 28862838cfddSThierry Reding <&mc TEGRA234_MEMORY_CLIENT_PCIE6AW &emc>; 28872838cfddSThierry Reding interconnect-names = "dma-mem", "write"; 28882838cfddSThierry Reding iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>; 28892838cfddSThierry Reding iommu-map-mask = <0x0>; 28902838cfddSThierry Reding dma-coherent; 28912838cfddSThierry Reding 28922838cfddSThierry Reding status = "disabled"; 28932838cfddSThierry Reding }; 28942838cfddSThierry Reding 2895ec142c44SVidya Sagar pcie@141e0000 { 2896ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie"; 2897ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8B>; 2898ec142c44SVidya Sagar reg = <0x00 0x141e0000 0x0 0x00020000>, /* appl registers (128K) */ 2899ec142c44SVidya Sagar <0x00 0x3e000000 0x0 0x00040000>, /* configuration space (256K) */ 2900ec142c44SVidya Sagar <0x00 0x3e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2901794b834dSVidya Sagar <0x00 0x3e080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2902794b834dSVidya Sagar <0x32 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2903794b834dSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2904ec142c44SVidya Sagar 2905ec142c44SVidya Sagar #address-cells = <3>; 2906ec142c44SVidya Sagar #size-cells = <2>; 2907ec142c44SVidya Sagar device_type = "pci"; 2908ec142c44SVidya Sagar num-lanes = <8>; 2909ec142c44SVidya Sagar num-viewport = <8>; 2910ec142c44SVidya Sagar linux,pci-domain = <7>; 2911ec142c44SVidya Sagar 2912ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX2_C7_CORE>; 2913ec142c44SVidya Sagar clock-names = "core"; 2914ec142c44SVidya Sagar 2915ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX2_CORE_7_APB>, 2916ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX2_CORE_7>; 2917ec142c44SVidya Sagar reset-names = "apb", "core"; 2918ec142c44SVidya Sagar 2919ec142c44SVidya Sagar interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2920ec142c44SVidya Sagar <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2921ec142c44SVidya Sagar interrupt-names = "intr", "msi"; 2922ec142c44SVidya Sagar 2923ec142c44SVidya Sagar #interrupt-cells = <1>; 2924ec142c44SVidya Sagar interrupt-map-mask = <0 0 0 0>; 2925ec142c44SVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 2926ec142c44SVidya Sagar 2927ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 7>; 2928ec142c44SVidya Sagar 2929ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2930ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2931ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2932ec142c44SVidya Sagar 2933ec142c44SVidya Sagar bus-range = <0x0 0xff>; 2934ec142c44SVidya Sagar 293524840065SVidya Sagar ranges = <0x43000000 0x30 0x00000000 0x30 0x00000000 0x2 0x28000000>, /* prefetchable memory (8832 MB) */ 2936ec142c44SVidya Sagar <0x02000000 0x0 0x40000000 0x32 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2937ec142c44SVidya Sagar <0x01000000 0x0 0x3e100000 0x00 0x3e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2938ec142c44SVidya Sagar 2939ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE7AR &emc>, 2940ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE7AW &emc>; 2941ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2942ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>; 2943ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2944ec142c44SVidya Sagar dma-coherent; 2945ec142c44SVidya Sagar 2946ec142c44SVidya Sagar status = "disabled"; 2947ec142c44SVidya Sagar }; 2948ec142c44SVidya Sagar 2949ec142c44SVidya Sagar pcie-ep@141e0000 { 2950ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie-ep"; 2951ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8B>; 2952ec142c44SVidya Sagar reg = <0x00 0x141e0000 0x0 0x00020000>, /* appl registers (128K) */ 2953ec142c44SVidya Sagar <0x00 0x3e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2954ec142c44SVidya Sagar <0x00 0x3e080000 0x0 0x00040000>, /* DBI space (256K) */ 2955ec142c44SVidya Sagar <0x2e 0x40000000 0x4 0x00000000>; /* Address Space (16G) */ 2956ec142c44SVidya Sagar reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2957ec142c44SVidya Sagar 2958ec142c44SVidya Sagar num-lanes = <8>; 2959ec142c44SVidya Sagar 2960ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX2_C7_CORE>; 2961ec142c44SVidya Sagar clock-names = "core"; 2962ec142c44SVidya Sagar 2963ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX2_CORE_7_APB>, 2964ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX2_CORE_7>; 2965ec142c44SVidya Sagar reset-names = "apb", "core"; 2966ec142c44SVidya Sagar 2967ec142c44SVidya Sagar interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2968ec142c44SVidya Sagar interrupt-names = "intr"; 2969ec142c44SVidya Sagar 2970ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 7>; 2971ec142c44SVidya Sagar 2972ec142c44SVidya Sagar nvidia,enable-ext-refclk; 2973ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2974ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2975ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2976ec142c44SVidya Sagar 2977ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE7AR &emc>, 2978ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE7AW &emc>; 2979ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2980ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>; 2981ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2982ec142c44SVidya Sagar dma-coherent; 2983ec142c44SVidya Sagar 2984ec142c44SVidya Sagar status = "disabled"; 2985ec142c44SVidya Sagar }; 2986ec142c44SVidya Sagar }; 2987ec142c44SVidya Sagar 29887fa30752SThierry Reding sram@40000000 { 298963944891SThierry Reding compatible = "nvidia,tegra234-sysram", "mmio-sram"; 299098094be1SMikko Perttunen reg = <0x0 0x40000000 0x0 0x80000>; 29912838cfddSThierry Reding 299263944891SThierry Reding #address-cells = <1>; 299363944891SThierry Reding #size-cells = <1>; 299498094be1SMikko Perttunen ranges = <0x0 0x0 0x40000000 0x80000>; 29952838cfddSThierry Reding 299661192a9dSMikko Perttunen no-memory-wc; 299763944891SThierry Reding 299898094be1SMikko Perttunen cpu_bpmp_tx: sram@70000 { 299998094be1SMikko Perttunen reg = <0x70000 0x1000>; 300063944891SThierry Reding label = "cpu-bpmp-tx"; 300163944891SThierry Reding pool; 300263944891SThierry Reding }; 300363944891SThierry Reding 300498094be1SMikko Perttunen cpu_bpmp_rx: sram@71000 { 300598094be1SMikko Perttunen reg = <0x71000 0x1000>; 300663944891SThierry Reding label = "cpu-bpmp-rx"; 300763944891SThierry Reding pool; 300863944891SThierry Reding }; 300963944891SThierry Reding }; 301063944891SThierry Reding 301163944891SThierry Reding bpmp: bpmp { 301263944891SThierry Reding compatible = "nvidia,tegra234-bpmp", "nvidia,tegra186-bpmp"; 301363944891SThierry Reding mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 301463944891SThierry Reding TEGRA_HSP_DB_MASTER_BPMP>; 30157fa30752SThierry Reding shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; 301663944891SThierry Reding #clock-cells = <1>; 301763944891SThierry Reding #reset-cells = <1>; 301863944891SThierry Reding #power-domain-cells = <1>; 30196de481e5SThierry Reding interconnects = <&mc TEGRA234_MEMORY_CLIENT_BPMPR &emc>, 30206de481e5SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_BPMPW &emc>, 30216de481e5SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAR &emc>, 30226de481e5SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAW &emc>; 30236de481e5SThierry Reding interconnect-names = "read", "write", "dma-mem", "dma-write"; 30245710e16aSThierry Reding iommus = <&smmu_niso1 TEGRA234_SID_BPMP>; 302563944891SThierry Reding 302663944891SThierry Reding bpmp_i2c: i2c { 302763944891SThierry Reding compatible = "nvidia,tegra186-bpmp-i2c"; 302863944891SThierry Reding nvidia,bpmp-bus-id = <5>; 302963944891SThierry Reding #address-cells = <1>; 303063944891SThierry Reding #size-cells = <0>; 303163944891SThierry Reding }; 303209d99078SThierry Reding 303309d99078SThierry Reding bpmp_thermal: thermal { 303409d99078SThierry Reding compatible = "nvidia,tegra186-bpmp-thermal"; 303509d99078SThierry Reding #thermal-sensor-cells = <1>; 303609d99078SThierry Reding }; 303763944891SThierry Reding }; 303863944891SThierry Reding 303963944891SThierry Reding cpus { 304063944891SThierry Reding #address-cells = <1>; 304163944891SThierry Reding #size-cells = <0>; 304263944891SThierry Reding 3043a12cf5c3SThierry Reding cpu0_0: cpu@0 { 3044a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 304563944891SThierry Reding device_type = "cpu"; 3046a12cf5c3SThierry Reding reg = <0x00000>; 304763944891SThierry Reding 304863944891SThierry Reding enable-method = "psci"; 3049a12cf5c3SThierry Reding 30501582e1d1SSumit Gupta operating-points-v2 = <&cl0_opp_tbl>; 30511582e1d1SSumit Gupta interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER0 &emc>; 30521582e1d1SSumit Gupta 3053a12cf5c3SThierry Reding i-cache-size = <65536>; 3054a12cf5c3SThierry Reding i-cache-line-size = <64>; 3055a12cf5c3SThierry Reding i-cache-sets = <256>; 3056a12cf5c3SThierry Reding d-cache-size = <65536>; 3057a12cf5c3SThierry Reding d-cache-line-size = <64>; 3058a12cf5c3SThierry Reding d-cache-sets = <256>; 3059a12cf5c3SThierry Reding next-level-cache = <&l2c0_0>; 306063944891SThierry Reding }; 3061a12cf5c3SThierry Reding 3062a12cf5c3SThierry Reding cpu0_1: cpu@100 { 3063a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 3064a12cf5c3SThierry Reding device_type = "cpu"; 3065a12cf5c3SThierry Reding reg = <0x00100>; 3066a12cf5c3SThierry Reding 3067a12cf5c3SThierry Reding enable-method = "psci"; 3068a12cf5c3SThierry Reding 30691582e1d1SSumit Gupta operating-points-v2 = <&cl0_opp_tbl>; 30701582e1d1SSumit Gupta interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER0 &emc>; 30711582e1d1SSumit Gupta 3072a12cf5c3SThierry Reding i-cache-size = <65536>; 3073a12cf5c3SThierry Reding i-cache-line-size = <64>; 3074a12cf5c3SThierry Reding i-cache-sets = <256>; 3075a12cf5c3SThierry Reding d-cache-size = <65536>; 3076a12cf5c3SThierry Reding d-cache-line-size = <64>; 3077a12cf5c3SThierry Reding d-cache-sets = <256>; 3078a12cf5c3SThierry Reding next-level-cache = <&l2c0_1>; 3079a12cf5c3SThierry Reding }; 3080a12cf5c3SThierry Reding 3081a12cf5c3SThierry Reding cpu0_2: cpu@200 { 3082a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 3083a12cf5c3SThierry Reding device_type = "cpu"; 3084a12cf5c3SThierry Reding reg = <0x00200>; 3085a12cf5c3SThierry Reding 3086a12cf5c3SThierry Reding enable-method = "psci"; 3087a12cf5c3SThierry Reding 30881582e1d1SSumit Gupta operating-points-v2 = <&cl0_opp_tbl>; 30891582e1d1SSumit Gupta interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER0 &emc>; 30901582e1d1SSumit Gupta 3091a12cf5c3SThierry Reding i-cache-size = <65536>; 3092a12cf5c3SThierry Reding i-cache-line-size = <64>; 3093a12cf5c3SThierry Reding i-cache-sets = <256>; 3094a12cf5c3SThierry Reding d-cache-size = <65536>; 3095a12cf5c3SThierry Reding d-cache-line-size = <64>; 3096a12cf5c3SThierry Reding d-cache-sets = <256>; 3097a12cf5c3SThierry Reding next-level-cache = <&l2c0_2>; 3098a12cf5c3SThierry Reding }; 3099a12cf5c3SThierry Reding 3100a12cf5c3SThierry Reding cpu0_3: cpu@300 { 3101a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 3102a12cf5c3SThierry Reding device_type = "cpu"; 3103a12cf5c3SThierry Reding reg = <0x00300>; 3104a12cf5c3SThierry Reding 3105a12cf5c3SThierry Reding enable-method = "psci"; 3106a12cf5c3SThierry Reding 31071582e1d1SSumit Gupta operating-points-v2 = <&cl0_opp_tbl>; 31081582e1d1SSumit Gupta interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER0 &emc>; 31091582e1d1SSumit Gupta 3110a12cf5c3SThierry Reding i-cache-size = <65536>; 3111a12cf5c3SThierry Reding i-cache-line-size = <64>; 3112a12cf5c3SThierry Reding i-cache-sets = <256>; 3113a12cf5c3SThierry Reding d-cache-size = <65536>; 3114a12cf5c3SThierry Reding d-cache-line-size = <64>; 3115a12cf5c3SThierry Reding d-cache-sets = <256>; 3116a12cf5c3SThierry Reding next-level-cache = <&l2c0_3>; 3117a12cf5c3SThierry Reding }; 3118a12cf5c3SThierry Reding 3119a12cf5c3SThierry Reding cpu1_0: cpu@10000 { 3120a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 3121a12cf5c3SThierry Reding device_type = "cpu"; 3122a12cf5c3SThierry Reding reg = <0x10000>; 3123a12cf5c3SThierry Reding 3124a12cf5c3SThierry Reding enable-method = "psci"; 3125a12cf5c3SThierry Reding 31261582e1d1SSumit Gupta operating-points-v2 = <&cl1_opp_tbl>; 31271582e1d1SSumit Gupta interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER1 &emc>; 31281582e1d1SSumit Gupta 3129a12cf5c3SThierry Reding i-cache-size = <65536>; 3130a12cf5c3SThierry Reding i-cache-line-size = <64>; 3131a12cf5c3SThierry Reding i-cache-sets = <256>; 3132a12cf5c3SThierry Reding d-cache-size = <65536>; 3133a12cf5c3SThierry Reding d-cache-line-size = <64>; 3134a12cf5c3SThierry Reding d-cache-sets = <256>; 3135a12cf5c3SThierry Reding next-level-cache = <&l2c1_0>; 3136a12cf5c3SThierry Reding }; 3137a12cf5c3SThierry Reding 3138a12cf5c3SThierry Reding cpu1_1: cpu@10100 { 3139a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 3140a12cf5c3SThierry Reding device_type = "cpu"; 3141a12cf5c3SThierry Reding reg = <0x10100>; 3142a12cf5c3SThierry Reding 3143a12cf5c3SThierry Reding enable-method = "psci"; 3144a12cf5c3SThierry Reding 31451582e1d1SSumit Gupta operating-points-v2 = <&cl1_opp_tbl>; 31461582e1d1SSumit Gupta interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER1 &emc>; 31471582e1d1SSumit Gupta 3148a12cf5c3SThierry Reding i-cache-size = <65536>; 3149a12cf5c3SThierry Reding i-cache-line-size = <64>; 3150a12cf5c3SThierry Reding i-cache-sets = <256>; 3151a12cf5c3SThierry Reding d-cache-size = <65536>; 3152a12cf5c3SThierry Reding d-cache-line-size = <64>; 3153a12cf5c3SThierry Reding d-cache-sets = <256>; 3154a12cf5c3SThierry Reding next-level-cache = <&l2c1_1>; 3155a12cf5c3SThierry Reding }; 3156a12cf5c3SThierry Reding 3157a12cf5c3SThierry Reding cpu1_2: cpu@10200 { 3158a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 3159a12cf5c3SThierry Reding device_type = "cpu"; 3160a12cf5c3SThierry Reding reg = <0x10200>; 3161a12cf5c3SThierry Reding 3162a12cf5c3SThierry Reding enable-method = "psci"; 3163a12cf5c3SThierry Reding 31641582e1d1SSumit Gupta operating-points-v2 = <&cl1_opp_tbl>; 31651582e1d1SSumit Gupta interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER1 &emc>; 31661582e1d1SSumit Gupta 3167a12cf5c3SThierry Reding i-cache-size = <65536>; 3168a12cf5c3SThierry Reding i-cache-line-size = <64>; 3169a12cf5c3SThierry Reding i-cache-sets = <256>; 3170a12cf5c3SThierry Reding d-cache-size = <65536>; 3171a12cf5c3SThierry Reding d-cache-line-size = <64>; 3172a12cf5c3SThierry Reding d-cache-sets = <256>; 3173a12cf5c3SThierry Reding next-level-cache = <&l2c1_2>; 3174a12cf5c3SThierry Reding }; 3175a12cf5c3SThierry Reding 3176a12cf5c3SThierry Reding cpu1_3: cpu@10300 { 3177a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 3178a12cf5c3SThierry Reding device_type = "cpu"; 3179a12cf5c3SThierry Reding reg = <0x10300>; 3180a12cf5c3SThierry Reding 3181a12cf5c3SThierry Reding enable-method = "psci"; 3182a12cf5c3SThierry Reding 31831582e1d1SSumit Gupta operating-points-v2 = <&cl1_opp_tbl>; 31841582e1d1SSumit Gupta interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER1 &emc>; 31851582e1d1SSumit Gupta 3186a12cf5c3SThierry Reding i-cache-size = <65536>; 3187a12cf5c3SThierry Reding i-cache-line-size = <64>; 3188a12cf5c3SThierry Reding i-cache-sets = <256>; 3189a12cf5c3SThierry Reding d-cache-size = <65536>; 3190a12cf5c3SThierry Reding d-cache-line-size = <64>; 3191a12cf5c3SThierry Reding d-cache-sets = <256>; 3192a12cf5c3SThierry Reding next-level-cache = <&l2c1_3>; 3193a12cf5c3SThierry Reding }; 3194a12cf5c3SThierry Reding 3195a12cf5c3SThierry Reding cpu2_0: cpu@20000 { 3196a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 3197a12cf5c3SThierry Reding device_type = "cpu"; 3198a12cf5c3SThierry Reding reg = <0x20000>; 3199a12cf5c3SThierry Reding 3200a12cf5c3SThierry Reding enable-method = "psci"; 3201a12cf5c3SThierry Reding 32021582e1d1SSumit Gupta operating-points-v2 = <&cl2_opp_tbl>; 32031582e1d1SSumit Gupta interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER2 &emc>; 32041582e1d1SSumit Gupta 3205a12cf5c3SThierry Reding i-cache-size = <65536>; 3206a12cf5c3SThierry Reding i-cache-line-size = <64>; 3207a12cf5c3SThierry Reding i-cache-sets = <256>; 3208a12cf5c3SThierry Reding d-cache-size = <65536>; 3209a12cf5c3SThierry Reding d-cache-line-size = <64>; 3210a12cf5c3SThierry Reding d-cache-sets = <256>; 3211a12cf5c3SThierry Reding next-level-cache = <&l2c2_0>; 3212a12cf5c3SThierry Reding }; 3213a12cf5c3SThierry Reding 3214a12cf5c3SThierry Reding cpu2_1: cpu@20100 { 3215a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 3216a12cf5c3SThierry Reding device_type = "cpu"; 3217a12cf5c3SThierry Reding reg = <0x20100>; 3218a12cf5c3SThierry Reding 3219a12cf5c3SThierry Reding enable-method = "psci"; 3220a12cf5c3SThierry Reding 32211582e1d1SSumit Gupta operating-points-v2 = <&cl2_opp_tbl>; 32221582e1d1SSumit Gupta interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER2 &emc>; 32231582e1d1SSumit Gupta 3224a12cf5c3SThierry Reding i-cache-size = <65536>; 3225a12cf5c3SThierry Reding i-cache-line-size = <64>; 3226a12cf5c3SThierry Reding i-cache-sets = <256>; 3227a12cf5c3SThierry Reding d-cache-size = <65536>; 3228a12cf5c3SThierry Reding d-cache-line-size = <64>; 3229a12cf5c3SThierry Reding d-cache-sets = <256>; 3230a12cf5c3SThierry Reding next-level-cache = <&l2c2_1>; 3231a12cf5c3SThierry Reding }; 3232a12cf5c3SThierry Reding 3233a12cf5c3SThierry Reding cpu2_2: cpu@20200 { 3234a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 3235a12cf5c3SThierry Reding device_type = "cpu"; 3236a12cf5c3SThierry Reding reg = <0x20200>; 3237a12cf5c3SThierry Reding 3238a12cf5c3SThierry Reding enable-method = "psci"; 3239a12cf5c3SThierry Reding 32401582e1d1SSumit Gupta operating-points-v2 = <&cl2_opp_tbl>; 32411582e1d1SSumit Gupta interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER2 &emc>; 32421582e1d1SSumit Gupta 3243a12cf5c3SThierry Reding i-cache-size = <65536>; 3244a12cf5c3SThierry Reding i-cache-line-size = <64>; 3245a12cf5c3SThierry Reding i-cache-sets = <256>; 3246a12cf5c3SThierry Reding d-cache-size = <65536>; 3247a12cf5c3SThierry Reding d-cache-line-size = <64>; 3248a12cf5c3SThierry Reding d-cache-sets = <256>; 3249a12cf5c3SThierry Reding next-level-cache = <&l2c2_2>; 3250a12cf5c3SThierry Reding }; 3251a12cf5c3SThierry Reding 3252a12cf5c3SThierry Reding cpu2_3: cpu@20300 { 3253a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 3254a12cf5c3SThierry Reding device_type = "cpu"; 3255a12cf5c3SThierry Reding reg = <0x20300>; 3256a12cf5c3SThierry Reding 3257a12cf5c3SThierry Reding enable-method = "psci"; 3258a12cf5c3SThierry Reding 32591582e1d1SSumit Gupta operating-points-v2 = <&cl2_opp_tbl>; 32601582e1d1SSumit Gupta interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER2 &emc>; 32611582e1d1SSumit Gupta 3262a12cf5c3SThierry Reding i-cache-size = <65536>; 3263a12cf5c3SThierry Reding i-cache-line-size = <64>; 3264a12cf5c3SThierry Reding i-cache-sets = <256>; 3265a12cf5c3SThierry Reding d-cache-size = <65536>; 3266a12cf5c3SThierry Reding d-cache-line-size = <64>; 3267a12cf5c3SThierry Reding d-cache-sets = <256>; 3268a12cf5c3SThierry Reding next-level-cache = <&l2c2_3>; 3269a12cf5c3SThierry Reding }; 3270a12cf5c3SThierry Reding 3271a12cf5c3SThierry Reding cpu-map { 3272a12cf5c3SThierry Reding cluster0 { 3273a12cf5c3SThierry Reding core0 { 3274a12cf5c3SThierry Reding cpu = <&cpu0_0>; 3275a12cf5c3SThierry Reding }; 3276a12cf5c3SThierry Reding 3277a12cf5c3SThierry Reding core1 { 3278a12cf5c3SThierry Reding cpu = <&cpu0_1>; 3279a12cf5c3SThierry Reding }; 3280a12cf5c3SThierry Reding 3281a12cf5c3SThierry Reding core2 { 3282a12cf5c3SThierry Reding cpu = <&cpu0_2>; 3283a12cf5c3SThierry Reding }; 3284a12cf5c3SThierry Reding 3285a12cf5c3SThierry Reding core3 { 3286a12cf5c3SThierry Reding cpu = <&cpu0_3>; 3287a12cf5c3SThierry Reding }; 3288a12cf5c3SThierry Reding }; 3289a12cf5c3SThierry Reding 3290a12cf5c3SThierry Reding cluster1 { 3291a12cf5c3SThierry Reding core0 { 3292a12cf5c3SThierry Reding cpu = <&cpu1_0>; 3293a12cf5c3SThierry Reding }; 3294a12cf5c3SThierry Reding 3295a12cf5c3SThierry Reding core1 { 3296a12cf5c3SThierry Reding cpu = <&cpu1_1>; 3297a12cf5c3SThierry Reding }; 3298a12cf5c3SThierry Reding 3299a12cf5c3SThierry Reding core2 { 3300a12cf5c3SThierry Reding cpu = <&cpu1_2>; 3301a12cf5c3SThierry Reding }; 3302a12cf5c3SThierry Reding 3303a12cf5c3SThierry Reding core3 { 3304a12cf5c3SThierry Reding cpu = <&cpu1_3>; 3305a12cf5c3SThierry Reding }; 3306a12cf5c3SThierry Reding }; 3307a12cf5c3SThierry Reding 3308a12cf5c3SThierry Reding cluster2 { 3309a12cf5c3SThierry Reding core0 { 3310a12cf5c3SThierry Reding cpu = <&cpu2_0>; 3311a12cf5c3SThierry Reding }; 3312a12cf5c3SThierry Reding 3313a12cf5c3SThierry Reding core1 { 3314a12cf5c3SThierry Reding cpu = <&cpu2_1>; 3315a12cf5c3SThierry Reding }; 3316a12cf5c3SThierry Reding 3317a12cf5c3SThierry Reding core2 { 3318a12cf5c3SThierry Reding cpu = <&cpu2_2>; 3319a12cf5c3SThierry Reding }; 3320a12cf5c3SThierry Reding 3321a12cf5c3SThierry Reding core3 { 3322a12cf5c3SThierry Reding cpu = <&cpu2_3>; 3323a12cf5c3SThierry Reding }; 3324a12cf5c3SThierry Reding }; 3325a12cf5c3SThierry Reding }; 3326a12cf5c3SThierry Reding 3327a12cf5c3SThierry Reding l2c0_0: l2-cache00 { 332827f1568bSPierre Gondois compatible = "cache"; 3329a12cf5c3SThierry Reding cache-size = <262144>; 3330a12cf5c3SThierry Reding cache-line-size = <64>; 3331a12cf5c3SThierry Reding cache-sets = <512>; 3332a12cf5c3SThierry Reding cache-unified; 333327f1568bSPierre Gondois cache-level = <2>; 3334a12cf5c3SThierry Reding next-level-cache = <&l3c0>; 3335a12cf5c3SThierry Reding }; 3336a12cf5c3SThierry Reding 3337a12cf5c3SThierry Reding l2c0_1: l2-cache01 { 333827f1568bSPierre Gondois compatible = "cache"; 3339a12cf5c3SThierry Reding cache-size = <262144>; 3340a12cf5c3SThierry Reding cache-line-size = <64>; 3341a12cf5c3SThierry Reding cache-sets = <512>; 3342a12cf5c3SThierry Reding cache-unified; 334327f1568bSPierre Gondois cache-level = <2>; 3344a12cf5c3SThierry Reding next-level-cache = <&l3c0>; 3345a12cf5c3SThierry Reding }; 3346a12cf5c3SThierry Reding 3347a12cf5c3SThierry Reding l2c0_2: l2-cache02 { 334827f1568bSPierre Gondois compatible = "cache"; 3349a12cf5c3SThierry Reding cache-size = <262144>; 3350a12cf5c3SThierry Reding cache-line-size = <64>; 3351a12cf5c3SThierry Reding cache-sets = <512>; 3352a12cf5c3SThierry Reding cache-unified; 335327f1568bSPierre Gondois cache-level = <2>; 3354a12cf5c3SThierry Reding next-level-cache = <&l3c0>; 3355a12cf5c3SThierry Reding }; 3356a12cf5c3SThierry Reding 3357a12cf5c3SThierry Reding l2c0_3: l2-cache03 { 335827f1568bSPierre Gondois compatible = "cache"; 3359a12cf5c3SThierry Reding cache-size = <262144>; 3360a12cf5c3SThierry Reding cache-line-size = <64>; 3361a12cf5c3SThierry Reding cache-sets = <512>; 3362a12cf5c3SThierry Reding cache-unified; 336327f1568bSPierre Gondois cache-level = <2>; 3364a12cf5c3SThierry Reding next-level-cache = <&l3c0>; 3365a12cf5c3SThierry Reding }; 3366a12cf5c3SThierry Reding 3367a12cf5c3SThierry Reding l2c1_0: l2-cache10 { 336827f1568bSPierre Gondois compatible = "cache"; 3369a12cf5c3SThierry Reding cache-size = <262144>; 3370a12cf5c3SThierry Reding cache-line-size = <64>; 3371a12cf5c3SThierry Reding cache-sets = <512>; 3372a12cf5c3SThierry Reding cache-unified; 337327f1568bSPierre Gondois cache-level = <2>; 3374a12cf5c3SThierry Reding next-level-cache = <&l3c1>; 3375a12cf5c3SThierry Reding }; 3376a12cf5c3SThierry Reding 3377a12cf5c3SThierry Reding l2c1_1: l2-cache11 { 337827f1568bSPierre Gondois compatible = "cache"; 3379a12cf5c3SThierry Reding cache-size = <262144>; 3380a12cf5c3SThierry Reding cache-line-size = <64>; 3381a12cf5c3SThierry Reding cache-sets = <512>; 3382a12cf5c3SThierry Reding cache-unified; 338327f1568bSPierre Gondois cache-level = <2>; 3384a12cf5c3SThierry Reding next-level-cache = <&l3c1>; 3385a12cf5c3SThierry Reding }; 3386a12cf5c3SThierry Reding 3387a12cf5c3SThierry Reding l2c1_2: l2-cache12 { 338827f1568bSPierre Gondois compatible = "cache"; 3389a12cf5c3SThierry Reding cache-size = <262144>; 3390a12cf5c3SThierry Reding cache-line-size = <64>; 3391a12cf5c3SThierry Reding cache-sets = <512>; 3392a12cf5c3SThierry Reding cache-unified; 339327f1568bSPierre Gondois cache-level = <2>; 3394a12cf5c3SThierry Reding next-level-cache = <&l3c1>; 3395a12cf5c3SThierry Reding }; 3396a12cf5c3SThierry Reding 3397a12cf5c3SThierry Reding l2c1_3: l2-cache13 { 339827f1568bSPierre Gondois compatible = "cache"; 3399a12cf5c3SThierry Reding cache-size = <262144>; 3400a12cf5c3SThierry Reding cache-line-size = <64>; 3401a12cf5c3SThierry Reding cache-sets = <512>; 3402a12cf5c3SThierry Reding cache-unified; 340327f1568bSPierre Gondois cache-level = <2>; 3404a12cf5c3SThierry Reding next-level-cache = <&l3c1>; 3405a12cf5c3SThierry Reding }; 3406a12cf5c3SThierry Reding 3407a12cf5c3SThierry Reding l2c2_0: l2-cache20 { 340827f1568bSPierre Gondois compatible = "cache"; 3409a12cf5c3SThierry Reding cache-size = <262144>; 3410a12cf5c3SThierry Reding cache-line-size = <64>; 3411a12cf5c3SThierry Reding cache-sets = <512>; 3412a12cf5c3SThierry Reding cache-unified; 341327f1568bSPierre Gondois cache-level = <2>; 3414a12cf5c3SThierry Reding next-level-cache = <&l3c2>; 3415a12cf5c3SThierry Reding }; 3416a12cf5c3SThierry Reding 3417a12cf5c3SThierry Reding l2c2_1: l2-cache21 { 341827f1568bSPierre Gondois compatible = "cache"; 3419a12cf5c3SThierry Reding cache-size = <262144>; 3420a12cf5c3SThierry Reding cache-line-size = <64>; 3421a12cf5c3SThierry Reding cache-sets = <512>; 3422a12cf5c3SThierry Reding cache-unified; 342327f1568bSPierre Gondois cache-level = <2>; 3424a12cf5c3SThierry Reding next-level-cache = <&l3c2>; 3425a12cf5c3SThierry Reding }; 3426a12cf5c3SThierry Reding 3427a12cf5c3SThierry Reding l2c2_2: l2-cache22 { 342827f1568bSPierre Gondois compatible = "cache"; 3429a12cf5c3SThierry Reding cache-size = <262144>; 3430a12cf5c3SThierry Reding cache-line-size = <64>; 3431a12cf5c3SThierry Reding cache-sets = <512>; 3432a12cf5c3SThierry Reding cache-unified; 343327f1568bSPierre Gondois cache-level = <2>; 3434a12cf5c3SThierry Reding next-level-cache = <&l3c2>; 3435a12cf5c3SThierry Reding }; 3436a12cf5c3SThierry Reding 3437a12cf5c3SThierry Reding l2c2_3: l2-cache23 { 343827f1568bSPierre Gondois compatible = "cache"; 3439a12cf5c3SThierry Reding cache-size = <262144>; 3440a12cf5c3SThierry Reding cache-line-size = <64>; 3441a12cf5c3SThierry Reding cache-sets = <512>; 3442a12cf5c3SThierry Reding cache-unified; 344327f1568bSPierre Gondois cache-level = <2>; 3444a12cf5c3SThierry Reding next-level-cache = <&l3c2>; 3445a12cf5c3SThierry Reding }; 3446a12cf5c3SThierry Reding 3447a12cf5c3SThierry Reding l3c0: l3-cache0 { 344827f1568bSPierre Gondois compatible = "cache"; 344927f1568bSPierre Gondois cache-unified; 3450a12cf5c3SThierry Reding cache-size = <2097152>; 3451a12cf5c3SThierry Reding cache-line-size = <64>; 3452a12cf5c3SThierry Reding cache-sets = <2048>; 345327f1568bSPierre Gondois cache-level = <3>; 3454a12cf5c3SThierry Reding }; 3455a12cf5c3SThierry Reding 3456a12cf5c3SThierry Reding l3c1: l3-cache1 { 345727f1568bSPierre Gondois compatible = "cache"; 345827f1568bSPierre Gondois cache-unified; 3459a12cf5c3SThierry Reding cache-size = <2097152>; 3460a12cf5c3SThierry Reding cache-line-size = <64>; 3461a12cf5c3SThierry Reding cache-sets = <2048>; 346227f1568bSPierre Gondois cache-level = <3>; 3463a12cf5c3SThierry Reding }; 3464a12cf5c3SThierry Reding 3465a12cf5c3SThierry Reding l3c2: l3-cache2 { 346627f1568bSPierre Gondois compatible = "cache"; 346727f1568bSPierre Gondois cache-unified; 3468a12cf5c3SThierry Reding cache-size = <2097152>; 3469a12cf5c3SThierry Reding cache-line-size = <64>; 3470a12cf5c3SThierry Reding cache-sets = <2048>; 347127f1568bSPierre Gondois cache-level = <3>; 3472a12cf5c3SThierry Reding }; 3473a12cf5c3SThierry Reding }; 3474a12cf5c3SThierry Reding 34758e0ae0fbSJon Hunter dsu-pmu0 { 34768e0ae0fbSJon Hunter compatible = "arm,dsu-pmu"; 34778e0ae0fbSJon Hunter interrupts = <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>; 34788e0ae0fbSJon Hunter cpus = <&cpu0_0>, <&cpu0_1>, <&cpu0_2>, <&cpu0_3>; 34798e0ae0fbSJon Hunter }; 34808e0ae0fbSJon Hunter 34818e0ae0fbSJon Hunter dsu-pmu1 { 34828e0ae0fbSJon Hunter compatible = "arm,dsu-pmu"; 34838e0ae0fbSJon Hunter interrupts = <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>; 34848e0ae0fbSJon Hunter cpus = <&cpu1_0>, <&cpu1_1>, <&cpu1_2>, <&cpu1_3>; 34858e0ae0fbSJon Hunter }; 34868e0ae0fbSJon Hunter 34878e0ae0fbSJon Hunter dsu-pmu2 { 34888e0ae0fbSJon Hunter compatible = "arm,dsu-pmu"; 34898e0ae0fbSJon Hunter interrupts = <GIC_SPI 549 IRQ_TYPE_LEVEL_HIGH>; 34908e0ae0fbSJon Hunter cpus = <&cpu2_0>, <&cpu2_1>, <&cpu2_2>, <&cpu2_3>; 34918e0ae0fbSJon Hunter }; 34928e0ae0fbSJon Hunter 3493a12cf5c3SThierry Reding pmu { 3494a12cf5c3SThierry Reding compatible = "arm,cortex-a78-pmu"; 3495a12cf5c3SThierry Reding interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 3496a12cf5c3SThierry Reding status = "okay"; 349763944891SThierry Reding }; 349863944891SThierry Reding 349963944891SThierry Reding psci { 350063944891SThierry Reding compatible = "arm,psci-1.0"; 350163944891SThierry Reding status = "okay"; 350263944891SThierry Reding method = "smc"; 350363944891SThierry Reding }; 350463944891SThierry Reding 350506ad2ec4SMikko Perttunen tcu: serial { 350606ad2ec4SMikko Perttunen compatible = "nvidia,tegra234-tcu", "nvidia,tegra194-tcu"; 350706ad2ec4SMikko Perttunen mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 350806ad2ec4SMikko Perttunen <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 350906ad2ec4SMikko Perttunen mbox-names = "rx", "tx"; 351006ad2ec4SMikko Perttunen status = "disabled"; 351106ad2ec4SMikko Perttunen }; 351206ad2ec4SMikko Perttunen 351309614acdSSameer Pujar sound { 351409614acdSSameer Pujar status = "disabled"; 351509614acdSSameer Pujar 351609614acdSSameer Pujar clocks = <&bpmp TEGRA234_CLK_PLLA>, 351709614acdSSameer Pujar <&bpmp TEGRA234_CLK_PLLA_OUT0>; 351809614acdSSameer Pujar clock-names = "pll_a", "plla_out0"; 351909614acdSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_PLLA>, 352009614acdSSameer Pujar <&bpmp TEGRA234_CLK_PLLA_OUT0>, 352109614acdSSameer Pujar <&bpmp TEGRA234_CLK_AUD_MCLK>; 352209614acdSSameer Pujar assigned-clock-parents = <0>, 352309614acdSSameer Pujar <&bpmp TEGRA234_CLK_PLLA>, 352409614acdSSameer Pujar <&bpmp TEGRA234_CLK_PLLA_OUT0>; 352509614acdSSameer Pujar }; 352609614acdSSameer Pujar 352709d99078SThierry Reding thermal-zones { 352809d99078SThierry Reding cpu-thermal { 352909d99078SThierry Reding thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_CPU>; 353009d99078SThierry Reding status = "disabled"; 353109d99078SThierry Reding }; 353209d99078SThierry Reding 353309d99078SThierry Reding gpu-thermal { 353409d99078SThierry Reding thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_GPU>; 353509d99078SThierry Reding status = "disabled"; 353609d99078SThierry Reding }; 353709d99078SThierry Reding 353809d99078SThierry Reding cv0-thermal { 353909d99078SThierry Reding thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_CV0>; 354009d99078SThierry Reding status = "disabled"; 354109d99078SThierry Reding }; 354209d99078SThierry Reding 354309d99078SThierry Reding cv1-thermal { 354409d99078SThierry Reding thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_CV1>; 354509d99078SThierry Reding status = "disabled"; 354609d99078SThierry Reding }; 354709d99078SThierry Reding 354809d99078SThierry Reding cv2-thermal { 354909d99078SThierry Reding thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_CV2>; 355009d99078SThierry Reding status = "disabled"; 355109d99078SThierry Reding }; 355209d99078SThierry Reding 355309d99078SThierry Reding soc0-thermal { 355409d99078SThierry Reding thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_SOC0>; 355509d99078SThierry Reding status = "disabled"; 355609d99078SThierry Reding }; 355709d99078SThierry Reding 355809d99078SThierry Reding soc1-thermal { 355909d99078SThierry Reding thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_SOC1>; 356009d99078SThierry Reding status = "disabled"; 356109d99078SThierry Reding }; 356209d99078SThierry Reding 356309d99078SThierry Reding soc2-thermal { 356409d99078SThierry Reding thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_SOC2>; 356509d99078SThierry Reding status = "disabled"; 356609d99078SThierry Reding }; 356709d99078SThierry Reding 356809d99078SThierry Reding tj-thermal { 356909d99078SThierry Reding thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_TJ_MAX>; 357009d99078SThierry Reding status = "disabled"; 357109d99078SThierry Reding }; 357209d99078SThierry Reding }; 357309d99078SThierry Reding 357463944891SThierry Reding timer { 357563944891SThierry Reding compatible = "arm,armv8-timer"; 357663944891SThierry Reding interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 357763944891SThierry Reding <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 357863944891SThierry Reding <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 357963944891SThierry Reding <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 358063944891SThierry Reding interrupt-parent = <&gic>; 358163944891SThierry Reding always-on; 358263944891SThierry Reding }; 35831582e1d1SSumit Gupta 35841582e1d1SSumit Gupta cl0_opp_tbl: opp-table-cluster0 { 35851582e1d1SSumit Gupta compatible = "operating-points-v2"; 35861582e1d1SSumit Gupta opp-shared; 35871582e1d1SSumit Gupta 35881582e1d1SSumit Gupta cl0_ch1_opp1: opp-115200000 { 35891582e1d1SSumit Gupta opp-hz = /bits/ 64 <115200000>; 35901582e1d1SSumit Gupta opp-peak-kBps = <816000>; 35911582e1d1SSumit Gupta }; 35921582e1d1SSumit Gupta 35931582e1d1SSumit Gupta cl0_ch1_opp2: opp-268800000 { 35941582e1d1SSumit Gupta opp-hz = /bits/ 64 <268800000>; 35951582e1d1SSumit Gupta opp-peak-kBps = <816000>; 35961582e1d1SSumit Gupta }; 35971582e1d1SSumit Gupta 35981582e1d1SSumit Gupta cl0_ch1_opp3: opp-422400000 { 35991582e1d1SSumit Gupta opp-hz = /bits/ 64 <422400000>; 36001582e1d1SSumit Gupta opp-peak-kBps = <816000>; 36011582e1d1SSumit Gupta }; 36021582e1d1SSumit Gupta 36031582e1d1SSumit Gupta cl0_ch1_opp4: opp-576000000 { 36041582e1d1SSumit Gupta opp-hz = /bits/ 64 <576000000>; 36051582e1d1SSumit Gupta opp-peak-kBps = <816000>; 36061582e1d1SSumit Gupta }; 36071582e1d1SSumit Gupta 36081582e1d1SSumit Gupta cl0_ch1_opp5: opp-729600000 { 36091582e1d1SSumit Gupta opp-hz = /bits/ 64 <729600000>; 36101582e1d1SSumit Gupta opp-peak-kBps = <816000>; 36111582e1d1SSumit Gupta }; 36121582e1d1SSumit Gupta 36131582e1d1SSumit Gupta cl0_ch1_opp6: opp-883200000 { 36141582e1d1SSumit Gupta opp-hz = /bits/ 64 <883200000>; 36151582e1d1SSumit Gupta opp-peak-kBps = <816000>; 36161582e1d1SSumit Gupta }; 36171582e1d1SSumit Gupta 36181582e1d1SSumit Gupta cl0_ch1_opp7: opp-1036800000 { 36191582e1d1SSumit Gupta opp-hz = /bits/ 64 <1036800000>; 36201582e1d1SSumit Gupta opp-peak-kBps = <816000>; 36211582e1d1SSumit Gupta }; 36221582e1d1SSumit Gupta 36231582e1d1SSumit Gupta cl0_ch1_opp8: opp-1190400000 { 36241582e1d1SSumit Gupta opp-hz = /bits/ 64 <1190400000>; 36251582e1d1SSumit Gupta opp-peak-kBps = <816000>; 36261582e1d1SSumit Gupta }; 36271582e1d1SSumit Gupta 36281582e1d1SSumit Gupta cl0_ch1_opp9: opp-1344000000 { 36291582e1d1SSumit Gupta opp-hz = /bits/ 64 <1344000000>; 36301582e1d1SSumit Gupta opp-peak-kBps = <1632000>; 36311582e1d1SSumit Gupta }; 36321582e1d1SSumit Gupta 36331582e1d1SSumit Gupta cl0_ch1_opp10: opp-1497600000 { 36341582e1d1SSumit Gupta opp-hz = /bits/ 64 <1497600000>; 36351582e1d1SSumit Gupta opp-peak-kBps = <1632000>; 36361582e1d1SSumit Gupta }; 36371582e1d1SSumit Gupta 36381582e1d1SSumit Gupta cl0_ch1_opp11: opp-1651200000 { 36391582e1d1SSumit Gupta opp-hz = /bits/ 64 <1651200000>; 36401582e1d1SSumit Gupta opp-peak-kBps = <2660000>; 36411582e1d1SSumit Gupta }; 36421582e1d1SSumit Gupta 36431582e1d1SSumit Gupta cl0_ch1_opp12: opp-1804800000 { 36441582e1d1SSumit Gupta opp-hz = /bits/ 64 <1804800000>; 36451582e1d1SSumit Gupta opp-peak-kBps = <2660000>; 36461582e1d1SSumit Gupta }; 36471582e1d1SSumit Gupta 36481582e1d1SSumit Gupta cl0_ch1_opp13: opp-1958400000 { 36491582e1d1SSumit Gupta opp-hz = /bits/ 64 <1958400000>; 36501582e1d1SSumit Gupta opp-peak-kBps = <3200000>; 36511582e1d1SSumit Gupta }; 36521582e1d1SSumit Gupta 36531582e1d1SSumit Gupta cl0_ch1_opp14: opp-2112000000 { 36541582e1d1SSumit Gupta opp-hz = /bits/ 64 <2112000000>; 36551582e1d1SSumit Gupta opp-peak-kBps = <6400000>; 36561582e1d1SSumit Gupta }; 36571582e1d1SSumit Gupta 36581582e1d1SSumit Gupta cl0_ch1_opp15: opp-2201600000 { 36591582e1d1SSumit Gupta opp-hz = /bits/ 64 <2201600000>; 36601582e1d1SSumit Gupta opp-peak-kBps = <6400000>; 36611582e1d1SSumit Gupta }; 36621582e1d1SSumit Gupta }; 36631582e1d1SSumit Gupta 36641582e1d1SSumit Gupta cl1_opp_tbl: opp-table-cluster1 { 36651582e1d1SSumit Gupta compatible = "operating-points-v2"; 36661582e1d1SSumit Gupta opp-shared; 36671582e1d1SSumit Gupta 36681582e1d1SSumit Gupta cl1_ch1_opp1: opp-115200000 { 36691582e1d1SSumit Gupta opp-hz = /bits/ 64 <115200000>; 36701582e1d1SSumit Gupta opp-peak-kBps = <816000>; 36711582e1d1SSumit Gupta }; 36721582e1d1SSumit Gupta 36731582e1d1SSumit Gupta cl1_ch1_opp2: opp-268800000 { 36741582e1d1SSumit Gupta opp-hz = /bits/ 64 <268800000>; 36751582e1d1SSumit Gupta opp-peak-kBps = <816000>; 36761582e1d1SSumit Gupta }; 36771582e1d1SSumit Gupta 36781582e1d1SSumit Gupta cl1_ch1_opp3: opp-422400000 { 36791582e1d1SSumit Gupta opp-hz = /bits/ 64 <422400000>; 36801582e1d1SSumit Gupta opp-peak-kBps = <816000>; 36811582e1d1SSumit Gupta }; 36821582e1d1SSumit Gupta 36831582e1d1SSumit Gupta cl1_ch1_opp4: opp-576000000 { 36841582e1d1SSumit Gupta opp-hz = /bits/ 64 <576000000>; 36851582e1d1SSumit Gupta opp-peak-kBps = <816000>; 36861582e1d1SSumit Gupta }; 36871582e1d1SSumit Gupta 36881582e1d1SSumit Gupta cl1_ch1_opp5: opp-729600000 { 36891582e1d1SSumit Gupta opp-hz = /bits/ 64 <729600000>; 36901582e1d1SSumit Gupta opp-peak-kBps = <816000>; 36911582e1d1SSumit Gupta }; 36921582e1d1SSumit Gupta 36931582e1d1SSumit Gupta cl1_ch1_opp6: opp-883200000 { 36941582e1d1SSumit Gupta opp-hz = /bits/ 64 <883200000>; 36951582e1d1SSumit Gupta opp-peak-kBps = <816000>; 36961582e1d1SSumit Gupta }; 36971582e1d1SSumit Gupta 36981582e1d1SSumit Gupta cl1_ch1_opp7: opp-1036800000 { 36991582e1d1SSumit Gupta opp-hz = /bits/ 64 <1036800000>; 37001582e1d1SSumit Gupta opp-peak-kBps = <816000>; 37011582e1d1SSumit Gupta }; 37021582e1d1SSumit Gupta 37031582e1d1SSumit Gupta cl1_ch1_opp8: opp-1190400000 { 37041582e1d1SSumit Gupta opp-hz = /bits/ 64 <1190400000>; 37051582e1d1SSumit Gupta opp-peak-kBps = <816000>; 37061582e1d1SSumit Gupta }; 37071582e1d1SSumit Gupta 37081582e1d1SSumit Gupta cl1_ch1_opp9: opp-1344000000 { 37091582e1d1SSumit Gupta opp-hz = /bits/ 64 <1344000000>; 37101582e1d1SSumit Gupta opp-peak-kBps = <1632000>; 37111582e1d1SSumit Gupta }; 37121582e1d1SSumit Gupta 37131582e1d1SSumit Gupta cl1_ch1_opp10: opp-1497600000 { 37141582e1d1SSumit Gupta opp-hz = /bits/ 64 <1497600000>; 37151582e1d1SSumit Gupta opp-peak-kBps = <1632000>; 37161582e1d1SSumit Gupta }; 37171582e1d1SSumit Gupta 37181582e1d1SSumit Gupta cl1_ch1_opp11: opp-1651200000 { 37191582e1d1SSumit Gupta opp-hz = /bits/ 64 <1651200000>; 37201582e1d1SSumit Gupta opp-peak-kBps = <2660000>; 37211582e1d1SSumit Gupta }; 37221582e1d1SSumit Gupta 37231582e1d1SSumit Gupta cl1_ch1_opp12: opp-1804800000 { 37241582e1d1SSumit Gupta opp-hz = /bits/ 64 <1804800000>; 37251582e1d1SSumit Gupta opp-peak-kBps = <2660000>; 37261582e1d1SSumit Gupta }; 37271582e1d1SSumit Gupta 37281582e1d1SSumit Gupta cl1_ch1_opp13: opp-1958400000 { 37291582e1d1SSumit Gupta opp-hz = /bits/ 64 <1958400000>; 37301582e1d1SSumit Gupta opp-peak-kBps = <3200000>; 37311582e1d1SSumit Gupta }; 37321582e1d1SSumit Gupta 37331582e1d1SSumit Gupta cl1_ch1_opp14: opp-2112000000 { 37341582e1d1SSumit Gupta opp-hz = /bits/ 64 <2112000000>; 37351582e1d1SSumit Gupta opp-peak-kBps = <6400000>; 37361582e1d1SSumit Gupta }; 37371582e1d1SSumit Gupta 37381582e1d1SSumit Gupta cl1_ch1_opp15: opp-2201600000 { 37391582e1d1SSumit Gupta opp-hz = /bits/ 64 <2201600000>; 37401582e1d1SSumit Gupta opp-peak-kBps = <6400000>; 37411582e1d1SSumit Gupta }; 37421582e1d1SSumit Gupta }; 37431582e1d1SSumit Gupta 37441582e1d1SSumit Gupta cl2_opp_tbl: opp-table-cluster2 { 37451582e1d1SSumit Gupta compatible = "operating-points-v2"; 37461582e1d1SSumit Gupta opp-shared; 37471582e1d1SSumit Gupta 37481582e1d1SSumit Gupta cl2_ch1_opp1: opp-115200000 { 37491582e1d1SSumit Gupta opp-hz = /bits/ 64 <115200000>; 37501582e1d1SSumit Gupta opp-peak-kBps = <816000>; 37511582e1d1SSumit Gupta }; 37521582e1d1SSumit Gupta 37531582e1d1SSumit Gupta cl2_ch1_opp2: opp-268800000 { 37541582e1d1SSumit Gupta opp-hz = /bits/ 64 <268800000>; 37551582e1d1SSumit Gupta opp-peak-kBps = <816000>; 37561582e1d1SSumit Gupta }; 37571582e1d1SSumit Gupta 37581582e1d1SSumit Gupta cl2_ch1_opp3: opp-422400000 { 37591582e1d1SSumit Gupta opp-hz = /bits/ 64 <422400000>; 37601582e1d1SSumit Gupta opp-peak-kBps = <816000>; 37611582e1d1SSumit Gupta }; 37621582e1d1SSumit Gupta 37631582e1d1SSumit Gupta cl2_ch1_opp4: opp-576000000 { 37641582e1d1SSumit Gupta opp-hz = /bits/ 64 <576000000>; 37651582e1d1SSumit Gupta opp-peak-kBps = <816000>; 37661582e1d1SSumit Gupta }; 37671582e1d1SSumit Gupta 37681582e1d1SSumit Gupta cl2_ch1_opp5: opp-729600000 { 37691582e1d1SSumit Gupta opp-hz = /bits/ 64 <729600000>; 37701582e1d1SSumit Gupta opp-peak-kBps = <816000>; 37711582e1d1SSumit Gupta }; 37721582e1d1SSumit Gupta 37731582e1d1SSumit Gupta cl2_ch1_opp6: opp-883200000 { 37741582e1d1SSumit Gupta opp-hz = /bits/ 64 <883200000>; 37751582e1d1SSumit Gupta opp-peak-kBps = <816000>; 37761582e1d1SSumit Gupta }; 37771582e1d1SSumit Gupta 37781582e1d1SSumit Gupta cl2_ch1_opp7: opp-1036800000 { 37791582e1d1SSumit Gupta opp-hz = /bits/ 64 <1036800000>; 37801582e1d1SSumit Gupta opp-peak-kBps = <816000>; 37811582e1d1SSumit Gupta }; 37821582e1d1SSumit Gupta 37831582e1d1SSumit Gupta cl2_ch1_opp8: opp-1190400000 { 37841582e1d1SSumit Gupta opp-hz = /bits/ 64 <1190400000>; 37851582e1d1SSumit Gupta opp-peak-kBps = <816000>; 37861582e1d1SSumit Gupta }; 37871582e1d1SSumit Gupta 37881582e1d1SSumit Gupta cl2_ch1_opp9: opp-1344000000 { 37891582e1d1SSumit Gupta opp-hz = /bits/ 64 <1344000000>; 37901582e1d1SSumit Gupta opp-peak-kBps = <1632000>; 37911582e1d1SSumit Gupta }; 37921582e1d1SSumit Gupta 37931582e1d1SSumit Gupta cl2_ch1_opp10: opp-1497600000 { 37941582e1d1SSumit Gupta opp-hz = /bits/ 64 <1497600000>; 37951582e1d1SSumit Gupta opp-peak-kBps = <1632000>; 37961582e1d1SSumit Gupta }; 37971582e1d1SSumit Gupta 37981582e1d1SSumit Gupta cl2_ch1_opp11: opp-1651200000 { 37991582e1d1SSumit Gupta opp-hz = /bits/ 64 <1651200000>; 38001582e1d1SSumit Gupta opp-peak-kBps = <2660000>; 38011582e1d1SSumit Gupta }; 38021582e1d1SSumit Gupta 38031582e1d1SSumit Gupta cl2_ch1_opp12: opp-1804800000 { 38041582e1d1SSumit Gupta opp-hz = /bits/ 64 <1804800000>; 38051582e1d1SSumit Gupta opp-peak-kBps = <2660000>; 38061582e1d1SSumit Gupta }; 38071582e1d1SSumit Gupta 38081582e1d1SSumit Gupta cl2_ch1_opp13: opp-1958400000 { 38091582e1d1SSumit Gupta opp-hz = /bits/ 64 <1958400000>; 38101582e1d1SSumit Gupta opp-peak-kBps = <3200000>; 38111582e1d1SSumit Gupta }; 38121582e1d1SSumit Gupta 38131582e1d1SSumit Gupta cl2_ch1_opp14: opp-2112000000 { 38141582e1d1SSumit Gupta opp-hz = /bits/ 64 <2112000000>; 38151582e1d1SSumit Gupta opp-peak-kBps = <6400000>; 38161582e1d1SSumit Gupta }; 38171582e1d1SSumit Gupta 38181582e1d1SSumit Gupta cl2_ch1_opp15: opp-2201600000 { 38191582e1d1SSumit Gupta opp-hz = /bits/ 64 <2201600000>; 38201582e1d1SSumit Gupta opp-peak-kBps = <6400000>; 38211582e1d1SSumit Gupta }; 38221582e1d1SSumit Gupta }; 382363944891SThierry Reding}; 3824