163944891SThierry Reding// SPDX-License-Identifier: GPL-2.0 263944891SThierry Reding 363944891SThierry Reding#include <dt-bindings/clock/tegra234-clock.h> 4699349e0SThierry Reding#include <dt-bindings/gpio/tegra234-gpio.h> 563944891SThierry Reding#include <dt-bindings/interrupt-controller/arm-gic.h> 663944891SThierry Reding#include <dt-bindings/mailbox/tegra186-hsp.h> 7eed280dfSThierry Reding#include <dt-bindings/memory/tegra234-mc.h> 8*dc94a94dSSameer Pujar#include <dt-bindings/power/tegra234-powergate.h> 963944891SThierry Reding#include <dt-bindings/reset/tegra234-reset.h> 1063944891SThierry Reding 1163944891SThierry Reding/ { 1263944891SThierry Reding compatible = "nvidia,tegra234"; 1363944891SThierry Reding interrupt-parent = <&gic>; 1463944891SThierry Reding #address-cells = <2>; 1563944891SThierry Reding #size-cells = <2>; 1663944891SThierry Reding 1763944891SThierry Reding bus@0 { 1863944891SThierry Reding compatible = "simple-bus"; 1963944891SThierry Reding #address-cells = <1>; 2063944891SThierry Reding #size-cells = <1>; 2163944891SThierry Reding 2263944891SThierry Reding ranges = <0x0 0x0 0x0 0x40000000>; 2363944891SThierry Reding 24*dc94a94dSSameer Pujar aconnect@2900000 { 25*dc94a94dSSameer Pujar compatible = "nvidia,tegra234-aconnect", 26*dc94a94dSSameer Pujar "nvidia,tegra210-aconnect"; 27*dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_APE>, 28*dc94a94dSSameer Pujar <&bpmp TEGRA234_CLK_APB2APE>; 29*dc94a94dSSameer Pujar clock-names = "ape", "apb2ape"; 30*dc94a94dSSameer Pujar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_AUD>; 31*dc94a94dSSameer Pujar #address-cells = <1>; 32*dc94a94dSSameer Pujar #size-cells = <1>; 33*dc94a94dSSameer Pujar ranges = <0x02900000 0x02900000 0x200000>; 34*dc94a94dSSameer Pujar status = "disabled"; 35*dc94a94dSSameer Pujar 36*dc94a94dSSameer Pujar tegra_ahub: ahub@2900800 { 37*dc94a94dSSameer Pujar compatible = "nvidia,tegra234-ahub"; 38*dc94a94dSSameer Pujar reg = <0x02900800 0x800>; 39*dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_AHUB>; 40*dc94a94dSSameer Pujar clock-names = "ahub"; 41*dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_AHUB>; 42*dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 43*dc94a94dSSameer Pujar #address-cells = <1>; 44*dc94a94dSSameer Pujar #size-cells = <1>; 45*dc94a94dSSameer Pujar ranges = <0x02900800 0x02900800 0x11800>; 46*dc94a94dSSameer Pujar status = "disabled"; 47*dc94a94dSSameer Pujar 48*dc94a94dSSameer Pujar tegra_i2s1: i2s@2901000 { 49*dc94a94dSSameer Pujar compatible = "nvidia,tegra234-i2s", 50*dc94a94dSSameer Pujar "nvidia,tegra210-i2s"; 51*dc94a94dSSameer Pujar reg = <0x2901000 0x100>; 52*dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_I2S1>, 53*dc94a94dSSameer Pujar <&bpmp TEGRA234_CLK_I2S1_SYNC_INPUT>; 54*dc94a94dSSameer Pujar clock-names = "i2s", "sync_input"; 55*dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_I2S1>; 56*dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 57*dc94a94dSSameer Pujar assigned-clock-rates = <1536000>; 58*dc94a94dSSameer Pujar sound-name-prefix = "I2S1"; 59*dc94a94dSSameer Pujar status = "disabled"; 60*dc94a94dSSameer Pujar }; 61*dc94a94dSSameer Pujar 62*dc94a94dSSameer Pujar tegra_i2s2: i2s@2901100 { 63*dc94a94dSSameer Pujar compatible = "nvidia,tegra234-i2s", 64*dc94a94dSSameer Pujar "nvidia,tegra210-i2s"; 65*dc94a94dSSameer Pujar reg = <0x2901100 0x100>; 66*dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_I2S2>, 67*dc94a94dSSameer Pujar <&bpmp TEGRA234_CLK_I2S2_SYNC_INPUT>; 68*dc94a94dSSameer Pujar clock-names = "i2s", "sync_input"; 69*dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_I2S2>; 70*dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 71*dc94a94dSSameer Pujar assigned-clock-rates = <1536000>; 72*dc94a94dSSameer Pujar sound-name-prefix = "I2S2"; 73*dc94a94dSSameer Pujar status = "disabled"; 74*dc94a94dSSameer Pujar }; 75*dc94a94dSSameer Pujar 76*dc94a94dSSameer Pujar tegra_i2s3: i2s@2901200 { 77*dc94a94dSSameer Pujar compatible = "nvidia,tegra234-i2s", 78*dc94a94dSSameer Pujar "nvidia,tegra210-i2s"; 79*dc94a94dSSameer Pujar reg = <0x2901200 0x100>; 80*dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_I2S3>, 81*dc94a94dSSameer Pujar <&bpmp TEGRA234_CLK_I2S3_SYNC_INPUT>; 82*dc94a94dSSameer Pujar clock-names = "i2s", "sync_input"; 83*dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_I2S3>; 84*dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 85*dc94a94dSSameer Pujar assigned-clock-rates = <1536000>; 86*dc94a94dSSameer Pujar sound-name-prefix = "I2S3"; 87*dc94a94dSSameer Pujar status = "disabled"; 88*dc94a94dSSameer Pujar }; 89*dc94a94dSSameer Pujar 90*dc94a94dSSameer Pujar tegra_i2s4: i2s@2901300 { 91*dc94a94dSSameer Pujar compatible = "nvidia,tegra234-i2s", 92*dc94a94dSSameer Pujar "nvidia,tegra210-i2s"; 93*dc94a94dSSameer Pujar reg = <0x2901300 0x100>; 94*dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_I2S4>, 95*dc94a94dSSameer Pujar <&bpmp TEGRA234_CLK_I2S4_SYNC_INPUT>; 96*dc94a94dSSameer Pujar clock-names = "i2s", "sync_input"; 97*dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_I2S4>; 98*dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 99*dc94a94dSSameer Pujar assigned-clock-rates = <1536000>; 100*dc94a94dSSameer Pujar sound-name-prefix = "I2S4"; 101*dc94a94dSSameer Pujar status = "disabled"; 102*dc94a94dSSameer Pujar }; 103*dc94a94dSSameer Pujar 104*dc94a94dSSameer Pujar tegra_i2s5: i2s@2901400 { 105*dc94a94dSSameer Pujar compatible = "nvidia,tegra234-i2s", 106*dc94a94dSSameer Pujar "nvidia,tegra210-i2s"; 107*dc94a94dSSameer Pujar reg = <0x2901400 0x100>; 108*dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_I2S5>, 109*dc94a94dSSameer Pujar <&bpmp TEGRA234_CLK_I2S5_SYNC_INPUT>; 110*dc94a94dSSameer Pujar clock-names = "i2s", "sync_input"; 111*dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_I2S5>; 112*dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 113*dc94a94dSSameer Pujar assigned-clock-rates = <1536000>; 114*dc94a94dSSameer Pujar sound-name-prefix = "I2S5"; 115*dc94a94dSSameer Pujar status = "disabled"; 116*dc94a94dSSameer Pujar }; 117*dc94a94dSSameer Pujar 118*dc94a94dSSameer Pujar tegra_i2s6: i2s@2901500 { 119*dc94a94dSSameer Pujar compatible = "nvidia,tegra234-i2s", 120*dc94a94dSSameer Pujar "nvidia,tegra210-i2s"; 121*dc94a94dSSameer Pujar reg = <0x2901500 0x100>; 122*dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_I2S6>, 123*dc94a94dSSameer Pujar <&bpmp TEGRA234_CLK_I2S6_SYNC_INPUT>; 124*dc94a94dSSameer Pujar clock-names = "i2s", "sync_input"; 125*dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_I2S6>; 126*dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 127*dc94a94dSSameer Pujar assigned-clock-rates = <1536000>; 128*dc94a94dSSameer Pujar sound-name-prefix = "I2S6"; 129*dc94a94dSSameer Pujar status = "disabled"; 130*dc94a94dSSameer Pujar }; 131*dc94a94dSSameer Pujar 132*dc94a94dSSameer Pujar tegra_sfc1: sfc@2902000 { 133*dc94a94dSSameer Pujar compatible = "nvidia,tegra234-sfc", 134*dc94a94dSSameer Pujar "nvidia,tegra210-sfc"; 135*dc94a94dSSameer Pujar reg = <0x2902000 0x200>; 136*dc94a94dSSameer Pujar sound-name-prefix = "SFC1"; 137*dc94a94dSSameer Pujar status = "disabled"; 138*dc94a94dSSameer Pujar }; 139*dc94a94dSSameer Pujar 140*dc94a94dSSameer Pujar tegra_sfc2: sfc@2902200 { 141*dc94a94dSSameer Pujar compatible = "nvidia,tegra234-sfc", 142*dc94a94dSSameer Pujar "nvidia,tegra210-sfc"; 143*dc94a94dSSameer Pujar reg = <0x2902200 0x200>; 144*dc94a94dSSameer Pujar sound-name-prefix = "SFC2"; 145*dc94a94dSSameer Pujar status = "disabled"; 146*dc94a94dSSameer Pujar }; 147*dc94a94dSSameer Pujar 148*dc94a94dSSameer Pujar tegra_sfc3: sfc@2902400 { 149*dc94a94dSSameer Pujar compatible = "nvidia,tegra234-sfc", 150*dc94a94dSSameer Pujar "nvidia,tegra210-sfc"; 151*dc94a94dSSameer Pujar reg = <0x2902400 0x200>; 152*dc94a94dSSameer Pujar sound-name-prefix = "SFC3"; 153*dc94a94dSSameer Pujar status = "disabled"; 154*dc94a94dSSameer Pujar }; 155*dc94a94dSSameer Pujar 156*dc94a94dSSameer Pujar tegra_sfc4: sfc@2902600 { 157*dc94a94dSSameer Pujar compatible = "nvidia,tegra234-sfc", 158*dc94a94dSSameer Pujar "nvidia,tegra210-sfc"; 159*dc94a94dSSameer Pujar reg = <0x2902600 0x200>; 160*dc94a94dSSameer Pujar sound-name-prefix = "SFC4"; 161*dc94a94dSSameer Pujar status = "disabled"; 162*dc94a94dSSameer Pujar }; 163*dc94a94dSSameer Pujar 164*dc94a94dSSameer Pujar tegra_amx1: amx@2903000 { 165*dc94a94dSSameer Pujar compatible = "nvidia,tegra234-amx", 166*dc94a94dSSameer Pujar "nvidia,tegra194-amx"; 167*dc94a94dSSameer Pujar reg = <0x2903000 0x100>; 168*dc94a94dSSameer Pujar sound-name-prefix = "AMX1"; 169*dc94a94dSSameer Pujar status = "disabled"; 170*dc94a94dSSameer Pujar }; 171*dc94a94dSSameer Pujar 172*dc94a94dSSameer Pujar tegra_amx2: amx@2903100 { 173*dc94a94dSSameer Pujar compatible = "nvidia,tegra234-amx", 174*dc94a94dSSameer Pujar "nvidia,tegra194-amx"; 175*dc94a94dSSameer Pujar reg = <0x2903100 0x100>; 176*dc94a94dSSameer Pujar sound-name-prefix = "AMX2"; 177*dc94a94dSSameer Pujar status = "disabled"; 178*dc94a94dSSameer Pujar }; 179*dc94a94dSSameer Pujar 180*dc94a94dSSameer Pujar tegra_amx3: amx@2903200 { 181*dc94a94dSSameer Pujar compatible = "nvidia,tegra234-amx", 182*dc94a94dSSameer Pujar "nvidia,tegra194-amx"; 183*dc94a94dSSameer Pujar reg = <0x2903200 0x100>; 184*dc94a94dSSameer Pujar sound-name-prefix = "AMX3"; 185*dc94a94dSSameer Pujar status = "disabled"; 186*dc94a94dSSameer Pujar }; 187*dc94a94dSSameer Pujar 188*dc94a94dSSameer Pujar tegra_amx4: amx@2903300 { 189*dc94a94dSSameer Pujar compatible = "nvidia,tegra234-amx", 190*dc94a94dSSameer Pujar "nvidia,tegra194-amx"; 191*dc94a94dSSameer Pujar reg = <0x2903300 0x100>; 192*dc94a94dSSameer Pujar sound-name-prefix = "AMX4"; 193*dc94a94dSSameer Pujar status = "disabled"; 194*dc94a94dSSameer Pujar }; 195*dc94a94dSSameer Pujar 196*dc94a94dSSameer Pujar tegra_adx1: adx@2903800 { 197*dc94a94dSSameer Pujar compatible = "nvidia,tegra234-adx", 198*dc94a94dSSameer Pujar "nvidia,tegra210-adx"; 199*dc94a94dSSameer Pujar reg = <0x2903800 0x100>; 200*dc94a94dSSameer Pujar sound-name-prefix = "ADX1"; 201*dc94a94dSSameer Pujar status = "disabled"; 202*dc94a94dSSameer Pujar }; 203*dc94a94dSSameer Pujar 204*dc94a94dSSameer Pujar tegra_adx2: adx@2903900 { 205*dc94a94dSSameer Pujar compatible = "nvidia,tegra234-adx", 206*dc94a94dSSameer Pujar "nvidia,tegra210-adx"; 207*dc94a94dSSameer Pujar reg = <0x2903900 0x100>; 208*dc94a94dSSameer Pujar sound-name-prefix = "ADX2"; 209*dc94a94dSSameer Pujar status = "disabled"; 210*dc94a94dSSameer Pujar }; 211*dc94a94dSSameer Pujar 212*dc94a94dSSameer Pujar tegra_adx3: adx@2903a00 { 213*dc94a94dSSameer Pujar compatible = "nvidia,tegra234-adx", 214*dc94a94dSSameer Pujar "nvidia,tegra210-adx"; 215*dc94a94dSSameer Pujar reg = <0x2903a00 0x100>; 216*dc94a94dSSameer Pujar sound-name-prefix = "ADX3"; 217*dc94a94dSSameer Pujar status = "disabled"; 218*dc94a94dSSameer Pujar }; 219*dc94a94dSSameer Pujar 220*dc94a94dSSameer Pujar tegra_adx4: adx@2903b00 { 221*dc94a94dSSameer Pujar compatible = "nvidia,tegra234-adx", 222*dc94a94dSSameer Pujar "nvidia,tegra210-adx"; 223*dc94a94dSSameer Pujar reg = <0x2903b00 0x100>; 224*dc94a94dSSameer Pujar sound-name-prefix = "ADX4"; 225*dc94a94dSSameer Pujar status = "disabled"; 226*dc94a94dSSameer Pujar }; 227*dc94a94dSSameer Pujar 228*dc94a94dSSameer Pujar 229*dc94a94dSSameer Pujar tegra_dmic1: dmic@2904000 { 230*dc94a94dSSameer Pujar compatible = "nvidia,tegra234-dmic", 231*dc94a94dSSameer Pujar "nvidia,tegra210-dmic"; 232*dc94a94dSSameer Pujar reg = <0x2904000 0x100>; 233*dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_DMIC1>; 234*dc94a94dSSameer Pujar clock-names = "dmic"; 235*dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_DMIC1>; 236*dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 237*dc94a94dSSameer Pujar assigned-clock-rates = <3072000>; 238*dc94a94dSSameer Pujar sound-name-prefix = "DMIC1"; 239*dc94a94dSSameer Pujar status = "disabled"; 240*dc94a94dSSameer Pujar }; 241*dc94a94dSSameer Pujar 242*dc94a94dSSameer Pujar tegra_dmic2: dmic@2904100 { 243*dc94a94dSSameer Pujar compatible = "nvidia,tegra234-dmic", 244*dc94a94dSSameer Pujar "nvidia,tegra210-dmic"; 245*dc94a94dSSameer Pujar reg = <0x2904100 0x100>; 246*dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_DMIC2>; 247*dc94a94dSSameer Pujar clock-names = "dmic"; 248*dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_DMIC2>; 249*dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 250*dc94a94dSSameer Pujar assigned-clock-rates = <3072000>; 251*dc94a94dSSameer Pujar sound-name-prefix = "DMIC2"; 252*dc94a94dSSameer Pujar status = "disabled"; 253*dc94a94dSSameer Pujar }; 254*dc94a94dSSameer Pujar 255*dc94a94dSSameer Pujar tegra_dmic3: dmic@2904200 { 256*dc94a94dSSameer Pujar compatible = "nvidia,tegra234-dmic", 257*dc94a94dSSameer Pujar "nvidia,tegra210-dmic"; 258*dc94a94dSSameer Pujar reg = <0x2904200 0x100>; 259*dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_DMIC3>; 260*dc94a94dSSameer Pujar clock-names = "dmic"; 261*dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_DMIC3>; 262*dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 263*dc94a94dSSameer Pujar assigned-clock-rates = <3072000>; 264*dc94a94dSSameer Pujar sound-name-prefix = "DMIC3"; 265*dc94a94dSSameer Pujar status = "disabled"; 266*dc94a94dSSameer Pujar }; 267*dc94a94dSSameer Pujar 268*dc94a94dSSameer Pujar tegra_dmic4: dmic@2904300 { 269*dc94a94dSSameer Pujar compatible = "nvidia,tegra234-dmic", 270*dc94a94dSSameer Pujar "nvidia,tegra210-dmic"; 271*dc94a94dSSameer Pujar reg = <0x2904300 0x100>; 272*dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_DMIC4>; 273*dc94a94dSSameer Pujar clock-names = "dmic"; 274*dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_DMIC4>; 275*dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 276*dc94a94dSSameer Pujar assigned-clock-rates = <3072000>; 277*dc94a94dSSameer Pujar sound-name-prefix = "DMIC4"; 278*dc94a94dSSameer Pujar status = "disabled"; 279*dc94a94dSSameer Pujar }; 280*dc94a94dSSameer Pujar 281*dc94a94dSSameer Pujar tegra_dspk1: dspk@2905000 { 282*dc94a94dSSameer Pujar compatible = "nvidia,tegra234-dspk", 283*dc94a94dSSameer Pujar "nvidia,tegra186-dspk"; 284*dc94a94dSSameer Pujar reg = <0x2905000 0x100>; 285*dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_DSPK1>; 286*dc94a94dSSameer Pujar clock-names = "dspk"; 287*dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_DSPK1>; 288*dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 289*dc94a94dSSameer Pujar assigned-clock-rates = <12288000>; 290*dc94a94dSSameer Pujar sound-name-prefix = "DSPK1"; 291*dc94a94dSSameer Pujar status = "disabled"; 292*dc94a94dSSameer Pujar }; 293*dc94a94dSSameer Pujar 294*dc94a94dSSameer Pujar tegra_dspk2: dspk@2905100 { 295*dc94a94dSSameer Pujar compatible = "nvidia,tegra234-dspk", 296*dc94a94dSSameer Pujar "nvidia,tegra186-dspk"; 297*dc94a94dSSameer Pujar reg = <0x2905100 0x100>; 298*dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_DSPK2>; 299*dc94a94dSSameer Pujar clock-names = "dspk"; 300*dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_DSPK2>; 301*dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 302*dc94a94dSSameer Pujar assigned-clock-rates = <12288000>; 303*dc94a94dSSameer Pujar sound-name-prefix = "DSPK2"; 304*dc94a94dSSameer Pujar status = "disabled"; 305*dc94a94dSSameer Pujar }; 306*dc94a94dSSameer Pujar 307*dc94a94dSSameer Pujar tegra_mvc1: mvc@290a000 { 308*dc94a94dSSameer Pujar compatible = "nvidia,tegra234-mvc", 309*dc94a94dSSameer Pujar "nvidia,tegra210-mvc"; 310*dc94a94dSSameer Pujar reg = <0x290a000 0x200>; 311*dc94a94dSSameer Pujar sound-name-prefix = "MVC1"; 312*dc94a94dSSameer Pujar status = "disabled"; 313*dc94a94dSSameer Pujar }; 314*dc94a94dSSameer Pujar 315*dc94a94dSSameer Pujar tegra_mvc2: mvc@290a200 { 316*dc94a94dSSameer Pujar compatible = "nvidia,tegra234-mvc", 317*dc94a94dSSameer Pujar "nvidia,tegra210-mvc"; 318*dc94a94dSSameer Pujar reg = <0x290a200 0x200>; 319*dc94a94dSSameer Pujar sound-name-prefix = "MVC2"; 320*dc94a94dSSameer Pujar status = "disabled"; 321*dc94a94dSSameer Pujar }; 322*dc94a94dSSameer Pujar 323*dc94a94dSSameer Pujar tegra_amixer: amixer@290bb00 { 324*dc94a94dSSameer Pujar compatible = "nvidia,tegra234-amixer", 325*dc94a94dSSameer Pujar "nvidia,tegra210-amixer"; 326*dc94a94dSSameer Pujar reg = <0x290bb00 0x800>; 327*dc94a94dSSameer Pujar sound-name-prefix = "MIXER1"; 328*dc94a94dSSameer Pujar status = "disabled"; 329*dc94a94dSSameer Pujar }; 330*dc94a94dSSameer Pujar 331*dc94a94dSSameer Pujar tegra_admaif: admaif@290f000 { 332*dc94a94dSSameer Pujar compatible = "nvidia,tegra234-admaif", 333*dc94a94dSSameer Pujar "nvidia,tegra186-admaif"; 334*dc94a94dSSameer Pujar reg = <0x0290f000 0x1000>; 335*dc94a94dSSameer Pujar dmas = <&adma 1>, <&adma 1>, 336*dc94a94dSSameer Pujar <&adma 2>, <&adma 2>, 337*dc94a94dSSameer Pujar <&adma 3>, <&adma 3>, 338*dc94a94dSSameer Pujar <&adma 4>, <&adma 4>, 339*dc94a94dSSameer Pujar <&adma 5>, <&adma 5>, 340*dc94a94dSSameer Pujar <&adma 6>, <&adma 6>, 341*dc94a94dSSameer Pujar <&adma 7>, <&adma 7>, 342*dc94a94dSSameer Pujar <&adma 8>, <&adma 8>, 343*dc94a94dSSameer Pujar <&adma 9>, <&adma 9>, 344*dc94a94dSSameer Pujar <&adma 10>, <&adma 10>, 345*dc94a94dSSameer Pujar <&adma 11>, <&adma 11>, 346*dc94a94dSSameer Pujar <&adma 12>, <&adma 12>, 347*dc94a94dSSameer Pujar <&adma 13>, <&adma 13>, 348*dc94a94dSSameer Pujar <&adma 14>, <&adma 14>, 349*dc94a94dSSameer Pujar <&adma 15>, <&adma 15>, 350*dc94a94dSSameer Pujar <&adma 16>, <&adma 16>, 351*dc94a94dSSameer Pujar <&adma 17>, <&adma 17>, 352*dc94a94dSSameer Pujar <&adma 18>, <&adma 18>, 353*dc94a94dSSameer Pujar <&adma 19>, <&adma 19>, 354*dc94a94dSSameer Pujar <&adma 20>, <&adma 20>; 355*dc94a94dSSameer Pujar dma-names = "rx1", "tx1", 356*dc94a94dSSameer Pujar "rx2", "tx2", 357*dc94a94dSSameer Pujar "rx3", "tx3", 358*dc94a94dSSameer Pujar "rx4", "tx4", 359*dc94a94dSSameer Pujar "rx5", "tx5", 360*dc94a94dSSameer Pujar "rx6", "tx6", 361*dc94a94dSSameer Pujar "rx7", "tx7", 362*dc94a94dSSameer Pujar "rx8", "tx8", 363*dc94a94dSSameer Pujar "rx9", "tx9", 364*dc94a94dSSameer Pujar "rx10", "tx10", 365*dc94a94dSSameer Pujar "rx11", "tx11", 366*dc94a94dSSameer Pujar "rx12", "tx12", 367*dc94a94dSSameer Pujar "rx13", "tx13", 368*dc94a94dSSameer Pujar "rx14", "tx14", 369*dc94a94dSSameer Pujar "rx15", "tx15", 370*dc94a94dSSameer Pujar "rx16", "tx16", 371*dc94a94dSSameer Pujar "rx17", "tx17", 372*dc94a94dSSameer Pujar "rx18", "tx18", 373*dc94a94dSSameer Pujar "rx19", "tx19", 374*dc94a94dSSameer Pujar "rx20", "tx20"; 375*dc94a94dSSameer Pujar interconnects = <&mc TEGRA234_MEMORY_CLIENT_APEDMAR &emc>, 376*dc94a94dSSameer Pujar <&mc TEGRA234_MEMORY_CLIENT_APEDMAW &emc>; 377*dc94a94dSSameer Pujar interconnect-names = "dma-mem", "write"; 378*dc94a94dSSameer Pujar iommus = <&smmu_niso0 TEGRA234_SID_APE>; 379*dc94a94dSSameer Pujar status = "disabled"; 380*dc94a94dSSameer Pujar }; 381*dc94a94dSSameer Pujar }; 382*dc94a94dSSameer Pujar 383*dc94a94dSSameer Pujar adma: dma-controller@2930000 { 384*dc94a94dSSameer Pujar compatible = "nvidia,tegra234-adma", 385*dc94a94dSSameer Pujar "nvidia,tegra186-adma"; 386*dc94a94dSSameer Pujar reg = <0x02930000 0x20000>; 387*dc94a94dSSameer Pujar interrupt-parent = <&agic>; 388*dc94a94dSSameer Pujar interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 389*dc94a94dSSameer Pujar <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 390*dc94a94dSSameer Pujar <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 391*dc94a94dSSameer Pujar <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 392*dc94a94dSSameer Pujar <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 393*dc94a94dSSameer Pujar <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 394*dc94a94dSSameer Pujar <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 395*dc94a94dSSameer Pujar <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 396*dc94a94dSSameer Pujar <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 397*dc94a94dSSameer Pujar <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 398*dc94a94dSSameer Pujar <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 399*dc94a94dSSameer Pujar <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 400*dc94a94dSSameer Pujar <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 401*dc94a94dSSameer Pujar <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 402*dc94a94dSSameer Pujar <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 403*dc94a94dSSameer Pujar <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 404*dc94a94dSSameer Pujar <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 405*dc94a94dSSameer Pujar <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 406*dc94a94dSSameer Pujar <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 407*dc94a94dSSameer Pujar <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 408*dc94a94dSSameer Pujar <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 409*dc94a94dSSameer Pujar <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 410*dc94a94dSSameer Pujar <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 411*dc94a94dSSameer Pujar <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 412*dc94a94dSSameer Pujar <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 413*dc94a94dSSameer Pujar <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 414*dc94a94dSSameer Pujar <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 415*dc94a94dSSameer Pujar <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 416*dc94a94dSSameer Pujar <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 417*dc94a94dSSameer Pujar <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 418*dc94a94dSSameer Pujar <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 419*dc94a94dSSameer Pujar <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 420*dc94a94dSSameer Pujar #dma-cells = <1>; 421*dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_AHUB>; 422*dc94a94dSSameer Pujar clock-names = "d_audio"; 423*dc94a94dSSameer Pujar status = "disabled"; 424*dc94a94dSSameer Pujar }; 425*dc94a94dSSameer Pujar 426*dc94a94dSSameer Pujar agic: interrupt-controller@2a40000 { 427*dc94a94dSSameer Pujar compatible = "nvidia,tegra234-agic", 428*dc94a94dSSameer Pujar "nvidia,tegra210-agic"; 429*dc94a94dSSameer Pujar #interrupt-cells = <3>; 430*dc94a94dSSameer Pujar interrupt-controller; 431*dc94a94dSSameer Pujar reg = <0x02a41000 0x1000>, 432*dc94a94dSSameer Pujar <0x02a42000 0x2000>; 433*dc94a94dSSameer Pujar interrupts = <GIC_SPI 145 434*dc94a94dSSameer Pujar (GIC_CPU_MASK_SIMPLE(4) | 435*dc94a94dSSameer Pujar IRQ_TYPE_LEVEL_HIGH)>; 436*dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_APE>; 437*dc94a94dSSameer Pujar clock-names = "clk"; 438*dc94a94dSSameer Pujar status = "disabled"; 439*dc94a94dSSameer Pujar }; 440*dc94a94dSSameer Pujar }; 441*dc94a94dSSameer Pujar 44263944891SThierry Reding misc@100000 { 44363944891SThierry Reding compatible = "nvidia,tegra234-misc"; 44463944891SThierry Reding reg = <0x00100000 0xf000>, 44563944891SThierry Reding <0x0010f000 0x1000>; 44663944891SThierry Reding status = "okay"; 44763944891SThierry Reding }; 44863944891SThierry Reding 449f0e12668SThierry Reding gpio: gpio@2200000 { 450f0e12668SThierry Reding compatible = "nvidia,tegra234-gpio"; 451f0e12668SThierry Reding reg-names = "security", "gpio"; 452f0e12668SThierry Reding reg = <0x02200000 0x10000>, 453f0e12668SThierry Reding <0x02210000 0x10000>; 454f0e12668SThierry Reding interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 455f0e12668SThierry Reding <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 456f0e12668SThierry Reding <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 457f0e12668SThierry Reding <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, 458f0e12668SThierry Reding <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 459f0e12668SThierry Reding <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 460f0e12668SThierry Reding <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 461f0e12668SThierry Reding <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 462f0e12668SThierry Reding <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 463f0e12668SThierry Reding <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 464f0e12668SThierry Reding <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 465f0e12668SThierry Reding <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 466f0e12668SThierry Reding <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 467f0e12668SThierry Reding <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 468f0e12668SThierry Reding <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 469f0e12668SThierry Reding <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 470f0e12668SThierry Reding <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 471f0e12668SThierry Reding <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 472f0e12668SThierry Reding <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 473f0e12668SThierry Reding <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 474f0e12668SThierry Reding <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 475f0e12668SThierry Reding <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 476f0e12668SThierry Reding <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 477f0e12668SThierry Reding <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 478f0e12668SThierry Reding <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 479f0e12668SThierry Reding <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 480f0e12668SThierry Reding <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 481f0e12668SThierry Reding <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 482f0e12668SThierry Reding <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 483f0e12668SThierry Reding <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 484f0e12668SThierry Reding <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 485f0e12668SThierry Reding <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 486f0e12668SThierry Reding <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 487f0e12668SThierry Reding <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 488f0e12668SThierry Reding <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 489f0e12668SThierry Reding <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 490f0e12668SThierry Reding <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 491f0e12668SThierry Reding <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 492f0e12668SThierry Reding <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 493f0e12668SThierry Reding <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 494f0e12668SThierry Reding <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 495f0e12668SThierry Reding <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 496f0e12668SThierry Reding <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 497f0e12668SThierry Reding <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 498f0e12668SThierry Reding <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 499f0e12668SThierry Reding <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 500f0e12668SThierry Reding <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 501f0e12668SThierry Reding <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 502f0e12668SThierry Reding #interrupt-cells = <2>; 503f0e12668SThierry Reding interrupt-controller; 504f0e12668SThierry Reding #gpio-cells = <2>; 505f0e12668SThierry Reding gpio-controller; 506f0e12668SThierry Reding }; 507f0e12668SThierry Reding 508eed280dfSThierry Reding mc: memory-controller@2c00000 { 509eed280dfSThierry Reding compatible = "nvidia,tegra234-mc"; 510eed280dfSThierry Reding reg = <0x02c00000 0x100000>, 511eed280dfSThierry Reding <0x02b80000 0x040000>, 512eed280dfSThierry Reding <0x01700000 0x100000>; 513eed280dfSThierry Reding interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 514eed280dfSThierry Reding #interconnect-cells = <1>; 515eed280dfSThierry Reding status = "okay"; 516eed280dfSThierry Reding 517eed280dfSThierry Reding #address-cells = <2>; 518eed280dfSThierry Reding #size-cells = <2>; 519eed280dfSThierry Reding 520eed280dfSThierry Reding ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>, 521eed280dfSThierry Reding <0x02b80000 0x0 0x02b80000 0x0 0x040000>, 522eed280dfSThierry Reding <0x02c00000 0x0 0x02c00000 0x0 0x100000>; 523eed280dfSThierry Reding 524eed280dfSThierry Reding /* 525eed280dfSThierry Reding * Bit 39 of addresses passing through the memory 526eed280dfSThierry Reding * controller selects the XBAR format used when memory 527eed280dfSThierry Reding * is accessed. This is used to transparently access 528eed280dfSThierry Reding * memory in the XBAR format used by the discrete GPU 529eed280dfSThierry Reding * (bit 39 set) or Tegra (bit 39 clear). 530eed280dfSThierry Reding * 531eed280dfSThierry Reding * As a consequence, the operating system must ensure 532eed280dfSThierry Reding * that bit 39 is never used implicitly, for example 533eed280dfSThierry Reding * via an I/O virtual address mapping of an IOMMU. If 534eed280dfSThierry Reding * devices require access to the XBAR switch, their 535eed280dfSThierry Reding * drivers must set this bit explicitly. 536eed280dfSThierry Reding * 537eed280dfSThierry Reding * Limit the DMA range for memory clients to [38:0]. 538eed280dfSThierry Reding */ 539eed280dfSThierry Reding dma-ranges = <0x0 0x0 0x0 0x80 0x0>; 540eed280dfSThierry Reding 541eed280dfSThierry Reding emc: external-memory-controller@2c60000 { 542eed280dfSThierry Reding compatible = "nvidia,tegra234-emc"; 543eed280dfSThierry Reding reg = <0x0 0x02c60000 0x0 0x90000>, 544eed280dfSThierry Reding <0x0 0x01780000 0x0 0x80000>; 545eed280dfSThierry Reding interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 546eed280dfSThierry Reding clocks = <&bpmp TEGRA234_CLK_EMC>; 547eed280dfSThierry Reding clock-names = "emc"; 548eed280dfSThierry Reding status = "okay"; 549eed280dfSThierry Reding 550eed280dfSThierry Reding #interconnect-cells = <0>; 551eed280dfSThierry Reding 552eed280dfSThierry Reding nvidia,bpmp = <&bpmp>; 553eed280dfSThierry Reding }; 554eed280dfSThierry Reding }; 555eed280dfSThierry Reding 55663944891SThierry Reding uarta: serial@3100000 { 55763944891SThierry Reding compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart"; 55863944891SThierry Reding reg = <0x03100000 0x10000>; 55963944891SThierry Reding interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 56063944891SThierry Reding clocks = <&bpmp TEGRA234_CLK_UARTA>; 56163944891SThierry Reding clock-names = "serial"; 56263944891SThierry Reding resets = <&bpmp TEGRA234_RESET_UARTA>; 56363944891SThierry Reding reset-names = "serial"; 56463944891SThierry Reding status = "disabled"; 56563944891SThierry Reding }; 56663944891SThierry Reding 567156af9deSAkhil R gen1_i2c: i2c@3160000 { 568156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 569156af9deSAkhil R reg = <0x3160000 0x100>; 570156af9deSAkhil R status = "disabled"; 571156af9deSAkhil R interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 572156af9deSAkhil R clock-frequency = <400000>; 573156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C1 574156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 575156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C1>; 576156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 577156af9deSAkhil R clock-names = "div-clk", "parent"; 578156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C1>; 579156af9deSAkhil R reset-names = "i2c"; 580156af9deSAkhil R }; 581156af9deSAkhil R 582156af9deSAkhil R cam_i2c: i2c@3180000 { 583156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 584156af9deSAkhil R reg = <0x3180000 0x100>; 585156af9deSAkhil R interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 586156af9deSAkhil R status = "disabled"; 587156af9deSAkhil R clock-frequency = <400000>; 588156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C3 589156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 590156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C3>; 591156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 592156af9deSAkhil R clock-names = "div-clk", "parent"; 593156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C3>; 594156af9deSAkhil R reset-names = "i2c"; 595156af9deSAkhil R }; 596156af9deSAkhil R 597156af9deSAkhil R dp_aux_ch1_i2c: i2c@3190000 { 598156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 599156af9deSAkhil R reg = <0x3190000 0x100>; 600156af9deSAkhil R interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 601156af9deSAkhil R status = "disabled"; 602156af9deSAkhil R clock-frequency = <100000>; 603156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C4 604156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 605156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C4>; 606156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 607156af9deSAkhil R clock-names = "div-clk", "parent"; 608156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C4>; 609156af9deSAkhil R reset-names = "i2c"; 610156af9deSAkhil R }; 611156af9deSAkhil R 612156af9deSAkhil R dp_aux_ch0_i2c: i2c@31b0000 { 613156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 614156af9deSAkhil R reg = <0x31b0000 0x100>; 615156af9deSAkhil R interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 616156af9deSAkhil R status = "disabled"; 617156af9deSAkhil R clock-frequency = <100000>; 618156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C6 619156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 620156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C6>; 621156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 622156af9deSAkhil R clock-names = "div-clk", "parent"; 623156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C6>; 624156af9deSAkhil R reset-names = "i2c"; 625156af9deSAkhil R }; 626156af9deSAkhil R 627156af9deSAkhil R dp_aux_ch2_i2c: i2c@31c0000 { 628156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 629156af9deSAkhil R reg = <0x31c0000 0x100>; 630156af9deSAkhil R interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 631156af9deSAkhil R status = "disabled"; 632156af9deSAkhil R clock-frequency = <100000>; 633156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C7 634156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 635156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C7>; 636156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 637156af9deSAkhil R clock-names = "div-clk", "parent"; 638156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C7>; 639156af9deSAkhil R reset-names = "i2c"; 640156af9deSAkhil R }; 641156af9deSAkhil R 642156af9deSAkhil R dp_aux_ch3_i2c: i2c@31e0000 { 643156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 644156af9deSAkhil R reg = <0x31e0000 0x100>; 645156af9deSAkhil R interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 646156af9deSAkhil R status = "disabled"; 647156af9deSAkhil R clock-frequency = <100000>; 648156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C9 649156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 650156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C9>; 651156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 652156af9deSAkhil R clock-names = "div-clk", "parent"; 653156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C9>; 654156af9deSAkhil R reset-names = "i2c"; 655156af9deSAkhil R }; 656156af9deSAkhil R 6575e69088dSAkhil R pwm1: pwm@3280000 { 6585e69088dSAkhil R compatible = "nvidia,tegra194-pwm", 6595e69088dSAkhil R "nvidia,tegra186-pwm"; 6605e69088dSAkhil R reg = <0x3280000 0x10000>; 6615e69088dSAkhil R clocks = <&bpmp TEGRA234_CLK_PWM1>; 6625e69088dSAkhil R clock-names = "pwm"; 6635e69088dSAkhil R resets = <&bpmp TEGRA234_RESET_PWM1>; 6645e69088dSAkhil R reset-names = "pwm"; 6655e69088dSAkhil R status = "disabled"; 6665e69088dSAkhil R #pwm-cells = <2>; 6675e69088dSAkhil R }; 6685e69088dSAkhil R 66963944891SThierry Reding mmc@3460000 { 67063944891SThierry Reding compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci"; 67163944891SThierry Reding reg = <0x03460000 0x20000>; 67263944891SThierry Reding interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 673e086d82dSMikko Perttunen clocks = <&bpmp TEGRA234_CLK_SDMMC4>, 674e086d82dSMikko Perttunen <&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>; 675e086d82dSMikko Perttunen clock-names = "sdhci", "tmclk"; 676e086d82dSMikko Perttunen assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC4>, 677e086d82dSMikko Perttunen <&bpmp TEGRA234_CLK_PLLC4>; 678e086d82dSMikko Perttunen assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4>; 67963944891SThierry Reding resets = <&bpmp TEGRA234_RESET_SDMMC4>; 68063944891SThierry Reding reset-names = "sdhci"; 6816de481e5SThierry Reding interconnects = <&mc TEGRA234_MEMORY_CLIENT_SDMMCRAB &emc>, 6826de481e5SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_SDMMCWAB &emc>; 6836de481e5SThierry Reding interconnect-names = "dma-mem", "write"; 6845710e16aSThierry Reding iommus = <&smmu_niso1 TEGRA234_SID_SDMMC4>; 685e086d82dSMikko Perttunen nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 686e086d82dSMikko Perttunen nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 687e086d82dSMikko Perttunen nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 688e086d82dSMikko Perttunen nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; 689e086d82dSMikko Perttunen nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 690e086d82dSMikko Perttunen nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>; 691e086d82dSMikko Perttunen nvidia,default-tap = <0x8>; 692e086d82dSMikko Perttunen nvidia,default-trim = <0x14>; 693e086d82dSMikko Perttunen nvidia,dqs-trim = <40>; 694e086d82dSMikko Perttunen supports-cqe; 69563944891SThierry Reding status = "disabled"; 69663944891SThierry Reding }; 69763944891SThierry Reding 69863944891SThierry Reding fuse@3810000 { 69963944891SThierry Reding compatible = "nvidia,tegra234-efuse"; 70063944891SThierry Reding reg = <0x03810000 0x10000>; 70163944891SThierry Reding clocks = <&bpmp TEGRA234_CLK_FUSE>; 70263944891SThierry Reding clock-names = "fuse"; 70363944891SThierry Reding }; 70463944891SThierry Reding 70563944891SThierry Reding hsp_top0: hsp@3c00000 { 70663944891SThierry Reding compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; 70763944891SThierry Reding reg = <0x03c00000 0xa0000>; 70863944891SThierry Reding interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 70963944891SThierry Reding <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 71063944891SThierry Reding <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 71163944891SThierry Reding <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 71263944891SThierry Reding <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 71363944891SThierry Reding <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 71463944891SThierry Reding <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 71563944891SThierry Reding <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 71663944891SThierry Reding <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 71763944891SThierry Reding interrupt-names = "doorbell", "shared0", "shared1", "shared2", 71863944891SThierry Reding "shared3", "shared4", "shared5", "shared6", 71963944891SThierry Reding "shared7"; 72063944891SThierry Reding #mbox-cells = <2>; 72163944891SThierry Reding }; 72263944891SThierry Reding 7235710e16aSThierry Reding smmu_niso1: iommu@8000000 { 7245710e16aSThierry Reding compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; 7255710e16aSThierry Reding reg = <0x8000000 0x1000000>, 7265710e16aSThierry Reding <0x7000000 0x1000000>; 7275710e16aSThierry Reding interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 7285710e16aSThierry Reding <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, 7295710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 7305710e16aSThierry Reding <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, 7315710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 7325710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 7335710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 7345710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 7355710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 7365710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 7375710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 7385710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 7395710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 7405710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 7415710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 7425710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 7435710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 7445710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 7455710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 7465710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 7475710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 7485710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 7495710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 7505710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 7515710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 7525710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 7535710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 7545710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 7555710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 7565710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 7575710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 7585710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 7595710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 7605710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 7615710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 7625710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 7635710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 7645710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 7655710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 7665710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 7675710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 7685710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 7695710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 7705710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 7715710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 7725710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 7735710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 7745710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 7755710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 7765710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 7775710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 7785710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 7795710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 7805710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 7815710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 7825710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 7835710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 7845710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 7855710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 7865710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 7875710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 7885710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 7895710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 7905710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 7915710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 7925710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 7935710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 7945710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 7955710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 7965710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 7975710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 7985710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 7995710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8005710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8015710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8025710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8035710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8045710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8055710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8065710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8075710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8085710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8095710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8105710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8115710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8125710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8135710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8145710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8155710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8165710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8175710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8185710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8195710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8205710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8215710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8225710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8235710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8245710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8255710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8265710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8275710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8285710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8295710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8305710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8315710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8325710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8335710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8345710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8355710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8365710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8375710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8385710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8395710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8405710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8415710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8425710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8435710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8445710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8455710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8465710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8475710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8485710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8495710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8505710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8515710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8525710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8535710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8545710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8555710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8565710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 8575710e16aSThierry Reding stream-match-mask = <0x7f80>; 8585710e16aSThierry Reding #global-interrupts = <2>; 8595710e16aSThierry Reding #iommu-cells = <1>; 8605710e16aSThierry Reding 8615710e16aSThierry Reding nvidia,memory-controller = <&mc>; 8625710e16aSThierry Reding status = "okay"; 8635710e16aSThierry Reding }; 8645710e16aSThierry Reding 86563944891SThierry Reding hsp_aon: hsp@c150000 { 86663944891SThierry Reding compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; 86763944891SThierry Reding reg = <0x0c150000 0x90000>; 86863944891SThierry Reding interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 86963944891SThierry Reding <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 87063944891SThierry Reding <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 87163944891SThierry Reding <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 87263944891SThierry Reding /* 87363944891SThierry Reding * Shared interrupt 0 is routed only to AON/SPE, so 87463944891SThierry Reding * we only have 4 shared interrupts for the CCPLEX. 87563944891SThierry Reding */ 87663944891SThierry Reding interrupt-names = "shared1", "shared2", "shared3", "shared4"; 87763944891SThierry Reding #mbox-cells = <2>; 87863944891SThierry Reding }; 87963944891SThierry Reding 880156af9deSAkhil R gen2_i2c: i2c@c240000 { 881156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 882156af9deSAkhil R reg = <0xc240000 0x100>; 883156af9deSAkhil R interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 884156af9deSAkhil R status = "disabled"; 885156af9deSAkhil R clock-frequency = <100000>; 886156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C2 887156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 888156af9deSAkhil R clock-names = "div-clk", "parent"; 889156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C2>; 890156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 891156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C2>; 892156af9deSAkhil R reset-names = "i2c"; 893156af9deSAkhil R }; 894156af9deSAkhil R 895156af9deSAkhil R gen8_i2c: i2c@c250000 { 896156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 897156af9deSAkhil R reg = <0xc250000 0x100>; 898156af9deSAkhil R nvidia,hw-instance-id = <0x7>; 899156af9deSAkhil R interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 900156af9deSAkhil R status = "disabled"; 901156af9deSAkhil R clock-frequency = <400000>; 902156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C8 903156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 904156af9deSAkhil R clock-names = "div-clk", "parent"; 905156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C8>; 906156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 907156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C8>; 908156af9deSAkhil R reset-names = "i2c"; 909156af9deSAkhil R }; 910156af9deSAkhil R 91163944891SThierry Reding rtc@c2a0000 { 91263944891SThierry Reding compatible = "nvidia,tegra234-rtc", "nvidia,tegra20-rtc"; 91363944891SThierry Reding reg = <0x0c2a0000 0x10000>; 91463944891SThierry Reding interrupt-parent = <&pmc>; 91563944891SThierry Reding interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 916e537addeSMikko Perttunen clocks = <&bpmp TEGRA234_CLK_CLK_32K>; 917e537addeSMikko Perttunen clock-names = "rtc"; 91863944891SThierry Reding status = "disabled"; 91963944891SThierry Reding }; 92063944891SThierry Reding 921f0e12668SThierry Reding gpio_aon: gpio@c2f0000 { 922f0e12668SThierry Reding compatible = "nvidia,tegra234-gpio-aon"; 923f0e12668SThierry Reding reg-names = "security", "gpio"; 924f0e12668SThierry Reding reg = <0x0c2f0000 0x1000>, 925f0e12668SThierry Reding <0x0c2f1000 0x1000>; 926f0e12668SThierry Reding interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 927f0e12668SThierry Reding <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 928f0e12668SThierry Reding <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 929f0e12668SThierry Reding <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 930f0e12668SThierry Reding #interrupt-cells = <2>; 931f0e12668SThierry Reding interrupt-controller; 932f0e12668SThierry Reding #gpio-cells = <2>; 933f0e12668SThierry Reding gpio-controller; 934f0e12668SThierry Reding }; 935f0e12668SThierry Reding 93663944891SThierry Reding pmc: pmc@c360000 { 93763944891SThierry Reding compatible = "nvidia,tegra234-pmc"; 93863944891SThierry Reding reg = <0x0c360000 0x10000>, 93963944891SThierry Reding <0x0c370000 0x10000>, 94063944891SThierry Reding <0x0c380000 0x10000>, 94163944891SThierry Reding <0x0c390000 0x10000>, 94263944891SThierry Reding <0x0c3a0000 0x10000>; 94363944891SThierry Reding reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 94463944891SThierry Reding 94563944891SThierry Reding #interrupt-cells = <2>; 94663944891SThierry Reding interrupt-controller; 94763944891SThierry Reding }; 94863944891SThierry Reding 94963944891SThierry Reding gic: interrupt-controller@f400000 { 95063944891SThierry Reding compatible = "arm,gic-v3"; 95163944891SThierry Reding reg = <0x0f400000 0x010000>, /* GICD */ 95263944891SThierry Reding <0x0f440000 0x200000>; /* GICR */ 95363944891SThierry Reding interrupt-parent = <&gic>; 95463944891SThierry Reding interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 95563944891SThierry Reding 95663944891SThierry Reding #redistributor-regions = <1>; 95763944891SThierry Reding #interrupt-cells = <3>; 95863944891SThierry Reding interrupt-controller; 95963944891SThierry Reding }; 9605710e16aSThierry Reding 9615710e16aSThierry Reding smmu_iso: iommu@10000000{ 9625710e16aSThierry Reding compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; 9635710e16aSThierry Reding reg = <0x10000000 0x1000000>; 9645710e16aSThierry Reding interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 9655710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 9665710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 9675710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 9685710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 9695710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 9705710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 9715710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 9725710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 9735710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 9745710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 9755710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 9765710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 9775710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 9785710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 9795710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 9805710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 9815710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 9825710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 9835710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 9845710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 9855710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 9865710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 9875710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 9885710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 9895710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 9905710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 9915710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 9925710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 9935710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 9945710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 9955710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 9965710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 9975710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 9985710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 9995710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10005710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10015710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10025710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10035710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10045710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10055710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10065710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10075710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10085710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10095710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10105710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10115710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10125710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10135710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10145710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10155710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10165710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10175710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10185710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10195710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10205710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10215710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10225710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10235710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10245710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10255710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10265710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10275710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10285710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10295710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10305710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10315710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10325710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10335710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10345710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10355710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10365710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10375710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10385710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10395710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10405710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10415710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10425710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10435710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10445710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10455710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10465710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10475710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10485710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10495710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10505710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10515710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10525710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10535710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10545710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10555710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10565710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10575710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10585710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10595710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10605710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10615710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10625710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10635710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10645710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10655710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10665710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10675710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10685710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10695710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10705710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10715710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10725710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10735710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10745710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10755710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10765710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10775710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10785710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10795710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10805710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10815710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10825710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10835710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10845710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10855710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10865710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10875710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10885710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10895710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10905710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10915710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10925710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 10935710e16aSThierry Reding stream-match-mask = <0x7f80>; 10945710e16aSThierry Reding #global-interrupts = <1>; 10955710e16aSThierry Reding #iommu-cells = <1>; 10965710e16aSThierry Reding 10975710e16aSThierry Reding nvidia,memory-controller = <&mc>; 10985710e16aSThierry Reding status = "okay"; 10995710e16aSThierry Reding }; 11005710e16aSThierry Reding 11015710e16aSThierry Reding smmu_niso0: iommu@12000000 { 11025710e16aSThierry Reding compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; 11035710e16aSThierry Reding reg = <0x12000000 0x1000000>, 11045710e16aSThierry Reding <0x11000000 0x1000000>; 11055710e16aSThierry Reding interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11065710e16aSThierry Reding <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 11075710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11085710e16aSThierry Reding <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 11095710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11105710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11115710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11125710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11135710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11145710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11155710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11165710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11175710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11185710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11195710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11205710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11215710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11225710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11235710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11245710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11255710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11265710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11275710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11285710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11295710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11305710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11315710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11325710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11335710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11345710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11355710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11365710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11375710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11385710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11395710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11405710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11415710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11425710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11435710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11445710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11455710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11465710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11475710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11485710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11495710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11505710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11515710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11525710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11535710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11545710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11555710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11565710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11575710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11585710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11595710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11605710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11615710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11625710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11635710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11645710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11655710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11665710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11675710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11685710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11695710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11705710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11715710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11725710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11735710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11745710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11755710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11765710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11775710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11785710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11795710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11805710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11815710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11825710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11835710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11845710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11855710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11865710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11875710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11885710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11895710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11905710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11915710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11925710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11935710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11945710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11955710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11965710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11975710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11985710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11995710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12005710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12015710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12025710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12035710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12045710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12055710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12065710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12075710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12085710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12095710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12105710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12115710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12125710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12135710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12145710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12155710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12165710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12175710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12185710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12195710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12205710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12215710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12225710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12235710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12245710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12255710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12265710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12275710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12285710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12295710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12305710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12315710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12325710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12335710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12345710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 12355710e16aSThierry Reding stream-match-mask = <0x7f80>; 12365710e16aSThierry Reding #global-interrupts = <2>; 12375710e16aSThierry Reding #iommu-cells = <1>; 12385710e16aSThierry Reding 12395710e16aSThierry Reding nvidia,memory-controller = <&mc>; 12405710e16aSThierry Reding status = "okay"; 12415710e16aSThierry Reding }; 124263944891SThierry Reding }; 124363944891SThierry Reding 12447fa30752SThierry Reding sram@40000000 { 124563944891SThierry Reding compatible = "nvidia,tegra234-sysram", "mmio-sram"; 124698094be1SMikko Perttunen reg = <0x0 0x40000000 0x0 0x80000>; 124763944891SThierry Reding #address-cells = <1>; 124863944891SThierry Reding #size-cells = <1>; 124998094be1SMikko Perttunen ranges = <0x0 0x0 0x40000000 0x80000>; 125063944891SThierry Reding 125198094be1SMikko Perttunen cpu_bpmp_tx: sram@70000 { 125298094be1SMikko Perttunen reg = <0x70000 0x1000>; 125363944891SThierry Reding label = "cpu-bpmp-tx"; 125463944891SThierry Reding pool; 125563944891SThierry Reding }; 125663944891SThierry Reding 125798094be1SMikko Perttunen cpu_bpmp_rx: sram@71000 { 125898094be1SMikko Perttunen reg = <0x71000 0x1000>; 125963944891SThierry Reding label = "cpu-bpmp-rx"; 126063944891SThierry Reding pool; 126163944891SThierry Reding }; 126263944891SThierry Reding }; 126363944891SThierry Reding 126463944891SThierry Reding bpmp: bpmp { 126563944891SThierry Reding compatible = "nvidia,tegra234-bpmp", "nvidia,tegra186-bpmp"; 126663944891SThierry Reding mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 126763944891SThierry Reding TEGRA_HSP_DB_MASTER_BPMP>; 12687fa30752SThierry Reding shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; 126963944891SThierry Reding #clock-cells = <1>; 127063944891SThierry Reding #reset-cells = <1>; 127163944891SThierry Reding #power-domain-cells = <1>; 12726de481e5SThierry Reding interconnects = <&mc TEGRA234_MEMORY_CLIENT_BPMPR &emc>, 12736de481e5SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_BPMPW &emc>, 12746de481e5SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAR &emc>, 12756de481e5SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAW &emc>; 12766de481e5SThierry Reding interconnect-names = "read", "write", "dma-mem", "dma-write"; 12775710e16aSThierry Reding iommus = <&smmu_niso1 TEGRA234_SID_BPMP>; 127863944891SThierry Reding 127963944891SThierry Reding bpmp_i2c: i2c { 128063944891SThierry Reding compatible = "nvidia,tegra186-bpmp-i2c"; 128163944891SThierry Reding nvidia,bpmp-bus-id = <5>; 128263944891SThierry Reding #address-cells = <1>; 128363944891SThierry Reding #size-cells = <0>; 128463944891SThierry Reding }; 128563944891SThierry Reding }; 128663944891SThierry Reding 128763944891SThierry Reding cpus { 128863944891SThierry Reding #address-cells = <1>; 128963944891SThierry Reding #size-cells = <0>; 129063944891SThierry Reding 1291a12cf5c3SThierry Reding cpu0_0: cpu@0 { 1292a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 129363944891SThierry Reding device_type = "cpu"; 1294a12cf5c3SThierry Reding reg = <0x00000>; 129563944891SThierry Reding 129663944891SThierry Reding enable-method = "psci"; 1297a12cf5c3SThierry Reding 1298a12cf5c3SThierry Reding i-cache-size = <65536>; 1299a12cf5c3SThierry Reding i-cache-line-size = <64>; 1300a12cf5c3SThierry Reding i-cache-sets = <256>; 1301a12cf5c3SThierry Reding d-cache-size = <65536>; 1302a12cf5c3SThierry Reding d-cache-line-size = <64>; 1303a12cf5c3SThierry Reding d-cache-sets = <256>; 1304a12cf5c3SThierry Reding next-level-cache = <&l2c0_0>; 130563944891SThierry Reding }; 1306a12cf5c3SThierry Reding 1307a12cf5c3SThierry Reding cpu0_1: cpu@100 { 1308a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 1309a12cf5c3SThierry Reding device_type = "cpu"; 1310a12cf5c3SThierry Reding reg = <0x00100>; 1311a12cf5c3SThierry Reding 1312a12cf5c3SThierry Reding enable-method = "psci"; 1313a12cf5c3SThierry Reding 1314a12cf5c3SThierry Reding i-cache-size = <65536>; 1315a12cf5c3SThierry Reding i-cache-line-size = <64>; 1316a12cf5c3SThierry Reding i-cache-sets = <256>; 1317a12cf5c3SThierry Reding d-cache-size = <65536>; 1318a12cf5c3SThierry Reding d-cache-line-size = <64>; 1319a12cf5c3SThierry Reding d-cache-sets = <256>; 1320a12cf5c3SThierry Reding next-level-cache = <&l2c0_1>; 1321a12cf5c3SThierry Reding }; 1322a12cf5c3SThierry Reding 1323a12cf5c3SThierry Reding cpu0_2: cpu@200 { 1324a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 1325a12cf5c3SThierry Reding device_type = "cpu"; 1326a12cf5c3SThierry Reding reg = <0x00200>; 1327a12cf5c3SThierry Reding 1328a12cf5c3SThierry Reding enable-method = "psci"; 1329a12cf5c3SThierry Reding 1330a12cf5c3SThierry Reding i-cache-size = <65536>; 1331a12cf5c3SThierry Reding i-cache-line-size = <64>; 1332a12cf5c3SThierry Reding i-cache-sets = <256>; 1333a12cf5c3SThierry Reding d-cache-size = <65536>; 1334a12cf5c3SThierry Reding d-cache-line-size = <64>; 1335a12cf5c3SThierry Reding d-cache-sets = <256>; 1336a12cf5c3SThierry Reding next-level-cache = <&l2c0_2>; 1337a12cf5c3SThierry Reding }; 1338a12cf5c3SThierry Reding 1339a12cf5c3SThierry Reding cpu0_3: cpu@300 { 1340a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 1341a12cf5c3SThierry Reding device_type = "cpu"; 1342a12cf5c3SThierry Reding reg = <0x00300>; 1343a12cf5c3SThierry Reding 1344a12cf5c3SThierry Reding enable-method = "psci"; 1345a12cf5c3SThierry Reding 1346a12cf5c3SThierry Reding i-cache-size = <65536>; 1347a12cf5c3SThierry Reding i-cache-line-size = <64>; 1348a12cf5c3SThierry Reding i-cache-sets = <256>; 1349a12cf5c3SThierry Reding d-cache-size = <65536>; 1350a12cf5c3SThierry Reding d-cache-line-size = <64>; 1351a12cf5c3SThierry Reding d-cache-sets = <256>; 1352a12cf5c3SThierry Reding next-level-cache = <&l2c0_3>; 1353a12cf5c3SThierry Reding }; 1354a12cf5c3SThierry Reding 1355a12cf5c3SThierry Reding cpu1_0: cpu@10000 { 1356a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 1357a12cf5c3SThierry Reding device_type = "cpu"; 1358a12cf5c3SThierry Reding reg = <0x10000>; 1359a12cf5c3SThierry Reding 1360a12cf5c3SThierry Reding enable-method = "psci"; 1361a12cf5c3SThierry Reding 1362a12cf5c3SThierry Reding i-cache-size = <65536>; 1363a12cf5c3SThierry Reding i-cache-line-size = <64>; 1364a12cf5c3SThierry Reding i-cache-sets = <256>; 1365a12cf5c3SThierry Reding d-cache-size = <65536>; 1366a12cf5c3SThierry Reding d-cache-line-size = <64>; 1367a12cf5c3SThierry Reding d-cache-sets = <256>; 1368a12cf5c3SThierry Reding next-level-cache = <&l2c1_0>; 1369a12cf5c3SThierry Reding }; 1370a12cf5c3SThierry Reding 1371a12cf5c3SThierry Reding cpu1_1: cpu@10100 { 1372a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 1373a12cf5c3SThierry Reding device_type = "cpu"; 1374a12cf5c3SThierry Reding reg = <0x10100>; 1375a12cf5c3SThierry Reding 1376a12cf5c3SThierry Reding enable-method = "psci"; 1377a12cf5c3SThierry Reding 1378a12cf5c3SThierry Reding i-cache-size = <65536>; 1379a12cf5c3SThierry Reding i-cache-line-size = <64>; 1380a12cf5c3SThierry Reding i-cache-sets = <256>; 1381a12cf5c3SThierry Reding d-cache-size = <65536>; 1382a12cf5c3SThierry Reding d-cache-line-size = <64>; 1383a12cf5c3SThierry Reding d-cache-sets = <256>; 1384a12cf5c3SThierry Reding next-level-cache = <&l2c1_1>; 1385a12cf5c3SThierry Reding }; 1386a12cf5c3SThierry Reding 1387a12cf5c3SThierry Reding cpu1_2: cpu@10200 { 1388a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 1389a12cf5c3SThierry Reding device_type = "cpu"; 1390a12cf5c3SThierry Reding reg = <0x10200>; 1391a12cf5c3SThierry Reding 1392a12cf5c3SThierry Reding enable-method = "psci"; 1393a12cf5c3SThierry Reding 1394a12cf5c3SThierry Reding i-cache-size = <65536>; 1395a12cf5c3SThierry Reding i-cache-line-size = <64>; 1396a12cf5c3SThierry Reding i-cache-sets = <256>; 1397a12cf5c3SThierry Reding d-cache-size = <65536>; 1398a12cf5c3SThierry Reding d-cache-line-size = <64>; 1399a12cf5c3SThierry Reding d-cache-sets = <256>; 1400a12cf5c3SThierry Reding next-level-cache = <&l2c1_2>; 1401a12cf5c3SThierry Reding }; 1402a12cf5c3SThierry Reding 1403a12cf5c3SThierry Reding cpu1_3: cpu@10300 { 1404a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 1405a12cf5c3SThierry Reding device_type = "cpu"; 1406a12cf5c3SThierry Reding reg = <0x10300>; 1407a12cf5c3SThierry Reding 1408a12cf5c3SThierry Reding enable-method = "psci"; 1409a12cf5c3SThierry Reding 1410a12cf5c3SThierry Reding i-cache-size = <65536>; 1411a12cf5c3SThierry Reding i-cache-line-size = <64>; 1412a12cf5c3SThierry Reding i-cache-sets = <256>; 1413a12cf5c3SThierry Reding d-cache-size = <65536>; 1414a12cf5c3SThierry Reding d-cache-line-size = <64>; 1415a12cf5c3SThierry Reding d-cache-sets = <256>; 1416a12cf5c3SThierry Reding next-level-cache = <&l2c1_3>; 1417a12cf5c3SThierry Reding }; 1418a12cf5c3SThierry Reding 1419a12cf5c3SThierry Reding cpu2_0: cpu@20000 { 1420a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 1421a12cf5c3SThierry Reding device_type = "cpu"; 1422a12cf5c3SThierry Reding reg = <0x20000>; 1423a12cf5c3SThierry Reding 1424a12cf5c3SThierry Reding enable-method = "psci"; 1425a12cf5c3SThierry Reding 1426a12cf5c3SThierry Reding i-cache-size = <65536>; 1427a12cf5c3SThierry Reding i-cache-line-size = <64>; 1428a12cf5c3SThierry Reding i-cache-sets = <256>; 1429a12cf5c3SThierry Reding d-cache-size = <65536>; 1430a12cf5c3SThierry Reding d-cache-line-size = <64>; 1431a12cf5c3SThierry Reding d-cache-sets = <256>; 1432a12cf5c3SThierry Reding next-level-cache = <&l2c2_0>; 1433a12cf5c3SThierry Reding }; 1434a12cf5c3SThierry Reding 1435a12cf5c3SThierry Reding cpu2_1: cpu@20100 { 1436a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 1437a12cf5c3SThierry Reding device_type = "cpu"; 1438a12cf5c3SThierry Reding reg = <0x20100>; 1439a12cf5c3SThierry Reding 1440a12cf5c3SThierry Reding enable-method = "psci"; 1441a12cf5c3SThierry Reding 1442a12cf5c3SThierry Reding i-cache-size = <65536>; 1443a12cf5c3SThierry Reding i-cache-line-size = <64>; 1444a12cf5c3SThierry Reding i-cache-sets = <256>; 1445a12cf5c3SThierry Reding d-cache-size = <65536>; 1446a12cf5c3SThierry Reding d-cache-line-size = <64>; 1447a12cf5c3SThierry Reding d-cache-sets = <256>; 1448a12cf5c3SThierry Reding next-level-cache = <&l2c2_1>; 1449a12cf5c3SThierry Reding }; 1450a12cf5c3SThierry Reding 1451a12cf5c3SThierry Reding cpu2_2: cpu@20200 { 1452a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 1453a12cf5c3SThierry Reding device_type = "cpu"; 1454a12cf5c3SThierry Reding reg = <0x20200>; 1455a12cf5c3SThierry Reding 1456a12cf5c3SThierry Reding enable-method = "psci"; 1457a12cf5c3SThierry Reding 1458a12cf5c3SThierry Reding i-cache-size = <65536>; 1459a12cf5c3SThierry Reding i-cache-line-size = <64>; 1460a12cf5c3SThierry Reding i-cache-sets = <256>; 1461a12cf5c3SThierry Reding d-cache-size = <65536>; 1462a12cf5c3SThierry Reding d-cache-line-size = <64>; 1463a12cf5c3SThierry Reding d-cache-sets = <256>; 1464a12cf5c3SThierry Reding next-level-cache = <&l2c2_2>; 1465a12cf5c3SThierry Reding }; 1466a12cf5c3SThierry Reding 1467a12cf5c3SThierry Reding cpu2_3: cpu@20300 { 1468a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 1469a12cf5c3SThierry Reding device_type = "cpu"; 1470a12cf5c3SThierry Reding reg = <0x20300>; 1471a12cf5c3SThierry Reding 1472a12cf5c3SThierry Reding enable-method = "psci"; 1473a12cf5c3SThierry Reding 1474a12cf5c3SThierry Reding i-cache-size = <65536>; 1475a12cf5c3SThierry Reding i-cache-line-size = <64>; 1476a12cf5c3SThierry Reding i-cache-sets = <256>; 1477a12cf5c3SThierry Reding d-cache-size = <65536>; 1478a12cf5c3SThierry Reding d-cache-line-size = <64>; 1479a12cf5c3SThierry Reding d-cache-sets = <256>; 1480a12cf5c3SThierry Reding next-level-cache = <&l2c2_3>; 1481a12cf5c3SThierry Reding }; 1482a12cf5c3SThierry Reding 1483a12cf5c3SThierry Reding cpu-map { 1484a12cf5c3SThierry Reding cluster0 { 1485a12cf5c3SThierry Reding core0 { 1486a12cf5c3SThierry Reding cpu = <&cpu0_0>; 1487a12cf5c3SThierry Reding }; 1488a12cf5c3SThierry Reding 1489a12cf5c3SThierry Reding core1 { 1490a12cf5c3SThierry Reding cpu = <&cpu0_1>; 1491a12cf5c3SThierry Reding }; 1492a12cf5c3SThierry Reding 1493a12cf5c3SThierry Reding core2 { 1494a12cf5c3SThierry Reding cpu = <&cpu0_2>; 1495a12cf5c3SThierry Reding }; 1496a12cf5c3SThierry Reding 1497a12cf5c3SThierry Reding core3 { 1498a12cf5c3SThierry Reding cpu = <&cpu0_3>; 1499a12cf5c3SThierry Reding }; 1500a12cf5c3SThierry Reding }; 1501a12cf5c3SThierry Reding 1502a12cf5c3SThierry Reding cluster1 { 1503a12cf5c3SThierry Reding core0 { 1504a12cf5c3SThierry Reding cpu = <&cpu1_0>; 1505a12cf5c3SThierry Reding }; 1506a12cf5c3SThierry Reding 1507a12cf5c3SThierry Reding core1 { 1508a12cf5c3SThierry Reding cpu = <&cpu1_1>; 1509a12cf5c3SThierry Reding }; 1510a12cf5c3SThierry Reding 1511a12cf5c3SThierry Reding core2 { 1512a12cf5c3SThierry Reding cpu = <&cpu1_2>; 1513a12cf5c3SThierry Reding }; 1514a12cf5c3SThierry Reding 1515a12cf5c3SThierry Reding core3 { 1516a12cf5c3SThierry Reding cpu = <&cpu1_3>; 1517a12cf5c3SThierry Reding }; 1518a12cf5c3SThierry Reding }; 1519a12cf5c3SThierry Reding 1520a12cf5c3SThierry Reding cluster2 { 1521a12cf5c3SThierry Reding core0 { 1522a12cf5c3SThierry Reding cpu = <&cpu2_0>; 1523a12cf5c3SThierry Reding }; 1524a12cf5c3SThierry Reding 1525a12cf5c3SThierry Reding core1 { 1526a12cf5c3SThierry Reding cpu = <&cpu2_1>; 1527a12cf5c3SThierry Reding }; 1528a12cf5c3SThierry Reding 1529a12cf5c3SThierry Reding core2 { 1530a12cf5c3SThierry Reding cpu = <&cpu2_2>; 1531a12cf5c3SThierry Reding }; 1532a12cf5c3SThierry Reding 1533a12cf5c3SThierry Reding core3 { 1534a12cf5c3SThierry Reding cpu = <&cpu2_3>; 1535a12cf5c3SThierry Reding }; 1536a12cf5c3SThierry Reding }; 1537a12cf5c3SThierry Reding }; 1538a12cf5c3SThierry Reding 1539a12cf5c3SThierry Reding l2c0_0: l2-cache00 { 1540a12cf5c3SThierry Reding cache-size = <262144>; 1541a12cf5c3SThierry Reding cache-line-size = <64>; 1542a12cf5c3SThierry Reding cache-sets = <512>; 1543a12cf5c3SThierry Reding cache-unified; 1544a12cf5c3SThierry Reding next-level-cache = <&l3c0>; 1545a12cf5c3SThierry Reding }; 1546a12cf5c3SThierry Reding 1547a12cf5c3SThierry Reding l2c0_1: l2-cache01 { 1548a12cf5c3SThierry Reding cache-size = <262144>; 1549a12cf5c3SThierry Reding cache-line-size = <64>; 1550a12cf5c3SThierry Reding cache-sets = <512>; 1551a12cf5c3SThierry Reding cache-unified; 1552a12cf5c3SThierry Reding next-level-cache = <&l3c0>; 1553a12cf5c3SThierry Reding }; 1554a12cf5c3SThierry Reding 1555a12cf5c3SThierry Reding l2c0_2: l2-cache02 { 1556a12cf5c3SThierry Reding cache-size = <262144>; 1557a12cf5c3SThierry Reding cache-line-size = <64>; 1558a12cf5c3SThierry Reding cache-sets = <512>; 1559a12cf5c3SThierry Reding cache-unified; 1560a12cf5c3SThierry Reding next-level-cache = <&l3c0>; 1561a12cf5c3SThierry Reding }; 1562a12cf5c3SThierry Reding 1563a12cf5c3SThierry Reding l2c0_3: l2-cache03 { 1564a12cf5c3SThierry Reding cache-size = <262144>; 1565a12cf5c3SThierry Reding cache-line-size = <64>; 1566a12cf5c3SThierry Reding cache-sets = <512>; 1567a12cf5c3SThierry Reding cache-unified; 1568a12cf5c3SThierry Reding next-level-cache = <&l3c0>; 1569a12cf5c3SThierry Reding }; 1570a12cf5c3SThierry Reding 1571a12cf5c3SThierry Reding l2c1_0: l2-cache10 { 1572a12cf5c3SThierry Reding cache-size = <262144>; 1573a12cf5c3SThierry Reding cache-line-size = <64>; 1574a12cf5c3SThierry Reding cache-sets = <512>; 1575a12cf5c3SThierry Reding cache-unified; 1576a12cf5c3SThierry Reding next-level-cache = <&l3c1>; 1577a12cf5c3SThierry Reding }; 1578a12cf5c3SThierry Reding 1579a12cf5c3SThierry Reding l2c1_1: l2-cache11 { 1580a12cf5c3SThierry Reding cache-size = <262144>; 1581a12cf5c3SThierry Reding cache-line-size = <64>; 1582a12cf5c3SThierry Reding cache-sets = <512>; 1583a12cf5c3SThierry Reding cache-unified; 1584a12cf5c3SThierry Reding next-level-cache = <&l3c1>; 1585a12cf5c3SThierry Reding }; 1586a12cf5c3SThierry Reding 1587a12cf5c3SThierry Reding l2c1_2: l2-cache12 { 1588a12cf5c3SThierry Reding cache-size = <262144>; 1589a12cf5c3SThierry Reding cache-line-size = <64>; 1590a12cf5c3SThierry Reding cache-sets = <512>; 1591a12cf5c3SThierry Reding cache-unified; 1592a12cf5c3SThierry Reding next-level-cache = <&l3c1>; 1593a12cf5c3SThierry Reding }; 1594a12cf5c3SThierry Reding 1595a12cf5c3SThierry Reding l2c1_3: l2-cache13 { 1596a12cf5c3SThierry Reding cache-size = <262144>; 1597a12cf5c3SThierry Reding cache-line-size = <64>; 1598a12cf5c3SThierry Reding cache-sets = <512>; 1599a12cf5c3SThierry Reding cache-unified; 1600a12cf5c3SThierry Reding next-level-cache = <&l3c1>; 1601a12cf5c3SThierry Reding }; 1602a12cf5c3SThierry Reding 1603a12cf5c3SThierry Reding l2c2_0: l2-cache20 { 1604a12cf5c3SThierry Reding cache-size = <262144>; 1605a12cf5c3SThierry Reding cache-line-size = <64>; 1606a12cf5c3SThierry Reding cache-sets = <512>; 1607a12cf5c3SThierry Reding cache-unified; 1608a12cf5c3SThierry Reding next-level-cache = <&l3c2>; 1609a12cf5c3SThierry Reding }; 1610a12cf5c3SThierry Reding 1611a12cf5c3SThierry Reding l2c2_1: l2-cache21 { 1612a12cf5c3SThierry Reding cache-size = <262144>; 1613a12cf5c3SThierry Reding cache-line-size = <64>; 1614a12cf5c3SThierry Reding cache-sets = <512>; 1615a12cf5c3SThierry Reding cache-unified; 1616a12cf5c3SThierry Reding next-level-cache = <&l3c2>; 1617a12cf5c3SThierry Reding }; 1618a12cf5c3SThierry Reding 1619a12cf5c3SThierry Reding l2c2_2: l2-cache22 { 1620a12cf5c3SThierry Reding cache-size = <262144>; 1621a12cf5c3SThierry Reding cache-line-size = <64>; 1622a12cf5c3SThierry Reding cache-sets = <512>; 1623a12cf5c3SThierry Reding cache-unified; 1624a12cf5c3SThierry Reding next-level-cache = <&l3c2>; 1625a12cf5c3SThierry Reding }; 1626a12cf5c3SThierry Reding 1627a12cf5c3SThierry Reding l2c2_3: l2-cache23 { 1628a12cf5c3SThierry Reding cache-size = <262144>; 1629a12cf5c3SThierry Reding cache-line-size = <64>; 1630a12cf5c3SThierry Reding cache-sets = <512>; 1631a12cf5c3SThierry Reding cache-unified; 1632a12cf5c3SThierry Reding next-level-cache = <&l3c2>; 1633a12cf5c3SThierry Reding }; 1634a12cf5c3SThierry Reding 1635a12cf5c3SThierry Reding l3c0: l3-cache0 { 1636a12cf5c3SThierry Reding cache-size = <2097152>; 1637a12cf5c3SThierry Reding cache-line-size = <64>; 1638a12cf5c3SThierry Reding cache-sets = <2048>; 1639a12cf5c3SThierry Reding }; 1640a12cf5c3SThierry Reding 1641a12cf5c3SThierry Reding l3c1: l3-cache1 { 1642a12cf5c3SThierry Reding cache-size = <2097152>; 1643a12cf5c3SThierry Reding cache-line-size = <64>; 1644a12cf5c3SThierry Reding cache-sets = <2048>; 1645a12cf5c3SThierry Reding }; 1646a12cf5c3SThierry Reding 1647a12cf5c3SThierry Reding l3c2: l3-cache2 { 1648a12cf5c3SThierry Reding cache-size = <2097152>; 1649a12cf5c3SThierry Reding cache-line-size = <64>; 1650a12cf5c3SThierry Reding cache-sets = <2048>; 1651a12cf5c3SThierry Reding }; 1652a12cf5c3SThierry Reding }; 1653a12cf5c3SThierry Reding 1654a12cf5c3SThierry Reding pmu { 1655a12cf5c3SThierry Reding compatible = "arm,cortex-a78-pmu"; 1656a12cf5c3SThierry Reding interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 1657a12cf5c3SThierry Reding status = "okay"; 165863944891SThierry Reding }; 165963944891SThierry Reding 166063944891SThierry Reding psci { 166163944891SThierry Reding compatible = "arm,psci-1.0"; 166263944891SThierry Reding status = "okay"; 166363944891SThierry Reding method = "smc"; 166463944891SThierry Reding }; 166563944891SThierry Reding 166606ad2ec4SMikko Perttunen tcu: serial { 166706ad2ec4SMikko Perttunen compatible = "nvidia,tegra234-tcu", "nvidia,tegra194-tcu"; 166806ad2ec4SMikko Perttunen mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 166906ad2ec4SMikko Perttunen <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 167006ad2ec4SMikko Perttunen mbox-names = "rx", "tx"; 167106ad2ec4SMikko Perttunen status = "disabled"; 167206ad2ec4SMikko Perttunen }; 167306ad2ec4SMikko Perttunen 167463944891SThierry Reding timer { 167563944891SThierry Reding compatible = "arm,armv8-timer"; 167663944891SThierry Reding interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 167763944891SThierry Reding <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 167863944891SThierry Reding <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 167963944891SThierry Reding <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 168063944891SThierry Reding interrupt-parent = <&gic>; 168163944891SThierry Reding always-on; 168263944891SThierry Reding }; 168363944891SThierry Reding}; 1684