163944891SThierry Reding// SPDX-License-Identifier: GPL-2.0 263944891SThierry Reding 363944891SThierry Reding#include <dt-bindings/clock/tegra234-clock.h> 4699349e0SThierry Reding#include <dt-bindings/gpio/tegra234-gpio.h> 563944891SThierry Reding#include <dt-bindings/interrupt-controller/arm-gic.h> 663944891SThierry Reding#include <dt-bindings/mailbox/tegra186-hsp.h> 7eed280dfSThierry Reding#include <dt-bindings/memory/tegra234-mc.h> 8dc94a94dSSameer Pujar#include <dt-bindings/power/tegra234-powergate.h> 963944891SThierry Reding#include <dt-bindings/reset/tegra234-reset.h> 1063944891SThierry Reding 1163944891SThierry Reding/ { 1263944891SThierry Reding compatible = "nvidia,tegra234"; 1363944891SThierry Reding interrupt-parent = <&gic>; 1463944891SThierry Reding #address-cells = <2>; 1563944891SThierry Reding #size-cells = <2>; 1663944891SThierry Reding 1763944891SThierry Reding bus@0 { 1863944891SThierry Reding compatible = "simple-bus"; 1963944891SThierry Reding #address-cells = <1>; 2063944891SThierry Reding #size-cells = <1>; 2163944891SThierry Reding 2263944891SThierry Reding ranges = <0x0 0x0 0x0 0x40000000>; 2363944891SThierry Reding 2460d2016aSAkhil R gpcdma: dma-controller@2600000 { 25f7b93a08SAkhil R compatible = "nvidia,tegra234-gpcdma", 2660d2016aSAkhil R "nvidia,tegra186-gpcdma"; 2760d2016aSAkhil R reg = <0x2600000 0x210000>; 2860d2016aSAkhil R resets = <&bpmp TEGRA234_RESET_GPCDMA>; 2960d2016aSAkhil R reset-names = "gpcdma"; 3060d2016aSAkhil R interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 3160d2016aSAkhil R <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 3260d2016aSAkhil R <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 3360d2016aSAkhil R <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 3460d2016aSAkhil R <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 3560d2016aSAkhil R <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 3660d2016aSAkhil R <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 3760d2016aSAkhil R <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 3860d2016aSAkhil R <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 3960d2016aSAkhil R <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 4060d2016aSAkhil R <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 4160d2016aSAkhil R <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 4260d2016aSAkhil R <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 4360d2016aSAkhil R <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 4460d2016aSAkhil R <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 4560d2016aSAkhil R <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 4660d2016aSAkhil R <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 4760d2016aSAkhil R <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 4860d2016aSAkhil R <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 4960d2016aSAkhil R <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 5060d2016aSAkhil R <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 5160d2016aSAkhil R <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 5260d2016aSAkhil R <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 5360d2016aSAkhil R <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 5460d2016aSAkhil R <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 5560d2016aSAkhil R <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 5660d2016aSAkhil R <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 5760d2016aSAkhil R <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 5860d2016aSAkhil R <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 5960d2016aSAkhil R <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 6060d2016aSAkhil R <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 6160d2016aSAkhil R #dma-cells = <1>; 6260d2016aSAkhil R iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 6360d2016aSAkhil R dma-coherent; 6460d2016aSAkhil R }; 6560d2016aSAkhil R 66dc94a94dSSameer Pujar aconnect@2900000 { 67dc94a94dSSameer Pujar compatible = "nvidia,tegra234-aconnect", 68dc94a94dSSameer Pujar "nvidia,tegra210-aconnect"; 69dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_APE>, 70dc94a94dSSameer Pujar <&bpmp TEGRA234_CLK_APB2APE>; 71dc94a94dSSameer Pujar clock-names = "ape", "apb2ape"; 72dc94a94dSSameer Pujar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_AUD>; 73dc94a94dSSameer Pujar #address-cells = <1>; 74dc94a94dSSameer Pujar #size-cells = <1>; 75dc94a94dSSameer Pujar ranges = <0x02900000 0x02900000 0x200000>; 76dc94a94dSSameer Pujar status = "disabled"; 77dc94a94dSSameer Pujar 78dc94a94dSSameer Pujar tegra_ahub: ahub@2900800 { 79dc94a94dSSameer Pujar compatible = "nvidia,tegra234-ahub"; 80dc94a94dSSameer Pujar reg = <0x02900800 0x800>; 81dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_AHUB>; 82dc94a94dSSameer Pujar clock-names = "ahub"; 83dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_AHUB>; 84dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 85dc94a94dSSameer Pujar #address-cells = <1>; 86dc94a94dSSameer Pujar #size-cells = <1>; 87dc94a94dSSameer Pujar ranges = <0x02900800 0x02900800 0x11800>; 88dc94a94dSSameer Pujar status = "disabled"; 89dc94a94dSSameer Pujar 90dc94a94dSSameer Pujar tegra_i2s1: i2s@2901000 { 91dc94a94dSSameer Pujar compatible = "nvidia,tegra234-i2s", 92dc94a94dSSameer Pujar "nvidia,tegra210-i2s"; 93dc94a94dSSameer Pujar reg = <0x2901000 0x100>; 94dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_I2S1>, 95dc94a94dSSameer Pujar <&bpmp TEGRA234_CLK_I2S1_SYNC_INPUT>; 96dc94a94dSSameer Pujar clock-names = "i2s", "sync_input"; 97dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_I2S1>; 98dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 99dc94a94dSSameer Pujar assigned-clock-rates = <1536000>; 100dc94a94dSSameer Pujar sound-name-prefix = "I2S1"; 101dc94a94dSSameer Pujar status = "disabled"; 102dc94a94dSSameer Pujar }; 103dc94a94dSSameer Pujar 104dc94a94dSSameer Pujar tegra_i2s2: i2s@2901100 { 105dc94a94dSSameer Pujar compatible = "nvidia,tegra234-i2s", 106dc94a94dSSameer Pujar "nvidia,tegra210-i2s"; 107dc94a94dSSameer Pujar reg = <0x2901100 0x100>; 108dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_I2S2>, 109dc94a94dSSameer Pujar <&bpmp TEGRA234_CLK_I2S2_SYNC_INPUT>; 110dc94a94dSSameer Pujar clock-names = "i2s", "sync_input"; 111dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_I2S2>; 112dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 113dc94a94dSSameer Pujar assigned-clock-rates = <1536000>; 114dc94a94dSSameer Pujar sound-name-prefix = "I2S2"; 115dc94a94dSSameer Pujar status = "disabled"; 116dc94a94dSSameer Pujar }; 117dc94a94dSSameer Pujar 118dc94a94dSSameer Pujar tegra_i2s3: i2s@2901200 { 119dc94a94dSSameer Pujar compatible = "nvidia,tegra234-i2s", 120dc94a94dSSameer Pujar "nvidia,tegra210-i2s"; 121dc94a94dSSameer Pujar reg = <0x2901200 0x100>; 122dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_I2S3>, 123dc94a94dSSameer Pujar <&bpmp TEGRA234_CLK_I2S3_SYNC_INPUT>; 124dc94a94dSSameer Pujar clock-names = "i2s", "sync_input"; 125dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_I2S3>; 126dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 127dc94a94dSSameer Pujar assigned-clock-rates = <1536000>; 128dc94a94dSSameer Pujar sound-name-prefix = "I2S3"; 129dc94a94dSSameer Pujar status = "disabled"; 130dc94a94dSSameer Pujar }; 131dc94a94dSSameer Pujar 132dc94a94dSSameer Pujar tegra_i2s4: i2s@2901300 { 133dc94a94dSSameer Pujar compatible = "nvidia,tegra234-i2s", 134dc94a94dSSameer Pujar "nvidia,tegra210-i2s"; 135dc94a94dSSameer Pujar reg = <0x2901300 0x100>; 136dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_I2S4>, 137dc94a94dSSameer Pujar <&bpmp TEGRA234_CLK_I2S4_SYNC_INPUT>; 138dc94a94dSSameer Pujar clock-names = "i2s", "sync_input"; 139dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_I2S4>; 140dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 141dc94a94dSSameer Pujar assigned-clock-rates = <1536000>; 142dc94a94dSSameer Pujar sound-name-prefix = "I2S4"; 143dc94a94dSSameer Pujar status = "disabled"; 144dc94a94dSSameer Pujar }; 145dc94a94dSSameer Pujar 146dc94a94dSSameer Pujar tegra_i2s5: i2s@2901400 { 147dc94a94dSSameer Pujar compatible = "nvidia,tegra234-i2s", 148dc94a94dSSameer Pujar "nvidia,tegra210-i2s"; 149dc94a94dSSameer Pujar reg = <0x2901400 0x100>; 150dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_I2S5>, 151dc94a94dSSameer Pujar <&bpmp TEGRA234_CLK_I2S5_SYNC_INPUT>; 152dc94a94dSSameer Pujar clock-names = "i2s", "sync_input"; 153dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_I2S5>; 154dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 155dc94a94dSSameer Pujar assigned-clock-rates = <1536000>; 156dc94a94dSSameer Pujar sound-name-prefix = "I2S5"; 157dc94a94dSSameer Pujar status = "disabled"; 158dc94a94dSSameer Pujar }; 159dc94a94dSSameer Pujar 160dc94a94dSSameer Pujar tegra_i2s6: i2s@2901500 { 161dc94a94dSSameer Pujar compatible = "nvidia,tegra234-i2s", 162dc94a94dSSameer Pujar "nvidia,tegra210-i2s"; 163dc94a94dSSameer Pujar reg = <0x2901500 0x100>; 164dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_I2S6>, 165dc94a94dSSameer Pujar <&bpmp TEGRA234_CLK_I2S6_SYNC_INPUT>; 166dc94a94dSSameer Pujar clock-names = "i2s", "sync_input"; 167dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_I2S6>; 168dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 169dc94a94dSSameer Pujar assigned-clock-rates = <1536000>; 170dc94a94dSSameer Pujar sound-name-prefix = "I2S6"; 171dc94a94dSSameer Pujar status = "disabled"; 172dc94a94dSSameer Pujar }; 173dc94a94dSSameer Pujar 174dc94a94dSSameer Pujar tegra_sfc1: sfc@2902000 { 175dc94a94dSSameer Pujar compatible = "nvidia,tegra234-sfc", 176dc94a94dSSameer Pujar "nvidia,tegra210-sfc"; 177dc94a94dSSameer Pujar reg = <0x2902000 0x200>; 178dc94a94dSSameer Pujar sound-name-prefix = "SFC1"; 179dc94a94dSSameer Pujar status = "disabled"; 180dc94a94dSSameer Pujar }; 181dc94a94dSSameer Pujar 182dc94a94dSSameer Pujar tegra_sfc2: sfc@2902200 { 183dc94a94dSSameer Pujar compatible = "nvidia,tegra234-sfc", 184dc94a94dSSameer Pujar "nvidia,tegra210-sfc"; 185dc94a94dSSameer Pujar reg = <0x2902200 0x200>; 186dc94a94dSSameer Pujar sound-name-prefix = "SFC2"; 187dc94a94dSSameer Pujar status = "disabled"; 188dc94a94dSSameer Pujar }; 189dc94a94dSSameer Pujar 190dc94a94dSSameer Pujar tegra_sfc3: sfc@2902400 { 191dc94a94dSSameer Pujar compatible = "nvidia,tegra234-sfc", 192dc94a94dSSameer Pujar "nvidia,tegra210-sfc"; 193dc94a94dSSameer Pujar reg = <0x2902400 0x200>; 194dc94a94dSSameer Pujar sound-name-prefix = "SFC3"; 195dc94a94dSSameer Pujar status = "disabled"; 196dc94a94dSSameer Pujar }; 197dc94a94dSSameer Pujar 198dc94a94dSSameer Pujar tegra_sfc4: sfc@2902600 { 199dc94a94dSSameer Pujar compatible = "nvidia,tegra234-sfc", 200dc94a94dSSameer Pujar "nvidia,tegra210-sfc"; 201dc94a94dSSameer Pujar reg = <0x2902600 0x200>; 202dc94a94dSSameer Pujar sound-name-prefix = "SFC4"; 203dc94a94dSSameer Pujar status = "disabled"; 204dc94a94dSSameer Pujar }; 205dc94a94dSSameer Pujar 206dc94a94dSSameer Pujar tegra_amx1: amx@2903000 { 207dc94a94dSSameer Pujar compatible = "nvidia,tegra234-amx", 208dc94a94dSSameer Pujar "nvidia,tegra194-amx"; 209dc94a94dSSameer Pujar reg = <0x2903000 0x100>; 210dc94a94dSSameer Pujar sound-name-prefix = "AMX1"; 211dc94a94dSSameer Pujar status = "disabled"; 212dc94a94dSSameer Pujar }; 213dc94a94dSSameer Pujar 214dc94a94dSSameer Pujar tegra_amx2: amx@2903100 { 215dc94a94dSSameer Pujar compatible = "nvidia,tegra234-amx", 216dc94a94dSSameer Pujar "nvidia,tegra194-amx"; 217dc94a94dSSameer Pujar reg = <0x2903100 0x100>; 218dc94a94dSSameer Pujar sound-name-prefix = "AMX2"; 219dc94a94dSSameer Pujar status = "disabled"; 220dc94a94dSSameer Pujar }; 221dc94a94dSSameer Pujar 222dc94a94dSSameer Pujar tegra_amx3: amx@2903200 { 223dc94a94dSSameer Pujar compatible = "nvidia,tegra234-amx", 224dc94a94dSSameer Pujar "nvidia,tegra194-amx"; 225dc94a94dSSameer Pujar reg = <0x2903200 0x100>; 226dc94a94dSSameer Pujar sound-name-prefix = "AMX3"; 227dc94a94dSSameer Pujar status = "disabled"; 228dc94a94dSSameer Pujar }; 229dc94a94dSSameer Pujar 230dc94a94dSSameer Pujar tegra_amx4: amx@2903300 { 231dc94a94dSSameer Pujar compatible = "nvidia,tegra234-amx", 232dc94a94dSSameer Pujar "nvidia,tegra194-amx"; 233dc94a94dSSameer Pujar reg = <0x2903300 0x100>; 234dc94a94dSSameer Pujar sound-name-prefix = "AMX4"; 235dc94a94dSSameer Pujar status = "disabled"; 236dc94a94dSSameer Pujar }; 237dc94a94dSSameer Pujar 238dc94a94dSSameer Pujar tegra_adx1: adx@2903800 { 239dc94a94dSSameer Pujar compatible = "nvidia,tegra234-adx", 240dc94a94dSSameer Pujar "nvidia,tegra210-adx"; 241dc94a94dSSameer Pujar reg = <0x2903800 0x100>; 242dc94a94dSSameer Pujar sound-name-prefix = "ADX1"; 243dc94a94dSSameer Pujar status = "disabled"; 244dc94a94dSSameer Pujar }; 245dc94a94dSSameer Pujar 246dc94a94dSSameer Pujar tegra_adx2: adx@2903900 { 247dc94a94dSSameer Pujar compatible = "nvidia,tegra234-adx", 248dc94a94dSSameer Pujar "nvidia,tegra210-adx"; 249dc94a94dSSameer Pujar reg = <0x2903900 0x100>; 250dc94a94dSSameer Pujar sound-name-prefix = "ADX2"; 251dc94a94dSSameer Pujar status = "disabled"; 252dc94a94dSSameer Pujar }; 253dc94a94dSSameer Pujar 254dc94a94dSSameer Pujar tegra_adx3: adx@2903a00 { 255dc94a94dSSameer Pujar compatible = "nvidia,tegra234-adx", 256dc94a94dSSameer Pujar "nvidia,tegra210-adx"; 257dc94a94dSSameer Pujar reg = <0x2903a00 0x100>; 258dc94a94dSSameer Pujar sound-name-prefix = "ADX3"; 259dc94a94dSSameer Pujar status = "disabled"; 260dc94a94dSSameer Pujar }; 261dc94a94dSSameer Pujar 262dc94a94dSSameer Pujar tegra_adx4: adx@2903b00 { 263dc94a94dSSameer Pujar compatible = "nvidia,tegra234-adx", 264dc94a94dSSameer Pujar "nvidia,tegra210-adx"; 265dc94a94dSSameer Pujar reg = <0x2903b00 0x100>; 266dc94a94dSSameer Pujar sound-name-prefix = "ADX4"; 267dc94a94dSSameer Pujar status = "disabled"; 268dc94a94dSSameer Pujar }; 269dc94a94dSSameer Pujar 270dc94a94dSSameer Pujar 271dc94a94dSSameer Pujar tegra_dmic1: dmic@2904000 { 272dc94a94dSSameer Pujar compatible = "nvidia,tegra234-dmic", 273dc94a94dSSameer Pujar "nvidia,tegra210-dmic"; 274dc94a94dSSameer Pujar reg = <0x2904000 0x100>; 275dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_DMIC1>; 276dc94a94dSSameer Pujar clock-names = "dmic"; 277dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_DMIC1>; 278dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 279dc94a94dSSameer Pujar assigned-clock-rates = <3072000>; 280dc94a94dSSameer Pujar sound-name-prefix = "DMIC1"; 281dc94a94dSSameer Pujar status = "disabled"; 282dc94a94dSSameer Pujar }; 283dc94a94dSSameer Pujar 284dc94a94dSSameer Pujar tegra_dmic2: dmic@2904100 { 285dc94a94dSSameer Pujar compatible = "nvidia,tegra234-dmic", 286dc94a94dSSameer Pujar "nvidia,tegra210-dmic"; 287dc94a94dSSameer Pujar reg = <0x2904100 0x100>; 288dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_DMIC2>; 289dc94a94dSSameer Pujar clock-names = "dmic"; 290dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_DMIC2>; 291dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 292dc94a94dSSameer Pujar assigned-clock-rates = <3072000>; 293dc94a94dSSameer Pujar sound-name-prefix = "DMIC2"; 294dc94a94dSSameer Pujar status = "disabled"; 295dc94a94dSSameer Pujar }; 296dc94a94dSSameer Pujar 297dc94a94dSSameer Pujar tegra_dmic3: dmic@2904200 { 298dc94a94dSSameer Pujar compatible = "nvidia,tegra234-dmic", 299dc94a94dSSameer Pujar "nvidia,tegra210-dmic"; 300dc94a94dSSameer Pujar reg = <0x2904200 0x100>; 301dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_DMIC3>; 302dc94a94dSSameer Pujar clock-names = "dmic"; 303dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_DMIC3>; 304dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 305dc94a94dSSameer Pujar assigned-clock-rates = <3072000>; 306dc94a94dSSameer Pujar sound-name-prefix = "DMIC3"; 307dc94a94dSSameer Pujar status = "disabled"; 308dc94a94dSSameer Pujar }; 309dc94a94dSSameer Pujar 310dc94a94dSSameer Pujar tegra_dmic4: dmic@2904300 { 311dc94a94dSSameer Pujar compatible = "nvidia,tegra234-dmic", 312dc94a94dSSameer Pujar "nvidia,tegra210-dmic"; 313dc94a94dSSameer Pujar reg = <0x2904300 0x100>; 314dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_DMIC4>; 315dc94a94dSSameer Pujar clock-names = "dmic"; 316dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_DMIC4>; 317dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 318dc94a94dSSameer Pujar assigned-clock-rates = <3072000>; 319dc94a94dSSameer Pujar sound-name-prefix = "DMIC4"; 320dc94a94dSSameer Pujar status = "disabled"; 321dc94a94dSSameer Pujar }; 322dc94a94dSSameer Pujar 323dc94a94dSSameer Pujar tegra_dspk1: dspk@2905000 { 324dc94a94dSSameer Pujar compatible = "nvidia,tegra234-dspk", 325dc94a94dSSameer Pujar "nvidia,tegra186-dspk"; 326dc94a94dSSameer Pujar reg = <0x2905000 0x100>; 327dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_DSPK1>; 328dc94a94dSSameer Pujar clock-names = "dspk"; 329dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_DSPK1>; 330dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 331dc94a94dSSameer Pujar assigned-clock-rates = <12288000>; 332dc94a94dSSameer Pujar sound-name-prefix = "DSPK1"; 333dc94a94dSSameer Pujar status = "disabled"; 334dc94a94dSSameer Pujar }; 335dc94a94dSSameer Pujar 336dc94a94dSSameer Pujar tegra_dspk2: dspk@2905100 { 337dc94a94dSSameer Pujar compatible = "nvidia,tegra234-dspk", 338dc94a94dSSameer Pujar "nvidia,tegra186-dspk"; 339dc94a94dSSameer Pujar reg = <0x2905100 0x100>; 340dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_DSPK2>; 341dc94a94dSSameer Pujar clock-names = "dspk"; 342dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_DSPK2>; 343dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 344dc94a94dSSameer Pujar assigned-clock-rates = <12288000>; 345dc94a94dSSameer Pujar sound-name-prefix = "DSPK2"; 346dc94a94dSSameer Pujar status = "disabled"; 347dc94a94dSSameer Pujar }; 348dc94a94dSSameer Pujar 3494b6a1b7cSSameer Pujar tegra_ope1: processing-engine@2908000 { 3504b6a1b7cSSameer Pujar compatible = "nvidia,tegra234-ope", 3514b6a1b7cSSameer Pujar "nvidia,tegra210-ope"; 3524b6a1b7cSSameer Pujar reg = <0x2908000 0x100>; 3534b6a1b7cSSameer Pujar #address-cells = <1>; 3544b6a1b7cSSameer Pujar #size-cells = <1>; 3554b6a1b7cSSameer Pujar ranges; 3564b6a1b7cSSameer Pujar sound-name-prefix = "OPE1"; 3574b6a1b7cSSameer Pujar status = "disabled"; 3584b6a1b7cSSameer Pujar 3594b6a1b7cSSameer Pujar equalizer@2908100 { 3604b6a1b7cSSameer Pujar compatible = "nvidia,tegra234-peq", 3614b6a1b7cSSameer Pujar "nvidia,tegra210-peq"; 3624b6a1b7cSSameer Pujar reg = <0x2908100 0x100>; 3634b6a1b7cSSameer Pujar }; 3644b6a1b7cSSameer Pujar 3654b6a1b7cSSameer Pujar dynamic-range-compressor@2908200 { 3664b6a1b7cSSameer Pujar compatible = "nvidia,tegra234-mbdrc", 3674b6a1b7cSSameer Pujar "nvidia,tegra210-mbdrc"; 3684b6a1b7cSSameer Pujar reg = <0x2908200 0x200>; 3694b6a1b7cSSameer Pujar }; 3704b6a1b7cSSameer Pujar }; 3714b6a1b7cSSameer Pujar 372dc94a94dSSameer Pujar tegra_mvc1: mvc@290a000 { 373dc94a94dSSameer Pujar compatible = "nvidia,tegra234-mvc", 374dc94a94dSSameer Pujar "nvidia,tegra210-mvc"; 375dc94a94dSSameer Pujar reg = <0x290a000 0x200>; 376dc94a94dSSameer Pujar sound-name-prefix = "MVC1"; 377dc94a94dSSameer Pujar status = "disabled"; 378dc94a94dSSameer Pujar }; 379dc94a94dSSameer Pujar 380dc94a94dSSameer Pujar tegra_mvc2: mvc@290a200 { 381dc94a94dSSameer Pujar compatible = "nvidia,tegra234-mvc", 382dc94a94dSSameer Pujar "nvidia,tegra210-mvc"; 383dc94a94dSSameer Pujar reg = <0x290a200 0x200>; 384dc94a94dSSameer Pujar sound-name-prefix = "MVC2"; 385dc94a94dSSameer Pujar status = "disabled"; 386dc94a94dSSameer Pujar }; 387dc94a94dSSameer Pujar 388dc94a94dSSameer Pujar tegra_amixer: amixer@290bb00 { 389dc94a94dSSameer Pujar compatible = "nvidia,tegra234-amixer", 390dc94a94dSSameer Pujar "nvidia,tegra210-amixer"; 391dc94a94dSSameer Pujar reg = <0x290bb00 0x800>; 392dc94a94dSSameer Pujar sound-name-prefix = "MIXER1"; 393dc94a94dSSameer Pujar status = "disabled"; 394dc94a94dSSameer Pujar }; 395dc94a94dSSameer Pujar 396dc94a94dSSameer Pujar tegra_admaif: admaif@290f000 { 397dc94a94dSSameer Pujar compatible = "nvidia,tegra234-admaif", 398dc94a94dSSameer Pujar "nvidia,tegra186-admaif"; 399dc94a94dSSameer Pujar reg = <0x0290f000 0x1000>; 400dc94a94dSSameer Pujar dmas = <&adma 1>, <&adma 1>, 401dc94a94dSSameer Pujar <&adma 2>, <&adma 2>, 402dc94a94dSSameer Pujar <&adma 3>, <&adma 3>, 403dc94a94dSSameer Pujar <&adma 4>, <&adma 4>, 404dc94a94dSSameer Pujar <&adma 5>, <&adma 5>, 405dc94a94dSSameer Pujar <&adma 6>, <&adma 6>, 406dc94a94dSSameer Pujar <&adma 7>, <&adma 7>, 407dc94a94dSSameer Pujar <&adma 8>, <&adma 8>, 408dc94a94dSSameer Pujar <&adma 9>, <&adma 9>, 409dc94a94dSSameer Pujar <&adma 10>, <&adma 10>, 410dc94a94dSSameer Pujar <&adma 11>, <&adma 11>, 411dc94a94dSSameer Pujar <&adma 12>, <&adma 12>, 412dc94a94dSSameer Pujar <&adma 13>, <&adma 13>, 413dc94a94dSSameer Pujar <&adma 14>, <&adma 14>, 414dc94a94dSSameer Pujar <&adma 15>, <&adma 15>, 415dc94a94dSSameer Pujar <&adma 16>, <&adma 16>, 416dc94a94dSSameer Pujar <&adma 17>, <&adma 17>, 417dc94a94dSSameer Pujar <&adma 18>, <&adma 18>, 418dc94a94dSSameer Pujar <&adma 19>, <&adma 19>, 419dc94a94dSSameer Pujar <&adma 20>, <&adma 20>; 420dc94a94dSSameer Pujar dma-names = "rx1", "tx1", 421dc94a94dSSameer Pujar "rx2", "tx2", 422dc94a94dSSameer Pujar "rx3", "tx3", 423dc94a94dSSameer Pujar "rx4", "tx4", 424dc94a94dSSameer Pujar "rx5", "tx5", 425dc94a94dSSameer Pujar "rx6", "tx6", 426dc94a94dSSameer Pujar "rx7", "tx7", 427dc94a94dSSameer Pujar "rx8", "tx8", 428dc94a94dSSameer Pujar "rx9", "tx9", 429dc94a94dSSameer Pujar "rx10", "tx10", 430dc94a94dSSameer Pujar "rx11", "tx11", 431dc94a94dSSameer Pujar "rx12", "tx12", 432dc94a94dSSameer Pujar "rx13", "tx13", 433dc94a94dSSameer Pujar "rx14", "tx14", 434dc94a94dSSameer Pujar "rx15", "tx15", 435dc94a94dSSameer Pujar "rx16", "tx16", 436dc94a94dSSameer Pujar "rx17", "tx17", 437dc94a94dSSameer Pujar "rx18", "tx18", 438dc94a94dSSameer Pujar "rx19", "tx19", 439dc94a94dSSameer Pujar "rx20", "tx20"; 440dc94a94dSSameer Pujar interconnects = <&mc TEGRA234_MEMORY_CLIENT_APEDMAR &emc>, 441dc94a94dSSameer Pujar <&mc TEGRA234_MEMORY_CLIENT_APEDMAW &emc>; 442dc94a94dSSameer Pujar interconnect-names = "dma-mem", "write"; 443dc94a94dSSameer Pujar iommus = <&smmu_niso0 TEGRA234_SID_APE>; 444dc94a94dSSameer Pujar status = "disabled"; 445dc94a94dSSameer Pujar }; 44647a08153SSameer Pujar 44747a08153SSameer Pujar tegra_asrc: asrc@2910000 { 44847a08153SSameer Pujar compatible = "nvidia,tegra234-asrc", 44947a08153SSameer Pujar "nvidia,tegra186-asrc"; 45047a08153SSameer Pujar reg = <0x2910000 0x2000>; 45147a08153SSameer Pujar sound-name-prefix = "ASRC1"; 45247a08153SSameer Pujar status = "disabled"; 45347a08153SSameer Pujar }; 454dc94a94dSSameer Pujar }; 455dc94a94dSSameer Pujar 456dc94a94dSSameer Pujar adma: dma-controller@2930000 { 457dc94a94dSSameer Pujar compatible = "nvidia,tegra234-adma", 458dc94a94dSSameer Pujar "nvidia,tegra186-adma"; 459dc94a94dSSameer Pujar reg = <0x02930000 0x20000>; 460dc94a94dSSameer Pujar interrupt-parent = <&agic>; 461dc94a94dSSameer Pujar interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 462dc94a94dSSameer Pujar <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 463dc94a94dSSameer Pujar <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 464dc94a94dSSameer Pujar <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 465dc94a94dSSameer Pujar <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 466dc94a94dSSameer Pujar <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 467dc94a94dSSameer Pujar <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 468dc94a94dSSameer Pujar <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 469dc94a94dSSameer Pujar <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 470dc94a94dSSameer Pujar <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 471dc94a94dSSameer Pujar <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 472dc94a94dSSameer Pujar <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 473dc94a94dSSameer Pujar <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 474dc94a94dSSameer Pujar <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 475dc94a94dSSameer Pujar <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 476dc94a94dSSameer Pujar <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 477dc94a94dSSameer Pujar <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 478dc94a94dSSameer Pujar <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 479dc94a94dSSameer Pujar <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 480dc94a94dSSameer Pujar <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 481dc94a94dSSameer Pujar <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 482dc94a94dSSameer Pujar <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 483dc94a94dSSameer Pujar <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 484dc94a94dSSameer Pujar <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 485dc94a94dSSameer Pujar <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 486dc94a94dSSameer Pujar <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 487dc94a94dSSameer Pujar <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 488dc94a94dSSameer Pujar <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 489dc94a94dSSameer Pujar <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 490dc94a94dSSameer Pujar <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 491dc94a94dSSameer Pujar <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 492dc94a94dSSameer Pujar <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 493dc94a94dSSameer Pujar #dma-cells = <1>; 494dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_AHUB>; 495dc94a94dSSameer Pujar clock-names = "d_audio"; 496dc94a94dSSameer Pujar status = "disabled"; 497dc94a94dSSameer Pujar }; 498dc94a94dSSameer Pujar 499dc94a94dSSameer Pujar agic: interrupt-controller@2a40000 { 500dc94a94dSSameer Pujar compatible = "nvidia,tegra234-agic", 501dc94a94dSSameer Pujar "nvidia,tegra210-agic"; 502dc94a94dSSameer Pujar #interrupt-cells = <3>; 503dc94a94dSSameer Pujar interrupt-controller; 504dc94a94dSSameer Pujar reg = <0x02a41000 0x1000>, 505dc94a94dSSameer Pujar <0x02a42000 0x2000>; 506dc94a94dSSameer Pujar interrupts = <GIC_SPI 145 507dc94a94dSSameer Pujar (GIC_CPU_MASK_SIMPLE(4) | 508dc94a94dSSameer Pujar IRQ_TYPE_LEVEL_HIGH)>; 509dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_APE>; 510dc94a94dSSameer Pujar clock-names = "clk"; 511dc94a94dSSameer Pujar status = "disabled"; 512dc94a94dSSameer Pujar }; 513dc94a94dSSameer Pujar }; 514dc94a94dSSameer Pujar 51563944891SThierry Reding misc@100000 { 51663944891SThierry Reding compatible = "nvidia,tegra234-misc"; 51763944891SThierry Reding reg = <0x00100000 0xf000>, 51863944891SThierry Reding <0x0010f000 0x1000>; 51963944891SThierry Reding status = "okay"; 52063944891SThierry Reding }; 52163944891SThierry Reding 52228d860edSKartik timer@2080000 { 52328d860edSKartik compatible = "nvidia,tegra234-timer"; 52428d860edSKartik reg = <0x02080000 0x00121000>; 52528d860edSKartik interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 52628d860edSKartik <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 52728d860edSKartik <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 52828d860edSKartik <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 52928d860edSKartik <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 53028d860edSKartik <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 53128d860edSKartik <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 53228d860edSKartik <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 53328d860edSKartik <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 53428d860edSKartik <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 53528d860edSKartik <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 53628d860edSKartik <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 53728d860edSKartik <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 53828d860edSKartik <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 53928d860edSKartik <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 54028d860edSKartik <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 54128d860edSKartik status = "okay"; 54228d860edSKartik }; 54328d860edSKartik 5444bb39ca2SMikko Perttunen host1x@13e00000 { 5454bb39ca2SMikko Perttunen compatible = "nvidia,tegra234-host1x"; 5464bb39ca2SMikko Perttunen reg = <0x13e00000 0x10000>, 5474bb39ca2SMikko Perttunen <0x13e10000 0x10000>, 5484bb39ca2SMikko Perttunen <0x13e40000 0x10000>; 5494bb39ca2SMikko Perttunen reg-names = "common", "hypervisor", "vm"; 5504bb39ca2SMikko Perttunen interrupts = <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, 5514bb39ca2SMikko Perttunen <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, 5524bb39ca2SMikko Perttunen <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, 5534bb39ca2SMikko Perttunen <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, 5544bb39ca2SMikko Perttunen <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, 5554bb39ca2SMikko Perttunen <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>, 5564bb39ca2SMikko Perttunen <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>, 5574bb39ca2SMikko Perttunen <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>, 5584bb39ca2SMikko Perttunen <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 5594bb39ca2SMikko Perttunen interrupt-names = "syncpt0", "syncpt1", "syncpt2", "syncpt3", "syncpt4", 5604bb39ca2SMikko Perttunen "syncpt5", "syncpt6", "syncpt7", "host1x"; 5614bb39ca2SMikko Perttunen clocks = <&bpmp TEGRA234_CLK_HOST1X>; 5624bb39ca2SMikko Perttunen clock-names = "host1x"; 5634bb39ca2SMikko Perttunen 5644bb39ca2SMikko Perttunen #address-cells = <1>; 5654bb39ca2SMikko Perttunen #size-cells = <1>; 5664bb39ca2SMikko Perttunen 5674bb39ca2SMikko Perttunen ranges = <0x15000000 0x15000000 0x01000000>; 5684bb39ca2SMikko Perttunen interconnects = <&mc TEGRA234_MEMORY_CLIENT_HOST1XDMAR &emc>; 5694bb39ca2SMikko Perttunen interconnect-names = "dma-mem"; 5704bb39ca2SMikko Perttunen iommus = <&smmu_niso1 TEGRA234_SID_HOST1X>; 5714bb39ca2SMikko Perttunen 572b35f5b53SMikko Perttunen /* Context isolation domains */ 573b35f5b53SMikko Perttunen iommu-map = <0 &smmu_niso0 TEGRA234_SID_HOST1X_CTX0 1>, 574b35f5b53SMikko Perttunen <1 &smmu_niso0 TEGRA234_SID_HOST1X_CTX1 1>, 575b35f5b53SMikko Perttunen <2 &smmu_niso0 TEGRA234_SID_HOST1X_CTX2 1>, 576b35f5b53SMikko Perttunen <3 &smmu_niso0 TEGRA234_SID_HOST1X_CTX3 1>, 577b35f5b53SMikko Perttunen <4 &smmu_niso0 TEGRA234_SID_HOST1X_CTX4 1>, 578b35f5b53SMikko Perttunen <5 &smmu_niso0 TEGRA234_SID_HOST1X_CTX5 1>, 579b35f5b53SMikko Perttunen <6 &smmu_niso0 TEGRA234_SID_HOST1X_CTX6 1>, 580b35f5b53SMikko Perttunen <7 &smmu_niso0 TEGRA234_SID_HOST1X_CTX7 1>, 581b35f5b53SMikko Perttunen <8 &smmu_niso1 TEGRA234_SID_HOST1X_CTX0 1>, 582b35f5b53SMikko Perttunen <9 &smmu_niso1 TEGRA234_SID_HOST1X_CTX1 1>, 583b35f5b53SMikko Perttunen <10 &smmu_niso1 TEGRA234_SID_HOST1X_CTX2 1>, 584b35f5b53SMikko Perttunen <11 &smmu_niso1 TEGRA234_SID_HOST1X_CTX3 1>, 585b35f5b53SMikko Perttunen <12 &smmu_niso1 TEGRA234_SID_HOST1X_CTX4 1>, 586b35f5b53SMikko Perttunen <13 &smmu_niso1 TEGRA234_SID_HOST1X_CTX5 1>, 587b35f5b53SMikko Perttunen <14 &smmu_niso1 TEGRA234_SID_HOST1X_CTX6 1>, 588b35f5b53SMikko Perttunen <15 &smmu_niso1 TEGRA234_SID_HOST1X_CTX7 1>; 589b35f5b53SMikko Perttunen 5904bb39ca2SMikko Perttunen vic@15340000 { 5914bb39ca2SMikko Perttunen compatible = "nvidia,tegra234-vic"; 5924bb39ca2SMikko Perttunen reg = <0x15340000 0x00040000>; 5934bb39ca2SMikko Perttunen interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 5944bb39ca2SMikko Perttunen clocks = <&bpmp TEGRA234_CLK_VIC>; 5954bb39ca2SMikko Perttunen clock-names = "vic"; 5964bb39ca2SMikko Perttunen resets = <&bpmp TEGRA234_RESET_VIC>; 5974bb39ca2SMikko Perttunen reset-names = "vic"; 5984bb39ca2SMikko Perttunen 5994bb39ca2SMikko Perttunen power-domains = <&bpmp TEGRA234_POWER_DOMAIN_VIC>; 6004bb39ca2SMikko Perttunen interconnects = <&mc TEGRA234_MEMORY_CLIENT_VICSRD &emc>, 6014bb39ca2SMikko Perttunen <&mc TEGRA234_MEMORY_CLIENT_VICSWR &emc>; 6024bb39ca2SMikko Perttunen interconnect-names = "dma-mem", "write"; 6034bb39ca2SMikko Perttunen iommus = <&smmu_niso1 TEGRA234_SID_VIC>; 6044bb39ca2SMikko Perttunen dma-coherent; 6054bb39ca2SMikko Perttunen }; 6064bb39ca2SMikko Perttunen }; 6074bb39ca2SMikko Perttunen 608f0e12668SThierry Reding gpio: gpio@2200000 { 609f0e12668SThierry Reding compatible = "nvidia,tegra234-gpio"; 610f0e12668SThierry Reding reg-names = "security", "gpio"; 611f0e12668SThierry Reding reg = <0x02200000 0x10000>, 612f0e12668SThierry Reding <0x02210000 0x10000>; 613f0e12668SThierry Reding interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 614f0e12668SThierry Reding <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 615f0e12668SThierry Reding <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 616f0e12668SThierry Reding <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, 617f0e12668SThierry Reding <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 618f0e12668SThierry Reding <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 619f0e12668SThierry Reding <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 620f0e12668SThierry Reding <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 621f0e12668SThierry Reding <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 622f0e12668SThierry Reding <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 623f0e12668SThierry Reding <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 624f0e12668SThierry Reding <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 625f0e12668SThierry Reding <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 626f0e12668SThierry Reding <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 627f0e12668SThierry Reding <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 628f0e12668SThierry Reding <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 629f0e12668SThierry Reding <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 630f0e12668SThierry Reding <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 631f0e12668SThierry Reding <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 632f0e12668SThierry Reding <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 633f0e12668SThierry Reding <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 634f0e12668SThierry Reding <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 635f0e12668SThierry Reding <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 636f0e12668SThierry Reding <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 637f0e12668SThierry Reding <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 638f0e12668SThierry Reding <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 639f0e12668SThierry Reding <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 640f0e12668SThierry Reding <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 641f0e12668SThierry Reding <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 642f0e12668SThierry Reding <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 643f0e12668SThierry Reding <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 644f0e12668SThierry Reding <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 645f0e12668SThierry Reding <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 646f0e12668SThierry Reding <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 647f0e12668SThierry Reding <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 648f0e12668SThierry Reding <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 649f0e12668SThierry Reding <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 650f0e12668SThierry Reding <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 651f0e12668SThierry Reding <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 652f0e12668SThierry Reding <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 653f0e12668SThierry Reding <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 654f0e12668SThierry Reding <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 655f0e12668SThierry Reding <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 656f0e12668SThierry Reding <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 657f0e12668SThierry Reding <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 658f0e12668SThierry Reding <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 659f0e12668SThierry Reding <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 660f0e12668SThierry Reding <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 661f0e12668SThierry Reding #interrupt-cells = <2>; 662f0e12668SThierry Reding interrupt-controller; 663f0e12668SThierry Reding #gpio-cells = <2>; 664f0e12668SThierry Reding gpio-controller; 665f0e12668SThierry Reding }; 666f0e12668SThierry Reding 667eed280dfSThierry Reding mc: memory-controller@2c00000 { 668eed280dfSThierry Reding compatible = "nvidia,tegra234-mc"; 669000b99e5SAshish Mhetre reg = <0x02c00000 0x10000>, /* MC-SID */ 670000b99e5SAshish Mhetre <0x02c10000 0x10000>, /* MC Broadcast*/ 671000b99e5SAshish Mhetre <0x02c20000 0x10000>, /* MC0 */ 672000b99e5SAshish Mhetre <0x02c30000 0x10000>, /* MC1 */ 673000b99e5SAshish Mhetre <0x02c40000 0x10000>, /* MC2 */ 674000b99e5SAshish Mhetre <0x02c50000 0x10000>, /* MC3 */ 675000b99e5SAshish Mhetre <0x02b80000 0x10000>, /* MC4 */ 676000b99e5SAshish Mhetre <0x02b90000 0x10000>, /* MC5 */ 677000b99e5SAshish Mhetre <0x02ba0000 0x10000>, /* MC6 */ 678000b99e5SAshish Mhetre <0x02bb0000 0x10000>, /* MC7 */ 679000b99e5SAshish Mhetre <0x01700000 0x10000>, /* MC8 */ 680000b99e5SAshish Mhetre <0x01710000 0x10000>, /* MC9 */ 681000b99e5SAshish Mhetre <0x01720000 0x10000>, /* MC10 */ 682000b99e5SAshish Mhetre <0x01730000 0x10000>, /* MC11 */ 683000b99e5SAshish Mhetre <0x01740000 0x10000>, /* MC12 */ 684000b99e5SAshish Mhetre <0x01750000 0x10000>, /* MC13 */ 685000b99e5SAshish Mhetre <0x01760000 0x10000>, /* MC14 */ 686000b99e5SAshish Mhetre <0x01770000 0x10000>; /* MC15 */ 687000b99e5SAshish Mhetre reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3", 688000b99e5SAshish Mhetre "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", 689000b99e5SAshish Mhetre "ch11", "ch12", "ch13", "ch14", "ch15"; 690eed280dfSThierry Reding interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 691eed280dfSThierry Reding #interconnect-cells = <1>; 692eed280dfSThierry Reding status = "okay"; 693eed280dfSThierry Reding 694eed280dfSThierry Reding #address-cells = <2>; 695eed280dfSThierry Reding #size-cells = <2>; 696eed280dfSThierry Reding 697eed280dfSThierry Reding ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>, 698eed280dfSThierry Reding <0x02b80000 0x0 0x02b80000 0x0 0x040000>, 699eed280dfSThierry Reding <0x02c00000 0x0 0x02c00000 0x0 0x100000>; 700eed280dfSThierry Reding 701eed280dfSThierry Reding /* 702eed280dfSThierry Reding * Bit 39 of addresses passing through the memory 703eed280dfSThierry Reding * controller selects the XBAR format used when memory 704eed280dfSThierry Reding * is accessed. This is used to transparently access 705eed280dfSThierry Reding * memory in the XBAR format used by the discrete GPU 706eed280dfSThierry Reding * (bit 39 set) or Tegra (bit 39 clear). 707eed280dfSThierry Reding * 708eed280dfSThierry Reding * As a consequence, the operating system must ensure 709eed280dfSThierry Reding * that bit 39 is never used implicitly, for example 710eed280dfSThierry Reding * via an I/O virtual address mapping of an IOMMU. If 711eed280dfSThierry Reding * devices require access to the XBAR switch, their 712eed280dfSThierry Reding * drivers must set this bit explicitly. 713eed280dfSThierry Reding * 714eed280dfSThierry Reding * Limit the DMA range for memory clients to [38:0]. 715eed280dfSThierry Reding */ 716eed280dfSThierry Reding dma-ranges = <0x0 0x0 0x0 0x80 0x0>; 717eed280dfSThierry Reding 718eed280dfSThierry Reding emc: external-memory-controller@2c60000 { 719eed280dfSThierry Reding compatible = "nvidia,tegra234-emc"; 720eed280dfSThierry Reding reg = <0x0 0x02c60000 0x0 0x90000>, 721eed280dfSThierry Reding <0x0 0x01780000 0x0 0x80000>; 722eed280dfSThierry Reding interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 723eed280dfSThierry Reding clocks = <&bpmp TEGRA234_CLK_EMC>; 724eed280dfSThierry Reding clock-names = "emc"; 725eed280dfSThierry Reding status = "okay"; 726eed280dfSThierry Reding 727eed280dfSThierry Reding #interconnect-cells = <0>; 728eed280dfSThierry Reding 729eed280dfSThierry Reding nvidia,bpmp = <&bpmp>; 730eed280dfSThierry Reding }; 731eed280dfSThierry Reding }; 732eed280dfSThierry Reding 73363944891SThierry Reding uarta: serial@3100000 { 73463944891SThierry Reding compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart"; 73563944891SThierry Reding reg = <0x03100000 0x10000>; 73663944891SThierry Reding interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 73763944891SThierry Reding clocks = <&bpmp TEGRA234_CLK_UARTA>; 73863944891SThierry Reding clock-names = "serial"; 73963944891SThierry Reding resets = <&bpmp TEGRA234_RESET_UARTA>; 74063944891SThierry Reding reset-names = "serial"; 74163944891SThierry Reding status = "disabled"; 74263944891SThierry Reding }; 74363944891SThierry Reding 744156af9deSAkhil R gen1_i2c: i2c@3160000 { 745156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 746156af9deSAkhil R reg = <0x3160000 0x100>; 747156af9deSAkhil R status = "disabled"; 748156af9deSAkhil R interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 749156af9deSAkhil R clock-frequency = <400000>; 750156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C1 751156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 752156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C1>; 753156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 754156af9deSAkhil R clock-names = "div-clk", "parent"; 755156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C1>; 756156af9deSAkhil R reset-names = "i2c"; 757156af9deSAkhil R }; 758156af9deSAkhil R 759156af9deSAkhil R cam_i2c: i2c@3180000 { 760156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 761156af9deSAkhil R reg = <0x3180000 0x100>; 762156af9deSAkhil R interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 763156af9deSAkhil R status = "disabled"; 764156af9deSAkhil R clock-frequency = <400000>; 765156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C3 766156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 767156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C3>; 768156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 769156af9deSAkhil R clock-names = "div-clk", "parent"; 770156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C3>; 771156af9deSAkhil R reset-names = "i2c"; 772156af9deSAkhil R }; 773156af9deSAkhil R 774156af9deSAkhil R dp_aux_ch1_i2c: i2c@3190000 { 775156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 776156af9deSAkhil R reg = <0x3190000 0x100>; 777156af9deSAkhil R interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 778156af9deSAkhil R status = "disabled"; 779156af9deSAkhil R clock-frequency = <100000>; 780156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C4 781156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 782156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C4>; 783156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 784156af9deSAkhil R clock-names = "div-clk", "parent"; 785156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C4>; 786156af9deSAkhil R reset-names = "i2c"; 787156af9deSAkhil R }; 788156af9deSAkhil R 789156af9deSAkhil R dp_aux_ch0_i2c: i2c@31b0000 { 790156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 791156af9deSAkhil R reg = <0x31b0000 0x100>; 792156af9deSAkhil R interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 793156af9deSAkhil R status = "disabled"; 794156af9deSAkhil R clock-frequency = <100000>; 795156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C6 796156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 797156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C6>; 798156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 799156af9deSAkhil R clock-names = "div-clk", "parent"; 800156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C6>; 801156af9deSAkhil R reset-names = "i2c"; 802156af9deSAkhil R }; 803156af9deSAkhil R 804156af9deSAkhil R dp_aux_ch2_i2c: i2c@31c0000 { 805156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 806156af9deSAkhil R reg = <0x31c0000 0x100>; 807156af9deSAkhil R interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 808156af9deSAkhil R status = "disabled"; 809156af9deSAkhil R clock-frequency = <100000>; 810156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C7 811156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 812156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C7>; 813156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 814156af9deSAkhil R clock-names = "div-clk", "parent"; 815156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C7>; 816156af9deSAkhil R reset-names = "i2c"; 817156af9deSAkhil R }; 818156af9deSAkhil R 819156af9deSAkhil R dp_aux_ch3_i2c: i2c@31e0000 { 820156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 821156af9deSAkhil R reg = <0x31e0000 0x100>; 822156af9deSAkhil R interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 823156af9deSAkhil R status = "disabled"; 824156af9deSAkhil R clock-frequency = <100000>; 825156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C9 826156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 827156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C9>; 828156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 829156af9deSAkhil R clock-names = "div-clk", "parent"; 830156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C9>; 831156af9deSAkhil R reset-names = "i2c"; 832156af9deSAkhil R }; 833156af9deSAkhil R 83471f69ffaSAshish Singhal spi@3270000 { 83571f69ffaSAshish Singhal compatible = "nvidia,tegra234-qspi"; 83671f69ffaSAshish Singhal reg = <0x3270000 0x1000>; 83771f69ffaSAshish Singhal interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 83871f69ffaSAshish Singhal #address-cells = <1>; 83971f69ffaSAshish Singhal #size-cells = <0>; 84071f69ffaSAshish Singhal clocks = <&bpmp TEGRA234_CLK_QSPI0_2X_PM>, 84171f69ffaSAshish Singhal <&bpmp TEGRA234_CLK_QSPI0_PM>; 84271f69ffaSAshish Singhal clock-names = "qspi", "qspi_out"; 84371f69ffaSAshish Singhal resets = <&bpmp TEGRA234_RESET_QSPI0>; 84471f69ffaSAshish Singhal reset-names = "qspi"; 84571f69ffaSAshish Singhal status = "disabled"; 84671f69ffaSAshish Singhal }; 84771f69ffaSAshish Singhal 8485e69088dSAkhil R pwm1: pwm@3280000 { 8495e69088dSAkhil R compatible = "nvidia,tegra194-pwm", 8505e69088dSAkhil R "nvidia,tegra186-pwm"; 8515e69088dSAkhil R reg = <0x3280000 0x10000>; 8525e69088dSAkhil R clocks = <&bpmp TEGRA234_CLK_PWM1>; 8535e69088dSAkhil R clock-names = "pwm"; 8545e69088dSAkhil R resets = <&bpmp TEGRA234_RESET_PWM1>; 8555e69088dSAkhil R reset-names = "pwm"; 8565e69088dSAkhil R status = "disabled"; 8575e69088dSAkhil R #pwm-cells = <2>; 8585e69088dSAkhil R }; 8595e69088dSAkhil R 86071f69ffaSAshish Singhal spi@3300000 { 86171f69ffaSAshish Singhal compatible = "nvidia,tegra234-qspi"; 86271f69ffaSAshish Singhal reg = <0x3300000 0x1000>; 86371f69ffaSAshish Singhal interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 86471f69ffaSAshish Singhal #address-cells = <1>; 86571f69ffaSAshish Singhal #size-cells = <0>; 86671f69ffaSAshish Singhal clocks = <&bpmp TEGRA234_CLK_QSPI1_2X_PM>, 86771f69ffaSAshish Singhal <&bpmp TEGRA234_CLK_QSPI1_PM>; 86871f69ffaSAshish Singhal clock-names = "qspi", "qspi_out"; 86971f69ffaSAshish Singhal resets = <&bpmp TEGRA234_RESET_QSPI1>; 87071f69ffaSAshish Singhal reset-names = "qspi"; 87171f69ffaSAshish Singhal status = "disabled"; 87271f69ffaSAshish Singhal }; 87371f69ffaSAshish Singhal 87463944891SThierry Reding mmc@3460000 { 87563944891SThierry Reding compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci"; 87663944891SThierry Reding reg = <0x03460000 0x20000>; 87763944891SThierry Reding interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 878e086d82dSMikko Perttunen clocks = <&bpmp TEGRA234_CLK_SDMMC4>, 879e086d82dSMikko Perttunen <&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>; 880e086d82dSMikko Perttunen clock-names = "sdhci", "tmclk"; 881e086d82dSMikko Perttunen assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC4>, 882e086d82dSMikko Perttunen <&bpmp TEGRA234_CLK_PLLC4>; 883e086d82dSMikko Perttunen assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4>; 88463944891SThierry Reding resets = <&bpmp TEGRA234_RESET_SDMMC4>; 88563944891SThierry Reding reset-names = "sdhci"; 8866de481e5SThierry Reding interconnects = <&mc TEGRA234_MEMORY_CLIENT_SDMMCRAB &emc>, 8876de481e5SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_SDMMCWAB &emc>; 8886de481e5SThierry Reding interconnect-names = "dma-mem", "write"; 8895710e16aSThierry Reding iommus = <&smmu_niso1 TEGRA234_SID_SDMMC4>; 890e086d82dSMikko Perttunen nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 891e086d82dSMikko Perttunen nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 892e086d82dSMikko Perttunen nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 893e086d82dSMikko Perttunen nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; 894e086d82dSMikko Perttunen nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 895e086d82dSMikko Perttunen nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>; 896e086d82dSMikko Perttunen nvidia,default-tap = <0x8>; 897e086d82dSMikko Perttunen nvidia,default-trim = <0x14>; 898e086d82dSMikko Perttunen nvidia,dqs-trim = <40>; 899e086d82dSMikko Perttunen supports-cqe; 90063944891SThierry Reding status = "disabled"; 90163944891SThierry Reding }; 90263944891SThierry Reding 903621e12a1SMohan Kumar hda@3510000 { 904621e12a1SMohan Kumar compatible = "nvidia,tegra234-hda", "nvidia,tegra30-hda"; 905621e12a1SMohan Kumar reg = <0x3510000 0x10000>; 906621e12a1SMohan Kumar interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 907621e12a1SMohan Kumar clocks = <&bpmp TEGRA234_CLK_AZA_BIT>, 908621e12a1SMohan Kumar <&bpmp TEGRA234_CLK_AZA_2XBIT>; 909621e12a1SMohan Kumar clock-names = "hda", "hda2codec_2x"; 910621e12a1SMohan Kumar resets = <&bpmp TEGRA234_RESET_HDA>, 911621e12a1SMohan Kumar <&bpmp TEGRA234_RESET_HDACODEC>; 912621e12a1SMohan Kumar reset-names = "hda", "hda2codec_2x"; 913621e12a1SMohan Kumar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_DISP>; 914621e12a1SMohan Kumar interconnects = <&mc TEGRA234_MEMORY_CLIENT_HDAR &emc>, 915621e12a1SMohan Kumar <&mc TEGRA234_MEMORY_CLIENT_HDAW &emc>; 916621e12a1SMohan Kumar interconnect-names = "dma-mem", "write"; 917*af4c2773SMohan Kumar iommus = <&smmu_niso0 TEGRA234_SID_HDA>; 918621e12a1SMohan Kumar status = "disabled"; 919621e12a1SMohan Kumar }; 920621e12a1SMohan Kumar 92163944891SThierry Reding fuse@3810000 { 92263944891SThierry Reding compatible = "nvidia,tegra234-efuse"; 92363944891SThierry Reding reg = <0x03810000 0x10000>; 92463944891SThierry Reding clocks = <&bpmp TEGRA234_CLK_FUSE>; 92563944891SThierry Reding clock-names = "fuse"; 92663944891SThierry Reding }; 92763944891SThierry Reding 92863944891SThierry Reding hsp_top0: hsp@3c00000 { 92963944891SThierry Reding compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; 93063944891SThierry Reding reg = <0x03c00000 0xa0000>; 93163944891SThierry Reding interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 93263944891SThierry Reding <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 93363944891SThierry Reding <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 93463944891SThierry Reding <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 93563944891SThierry Reding <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 93663944891SThierry Reding <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 93763944891SThierry Reding <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 93863944891SThierry Reding <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 93963944891SThierry Reding <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 94063944891SThierry Reding interrupt-names = "doorbell", "shared0", "shared1", "shared2", 94163944891SThierry Reding "shared3", "shared4", "shared5", "shared6", 94263944891SThierry Reding "shared7"; 94363944891SThierry Reding #mbox-cells = <2>; 94463944891SThierry Reding }; 94563944891SThierry Reding 946610cdf31SThierry Reding ethernet@6800000 { 947610cdf31SThierry Reding compatible = "nvidia,tegra234-mgbe"; 948610cdf31SThierry Reding reg = <0x06800000 0x10000>, 949610cdf31SThierry Reding <0x06810000 0x10000>, 950610cdf31SThierry Reding <0x068a0000 0x10000>; 951610cdf31SThierry Reding reg-names = "hypervisor", "mac", "xpcs"; 952610cdf31SThierry Reding interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>; 953610cdf31SThierry Reding interrupt-names = "common"; 954610cdf31SThierry Reding clocks = <&bpmp TEGRA234_CLK_MGBE0_APP>, 955610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE0_MAC>, 956610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE0_MAC_DIVIDER>, 957610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE0_PTP_REF>, 958610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT_M>, 959610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT>, 960610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE0_TX>, 961610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE0_EEE_PCS>, 962610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_INPUT>, 963610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_M>, 964610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE0_RX_PCS>, 965610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE0_TX_PCS>; 966610cdf31SThierry Reding clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", 967610cdf31SThierry Reding "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", 968610cdf31SThierry Reding "rx-pcs", "tx-pcs"; 969610cdf31SThierry Reding resets = <&bpmp TEGRA234_RESET_MGBE0_MAC>, 970610cdf31SThierry Reding <&bpmp TEGRA234_RESET_MGBE0_PCS>; 971610cdf31SThierry Reding reset-names = "mac", "pcs"; 972610cdf31SThierry Reding interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEARD &emc>, 973610cdf31SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_MGBEAWR &emc>; 974610cdf31SThierry Reding interconnect-names = "dma-mem", "write"; 975610cdf31SThierry Reding iommus = <&smmu_niso0 TEGRA234_SID_MGBE>; 976610cdf31SThierry Reding power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEA>; 977610cdf31SThierry Reding status = "disabled"; 978610cdf31SThierry Reding }; 979610cdf31SThierry Reding 980610cdf31SThierry Reding ethernet@6900000 { 981610cdf31SThierry Reding compatible = "nvidia,tegra234-mgbe"; 982610cdf31SThierry Reding reg = <0x06900000 0x10000>, 983610cdf31SThierry Reding <0x06910000 0x10000>, 984610cdf31SThierry Reding <0x069a0000 0x10000>; 985610cdf31SThierry Reding reg-names = "hypervisor", "mac", "xpcs"; 986610cdf31SThierry Reding interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>; 987610cdf31SThierry Reding interrupt-names = "common"; 988610cdf31SThierry Reding clocks = <&bpmp TEGRA234_CLK_MGBE1_APP>, 989610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE1_MAC>, 990610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE1_MAC_DIVIDER>, 991610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE1_PTP_REF>, 992610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE1_RX_INPUT_M>, 993610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE1_RX_INPUT>, 994610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE1_TX>, 995610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE1_EEE_PCS>, 996610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE1_RX_PCS_INPUT>, 997610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE1_RX_PCS_M>, 998610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE1_RX_PCS>, 999610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE1_TX_PCS>; 1000610cdf31SThierry Reding clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", 1001610cdf31SThierry Reding "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", 1002610cdf31SThierry Reding "rx-pcs", "tx-pcs"; 1003610cdf31SThierry Reding resets = <&bpmp TEGRA234_RESET_MGBE1_MAC>, 1004610cdf31SThierry Reding <&bpmp TEGRA234_RESET_MGBE1_PCS>; 1005610cdf31SThierry Reding reset-names = "mac", "pcs"; 1006610cdf31SThierry Reding interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEBRD &emc>, 1007610cdf31SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_MGBEBWR &emc>; 1008610cdf31SThierry Reding interconnect-names = "dma-mem", "write"; 1009610cdf31SThierry Reding iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF1>; 1010610cdf31SThierry Reding power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEB>; 1011610cdf31SThierry Reding status = "disabled"; 1012610cdf31SThierry Reding }; 1013610cdf31SThierry Reding 1014610cdf31SThierry Reding ethernet@6a00000 { 1015610cdf31SThierry Reding compatible = "nvidia,tegra234-mgbe"; 1016610cdf31SThierry Reding reg = <0x06a00000 0x10000>, 1017610cdf31SThierry Reding <0x06a10000 0x10000>, 1018610cdf31SThierry Reding <0x06aa0000 0x10000>; 1019610cdf31SThierry Reding reg-names = "hypervisor", "mac", "xpcs"; 1020610cdf31SThierry Reding interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>; 1021610cdf31SThierry Reding interrupt-names = "common"; 1022610cdf31SThierry Reding clocks = <&bpmp TEGRA234_CLK_MGBE2_APP>, 1023610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE2_MAC>, 1024610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE2_MAC_DIVIDER>, 1025610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE2_PTP_REF>, 1026610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE2_RX_INPUT_M>, 1027610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE2_RX_INPUT>, 1028610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE2_TX>, 1029610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE2_EEE_PCS>, 1030610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE2_RX_PCS_INPUT>, 1031610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE2_RX_PCS_M>, 1032610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE2_RX_PCS>, 1033610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE2_TX_PCS>; 1034610cdf31SThierry Reding clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", 1035610cdf31SThierry Reding "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", 1036610cdf31SThierry Reding "rx-pcs", "tx-pcs"; 1037610cdf31SThierry Reding resets = <&bpmp TEGRA234_RESET_MGBE2_MAC>, 1038610cdf31SThierry Reding <&bpmp TEGRA234_RESET_MGBE2_PCS>; 1039610cdf31SThierry Reding reset-names = "mac", "pcs"; 1040610cdf31SThierry Reding interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBECRD &emc>, 1041610cdf31SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_MGBECWR &emc>; 1042610cdf31SThierry Reding interconnect-names = "dma-mem", "write"; 1043610cdf31SThierry Reding iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF2>; 1044610cdf31SThierry Reding power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEC>; 1045610cdf31SThierry Reding status = "disabled"; 1046610cdf31SThierry Reding }; 1047610cdf31SThierry Reding 1048610cdf31SThierry Reding ethernet@6b00000 { 1049610cdf31SThierry Reding compatible = "nvidia,tegra234-mgbe"; 1050610cdf31SThierry Reding reg = <0x06b00000 0x10000>, 1051610cdf31SThierry Reding <0x06b10000 0x10000>, 1052610cdf31SThierry Reding <0x06ba0000 0x10000>; 1053610cdf31SThierry Reding reg-names = "hypervisor", "mac", "xpcs"; 1054610cdf31SThierry Reding interrupts = <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 1055610cdf31SThierry Reding interrupt-names = "common"; 1056610cdf31SThierry Reding clocks = <&bpmp TEGRA234_CLK_MGBE3_APP>, 1057610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE3_MAC>, 1058610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE3_MAC_DIVIDER>, 1059610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE3_PTP_REF>, 1060610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE3_RX_INPUT_M>, 1061610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE3_RX_INPUT>, 1062610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE3_TX>, 1063610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE3_EEE_PCS>, 1064610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE3_RX_PCS_INPUT>, 1065610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE3_RX_PCS_M>, 1066610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE3_RX_PCS>, 1067610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE3_TX_PCS>; 1068610cdf31SThierry Reding clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", 1069610cdf31SThierry Reding "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", 1070610cdf31SThierry Reding "rx-pcs", "tx-pcs"; 1071610cdf31SThierry Reding resets = <&bpmp TEGRA234_RESET_MGBE3_MAC>, 1072610cdf31SThierry Reding <&bpmp TEGRA234_RESET_MGBE3_PCS>; 1073610cdf31SThierry Reding reset-names = "mac", "pcs"; 1074610cdf31SThierry Reding interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEDRD &emc>, 1075610cdf31SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_MGBEDWR &emc>; 1076610cdf31SThierry Reding interconnect-names = "dma-mem", "write"; 1077610cdf31SThierry Reding iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF3>; 1078610cdf31SThierry Reding power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBED>; 1079610cdf31SThierry Reding status = "disabled"; 1080610cdf31SThierry Reding }; 1081610cdf31SThierry Reding 10825710e16aSThierry Reding smmu_niso1: iommu@8000000 { 10835710e16aSThierry Reding compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; 10845710e16aSThierry Reding reg = <0x8000000 0x1000000>, 10855710e16aSThierry Reding <0x7000000 0x1000000>; 10865710e16aSThierry Reding interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 10875710e16aSThierry Reding <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, 10885710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 10895710e16aSThierry Reding <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, 10905710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 10915710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 10925710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 10935710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 10945710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 10955710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 10965710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 10975710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 10985710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 10995710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11005710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11015710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11025710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11035710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11045710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11055710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11065710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11075710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11085710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11095710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11105710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11115710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11125710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11135710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11145710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11155710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11165710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11175710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11185710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11195710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11205710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11215710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11225710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11235710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11245710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11255710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11265710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11275710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11285710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11295710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11305710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11315710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11325710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11335710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11345710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11355710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11365710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11375710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11385710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11395710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11405710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11415710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11425710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11435710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11445710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11455710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11465710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11475710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11485710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11495710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11505710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11515710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11525710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11535710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11545710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11555710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11565710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11575710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11585710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11595710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11605710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11615710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11625710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11635710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11645710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11655710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11665710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11675710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11685710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11695710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11705710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11715710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11725710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11735710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11745710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11755710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11765710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11775710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11785710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11795710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11805710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11815710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11825710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11835710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11845710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11855710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11865710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11875710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11885710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11895710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11905710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11915710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11925710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11935710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11945710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11955710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11965710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11975710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11985710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 11995710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12005710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12015710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12025710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12035710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12045710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12055710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12065710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12075710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12085710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12095710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12105710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12115710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12125710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12135710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12145710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12155710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 12165710e16aSThierry Reding stream-match-mask = <0x7f80>; 12175710e16aSThierry Reding #global-interrupts = <2>; 12185710e16aSThierry Reding #iommu-cells = <1>; 12195710e16aSThierry Reding 12205710e16aSThierry Reding nvidia,memory-controller = <&mc>; 12215710e16aSThierry Reding status = "okay"; 12225710e16aSThierry Reding }; 12235710e16aSThierry Reding 1224302e1540SSumit Gupta sce-fabric@b600000 { 1225302e1540SSumit Gupta compatible = "nvidia,tegra234-sce-fabric"; 1226302e1540SSumit Gupta reg = <0xb600000 0x40000>; 1227302e1540SSumit Gupta interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 1228302e1540SSumit Gupta status = "okay"; 1229302e1540SSumit Gupta }; 1230302e1540SSumit Gupta 1231302e1540SSumit Gupta rce-fabric@be00000 { 1232302e1540SSumit Gupta compatible = "nvidia,tegra234-rce-fabric"; 1233302e1540SSumit Gupta reg = <0xbe00000 0x40000>; 1234302e1540SSumit Gupta interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 1235302e1540SSumit Gupta status = "okay"; 1236302e1540SSumit Gupta }; 1237302e1540SSumit Gupta 1238ec142c44SVidya Sagar p2u_hsio_0: phy@3e00000 { 1239ec142c44SVidya Sagar compatible = "nvidia,tegra234-p2u"; 1240ec142c44SVidya Sagar reg = <0x03e00000 0x10000>; 1241ec142c44SVidya Sagar reg-names = "ctl"; 1242ec142c44SVidya Sagar 1243ec142c44SVidya Sagar #phy-cells = <0>; 1244ec142c44SVidya Sagar }; 1245ec142c44SVidya Sagar 1246ec142c44SVidya Sagar p2u_hsio_1: phy@3e10000 { 1247ec142c44SVidya Sagar compatible = "nvidia,tegra234-p2u"; 1248ec142c44SVidya Sagar reg = <0x03e10000 0x10000>; 1249ec142c44SVidya Sagar reg-names = "ctl"; 1250ec142c44SVidya Sagar 1251ec142c44SVidya Sagar #phy-cells = <0>; 1252ec142c44SVidya Sagar }; 1253ec142c44SVidya Sagar 1254ec142c44SVidya Sagar p2u_hsio_2: phy@3e20000 { 1255ec142c44SVidya Sagar compatible = "nvidia,tegra234-p2u"; 1256ec142c44SVidya Sagar reg = <0x03e20000 0x10000>; 1257ec142c44SVidya Sagar reg-names = "ctl"; 1258ec142c44SVidya Sagar 1259ec142c44SVidya Sagar #phy-cells = <0>; 1260ec142c44SVidya Sagar }; 1261ec142c44SVidya Sagar 1262ec142c44SVidya Sagar p2u_hsio_3: phy@3e30000 { 1263ec142c44SVidya Sagar compatible = "nvidia,tegra234-p2u"; 1264ec142c44SVidya Sagar reg = <0x03e30000 0x10000>; 1265ec142c44SVidya Sagar reg-names = "ctl"; 1266ec142c44SVidya Sagar 1267ec142c44SVidya Sagar #phy-cells = <0>; 1268ec142c44SVidya Sagar }; 1269ec142c44SVidya Sagar 1270ec142c44SVidya Sagar p2u_hsio_4: phy@3e40000 { 1271ec142c44SVidya Sagar compatible = "nvidia,tegra234-p2u"; 1272ec142c44SVidya Sagar reg = <0x03e40000 0x10000>; 1273ec142c44SVidya Sagar reg-names = "ctl"; 1274ec142c44SVidya Sagar 1275ec142c44SVidya Sagar #phy-cells = <0>; 1276ec142c44SVidya Sagar }; 1277ec142c44SVidya Sagar 1278ec142c44SVidya Sagar p2u_hsio_5: phy@3e50000 { 1279ec142c44SVidya Sagar compatible = "nvidia,tegra234-p2u"; 1280ec142c44SVidya Sagar reg = <0x03e50000 0x10000>; 1281ec142c44SVidya Sagar reg-names = "ctl"; 1282ec142c44SVidya Sagar 1283ec142c44SVidya Sagar #phy-cells = <0>; 1284ec142c44SVidya Sagar }; 1285ec142c44SVidya Sagar 1286ec142c44SVidya Sagar p2u_hsio_6: phy@3e60000 { 1287ec142c44SVidya Sagar compatible = "nvidia,tegra234-p2u"; 1288ec142c44SVidya Sagar reg = <0x03e60000 0x10000>; 1289ec142c44SVidya Sagar reg-names = "ctl"; 1290ec142c44SVidya Sagar 1291ec142c44SVidya Sagar #phy-cells = <0>; 1292ec142c44SVidya Sagar }; 1293ec142c44SVidya Sagar 1294ec142c44SVidya Sagar p2u_hsio_7: phy@3e70000 { 1295ec142c44SVidya Sagar compatible = "nvidia,tegra234-p2u"; 1296ec142c44SVidya Sagar reg = <0x03e70000 0x10000>; 1297ec142c44SVidya Sagar reg-names = "ctl"; 1298ec142c44SVidya Sagar 1299ec142c44SVidya Sagar #phy-cells = <0>; 1300ec142c44SVidya Sagar }; 1301ec142c44SVidya Sagar 1302ec142c44SVidya Sagar p2u_nvhs_0: phy@3e90000 { 1303ec142c44SVidya Sagar compatible = "nvidia,tegra234-p2u"; 1304ec142c44SVidya Sagar reg = <0x03e90000 0x10000>; 1305ec142c44SVidya Sagar reg-names = "ctl"; 1306ec142c44SVidya Sagar 1307ec142c44SVidya Sagar #phy-cells = <0>; 1308ec142c44SVidya Sagar }; 1309ec142c44SVidya Sagar 1310ec142c44SVidya Sagar p2u_nvhs_1: phy@3ea0000 { 1311ec142c44SVidya Sagar compatible = "nvidia,tegra234-p2u"; 1312ec142c44SVidya Sagar reg = <0x03ea0000 0x10000>; 1313ec142c44SVidya Sagar reg-names = "ctl"; 1314ec142c44SVidya Sagar 1315ec142c44SVidya Sagar #phy-cells = <0>; 1316ec142c44SVidya Sagar }; 1317ec142c44SVidya Sagar 1318ec142c44SVidya Sagar p2u_nvhs_2: phy@3eb0000 { 1319ec142c44SVidya Sagar compatible = "nvidia,tegra234-p2u"; 1320ec142c44SVidya Sagar reg = <0x03eb0000 0x10000>; 1321ec142c44SVidya Sagar reg-names = "ctl"; 1322ec142c44SVidya Sagar 1323ec142c44SVidya Sagar #phy-cells = <0>; 1324ec142c44SVidya Sagar }; 1325ec142c44SVidya Sagar 1326ec142c44SVidya Sagar p2u_nvhs_3: phy@3ec0000 { 1327ec142c44SVidya Sagar compatible = "nvidia,tegra234-p2u"; 1328ec142c44SVidya Sagar reg = <0x03ec0000 0x10000>; 1329ec142c44SVidya Sagar reg-names = "ctl"; 1330ec142c44SVidya Sagar 1331ec142c44SVidya Sagar #phy-cells = <0>; 1332ec142c44SVidya Sagar }; 1333ec142c44SVidya Sagar 1334ec142c44SVidya Sagar p2u_nvhs_4: phy@3ed0000 { 1335ec142c44SVidya Sagar compatible = "nvidia,tegra234-p2u"; 1336ec142c44SVidya Sagar reg = <0x03ed0000 0x10000>; 1337ec142c44SVidya Sagar reg-names = "ctl"; 1338ec142c44SVidya Sagar 1339ec142c44SVidya Sagar #phy-cells = <0>; 1340ec142c44SVidya Sagar }; 1341ec142c44SVidya Sagar 1342ec142c44SVidya Sagar p2u_nvhs_5: phy@3ee0000 { 1343ec142c44SVidya Sagar compatible = "nvidia,tegra234-p2u"; 1344ec142c44SVidya Sagar reg = <0x03ee0000 0x10000>; 1345ec142c44SVidya Sagar reg-names = "ctl"; 1346ec142c44SVidya Sagar 1347ec142c44SVidya Sagar #phy-cells = <0>; 1348ec142c44SVidya Sagar }; 1349ec142c44SVidya Sagar 1350ec142c44SVidya Sagar p2u_nvhs_6: phy@3ef0000 { 1351ec142c44SVidya Sagar compatible = "nvidia,tegra234-p2u"; 1352ec142c44SVidya Sagar reg = <0x03ef0000 0x10000>; 1353ec142c44SVidya Sagar reg-names = "ctl"; 1354ec142c44SVidya Sagar 1355ec142c44SVidya Sagar #phy-cells = <0>; 1356ec142c44SVidya Sagar }; 1357ec142c44SVidya Sagar 1358ec142c44SVidya Sagar p2u_nvhs_7: phy@3f00000 { 1359ec142c44SVidya Sagar compatible = "nvidia,tegra234-p2u"; 1360ec142c44SVidya Sagar reg = <0x03f00000 0x10000>; 1361ec142c44SVidya Sagar reg-names = "ctl"; 1362ec142c44SVidya Sagar 1363ec142c44SVidya Sagar #phy-cells = <0>; 1364ec142c44SVidya Sagar }; 1365ec142c44SVidya Sagar 1366ec142c44SVidya Sagar p2u_gbe_0: phy@3f20000 { 1367ec142c44SVidya Sagar compatible = "nvidia,tegra234-p2u"; 1368ec142c44SVidya Sagar reg = <0x03f20000 0x10000>; 1369ec142c44SVidya Sagar reg-names = "ctl"; 1370ec142c44SVidya Sagar 1371ec142c44SVidya Sagar #phy-cells = <0>; 1372ec142c44SVidya Sagar }; 1373ec142c44SVidya Sagar 1374ec142c44SVidya Sagar p2u_gbe_1: phy@3f30000 { 1375ec142c44SVidya Sagar compatible = "nvidia,tegra234-p2u"; 1376ec142c44SVidya Sagar reg = <0x03f30000 0x10000>; 1377ec142c44SVidya Sagar reg-names = "ctl"; 1378ec142c44SVidya Sagar 1379ec142c44SVidya Sagar #phy-cells = <0>; 1380ec142c44SVidya Sagar }; 1381ec142c44SVidya Sagar 1382ec142c44SVidya Sagar p2u_gbe_2: phy@3f40000 { 1383ec142c44SVidya Sagar compatible = "nvidia,tegra234-p2u"; 1384ec142c44SVidya Sagar reg = <0x03f40000 0x10000>; 1385ec142c44SVidya Sagar reg-names = "ctl"; 1386ec142c44SVidya Sagar 1387ec142c44SVidya Sagar #phy-cells = <0>; 1388ec142c44SVidya Sagar }; 1389ec142c44SVidya Sagar 1390ec142c44SVidya Sagar p2u_gbe_3: phy@3f50000 { 1391ec142c44SVidya Sagar compatible = "nvidia,tegra234-p2u"; 1392ec142c44SVidya Sagar reg = <0x03f50000 0x10000>; 1393ec142c44SVidya Sagar reg-names = "ctl"; 1394ec142c44SVidya Sagar 1395ec142c44SVidya Sagar #phy-cells = <0>; 1396ec142c44SVidya Sagar }; 1397ec142c44SVidya Sagar 1398ec142c44SVidya Sagar p2u_gbe_4: phy@3f60000 { 1399ec142c44SVidya Sagar compatible = "nvidia,tegra234-p2u"; 1400ec142c44SVidya Sagar reg = <0x03f60000 0x10000>; 1401ec142c44SVidya Sagar reg-names = "ctl"; 1402ec142c44SVidya Sagar 1403ec142c44SVidya Sagar #phy-cells = <0>; 1404ec142c44SVidya Sagar }; 1405ec142c44SVidya Sagar 1406ec142c44SVidya Sagar p2u_gbe_5: phy@3f70000 { 1407ec142c44SVidya Sagar compatible = "nvidia,tegra234-p2u"; 1408ec142c44SVidya Sagar reg = <0x03f70000 0x10000>; 1409ec142c44SVidya Sagar reg-names = "ctl"; 1410ec142c44SVidya Sagar 1411ec142c44SVidya Sagar #phy-cells = <0>; 1412ec142c44SVidya Sagar }; 1413ec142c44SVidya Sagar 1414ec142c44SVidya Sagar p2u_gbe_6: phy@3f80000 { 1415ec142c44SVidya Sagar compatible = "nvidia,tegra234-p2u"; 1416ec142c44SVidya Sagar reg = <0x03f80000 0x10000>; 1417ec142c44SVidya Sagar reg-names = "ctl"; 1418ec142c44SVidya Sagar 1419ec142c44SVidya Sagar #phy-cells = <0>; 1420ec142c44SVidya Sagar }; 1421ec142c44SVidya Sagar 1422ec142c44SVidya Sagar p2u_gbe_7: phy@3f90000 { 1423ec142c44SVidya Sagar compatible = "nvidia,tegra234-p2u"; 1424ec142c44SVidya Sagar reg = <0x03f90000 0x10000>; 1425ec142c44SVidya Sagar reg-names = "ctl"; 1426ec142c44SVidya Sagar 1427ec142c44SVidya Sagar #phy-cells = <0>; 1428ec142c44SVidya Sagar }; 1429ec142c44SVidya Sagar 143063944891SThierry Reding hsp_aon: hsp@c150000 { 143163944891SThierry Reding compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; 143263944891SThierry Reding reg = <0x0c150000 0x90000>; 143363944891SThierry Reding interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 143463944891SThierry Reding <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 143563944891SThierry Reding <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 143663944891SThierry Reding <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 143763944891SThierry Reding /* 143863944891SThierry Reding * Shared interrupt 0 is routed only to AON/SPE, so 143963944891SThierry Reding * we only have 4 shared interrupts for the CCPLEX. 144063944891SThierry Reding */ 144163944891SThierry Reding interrupt-names = "shared1", "shared2", "shared3", "shared4"; 144263944891SThierry Reding #mbox-cells = <2>; 144363944891SThierry Reding }; 144463944891SThierry Reding 1445156af9deSAkhil R gen2_i2c: i2c@c240000 { 1446156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 1447156af9deSAkhil R reg = <0xc240000 0x100>; 1448156af9deSAkhil R interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1449156af9deSAkhil R status = "disabled"; 1450156af9deSAkhil R clock-frequency = <100000>; 1451156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C2 1452156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 1453156af9deSAkhil R clock-names = "div-clk", "parent"; 1454156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C2>; 1455156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 1456156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C2>; 1457156af9deSAkhil R reset-names = "i2c"; 1458156af9deSAkhil R }; 1459156af9deSAkhil R 1460156af9deSAkhil R gen8_i2c: i2c@c250000 { 1461156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 1462156af9deSAkhil R reg = <0xc250000 0x100>; 1463156af9deSAkhil R nvidia,hw-instance-id = <0x7>; 1464156af9deSAkhil R interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1465156af9deSAkhil R status = "disabled"; 1466156af9deSAkhil R clock-frequency = <400000>; 1467156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C8 1468156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 1469156af9deSAkhil R clock-names = "div-clk", "parent"; 1470156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C8>; 1471156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 1472156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C8>; 1473156af9deSAkhil R reset-names = "i2c"; 1474156af9deSAkhil R }; 1475156af9deSAkhil R 147663944891SThierry Reding rtc@c2a0000 { 147763944891SThierry Reding compatible = "nvidia,tegra234-rtc", "nvidia,tegra20-rtc"; 147863944891SThierry Reding reg = <0x0c2a0000 0x10000>; 147963944891SThierry Reding interrupt-parent = <&pmc>; 148063944891SThierry Reding interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 1481e537addeSMikko Perttunen clocks = <&bpmp TEGRA234_CLK_CLK_32K>; 1482e537addeSMikko Perttunen clock-names = "rtc"; 148363944891SThierry Reding status = "disabled"; 148463944891SThierry Reding }; 148563944891SThierry Reding 1486f0e12668SThierry Reding gpio_aon: gpio@c2f0000 { 1487f0e12668SThierry Reding compatible = "nvidia,tegra234-gpio-aon"; 1488f0e12668SThierry Reding reg-names = "security", "gpio"; 1489f0e12668SThierry Reding reg = <0x0c2f0000 0x1000>, 1490f0e12668SThierry Reding <0x0c2f1000 0x1000>; 1491f0e12668SThierry Reding interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1492f0e12668SThierry Reding <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1493f0e12668SThierry Reding <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1494f0e12668SThierry Reding <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 1495f0e12668SThierry Reding #interrupt-cells = <2>; 1496f0e12668SThierry Reding interrupt-controller; 1497f0e12668SThierry Reding #gpio-cells = <2>; 1498f0e12668SThierry Reding gpio-controller; 1499f0e12668SThierry Reding }; 1500f0e12668SThierry Reding 150163944891SThierry Reding pmc: pmc@c360000 { 150263944891SThierry Reding compatible = "nvidia,tegra234-pmc"; 150363944891SThierry Reding reg = <0x0c360000 0x10000>, 150463944891SThierry Reding <0x0c370000 0x10000>, 150563944891SThierry Reding <0x0c380000 0x10000>, 150663944891SThierry Reding <0x0c390000 0x10000>, 150763944891SThierry Reding <0x0c3a0000 0x10000>; 150863944891SThierry Reding reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 150963944891SThierry Reding 151063944891SThierry Reding #interrupt-cells = <2>; 151163944891SThierry Reding interrupt-controller; 151263944891SThierry Reding }; 151363944891SThierry Reding 1514302e1540SSumit Gupta aon-fabric@c600000 { 1515302e1540SSumit Gupta compatible = "nvidia,tegra234-aon-fabric"; 1516302e1540SSumit Gupta reg = <0xc600000 0x40000>; 1517302e1540SSumit Gupta interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 1518302e1540SSumit Gupta status = "okay"; 1519302e1540SSumit Gupta }; 1520302e1540SSumit Gupta 1521302e1540SSumit Gupta bpmp-fabric@d600000 { 1522302e1540SSumit Gupta compatible = "nvidia,tegra234-bpmp-fabric"; 1523302e1540SSumit Gupta reg = <0xd600000 0x40000>; 1524302e1540SSumit Gupta interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1525302e1540SSumit Gupta status = "okay"; 1526302e1540SSumit Gupta }; 1527302e1540SSumit Gupta 1528302e1540SSumit Gupta dce-fabric@de00000 { 1529302e1540SSumit Gupta compatible = "nvidia,tegra234-sce-fabric"; 1530302e1540SSumit Gupta reg = <0xde00000 0x40000>; 1531302e1540SSumit Gupta interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>; 1532302e1540SSumit Gupta status = "okay"; 1533302e1540SSumit Gupta }; 1534302e1540SSumit Gupta 153563944891SThierry Reding gic: interrupt-controller@f400000 { 153663944891SThierry Reding compatible = "arm,gic-v3"; 153763944891SThierry Reding reg = <0x0f400000 0x010000>, /* GICD */ 153863944891SThierry Reding <0x0f440000 0x200000>; /* GICR */ 153963944891SThierry Reding interrupt-parent = <&gic>; 154063944891SThierry Reding interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 154163944891SThierry Reding 154263944891SThierry Reding #redistributor-regions = <1>; 154363944891SThierry Reding #interrupt-cells = <3>; 154463944891SThierry Reding interrupt-controller; 154563944891SThierry Reding }; 15465710e16aSThierry Reding 15475710e16aSThierry Reding smmu_iso: iommu@10000000{ 15485710e16aSThierry Reding compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; 15495710e16aSThierry Reding reg = <0x10000000 0x1000000>; 15505710e16aSThierry Reding interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 15515710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 15525710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 15535710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 15545710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 15555710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 15565710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 15575710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 15585710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 15595710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 15605710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 15615710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 15625710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 15635710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 15645710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 15655710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 15665710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 15675710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 15685710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 15695710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 15705710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 15715710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 15725710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 15735710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 15745710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 15755710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 15765710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 15775710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 15785710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 15795710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 15805710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 15815710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 15825710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 15835710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 15845710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 15855710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 15865710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 15875710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 15885710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 15895710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 15905710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 15915710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 15925710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 15935710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 15945710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 15955710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 15965710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 15975710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 15985710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 15995710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16005710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16015710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16025710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16035710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16045710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16055710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16065710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16075710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16085710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16095710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16105710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16115710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16125710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16135710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16145710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16155710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16165710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16175710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16185710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16195710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16205710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16215710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16225710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16235710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16245710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16255710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16265710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16275710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16285710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16295710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16305710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16315710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16325710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16335710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16345710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16355710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16365710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16375710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16385710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16395710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16405710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16415710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16425710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16435710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16445710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16455710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16465710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16475710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16485710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16495710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16505710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16515710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16525710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16535710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16545710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16555710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16565710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16575710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16585710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16595710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16605710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16615710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16625710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16635710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16645710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16655710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16665710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16675710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16685710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16695710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16705710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16715710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16725710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16735710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16745710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16755710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16765710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16775710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16785710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 16795710e16aSThierry Reding stream-match-mask = <0x7f80>; 16805710e16aSThierry Reding #global-interrupts = <1>; 16815710e16aSThierry Reding #iommu-cells = <1>; 16825710e16aSThierry Reding 16835710e16aSThierry Reding nvidia,memory-controller = <&mc>; 16845710e16aSThierry Reding status = "okay"; 16855710e16aSThierry Reding }; 16865710e16aSThierry Reding 16875710e16aSThierry Reding smmu_niso0: iommu@12000000 { 16885710e16aSThierry Reding compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; 16895710e16aSThierry Reding reg = <0x12000000 0x1000000>, 16905710e16aSThierry Reding <0x11000000 0x1000000>; 16915710e16aSThierry Reding interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 16925710e16aSThierry Reding <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 16935710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 16945710e16aSThierry Reding <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 16955710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 16965710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 16975710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 16985710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 16995710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17005710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17015710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17025710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17035710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17045710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17055710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17065710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17075710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17085710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17095710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17105710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17115710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17125710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17135710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17145710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17155710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17165710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17175710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17185710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17195710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17205710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17215710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17225710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17235710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17245710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17255710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17265710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17275710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17285710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17295710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17305710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17315710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17325710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17335710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17345710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17355710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17365710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17375710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17385710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17395710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17405710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17415710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17425710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17435710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17445710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17455710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17465710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17475710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17485710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17495710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17505710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17515710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17525710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17535710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17545710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17555710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17565710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17575710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17585710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17595710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17605710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17615710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17625710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17635710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17645710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17655710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17665710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17675710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17685710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17695710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17705710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17715710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17725710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17735710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17745710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17755710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17765710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17775710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17785710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17795710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17805710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17815710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17825710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17835710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17845710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17855710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17865710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17875710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17885710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17895710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17905710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17915710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17925710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17935710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17945710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17955710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17965710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17975710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17985710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17995710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18005710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18015710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18025710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18035710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18045710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18055710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18065710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18075710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18085710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18095710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18105710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18115710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18125710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18135710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18145710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18155710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18165710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18175710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18185710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18195710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18205710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 18215710e16aSThierry Reding stream-match-mask = <0x7f80>; 18225710e16aSThierry Reding #global-interrupts = <2>; 18235710e16aSThierry Reding #iommu-cells = <1>; 18245710e16aSThierry Reding 18255710e16aSThierry Reding nvidia,memory-controller = <&mc>; 18265710e16aSThierry Reding status = "okay"; 18275710e16aSThierry Reding }; 1828302e1540SSumit Gupta 1829302e1540SSumit Gupta cbb-fabric@13a00000 { 1830302e1540SSumit Gupta compatible = "nvidia,tegra234-cbb-fabric"; 1831302e1540SSumit Gupta reg = <0x13a00000 0x400000>; 1832302e1540SSumit Gupta interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 1833302e1540SSumit Gupta status = "okay"; 1834302e1540SSumit Gupta }; 183563944891SThierry Reding }; 183663944891SThierry Reding 1837962c400dSSumit Gupta ccplex@e000000 { 1838962c400dSSumit Gupta compatible = "nvidia,tegra234-ccplex-cluster"; 1839962c400dSSumit Gupta reg = <0x0 0x0e000000 0x0 0x5ffff>; 1840962c400dSSumit Gupta nvidia,bpmp = <&bpmp>; 1841962c400dSSumit Gupta status = "okay"; 1842962c400dSSumit Gupta }; 1843962c400dSSumit Gupta 1844ec142c44SVidya Sagar pcie@140a0000 { 1845ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie"; 1846ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CA>; 1847ec142c44SVidya Sagar reg = <0x00 0x140a0000 0x0 0x00020000>, /* appl registers (128K) */ 1848ec142c44SVidya Sagar <0x00 0x2a000000 0x0 0x00040000>, /* configuration space (256K) */ 1849ec142c44SVidya Sagar <0x00 0x2a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1850ec142c44SVidya Sagar <0x00 0x2a080000 0x0 0x00040000>; /* DBI reg space (256K) */ 1851ec142c44SVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 1852ec142c44SVidya Sagar 1853ec142c44SVidya Sagar #address-cells = <3>; 1854ec142c44SVidya Sagar #size-cells = <2>; 1855ec142c44SVidya Sagar device_type = "pci"; 1856ec142c44SVidya Sagar num-lanes = <4>; 1857ec142c44SVidya Sagar num-viewport = <8>; 1858ec142c44SVidya Sagar linux,pci-domain = <8>; 1859ec142c44SVidya Sagar 1860ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX2_C8_CORE>; 1861ec142c44SVidya Sagar clock-names = "core"; 1862ec142c44SVidya Sagar 1863ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX2_CORE_8_APB>, 1864ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX2_CORE_8>; 1865ec142c44SVidya Sagar reset-names = "apb", "core"; 1866ec142c44SVidya Sagar 1867ec142c44SVidya Sagar interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1868ec142c44SVidya Sagar <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1869ec142c44SVidya Sagar interrupt-names = "intr", "msi"; 1870ec142c44SVidya Sagar 1871ec142c44SVidya Sagar #interrupt-cells = <1>; 1872ec142c44SVidya Sagar interrupt-map-mask = <0 0 0 0>; 1873ec142c44SVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1874ec142c44SVidya Sagar 1875ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 8>; 1876ec142c44SVidya Sagar 1877ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 1878ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 1879ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 1880ec142c44SVidya Sagar 1881ec142c44SVidya Sagar bus-range = <0x0 0xff>; 1882ec142c44SVidya Sagar 1883ec142c44SVidya Sagar ranges = <0x43000000 0x32 0x40000000 0x32 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 1884ec142c44SVidya Sagar <0x02000000 0x0 0x40000000 0x35 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 1885ec142c44SVidya Sagar <0x01000000 0x0 0x2a100000 0x00 0x2a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 1886ec142c44SVidya Sagar 1887ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE8AR &emc>, 1888ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE8AW &emc>; 1889ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 1890ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE8 0x1000>; 1891ec142c44SVidya Sagar iommu-map-mask = <0x0>; 1892ec142c44SVidya Sagar dma-coherent; 1893ec142c44SVidya Sagar 1894ec142c44SVidya Sagar status = "disabled"; 1895ec142c44SVidya Sagar }; 1896ec142c44SVidya Sagar 1897ec142c44SVidya Sagar pcie@140c0000 { 1898ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie"; 1899ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CB>; 1900ec142c44SVidya Sagar reg = <0x00 0x140c0000 0x0 0x00020000>, /* appl registers (128K) */ 1901ec142c44SVidya Sagar <0x00 0x2c000000 0x0 0x00040000>, /* configuration space (256K) */ 1902ec142c44SVidya Sagar <0x00 0x2c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1903ec142c44SVidya Sagar <0x00 0x2c080000 0x0 0x00040000>; /* DBI reg space (256K) */ 1904ec142c44SVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 1905ec142c44SVidya Sagar 1906ec142c44SVidya Sagar #address-cells = <3>; 1907ec142c44SVidya Sagar #size-cells = <2>; 1908ec142c44SVidya Sagar device_type = "pci"; 1909ec142c44SVidya Sagar num-lanes = <4>; 1910ec142c44SVidya Sagar num-viewport = <8>; 1911ec142c44SVidya Sagar linux,pci-domain = <9>; 1912ec142c44SVidya Sagar 1913ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX2_C9_CORE>; 1914ec142c44SVidya Sagar clock-names = "core"; 1915ec142c44SVidya Sagar 1916ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX2_CORE_9_APB>, 1917ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX2_CORE_9>; 1918ec142c44SVidya Sagar reset-names = "apb", "core"; 1919ec142c44SVidya Sagar 1920ec142c44SVidya Sagar interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1921ec142c44SVidya Sagar <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1922ec142c44SVidya Sagar interrupt-names = "intr", "msi"; 1923ec142c44SVidya Sagar 1924ec142c44SVidya Sagar #interrupt-cells = <1>; 1925ec142c44SVidya Sagar interrupt-map-mask = <0 0 0 0>; 1926ec142c44SVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1927ec142c44SVidya Sagar 1928ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 9>; 1929ec142c44SVidya Sagar 1930ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 1931ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 1932ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 1933ec142c44SVidya Sagar 1934ec142c44SVidya Sagar bus-range = <0x0 0xff>; 1935ec142c44SVidya Sagar 1936ec142c44SVidya Sagar ranges = <0x43000000 0x35 0x40000000 0x35 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 1937ec142c44SVidya Sagar <0x02000000 0x0 0x40000000 0x38 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 1938ec142c44SVidya Sagar <0x01000000 0x0 0x2c100000 0x00 0x2c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 1939ec142c44SVidya Sagar 1940ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE9AR &emc>, 1941ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE9AW &emc>; 1942ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 1943ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE9 0x1000>; 1944ec142c44SVidya Sagar iommu-map-mask = <0x0>; 1945ec142c44SVidya Sagar dma-coherent; 1946ec142c44SVidya Sagar 1947ec142c44SVidya Sagar status = "disabled"; 1948ec142c44SVidya Sagar }; 1949ec142c44SVidya Sagar 1950ec142c44SVidya Sagar pcie@140e0000 { 1951ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie"; 1952ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CC>; 1953ec142c44SVidya Sagar reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K) */ 1954ec142c44SVidya Sagar <0x00 0x2e000000 0x0 0x00040000>, /* configuration space (256K) */ 1955ec142c44SVidya Sagar <0x00 0x2e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1956ec142c44SVidya Sagar <0x00 0x2e080000 0x0 0x00040000>; /* DBI reg space (256K) */ 1957ec142c44SVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 1958ec142c44SVidya Sagar 1959ec142c44SVidya Sagar #address-cells = <3>; 1960ec142c44SVidya Sagar #size-cells = <2>; 1961ec142c44SVidya Sagar device_type = "pci"; 1962ec142c44SVidya Sagar num-lanes = <4>; 1963ec142c44SVidya Sagar num-viewport = <8>; 1964ec142c44SVidya Sagar linux,pci-domain = <10>; 1965ec142c44SVidya Sagar 1966ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX2_C10_CORE>; 1967ec142c44SVidya Sagar clock-names = "core"; 1968ec142c44SVidya Sagar 1969ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX2_CORE_10_APB>, 1970ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX2_CORE_10>; 1971ec142c44SVidya Sagar reset-names = "apb", "core"; 1972ec142c44SVidya Sagar 1973ec142c44SVidya Sagar interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1974ec142c44SVidya Sagar <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1975ec142c44SVidya Sagar interrupt-names = "intr", "msi"; 1976ec142c44SVidya Sagar 1977ec142c44SVidya Sagar #interrupt-cells = <1>; 1978ec142c44SVidya Sagar interrupt-map-mask = <0 0 0 0>; 1979ec142c44SVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1980ec142c44SVidya Sagar 1981ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 10>; 1982ec142c44SVidya Sagar 1983ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 1984ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 1985ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 1986ec142c44SVidya Sagar 1987ec142c44SVidya Sagar bus-range = <0x0 0xff>; 1988ec142c44SVidya Sagar 1989ec142c44SVidya Sagar ranges = <0x43000000 0x38 0x40000000 0x38 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 1990ec142c44SVidya Sagar <0x02000000 0x0 0x40000000 0x3b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 1991ec142c44SVidya Sagar <0x01000000 0x0 0x2e100000 0x00 0x2e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 1992ec142c44SVidya Sagar 1993ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE10AR &emc>, 1994ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE10AW &emc>; 1995ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 1996ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>; 1997ec142c44SVidya Sagar iommu-map-mask = <0x0>; 1998ec142c44SVidya Sagar dma-coherent; 1999ec142c44SVidya Sagar 2000ec142c44SVidya Sagar status = "disabled"; 2001ec142c44SVidya Sagar }; 2002ec142c44SVidya Sagar 2003ec142c44SVidya Sagar pcie@14100000 { 2004ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie"; 2005ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>; 2006ec142c44SVidya Sagar reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */ 2007ec142c44SVidya Sagar <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */ 2008ec142c44SVidya Sagar <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2009ec142c44SVidya Sagar <0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2010ec142c44SVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 2011ec142c44SVidya Sagar 2012ec142c44SVidya Sagar #address-cells = <3>; 2013ec142c44SVidya Sagar #size-cells = <2>; 2014ec142c44SVidya Sagar device_type = "pci"; 2015ec142c44SVidya Sagar num-lanes = <1>; 2016ec142c44SVidya Sagar num-viewport = <8>; 2017ec142c44SVidya Sagar linux,pci-domain = <1>; 2018ec142c44SVidya Sagar 2019ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX0_C1_CORE>; 2020ec142c44SVidya Sagar clock-names = "core"; 2021ec142c44SVidya Sagar 2022ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX0_CORE_1_APB>, 2023ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX0_CORE_1>; 2024ec142c44SVidya Sagar reset-names = "apb", "core"; 2025ec142c44SVidya Sagar 2026ec142c44SVidya Sagar interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2027ec142c44SVidya Sagar <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2028ec142c44SVidya Sagar interrupt-names = "intr", "msi"; 2029ec142c44SVidya Sagar 2030ec142c44SVidya Sagar #interrupt-cells = <1>; 2031ec142c44SVidya Sagar interrupt-map-mask = <0 0 0 0>; 2032ec142c44SVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 2033ec142c44SVidya Sagar 2034ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 1>; 2035ec142c44SVidya Sagar 2036ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2037ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2038ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2039ec142c44SVidya Sagar 2040ec142c44SVidya Sagar bus-range = <0x0 0xff>; 2041ec142c44SVidya Sagar 2042ec142c44SVidya Sagar ranges = <0x43000000 0x20 0x80000000 0x20 0x80000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ 2043ec142c44SVidya Sagar <0x02000000 0x0 0x40000000 0x20 0xa8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2044ec142c44SVidya Sagar <0x01000000 0x0 0x30100000 0x00 0x30100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2045ec142c44SVidya Sagar 2046ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE1R &emc>, 2047ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE1W &emc>; 2048ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2049ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE1 0x1000>; 2050ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2051ec142c44SVidya Sagar dma-coherent; 2052ec142c44SVidya Sagar 2053ec142c44SVidya Sagar status = "disabled"; 2054ec142c44SVidya Sagar }; 2055ec142c44SVidya Sagar 2056ec142c44SVidya Sagar pcie@14120000 { 2057ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie"; 2058ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>; 2059ec142c44SVidya Sagar reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */ 2060ec142c44SVidya Sagar <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */ 2061ec142c44SVidya Sagar <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2062ec142c44SVidya Sagar <0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2063ec142c44SVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 2064ec142c44SVidya Sagar 2065ec142c44SVidya Sagar #address-cells = <3>; 2066ec142c44SVidya Sagar #size-cells = <2>; 2067ec142c44SVidya Sagar device_type = "pci"; 2068ec142c44SVidya Sagar num-lanes = <1>; 2069ec142c44SVidya Sagar num-viewport = <8>; 2070ec142c44SVidya Sagar linux,pci-domain = <2>; 2071ec142c44SVidya Sagar 2072ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX0_C2_CORE>; 2073ec142c44SVidya Sagar clock-names = "core"; 2074ec142c44SVidya Sagar 2075ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX0_CORE_2_APB>, 2076ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX0_CORE_2>; 2077ec142c44SVidya Sagar reset-names = "apb", "core"; 2078ec142c44SVidya Sagar 2079ec142c44SVidya Sagar interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2080ec142c44SVidya Sagar <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2081ec142c44SVidya Sagar interrupt-names = "intr", "msi"; 2082ec142c44SVidya Sagar 2083ec142c44SVidya Sagar #interrupt-cells = <1>; 2084ec142c44SVidya Sagar interrupt-map-mask = <0 0 0 0>; 2085ec142c44SVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 2086ec142c44SVidya Sagar 2087ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 2>; 2088ec142c44SVidya Sagar 2089ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2090ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2091ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2092ec142c44SVidya Sagar 2093ec142c44SVidya Sagar bus-range = <0x0 0xff>; 2094ec142c44SVidya Sagar 2095ec142c44SVidya Sagar ranges = <0x43000000 0x20 0xc0000000 0x20 0xc0000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ 2096ec142c44SVidya Sagar <0x02000000 0x0 0x40000000 0x20 0xe8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2097ec142c44SVidya Sagar <0x01000000 0x0 0x32100000 0x00 0x32100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2098ec142c44SVidya Sagar 2099ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE2AR &emc>, 2100ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE2AW &emc>; 2101ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2102ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE2 0x1000>; 2103ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2104ec142c44SVidya Sagar dma-coherent; 2105ec142c44SVidya Sagar 2106ec142c44SVidya Sagar status = "disabled"; 2107ec142c44SVidya Sagar }; 2108ec142c44SVidya Sagar 2109ec142c44SVidya Sagar pcie@14140000 { 2110ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie"; 2111ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>; 2112ec142c44SVidya Sagar reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */ 2113ec142c44SVidya Sagar <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */ 2114ec142c44SVidya Sagar <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2115ec142c44SVidya Sagar <0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2116ec142c44SVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 2117ec142c44SVidya Sagar 2118ec142c44SVidya Sagar #address-cells = <3>; 2119ec142c44SVidya Sagar #size-cells = <2>; 2120ec142c44SVidya Sagar device_type = "pci"; 2121ec142c44SVidya Sagar num-lanes = <1>; 2122ec142c44SVidya Sagar num-viewport = <8>; 2123ec142c44SVidya Sagar linux,pci-domain = <3>; 2124ec142c44SVidya Sagar 2125ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX0_C3_CORE>; 2126ec142c44SVidya Sagar clock-names = "core"; 2127ec142c44SVidya Sagar 2128ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX0_CORE_3_APB>, 2129ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX0_CORE_3>; 2130ec142c44SVidya Sagar reset-names = "apb", "core"; 2131ec142c44SVidya Sagar 2132ec142c44SVidya Sagar interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2133ec142c44SVidya Sagar <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2134ec142c44SVidya Sagar interrupt-names = "intr", "msi"; 2135ec142c44SVidya Sagar 2136ec142c44SVidya Sagar #interrupt-cells = <1>; 2137ec142c44SVidya Sagar interrupt-map-mask = <0 0 0 0>; 2138ec142c44SVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 2139ec142c44SVidya Sagar 2140ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 3>; 2141ec142c44SVidya Sagar 2142ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2143ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2144ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2145ec142c44SVidya Sagar 2146ec142c44SVidya Sagar bus-range = <0x0 0xff>; 2147ec142c44SVidya Sagar 2148ec142c44SVidya Sagar ranges = <0x43000000 0x21 0x00000000 0x21 0x00000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ 2149ec142c44SVidya Sagar <0x02000000 0x0 0x40000000 0x21 0xe8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2150ec142c44SVidya Sagar <0x01000000 0x0 0x34100000 0x00 0x34100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2151ec142c44SVidya Sagar 2152ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE3R &emc>, 2153ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE3W &emc>; 2154ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2155ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE3 0x1000>; 2156ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2157ec142c44SVidya Sagar dma-coherent; 2158ec142c44SVidya Sagar 2159ec142c44SVidya Sagar status = "disabled"; 2160ec142c44SVidya Sagar }; 2161ec142c44SVidya Sagar 2162ec142c44SVidya Sagar pcie@14160000 { 2163ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie"; 2164ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BB>; 2165ec142c44SVidya Sagar reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2166ec142c44SVidya Sagar <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ 2167ec142c44SVidya Sagar <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2168ec142c44SVidya Sagar <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2169ec142c44SVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 2170ec142c44SVidya Sagar 2171ec142c44SVidya Sagar #address-cells = <3>; 2172ec142c44SVidya Sagar #size-cells = <2>; 2173ec142c44SVidya Sagar device_type = "pci"; 2174ec142c44SVidya Sagar num-lanes = <4>; 2175ec142c44SVidya Sagar num-viewport = <8>; 2176ec142c44SVidya Sagar linux,pci-domain = <4>; 2177ec142c44SVidya Sagar 2178ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX0_C4_CORE>; 2179ec142c44SVidya Sagar clock-names = "core"; 2180ec142c44SVidya Sagar 2181ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX0_CORE_4_APB>, 2182ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX0_CORE_4>; 2183ec142c44SVidya Sagar reset-names = "apb", "core"; 2184ec142c44SVidya Sagar 2185ec142c44SVidya Sagar interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2186ec142c44SVidya Sagar <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2187ec142c44SVidya Sagar interrupt-names = "intr", "msi"; 2188ec142c44SVidya Sagar 2189ec142c44SVidya Sagar #interrupt-cells = <1>; 2190ec142c44SVidya Sagar interrupt-map-mask = <0 0 0 0>; 2191ec142c44SVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 2192ec142c44SVidya Sagar 2193ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 4>; 2194ec142c44SVidya Sagar 2195ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2196ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2197ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2198ec142c44SVidya Sagar 2199ec142c44SVidya Sagar bus-range = <0x0 0xff>; 2200ec142c44SVidya Sagar 2201ec142c44SVidya Sagar ranges = <0x43000000 0x21 0x40000000 0x21 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2202ec142c44SVidya Sagar <0x02000000 0x0 0x40000000 0x24 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2203ec142c44SVidya Sagar <0x01000000 0x0 0x36100000 0x00 0x36100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2204ec142c44SVidya Sagar 2205ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE4R &emc>, 2206ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE4W &emc>; 2207ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2208ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE4 0x1000>; 2209ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2210ec142c44SVidya Sagar dma-coherent; 2211ec142c44SVidya Sagar 2212ec142c44SVidya Sagar status = "disabled"; 2213ec142c44SVidya Sagar }; 2214ec142c44SVidya Sagar 2215ec142c44SVidya Sagar pcie@14180000 { 2216ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie"; 2217ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BA>; 2218ec142c44SVidya Sagar reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2219ec142c44SVidya Sagar <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ 2220ec142c44SVidya Sagar <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2221ec142c44SVidya Sagar <0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2222ec142c44SVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 2223ec142c44SVidya Sagar 2224ec142c44SVidya Sagar #address-cells = <3>; 2225ec142c44SVidya Sagar #size-cells = <2>; 2226ec142c44SVidya Sagar device_type = "pci"; 2227ec142c44SVidya Sagar num-lanes = <4>; 2228ec142c44SVidya Sagar num-viewport = <8>; 2229ec142c44SVidya Sagar linux,pci-domain = <0>; 2230ec142c44SVidya Sagar 2231ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX0_C0_CORE>; 2232ec142c44SVidya Sagar clock-names = "core"; 2233ec142c44SVidya Sagar 2234ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX0_CORE_0_APB>, 2235ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX0_CORE_0>; 2236ec142c44SVidya Sagar reset-names = "apb", "core"; 2237ec142c44SVidya Sagar 2238ec142c44SVidya Sagar interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2239ec142c44SVidya Sagar <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2240ec142c44SVidya Sagar interrupt-names = "intr", "msi"; 2241ec142c44SVidya Sagar 2242ec142c44SVidya Sagar #interrupt-cells = <1>; 2243ec142c44SVidya Sagar interrupt-map-mask = <0 0 0 0>; 2244ec142c44SVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 2245ec142c44SVidya Sagar 2246ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 0>; 2247ec142c44SVidya Sagar 2248ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2249ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2250ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2251ec142c44SVidya Sagar 2252ec142c44SVidya Sagar bus-range = <0x0 0xff>; 2253ec142c44SVidya Sagar 2254ec142c44SVidya Sagar ranges = <0x43000000 0x24 0x40000000 0x24 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2255ec142c44SVidya Sagar <0x02000000 0x0 0x40000000 0x27 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2256ec142c44SVidya Sagar <0x01000000 0x0 0x38100000 0x00 0x38100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2257ec142c44SVidya Sagar 2258ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE0R &emc>, 2259ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE0W &emc>; 2260ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2261ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE0 0x1000>; 2262ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2263ec142c44SVidya Sagar dma-coherent; 2264ec142c44SVidya Sagar 2265ec142c44SVidya Sagar status = "disabled"; 2266ec142c44SVidya Sagar }; 2267ec142c44SVidya Sagar 2268ec142c44SVidya Sagar pcie@141a0000 { 2269ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie"; 2270ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>; 2271ec142c44SVidya Sagar reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2272ec142c44SVidya Sagar <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */ 2273ec142c44SVidya Sagar <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2274ec142c44SVidya Sagar <0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2275ec142c44SVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 2276ec142c44SVidya Sagar 2277ec142c44SVidya Sagar #address-cells = <3>; 2278ec142c44SVidya Sagar #size-cells = <2>; 2279ec142c44SVidya Sagar device_type = "pci"; 2280ec142c44SVidya Sagar num-lanes = <8>; 2281ec142c44SVidya Sagar num-viewport = <8>; 2282ec142c44SVidya Sagar linux,pci-domain = <5>; 2283ec142c44SVidya Sagar 2284ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>; 2285ec142c44SVidya Sagar clock-names = "core"; 2286ec142c44SVidya Sagar 2287ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>, 2288ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX1_CORE_5>; 2289ec142c44SVidya Sagar reset-names = "apb", "core"; 2290ec142c44SVidya Sagar 2291ec142c44SVidya Sagar interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2292ec142c44SVidya Sagar <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2293ec142c44SVidya Sagar interrupt-names = "intr", "msi"; 2294ec142c44SVidya Sagar 2295ec142c44SVidya Sagar #interrupt-cells = <1>; 2296ec142c44SVidya Sagar interrupt-map-mask = <0 0 0 0>; 2297ec142c44SVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 2298ec142c44SVidya Sagar 2299ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 5>; 2300ec142c44SVidya Sagar 2301ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2302ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2303ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2304ec142c44SVidya Sagar 2305ec142c44SVidya Sagar bus-range = <0x0 0xff>; 2306ec142c44SVidya Sagar 2307ec142c44SVidya Sagar ranges = <0x43000000 0x27 0x40000000 0x27 0x40000000 0x3 0xe8000000>, /* prefetchable memory (16000 MB) */ 2308ec142c44SVidya Sagar <0x02000000 0x0 0x40000000 0x2b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2309ec142c44SVidya Sagar <0x01000000 0x0 0x3a100000 0x00 0x3a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2310ec142c44SVidya Sagar 2311ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE5R &emc>, 2312ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE5W &emc>; 2313ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2314ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>; 2315ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2316ec142c44SVidya Sagar dma-coherent; 2317ec142c44SVidya Sagar 2318ec142c44SVidya Sagar status = "disabled"; 2319ec142c44SVidya Sagar }; 2320ec142c44SVidya Sagar 2321ec142c44SVidya Sagar pcie@141c0000 { 2322ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie"; 2323ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4A>; 2324ec142c44SVidya Sagar reg = <0x00 0x141c0000 0x0 0x00020000>, /* appl registers (128K) */ 2325ec142c44SVidya Sagar <0x00 0x3c000000 0x0 0x00040000>, /* configuration space (256K) */ 2326ec142c44SVidya Sagar <0x00 0x3c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2327ec142c44SVidya Sagar <0x00 0x3c080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2328ec142c44SVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 2329ec142c44SVidya Sagar 2330ec142c44SVidya Sagar #address-cells = <3>; 2331ec142c44SVidya Sagar #size-cells = <2>; 2332ec142c44SVidya Sagar device_type = "pci"; 2333ec142c44SVidya Sagar num-lanes = <4>; 2334ec142c44SVidya Sagar num-viewport = <8>; 2335ec142c44SVidya Sagar linux,pci-domain = <6>; 2336ec142c44SVidya Sagar 2337ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX1_C6_CORE>; 2338ec142c44SVidya Sagar clock-names = "core"; 2339ec142c44SVidya Sagar 2340ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX1_CORE_6_APB>, 2341ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX1_CORE_6>; 2342ec142c44SVidya Sagar reset-names = "apb", "core"; 2343ec142c44SVidya Sagar 2344ec142c44SVidya Sagar interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2345ec142c44SVidya Sagar <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2346ec142c44SVidya Sagar interrupt-names = "intr", "msi"; 2347ec142c44SVidya Sagar 2348ec142c44SVidya Sagar #interrupt-cells = <1>; 2349ec142c44SVidya Sagar interrupt-map-mask = <0 0 0 0>; 2350ec142c44SVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 2351ec142c44SVidya Sagar 2352ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 6>; 2353ec142c44SVidya Sagar 2354ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2355ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2356ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2357ec142c44SVidya Sagar 2358ec142c44SVidya Sagar bus-range = <0x0 0xff>; 2359ec142c44SVidya Sagar 2360ec142c44SVidya Sagar ranges = <0x43000000 0x2b 0x40000000 0x2b 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2361ec142c44SVidya Sagar <0x02000000 0x0 0x40000000 0x2e 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2362ec142c44SVidya Sagar <0x01000000 0x0 0x3c100000 0x00 0x3c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2363ec142c44SVidya Sagar 2364ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE6AR &emc>, 2365ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE6AW &emc>; 2366ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2367ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>; 2368ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2369ec142c44SVidya Sagar dma-coherent; 2370ec142c44SVidya Sagar 2371ec142c44SVidya Sagar status = "disabled"; 2372ec142c44SVidya Sagar }; 2373ec142c44SVidya Sagar 2374ec142c44SVidya Sagar pcie@141e0000 { 2375ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie"; 2376ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8B>; 2377ec142c44SVidya Sagar reg = <0x00 0x141e0000 0x0 0x00020000>, /* appl registers (128K) */ 2378ec142c44SVidya Sagar <0x00 0x3e000000 0x0 0x00040000>, /* configuration space (256K) */ 2379ec142c44SVidya Sagar <0x00 0x3e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2380ec142c44SVidya Sagar <0x00 0x3e080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2381ec142c44SVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 2382ec142c44SVidya Sagar 2383ec142c44SVidya Sagar #address-cells = <3>; 2384ec142c44SVidya Sagar #size-cells = <2>; 2385ec142c44SVidya Sagar device_type = "pci"; 2386ec142c44SVidya Sagar num-lanes = <8>; 2387ec142c44SVidya Sagar num-viewport = <8>; 2388ec142c44SVidya Sagar linux,pci-domain = <7>; 2389ec142c44SVidya Sagar 2390ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX2_C7_CORE>; 2391ec142c44SVidya Sagar clock-names = "core"; 2392ec142c44SVidya Sagar 2393ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX2_CORE_7_APB>, 2394ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX2_CORE_7>; 2395ec142c44SVidya Sagar reset-names = "apb", "core"; 2396ec142c44SVidya Sagar 2397ec142c44SVidya Sagar interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2398ec142c44SVidya Sagar <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2399ec142c44SVidya Sagar interrupt-names = "intr", "msi"; 2400ec142c44SVidya Sagar 2401ec142c44SVidya Sagar #interrupt-cells = <1>; 2402ec142c44SVidya Sagar interrupt-map-mask = <0 0 0 0>; 2403ec142c44SVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 2404ec142c44SVidya Sagar 2405ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 7>; 2406ec142c44SVidya Sagar 2407ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2408ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2409ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2410ec142c44SVidya Sagar 2411ec142c44SVidya Sagar bus-range = <0x0 0xff>; 2412ec142c44SVidya Sagar 2413ec142c44SVidya Sagar ranges = <0x43000000 0x2e 0x40000000 0x2e 0x40000000 0x3 0xe8000000>, /* prefetchable memory (16000 MB) */ 2414ec142c44SVidya Sagar <0x02000000 0x0 0x40000000 0x32 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2415ec142c44SVidya Sagar <0x01000000 0x0 0x3e100000 0x00 0x3e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2416ec142c44SVidya Sagar 2417ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE7AR &emc>, 2418ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE7AW &emc>; 2419ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2420ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>; 2421ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2422ec142c44SVidya Sagar dma-coherent; 2423ec142c44SVidya Sagar 2424ec142c44SVidya Sagar status = "disabled"; 2425ec142c44SVidya Sagar }; 2426ec142c44SVidya Sagar 2427ec142c44SVidya Sagar pcie-ep@141a0000 { 2428ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie-ep"; 2429ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>; 2430ec142c44SVidya Sagar reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2431ec142c44SVidya Sagar <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2432ec142c44SVidya Sagar <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2433ec142c44SVidya Sagar <0x27 0x40000000 0x4 0x00000000>; /* Address Space (16G) */ 2434ec142c44SVidya Sagar reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2435ec142c44SVidya Sagar 2436ec142c44SVidya Sagar num-lanes = <8>; 2437ec142c44SVidya Sagar 2438ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>; 2439ec142c44SVidya Sagar clock-names = "core"; 2440ec142c44SVidya Sagar 2441ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>, 2442ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX1_CORE_5>; 2443ec142c44SVidya Sagar reset-names = "apb", "core"; 2444ec142c44SVidya Sagar 2445ec142c44SVidya Sagar interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2446ec142c44SVidya Sagar interrupt-names = "intr"; 2447ec142c44SVidya Sagar 2448ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 5>; 2449ec142c44SVidya Sagar 2450ec142c44SVidya Sagar nvidia,enable-ext-refclk; 2451ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2452ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2453ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2454ec142c44SVidya Sagar 2455ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE5R &emc>, 2456ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE5W &emc>; 2457ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2458ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>; 2459ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2460ec142c44SVidya Sagar dma-coherent; 2461ec142c44SVidya Sagar 2462ec142c44SVidya Sagar status = "disabled"; 2463ec142c44SVidya Sagar }; 2464ec142c44SVidya Sagar 2465ec142c44SVidya Sagar pcie-ep@141c0000{ 2466ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie-ep"; 2467ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4A>; 2468ec142c44SVidya Sagar reg = <0x00 0x141c0000 0x0 0x00020000>, /* appl registers (128K) */ 2469ec142c44SVidya Sagar <0x00 0x3c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2470ec142c44SVidya Sagar <0x00 0x3c080000 0x0 0x00040000>, /* DBI space (256K) */ 2471ec142c44SVidya Sagar <0x2b 0x40000000 0x3 0x00000000>; /* Address Space (12G) */ 2472ec142c44SVidya Sagar reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2473ec142c44SVidya Sagar 2474ec142c44SVidya Sagar num-lanes = <4>; 2475ec142c44SVidya Sagar 2476ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX1_C6_CORE>; 2477ec142c44SVidya Sagar clock-names = "core"; 2478ec142c44SVidya Sagar 2479ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX1_CORE_6_APB>, 2480ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX1_CORE_6>; 2481ec142c44SVidya Sagar reset-names = "apb", "core"; 2482ec142c44SVidya Sagar 2483ec142c44SVidya Sagar interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2484ec142c44SVidya Sagar interrupt-names = "intr"; 2485ec142c44SVidya Sagar 2486ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 6>; 2487ec142c44SVidya Sagar 2488ec142c44SVidya Sagar nvidia,enable-ext-refclk; 2489ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2490ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2491ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2492ec142c44SVidya Sagar 2493ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE6AR &emc>, 2494ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE6AW &emc>; 2495ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2496ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>; 2497ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2498ec142c44SVidya Sagar dma-coherent; 2499ec142c44SVidya Sagar 2500ec142c44SVidya Sagar status = "disabled"; 2501ec142c44SVidya Sagar }; 2502ec142c44SVidya Sagar 2503ec142c44SVidya Sagar pcie-ep@141e0000{ 2504ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie-ep"; 2505ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8B>; 2506ec142c44SVidya Sagar reg = <0x00 0x141e0000 0x0 0x00020000>, /* appl registers (128K) */ 2507ec142c44SVidya Sagar <0x00 0x3e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2508ec142c44SVidya Sagar <0x00 0x3e080000 0x0 0x00040000>, /* DBI space (256K) */ 2509ec142c44SVidya Sagar <0x2e 0x40000000 0x4 0x00000000>; /* Address Space (16G) */ 2510ec142c44SVidya Sagar reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2511ec142c44SVidya Sagar 2512ec142c44SVidya Sagar num-lanes = <8>; 2513ec142c44SVidya Sagar 2514ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX2_C7_CORE>; 2515ec142c44SVidya Sagar clock-names = "core"; 2516ec142c44SVidya Sagar 2517ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX2_CORE_7_APB>, 2518ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX2_CORE_7>; 2519ec142c44SVidya Sagar reset-names = "apb", "core"; 2520ec142c44SVidya Sagar 2521ec142c44SVidya Sagar interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2522ec142c44SVidya Sagar interrupt-names = "intr"; 2523ec142c44SVidya Sagar 2524ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 7>; 2525ec142c44SVidya Sagar 2526ec142c44SVidya Sagar nvidia,enable-ext-refclk; 2527ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2528ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2529ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2530ec142c44SVidya Sagar 2531ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE7AR &emc>, 2532ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE7AW &emc>; 2533ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2534ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>; 2535ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2536ec142c44SVidya Sagar dma-coherent; 2537ec142c44SVidya Sagar 2538ec142c44SVidya Sagar status = "disabled"; 2539ec142c44SVidya Sagar }; 2540ec142c44SVidya Sagar 2541ec142c44SVidya Sagar pcie-ep@140e0000{ 2542ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie-ep"; 2543ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CC>; 2544ec142c44SVidya Sagar reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K) */ 2545ec142c44SVidya Sagar <0x00 0x2e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2546ec142c44SVidya Sagar <0x00 0x2e080000 0x0 0x00040000>, /* DBI space (256K) */ 2547ec142c44SVidya Sagar <0x38 0x40000000 0x3 0x00000000>; /* Address Space (12G) */ 2548ec142c44SVidya Sagar reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2549ec142c44SVidya Sagar 2550ec142c44SVidya Sagar num-lanes = <4>; 2551ec142c44SVidya Sagar 2552ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX2_C10_CORE>; 2553ec142c44SVidya Sagar clock-names = "core"; 2554ec142c44SVidya Sagar 2555ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX2_CORE_10_APB>, 2556ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX2_CORE_10>; 2557ec142c44SVidya Sagar reset-names = "apb", "core"; 2558ec142c44SVidya Sagar 2559ec142c44SVidya Sagar interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2560ec142c44SVidya Sagar interrupt-names = "intr"; 2561ec142c44SVidya Sagar 2562ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 10>; 2563ec142c44SVidya Sagar 2564ec142c44SVidya Sagar nvidia,enable-ext-refclk; 2565ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2566ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2567ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2568ec142c44SVidya Sagar 2569ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE10AR &emc>, 2570ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE10AW &emc>; 2571ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2572ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>; 2573ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2574ec142c44SVidya Sagar dma-coherent; 2575ec142c44SVidya Sagar 2576ec142c44SVidya Sagar status = "disabled"; 2577ec142c44SVidya Sagar }; 2578ec142c44SVidya Sagar 25797fa30752SThierry Reding sram@40000000 { 258063944891SThierry Reding compatible = "nvidia,tegra234-sysram", "mmio-sram"; 258198094be1SMikko Perttunen reg = <0x0 0x40000000 0x0 0x80000>; 258263944891SThierry Reding #address-cells = <1>; 258363944891SThierry Reding #size-cells = <1>; 258498094be1SMikko Perttunen ranges = <0x0 0x0 0x40000000 0x80000>; 258561192a9dSMikko Perttunen no-memory-wc; 258663944891SThierry Reding 258798094be1SMikko Perttunen cpu_bpmp_tx: sram@70000 { 258898094be1SMikko Perttunen reg = <0x70000 0x1000>; 258963944891SThierry Reding label = "cpu-bpmp-tx"; 259063944891SThierry Reding pool; 259163944891SThierry Reding }; 259263944891SThierry Reding 259398094be1SMikko Perttunen cpu_bpmp_rx: sram@71000 { 259498094be1SMikko Perttunen reg = <0x71000 0x1000>; 259563944891SThierry Reding label = "cpu-bpmp-rx"; 259663944891SThierry Reding pool; 259763944891SThierry Reding }; 259863944891SThierry Reding }; 259963944891SThierry Reding 260063944891SThierry Reding bpmp: bpmp { 260163944891SThierry Reding compatible = "nvidia,tegra234-bpmp", "nvidia,tegra186-bpmp"; 260263944891SThierry Reding mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 260363944891SThierry Reding TEGRA_HSP_DB_MASTER_BPMP>; 26047fa30752SThierry Reding shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; 260563944891SThierry Reding #clock-cells = <1>; 260663944891SThierry Reding #reset-cells = <1>; 260763944891SThierry Reding #power-domain-cells = <1>; 26086de481e5SThierry Reding interconnects = <&mc TEGRA234_MEMORY_CLIENT_BPMPR &emc>, 26096de481e5SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_BPMPW &emc>, 26106de481e5SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAR &emc>, 26116de481e5SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAW &emc>; 26126de481e5SThierry Reding interconnect-names = "read", "write", "dma-mem", "dma-write"; 26135710e16aSThierry Reding iommus = <&smmu_niso1 TEGRA234_SID_BPMP>; 261463944891SThierry Reding 261563944891SThierry Reding bpmp_i2c: i2c { 261663944891SThierry Reding compatible = "nvidia,tegra186-bpmp-i2c"; 261763944891SThierry Reding nvidia,bpmp-bus-id = <5>; 261863944891SThierry Reding #address-cells = <1>; 261963944891SThierry Reding #size-cells = <0>; 262063944891SThierry Reding }; 262163944891SThierry Reding }; 262263944891SThierry Reding 262363944891SThierry Reding cpus { 262463944891SThierry Reding #address-cells = <1>; 262563944891SThierry Reding #size-cells = <0>; 262663944891SThierry Reding 2627a12cf5c3SThierry Reding cpu0_0: cpu@0 { 2628a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 262963944891SThierry Reding device_type = "cpu"; 2630a12cf5c3SThierry Reding reg = <0x00000>; 263163944891SThierry Reding 263263944891SThierry Reding enable-method = "psci"; 2633a12cf5c3SThierry Reding 2634a12cf5c3SThierry Reding i-cache-size = <65536>; 2635a12cf5c3SThierry Reding i-cache-line-size = <64>; 2636a12cf5c3SThierry Reding i-cache-sets = <256>; 2637a12cf5c3SThierry Reding d-cache-size = <65536>; 2638a12cf5c3SThierry Reding d-cache-line-size = <64>; 2639a12cf5c3SThierry Reding d-cache-sets = <256>; 2640a12cf5c3SThierry Reding next-level-cache = <&l2c0_0>; 264163944891SThierry Reding }; 2642a12cf5c3SThierry Reding 2643a12cf5c3SThierry Reding cpu0_1: cpu@100 { 2644a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 2645a12cf5c3SThierry Reding device_type = "cpu"; 2646a12cf5c3SThierry Reding reg = <0x00100>; 2647a12cf5c3SThierry Reding 2648a12cf5c3SThierry Reding enable-method = "psci"; 2649a12cf5c3SThierry Reding 2650a12cf5c3SThierry Reding i-cache-size = <65536>; 2651a12cf5c3SThierry Reding i-cache-line-size = <64>; 2652a12cf5c3SThierry Reding i-cache-sets = <256>; 2653a12cf5c3SThierry Reding d-cache-size = <65536>; 2654a12cf5c3SThierry Reding d-cache-line-size = <64>; 2655a12cf5c3SThierry Reding d-cache-sets = <256>; 2656a12cf5c3SThierry Reding next-level-cache = <&l2c0_1>; 2657a12cf5c3SThierry Reding }; 2658a12cf5c3SThierry Reding 2659a12cf5c3SThierry Reding cpu0_2: cpu@200 { 2660a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 2661a12cf5c3SThierry Reding device_type = "cpu"; 2662a12cf5c3SThierry Reding reg = <0x00200>; 2663a12cf5c3SThierry Reding 2664a12cf5c3SThierry Reding enable-method = "psci"; 2665a12cf5c3SThierry Reding 2666a12cf5c3SThierry Reding i-cache-size = <65536>; 2667a12cf5c3SThierry Reding i-cache-line-size = <64>; 2668a12cf5c3SThierry Reding i-cache-sets = <256>; 2669a12cf5c3SThierry Reding d-cache-size = <65536>; 2670a12cf5c3SThierry Reding d-cache-line-size = <64>; 2671a12cf5c3SThierry Reding d-cache-sets = <256>; 2672a12cf5c3SThierry Reding next-level-cache = <&l2c0_2>; 2673a12cf5c3SThierry Reding }; 2674a12cf5c3SThierry Reding 2675a12cf5c3SThierry Reding cpu0_3: cpu@300 { 2676a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 2677a12cf5c3SThierry Reding device_type = "cpu"; 2678a12cf5c3SThierry Reding reg = <0x00300>; 2679a12cf5c3SThierry Reding 2680a12cf5c3SThierry Reding enable-method = "psci"; 2681a12cf5c3SThierry Reding 2682a12cf5c3SThierry Reding i-cache-size = <65536>; 2683a12cf5c3SThierry Reding i-cache-line-size = <64>; 2684a12cf5c3SThierry Reding i-cache-sets = <256>; 2685a12cf5c3SThierry Reding d-cache-size = <65536>; 2686a12cf5c3SThierry Reding d-cache-line-size = <64>; 2687a12cf5c3SThierry Reding d-cache-sets = <256>; 2688a12cf5c3SThierry Reding next-level-cache = <&l2c0_3>; 2689a12cf5c3SThierry Reding }; 2690a12cf5c3SThierry Reding 2691a12cf5c3SThierry Reding cpu1_0: cpu@10000 { 2692a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 2693a12cf5c3SThierry Reding device_type = "cpu"; 2694a12cf5c3SThierry Reding reg = <0x10000>; 2695a12cf5c3SThierry Reding 2696a12cf5c3SThierry Reding enable-method = "psci"; 2697a12cf5c3SThierry Reding 2698a12cf5c3SThierry Reding i-cache-size = <65536>; 2699a12cf5c3SThierry Reding i-cache-line-size = <64>; 2700a12cf5c3SThierry Reding i-cache-sets = <256>; 2701a12cf5c3SThierry Reding d-cache-size = <65536>; 2702a12cf5c3SThierry Reding d-cache-line-size = <64>; 2703a12cf5c3SThierry Reding d-cache-sets = <256>; 2704a12cf5c3SThierry Reding next-level-cache = <&l2c1_0>; 2705a12cf5c3SThierry Reding }; 2706a12cf5c3SThierry Reding 2707a12cf5c3SThierry Reding cpu1_1: cpu@10100 { 2708a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 2709a12cf5c3SThierry Reding device_type = "cpu"; 2710a12cf5c3SThierry Reding reg = <0x10100>; 2711a12cf5c3SThierry Reding 2712a12cf5c3SThierry Reding enable-method = "psci"; 2713a12cf5c3SThierry Reding 2714a12cf5c3SThierry Reding i-cache-size = <65536>; 2715a12cf5c3SThierry Reding i-cache-line-size = <64>; 2716a12cf5c3SThierry Reding i-cache-sets = <256>; 2717a12cf5c3SThierry Reding d-cache-size = <65536>; 2718a12cf5c3SThierry Reding d-cache-line-size = <64>; 2719a12cf5c3SThierry Reding d-cache-sets = <256>; 2720a12cf5c3SThierry Reding next-level-cache = <&l2c1_1>; 2721a12cf5c3SThierry Reding }; 2722a12cf5c3SThierry Reding 2723a12cf5c3SThierry Reding cpu1_2: cpu@10200 { 2724a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 2725a12cf5c3SThierry Reding device_type = "cpu"; 2726a12cf5c3SThierry Reding reg = <0x10200>; 2727a12cf5c3SThierry Reding 2728a12cf5c3SThierry Reding enable-method = "psci"; 2729a12cf5c3SThierry Reding 2730a12cf5c3SThierry Reding i-cache-size = <65536>; 2731a12cf5c3SThierry Reding i-cache-line-size = <64>; 2732a12cf5c3SThierry Reding i-cache-sets = <256>; 2733a12cf5c3SThierry Reding d-cache-size = <65536>; 2734a12cf5c3SThierry Reding d-cache-line-size = <64>; 2735a12cf5c3SThierry Reding d-cache-sets = <256>; 2736a12cf5c3SThierry Reding next-level-cache = <&l2c1_2>; 2737a12cf5c3SThierry Reding }; 2738a12cf5c3SThierry Reding 2739a12cf5c3SThierry Reding cpu1_3: cpu@10300 { 2740a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 2741a12cf5c3SThierry Reding device_type = "cpu"; 2742a12cf5c3SThierry Reding reg = <0x10300>; 2743a12cf5c3SThierry Reding 2744a12cf5c3SThierry Reding enable-method = "psci"; 2745a12cf5c3SThierry Reding 2746a12cf5c3SThierry Reding i-cache-size = <65536>; 2747a12cf5c3SThierry Reding i-cache-line-size = <64>; 2748a12cf5c3SThierry Reding i-cache-sets = <256>; 2749a12cf5c3SThierry Reding d-cache-size = <65536>; 2750a12cf5c3SThierry Reding d-cache-line-size = <64>; 2751a12cf5c3SThierry Reding d-cache-sets = <256>; 2752a12cf5c3SThierry Reding next-level-cache = <&l2c1_3>; 2753a12cf5c3SThierry Reding }; 2754a12cf5c3SThierry Reding 2755a12cf5c3SThierry Reding cpu2_0: cpu@20000 { 2756a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 2757a12cf5c3SThierry Reding device_type = "cpu"; 2758a12cf5c3SThierry Reding reg = <0x20000>; 2759a12cf5c3SThierry Reding 2760a12cf5c3SThierry Reding enable-method = "psci"; 2761a12cf5c3SThierry Reding 2762a12cf5c3SThierry Reding i-cache-size = <65536>; 2763a12cf5c3SThierry Reding i-cache-line-size = <64>; 2764a12cf5c3SThierry Reding i-cache-sets = <256>; 2765a12cf5c3SThierry Reding d-cache-size = <65536>; 2766a12cf5c3SThierry Reding d-cache-line-size = <64>; 2767a12cf5c3SThierry Reding d-cache-sets = <256>; 2768a12cf5c3SThierry Reding next-level-cache = <&l2c2_0>; 2769a12cf5c3SThierry Reding }; 2770a12cf5c3SThierry Reding 2771a12cf5c3SThierry Reding cpu2_1: cpu@20100 { 2772a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 2773a12cf5c3SThierry Reding device_type = "cpu"; 2774a12cf5c3SThierry Reding reg = <0x20100>; 2775a12cf5c3SThierry Reding 2776a12cf5c3SThierry Reding enable-method = "psci"; 2777a12cf5c3SThierry Reding 2778a12cf5c3SThierry Reding i-cache-size = <65536>; 2779a12cf5c3SThierry Reding i-cache-line-size = <64>; 2780a12cf5c3SThierry Reding i-cache-sets = <256>; 2781a12cf5c3SThierry Reding d-cache-size = <65536>; 2782a12cf5c3SThierry Reding d-cache-line-size = <64>; 2783a12cf5c3SThierry Reding d-cache-sets = <256>; 2784a12cf5c3SThierry Reding next-level-cache = <&l2c2_1>; 2785a12cf5c3SThierry Reding }; 2786a12cf5c3SThierry Reding 2787a12cf5c3SThierry Reding cpu2_2: cpu@20200 { 2788a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 2789a12cf5c3SThierry Reding device_type = "cpu"; 2790a12cf5c3SThierry Reding reg = <0x20200>; 2791a12cf5c3SThierry Reding 2792a12cf5c3SThierry Reding enable-method = "psci"; 2793a12cf5c3SThierry Reding 2794a12cf5c3SThierry Reding i-cache-size = <65536>; 2795a12cf5c3SThierry Reding i-cache-line-size = <64>; 2796a12cf5c3SThierry Reding i-cache-sets = <256>; 2797a12cf5c3SThierry Reding d-cache-size = <65536>; 2798a12cf5c3SThierry Reding d-cache-line-size = <64>; 2799a12cf5c3SThierry Reding d-cache-sets = <256>; 2800a12cf5c3SThierry Reding next-level-cache = <&l2c2_2>; 2801a12cf5c3SThierry Reding }; 2802a12cf5c3SThierry Reding 2803a12cf5c3SThierry Reding cpu2_3: cpu@20300 { 2804a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 2805a12cf5c3SThierry Reding device_type = "cpu"; 2806a12cf5c3SThierry Reding reg = <0x20300>; 2807a12cf5c3SThierry Reding 2808a12cf5c3SThierry Reding enable-method = "psci"; 2809a12cf5c3SThierry Reding 2810a12cf5c3SThierry Reding i-cache-size = <65536>; 2811a12cf5c3SThierry Reding i-cache-line-size = <64>; 2812a12cf5c3SThierry Reding i-cache-sets = <256>; 2813a12cf5c3SThierry Reding d-cache-size = <65536>; 2814a12cf5c3SThierry Reding d-cache-line-size = <64>; 2815a12cf5c3SThierry Reding d-cache-sets = <256>; 2816a12cf5c3SThierry Reding next-level-cache = <&l2c2_3>; 2817a12cf5c3SThierry Reding }; 2818a12cf5c3SThierry Reding 2819a12cf5c3SThierry Reding cpu-map { 2820a12cf5c3SThierry Reding cluster0 { 2821a12cf5c3SThierry Reding core0 { 2822a12cf5c3SThierry Reding cpu = <&cpu0_0>; 2823a12cf5c3SThierry Reding }; 2824a12cf5c3SThierry Reding 2825a12cf5c3SThierry Reding core1 { 2826a12cf5c3SThierry Reding cpu = <&cpu0_1>; 2827a12cf5c3SThierry Reding }; 2828a12cf5c3SThierry Reding 2829a12cf5c3SThierry Reding core2 { 2830a12cf5c3SThierry Reding cpu = <&cpu0_2>; 2831a12cf5c3SThierry Reding }; 2832a12cf5c3SThierry Reding 2833a12cf5c3SThierry Reding core3 { 2834a12cf5c3SThierry Reding cpu = <&cpu0_3>; 2835a12cf5c3SThierry Reding }; 2836a12cf5c3SThierry Reding }; 2837a12cf5c3SThierry Reding 2838a12cf5c3SThierry Reding cluster1 { 2839a12cf5c3SThierry Reding core0 { 2840a12cf5c3SThierry Reding cpu = <&cpu1_0>; 2841a12cf5c3SThierry Reding }; 2842a12cf5c3SThierry Reding 2843a12cf5c3SThierry Reding core1 { 2844a12cf5c3SThierry Reding cpu = <&cpu1_1>; 2845a12cf5c3SThierry Reding }; 2846a12cf5c3SThierry Reding 2847a12cf5c3SThierry Reding core2 { 2848a12cf5c3SThierry Reding cpu = <&cpu1_2>; 2849a12cf5c3SThierry Reding }; 2850a12cf5c3SThierry Reding 2851a12cf5c3SThierry Reding core3 { 2852a12cf5c3SThierry Reding cpu = <&cpu1_3>; 2853a12cf5c3SThierry Reding }; 2854a12cf5c3SThierry Reding }; 2855a12cf5c3SThierry Reding 2856a12cf5c3SThierry Reding cluster2 { 2857a12cf5c3SThierry Reding core0 { 2858a12cf5c3SThierry Reding cpu = <&cpu2_0>; 2859a12cf5c3SThierry Reding }; 2860a12cf5c3SThierry Reding 2861a12cf5c3SThierry Reding core1 { 2862a12cf5c3SThierry Reding cpu = <&cpu2_1>; 2863a12cf5c3SThierry Reding }; 2864a12cf5c3SThierry Reding 2865a12cf5c3SThierry Reding core2 { 2866a12cf5c3SThierry Reding cpu = <&cpu2_2>; 2867a12cf5c3SThierry Reding }; 2868a12cf5c3SThierry Reding 2869a12cf5c3SThierry Reding core3 { 2870a12cf5c3SThierry Reding cpu = <&cpu2_3>; 2871a12cf5c3SThierry Reding }; 2872a12cf5c3SThierry Reding }; 2873a12cf5c3SThierry Reding }; 2874a12cf5c3SThierry Reding 2875a12cf5c3SThierry Reding l2c0_0: l2-cache00 { 2876a12cf5c3SThierry Reding cache-size = <262144>; 2877a12cf5c3SThierry Reding cache-line-size = <64>; 2878a12cf5c3SThierry Reding cache-sets = <512>; 2879a12cf5c3SThierry Reding cache-unified; 2880a12cf5c3SThierry Reding next-level-cache = <&l3c0>; 2881a12cf5c3SThierry Reding }; 2882a12cf5c3SThierry Reding 2883a12cf5c3SThierry Reding l2c0_1: l2-cache01 { 2884a12cf5c3SThierry Reding cache-size = <262144>; 2885a12cf5c3SThierry Reding cache-line-size = <64>; 2886a12cf5c3SThierry Reding cache-sets = <512>; 2887a12cf5c3SThierry Reding cache-unified; 2888a12cf5c3SThierry Reding next-level-cache = <&l3c0>; 2889a12cf5c3SThierry Reding }; 2890a12cf5c3SThierry Reding 2891a12cf5c3SThierry Reding l2c0_2: l2-cache02 { 2892a12cf5c3SThierry Reding cache-size = <262144>; 2893a12cf5c3SThierry Reding cache-line-size = <64>; 2894a12cf5c3SThierry Reding cache-sets = <512>; 2895a12cf5c3SThierry Reding cache-unified; 2896a12cf5c3SThierry Reding next-level-cache = <&l3c0>; 2897a12cf5c3SThierry Reding }; 2898a12cf5c3SThierry Reding 2899a12cf5c3SThierry Reding l2c0_3: l2-cache03 { 2900a12cf5c3SThierry Reding cache-size = <262144>; 2901a12cf5c3SThierry Reding cache-line-size = <64>; 2902a12cf5c3SThierry Reding cache-sets = <512>; 2903a12cf5c3SThierry Reding cache-unified; 2904a12cf5c3SThierry Reding next-level-cache = <&l3c0>; 2905a12cf5c3SThierry Reding }; 2906a12cf5c3SThierry Reding 2907a12cf5c3SThierry Reding l2c1_0: l2-cache10 { 2908a12cf5c3SThierry Reding cache-size = <262144>; 2909a12cf5c3SThierry Reding cache-line-size = <64>; 2910a12cf5c3SThierry Reding cache-sets = <512>; 2911a12cf5c3SThierry Reding cache-unified; 2912a12cf5c3SThierry Reding next-level-cache = <&l3c1>; 2913a12cf5c3SThierry Reding }; 2914a12cf5c3SThierry Reding 2915a12cf5c3SThierry Reding l2c1_1: l2-cache11 { 2916a12cf5c3SThierry Reding cache-size = <262144>; 2917a12cf5c3SThierry Reding cache-line-size = <64>; 2918a12cf5c3SThierry Reding cache-sets = <512>; 2919a12cf5c3SThierry Reding cache-unified; 2920a12cf5c3SThierry Reding next-level-cache = <&l3c1>; 2921a12cf5c3SThierry Reding }; 2922a12cf5c3SThierry Reding 2923a12cf5c3SThierry Reding l2c1_2: l2-cache12 { 2924a12cf5c3SThierry Reding cache-size = <262144>; 2925a12cf5c3SThierry Reding cache-line-size = <64>; 2926a12cf5c3SThierry Reding cache-sets = <512>; 2927a12cf5c3SThierry Reding cache-unified; 2928a12cf5c3SThierry Reding next-level-cache = <&l3c1>; 2929a12cf5c3SThierry Reding }; 2930a12cf5c3SThierry Reding 2931a12cf5c3SThierry Reding l2c1_3: l2-cache13 { 2932a12cf5c3SThierry Reding cache-size = <262144>; 2933a12cf5c3SThierry Reding cache-line-size = <64>; 2934a12cf5c3SThierry Reding cache-sets = <512>; 2935a12cf5c3SThierry Reding cache-unified; 2936a12cf5c3SThierry Reding next-level-cache = <&l3c1>; 2937a12cf5c3SThierry Reding }; 2938a12cf5c3SThierry Reding 2939a12cf5c3SThierry Reding l2c2_0: l2-cache20 { 2940a12cf5c3SThierry Reding cache-size = <262144>; 2941a12cf5c3SThierry Reding cache-line-size = <64>; 2942a12cf5c3SThierry Reding cache-sets = <512>; 2943a12cf5c3SThierry Reding cache-unified; 2944a12cf5c3SThierry Reding next-level-cache = <&l3c2>; 2945a12cf5c3SThierry Reding }; 2946a12cf5c3SThierry Reding 2947a12cf5c3SThierry Reding l2c2_1: l2-cache21 { 2948a12cf5c3SThierry Reding cache-size = <262144>; 2949a12cf5c3SThierry Reding cache-line-size = <64>; 2950a12cf5c3SThierry Reding cache-sets = <512>; 2951a12cf5c3SThierry Reding cache-unified; 2952a12cf5c3SThierry Reding next-level-cache = <&l3c2>; 2953a12cf5c3SThierry Reding }; 2954a12cf5c3SThierry Reding 2955a12cf5c3SThierry Reding l2c2_2: l2-cache22 { 2956a12cf5c3SThierry Reding cache-size = <262144>; 2957a12cf5c3SThierry Reding cache-line-size = <64>; 2958a12cf5c3SThierry Reding cache-sets = <512>; 2959a12cf5c3SThierry Reding cache-unified; 2960a12cf5c3SThierry Reding next-level-cache = <&l3c2>; 2961a12cf5c3SThierry Reding }; 2962a12cf5c3SThierry Reding 2963a12cf5c3SThierry Reding l2c2_3: l2-cache23 { 2964a12cf5c3SThierry Reding cache-size = <262144>; 2965a12cf5c3SThierry Reding cache-line-size = <64>; 2966a12cf5c3SThierry Reding cache-sets = <512>; 2967a12cf5c3SThierry Reding cache-unified; 2968a12cf5c3SThierry Reding next-level-cache = <&l3c2>; 2969a12cf5c3SThierry Reding }; 2970a12cf5c3SThierry Reding 2971a12cf5c3SThierry Reding l3c0: l3-cache0 { 2972a12cf5c3SThierry Reding cache-size = <2097152>; 2973a12cf5c3SThierry Reding cache-line-size = <64>; 2974a12cf5c3SThierry Reding cache-sets = <2048>; 2975a12cf5c3SThierry Reding }; 2976a12cf5c3SThierry Reding 2977a12cf5c3SThierry Reding l3c1: l3-cache1 { 2978a12cf5c3SThierry Reding cache-size = <2097152>; 2979a12cf5c3SThierry Reding cache-line-size = <64>; 2980a12cf5c3SThierry Reding cache-sets = <2048>; 2981a12cf5c3SThierry Reding }; 2982a12cf5c3SThierry Reding 2983a12cf5c3SThierry Reding l3c2: l3-cache2 { 2984a12cf5c3SThierry Reding cache-size = <2097152>; 2985a12cf5c3SThierry Reding cache-line-size = <64>; 2986a12cf5c3SThierry Reding cache-sets = <2048>; 2987a12cf5c3SThierry Reding }; 2988a12cf5c3SThierry Reding }; 2989a12cf5c3SThierry Reding 2990a12cf5c3SThierry Reding pmu { 2991a12cf5c3SThierry Reding compatible = "arm,cortex-a78-pmu"; 2992a12cf5c3SThierry Reding interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 2993a12cf5c3SThierry Reding status = "okay"; 299463944891SThierry Reding }; 299563944891SThierry Reding 299663944891SThierry Reding psci { 299763944891SThierry Reding compatible = "arm,psci-1.0"; 299863944891SThierry Reding status = "okay"; 299963944891SThierry Reding method = "smc"; 300063944891SThierry Reding }; 300163944891SThierry Reding 300206ad2ec4SMikko Perttunen tcu: serial { 300306ad2ec4SMikko Perttunen compatible = "nvidia,tegra234-tcu", "nvidia,tegra194-tcu"; 300406ad2ec4SMikko Perttunen mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 300506ad2ec4SMikko Perttunen <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 300606ad2ec4SMikko Perttunen mbox-names = "rx", "tx"; 300706ad2ec4SMikko Perttunen status = "disabled"; 300806ad2ec4SMikko Perttunen }; 300906ad2ec4SMikko Perttunen 301009614acdSSameer Pujar sound { 301109614acdSSameer Pujar status = "disabled"; 301209614acdSSameer Pujar 301309614acdSSameer Pujar clocks = <&bpmp TEGRA234_CLK_PLLA>, 301409614acdSSameer Pujar <&bpmp TEGRA234_CLK_PLLA_OUT0>; 301509614acdSSameer Pujar clock-names = "pll_a", "plla_out0"; 301609614acdSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_PLLA>, 301709614acdSSameer Pujar <&bpmp TEGRA234_CLK_PLLA_OUT0>, 301809614acdSSameer Pujar <&bpmp TEGRA234_CLK_AUD_MCLK>; 301909614acdSSameer Pujar assigned-clock-parents = <0>, 302009614acdSSameer Pujar <&bpmp TEGRA234_CLK_PLLA>, 302109614acdSSameer Pujar <&bpmp TEGRA234_CLK_PLLA_OUT0>; 302209614acdSSameer Pujar }; 302309614acdSSameer Pujar 302463944891SThierry Reding timer { 302563944891SThierry Reding compatible = "arm,armv8-timer"; 302663944891SThierry Reding interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 302763944891SThierry Reding <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 302863944891SThierry Reding <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 302963944891SThierry Reding <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 303063944891SThierry Reding interrupt-parent = <&gic>; 303163944891SThierry Reding always-on; 303263944891SThierry Reding }; 303363944891SThierry Reding}; 3034