163944891SThierry Reding// SPDX-License-Identifier: GPL-2.0 263944891SThierry Reding 363944891SThierry Reding#include <dt-bindings/clock/tegra234-clock.h> 463944891SThierry Reding#include <dt-bindings/interrupt-controller/arm-gic.h> 563944891SThierry Reding#include <dt-bindings/mailbox/tegra186-hsp.h> 663944891SThierry Reding#include <dt-bindings/reset/tegra234-reset.h> 763944891SThierry Reding 863944891SThierry Reding/ { 963944891SThierry Reding compatible = "nvidia,tegra234"; 1063944891SThierry Reding interrupt-parent = <&gic>; 1163944891SThierry Reding #address-cells = <2>; 1263944891SThierry Reding #size-cells = <2>; 1363944891SThierry Reding 1463944891SThierry Reding bus@0 { 1563944891SThierry Reding compatible = "simple-bus"; 1663944891SThierry Reding #address-cells = <1>; 1763944891SThierry Reding #size-cells = <1>; 1863944891SThierry Reding 1963944891SThierry Reding ranges = <0x0 0x0 0x0 0x40000000>; 2063944891SThierry Reding 2163944891SThierry Reding misc@100000 { 2263944891SThierry Reding compatible = "nvidia,tegra234-misc"; 2363944891SThierry Reding reg = <0x00100000 0xf000>, 2463944891SThierry Reding <0x0010f000 0x1000>; 2563944891SThierry Reding status = "okay"; 2663944891SThierry Reding }; 2763944891SThierry Reding 28f0e12668SThierry Reding gpio: gpio@2200000 { 29f0e12668SThierry Reding compatible = "nvidia,tegra234-gpio"; 30f0e12668SThierry Reding reg-names = "security", "gpio"; 31f0e12668SThierry Reding reg = <0x02200000 0x10000>, 32f0e12668SThierry Reding <0x02210000 0x10000>; 33f0e12668SThierry Reding interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 34f0e12668SThierry Reding <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 35f0e12668SThierry Reding <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 36f0e12668SThierry Reding <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, 37f0e12668SThierry Reding <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 38f0e12668SThierry Reding <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 39f0e12668SThierry Reding <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 40f0e12668SThierry Reding <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 41f0e12668SThierry Reding <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 42f0e12668SThierry Reding <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 43f0e12668SThierry Reding <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 44f0e12668SThierry Reding <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 45f0e12668SThierry Reding <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 46f0e12668SThierry Reding <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 47f0e12668SThierry Reding <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 48f0e12668SThierry Reding <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 49f0e12668SThierry Reding <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 50f0e12668SThierry Reding <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 51f0e12668SThierry Reding <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 52f0e12668SThierry Reding <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 53f0e12668SThierry Reding <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 54f0e12668SThierry Reding <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 55f0e12668SThierry Reding <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 56f0e12668SThierry Reding <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 57f0e12668SThierry Reding <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 58f0e12668SThierry Reding <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 59f0e12668SThierry Reding <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 60f0e12668SThierry Reding <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 61f0e12668SThierry Reding <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 62f0e12668SThierry Reding <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 63f0e12668SThierry Reding <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 64f0e12668SThierry Reding <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 65f0e12668SThierry Reding <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 66f0e12668SThierry Reding <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 67f0e12668SThierry Reding <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 68f0e12668SThierry Reding <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 69f0e12668SThierry Reding <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 70f0e12668SThierry Reding <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 71f0e12668SThierry Reding <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 72f0e12668SThierry Reding <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 73f0e12668SThierry Reding <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 74f0e12668SThierry Reding <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 75f0e12668SThierry Reding <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 76f0e12668SThierry Reding <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 77f0e12668SThierry Reding <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 78f0e12668SThierry Reding <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 79f0e12668SThierry Reding <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 80f0e12668SThierry Reding <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 81f0e12668SThierry Reding #interrupt-cells = <2>; 82f0e12668SThierry Reding interrupt-controller; 83f0e12668SThierry Reding #gpio-cells = <2>; 84f0e12668SThierry Reding gpio-controller; 85f0e12668SThierry Reding }; 86f0e12668SThierry Reding 8763944891SThierry Reding uarta: serial@3100000 { 8863944891SThierry Reding compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart"; 8963944891SThierry Reding reg = <0x03100000 0x10000>; 9063944891SThierry Reding interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 9163944891SThierry Reding clocks = <&bpmp TEGRA234_CLK_UARTA>; 9263944891SThierry Reding clock-names = "serial"; 9363944891SThierry Reding resets = <&bpmp TEGRA234_RESET_UARTA>; 9463944891SThierry Reding reset-names = "serial"; 9563944891SThierry Reding status = "disabled"; 9663944891SThierry Reding }; 9763944891SThierry Reding 9863944891SThierry Reding mmc@3460000 { 9963944891SThierry Reding compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci"; 10063944891SThierry Reding reg = <0x03460000 0x20000>; 10163944891SThierry Reding interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 102e086d82dSMikko Perttunen clocks = <&bpmp TEGRA234_CLK_SDMMC4>, 103e086d82dSMikko Perttunen <&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>; 104e086d82dSMikko Perttunen clock-names = "sdhci", "tmclk"; 105e086d82dSMikko Perttunen assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC4>, 106e086d82dSMikko Perttunen <&bpmp TEGRA234_CLK_PLLC4>; 107e086d82dSMikko Perttunen assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4>; 10863944891SThierry Reding resets = <&bpmp TEGRA234_RESET_SDMMC4>; 10963944891SThierry Reding reset-names = "sdhci"; 110e086d82dSMikko Perttunen nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 111e086d82dSMikko Perttunen nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 112e086d82dSMikko Perttunen nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 113e086d82dSMikko Perttunen nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; 114e086d82dSMikko Perttunen nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 115e086d82dSMikko Perttunen nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>; 116e086d82dSMikko Perttunen nvidia,default-tap = <0x8>; 117e086d82dSMikko Perttunen nvidia,default-trim = <0x14>; 118e086d82dSMikko Perttunen nvidia,dqs-trim = <40>; 119e086d82dSMikko Perttunen supports-cqe; 12063944891SThierry Reding status = "disabled"; 12163944891SThierry Reding }; 12263944891SThierry Reding 12363944891SThierry Reding fuse@3810000 { 12463944891SThierry Reding compatible = "nvidia,tegra234-efuse"; 12563944891SThierry Reding reg = <0x03810000 0x10000>; 12663944891SThierry Reding clocks = <&bpmp TEGRA234_CLK_FUSE>; 12763944891SThierry Reding clock-names = "fuse"; 12863944891SThierry Reding }; 12963944891SThierry Reding 13063944891SThierry Reding hsp_top0: hsp@3c00000 { 13163944891SThierry Reding compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; 13263944891SThierry Reding reg = <0x03c00000 0xa0000>; 13363944891SThierry Reding interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 13463944891SThierry Reding <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 13563944891SThierry Reding <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 13663944891SThierry Reding <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 13763944891SThierry Reding <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 13863944891SThierry Reding <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 13963944891SThierry Reding <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 14063944891SThierry Reding <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 14163944891SThierry Reding <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 14263944891SThierry Reding interrupt-names = "doorbell", "shared0", "shared1", "shared2", 14363944891SThierry Reding "shared3", "shared4", "shared5", "shared6", 14463944891SThierry Reding "shared7"; 14563944891SThierry Reding #mbox-cells = <2>; 14663944891SThierry Reding }; 14763944891SThierry Reding 14863944891SThierry Reding hsp_aon: hsp@c150000 { 14963944891SThierry Reding compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; 15063944891SThierry Reding reg = <0x0c150000 0x90000>; 15163944891SThierry Reding interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 15263944891SThierry Reding <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 15363944891SThierry Reding <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 15463944891SThierry Reding <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 15563944891SThierry Reding /* 15663944891SThierry Reding * Shared interrupt 0 is routed only to AON/SPE, so 15763944891SThierry Reding * we only have 4 shared interrupts for the CCPLEX. 15863944891SThierry Reding */ 15963944891SThierry Reding interrupt-names = "shared1", "shared2", "shared3", "shared4"; 16063944891SThierry Reding #mbox-cells = <2>; 16163944891SThierry Reding }; 16263944891SThierry Reding 16363944891SThierry Reding rtc@c2a0000 { 16463944891SThierry Reding compatible = "nvidia,tegra234-rtc", "nvidia,tegra20-rtc"; 16563944891SThierry Reding reg = <0x0c2a0000 0x10000>; 16663944891SThierry Reding interrupt-parent = <&pmc>; 16763944891SThierry Reding interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 168e537addeSMikko Perttunen clocks = <&bpmp TEGRA234_CLK_CLK_32K>; 169e537addeSMikko Perttunen clock-names = "rtc"; 17063944891SThierry Reding status = "disabled"; 17163944891SThierry Reding }; 17263944891SThierry Reding 173f0e12668SThierry Reding gpio_aon: gpio@c2f0000 { 174f0e12668SThierry Reding compatible = "nvidia,tegra234-gpio-aon"; 175f0e12668SThierry Reding reg-names = "security", "gpio"; 176f0e12668SThierry Reding reg = <0x0c2f0000 0x1000>, 177f0e12668SThierry Reding <0x0c2f1000 0x1000>; 178f0e12668SThierry Reding interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 179f0e12668SThierry Reding <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 180f0e12668SThierry Reding <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 181f0e12668SThierry Reding <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 182f0e12668SThierry Reding #interrupt-cells = <2>; 183f0e12668SThierry Reding interrupt-controller; 184f0e12668SThierry Reding #gpio-cells = <2>; 185f0e12668SThierry Reding gpio-controller; 186f0e12668SThierry Reding }; 187f0e12668SThierry Reding 18863944891SThierry Reding pmc: pmc@c360000 { 18963944891SThierry Reding compatible = "nvidia,tegra234-pmc"; 19063944891SThierry Reding reg = <0x0c360000 0x10000>, 19163944891SThierry Reding <0x0c370000 0x10000>, 19263944891SThierry Reding <0x0c380000 0x10000>, 19363944891SThierry Reding <0x0c390000 0x10000>, 19463944891SThierry Reding <0x0c3a0000 0x10000>; 19563944891SThierry Reding reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 19663944891SThierry Reding 19763944891SThierry Reding #interrupt-cells = <2>; 19863944891SThierry Reding interrupt-controller; 19963944891SThierry Reding }; 20063944891SThierry Reding 20163944891SThierry Reding gic: interrupt-controller@f400000 { 20263944891SThierry Reding compatible = "arm,gic-v3"; 20363944891SThierry Reding reg = <0x0f400000 0x010000>, /* GICD */ 20463944891SThierry Reding <0x0f440000 0x200000>; /* GICR */ 20563944891SThierry Reding interrupt-parent = <&gic>; 20663944891SThierry Reding interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 20763944891SThierry Reding 20863944891SThierry Reding #redistributor-regions = <1>; 20963944891SThierry Reding #interrupt-cells = <3>; 21063944891SThierry Reding interrupt-controller; 21163944891SThierry Reding }; 21263944891SThierry Reding }; 21363944891SThierry Reding 2147fa30752SThierry Reding sram@40000000 { 21563944891SThierry Reding compatible = "nvidia,tegra234-sysram", "mmio-sram"; 21698094be1SMikko Perttunen reg = <0x0 0x40000000 0x0 0x80000>; 21763944891SThierry Reding #address-cells = <1>; 21863944891SThierry Reding #size-cells = <1>; 21998094be1SMikko Perttunen ranges = <0x0 0x0 0x40000000 0x80000>; 22063944891SThierry Reding 22198094be1SMikko Perttunen cpu_bpmp_tx: sram@70000 { 22298094be1SMikko Perttunen reg = <0x70000 0x1000>; 22363944891SThierry Reding label = "cpu-bpmp-tx"; 22463944891SThierry Reding pool; 22563944891SThierry Reding }; 22663944891SThierry Reding 22798094be1SMikko Perttunen cpu_bpmp_rx: sram@71000 { 22898094be1SMikko Perttunen reg = <0x71000 0x1000>; 22963944891SThierry Reding label = "cpu-bpmp-rx"; 23063944891SThierry Reding pool; 23163944891SThierry Reding }; 23263944891SThierry Reding }; 23363944891SThierry Reding 23463944891SThierry Reding bpmp: bpmp { 23563944891SThierry Reding compatible = "nvidia,tegra234-bpmp", "nvidia,tegra186-bpmp"; 23663944891SThierry Reding mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 23763944891SThierry Reding TEGRA_HSP_DB_MASTER_BPMP>; 2387fa30752SThierry Reding shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; 23963944891SThierry Reding #clock-cells = <1>; 24063944891SThierry Reding #reset-cells = <1>; 24163944891SThierry Reding #power-domain-cells = <1>; 24263944891SThierry Reding 24363944891SThierry Reding bpmp_i2c: i2c { 24463944891SThierry Reding compatible = "nvidia,tegra186-bpmp-i2c"; 24563944891SThierry Reding nvidia,bpmp-bus-id = <5>; 24663944891SThierry Reding #address-cells = <1>; 24763944891SThierry Reding #size-cells = <0>; 24863944891SThierry Reding }; 24963944891SThierry Reding }; 25063944891SThierry Reding 25163944891SThierry Reding cpus { 25263944891SThierry Reding #address-cells = <1>; 25363944891SThierry Reding #size-cells = <0>; 25463944891SThierry Reding 255*a12cf5c3SThierry Reding cpu0_0: cpu@0 { 256*a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 25763944891SThierry Reding device_type = "cpu"; 258*a12cf5c3SThierry Reding reg = <0x00000>; 25963944891SThierry Reding 26063944891SThierry Reding enable-method = "psci"; 261*a12cf5c3SThierry Reding 262*a12cf5c3SThierry Reding i-cache-size = <65536>; 263*a12cf5c3SThierry Reding i-cache-line-size = <64>; 264*a12cf5c3SThierry Reding i-cache-sets = <256>; 265*a12cf5c3SThierry Reding d-cache-size = <65536>; 266*a12cf5c3SThierry Reding d-cache-line-size = <64>; 267*a12cf5c3SThierry Reding d-cache-sets = <256>; 268*a12cf5c3SThierry Reding next-level-cache = <&l2c0_0>; 26963944891SThierry Reding }; 270*a12cf5c3SThierry Reding 271*a12cf5c3SThierry Reding cpu0_1: cpu@100 { 272*a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 273*a12cf5c3SThierry Reding device_type = "cpu"; 274*a12cf5c3SThierry Reding reg = <0x00100>; 275*a12cf5c3SThierry Reding 276*a12cf5c3SThierry Reding enable-method = "psci"; 277*a12cf5c3SThierry Reding 278*a12cf5c3SThierry Reding i-cache-size = <65536>; 279*a12cf5c3SThierry Reding i-cache-line-size = <64>; 280*a12cf5c3SThierry Reding i-cache-sets = <256>; 281*a12cf5c3SThierry Reding d-cache-size = <65536>; 282*a12cf5c3SThierry Reding d-cache-line-size = <64>; 283*a12cf5c3SThierry Reding d-cache-sets = <256>; 284*a12cf5c3SThierry Reding next-level-cache = <&l2c0_1>; 285*a12cf5c3SThierry Reding }; 286*a12cf5c3SThierry Reding 287*a12cf5c3SThierry Reding cpu0_2: cpu@200 { 288*a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 289*a12cf5c3SThierry Reding device_type = "cpu"; 290*a12cf5c3SThierry Reding reg = <0x00200>; 291*a12cf5c3SThierry Reding 292*a12cf5c3SThierry Reding enable-method = "psci"; 293*a12cf5c3SThierry Reding 294*a12cf5c3SThierry Reding i-cache-size = <65536>; 295*a12cf5c3SThierry Reding i-cache-line-size = <64>; 296*a12cf5c3SThierry Reding i-cache-sets = <256>; 297*a12cf5c3SThierry Reding d-cache-size = <65536>; 298*a12cf5c3SThierry Reding d-cache-line-size = <64>; 299*a12cf5c3SThierry Reding d-cache-sets = <256>; 300*a12cf5c3SThierry Reding next-level-cache = <&l2c0_2>; 301*a12cf5c3SThierry Reding }; 302*a12cf5c3SThierry Reding 303*a12cf5c3SThierry Reding cpu0_3: cpu@300 { 304*a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 305*a12cf5c3SThierry Reding device_type = "cpu"; 306*a12cf5c3SThierry Reding reg = <0x00300>; 307*a12cf5c3SThierry Reding 308*a12cf5c3SThierry Reding enable-method = "psci"; 309*a12cf5c3SThierry Reding 310*a12cf5c3SThierry Reding i-cache-size = <65536>; 311*a12cf5c3SThierry Reding i-cache-line-size = <64>; 312*a12cf5c3SThierry Reding i-cache-sets = <256>; 313*a12cf5c3SThierry Reding d-cache-size = <65536>; 314*a12cf5c3SThierry Reding d-cache-line-size = <64>; 315*a12cf5c3SThierry Reding d-cache-sets = <256>; 316*a12cf5c3SThierry Reding next-level-cache = <&l2c0_3>; 317*a12cf5c3SThierry Reding }; 318*a12cf5c3SThierry Reding 319*a12cf5c3SThierry Reding cpu1_0: cpu@10000 { 320*a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 321*a12cf5c3SThierry Reding device_type = "cpu"; 322*a12cf5c3SThierry Reding reg = <0x10000>; 323*a12cf5c3SThierry Reding 324*a12cf5c3SThierry Reding enable-method = "psci"; 325*a12cf5c3SThierry Reding 326*a12cf5c3SThierry Reding i-cache-size = <65536>; 327*a12cf5c3SThierry Reding i-cache-line-size = <64>; 328*a12cf5c3SThierry Reding i-cache-sets = <256>; 329*a12cf5c3SThierry Reding d-cache-size = <65536>; 330*a12cf5c3SThierry Reding d-cache-line-size = <64>; 331*a12cf5c3SThierry Reding d-cache-sets = <256>; 332*a12cf5c3SThierry Reding next-level-cache = <&l2c1_0>; 333*a12cf5c3SThierry Reding }; 334*a12cf5c3SThierry Reding 335*a12cf5c3SThierry Reding cpu1_1: cpu@10100 { 336*a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 337*a12cf5c3SThierry Reding device_type = "cpu"; 338*a12cf5c3SThierry Reding reg = <0x10100>; 339*a12cf5c3SThierry Reding 340*a12cf5c3SThierry Reding enable-method = "psci"; 341*a12cf5c3SThierry Reding 342*a12cf5c3SThierry Reding i-cache-size = <65536>; 343*a12cf5c3SThierry Reding i-cache-line-size = <64>; 344*a12cf5c3SThierry Reding i-cache-sets = <256>; 345*a12cf5c3SThierry Reding d-cache-size = <65536>; 346*a12cf5c3SThierry Reding d-cache-line-size = <64>; 347*a12cf5c3SThierry Reding d-cache-sets = <256>; 348*a12cf5c3SThierry Reding next-level-cache = <&l2c1_1>; 349*a12cf5c3SThierry Reding }; 350*a12cf5c3SThierry Reding 351*a12cf5c3SThierry Reding cpu1_2: cpu@10200 { 352*a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 353*a12cf5c3SThierry Reding device_type = "cpu"; 354*a12cf5c3SThierry Reding reg = <0x10200>; 355*a12cf5c3SThierry Reding 356*a12cf5c3SThierry Reding enable-method = "psci"; 357*a12cf5c3SThierry Reding 358*a12cf5c3SThierry Reding i-cache-size = <65536>; 359*a12cf5c3SThierry Reding i-cache-line-size = <64>; 360*a12cf5c3SThierry Reding i-cache-sets = <256>; 361*a12cf5c3SThierry Reding d-cache-size = <65536>; 362*a12cf5c3SThierry Reding d-cache-line-size = <64>; 363*a12cf5c3SThierry Reding d-cache-sets = <256>; 364*a12cf5c3SThierry Reding next-level-cache = <&l2c1_2>; 365*a12cf5c3SThierry Reding }; 366*a12cf5c3SThierry Reding 367*a12cf5c3SThierry Reding cpu1_3: cpu@10300 { 368*a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 369*a12cf5c3SThierry Reding device_type = "cpu"; 370*a12cf5c3SThierry Reding reg = <0x10300>; 371*a12cf5c3SThierry Reding 372*a12cf5c3SThierry Reding enable-method = "psci"; 373*a12cf5c3SThierry Reding 374*a12cf5c3SThierry Reding i-cache-size = <65536>; 375*a12cf5c3SThierry Reding i-cache-line-size = <64>; 376*a12cf5c3SThierry Reding i-cache-sets = <256>; 377*a12cf5c3SThierry Reding d-cache-size = <65536>; 378*a12cf5c3SThierry Reding d-cache-line-size = <64>; 379*a12cf5c3SThierry Reding d-cache-sets = <256>; 380*a12cf5c3SThierry Reding next-level-cache = <&l2c1_3>; 381*a12cf5c3SThierry Reding }; 382*a12cf5c3SThierry Reding 383*a12cf5c3SThierry Reding cpu2_0: cpu@20000 { 384*a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 385*a12cf5c3SThierry Reding device_type = "cpu"; 386*a12cf5c3SThierry Reding reg = <0x20000>; 387*a12cf5c3SThierry Reding 388*a12cf5c3SThierry Reding enable-method = "psci"; 389*a12cf5c3SThierry Reding 390*a12cf5c3SThierry Reding i-cache-size = <65536>; 391*a12cf5c3SThierry Reding i-cache-line-size = <64>; 392*a12cf5c3SThierry Reding i-cache-sets = <256>; 393*a12cf5c3SThierry Reding d-cache-size = <65536>; 394*a12cf5c3SThierry Reding d-cache-line-size = <64>; 395*a12cf5c3SThierry Reding d-cache-sets = <256>; 396*a12cf5c3SThierry Reding next-level-cache = <&l2c2_0>; 397*a12cf5c3SThierry Reding }; 398*a12cf5c3SThierry Reding 399*a12cf5c3SThierry Reding cpu2_1: cpu@20100 { 400*a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 401*a12cf5c3SThierry Reding device_type = "cpu"; 402*a12cf5c3SThierry Reding reg = <0x20100>; 403*a12cf5c3SThierry Reding 404*a12cf5c3SThierry Reding enable-method = "psci"; 405*a12cf5c3SThierry Reding 406*a12cf5c3SThierry Reding i-cache-size = <65536>; 407*a12cf5c3SThierry Reding i-cache-line-size = <64>; 408*a12cf5c3SThierry Reding i-cache-sets = <256>; 409*a12cf5c3SThierry Reding d-cache-size = <65536>; 410*a12cf5c3SThierry Reding d-cache-line-size = <64>; 411*a12cf5c3SThierry Reding d-cache-sets = <256>; 412*a12cf5c3SThierry Reding next-level-cache = <&l2c2_1>; 413*a12cf5c3SThierry Reding }; 414*a12cf5c3SThierry Reding 415*a12cf5c3SThierry Reding cpu2_2: cpu@20200 { 416*a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 417*a12cf5c3SThierry Reding device_type = "cpu"; 418*a12cf5c3SThierry Reding reg = <0x20200>; 419*a12cf5c3SThierry Reding 420*a12cf5c3SThierry Reding enable-method = "psci"; 421*a12cf5c3SThierry Reding 422*a12cf5c3SThierry Reding i-cache-size = <65536>; 423*a12cf5c3SThierry Reding i-cache-line-size = <64>; 424*a12cf5c3SThierry Reding i-cache-sets = <256>; 425*a12cf5c3SThierry Reding d-cache-size = <65536>; 426*a12cf5c3SThierry Reding d-cache-line-size = <64>; 427*a12cf5c3SThierry Reding d-cache-sets = <256>; 428*a12cf5c3SThierry Reding next-level-cache = <&l2c2_2>; 429*a12cf5c3SThierry Reding }; 430*a12cf5c3SThierry Reding 431*a12cf5c3SThierry Reding cpu2_3: cpu@20300 { 432*a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 433*a12cf5c3SThierry Reding device_type = "cpu"; 434*a12cf5c3SThierry Reding reg = <0x20300>; 435*a12cf5c3SThierry Reding 436*a12cf5c3SThierry Reding enable-method = "psci"; 437*a12cf5c3SThierry Reding 438*a12cf5c3SThierry Reding i-cache-size = <65536>; 439*a12cf5c3SThierry Reding i-cache-line-size = <64>; 440*a12cf5c3SThierry Reding i-cache-sets = <256>; 441*a12cf5c3SThierry Reding d-cache-size = <65536>; 442*a12cf5c3SThierry Reding d-cache-line-size = <64>; 443*a12cf5c3SThierry Reding d-cache-sets = <256>; 444*a12cf5c3SThierry Reding next-level-cache = <&l2c2_3>; 445*a12cf5c3SThierry Reding }; 446*a12cf5c3SThierry Reding 447*a12cf5c3SThierry Reding cpu-map { 448*a12cf5c3SThierry Reding cluster0 { 449*a12cf5c3SThierry Reding core0 { 450*a12cf5c3SThierry Reding cpu = <&cpu0_0>; 451*a12cf5c3SThierry Reding }; 452*a12cf5c3SThierry Reding 453*a12cf5c3SThierry Reding core1 { 454*a12cf5c3SThierry Reding cpu = <&cpu0_1>; 455*a12cf5c3SThierry Reding }; 456*a12cf5c3SThierry Reding 457*a12cf5c3SThierry Reding core2 { 458*a12cf5c3SThierry Reding cpu = <&cpu0_2>; 459*a12cf5c3SThierry Reding }; 460*a12cf5c3SThierry Reding 461*a12cf5c3SThierry Reding core3 { 462*a12cf5c3SThierry Reding cpu = <&cpu0_3>; 463*a12cf5c3SThierry Reding }; 464*a12cf5c3SThierry Reding }; 465*a12cf5c3SThierry Reding 466*a12cf5c3SThierry Reding cluster1 { 467*a12cf5c3SThierry Reding core0 { 468*a12cf5c3SThierry Reding cpu = <&cpu1_0>; 469*a12cf5c3SThierry Reding }; 470*a12cf5c3SThierry Reding 471*a12cf5c3SThierry Reding core1 { 472*a12cf5c3SThierry Reding cpu = <&cpu1_1>; 473*a12cf5c3SThierry Reding }; 474*a12cf5c3SThierry Reding 475*a12cf5c3SThierry Reding core2 { 476*a12cf5c3SThierry Reding cpu = <&cpu1_2>; 477*a12cf5c3SThierry Reding }; 478*a12cf5c3SThierry Reding 479*a12cf5c3SThierry Reding core3 { 480*a12cf5c3SThierry Reding cpu = <&cpu1_3>; 481*a12cf5c3SThierry Reding }; 482*a12cf5c3SThierry Reding }; 483*a12cf5c3SThierry Reding 484*a12cf5c3SThierry Reding cluster2 { 485*a12cf5c3SThierry Reding core0 { 486*a12cf5c3SThierry Reding cpu = <&cpu2_0>; 487*a12cf5c3SThierry Reding }; 488*a12cf5c3SThierry Reding 489*a12cf5c3SThierry Reding core1 { 490*a12cf5c3SThierry Reding cpu = <&cpu2_1>; 491*a12cf5c3SThierry Reding }; 492*a12cf5c3SThierry Reding 493*a12cf5c3SThierry Reding core2 { 494*a12cf5c3SThierry Reding cpu = <&cpu2_2>; 495*a12cf5c3SThierry Reding }; 496*a12cf5c3SThierry Reding 497*a12cf5c3SThierry Reding core3 { 498*a12cf5c3SThierry Reding cpu = <&cpu2_3>; 499*a12cf5c3SThierry Reding }; 500*a12cf5c3SThierry Reding }; 501*a12cf5c3SThierry Reding }; 502*a12cf5c3SThierry Reding 503*a12cf5c3SThierry Reding l2c0_0: l2-cache00 { 504*a12cf5c3SThierry Reding cache-size = <262144>; 505*a12cf5c3SThierry Reding cache-line-size = <64>; 506*a12cf5c3SThierry Reding cache-sets = <512>; 507*a12cf5c3SThierry Reding cache-unified; 508*a12cf5c3SThierry Reding next-level-cache = <&l3c0>; 509*a12cf5c3SThierry Reding }; 510*a12cf5c3SThierry Reding 511*a12cf5c3SThierry Reding l2c0_1: l2-cache01 { 512*a12cf5c3SThierry Reding cache-size = <262144>; 513*a12cf5c3SThierry Reding cache-line-size = <64>; 514*a12cf5c3SThierry Reding cache-sets = <512>; 515*a12cf5c3SThierry Reding cache-unified; 516*a12cf5c3SThierry Reding next-level-cache = <&l3c0>; 517*a12cf5c3SThierry Reding }; 518*a12cf5c3SThierry Reding 519*a12cf5c3SThierry Reding l2c0_2: l2-cache02 { 520*a12cf5c3SThierry Reding cache-size = <262144>; 521*a12cf5c3SThierry Reding cache-line-size = <64>; 522*a12cf5c3SThierry Reding cache-sets = <512>; 523*a12cf5c3SThierry Reding cache-unified; 524*a12cf5c3SThierry Reding next-level-cache = <&l3c0>; 525*a12cf5c3SThierry Reding }; 526*a12cf5c3SThierry Reding 527*a12cf5c3SThierry Reding l2c0_3: l2-cache03 { 528*a12cf5c3SThierry Reding cache-size = <262144>; 529*a12cf5c3SThierry Reding cache-line-size = <64>; 530*a12cf5c3SThierry Reding cache-sets = <512>; 531*a12cf5c3SThierry Reding cache-unified; 532*a12cf5c3SThierry Reding next-level-cache = <&l3c0>; 533*a12cf5c3SThierry Reding }; 534*a12cf5c3SThierry Reding 535*a12cf5c3SThierry Reding l2c1_0: l2-cache10 { 536*a12cf5c3SThierry Reding cache-size = <262144>; 537*a12cf5c3SThierry Reding cache-line-size = <64>; 538*a12cf5c3SThierry Reding cache-sets = <512>; 539*a12cf5c3SThierry Reding cache-unified; 540*a12cf5c3SThierry Reding next-level-cache = <&l3c1>; 541*a12cf5c3SThierry Reding }; 542*a12cf5c3SThierry Reding 543*a12cf5c3SThierry Reding l2c1_1: l2-cache11 { 544*a12cf5c3SThierry Reding cache-size = <262144>; 545*a12cf5c3SThierry Reding cache-line-size = <64>; 546*a12cf5c3SThierry Reding cache-sets = <512>; 547*a12cf5c3SThierry Reding cache-unified; 548*a12cf5c3SThierry Reding next-level-cache = <&l3c1>; 549*a12cf5c3SThierry Reding }; 550*a12cf5c3SThierry Reding 551*a12cf5c3SThierry Reding l2c1_2: l2-cache12 { 552*a12cf5c3SThierry Reding cache-size = <262144>; 553*a12cf5c3SThierry Reding cache-line-size = <64>; 554*a12cf5c3SThierry Reding cache-sets = <512>; 555*a12cf5c3SThierry Reding cache-unified; 556*a12cf5c3SThierry Reding next-level-cache = <&l3c1>; 557*a12cf5c3SThierry Reding }; 558*a12cf5c3SThierry Reding 559*a12cf5c3SThierry Reding l2c1_3: l2-cache13 { 560*a12cf5c3SThierry Reding cache-size = <262144>; 561*a12cf5c3SThierry Reding cache-line-size = <64>; 562*a12cf5c3SThierry Reding cache-sets = <512>; 563*a12cf5c3SThierry Reding cache-unified; 564*a12cf5c3SThierry Reding next-level-cache = <&l3c1>; 565*a12cf5c3SThierry Reding }; 566*a12cf5c3SThierry Reding 567*a12cf5c3SThierry Reding l2c2_0: l2-cache20 { 568*a12cf5c3SThierry Reding cache-size = <262144>; 569*a12cf5c3SThierry Reding cache-line-size = <64>; 570*a12cf5c3SThierry Reding cache-sets = <512>; 571*a12cf5c3SThierry Reding cache-unified; 572*a12cf5c3SThierry Reding next-level-cache = <&l3c2>; 573*a12cf5c3SThierry Reding }; 574*a12cf5c3SThierry Reding 575*a12cf5c3SThierry Reding l2c2_1: l2-cache21 { 576*a12cf5c3SThierry Reding cache-size = <262144>; 577*a12cf5c3SThierry Reding cache-line-size = <64>; 578*a12cf5c3SThierry Reding cache-sets = <512>; 579*a12cf5c3SThierry Reding cache-unified; 580*a12cf5c3SThierry Reding next-level-cache = <&l3c2>; 581*a12cf5c3SThierry Reding }; 582*a12cf5c3SThierry Reding 583*a12cf5c3SThierry Reding l2c2_2: l2-cache22 { 584*a12cf5c3SThierry Reding cache-size = <262144>; 585*a12cf5c3SThierry Reding cache-line-size = <64>; 586*a12cf5c3SThierry Reding cache-sets = <512>; 587*a12cf5c3SThierry Reding cache-unified; 588*a12cf5c3SThierry Reding next-level-cache = <&l3c2>; 589*a12cf5c3SThierry Reding }; 590*a12cf5c3SThierry Reding 591*a12cf5c3SThierry Reding l2c2_3: l2-cache23 { 592*a12cf5c3SThierry Reding cache-size = <262144>; 593*a12cf5c3SThierry Reding cache-line-size = <64>; 594*a12cf5c3SThierry Reding cache-sets = <512>; 595*a12cf5c3SThierry Reding cache-unified; 596*a12cf5c3SThierry Reding next-level-cache = <&l3c2>; 597*a12cf5c3SThierry Reding }; 598*a12cf5c3SThierry Reding 599*a12cf5c3SThierry Reding l3c0: l3-cache0 { 600*a12cf5c3SThierry Reding cache-size = <2097152>; 601*a12cf5c3SThierry Reding cache-line-size = <64>; 602*a12cf5c3SThierry Reding cache-sets = <2048>; 603*a12cf5c3SThierry Reding }; 604*a12cf5c3SThierry Reding 605*a12cf5c3SThierry Reding l3c1: l3-cache1 { 606*a12cf5c3SThierry Reding cache-size = <2097152>; 607*a12cf5c3SThierry Reding cache-line-size = <64>; 608*a12cf5c3SThierry Reding cache-sets = <2048>; 609*a12cf5c3SThierry Reding }; 610*a12cf5c3SThierry Reding 611*a12cf5c3SThierry Reding l3c2: l3-cache2 { 612*a12cf5c3SThierry Reding cache-size = <2097152>; 613*a12cf5c3SThierry Reding cache-line-size = <64>; 614*a12cf5c3SThierry Reding cache-sets = <2048>; 615*a12cf5c3SThierry Reding }; 616*a12cf5c3SThierry Reding }; 617*a12cf5c3SThierry Reding 618*a12cf5c3SThierry Reding pmu { 619*a12cf5c3SThierry Reding compatible = "arm,cortex-a78-pmu"; 620*a12cf5c3SThierry Reding interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 621*a12cf5c3SThierry Reding status = "okay"; 62263944891SThierry Reding }; 62363944891SThierry Reding 62463944891SThierry Reding psci { 62563944891SThierry Reding compatible = "arm,psci-1.0"; 62663944891SThierry Reding status = "okay"; 62763944891SThierry Reding method = "smc"; 62863944891SThierry Reding }; 62963944891SThierry Reding 63006ad2ec4SMikko Perttunen tcu: serial { 63106ad2ec4SMikko Perttunen compatible = "nvidia,tegra234-tcu", "nvidia,tegra194-tcu"; 63206ad2ec4SMikko Perttunen mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 63306ad2ec4SMikko Perttunen <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 63406ad2ec4SMikko Perttunen mbox-names = "rx", "tx"; 63506ad2ec4SMikko Perttunen status = "disabled"; 63606ad2ec4SMikko Perttunen }; 63706ad2ec4SMikko Perttunen 63863944891SThierry Reding timer { 63963944891SThierry Reding compatible = "arm,armv8-timer"; 64063944891SThierry Reding interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 64163944891SThierry Reding <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 64263944891SThierry Reding <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 64363944891SThierry Reding <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 64463944891SThierry Reding interrupt-parent = <&gic>; 64563944891SThierry Reding always-on; 64663944891SThierry Reding }; 64763944891SThierry Reding}; 648