163944891SThierry Reding// SPDX-License-Identifier: GPL-2.0 263944891SThierry Reding 363944891SThierry Reding#include <dt-bindings/clock/tegra234-clock.h> 4699349e0SThierry Reding#include <dt-bindings/gpio/tegra234-gpio.h> 563944891SThierry Reding#include <dt-bindings/interrupt-controller/arm-gic.h> 663944891SThierry Reding#include <dt-bindings/mailbox/tegra186-hsp.h> 7eed280dfSThierry Reding#include <dt-bindings/memory/tegra234-mc.h> 8c71e1897SThierry Reding#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 9dc94a94dSSameer Pujar#include <dt-bindings/power/tegra234-powergate.h> 1063944891SThierry Reding#include <dt-bindings/reset/tegra234-reset.h> 1163944891SThierry Reding 1263944891SThierry Reding/ { 1363944891SThierry Reding compatible = "nvidia,tegra234"; 1463944891SThierry Reding interrupt-parent = <&gic>; 1563944891SThierry Reding #address-cells = <2>; 1663944891SThierry Reding #size-cells = <2>; 1763944891SThierry Reding 1863944891SThierry Reding bus@0 { 1963944891SThierry Reding compatible = "simple-bus"; 2063944891SThierry Reding 212838cfddSThierry Reding #address-cells = <2>; 222838cfddSThierry Reding #size-cells = <2>; 232838cfddSThierry Reding ranges = <0x0 0x0 0x0 0x0 0x0 0x40000000>; 2463944891SThierry Reding 25*79ed18d9SThierry Reding misc@100000 { 26*79ed18d9SThierry Reding compatible = "nvidia,tegra234-misc"; 27*79ed18d9SThierry Reding reg = <0x0 0x00100000 0x0 0xf000>, 28*79ed18d9SThierry Reding <0x0 0x0010f000 0x0 0x1000>; 29*79ed18d9SThierry Reding status = "okay"; 30*79ed18d9SThierry Reding }; 31*79ed18d9SThierry Reding 32*79ed18d9SThierry Reding timer@2080000 { 33*79ed18d9SThierry Reding compatible = "nvidia,tegra234-timer"; 34*79ed18d9SThierry Reding reg = <0x0 0x02080000 0x0 0x00121000>; 35*79ed18d9SThierry Reding interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 36*79ed18d9SThierry Reding <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 37*79ed18d9SThierry Reding <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 38*79ed18d9SThierry Reding <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 39*79ed18d9SThierry Reding <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 40*79ed18d9SThierry Reding <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 41*79ed18d9SThierry Reding <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 42*79ed18d9SThierry Reding <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 43*79ed18d9SThierry Reding <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 44*79ed18d9SThierry Reding <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 45*79ed18d9SThierry Reding <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 46*79ed18d9SThierry Reding <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 47*79ed18d9SThierry Reding <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 48*79ed18d9SThierry Reding <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 49*79ed18d9SThierry Reding <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 50*79ed18d9SThierry Reding <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 51*79ed18d9SThierry Reding status = "okay"; 52*79ed18d9SThierry Reding }; 53*79ed18d9SThierry Reding 54*79ed18d9SThierry Reding gpio: gpio@2200000 { 55*79ed18d9SThierry Reding compatible = "nvidia,tegra234-gpio"; 56*79ed18d9SThierry Reding reg-names = "security", "gpio"; 57*79ed18d9SThierry Reding reg = <0x0 0x02200000 0x0 0x10000>, 58*79ed18d9SThierry Reding <0x0 0x02210000 0x0 0x10000>; 59*79ed18d9SThierry Reding interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 60*79ed18d9SThierry Reding <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 61*79ed18d9SThierry Reding <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 62*79ed18d9SThierry Reding <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, 63*79ed18d9SThierry Reding <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 64*79ed18d9SThierry Reding <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 65*79ed18d9SThierry Reding <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 66*79ed18d9SThierry Reding <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 67*79ed18d9SThierry Reding <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 68*79ed18d9SThierry Reding <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 69*79ed18d9SThierry Reding <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 70*79ed18d9SThierry Reding <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 71*79ed18d9SThierry Reding <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 72*79ed18d9SThierry Reding <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 73*79ed18d9SThierry Reding <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 74*79ed18d9SThierry Reding <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 75*79ed18d9SThierry Reding <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 76*79ed18d9SThierry Reding <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 77*79ed18d9SThierry Reding <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 78*79ed18d9SThierry Reding <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 79*79ed18d9SThierry Reding <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 80*79ed18d9SThierry Reding <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 81*79ed18d9SThierry Reding <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 82*79ed18d9SThierry Reding <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 83*79ed18d9SThierry Reding <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 84*79ed18d9SThierry Reding <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 85*79ed18d9SThierry Reding <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 86*79ed18d9SThierry Reding <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 87*79ed18d9SThierry Reding <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 88*79ed18d9SThierry Reding <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 89*79ed18d9SThierry Reding <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 90*79ed18d9SThierry Reding <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 91*79ed18d9SThierry Reding <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 92*79ed18d9SThierry Reding <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 93*79ed18d9SThierry Reding <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 94*79ed18d9SThierry Reding <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 95*79ed18d9SThierry Reding <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 96*79ed18d9SThierry Reding <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 97*79ed18d9SThierry Reding <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 98*79ed18d9SThierry Reding <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 99*79ed18d9SThierry Reding <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 100*79ed18d9SThierry Reding <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 101*79ed18d9SThierry Reding <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 102*79ed18d9SThierry Reding <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 103*79ed18d9SThierry Reding <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 104*79ed18d9SThierry Reding <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 105*79ed18d9SThierry Reding <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 106*79ed18d9SThierry Reding <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 107*79ed18d9SThierry Reding #interrupt-cells = <2>; 108*79ed18d9SThierry Reding interrupt-controller; 109*79ed18d9SThierry Reding #gpio-cells = <2>; 110*79ed18d9SThierry Reding gpio-controller; 111*79ed18d9SThierry Reding }; 112*79ed18d9SThierry Reding 11360d2016aSAkhil R gpcdma: dma-controller@2600000 { 114f7b93a08SAkhil R compatible = "nvidia,tegra234-gpcdma", 11560d2016aSAkhil R "nvidia,tegra186-gpcdma"; 1162838cfddSThierry Reding reg = <0x0 0x2600000 0x0 0x210000>; 11760d2016aSAkhil R resets = <&bpmp TEGRA234_RESET_GPCDMA>; 11860d2016aSAkhil R reset-names = "gpcdma"; 119dd0be827SAkhil R interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 120dd0be827SAkhil R <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 12160d2016aSAkhil R <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 12260d2016aSAkhil R <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 12360d2016aSAkhil R <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 12460d2016aSAkhil R <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 12560d2016aSAkhil R <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 12660d2016aSAkhil R <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 12760d2016aSAkhil R <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 12860d2016aSAkhil R <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 12960d2016aSAkhil R <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 13060d2016aSAkhil R <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 13160d2016aSAkhil R <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 13260d2016aSAkhil R <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 13360d2016aSAkhil R <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 13460d2016aSAkhil R <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 13560d2016aSAkhil R <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 13660d2016aSAkhil R <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 13760d2016aSAkhil R <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 13860d2016aSAkhil R <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 13960d2016aSAkhil R <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 14060d2016aSAkhil R <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 14160d2016aSAkhil R <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 14260d2016aSAkhil R <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 14360d2016aSAkhil R <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 14460d2016aSAkhil R <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 14560d2016aSAkhil R <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 14660d2016aSAkhil R <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 14760d2016aSAkhil R <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 14860d2016aSAkhil R <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 14960d2016aSAkhil R <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 15060d2016aSAkhil R <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 15160d2016aSAkhil R #dma-cells = <1>; 15260d2016aSAkhil R iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 153dd0be827SAkhil R dma-channel-mask = <0xfffffffe>; 15460d2016aSAkhil R dma-coherent; 15560d2016aSAkhil R }; 15660d2016aSAkhil R 157dc94a94dSSameer Pujar aconnect@2900000 { 158dc94a94dSSameer Pujar compatible = "nvidia,tegra234-aconnect", 159dc94a94dSSameer Pujar "nvidia,tegra210-aconnect"; 160dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_APE>, 161dc94a94dSSameer Pujar <&bpmp TEGRA234_CLK_APB2APE>; 162dc94a94dSSameer Pujar clock-names = "ape", "apb2ape"; 163dc94a94dSSameer Pujar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_AUD>; 164dc94a94dSSameer Pujar status = "disabled"; 165dc94a94dSSameer Pujar 1662838cfddSThierry Reding #address-cells = <2>; 1672838cfddSThierry Reding #size-cells = <2>; 1682838cfddSThierry Reding ranges = <0x0 0x02900000 0x0 0x02900000 0x0 0x200000>; 1692838cfddSThierry Reding 170dc94a94dSSameer Pujar tegra_ahub: ahub@2900800 { 171dc94a94dSSameer Pujar compatible = "nvidia,tegra234-ahub"; 1722838cfddSThierry Reding reg = <0x0 0x02900800 0x0 0x800>; 173dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_AHUB>; 174dc94a94dSSameer Pujar clock-names = "ahub"; 175dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_AHUB>; 176dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 177dc94a94dSSameer Pujar status = "disabled"; 178dc94a94dSSameer Pujar 1792838cfddSThierry Reding #address-cells = <2>; 1802838cfddSThierry Reding #size-cells = <2>; 1812838cfddSThierry Reding ranges = <0x0 0x02900800 0x0 0x02900800 0x0 0x11800>; 1822838cfddSThierry Reding 183dc94a94dSSameer Pujar tegra_i2s1: i2s@2901000 { 184dc94a94dSSameer Pujar compatible = "nvidia,tegra234-i2s", 185dc94a94dSSameer Pujar "nvidia,tegra210-i2s"; 1862838cfddSThierry Reding reg = <0x0 0x2901000 0x0 0x100>; 187dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_I2S1>, 188dc94a94dSSameer Pujar <&bpmp TEGRA234_CLK_I2S1_SYNC_INPUT>; 189dc94a94dSSameer Pujar clock-names = "i2s", "sync_input"; 190dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_I2S1>; 191dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 192dc94a94dSSameer Pujar assigned-clock-rates = <1536000>; 193dc94a94dSSameer Pujar sound-name-prefix = "I2S1"; 194dc94a94dSSameer Pujar status = "disabled"; 195dc94a94dSSameer Pujar }; 196dc94a94dSSameer Pujar 197dc94a94dSSameer Pujar tegra_i2s2: i2s@2901100 { 198dc94a94dSSameer Pujar compatible = "nvidia,tegra234-i2s", 199dc94a94dSSameer Pujar "nvidia,tegra210-i2s"; 2002838cfddSThierry Reding reg = <0x0 0x2901100 0x0 0x100>; 201dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_I2S2>, 202dc94a94dSSameer Pujar <&bpmp TEGRA234_CLK_I2S2_SYNC_INPUT>; 203dc94a94dSSameer Pujar clock-names = "i2s", "sync_input"; 204dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_I2S2>; 205dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 206dc94a94dSSameer Pujar assigned-clock-rates = <1536000>; 207dc94a94dSSameer Pujar sound-name-prefix = "I2S2"; 208dc94a94dSSameer Pujar status = "disabled"; 209dc94a94dSSameer Pujar }; 210dc94a94dSSameer Pujar 211dc94a94dSSameer Pujar tegra_i2s3: i2s@2901200 { 212dc94a94dSSameer Pujar compatible = "nvidia,tegra234-i2s", 213dc94a94dSSameer Pujar "nvidia,tegra210-i2s"; 2142838cfddSThierry Reding reg = <0x0 0x2901200 0x0 0x100>; 215dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_I2S3>, 216dc94a94dSSameer Pujar <&bpmp TEGRA234_CLK_I2S3_SYNC_INPUT>; 217dc94a94dSSameer Pujar clock-names = "i2s", "sync_input"; 218dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_I2S3>; 219dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 220dc94a94dSSameer Pujar assigned-clock-rates = <1536000>; 221dc94a94dSSameer Pujar sound-name-prefix = "I2S3"; 222dc94a94dSSameer Pujar status = "disabled"; 223dc94a94dSSameer Pujar }; 224dc94a94dSSameer Pujar 225dc94a94dSSameer Pujar tegra_i2s4: i2s@2901300 { 226dc94a94dSSameer Pujar compatible = "nvidia,tegra234-i2s", 227dc94a94dSSameer Pujar "nvidia,tegra210-i2s"; 2282838cfddSThierry Reding reg = <0x0 0x2901300 0x0 0x100>; 229dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_I2S4>, 230dc94a94dSSameer Pujar <&bpmp TEGRA234_CLK_I2S4_SYNC_INPUT>; 231dc94a94dSSameer Pujar clock-names = "i2s", "sync_input"; 232dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_I2S4>; 233dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 234dc94a94dSSameer Pujar assigned-clock-rates = <1536000>; 235dc94a94dSSameer Pujar sound-name-prefix = "I2S4"; 236dc94a94dSSameer Pujar status = "disabled"; 237dc94a94dSSameer Pujar }; 238dc94a94dSSameer Pujar 239dc94a94dSSameer Pujar tegra_i2s5: i2s@2901400 { 240dc94a94dSSameer Pujar compatible = "nvidia,tegra234-i2s", 241dc94a94dSSameer Pujar "nvidia,tegra210-i2s"; 2422838cfddSThierry Reding reg = <0x0 0x2901400 0x0 0x100>; 243dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_I2S5>, 244dc94a94dSSameer Pujar <&bpmp TEGRA234_CLK_I2S5_SYNC_INPUT>; 245dc94a94dSSameer Pujar clock-names = "i2s", "sync_input"; 246dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_I2S5>; 247dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 248dc94a94dSSameer Pujar assigned-clock-rates = <1536000>; 249dc94a94dSSameer Pujar sound-name-prefix = "I2S5"; 250dc94a94dSSameer Pujar status = "disabled"; 251dc94a94dSSameer Pujar }; 252dc94a94dSSameer Pujar 253dc94a94dSSameer Pujar tegra_i2s6: i2s@2901500 { 254dc94a94dSSameer Pujar compatible = "nvidia,tegra234-i2s", 255dc94a94dSSameer Pujar "nvidia,tegra210-i2s"; 2562838cfddSThierry Reding reg = <0x0 0x2901500 0x0 0x100>; 257dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_I2S6>, 258dc94a94dSSameer Pujar <&bpmp TEGRA234_CLK_I2S6_SYNC_INPUT>; 259dc94a94dSSameer Pujar clock-names = "i2s", "sync_input"; 260dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_I2S6>; 261dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 262dc94a94dSSameer Pujar assigned-clock-rates = <1536000>; 263dc94a94dSSameer Pujar sound-name-prefix = "I2S6"; 264dc94a94dSSameer Pujar status = "disabled"; 265dc94a94dSSameer Pujar }; 266dc94a94dSSameer Pujar 267dc94a94dSSameer Pujar tegra_sfc1: sfc@2902000 { 268dc94a94dSSameer Pujar compatible = "nvidia,tegra234-sfc", 269dc94a94dSSameer Pujar "nvidia,tegra210-sfc"; 2702838cfddSThierry Reding reg = <0x0 0x2902000 0x0 0x200>; 271dc94a94dSSameer Pujar sound-name-prefix = "SFC1"; 272dc94a94dSSameer Pujar status = "disabled"; 273dc94a94dSSameer Pujar }; 274dc94a94dSSameer Pujar 275dc94a94dSSameer Pujar tegra_sfc2: sfc@2902200 { 276dc94a94dSSameer Pujar compatible = "nvidia,tegra234-sfc", 277dc94a94dSSameer Pujar "nvidia,tegra210-sfc"; 2782838cfddSThierry Reding reg = <0x0 0x2902200 0x0 0x200>; 279dc94a94dSSameer Pujar sound-name-prefix = "SFC2"; 280dc94a94dSSameer Pujar status = "disabled"; 281dc94a94dSSameer Pujar }; 282dc94a94dSSameer Pujar 283dc94a94dSSameer Pujar tegra_sfc3: sfc@2902400 { 284dc94a94dSSameer Pujar compatible = "nvidia,tegra234-sfc", 285dc94a94dSSameer Pujar "nvidia,tegra210-sfc"; 2862838cfddSThierry Reding reg = <0x0 0x2902400 0x0 0x200>; 287dc94a94dSSameer Pujar sound-name-prefix = "SFC3"; 288dc94a94dSSameer Pujar status = "disabled"; 289dc94a94dSSameer Pujar }; 290dc94a94dSSameer Pujar 291dc94a94dSSameer Pujar tegra_sfc4: sfc@2902600 { 292dc94a94dSSameer Pujar compatible = "nvidia,tegra234-sfc", 293dc94a94dSSameer Pujar "nvidia,tegra210-sfc"; 2942838cfddSThierry Reding reg = <0x0 0x2902600 0x0 0x200>; 295dc94a94dSSameer Pujar sound-name-prefix = "SFC4"; 296dc94a94dSSameer Pujar status = "disabled"; 297dc94a94dSSameer Pujar }; 298dc94a94dSSameer Pujar 299dc94a94dSSameer Pujar tegra_amx1: amx@2903000 { 300dc94a94dSSameer Pujar compatible = "nvidia,tegra234-amx", 301dc94a94dSSameer Pujar "nvidia,tegra194-amx"; 3022838cfddSThierry Reding reg = <0x0 0x2903000 0x0 0x100>; 303dc94a94dSSameer Pujar sound-name-prefix = "AMX1"; 304dc94a94dSSameer Pujar status = "disabled"; 305dc94a94dSSameer Pujar }; 306dc94a94dSSameer Pujar 307dc94a94dSSameer Pujar tegra_amx2: amx@2903100 { 308dc94a94dSSameer Pujar compatible = "nvidia,tegra234-amx", 309dc94a94dSSameer Pujar "nvidia,tegra194-amx"; 3102838cfddSThierry Reding reg = <0x0 0x2903100 0x0 0x100>; 311dc94a94dSSameer Pujar sound-name-prefix = "AMX2"; 312dc94a94dSSameer Pujar status = "disabled"; 313dc94a94dSSameer Pujar }; 314dc94a94dSSameer Pujar 315dc94a94dSSameer Pujar tegra_amx3: amx@2903200 { 316dc94a94dSSameer Pujar compatible = "nvidia,tegra234-amx", 317dc94a94dSSameer Pujar "nvidia,tegra194-amx"; 3182838cfddSThierry Reding reg = <0x0 0x2903200 0x0 0x100>; 319dc94a94dSSameer Pujar sound-name-prefix = "AMX3"; 320dc94a94dSSameer Pujar status = "disabled"; 321dc94a94dSSameer Pujar }; 322dc94a94dSSameer Pujar 323dc94a94dSSameer Pujar tegra_amx4: amx@2903300 { 324dc94a94dSSameer Pujar compatible = "nvidia,tegra234-amx", 325dc94a94dSSameer Pujar "nvidia,tegra194-amx"; 3262838cfddSThierry Reding reg = <0x0 0x2903300 0x0 0x100>; 327dc94a94dSSameer Pujar sound-name-prefix = "AMX4"; 328dc94a94dSSameer Pujar status = "disabled"; 329dc94a94dSSameer Pujar }; 330dc94a94dSSameer Pujar 331dc94a94dSSameer Pujar tegra_adx1: adx@2903800 { 332dc94a94dSSameer Pujar compatible = "nvidia,tegra234-adx", 333dc94a94dSSameer Pujar "nvidia,tegra210-adx"; 3342838cfddSThierry Reding reg = <0x0 0x2903800 0x0 0x100>; 335dc94a94dSSameer Pujar sound-name-prefix = "ADX1"; 336dc94a94dSSameer Pujar status = "disabled"; 337dc94a94dSSameer Pujar }; 338dc94a94dSSameer Pujar 339dc94a94dSSameer Pujar tegra_adx2: adx@2903900 { 340dc94a94dSSameer Pujar compatible = "nvidia,tegra234-adx", 341dc94a94dSSameer Pujar "nvidia,tegra210-adx"; 3422838cfddSThierry Reding reg = <0x0 0x2903900 0x0 0x100>; 343dc94a94dSSameer Pujar sound-name-prefix = "ADX2"; 344dc94a94dSSameer Pujar status = "disabled"; 345dc94a94dSSameer Pujar }; 346dc94a94dSSameer Pujar 347dc94a94dSSameer Pujar tegra_adx3: adx@2903a00 { 348dc94a94dSSameer Pujar compatible = "nvidia,tegra234-adx", 349dc94a94dSSameer Pujar "nvidia,tegra210-adx"; 3502838cfddSThierry Reding reg = <0x0 0x2903a00 0x0 0x100>; 351dc94a94dSSameer Pujar sound-name-prefix = "ADX3"; 352dc94a94dSSameer Pujar status = "disabled"; 353dc94a94dSSameer Pujar }; 354dc94a94dSSameer Pujar 355dc94a94dSSameer Pujar tegra_adx4: adx@2903b00 { 356dc94a94dSSameer Pujar compatible = "nvidia,tegra234-adx", 357dc94a94dSSameer Pujar "nvidia,tegra210-adx"; 3582838cfddSThierry Reding reg = <0x0 0x2903b00 0x0 0x100>; 359dc94a94dSSameer Pujar sound-name-prefix = "ADX4"; 360dc94a94dSSameer Pujar status = "disabled"; 361dc94a94dSSameer Pujar }; 362dc94a94dSSameer Pujar 363dc94a94dSSameer Pujar 364dc94a94dSSameer Pujar tegra_dmic1: dmic@2904000 { 365dc94a94dSSameer Pujar compatible = "nvidia,tegra234-dmic", 366dc94a94dSSameer Pujar "nvidia,tegra210-dmic"; 3672838cfddSThierry Reding reg = <0x0 0x2904000 0x0 0x100>; 368dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_DMIC1>; 369dc94a94dSSameer Pujar clock-names = "dmic"; 370dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_DMIC1>; 371dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 372dc94a94dSSameer Pujar assigned-clock-rates = <3072000>; 373dc94a94dSSameer Pujar sound-name-prefix = "DMIC1"; 374dc94a94dSSameer Pujar status = "disabled"; 375dc94a94dSSameer Pujar }; 376dc94a94dSSameer Pujar 377dc94a94dSSameer Pujar tegra_dmic2: dmic@2904100 { 378dc94a94dSSameer Pujar compatible = "nvidia,tegra234-dmic", 379dc94a94dSSameer Pujar "nvidia,tegra210-dmic"; 3802838cfddSThierry Reding reg = <0x0 0x2904100 0x0 0x100>; 381dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_DMIC2>; 382dc94a94dSSameer Pujar clock-names = "dmic"; 383dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_DMIC2>; 384dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 385dc94a94dSSameer Pujar assigned-clock-rates = <3072000>; 386dc94a94dSSameer Pujar sound-name-prefix = "DMIC2"; 387dc94a94dSSameer Pujar status = "disabled"; 388dc94a94dSSameer Pujar }; 389dc94a94dSSameer Pujar 390dc94a94dSSameer Pujar tegra_dmic3: dmic@2904200 { 391dc94a94dSSameer Pujar compatible = "nvidia,tegra234-dmic", 392dc94a94dSSameer Pujar "nvidia,tegra210-dmic"; 3932838cfddSThierry Reding reg = <0x0 0x2904200 0x0 0x100>; 394dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_DMIC3>; 395dc94a94dSSameer Pujar clock-names = "dmic"; 396dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_DMIC3>; 397dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 398dc94a94dSSameer Pujar assigned-clock-rates = <3072000>; 399dc94a94dSSameer Pujar sound-name-prefix = "DMIC3"; 400dc94a94dSSameer Pujar status = "disabled"; 401dc94a94dSSameer Pujar }; 402dc94a94dSSameer Pujar 403dc94a94dSSameer Pujar tegra_dmic4: dmic@2904300 { 404dc94a94dSSameer Pujar compatible = "nvidia,tegra234-dmic", 405dc94a94dSSameer Pujar "nvidia,tegra210-dmic"; 4062838cfddSThierry Reding reg = <0x0 0x2904300 0x0 0x100>; 407dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_DMIC4>; 408dc94a94dSSameer Pujar clock-names = "dmic"; 409dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_DMIC4>; 410dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 411dc94a94dSSameer Pujar assigned-clock-rates = <3072000>; 412dc94a94dSSameer Pujar sound-name-prefix = "DMIC4"; 413dc94a94dSSameer Pujar status = "disabled"; 414dc94a94dSSameer Pujar }; 415dc94a94dSSameer Pujar 416dc94a94dSSameer Pujar tegra_dspk1: dspk@2905000 { 417dc94a94dSSameer Pujar compatible = "nvidia,tegra234-dspk", 418dc94a94dSSameer Pujar "nvidia,tegra186-dspk"; 4192838cfddSThierry Reding reg = <0x0 0x2905000 0x0 0x100>; 420dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_DSPK1>; 421dc94a94dSSameer Pujar clock-names = "dspk"; 422dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_DSPK1>; 423dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 424dc94a94dSSameer Pujar assigned-clock-rates = <12288000>; 425dc94a94dSSameer Pujar sound-name-prefix = "DSPK1"; 426dc94a94dSSameer Pujar status = "disabled"; 427dc94a94dSSameer Pujar }; 428dc94a94dSSameer Pujar 429dc94a94dSSameer Pujar tegra_dspk2: dspk@2905100 { 430dc94a94dSSameer Pujar compatible = "nvidia,tegra234-dspk", 431dc94a94dSSameer Pujar "nvidia,tegra186-dspk"; 4322838cfddSThierry Reding reg = <0x0 0x2905100 0x0 0x100>; 433dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_DSPK2>; 434dc94a94dSSameer Pujar clock-names = "dspk"; 435dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_DSPK2>; 436dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 437dc94a94dSSameer Pujar assigned-clock-rates = <12288000>; 438dc94a94dSSameer Pujar sound-name-prefix = "DSPK2"; 439dc94a94dSSameer Pujar status = "disabled"; 440dc94a94dSSameer Pujar }; 441dc94a94dSSameer Pujar 4424b6a1b7cSSameer Pujar tegra_ope1: processing-engine@2908000 { 4434b6a1b7cSSameer Pujar compatible = "nvidia,tegra234-ope", 4444b6a1b7cSSameer Pujar "nvidia,tegra210-ope"; 4452838cfddSThierry Reding reg = <0x0 0x2908000 0x0 0x100>; 4464b6a1b7cSSameer Pujar sound-name-prefix = "OPE1"; 4474b6a1b7cSSameer Pujar status = "disabled"; 4484b6a1b7cSSameer Pujar 4492838cfddSThierry Reding #address-cells = <2>; 4502838cfddSThierry Reding #size-cells = <2>; 4512838cfddSThierry Reding ranges; 4522838cfddSThierry Reding 4534b6a1b7cSSameer Pujar equalizer@2908100 { 4544b6a1b7cSSameer Pujar compatible = "nvidia,tegra234-peq", 4554b6a1b7cSSameer Pujar "nvidia,tegra210-peq"; 4562838cfddSThierry Reding reg = <0x0 0x2908100 0x0 0x100>; 4574b6a1b7cSSameer Pujar }; 4584b6a1b7cSSameer Pujar 4594b6a1b7cSSameer Pujar dynamic-range-compressor@2908200 { 4604b6a1b7cSSameer Pujar compatible = "nvidia,tegra234-mbdrc", 4614b6a1b7cSSameer Pujar "nvidia,tegra210-mbdrc"; 4622838cfddSThierry Reding reg = <0x0 0x2908200 0x0 0x200>; 4634b6a1b7cSSameer Pujar }; 4644b6a1b7cSSameer Pujar }; 4654b6a1b7cSSameer Pujar 466dc94a94dSSameer Pujar tegra_mvc1: mvc@290a000 { 467dc94a94dSSameer Pujar compatible = "nvidia,tegra234-mvc", 468dc94a94dSSameer Pujar "nvidia,tegra210-mvc"; 4692838cfddSThierry Reding reg = <0x0 0x290a000 0x0 0x200>; 470dc94a94dSSameer Pujar sound-name-prefix = "MVC1"; 471dc94a94dSSameer Pujar status = "disabled"; 472dc94a94dSSameer Pujar }; 473dc94a94dSSameer Pujar 474dc94a94dSSameer Pujar tegra_mvc2: mvc@290a200 { 475dc94a94dSSameer Pujar compatible = "nvidia,tegra234-mvc", 476dc94a94dSSameer Pujar "nvidia,tegra210-mvc"; 4772838cfddSThierry Reding reg = <0x0 0x290a200 0x0 0x200>; 478dc94a94dSSameer Pujar sound-name-prefix = "MVC2"; 479dc94a94dSSameer Pujar status = "disabled"; 480dc94a94dSSameer Pujar }; 481dc94a94dSSameer Pujar 482dc94a94dSSameer Pujar tegra_amixer: amixer@290bb00 { 483dc94a94dSSameer Pujar compatible = "nvidia,tegra234-amixer", 484dc94a94dSSameer Pujar "nvidia,tegra210-amixer"; 4852838cfddSThierry Reding reg = <0x0 0x290bb00 0x0 0x800>; 486dc94a94dSSameer Pujar sound-name-prefix = "MIXER1"; 487dc94a94dSSameer Pujar status = "disabled"; 488dc94a94dSSameer Pujar }; 489dc94a94dSSameer Pujar 490dc94a94dSSameer Pujar tegra_admaif: admaif@290f000 { 491dc94a94dSSameer Pujar compatible = "nvidia,tegra234-admaif", 492dc94a94dSSameer Pujar "nvidia,tegra186-admaif"; 4932838cfddSThierry Reding reg = <0x0 0x0290f000 0x0 0x1000>; 494dc94a94dSSameer Pujar dmas = <&adma 1>, <&adma 1>, 495dc94a94dSSameer Pujar <&adma 2>, <&adma 2>, 496dc94a94dSSameer Pujar <&adma 3>, <&adma 3>, 497dc94a94dSSameer Pujar <&adma 4>, <&adma 4>, 498dc94a94dSSameer Pujar <&adma 5>, <&adma 5>, 499dc94a94dSSameer Pujar <&adma 6>, <&adma 6>, 500dc94a94dSSameer Pujar <&adma 7>, <&adma 7>, 501dc94a94dSSameer Pujar <&adma 8>, <&adma 8>, 502dc94a94dSSameer Pujar <&adma 9>, <&adma 9>, 503dc94a94dSSameer Pujar <&adma 10>, <&adma 10>, 504dc94a94dSSameer Pujar <&adma 11>, <&adma 11>, 505dc94a94dSSameer Pujar <&adma 12>, <&adma 12>, 506dc94a94dSSameer Pujar <&adma 13>, <&adma 13>, 507dc94a94dSSameer Pujar <&adma 14>, <&adma 14>, 508dc94a94dSSameer Pujar <&adma 15>, <&adma 15>, 509dc94a94dSSameer Pujar <&adma 16>, <&adma 16>, 510dc94a94dSSameer Pujar <&adma 17>, <&adma 17>, 511dc94a94dSSameer Pujar <&adma 18>, <&adma 18>, 512dc94a94dSSameer Pujar <&adma 19>, <&adma 19>, 513dc94a94dSSameer Pujar <&adma 20>, <&adma 20>; 514dc94a94dSSameer Pujar dma-names = "rx1", "tx1", 515dc94a94dSSameer Pujar "rx2", "tx2", 516dc94a94dSSameer Pujar "rx3", "tx3", 517dc94a94dSSameer Pujar "rx4", "tx4", 518dc94a94dSSameer Pujar "rx5", "tx5", 519dc94a94dSSameer Pujar "rx6", "tx6", 520dc94a94dSSameer Pujar "rx7", "tx7", 521dc94a94dSSameer Pujar "rx8", "tx8", 522dc94a94dSSameer Pujar "rx9", "tx9", 523dc94a94dSSameer Pujar "rx10", "tx10", 524dc94a94dSSameer Pujar "rx11", "tx11", 525dc94a94dSSameer Pujar "rx12", "tx12", 526dc94a94dSSameer Pujar "rx13", "tx13", 527dc94a94dSSameer Pujar "rx14", "tx14", 528dc94a94dSSameer Pujar "rx15", "tx15", 529dc94a94dSSameer Pujar "rx16", "tx16", 530dc94a94dSSameer Pujar "rx17", "tx17", 531dc94a94dSSameer Pujar "rx18", "tx18", 532dc94a94dSSameer Pujar "rx19", "tx19", 533dc94a94dSSameer Pujar "rx20", "tx20"; 534dc94a94dSSameer Pujar interconnects = <&mc TEGRA234_MEMORY_CLIENT_APEDMAR &emc>, 535dc94a94dSSameer Pujar <&mc TEGRA234_MEMORY_CLIENT_APEDMAW &emc>; 536dc94a94dSSameer Pujar interconnect-names = "dma-mem", "write"; 537dc94a94dSSameer Pujar iommus = <&smmu_niso0 TEGRA234_SID_APE>; 538dc94a94dSSameer Pujar status = "disabled"; 539dc94a94dSSameer Pujar }; 54047a08153SSameer Pujar 54147a08153SSameer Pujar tegra_asrc: asrc@2910000 { 54247a08153SSameer Pujar compatible = "nvidia,tegra234-asrc", 54347a08153SSameer Pujar "nvidia,tegra186-asrc"; 5442838cfddSThierry Reding reg = <0x0 0x2910000 0x0 0x2000>; 54547a08153SSameer Pujar sound-name-prefix = "ASRC1"; 54647a08153SSameer Pujar status = "disabled"; 54747a08153SSameer Pujar }; 548dc94a94dSSameer Pujar }; 549dc94a94dSSameer Pujar 550dc94a94dSSameer Pujar adma: dma-controller@2930000 { 551dc94a94dSSameer Pujar compatible = "nvidia,tegra234-adma", 552dc94a94dSSameer Pujar "nvidia,tegra186-adma"; 5532838cfddSThierry Reding reg = <0x0 0x02930000 0x0 0x20000>; 554dc94a94dSSameer Pujar interrupt-parent = <&agic>; 555dc94a94dSSameer Pujar interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 556dc94a94dSSameer Pujar <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 557dc94a94dSSameer Pujar <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 558dc94a94dSSameer Pujar <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 559dc94a94dSSameer Pujar <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 560dc94a94dSSameer Pujar <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 561dc94a94dSSameer Pujar <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 562dc94a94dSSameer Pujar <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 563dc94a94dSSameer Pujar <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 564dc94a94dSSameer Pujar <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 565dc94a94dSSameer Pujar <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 566dc94a94dSSameer Pujar <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 567dc94a94dSSameer Pujar <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 568dc94a94dSSameer Pujar <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 569dc94a94dSSameer Pujar <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 570dc94a94dSSameer Pujar <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 571dc94a94dSSameer Pujar <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 572dc94a94dSSameer Pujar <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 573dc94a94dSSameer Pujar <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 574dc94a94dSSameer Pujar <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 575dc94a94dSSameer Pujar <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 576dc94a94dSSameer Pujar <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 577dc94a94dSSameer Pujar <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 578dc94a94dSSameer Pujar <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 579dc94a94dSSameer Pujar <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 580dc94a94dSSameer Pujar <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 581dc94a94dSSameer Pujar <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 582dc94a94dSSameer Pujar <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 583dc94a94dSSameer Pujar <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 584dc94a94dSSameer Pujar <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 585dc94a94dSSameer Pujar <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 586dc94a94dSSameer Pujar <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 587dc94a94dSSameer Pujar #dma-cells = <1>; 588dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_AHUB>; 589dc94a94dSSameer Pujar clock-names = "d_audio"; 590dc94a94dSSameer Pujar status = "disabled"; 591dc94a94dSSameer Pujar }; 592dc94a94dSSameer Pujar 593dc94a94dSSameer Pujar agic: interrupt-controller@2a40000 { 594dc94a94dSSameer Pujar compatible = "nvidia,tegra234-agic", 595dc94a94dSSameer Pujar "nvidia,tegra210-agic"; 596dc94a94dSSameer Pujar #interrupt-cells = <3>; 597dc94a94dSSameer Pujar interrupt-controller; 5982838cfddSThierry Reding reg = <0x0 0x02a41000 0x0 0x1000>, 5992838cfddSThierry Reding <0x0 0x02a42000 0x0 0x2000>; 600dc94a94dSSameer Pujar interrupts = <GIC_SPI 145 601dc94a94dSSameer Pujar (GIC_CPU_MASK_SIMPLE(4) | 602dc94a94dSSameer Pujar IRQ_TYPE_LEVEL_HIGH)>; 603dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_APE>; 604dc94a94dSSameer Pujar clock-names = "clk"; 605dc94a94dSSameer Pujar status = "disabled"; 606dc94a94dSSameer Pujar }; 607dc94a94dSSameer Pujar }; 608dc94a94dSSameer Pujar 609eed280dfSThierry Reding mc: memory-controller@2c00000 { 610eed280dfSThierry Reding compatible = "nvidia,tegra234-mc"; 6112838cfddSThierry Reding reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */ 6122838cfddSThierry Reding <0x0 0x02c10000 0x0 0x10000>, /* MC Broadcast*/ 6132838cfddSThierry Reding <0x0 0x02c20000 0x0 0x10000>, /* MC0 */ 6142838cfddSThierry Reding <0x0 0x02c30000 0x0 0x10000>, /* MC1 */ 6152838cfddSThierry Reding <0x0 0x02c40000 0x0 0x10000>, /* MC2 */ 6162838cfddSThierry Reding <0x0 0x02c50000 0x0 0x10000>, /* MC3 */ 6172838cfddSThierry Reding <0x0 0x02b80000 0x0 0x10000>, /* MC4 */ 6182838cfddSThierry Reding <0x0 0x02b90000 0x0 0x10000>, /* MC5 */ 6192838cfddSThierry Reding <0x0 0x02ba0000 0x0 0x10000>, /* MC6 */ 6202838cfddSThierry Reding <0x0 0x02bb0000 0x0 0x10000>, /* MC7 */ 6212838cfddSThierry Reding <0x0 0x01700000 0x0 0x10000>, /* MC8 */ 6222838cfddSThierry Reding <0x0 0x01710000 0x0 0x10000>, /* MC9 */ 6232838cfddSThierry Reding <0x0 0x01720000 0x0 0x10000>, /* MC10 */ 6242838cfddSThierry Reding <0x0 0x01730000 0x0 0x10000>, /* MC11 */ 6252838cfddSThierry Reding <0x0 0x01740000 0x0 0x10000>, /* MC12 */ 6262838cfddSThierry Reding <0x0 0x01750000 0x0 0x10000>, /* MC13 */ 6272838cfddSThierry Reding <0x0 0x01760000 0x0 0x10000>, /* MC14 */ 6282838cfddSThierry Reding <0x0 0x01770000 0x0 0x10000>; /* MC15 */ 629000b99e5SAshish Mhetre reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3", 630000b99e5SAshish Mhetre "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", 631000b99e5SAshish Mhetre "ch11", "ch12", "ch13", "ch14", "ch15"; 632eed280dfSThierry Reding interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 633eed280dfSThierry Reding #interconnect-cells = <1>; 634eed280dfSThierry Reding status = "okay"; 635eed280dfSThierry Reding 636eed280dfSThierry Reding #address-cells = <2>; 637eed280dfSThierry Reding #size-cells = <2>; 6382838cfddSThierry Reding ranges = <0x0 0x01700000 0x0 0x01700000 0x0 0x100000>, 6392838cfddSThierry Reding <0x0 0x02b80000 0x0 0x02b80000 0x0 0x040000>, 6402838cfddSThierry Reding <0x0 0x02c00000 0x0 0x02c00000 0x0 0x100000>; 641eed280dfSThierry Reding 642eed280dfSThierry Reding /* 643eed280dfSThierry Reding * Bit 39 of addresses passing through the memory 644eed280dfSThierry Reding * controller selects the XBAR format used when memory 645eed280dfSThierry Reding * is accessed. This is used to transparently access 646eed280dfSThierry Reding * memory in the XBAR format used by the discrete GPU 647eed280dfSThierry Reding * (bit 39 set) or Tegra (bit 39 clear). 648eed280dfSThierry Reding * 649eed280dfSThierry Reding * As a consequence, the operating system must ensure 650eed280dfSThierry Reding * that bit 39 is never used implicitly, for example 651eed280dfSThierry Reding * via an I/O virtual address mapping of an IOMMU. If 652eed280dfSThierry Reding * devices require access to the XBAR switch, their 653eed280dfSThierry Reding * drivers must set this bit explicitly. 654eed280dfSThierry Reding * 655eed280dfSThierry Reding * Limit the DMA range for memory clients to [38:0]. 656eed280dfSThierry Reding */ 6572838cfddSThierry Reding dma-ranges = <0x0 0x0 0x0 0x0 0x80 0x0>; 658eed280dfSThierry Reding 659eed280dfSThierry Reding emc: external-memory-controller@2c60000 { 660eed280dfSThierry Reding compatible = "nvidia,tegra234-emc"; 661eed280dfSThierry Reding reg = <0x0 0x02c60000 0x0 0x90000>, 662eed280dfSThierry Reding <0x0 0x01780000 0x0 0x80000>; 663eed280dfSThierry Reding interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 664eed280dfSThierry Reding clocks = <&bpmp TEGRA234_CLK_EMC>; 665eed280dfSThierry Reding clock-names = "emc"; 666eed280dfSThierry Reding status = "okay"; 667eed280dfSThierry Reding 668eed280dfSThierry Reding #interconnect-cells = <0>; 669eed280dfSThierry Reding 670eed280dfSThierry Reding nvidia,bpmp = <&bpmp>; 671eed280dfSThierry Reding }; 672eed280dfSThierry Reding }; 673eed280dfSThierry Reding 67463944891SThierry Reding uarta: serial@3100000 { 67563944891SThierry Reding compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart"; 6762838cfddSThierry Reding reg = <0x0 0x03100000 0x0 0x10000>; 67763944891SThierry Reding interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 67863944891SThierry Reding clocks = <&bpmp TEGRA234_CLK_UARTA>; 67963944891SThierry Reding clock-names = "serial"; 68063944891SThierry Reding resets = <&bpmp TEGRA234_RESET_UARTA>; 68163944891SThierry Reding reset-names = "serial"; 68263944891SThierry Reding status = "disabled"; 68363944891SThierry Reding }; 68463944891SThierry Reding 685156af9deSAkhil R gen1_i2c: i2c@3160000 { 686156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 6872838cfddSThierry Reding reg = <0x0 0x3160000 0x0 0x100>; 688156af9deSAkhil R status = "disabled"; 689156af9deSAkhil R interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 690156af9deSAkhil R clock-frequency = <400000>; 691156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C1 692156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 693156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C1>; 694156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 695156af9deSAkhil R clock-names = "div-clk", "parent"; 696156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C1>; 697156af9deSAkhil R reset-names = "i2c"; 6988e442805SAkhil R iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 6998e442805SAkhil R dma-coherent; 7008e442805SAkhil R dmas = <&gpcdma 21>, <&gpcdma 21>; 7018e442805SAkhil R dma-names = "rx", "tx"; 702156af9deSAkhil R }; 703156af9deSAkhil R 704156af9deSAkhil R cam_i2c: i2c@3180000 { 705156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 7062838cfddSThierry Reding reg = <0x0 0x3180000 0x0 0x100>; 707156af9deSAkhil R interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 708156af9deSAkhil R status = "disabled"; 709156af9deSAkhil R clock-frequency = <400000>; 710156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C3 711156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 712156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C3>; 713156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 714156af9deSAkhil R clock-names = "div-clk", "parent"; 715156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C3>; 716156af9deSAkhil R reset-names = "i2c"; 7178e442805SAkhil R iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 7188e442805SAkhil R dma-coherent; 7198e442805SAkhil R dmas = <&gpcdma 23>, <&gpcdma 23>; 7208e442805SAkhil R dma-names = "rx", "tx"; 721156af9deSAkhil R }; 722156af9deSAkhil R 723156af9deSAkhil R dp_aux_ch1_i2c: i2c@3190000 { 724156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 7252838cfddSThierry Reding reg = <0x0 0x3190000 0x0 0x100>; 726156af9deSAkhil R interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 727156af9deSAkhil R status = "disabled"; 728156af9deSAkhil R clock-frequency = <100000>; 729156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C4 730156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 731156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C4>; 732156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 733156af9deSAkhil R clock-names = "div-clk", "parent"; 734156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C4>; 735156af9deSAkhil R reset-names = "i2c"; 7368e442805SAkhil R iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 7378e442805SAkhil R dma-coherent; 7388e442805SAkhil R dmas = <&gpcdma 26>, <&gpcdma 26>; 7398e442805SAkhil R dma-names = "rx", "tx"; 740156af9deSAkhil R }; 741156af9deSAkhil R 742156af9deSAkhil R dp_aux_ch0_i2c: i2c@31b0000 { 743156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 7442838cfddSThierry Reding reg = <0x0 0x31b0000 0x0 0x100>; 745156af9deSAkhil R interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 746156af9deSAkhil R status = "disabled"; 747156af9deSAkhil R clock-frequency = <100000>; 748156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C6 749156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 750156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C6>; 751156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 752156af9deSAkhil R clock-names = "div-clk", "parent"; 753156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C6>; 754156af9deSAkhil R reset-names = "i2c"; 7558e442805SAkhil R iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 7568e442805SAkhil R dma-coherent; 7578e442805SAkhil R dmas = <&gpcdma 30>, <&gpcdma 30>; 7588e442805SAkhil R dma-names = "rx", "tx"; 759156af9deSAkhil R }; 760156af9deSAkhil R 761156af9deSAkhil R dp_aux_ch2_i2c: i2c@31c0000 { 762156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 7632838cfddSThierry Reding reg = <0x0 0x31c0000 0x0 0x100>; 764156af9deSAkhil R interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 765156af9deSAkhil R status = "disabled"; 766156af9deSAkhil R clock-frequency = <100000>; 767156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C7 768156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 769156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C7>; 770156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 771156af9deSAkhil R clock-names = "div-clk", "parent"; 772156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C7>; 773156af9deSAkhil R reset-names = "i2c"; 7748e442805SAkhil R iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 7758e442805SAkhil R dma-coherent; 7768e442805SAkhil R dmas = <&gpcdma 27>, <&gpcdma 27>; 7778e442805SAkhil R dma-names = "rx", "tx"; 778156af9deSAkhil R }; 779156af9deSAkhil R 7801bbba854SJon Hunter uarti: serial@31d0000 { 7811bbba854SJon Hunter compatible = "arm,sbsa-uart"; 7822838cfddSThierry Reding reg = <0x0 0x31d0000 0x0 0x10000>; 7831bbba854SJon Hunter interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; 7841bbba854SJon Hunter status = "disabled"; 7851bbba854SJon Hunter }; 7861bbba854SJon Hunter 787156af9deSAkhil R dp_aux_ch3_i2c: i2c@31e0000 { 788156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 7892838cfddSThierry Reding reg = <0x0 0x31e0000 0x0 0x100>; 790156af9deSAkhil R interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 791156af9deSAkhil R status = "disabled"; 792156af9deSAkhil R clock-frequency = <100000>; 793156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C9 794156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 795156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C9>; 796156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 797156af9deSAkhil R clock-names = "div-clk", "parent"; 798156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C9>; 799156af9deSAkhil R reset-names = "i2c"; 8008e442805SAkhil R iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 8018e442805SAkhil R dma-coherent; 8028e442805SAkhil R dmas = <&gpcdma 31>, <&gpcdma 31>; 8038e442805SAkhil R dma-names = "rx", "tx"; 804156af9deSAkhil R }; 805156af9deSAkhil R 80671f69ffaSAshish Singhal spi@3270000 { 80771f69ffaSAshish Singhal compatible = "nvidia,tegra234-qspi"; 8082838cfddSThierry Reding reg = <0x0 0x3270000 0x0 0x1000>; 80971f69ffaSAshish Singhal interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 81071f69ffaSAshish Singhal #address-cells = <1>; 81171f69ffaSAshish Singhal #size-cells = <0>; 81271f69ffaSAshish Singhal clocks = <&bpmp TEGRA234_CLK_QSPI0_2X_PM>, 81371f69ffaSAshish Singhal <&bpmp TEGRA234_CLK_QSPI0_PM>; 81471f69ffaSAshish Singhal clock-names = "qspi", "qspi_out"; 81571f69ffaSAshish Singhal resets = <&bpmp TEGRA234_RESET_QSPI0>; 81671f69ffaSAshish Singhal status = "disabled"; 81771f69ffaSAshish Singhal }; 81871f69ffaSAshish Singhal 8195e69088dSAkhil R pwm1: pwm@3280000 { 8202566d28cSJon Hunter compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 8212838cfddSThierry Reding reg = <0x0 0x3280000 0x0 0x10000>; 8225e69088dSAkhil R clocks = <&bpmp TEGRA234_CLK_PWM1>; 8235e69088dSAkhil R resets = <&bpmp TEGRA234_RESET_PWM1>; 8245e69088dSAkhil R reset-names = "pwm"; 8255e69088dSAkhil R status = "disabled"; 8265e69088dSAkhil R #pwm-cells = <2>; 8275e69088dSAkhil R }; 8285e69088dSAkhil R 8292566d28cSJon Hunter pwm2: pwm@3290000 { 8302566d28cSJon Hunter compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 8312838cfddSThierry Reding reg = <0x0 0x3290000 0x0 0x10000>; 8322566d28cSJon Hunter clocks = <&bpmp TEGRA234_CLK_PWM2>; 8332566d28cSJon Hunter resets = <&bpmp TEGRA234_RESET_PWM2>; 8342566d28cSJon Hunter reset-names = "pwm"; 8352566d28cSJon Hunter status = "disabled"; 8362566d28cSJon Hunter #pwm-cells = <2>; 8372566d28cSJon Hunter }; 8382566d28cSJon Hunter 8392566d28cSJon Hunter pwm3: pwm@32a0000 { 8402566d28cSJon Hunter compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 8412838cfddSThierry Reding reg = <0x0 0x32a0000 0x0 0x10000>; 8422566d28cSJon Hunter clocks = <&bpmp TEGRA234_CLK_PWM3>; 8432566d28cSJon Hunter resets = <&bpmp TEGRA234_RESET_PWM3>; 8442566d28cSJon Hunter reset-names = "pwm"; 8452566d28cSJon Hunter status = "disabled"; 8462566d28cSJon Hunter #pwm-cells = <2>; 8472566d28cSJon Hunter }; 8482566d28cSJon Hunter 8492566d28cSJon Hunter pwm5: pwm@32c0000 { 8502566d28cSJon Hunter compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 8512838cfddSThierry Reding reg = <0x0 0x32c0000 0x0 0x10000>; 8522566d28cSJon Hunter clocks = <&bpmp TEGRA234_CLK_PWM5>; 8532566d28cSJon Hunter resets = <&bpmp TEGRA234_RESET_PWM5>; 8542566d28cSJon Hunter reset-names = "pwm"; 8552566d28cSJon Hunter status = "disabled"; 8562566d28cSJon Hunter #pwm-cells = <2>; 8572566d28cSJon Hunter }; 8582566d28cSJon Hunter 8592566d28cSJon Hunter pwm6: pwm@32d0000 { 8602566d28cSJon Hunter compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 8612838cfddSThierry Reding reg = <0x0 0x32d0000 0x0 0x10000>; 8622566d28cSJon Hunter clocks = <&bpmp TEGRA234_CLK_PWM6>; 8632566d28cSJon Hunter resets = <&bpmp TEGRA234_RESET_PWM6>; 8642566d28cSJon Hunter reset-names = "pwm"; 8652566d28cSJon Hunter status = "disabled"; 8662566d28cSJon Hunter #pwm-cells = <2>; 8672566d28cSJon Hunter }; 8682566d28cSJon Hunter 8692566d28cSJon Hunter pwm7: pwm@32e0000 { 8702566d28cSJon Hunter compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 8712838cfddSThierry Reding reg = <0x0 0x32e0000 0x0 0x10000>; 8722566d28cSJon Hunter clocks = <&bpmp TEGRA234_CLK_PWM7>; 8732566d28cSJon Hunter resets = <&bpmp TEGRA234_RESET_PWM7>; 8742566d28cSJon Hunter reset-names = "pwm"; 8752566d28cSJon Hunter status = "disabled"; 8762566d28cSJon Hunter #pwm-cells = <2>; 8772566d28cSJon Hunter }; 8782566d28cSJon Hunter 8792566d28cSJon Hunter pwm8: pwm@32f0000 { 8802566d28cSJon Hunter compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 8812838cfddSThierry Reding reg = <0x0 0x32f0000 0x0 0x10000>; 8822566d28cSJon Hunter clocks = <&bpmp TEGRA234_CLK_PWM8>; 8832566d28cSJon Hunter resets = <&bpmp TEGRA234_RESET_PWM8>; 8842566d28cSJon Hunter reset-names = "pwm"; 8852566d28cSJon Hunter status = "disabled"; 8862566d28cSJon Hunter #pwm-cells = <2>; 8872566d28cSJon Hunter }; 8882566d28cSJon Hunter 88971f69ffaSAshish Singhal spi@3300000 { 89071f69ffaSAshish Singhal compatible = "nvidia,tegra234-qspi"; 8912838cfddSThierry Reding reg = <0x0 0x3300000 0x0 0x1000>; 89271f69ffaSAshish Singhal interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 89371f69ffaSAshish Singhal #address-cells = <1>; 89471f69ffaSAshish Singhal #size-cells = <0>; 89571f69ffaSAshish Singhal clocks = <&bpmp TEGRA234_CLK_QSPI1_2X_PM>, 89671f69ffaSAshish Singhal <&bpmp TEGRA234_CLK_QSPI1_PM>; 89771f69ffaSAshish Singhal clock-names = "qspi", "qspi_out"; 89871f69ffaSAshish Singhal resets = <&bpmp TEGRA234_RESET_QSPI1>; 89971f69ffaSAshish Singhal status = "disabled"; 90071f69ffaSAshish Singhal }; 90171f69ffaSAshish Singhal 902d71b893aSPrathamesh Shete mmc@3400000 { 903132b552cSThierry Reding compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci"; 9042838cfddSThierry Reding reg = <0x0 0x03400000 0x0 0x20000>; 905d71b893aSPrathamesh Shete interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 906d71b893aSPrathamesh Shete clocks = <&bpmp TEGRA234_CLK_SDMMC1>, 907d71b893aSPrathamesh Shete <&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>; 908d71b893aSPrathamesh Shete clock-names = "sdhci", "tmclk"; 909d71b893aSPrathamesh Shete assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC1>, 910d71b893aSPrathamesh Shete <&bpmp TEGRA234_CLK_PLLC4_MUXED>; 911d71b893aSPrathamesh Shete assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4_MUXED>, 912d71b893aSPrathamesh Shete <&bpmp TEGRA234_CLK_PLLC4_VCO_DIV2>; 913d71b893aSPrathamesh Shete resets = <&bpmp TEGRA234_RESET_SDMMC1>; 914d71b893aSPrathamesh Shete reset-names = "sdhci"; 915d71b893aSPrathamesh Shete interconnects = <&mc TEGRA234_MEMORY_CLIENT_SDMMCRA &emc>, 916d71b893aSPrathamesh Shete <&mc TEGRA234_MEMORY_CLIENT_SDMMCWA &emc>; 917d71b893aSPrathamesh Shete interconnect-names = "dma-mem", "write"; 918d71b893aSPrathamesh Shete iommus = <&smmu_niso1 TEGRA234_SID_SDMMC1A>; 919d71b893aSPrathamesh Shete pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 920d71b893aSPrathamesh Shete pinctrl-0 = <&sdmmc1_3v3>; 921d71b893aSPrathamesh Shete pinctrl-1 = <&sdmmc1_1v8>; 922d71b893aSPrathamesh Shete nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 923d71b893aSPrathamesh Shete nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x07>; 924d71b893aSPrathamesh Shete nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 925d71b893aSPrathamesh Shete nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 926d71b893aSPrathamesh Shete nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 927d71b893aSPrathamesh Shete nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 928d71b893aSPrathamesh Shete nvidia,default-tap = <14>; 929d71b893aSPrathamesh Shete nvidia,default-trim = <0x8>; 930d71b893aSPrathamesh Shete sd-uhs-sdr25; 931d71b893aSPrathamesh Shete sd-uhs-sdr50; 932d71b893aSPrathamesh Shete sd-uhs-ddr50; 933d71b893aSPrathamesh Shete sd-uhs-sdr104; 934d71b893aSPrathamesh Shete status = "disabled"; 935d71b893aSPrathamesh Shete }; 936d71b893aSPrathamesh Shete 93763944891SThierry Reding mmc@3460000 { 93863944891SThierry Reding compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci"; 9392838cfddSThierry Reding reg = <0x0 0x03460000 0x0 0x20000>; 94063944891SThierry Reding interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 941e086d82dSMikko Perttunen clocks = <&bpmp TEGRA234_CLK_SDMMC4>, 942e086d82dSMikko Perttunen <&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>; 943e086d82dSMikko Perttunen clock-names = "sdhci", "tmclk"; 944e086d82dSMikko Perttunen assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC4>, 945e086d82dSMikko Perttunen <&bpmp TEGRA234_CLK_PLLC4>; 946e086d82dSMikko Perttunen assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4>; 94763944891SThierry Reding resets = <&bpmp TEGRA234_RESET_SDMMC4>; 94863944891SThierry Reding reset-names = "sdhci"; 9496de481e5SThierry Reding interconnects = <&mc TEGRA234_MEMORY_CLIENT_SDMMCRAB &emc>, 9506de481e5SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_SDMMCWAB &emc>; 9516de481e5SThierry Reding interconnect-names = "dma-mem", "write"; 9525710e16aSThierry Reding iommus = <&smmu_niso1 TEGRA234_SID_SDMMC4>; 953e086d82dSMikko Perttunen nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 954e086d82dSMikko Perttunen nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 955e086d82dSMikko Perttunen nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 956e086d82dSMikko Perttunen nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; 957e086d82dSMikko Perttunen nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 958e086d82dSMikko Perttunen nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>; 959e086d82dSMikko Perttunen nvidia,default-tap = <0x8>; 960e086d82dSMikko Perttunen nvidia,default-trim = <0x14>; 961e086d82dSMikko Perttunen nvidia,dqs-trim = <40>; 962e086d82dSMikko Perttunen supports-cqe; 96363944891SThierry Reding status = "disabled"; 96463944891SThierry Reding }; 96563944891SThierry Reding 966621e12a1SMohan Kumar hda@3510000 { 967b2fbcbe1SThierry Reding compatible = "nvidia,tegra234-hda"; 9682838cfddSThierry Reding reg = <0x0 0x3510000 0x0 0x10000>; 969621e12a1SMohan Kumar interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 970621e12a1SMohan Kumar clocks = <&bpmp TEGRA234_CLK_AZA_BIT>, 971621e12a1SMohan Kumar <&bpmp TEGRA234_CLK_AZA_2XBIT>; 972621e12a1SMohan Kumar clock-names = "hda", "hda2codec_2x"; 973621e12a1SMohan Kumar resets = <&bpmp TEGRA234_RESET_HDA>, 974621e12a1SMohan Kumar <&bpmp TEGRA234_RESET_HDACODEC>; 975621e12a1SMohan Kumar reset-names = "hda", "hda2codec_2x"; 976621e12a1SMohan Kumar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_DISP>; 977621e12a1SMohan Kumar interconnects = <&mc TEGRA234_MEMORY_CLIENT_HDAR &emc>, 978621e12a1SMohan Kumar <&mc TEGRA234_MEMORY_CLIENT_HDAW &emc>; 979621e12a1SMohan Kumar interconnect-names = "dma-mem", "write"; 980af4c2773SMohan Kumar iommus = <&smmu_niso0 TEGRA234_SID_HDA>; 981621e12a1SMohan Kumar status = "disabled"; 982621e12a1SMohan Kumar }; 983621e12a1SMohan Kumar 98463944891SThierry Reding fuse@3810000 { 98563944891SThierry Reding compatible = "nvidia,tegra234-efuse"; 9862838cfddSThierry Reding reg = <0x0 0x03810000 0x0 0x10000>; 98763944891SThierry Reding clocks = <&bpmp TEGRA234_CLK_FUSE>; 98863944891SThierry Reding clock-names = "fuse"; 98963944891SThierry Reding }; 99063944891SThierry Reding 99163944891SThierry Reding hsp_top0: hsp@3c00000 { 99263944891SThierry Reding compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; 9932838cfddSThierry Reding reg = <0x0 0x03c00000 0x0 0xa0000>; 99463944891SThierry Reding interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 99563944891SThierry Reding <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 99663944891SThierry Reding <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 99763944891SThierry Reding <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 99863944891SThierry Reding <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 99963944891SThierry Reding <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 100063944891SThierry Reding <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 100163944891SThierry Reding <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 100263944891SThierry Reding <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 100363944891SThierry Reding interrupt-names = "doorbell", "shared0", "shared1", "shared2", 100463944891SThierry Reding "shared3", "shared4", "shared5", "shared6", 100563944891SThierry Reding "shared7"; 100663944891SThierry Reding #mbox-cells = <2>; 100763944891SThierry Reding }; 100863944891SThierry Reding 100978159542SThierry Reding p2u_hsio_0: phy@3e00000 { 101078159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 10112838cfddSThierry Reding reg = <0x0 0x03e00000 0x0 0x10000>; 101278159542SThierry Reding reg-names = "ctl"; 101378159542SThierry Reding 101478159542SThierry Reding #phy-cells = <0>; 101578159542SThierry Reding }; 101678159542SThierry Reding 101778159542SThierry Reding p2u_hsio_1: phy@3e10000 { 101878159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 10192838cfddSThierry Reding reg = <0x0 0x03e10000 0x0 0x10000>; 102078159542SThierry Reding reg-names = "ctl"; 102178159542SThierry Reding 102278159542SThierry Reding #phy-cells = <0>; 102378159542SThierry Reding }; 102478159542SThierry Reding 102578159542SThierry Reding p2u_hsio_2: phy@3e20000 { 102678159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 10272838cfddSThierry Reding reg = <0x0 0x03e20000 0x0 0x10000>; 102878159542SThierry Reding reg-names = "ctl"; 102978159542SThierry Reding 103078159542SThierry Reding #phy-cells = <0>; 103178159542SThierry Reding }; 103278159542SThierry Reding 103378159542SThierry Reding p2u_hsio_3: phy@3e30000 { 103478159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 10352838cfddSThierry Reding reg = <0x0 0x03e30000 0x0 0x10000>; 103678159542SThierry Reding reg-names = "ctl"; 103778159542SThierry Reding 103878159542SThierry Reding #phy-cells = <0>; 103978159542SThierry Reding }; 104078159542SThierry Reding 104178159542SThierry Reding p2u_hsio_4: phy@3e40000 { 104278159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 10432838cfddSThierry Reding reg = <0x0 0x03e40000 0x0 0x10000>; 104478159542SThierry Reding reg-names = "ctl"; 104578159542SThierry Reding 104678159542SThierry Reding #phy-cells = <0>; 104778159542SThierry Reding }; 104878159542SThierry Reding 104978159542SThierry Reding p2u_hsio_5: phy@3e50000 { 105078159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 10512838cfddSThierry Reding reg = <0x0 0x03e50000 0x0 0x10000>; 105278159542SThierry Reding reg-names = "ctl"; 105378159542SThierry Reding 105478159542SThierry Reding #phy-cells = <0>; 105578159542SThierry Reding }; 105678159542SThierry Reding 105778159542SThierry Reding p2u_hsio_6: phy@3e60000 { 105878159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 10592838cfddSThierry Reding reg = <0x0 0x03e60000 0x0 0x10000>; 106078159542SThierry Reding reg-names = "ctl"; 106178159542SThierry Reding 106278159542SThierry Reding #phy-cells = <0>; 106378159542SThierry Reding }; 106478159542SThierry Reding 106578159542SThierry Reding p2u_hsio_7: phy@3e70000 { 106678159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 10672838cfddSThierry Reding reg = <0x0 0x03e70000 0x0 0x10000>; 106878159542SThierry Reding reg-names = "ctl"; 106978159542SThierry Reding 107078159542SThierry Reding #phy-cells = <0>; 107178159542SThierry Reding }; 107278159542SThierry Reding 107378159542SThierry Reding p2u_nvhs_0: phy@3e90000 { 107478159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 10752838cfddSThierry Reding reg = <0x0 0x03e90000 0x0 0x10000>; 107678159542SThierry Reding reg-names = "ctl"; 107778159542SThierry Reding 107878159542SThierry Reding #phy-cells = <0>; 107978159542SThierry Reding }; 108078159542SThierry Reding 108178159542SThierry Reding p2u_nvhs_1: phy@3ea0000 { 108278159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 10832838cfddSThierry Reding reg = <0x0 0x03ea0000 0x0 0x10000>; 108478159542SThierry Reding reg-names = "ctl"; 108578159542SThierry Reding 108678159542SThierry Reding #phy-cells = <0>; 108778159542SThierry Reding }; 108878159542SThierry Reding 108978159542SThierry Reding p2u_nvhs_2: phy@3eb0000 { 109078159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 10912838cfddSThierry Reding reg = <0x0 0x03eb0000 0x0 0x10000>; 109278159542SThierry Reding reg-names = "ctl"; 109378159542SThierry Reding 109478159542SThierry Reding #phy-cells = <0>; 109578159542SThierry Reding }; 109678159542SThierry Reding 109778159542SThierry Reding p2u_nvhs_3: phy@3ec0000 { 109878159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 10992838cfddSThierry Reding reg = <0x0 0x03ec0000 0x0 0x10000>; 110078159542SThierry Reding reg-names = "ctl"; 110178159542SThierry Reding 110278159542SThierry Reding #phy-cells = <0>; 110378159542SThierry Reding }; 110478159542SThierry Reding 110578159542SThierry Reding p2u_nvhs_4: phy@3ed0000 { 110678159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 11072838cfddSThierry Reding reg = <0x0 0x03ed0000 0x0 0x10000>; 110878159542SThierry Reding reg-names = "ctl"; 110978159542SThierry Reding 111078159542SThierry Reding #phy-cells = <0>; 111178159542SThierry Reding }; 111278159542SThierry Reding 111378159542SThierry Reding p2u_nvhs_5: phy@3ee0000 { 111478159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 11152838cfddSThierry Reding reg = <0x0 0x03ee0000 0x0 0x10000>; 111678159542SThierry Reding reg-names = "ctl"; 111778159542SThierry Reding 111878159542SThierry Reding #phy-cells = <0>; 111978159542SThierry Reding }; 112078159542SThierry Reding 112178159542SThierry Reding p2u_nvhs_6: phy@3ef0000 { 112278159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 11232838cfddSThierry Reding reg = <0x0 0x03ef0000 0x0 0x10000>; 112478159542SThierry Reding reg-names = "ctl"; 112578159542SThierry Reding 112678159542SThierry Reding #phy-cells = <0>; 112778159542SThierry Reding }; 112878159542SThierry Reding 112978159542SThierry Reding p2u_nvhs_7: phy@3f00000 { 113078159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 11312838cfddSThierry Reding reg = <0x0 0x03f00000 0x0 0x10000>; 113278159542SThierry Reding reg-names = "ctl"; 113378159542SThierry Reding 113478159542SThierry Reding #phy-cells = <0>; 113578159542SThierry Reding }; 113678159542SThierry Reding 113778159542SThierry Reding p2u_gbe_0: phy@3f20000 { 113878159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 11392838cfddSThierry Reding reg = <0x0 0x03f20000 0x0 0x10000>; 114078159542SThierry Reding reg-names = "ctl"; 114178159542SThierry Reding 114278159542SThierry Reding #phy-cells = <0>; 114378159542SThierry Reding }; 114478159542SThierry Reding 114578159542SThierry Reding p2u_gbe_1: phy@3f30000 { 114678159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 11472838cfddSThierry Reding reg = <0x0 0x03f30000 0x0 0x10000>; 114878159542SThierry Reding reg-names = "ctl"; 114978159542SThierry Reding 115078159542SThierry Reding #phy-cells = <0>; 115178159542SThierry Reding }; 115278159542SThierry Reding 115378159542SThierry Reding p2u_gbe_2: phy@3f40000 { 115478159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 11552838cfddSThierry Reding reg = <0x0 0x03f40000 0x0 0x10000>; 115678159542SThierry Reding reg-names = "ctl"; 115778159542SThierry Reding 115878159542SThierry Reding #phy-cells = <0>; 115978159542SThierry Reding }; 116078159542SThierry Reding 116178159542SThierry Reding p2u_gbe_3: phy@3f50000 { 116278159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 11632838cfddSThierry Reding reg = <0x0 0x03f50000 0x0 0x10000>; 116478159542SThierry Reding reg-names = "ctl"; 116578159542SThierry Reding 116678159542SThierry Reding #phy-cells = <0>; 116778159542SThierry Reding }; 116878159542SThierry Reding 116978159542SThierry Reding p2u_gbe_4: phy@3f60000 { 117078159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 11712838cfddSThierry Reding reg = <0x0 0x03f60000 0x0 0x10000>; 117278159542SThierry Reding reg-names = "ctl"; 117378159542SThierry Reding 117478159542SThierry Reding #phy-cells = <0>; 117578159542SThierry Reding }; 117678159542SThierry Reding 117778159542SThierry Reding p2u_gbe_5: phy@3f70000 { 117878159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 11792838cfddSThierry Reding reg = <0x0 0x03f70000 0x0 0x10000>; 118078159542SThierry Reding reg-names = "ctl"; 118178159542SThierry Reding 118278159542SThierry Reding #phy-cells = <0>; 118378159542SThierry Reding }; 118478159542SThierry Reding 118578159542SThierry Reding p2u_gbe_6: phy@3f80000 { 118678159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 11872838cfddSThierry Reding reg = <0x0 0x03f80000 0x0 0x10000>; 118878159542SThierry Reding reg-names = "ctl"; 118978159542SThierry Reding 119078159542SThierry Reding #phy-cells = <0>; 119178159542SThierry Reding }; 119278159542SThierry Reding 119378159542SThierry Reding p2u_gbe_7: phy@3f90000 { 119478159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 11952838cfddSThierry Reding reg = <0x0 0x03f90000 0x0 0x10000>; 119678159542SThierry Reding reg-names = "ctl"; 119778159542SThierry Reding 119878159542SThierry Reding #phy-cells = <0>; 119978159542SThierry Reding }; 120078159542SThierry Reding 1201610cdf31SThierry Reding ethernet@6800000 { 1202610cdf31SThierry Reding compatible = "nvidia,tegra234-mgbe"; 12032838cfddSThierry Reding reg = <0x0 0x06800000 0x0 0x10000>, 12042838cfddSThierry Reding <0x0 0x06810000 0x0 0x10000>, 12052838cfddSThierry Reding <0x0 0x068a0000 0x0 0x10000>; 1206610cdf31SThierry Reding reg-names = "hypervisor", "mac", "xpcs"; 1207610cdf31SThierry Reding interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>; 1208610cdf31SThierry Reding interrupt-names = "common"; 1209610cdf31SThierry Reding clocks = <&bpmp TEGRA234_CLK_MGBE0_APP>, 1210610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE0_MAC>, 1211610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE0_MAC_DIVIDER>, 1212610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE0_PTP_REF>, 1213610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT_M>, 1214610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT>, 1215610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE0_TX>, 1216610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE0_EEE_PCS>, 1217610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_INPUT>, 1218610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_M>, 1219610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE0_RX_PCS>, 1220610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE0_TX_PCS>; 1221610cdf31SThierry Reding clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", 1222610cdf31SThierry Reding "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", 1223610cdf31SThierry Reding "rx-pcs", "tx-pcs"; 1224610cdf31SThierry Reding resets = <&bpmp TEGRA234_RESET_MGBE0_MAC>, 1225610cdf31SThierry Reding <&bpmp TEGRA234_RESET_MGBE0_PCS>; 1226610cdf31SThierry Reding reset-names = "mac", "pcs"; 1227610cdf31SThierry Reding interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEARD &emc>, 1228610cdf31SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_MGBEAWR &emc>; 1229610cdf31SThierry Reding interconnect-names = "dma-mem", "write"; 1230610cdf31SThierry Reding iommus = <&smmu_niso0 TEGRA234_SID_MGBE>; 1231610cdf31SThierry Reding power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEA>; 1232610cdf31SThierry Reding status = "disabled"; 1233610cdf31SThierry Reding }; 1234610cdf31SThierry Reding 1235610cdf31SThierry Reding ethernet@6900000 { 1236610cdf31SThierry Reding compatible = "nvidia,tegra234-mgbe"; 12372838cfddSThierry Reding reg = <0x0 0x06900000 0x0 0x10000>, 12382838cfddSThierry Reding <0x0 0x06910000 0x0 0x10000>, 12392838cfddSThierry Reding <0x0 0x069a0000 0x0 0x10000>; 1240610cdf31SThierry Reding reg-names = "hypervisor", "mac", "xpcs"; 1241610cdf31SThierry Reding interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>; 1242610cdf31SThierry Reding interrupt-names = "common"; 1243610cdf31SThierry Reding clocks = <&bpmp TEGRA234_CLK_MGBE1_APP>, 1244610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE1_MAC>, 1245610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE1_MAC_DIVIDER>, 1246610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE1_PTP_REF>, 1247610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE1_RX_INPUT_M>, 1248610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE1_RX_INPUT>, 1249610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE1_TX>, 1250610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE1_EEE_PCS>, 1251610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE1_RX_PCS_INPUT>, 1252610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE1_RX_PCS_M>, 1253610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE1_RX_PCS>, 1254610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE1_TX_PCS>; 1255610cdf31SThierry Reding clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", 1256610cdf31SThierry Reding "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", 1257610cdf31SThierry Reding "rx-pcs", "tx-pcs"; 1258610cdf31SThierry Reding resets = <&bpmp TEGRA234_RESET_MGBE1_MAC>, 1259610cdf31SThierry Reding <&bpmp TEGRA234_RESET_MGBE1_PCS>; 1260610cdf31SThierry Reding reset-names = "mac", "pcs"; 1261610cdf31SThierry Reding interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEBRD &emc>, 1262610cdf31SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_MGBEBWR &emc>; 1263610cdf31SThierry Reding interconnect-names = "dma-mem", "write"; 1264610cdf31SThierry Reding iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF1>; 1265610cdf31SThierry Reding power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEB>; 1266610cdf31SThierry Reding status = "disabled"; 1267610cdf31SThierry Reding }; 1268610cdf31SThierry Reding 1269610cdf31SThierry Reding ethernet@6a00000 { 1270610cdf31SThierry Reding compatible = "nvidia,tegra234-mgbe"; 12712838cfddSThierry Reding reg = <0x0 0x06a00000 0x0 0x10000>, 12722838cfddSThierry Reding <0x0 0x06a10000 0x0 0x10000>, 12732838cfddSThierry Reding <0x0 0x06aa0000 0x0 0x10000>; 1274610cdf31SThierry Reding reg-names = "hypervisor", "mac", "xpcs"; 1275610cdf31SThierry Reding interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>; 1276610cdf31SThierry Reding interrupt-names = "common"; 1277610cdf31SThierry Reding clocks = <&bpmp TEGRA234_CLK_MGBE2_APP>, 1278610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE2_MAC>, 1279610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE2_MAC_DIVIDER>, 1280610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE2_PTP_REF>, 1281610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE2_RX_INPUT_M>, 1282610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE2_RX_INPUT>, 1283610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE2_TX>, 1284610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE2_EEE_PCS>, 1285610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE2_RX_PCS_INPUT>, 1286610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE2_RX_PCS_M>, 1287610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE2_RX_PCS>, 1288610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE2_TX_PCS>; 1289610cdf31SThierry Reding clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", 1290610cdf31SThierry Reding "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", 1291610cdf31SThierry Reding "rx-pcs", "tx-pcs"; 1292610cdf31SThierry Reding resets = <&bpmp TEGRA234_RESET_MGBE2_MAC>, 1293610cdf31SThierry Reding <&bpmp TEGRA234_RESET_MGBE2_PCS>; 1294610cdf31SThierry Reding reset-names = "mac", "pcs"; 1295610cdf31SThierry Reding interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBECRD &emc>, 1296610cdf31SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_MGBECWR &emc>; 1297610cdf31SThierry Reding interconnect-names = "dma-mem", "write"; 1298610cdf31SThierry Reding iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF2>; 1299610cdf31SThierry Reding power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEC>; 1300610cdf31SThierry Reding status = "disabled"; 1301610cdf31SThierry Reding }; 1302610cdf31SThierry Reding 1303610cdf31SThierry Reding ethernet@6b00000 { 1304610cdf31SThierry Reding compatible = "nvidia,tegra234-mgbe"; 13052838cfddSThierry Reding reg = <0x0 0x06b00000 0x0 0x10000>, 13062838cfddSThierry Reding <0x0 0x06b10000 0x0 0x10000>, 13072838cfddSThierry Reding <0x0 0x06ba0000 0x0 0x10000>; 1308610cdf31SThierry Reding reg-names = "hypervisor", "mac", "xpcs"; 1309610cdf31SThierry Reding interrupts = <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 1310610cdf31SThierry Reding interrupt-names = "common"; 1311610cdf31SThierry Reding clocks = <&bpmp TEGRA234_CLK_MGBE3_APP>, 1312610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE3_MAC>, 1313610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE3_MAC_DIVIDER>, 1314610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE3_PTP_REF>, 1315610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE3_RX_INPUT_M>, 1316610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE3_RX_INPUT>, 1317610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE3_TX>, 1318610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE3_EEE_PCS>, 1319610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE3_RX_PCS_INPUT>, 1320610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE3_RX_PCS_M>, 1321610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE3_RX_PCS>, 1322610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE3_TX_PCS>; 1323610cdf31SThierry Reding clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", 1324610cdf31SThierry Reding "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", 1325610cdf31SThierry Reding "rx-pcs", "tx-pcs"; 1326610cdf31SThierry Reding resets = <&bpmp TEGRA234_RESET_MGBE3_MAC>, 1327610cdf31SThierry Reding <&bpmp TEGRA234_RESET_MGBE3_PCS>; 1328610cdf31SThierry Reding reset-names = "mac", "pcs"; 1329610cdf31SThierry Reding interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEDRD &emc>, 1330610cdf31SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_MGBEDWR &emc>; 1331610cdf31SThierry Reding interconnect-names = "dma-mem", "write"; 1332610cdf31SThierry Reding iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF3>; 1333610cdf31SThierry Reding power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBED>; 1334610cdf31SThierry Reding status = "disabled"; 1335610cdf31SThierry Reding }; 1336610cdf31SThierry Reding 13375710e16aSThierry Reding smmu_niso1: iommu@8000000 { 13385710e16aSThierry Reding compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; 13392838cfddSThierry Reding reg = <0x0 0x8000000 0x0 0x1000000>, 13402838cfddSThierry Reding <0x0 0x7000000 0x0 0x1000000>; 13415710e16aSThierry Reding interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13425710e16aSThierry Reding <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, 13435710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13445710e16aSThierry Reding <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, 13455710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13465710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13475710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13485710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13495710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13505710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13515710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13525710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13535710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13545710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13555710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13565710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13575710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13585710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13595710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13605710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13615710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13625710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13635710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13645710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13655710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13665710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13675710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13685710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13695710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13705710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13715710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13725710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13735710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13745710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13755710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13765710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13775710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13785710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13795710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13805710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13815710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13825710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13835710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13845710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13855710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13865710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13875710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13885710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13895710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13905710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13915710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13925710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13935710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13945710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13955710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13965710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13975710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13985710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13995710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14005710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14015710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14025710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14035710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14045710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14055710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14065710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14075710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14085710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14095710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14105710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14115710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14125710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14135710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14145710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14155710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14165710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14175710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14185710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14195710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14205710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14215710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14225710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14235710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14245710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14255710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14265710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14275710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14285710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14295710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14305710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14315710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14325710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14335710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14345710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14355710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14365710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14375710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14385710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14395710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14405710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14415710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14425710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14435710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14445710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14455710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14465710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14475710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14485710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14495710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14505710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14515710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14525710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14535710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14545710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14555710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14565710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14575710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14585710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14595710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14605710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14615710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14625710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14635710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14645710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14655710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14665710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14675710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14685710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14695710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14705710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 14715710e16aSThierry Reding stream-match-mask = <0x7f80>; 14725710e16aSThierry Reding #global-interrupts = <2>; 14735710e16aSThierry Reding #iommu-cells = <1>; 14745710e16aSThierry Reding 14755710e16aSThierry Reding nvidia,memory-controller = <&mc>; 14765710e16aSThierry Reding status = "okay"; 14775710e16aSThierry Reding }; 14785710e16aSThierry Reding 1479302e1540SSumit Gupta sce-fabric@b600000 { 1480302e1540SSumit Gupta compatible = "nvidia,tegra234-sce-fabric"; 14812838cfddSThierry Reding reg = <0x0 0xb600000 0x0 0x40000>; 1482302e1540SSumit Gupta interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 1483302e1540SSumit Gupta status = "okay"; 1484302e1540SSumit Gupta }; 1485302e1540SSumit Gupta 1486302e1540SSumit Gupta rce-fabric@be00000 { 1487302e1540SSumit Gupta compatible = "nvidia,tegra234-rce-fabric"; 14882838cfddSThierry Reding reg = <0x0 0xbe00000 0x0 0x40000>; 1489302e1540SSumit Gupta interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 1490302e1540SSumit Gupta status = "okay"; 1491302e1540SSumit Gupta }; 1492302e1540SSumit Gupta 149363944891SThierry Reding hsp_aon: hsp@c150000 { 149463944891SThierry Reding compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; 14952838cfddSThierry Reding reg = <0x0 0x0c150000 0x0 0x90000>; 149663944891SThierry Reding interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 149763944891SThierry Reding <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 149863944891SThierry Reding <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 149963944891SThierry Reding <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 150063944891SThierry Reding /* 150163944891SThierry Reding * Shared interrupt 0 is routed only to AON/SPE, so 150263944891SThierry Reding * we only have 4 shared interrupts for the CCPLEX. 150363944891SThierry Reding */ 150463944891SThierry Reding interrupt-names = "shared1", "shared2", "shared3", "shared4"; 150563944891SThierry Reding #mbox-cells = <2>; 150663944891SThierry Reding }; 150763944891SThierry Reding 1508156af9deSAkhil R gen2_i2c: i2c@c240000 { 1509156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 15102838cfddSThierry Reding reg = <0x0 0xc240000 0x0 0x100>; 1511156af9deSAkhil R interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1512156af9deSAkhil R status = "disabled"; 1513156af9deSAkhil R clock-frequency = <100000>; 1514156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C2 1515156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 1516156af9deSAkhil R clock-names = "div-clk", "parent"; 1517156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C2>; 1518156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 1519156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C2>; 1520156af9deSAkhil R reset-names = "i2c"; 15218e442805SAkhil R iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 15228e442805SAkhil R dma-coherent; 15238e442805SAkhil R dmas = <&gpcdma 22>, <&gpcdma 22>; 15248e442805SAkhil R dma-names = "rx", "tx"; 1525156af9deSAkhil R }; 1526156af9deSAkhil R 1527156af9deSAkhil R gen8_i2c: i2c@c250000 { 1528156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 15292838cfddSThierry Reding reg = <0x0 0xc250000 0x0 0x100>; 1530156af9deSAkhil R interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1531156af9deSAkhil R status = "disabled"; 1532156af9deSAkhil R clock-frequency = <400000>; 1533156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C8 1534156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 1535156af9deSAkhil R clock-names = "div-clk", "parent"; 1536156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C8>; 1537156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 1538156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C8>; 1539156af9deSAkhil R reset-names = "i2c"; 15408e442805SAkhil R iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 15418e442805SAkhil R dma-coherent; 15428e442805SAkhil R dmas = <&gpcdma 0>, <&gpcdma 0>; 15438e442805SAkhil R dma-names = "rx", "tx"; 1544156af9deSAkhil R }; 1545156af9deSAkhil R 154663944891SThierry Reding rtc@c2a0000 { 154763944891SThierry Reding compatible = "nvidia,tegra234-rtc", "nvidia,tegra20-rtc"; 15482838cfddSThierry Reding reg = <0x0 0x0c2a0000 0x0 0x10000>; 154963944891SThierry Reding interrupt-parent = <&pmc>; 155063944891SThierry Reding interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 1551e537addeSMikko Perttunen clocks = <&bpmp TEGRA234_CLK_CLK_32K>; 1552e537addeSMikko Perttunen clock-names = "rtc"; 155363944891SThierry Reding status = "disabled"; 155463944891SThierry Reding }; 155563944891SThierry Reding 1556f0e12668SThierry Reding gpio_aon: gpio@c2f0000 { 1557f0e12668SThierry Reding compatible = "nvidia,tegra234-gpio-aon"; 1558f0e12668SThierry Reding reg-names = "security", "gpio"; 15592838cfddSThierry Reding reg = <0x0 0x0c2f0000 0x0 0x1000>, 15602838cfddSThierry Reding <0x0 0x0c2f1000 0x0 0x1000>; 1561f0e12668SThierry Reding interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1562f0e12668SThierry Reding <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1563f0e12668SThierry Reding <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1564f0e12668SThierry Reding <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 1565f0e12668SThierry Reding #interrupt-cells = <2>; 1566f0e12668SThierry Reding interrupt-controller; 1567f0e12668SThierry Reding #gpio-cells = <2>; 1568f0e12668SThierry Reding gpio-controller; 1569f0e12668SThierry Reding }; 1570f0e12668SThierry Reding 15712566d28cSJon Hunter pwm4: pwm@c340000 { 15722566d28cSJon Hunter compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 15732838cfddSThierry Reding reg = <0x0 0xc340000 0x0 0x10000>; 15742566d28cSJon Hunter clocks = <&bpmp TEGRA234_CLK_PWM4>; 15752566d28cSJon Hunter resets = <&bpmp TEGRA234_RESET_PWM4>; 15762566d28cSJon Hunter reset-names = "pwm"; 15772566d28cSJon Hunter status = "disabled"; 15782566d28cSJon Hunter #pwm-cells = <2>; 15792566d28cSJon Hunter }; 15802566d28cSJon Hunter 158163944891SThierry Reding pmc: pmc@c360000 { 158263944891SThierry Reding compatible = "nvidia,tegra234-pmc"; 15832838cfddSThierry Reding reg = <0x0 0x0c360000 0x0 0x10000>, 15842838cfddSThierry Reding <0x0 0x0c370000 0x0 0x10000>, 15852838cfddSThierry Reding <0x0 0x0c380000 0x0 0x10000>, 15862838cfddSThierry Reding <0x0 0x0c390000 0x0 0x10000>, 15872838cfddSThierry Reding <0x0 0x0c3a0000 0x0 0x10000>; 158863944891SThierry Reding reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 158963944891SThierry Reding 159063944891SThierry Reding #interrupt-cells = <2>; 159163944891SThierry Reding interrupt-controller; 1592d71b893aSPrathamesh Shete 1593d71b893aSPrathamesh Shete sdmmc1_1v8: sdmmc1-1v8 { 1594d71b893aSPrathamesh Shete pins = "sdmmc1-hv"; 1595d71b893aSPrathamesh Shete power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1596d71b893aSPrathamesh Shete }; 1597d71b893aSPrathamesh Shete 1598*79ed18d9SThierry Reding sdmmc1_3v3: sdmmc1-3v3 { 1599*79ed18d9SThierry Reding pins = "sdmmc1-hv"; 1600d71b893aSPrathamesh Shete power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1601d71b893aSPrathamesh Shete }; 1602d71b893aSPrathamesh Shete 1603d71b893aSPrathamesh Shete sdmmc3_1v8: sdmmc3-1v8 { 1604d71b893aSPrathamesh Shete pins = "sdmmc3-hv"; 1605d71b893aSPrathamesh Shete power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1606d71b893aSPrathamesh Shete }; 1607*79ed18d9SThierry Reding 1608*79ed18d9SThierry Reding sdmmc3_3v3: sdmmc3-3v3 { 1609*79ed18d9SThierry Reding pins = "sdmmc3-hv"; 1610*79ed18d9SThierry Reding power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1611*79ed18d9SThierry Reding }; 161263944891SThierry Reding }; 161363944891SThierry Reding 1614302e1540SSumit Gupta aon-fabric@c600000 { 1615302e1540SSumit Gupta compatible = "nvidia,tegra234-aon-fabric"; 16162838cfddSThierry Reding reg = <0x0 0xc600000 0x0 0x40000>; 1617302e1540SSumit Gupta interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 1618302e1540SSumit Gupta status = "okay"; 1619302e1540SSumit Gupta }; 1620302e1540SSumit Gupta 1621302e1540SSumit Gupta bpmp-fabric@d600000 { 1622302e1540SSumit Gupta compatible = "nvidia,tegra234-bpmp-fabric"; 16232838cfddSThierry Reding reg = <0x0 0xd600000 0x0 0x40000>; 1624302e1540SSumit Gupta interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1625302e1540SSumit Gupta status = "okay"; 1626302e1540SSumit Gupta }; 1627302e1540SSumit Gupta 1628302e1540SSumit Gupta dce-fabric@de00000 { 1629302e1540SSumit Gupta compatible = "nvidia,tegra234-sce-fabric"; 16302838cfddSThierry Reding reg = <0x0 0xde00000 0x0 0x40000>; 1631302e1540SSumit Gupta interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>; 1632302e1540SSumit Gupta status = "okay"; 1633302e1540SSumit Gupta }; 1634302e1540SSumit Gupta 16352838cfddSThierry Reding ccplex@e000000 { 16362838cfddSThierry Reding compatible = "nvidia,tegra234-ccplex-cluster"; 16372838cfddSThierry Reding reg = <0x0 0x0e000000 0x0 0x5ffff>; 16382838cfddSThierry Reding nvidia,bpmp = <&bpmp>; 16392838cfddSThierry Reding status = "okay"; 16402838cfddSThierry Reding }; 16412838cfddSThierry Reding 164263944891SThierry Reding gic: interrupt-controller@f400000 { 164363944891SThierry Reding compatible = "arm,gic-v3"; 16442838cfddSThierry Reding reg = <0x0 0x0f400000 0x0 0x010000>, /* GICD */ 16452838cfddSThierry Reding <0x0 0x0f440000 0x0 0x200000>; /* GICR */ 164663944891SThierry Reding interrupt-parent = <&gic>; 164763944891SThierry Reding interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 164863944891SThierry Reding 164963944891SThierry Reding #redistributor-regions = <1>; 165063944891SThierry Reding #interrupt-cells = <3>; 165163944891SThierry Reding interrupt-controller; 165263944891SThierry Reding }; 16535710e16aSThierry Reding 16545710e16aSThierry Reding smmu_iso: iommu@10000000 { 16555710e16aSThierry Reding compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; 16562838cfddSThierry Reding reg = <0x0 0x10000000 0x0 0x1000000>; 16575710e16aSThierry Reding interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16585710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16595710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16605710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16615710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16625710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16635710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16645710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16655710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16665710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16675710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16685710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16695710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16705710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16715710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16725710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16735710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16745710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16755710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16765710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16775710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16785710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16795710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16805710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16815710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16825710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16835710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16845710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16855710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16865710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16875710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16885710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16895710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16905710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16915710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16925710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16935710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16945710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16955710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16965710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16975710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16985710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16995710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17005710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17015710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17025710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17035710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17045710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17055710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17065710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17075710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17085710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17095710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17105710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17115710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17125710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17135710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17145710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17155710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17165710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17175710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17185710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17195710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17205710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17215710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17225710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17235710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17245710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17255710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17265710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17275710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17285710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17295710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17305710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17315710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17325710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17335710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17345710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17355710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17365710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17375710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17385710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17395710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17405710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17415710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17425710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17435710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17445710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17455710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17465710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17475710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17485710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17495710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17505710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17515710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17525710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17535710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17545710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17555710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17565710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17575710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17585710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17595710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17605710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17615710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17625710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17635710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17645710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17655710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17665710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17675710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17685710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17695710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17705710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17715710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17725710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17735710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17745710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17755710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17765710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17775710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17785710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17795710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17805710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17815710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17825710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17835710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17845710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17855710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 17865710e16aSThierry Reding stream-match-mask = <0x7f80>; 17875710e16aSThierry Reding #global-interrupts = <1>; 17885710e16aSThierry Reding #iommu-cells = <1>; 17895710e16aSThierry Reding 17905710e16aSThierry Reding nvidia,memory-controller = <&mc>; 17915710e16aSThierry Reding status = "okay"; 17925710e16aSThierry Reding }; 17935710e16aSThierry Reding 17945710e16aSThierry Reding smmu_niso0: iommu@12000000 { 17955710e16aSThierry Reding compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; 17962838cfddSThierry Reding reg = <0x0 0x12000000 0x0 0x1000000>, 17972838cfddSThierry Reding <0x0 0x11000000 0x0 0x1000000>; 17985710e16aSThierry Reding interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 17995710e16aSThierry Reding <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 18005710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18015710e16aSThierry Reding <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 18025710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18035710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18045710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18055710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18065710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18075710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18085710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18095710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18105710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18115710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18125710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18135710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18145710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18155710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18165710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18175710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18185710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18195710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18205710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18215710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18225710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18235710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18245710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18255710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18265710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18275710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18285710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18295710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18305710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18315710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18325710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18335710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18345710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18355710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18365710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18375710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18385710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18395710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18405710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18415710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18425710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18435710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18445710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18455710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18465710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18475710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18485710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18495710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18505710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18515710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18525710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18535710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18545710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18555710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18565710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18575710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18585710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18595710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18605710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18615710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18625710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18635710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18645710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18655710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18665710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18675710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18685710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18695710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18705710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18715710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18725710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18735710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18745710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18755710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18765710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18775710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18785710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18795710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18805710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18815710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18825710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18835710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18845710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18855710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18865710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18875710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18885710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18895710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18905710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18915710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18925710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18935710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18945710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18955710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18965710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18975710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18985710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18995710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19005710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19015710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19025710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19035710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19045710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19055710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19065710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19075710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19085710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19095710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19105710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19115710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19125710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19135710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19145710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19155710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19165710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19175710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19185710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19195710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19205710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19215710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19225710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19235710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19245710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19255710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19265710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19275710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 19285710e16aSThierry Reding stream-match-mask = <0x7f80>; 19295710e16aSThierry Reding #global-interrupts = <2>; 19305710e16aSThierry Reding #iommu-cells = <1>; 19315710e16aSThierry Reding 19325710e16aSThierry Reding nvidia,memory-controller = <&mc>; 19335710e16aSThierry Reding status = "okay"; 19345710e16aSThierry Reding }; 1935302e1540SSumit Gupta 1936302e1540SSumit Gupta cbb-fabric@13a00000 { 1937302e1540SSumit Gupta compatible = "nvidia,tegra234-cbb-fabric"; 19382838cfddSThierry Reding reg = <0x0 0x13a00000 0x0 0x400000>; 1939302e1540SSumit Gupta interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 1940302e1540SSumit Gupta status = "okay"; 1941302e1540SSumit Gupta }; 1942962c400dSSumit Gupta 1943*79ed18d9SThierry Reding host1x@13e00000 { 1944*79ed18d9SThierry Reding compatible = "nvidia,tegra234-host1x"; 1945*79ed18d9SThierry Reding reg = <0x0 0x13e00000 0x0 0x10000>, 1946*79ed18d9SThierry Reding <0x0 0x13e10000 0x0 0x10000>, 1947*79ed18d9SThierry Reding <0x0 0x13e40000 0x0 0x10000>; 1948*79ed18d9SThierry Reding reg-names = "common", "hypervisor", "vm"; 1949*79ed18d9SThierry Reding interrupts = <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, 1950*79ed18d9SThierry Reding <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, 1951*79ed18d9SThierry Reding <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, 1952*79ed18d9SThierry Reding <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, 1953*79ed18d9SThierry Reding <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, 1954*79ed18d9SThierry Reding <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>, 1955*79ed18d9SThierry Reding <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>, 1956*79ed18d9SThierry Reding <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>, 1957*79ed18d9SThierry Reding <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 1958*79ed18d9SThierry Reding interrupt-names = "syncpt0", "syncpt1", "syncpt2", "syncpt3", "syncpt4", 1959*79ed18d9SThierry Reding "syncpt5", "syncpt6", "syncpt7", "host1x"; 1960*79ed18d9SThierry Reding clocks = <&bpmp TEGRA234_CLK_HOST1X>; 1961*79ed18d9SThierry Reding clock-names = "host1x"; 1962*79ed18d9SThierry Reding 1963*79ed18d9SThierry Reding #address-cells = <2>; 1964*79ed18d9SThierry Reding #size-cells = <2>; 1965*79ed18d9SThierry Reding ranges = <0x0 0x14800000 0x0 0x14800000 0x0 0x02000000>; 1966*79ed18d9SThierry Reding 1967*79ed18d9SThierry Reding interconnects = <&mc TEGRA234_MEMORY_CLIENT_HOST1XDMAR &emc>; 1968*79ed18d9SThierry Reding interconnect-names = "dma-mem"; 1969*79ed18d9SThierry Reding iommus = <&smmu_niso1 TEGRA234_SID_HOST1X>; 1970*79ed18d9SThierry Reding 1971*79ed18d9SThierry Reding /* Context isolation domains */ 1972*79ed18d9SThierry Reding iommu-map = <0 &smmu_niso0 TEGRA234_SID_HOST1X_CTX0 1>, 1973*79ed18d9SThierry Reding <1 &smmu_niso0 TEGRA234_SID_HOST1X_CTX1 1>, 1974*79ed18d9SThierry Reding <2 &smmu_niso0 TEGRA234_SID_HOST1X_CTX2 1>, 1975*79ed18d9SThierry Reding <3 &smmu_niso0 TEGRA234_SID_HOST1X_CTX3 1>, 1976*79ed18d9SThierry Reding <4 &smmu_niso0 TEGRA234_SID_HOST1X_CTX4 1>, 1977*79ed18d9SThierry Reding <5 &smmu_niso0 TEGRA234_SID_HOST1X_CTX5 1>, 1978*79ed18d9SThierry Reding <6 &smmu_niso0 TEGRA234_SID_HOST1X_CTX6 1>, 1979*79ed18d9SThierry Reding <7 &smmu_niso0 TEGRA234_SID_HOST1X_CTX7 1>, 1980*79ed18d9SThierry Reding <8 &smmu_niso1 TEGRA234_SID_HOST1X_CTX0 1>, 1981*79ed18d9SThierry Reding <9 &smmu_niso1 TEGRA234_SID_HOST1X_CTX1 1>, 1982*79ed18d9SThierry Reding <10 &smmu_niso1 TEGRA234_SID_HOST1X_CTX2 1>, 1983*79ed18d9SThierry Reding <11 &smmu_niso1 TEGRA234_SID_HOST1X_CTX3 1>, 1984*79ed18d9SThierry Reding <12 &smmu_niso1 TEGRA234_SID_HOST1X_CTX4 1>, 1985*79ed18d9SThierry Reding <13 &smmu_niso1 TEGRA234_SID_HOST1X_CTX5 1>, 1986*79ed18d9SThierry Reding <14 &smmu_niso1 TEGRA234_SID_HOST1X_CTX6 1>, 1987*79ed18d9SThierry Reding <15 &smmu_niso1 TEGRA234_SID_HOST1X_CTX7 1>; 1988*79ed18d9SThierry Reding 1989*79ed18d9SThierry Reding vic@15340000 { 1990*79ed18d9SThierry Reding compatible = "nvidia,tegra234-vic"; 1991*79ed18d9SThierry Reding reg = <0x0 0x15340000 0x0 0x00040000>; 1992*79ed18d9SThierry Reding interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1993*79ed18d9SThierry Reding clocks = <&bpmp TEGRA234_CLK_VIC>; 1994*79ed18d9SThierry Reding clock-names = "vic"; 1995*79ed18d9SThierry Reding resets = <&bpmp TEGRA234_RESET_VIC>; 1996*79ed18d9SThierry Reding reset-names = "vic"; 1997*79ed18d9SThierry Reding 1998*79ed18d9SThierry Reding power-domains = <&bpmp TEGRA234_POWER_DOMAIN_VIC>; 1999*79ed18d9SThierry Reding interconnects = <&mc TEGRA234_MEMORY_CLIENT_VICSRD &emc>, 2000*79ed18d9SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_VICSWR &emc>; 2001*79ed18d9SThierry Reding interconnect-names = "dma-mem", "write"; 2002*79ed18d9SThierry Reding iommus = <&smmu_niso1 TEGRA234_SID_VIC>; 2003*79ed18d9SThierry Reding dma-coherent; 2004*79ed18d9SThierry Reding }; 2005*79ed18d9SThierry Reding 2006*79ed18d9SThierry Reding nvdec@15480000 { 2007*79ed18d9SThierry Reding compatible = "nvidia,tegra234-nvdec"; 2008*79ed18d9SThierry Reding reg = <0x0 0x15480000 0x0 0x00040000>; 2009*79ed18d9SThierry Reding clocks = <&bpmp TEGRA234_CLK_NVDEC>, 2010*79ed18d9SThierry Reding <&bpmp TEGRA234_CLK_FUSE>, 2011*79ed18d9SThierry Reding <&bpmp TEGRA234_CLK_TSEC_PKA>; 2012*79ed18d9SThierry Reding clock-names = "nvdec", "fuse", "tsec_pka"; 2013*79ed18d9SThierry Reding resets = <&bpmp TEGRA234_RESET_NVDEC>; 2014*79ed18d9SThierry Reding reset-names = "nvdec"; 2015*79ed18d9SThierry Reding power-domains = <&bpmp TEGRA234_POWER_DOMAIN_NVDEC>; 2016*79ed18d9SThierry Reding interconnects = <&mc TEGRA234_MEMORY_CLIENT_NVDECSRD &emc>, 2017*79ed18d9SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_NVDECSWR &emc>; 2018*79ed18d9SThierry Reding interconnect-names = "dma-mem", "write"; 2019*79ed18d9SThierry Reding iommus = <&smmu_niso1 TEGRA234_SID_NVDEC>; 2020*79ed18d9SThierry Reding dma-coherent; 2021*79ed18d9SThierry Reding 2022*79ed18d9SThierry Reding nvidia,memory-controller = <&mc>; 2023*79ed18d9SThierry Reding 2024*79ed18d9SThierry Reding /* 2025*79ed18d9SThierry Reding * Placeholder values that firmware needs to update with the real 2026*79ed18d9SThierry Reding * offsets parsed from the microcode headers. 2027*79ed18d9SThierry Reding */ 2028*79ed18d9SThierry Reding nvidia,bl-manifest-offset = <0>; 2029*79ed18d9SThierry Reding nvidia,bl-data-offset = <0>; 2030*79ed18d9SThierry Reding nvidia,bl-code-offset = <0>; 2031*79ed18d9SThierry Reding nvidia,os-manifest-offset = <0>; 2032*79ed18d9SThierry Reding nvidia,os-data-offset = <0>; 2033*79ed18d9SThierry Reding nvidia,os-code-offset = <0>; 2034*79ed18d9SThierry Reding 2035*79ed18d9SThierry Reding /* 2036*79ed18d9SThierry Reding * Firmware needs to set this to "okay" once the above values have 2037*79ed18d9SThierry Reding * been updated. 2038*79ed18d9SThierry Reding */ 2039*79ed18d9SThierry Reding status = "disabled"; 2040*79ed18d9SThierry Reding }; 2041*79ed18d9SThierry Reding }; 2042*79ed18d9SThierry Reding 2043ec142c44SVidya Sagar pcie@140a0000 { 2044ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie"; 2045ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CA>; 2046ec142c44SVidya Sagar reg = <0x00 0x140a0000 0x0 0x00020000>, /* appl registers (128K) */ 2047ec142c44SVidya Sagar <0x00 0x2a000000 0x0 0x00040000>, /* configuration space (256K) */ 2048ec142c44SVidya Sagar <0x00 0x2a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2049794b834dSVidya Sagar <0x00 0x2a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2050794b834dSVidya Sagar <0x35 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2051794b834dSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2052ec142c44SVidya Sagar 2053ec142c44SVidya Sagar #address-cells = <3>; 2054ec142c44SVidya Sagar #size-cells = <2>; 2055ec142c44SVidya Sagar device_type = "pci"; 2056ec142c44SVidya Sagar num-lanes = <4>; 2057ec142c44SVidya Sagar num-viewport = <8>; 2058ec142c44SVidya Sagar linux,pci-domain = <8>; 2059ec142c44SVidya Sagar 2060ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX2_C8_CORE>; 2061ec142c44SVidya Sagar clock-names = "core"; 2062ec142c44SVidya Sagar 2063ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX2_CORE_8_APB>, 2064ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX2_CORE_8>; 2065ec142c44SVidya Sagar reset-names = "apb", "core"; 2066ec142c44SVidya Sagar 2067ec142c44SVidya Sagar interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2068ec142c44SVidya Sagar <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2069ec142c44SVidya Sagar interrupt-names = "intr", "msi"; 2070ec142c44SVidya Sagar 2071ec142c44SVidya Sagar #interrupt-cells = <1>; 2072ec142c44SVidya Sagar interrupt-map-mask = <0 0 0 0>; 2073ec142c44SVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 2074ec142c44SVidya Sagar 2075ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 8>; 2076ec142c44SVidya Sagar 2077ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2078ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2079ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2080ec142c44SVidya Sagar 2081ec142c44SVidya Sagar bus-range = <0x0 0xff>; 2082ec142c44SVidya Sagar 2083ec142c44SVidya Sagar ranges = <0x43000000 0x32 0x40000000 0x32 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2084ec142c44SVidya Sagar <0x02000000 0x0 0x40000000 0x35 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2085ec142c44SVidya Sagar <0x01000000 0x0 0x2a100000 0x00 0x2a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2086ec142c44SVidya Sagar 2087ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE8AR &emc>, 2088ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE8AW &emc>; 2089ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2090ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE8 0x1000>; 2091ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2092ec142c44SVidya Sagar dma-coherent; 2093ec142c44SVidya Sagar 2094ec142c44SVidya Sagar status = "disabled"; 2095ec142c44SVidya Sagar }; 2096ec142c44SVidya Sagar 2097ec142c44SVidya Sagar pcie@140c0000 { 2098ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie"; 2099ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CB>; 2100ec142c44SVidya Sagar reg = <0x00 0x140c0000 0x0 0x00020000>, /* appl registers (128K) */ 2101ec142c44SVidya Sagar <0x00 0x2c000000 0x0 0x00040000>, /* configuration space (256K) */ 2102ec142c44SVidya Sagar <0x00 0x2c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2103794b834dSVidya Sagar <0x00 0x2c080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2104794b834dSVidya Sagar <0x38 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2105794b834dSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2106ec142c44SVidya Sagar 2107ec142c44SVidya Sagar #address-cells = <3>; 2108ec142c44SVidya Sagar #size-cells = <2>; 2109ec142c44SVidya Sagar device_type = "pci"; 2110ec142c44SVidya Sagar num-lanes = <4>; 2111ec142c44SVidya Sagar num-viewport = <8>; 2112ec142c44SVidya Sagar linux,pci-domain = <9>; 2113ec142c44SVidya Sagar 2114ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX2_C9_CORE>; 2115ec142c44SVidya Sagar clock-names = "core"; 2116ec142c44SVidya Sagar 2117ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX2_CORE_9_APB>, 2118ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX2_CORE_9>; 2119ec142c44SVidya Sagar reset-names = "apb", "core"; 2120ec142c44SVidya Sagar 2121ec142c44SVidya Sagar interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2122ec142c44SVidya Sagar <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2123ec142c44SVidya Sagar interrupt-names = "intr", "msi"; 2124ec142c44SVidya Sagar 2125ec142c44SVidya Sagar #interrupt-cells = <1>; 2126ec142c44SVidya Sagar interrupt-map-mask = <0 0 0 0>; 2127ec142c44SVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2128ec142c44SVidya Sagar 2129ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 9>; 2130ec142c44SVidya Sagar 2131ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2132ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2133ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2134ec142c44SVidya Sagar 2135ec142c44SVidya Sagar bus-range = <0x0 0xff>; 2136ec142c44SVidya Sagar 213724840065SVidya Sagar ranges = <0x43000000 0x35 0x40000000 0x35 0x40000000 0x2 0xc0000000>, /* prefetchable memory (11264 MB) */ 2138ec142c44SVidya Sagar <0x02000000 0x0 0x40000000 0x38 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2139ec142c44SVidya Sagar <0x01000000 0x0 0x2c100000 0x00 0x2c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2140ec142c44SVidya Sagar 2141ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE9AR &emc>, 2142ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE9AW &emc>; 2143ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2144ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE9 0x1000>; 2145ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2146ec142c44SVidya Sagar dma-coherent; 2147ec142c44SVidya Sagar 2148ec142c44SVidya Sagar status = "disabled"; 2149ec142c44SVidya Sagar }; 2150ec142c44SVidya Sagar 2151ec142c44SVidya Sagar pcie@140e0000 { 2152ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie"; 2153ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CC>; 2154ec142c44SVidya Sagar reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K) */ 2155ec142c44SVidya Sagar <0x00 0x2e000000 0x0 0x00040000>, /* configuration space (256K) */ 2156ec142c44SVidya Sagar <0x00 0x2e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2157794b834dSVidya Sagar <0x00 0x2e080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2158794b834dSVidya Sagar <0x3b 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2159794b834dSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2160ec142c44SVidya Sagar 2161ec142c44SVidya Sagar #address-cells = <3>; 2162ec142c44SVidya Sagar #size-cells = <2>; 2163ec142c44SVidya Sagar device_type = "pci"; 2164ec142c44SVidya Sagar num-lanes = <4>; 2165ec142c44SVidya Sagar num-viewport = <8>; 2166ec142c44SVidya Sagar linux,pci-domain = <10>; 2167ec142c44SVidya Sagar 2168ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX2_C10_CORE>; 2169ec142c44SVidya Sagar clock-names = "core"; 2170ec142c44SVidya Sagar 2171ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX2_CORE_10_APB>, 2172ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX2_CORE_10>; 2173ec142c44SVidya Sagar reset-names = "apb", "core"; 2174ec142c44SVidya Sagar 2175ec142c44SVidya Sagar interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2176ec142c44SVidya Sagar <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2177ec142c44SVidya Sagar interrupt-names = "intr", "msi"; 2178ec142c44SVidya Sagar 2179ec142c44SVidya Sagar #interrupt-cells = <1>; 2180ec142c44SVidya Sagar interrupt-map-mask = <0 0 0 0>; 2181ec142c44SVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 2182ec142c44SVidya Sagar 2183ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 10>; 2184ec142c44SVidya Sagar 2185ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2186ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2187ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2188ec142c44SVidya Sagar 2189ec142c44SVidya Sagar bus-range = <0x0 0xff>; 2190ec142c44SVidya Sagar 2191ec142c44SVidya Sagar ranges = <0x43000000 0x38 0x40000000 0x38 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2192ec142c44SVidya Sagar <0x02000000 0x0 0x40000000 0x3b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2193ec142c44SVidya Sagar <0x01000000 0x0 0x2e100000 0x00 0x2e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2194ec142c44SVidya Sagar 2195ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE10AR &emc>, 2196ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE10AW &emc>; 2197ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2198ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>; 2199ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2200ec142c44SVidya Sagar dma-coherent; 2201ec142c44SVidya Sagar 2202ec142c44SVidya Sagar status = "disabled"; 2203ec142c44SVidya Sagar }; 2204ec142c44SVidya Sagar 22052838cfddSThierry Reding pcie-ep@140e0000 { 22062838cfddSThierry Reding compatible = "nvidia,tegra234-pcie-ep"; 22072838cfddSThierry Reding power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CC>; 22082838cfddSThierry Reding reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K) */ 22092838cfddSThierry Reding <0x00 0x2e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 22102838cfddSThierry Reding <0x00 0x2e080000 0x0 0x00040000>, /* DBI space (256K) */ 22112838cfddSThierry Reding <0x38 0x40000000 0x3 0x00000000>; /* Address Space (12G) */ 22122838cfddSThierry Reding reg-names = "appl", "atu_dma", "dbi", "addr_space"; 22132838cfddSThierry Reding 22142838cfddSThierry Reding num-lanes = <4>; 22152838cfddSThierry Reding 22162838cfddSThierry Reding clocks = <&bpmp TEGRA234_CLK_PEX2_C10_CORE>; 22172838cfddSThierry Reding clock-names = "core"; 22182838cfddSThierry Reding 22192838cfddSThierry Reding resets = <&bpmp TEGRA234_RESET_PEX2_CORE_10_APB>, 22202838cfddSThierry Reding <&bpmp TEGRA234_RESET_PEX2_CORE_10>; 22212838cfddSThierry Reding reset-names = "apb", "core"; 22222838cfddSThierry Reding 22232838cfddSThierry Reding interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 22242838cfddSThierry Reding interrupt-names = "intr"; 22252838cfddSThierry Reding 22262838cfddSThierry Reding nvidia,bpmp = <&bpmp 10>; 22272838cfddSThierry Reding 22282838cfddSThierry Reding nvidia,enable-ext-refclk; 22292838cfddSThierry Reding nvidia,aspm-cmrt-us = <60>; 22302838cfddSThierry Reding nvidia,aspm-pwr-on-t-us = <20>; 22312838cfddSThierry Reding nvidia,aspm-l0s-entrance-latency-us = <3>; 22322838cfddSThierry Reding 22332838cfddSThierry Reding interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE10AR &emc>, 22342838cfddSThierry Reding <&mc TEGRA234_MEMORY_CLIENT_PCIE10AW &emc>; 22352838cfddSThierry Reding interconnect-names = "dma-mem", "write"; 22362838cfddSThierry Reding iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>; 22372838cfddSThierry Reding iommu-map-mask = <0x0>; 22382838cfddSThierry Reding dma-coherent; 22392838cfddSThierry Reding 22402838cfddSThierry Reding status = "disabled"; 22412838cfddSThierry Reding }; 22422838cfddSThierry Reding 2243ec142c44SVidya Sagar pcie@14100000 { 2244ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie"; 2245ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>; 2246ec142c44SVidya Sagar reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */ 2247ec142c44SVidya Sagar <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */ 2248ec142c44SVidya Sagar <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2249794b834dSVidya Sagar <0x00 0x30080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2250794b834dSVidya Sagar <0x20 0xb0000000 0x0 0x10000000>; /* ECAM (256MB) */ 2251794b834dSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2252ec142c44SVidya Sagar 2253ec142c44SVidya Sagar #address-cells = <3>; 2254ec142c44SVidya Sagar #size-cells = <2>; 2255ec142c44SVidya Sagar device_type = "pci"; 2256ec142c44SVidya Sagar num-lanes = <1>; 2257ec142c44SVidya Sagar num-viewport = <8>; 2258ec142c44SVidya Sagar linux,pci-domain = <1>; 2259ec142c44SVidya Sagar 2260ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX0_C1_CORE>; 2261ec142c44SVidya Sagar clock-names = "core"; 2262ec142c44SVidya Sagar 2263ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX0_CORE_1_APB>, 2264ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX0_CORE_1>; 2265ec142c44SVidya Sagar reset-names = "apb", "core"; 2266ec142c44SVidya Sagar 2267ec142c44SVidya Sagar interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2268ec142c44SVidya Sagar <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2269ec142c44SVidya Sagar interrupt-names = "intr", "msi"; 2270ec142c44SVidya Sagar 2271ec142c44SVidya Sagar #interrupt-cells = <1>; 2272ec142c44SVidya Sagar interrupt-map-mask = <0 0 0 0>; 2273ec142c44SVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 2274ec142c44SVidya Sagar 2275ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 1>; 2276ec142c44SVidya Sagar 2277ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2278ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2279ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2280ec142c44SVidya Sagar 2281ec142c44SVidya Sagar bus-range = <0x0 0xff>; 2282ec142c44SVidya Sagar 2283ec142c44SVidya Sagar ranges = <0x43000000 0x20 0x80000000 0x20 0x80000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ 2284ec142c44SVidya Sagar <0x02000000 0x0 0x40000000 0x20 0xa8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2285ec142c44SVidya Sagar <0x01000000 0x0 0x30100000 0x00 0x30100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2286ec142c44SVidya Sagar 2287ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE1R &emc>, 2288ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE1W &emc>; 2289ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2290ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE1 0x1000>; 2291ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2292ec142c44SVidya Sagar dma-coherent; 2293ec142c44SVidya Sagar 2294ec142c44SVidya Sagar status = "disabled"; 2295ec142c44SVidya Sagar }; 2296ec142c44SVidya Sagar 2297ec142c44SVidya Sagar pcie@14120000 { 2298ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie"; 2299ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>; 2300ec142c44SVidya Sagar reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */ 2301ec142c44SVidya Sagar <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */ 2302ec142c44SVidya Sagar <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2303794b834dSVidya Sagar <0x00 0x32080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2304794b834dSVidya Sagar <0x20 0xf0000000 0x0 0x10000000>; /* ECAM (256MB) */ 2305794b834dSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2306ec142c44SVidya Sagar 2307ec142c44SVidya Sagar #address-cells = <3>; 2308ec142c44SVidya Sagar #size-cells = <2>; 2309ec142c44SVidya Sagar device_type = "pci"; 2310ec142c44SVidya Sagar num-lanes = <1>; 2311ec142c44SVidya Sagar num-viewport = <8>; 2312ec142c44SVidya Sagar linux,pci-domain = <2>; 2313ec142c44SVidya Sagar 2314ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX0_C2_CORE>; 2315ec142c44SVidya Sagar clock-names = "core"; 2316ec142c44SVidya Sagar 2317ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX0_CORE_2_APB>, 2318ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX0_CORE_2>; 2319ec142c44SVidya Sagar reset-names = "apb", "core"; 2320ec142c44SVidya Sagar 2321ec142c44SVidya Sagar interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2322ec142c44SVidya Sagar <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2323ec142c44SVidya Sagar interrupt-names = "intr", "msi"; 2324ec142c44SVidya Sagar 2325ec142c44SVidya Sagar #interrupt-cells = <1>; 2326ec142c44SVidya Sagar interrupt-map-mask = <0 0 0 0>; 2327ec142c44SVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 2328ec142c44SVidya Sagar 2329ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 2>; 2330ec142c44SVidya Sagar 2331ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2332ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2333ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2334ec142c44SVidya Sagar 2335ec142c44SVidya Sagar bus-range = <0x0 0xff>; 2336ec142c44SVidya Sagar 2337ec142c44SVidya Sagar ranges = <0x43000000 0x20 0xc0000000 0x20 0xc0000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ 2338ec142c44SVidya Sagar <0x02000000 0x0 0x40000000 0x20 0xe8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2339ec142c44SVidya Sagar <0x01000000 0x0 0x32100000 0x00 0x32100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2340ec142c44SVidya Sagar 2341ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE2AR &emc>, 2342ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE2AW &emc>; 2343ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2344ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE2 0x1000>; 2345ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2346ec142c44SVidya Sagar dma-coherent; 2347ec142c44SVidya Sagar 2348ec142c44SVidya Sagar status = "disabled"; 2349ec142c44SVidya Sagar }; 2350ec142c44SVidya Sagar 2351ec142c44SVidya Sagar pcie@14140000 { 2352ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie"; 2353ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>; 2354ec142c44SVidya Sagar reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */ 2355ec142c44SVidya Sagar <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */ 2356ec142c44SVidya Sagar <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2357794b834dSVidya Sagar <0x00 0x34080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2358794b834dSVidya Sagar <0x21 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2359794b834dSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2360ec142c44SVidya Sagar 2361ec142c44SVidya Sagar #address-cells = <3>; 2362ec142c44SVidya Sagar #size-cells = <2>; 2363ec142c44SVidya Sagar device_type = "pci"; 2364ec142c44SVidya Sagar num-lanes = <1>; 2365ec142c44SVidya Sagar num-viewport = <8>; 2366ec142c44SVidya Sagar linux,pci-domain = <3>; 2367ec142c44SVidya Sagar 2368ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX0_C3_CORE>; 2369ec142c44SVidya Sagar clock-names = "core"; 2370ec142c44SVidya Sagar 2371ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX0_CORE_3_APB>, 2372ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX0_CORE_3>; 2373ec142c44SVidya Sagar reset-names = "apb", "core"; 2374ec142c44SVidya Sagar 2375ec142c44SVidya Sagar interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2376ec142c44SVidya Sagar <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2377ec142c44SVidya Sagar interrupt-names = "intr", "msi"; 2378ec142c44SVidya Sagar 2379ec142c44SVidya Sagar #interrupt-cells = <1>; 2380ec142c44SVidya Sagar interrupt-map-mask = <0 0 0 0>; 2381ec142c44SVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 2382ec142c44SVidya Sagar 2383ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 3>; 2384ec142c44SVidya Sagar 2385ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2386ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2387ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2388ec142c44SVidya Sagar 2389ec142c44SVidya Sagar bus-range = <0x0 0xff>; 2390ec142c44SVidya Sagar 2391ec142c44SVidya Sagar ranges = <0x43000000 0x21 0x00000000 0x21 0x00000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ 239247a2f35dSVidya Sagar <0x02000000 0x0 0x40000000 0x21 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2393ec142c44SVidya Sagar <0x01000000 0x0 0x34100000 0x00 0x34100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2394ec142c44SVidya Sagar 2395ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE3R &emc>, 2396ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE3W &emc>; 2397ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2398ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE3 0x1000>; 2399ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2400ec142c44SVidya Sagar dma-coherent; 2401ec142c44SVidya Sagar 2402ec142c44SVidya Sagar status = "disabled"; 2403ec142c44SVidya Sagar }; 2404ec142c44SVidya Sagar 2405ec142c44SVidya Sagar pcie@14160000 { 2406ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie"; 2407ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BB>; 2408ec142c44SVidya Sagar reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2409ec142c44SVidya Sagar <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ 2410ec142c44SVidya Sagar <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2411794b834dSVidya Sagar <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2412794b834dSVidya Sagar <0x24 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2413794b834dSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2414ec142c44SVidya Sagar 2415ec142c44SVidya Sagar #address-cells = <3>; 2416ec142c44SVidya Sagar #size-cells = <2>; 2417ec142c44SVidya Sagar device_type = "pci"; 2418ec142c44SVidya Sagar num-lanes = <4>; 2419ec142c44SVidya Sagar num-viewport = <8>; 2420ec142c44SVidya Sagar linux,pci-domain = <4>; 2421ec142c44SVidya Sagar 2422ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX0_C4_CORE>; 2423ec142c44SVidya Sagar clock-names = "core"; 2424ec142c44SVidya Sagar 2425ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX0_CORE_4_APB>, 2426ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX0_CORE_4>; 2427ec142c44SVidya Sagar reset-names = "apb", "core"; 2428ec142c44SVidya Sagar 2429ec142c44SVidya Sagar interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2430ec142c44SVidya Sagar <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2431ec142c44SVidya Sagar interrupt-names = "intr", "msi"; 2432ec142c44SVidya Sagar 2433ec142c44SVidya Sagar #interrupt-cells = <1>; 2434ec142c44SVidya Sagar interrupt-map-mask = <0 0 0 0>; 2435ec142c44SVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 2436ec142c44SVidya Sagar 2437ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 4>; 2438ec142c44SVidya Sagar 2439ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2440ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2441ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2442ec142c44SVidya Sagar 2443ec142c44SVidya Sagar bus-range = <0x0 0xff>; 2444ec142c44SVidya Sagar 2445ec142c44SVidya Sagar ranges = <0x43000000 0x21 0x40000000 0x21 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2446ec142c44SVidya Sagar <0x02000000 0x0 0x40000000 0x24 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2447ec142c44SVidya Sagar <0x01000000 0x0 0x36100000 0x00 0x36100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2448ec142c44SVidya Sagar 2449ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE4R &emc>, 2450ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE4W &emc>; 2451ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2452ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE4 0x1000>; 2453ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2454ec142c44SVidya Sagar dma-coherent; 2455ec142c44SVidya Sagar 2456ec142c44SVidya Sagar status = "disabled"; 2457ec142c44SVidya Sagar }; 2458ec142c44SVidya Sagar 2459ec142c44SVidya Sagar pcie@14180000 { 2460ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie"; 2461ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BA>; 2462ec142c44SVidya Sagar reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2463ec142c44SVidya Sagar <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ 2464ec142c44SVidya Sagar <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2465794b834dSVidya Sagar <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2466794b834dSVidya Sagar <0x27 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2467794b834dSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2468ec142c44SVidya Sagar 2469ec142c44SVidya Sagar #address-cells = <3>; 2470ec142c44SVidya Sagar #size-cells = <2>; 2471ec142c44SVidya Sagar device_type = "pci"; 2472ec142c44SVidya Sagar num-lanes = <4>; 2473ec142c44SVidya Sagar num-viewport = <8>; 2474ec142c44SVidya Sagar linux,pci-domain = <0>; 2475ec142c44SVidya Sagar 2476ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX0_C0_CORE>; 2477ec142c44SVidya Sagar clock-names = "core"; 2478ec142c44SVidya Sagar 2479ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX0_CORE_0_APB>, 2480ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX0_CORE_0>; 2481ec142c44SVidya Sagar reset-names = "apb", "core"; 2482ec142c44SVidya Sagar 2483ec142c44SVidya Sagar interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2484ec142c44SVidya Sagar <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2485ec142c44SVidya Sagar interrupt-names = "intr", "msi"; 2486ec142c44SVidya Sagar 2487ec142c44SVidya Sagar #interrupt-cells = <1>; 2488ec142c44SVidya Sagar interrupt-map-mask = <0 0 0 0>; 2489ec142c44SVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 2490ec142c44SVidya Sagar 2491ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 0>; 2492ec142c44SVidya Sagar 2493ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2494ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2495ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2496ec142c44SVidya Sagar 2497ec142c44SVidya Sagar bus-range = <0x0 0xff>; 2498ec142c44SVidya Sagar 2499ec142c44SVidya Sagar ranges = <0x43000000 0x24 0x40000000 0x24 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2500ec142c44SVidya Sagar <0x02000000 0x0 0x40000000 0x27 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2501ec142c44SVidya Sagar <0x01000000 0x0 0x38100000 0x00 0x38100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2502ec142c44SVidya Sagar 2503ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE0R &emc>, 2504ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE0W &emc>; 2505ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2506ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE0 0x1000>; 2507ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2508ec142c44SVidya Sagar dma-coherent; 2509ec142c44SVidya Sagar 2510ec142c44SVidya Sagar status = "disabled"; 2511ec142c44SVidya Sagar }; 2512ec142c44SVidya Sagar 2513ec142c44SVidya Sagar pcie@141a0000 { 2514ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie"; 2515ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>; 2516ec142c44SVidya Sagar reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2517ec142c44SVidya Sagar <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */ 2518ec142c44SVidya Sagar <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2519794b834dSVidya Sagar <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2520794b834dSVidya Sagar <0x2b 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2521794b834dSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2522ec142c44SVidya Sagar 2523ec142c44SVidya Sagar #address-cells = <3>; 2524ec142c44SVidya Sagar #size-cells = <2>; 2525ec142c44SVidya Sagar device_type = "pci"; 2526ec142c44SVidya Sagar num-lanes = <8>; 2527ec142c44SVidya Sagar num-viewport = <8>; 2528ec142c44SVidya Sagar linux,pci-domain = <5>; 2529ec142c44SVidya Sagar 2530ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>; 2531ec142c44SVidya Sagar clock-names = "core"; 2532ec142c44SVidya Sagar 2533ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>, 2534ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX1_CORE_5>; 2535ec142c44SVidya Sagar reset-names = "apb", "core"; 2536ec142c44SVidya Sagar 2537ec142c44SVidya Sagar interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2538ec142c44SVidya Sagar <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2539ec142c44SVidya Sagar interrupt-names = "intr", "msi"; 2540ec142c44SVidya Sagar 2541ec142c44SVidya Sagar #interrupt-cells = <1>; 2542ec142c44SVidya Sagar interrupt-map-mask = <0 0 0 0>; 2543ec142c44SVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 2544ec142c44SVidya Sagar 2545ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 5>; 2546ec142c44SVidya Sagar 2547ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2548ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2549ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2550ec142c44SVidya Sagar 2551ec142c44SVidya Sagar bus-range = <0x0 0xff>; 2552ec142c44SVidya Sagar 255324840065SVidya Sagar ranges = <0x43000000 0x28 0x00000000 0x28 0x00000000 0x3 0x28000000>, /* prefetchable memory (12928 MB) */ 2554ec142c44SVidya Sagar <0x02000000 0x0 0x40000000 0x2b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2555ec142c44SVidya Sagar <0x01000000 0x0 0x3a100000 0x00 0x3a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2556ec142c44SVidya Sagar 2557ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE5R &emc>, 2558ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE5W &emc>; 2559ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2560ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>; 2561ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2562ec142c44SVidya Sagar dma-coherent; 2563ec142c44SVidya Sagar 2564ec142c44SVidya Sagar status = "disabled"; 2565ec142c44SVidya Sagar }; 2566ec142c44SVidya Sagar 25672838cfddSThierry Reding pcie-ep@141a0000 { 25682838cfddSThierry Reding compatible = "nvidia,tegra234-pcie-ep"; 25692838cfddSThierry Reding power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>; 25702838cfddSThierry Reding reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 25712838cfddSThierry Reding <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 25722838cfddSThierry Reding <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 25732838cfddSThierry Reding <0x27 0x40000000 0x4 0x00000000>; /* Address Space (16G) */ 25742838cfddSThierry Reding reg-names = "appl", "atu_dma", "dbi", "addr_space"; 25752838cfddSThierry Reding 25762838cfddSThierry Reding num-lanes = <8>; 25772838cfddSThierry Reding 25782838cfddSThierry Reding clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>; 25792838cfddSThierry Reding clock-names = "core"; 25802838cfddSThierry Reding 25812838cfddSThierry Reding resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>, 25822838cfddSThierry Reding <&bpmp TEGRA234_RESET_PEX1_CORE_5>; 25832838cfddSThierry Reding reset-names = "apb", "core"; 25842838cfddSThierry Reding 25852838cfddSThierry Reding interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 25862838cfddSThierry Reding interrupt-names = "intr"; 25872838cfddSThierry Reding 25882838cfddSThierry Reding nvidia,bpmp = <&bpmp 5>; 25892838cfddSThierry Reding 25902838cfddSThierry Reding nvidia,enable-ext-refclk; 25912838cfddSThierry Reding nvidia,aspm-cmrt-us = <60>; 25922838cfddSThierry Reding nvidia,aspm-pwr-on-t-us = <20>; 25932838cfddSThierry Reding nvidia,aspm-l0s-entrance-latency-us = <3>; 25942838cfddSThierry Reding 25952838cfddSThierry Reding interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE5R &emc>, 25962838cfddSThierry Reding <&mc TEGRA234_MEMORY_CLIENT_PCIE5W &emc>; 25972838cfddSThierry Reding interconnect-names = "dma-mem", "write"; 25982838cfddSThierry Reding iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>; 25992838cfddSThierry Reding iommu-map-mask = <0x0>; 26002838cfddSThierry Reding dma-coherent; 26012838cfddSThierry Reding 26022838cfddSThierry Reding status = "disabled"; 26032838cfddSThierry Reding }; 26042838cfddSThierry Reding 2605ec142c44SVidya Sagar pcie@141c0000 { 2606ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie"; 2607ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4A>; 2608ec142c44SVidya Sagar reg = <0x00 0x141c0000 0x0 0x00020000>, /* appl registers (128K) */ 2609ec142c44SVidya Sagar <0x00 0x3c000000 0x0 0x00040000>, /* configuration space (256K) */ 2610ec142c44SVidya Sagar <0x00 0x3c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2611794b834dSVidya Sagar <0x00 0x3c080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2612794b834dSVidya Sagar <0x2e 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2613794b834dSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2614ec142c44SVidya Sagar 2615ec142c44SVidya Sagar #address-cells = <3>; 2616ec142c44SVidya Sagar #size-cells = <2>; 2617ec142c44SVidya Sagar device_type = "pci"; 2618ec142c44SVidya Sagar num-lanes = <4>; 2619ec142c44SVidya Sagar num-viewport = <8>; 2620ec142c44SVidya Sagar linux,pci-domain = <6>; 2621ec142c44SVidya Sagar 2622ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX1_C6_CORE>; 2623ec142c44SVidya Sagar clock-names = "core"; 2624ec142c44SVidya Sagar 2625ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX1_CORE_6_APB>, 2626ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX1_CORE_6>; 2627ec142c44SVidya Sagar reset-names = "apb", "core"; 2628ec142c44SVidya Sagar 2629ec142c44SVidya Sagar interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2630ec142c44SVidya Sagar <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2631ec142c44SVidya Sagar interrupt-names = "intr", "msi"; 2632ec142c44SVidya Sagar 2633ec142c44SVidya Sagar #interrupt-cells = <1>; 2634ec142c44SVidya Sagar interrupt-map-mask = <0 0 0 0>; 2635ec142c44SVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 2636ec142c44SVidya Sagar 2637ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 6>; 2638ec142c44SVidya Sagar 2639ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2640ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2641ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2642ec142c44SVidya Sagar 2643ec142c44SVidya Sagar bus-range = <0x0 0xff>; 2644ec142c44SVidya Sagar 2645ec142c44SVidya Sagar ranges = <0x43000000 0x2b 0x40000000 0x2b 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2646ec142c44SVidya Sagar <0x02000000 0x0 0x40000000 0x2e 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2647ec142c44SVidya Sagar <0x01000000 0x0 0x3c100000 0x00 0x3c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2648ec142c44SVidya Sagar 2649ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE6AR &emc>, 2650ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE6AW &emc>; 2651ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2652ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>; 2653ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2654ec142c44SVidya Sagar dma-coherent; 2655ec142c44SVidya Sagar 2656ec142c44SVidya Sagar status = "disabled"; 2657ec142c44SVidya Sagar }; 2658ec142c44SVidya Sagar 26592838cfddSThierry Reding pcie-ep@141c0000 { 26602838cfddSThierry Reding compatible = "nvidia,tegra234-pcie-ep"; 26612838cfddSThierry Reding power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4A>; 26622838cfddSThierry Reding reg = <0x00 0x141c0000 0x0 0x00020000>, /* appl registers (128K) */ 26632838cfddSThierry Reding <0x00 0x3c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 26642838cfddSThierry Reding <0x00 0x3c080000 0x0 0x00040000>, /* DBI space (256K) */ 26652838cfddSThierry Reding <0x2b 0x40000000 0x3 0x00000000>; /* Address Space (12G) */ 26662838cfddSThierry Reding reg-names = "appl", "atu_dma", "dbi", "addr_space"; 26672838cfddSThierry Reding 26682838cfddSThierry Reding num-lanes = <4>; 26692838cfddSThierry Reding 26702838cfddSThierry Reding clocks = <&bpmp TEGRA234_CLK_PEX1_C6_CORE>; 26712838cfddSThierry Reding clock-names = "core"; 26722838cfddSThierry Reding 26732838cfddSThierry Reding resets = <&bpmp TEGRA234_RESET_PEX1_CORE_6_APB>, 26742838cfddSThierry Reding <&bpmp TEGRA234_RESET_PEX1_CORE_6>; 26752838cfddSThierry Reding reset-names = "apb", "core"; 26762838cfddSThierry Reding 26772838cfddSThierry Reding interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 26782838cfddSThierry Reding interrupt-names = "intr"; 26792838cfddSThierry Reding 26802838cfddSThierry Reding nvidia,bpmp = <&bpmp 6>; 26812838cfddSThierry Reding 26822838cfddSThierry Reding nvidia,enable-ext-refclk; 26832838cfddSThierry Reding nvidia,aspm-cmrt-us = <60>; 26842838cfddSThierry Reding nvidia,aspm-pwr-on-t-us = <20>; 26852838cfddSThierry Reding nvidia,aspm-l0s-entrance-latency-us = <3>; 26862838cfddSThierry Reding 26872838cfddSThierry Reding interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE6AR &emc>, 26882838cfddSThierry Reding <&mc TEGRA234_MEMORY_CLIENT_PCIE6AW &emc>; 26892838cfddSThierry Reding interconnect-names = "dma-mem", "write"; 26902838cfddSThierry Reding iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>; 26912838cfddSThierry Reding iommu-map-mask = <0x0>; 26922838cfddSThierry Reding dma-coherent; 26932838cfddSThierry Reding 26942838cfddSThierry Reding status = "disabled"; 26952838cfddSThierry Reding }; 26962838cfddSThierry Reding 2697ec142c44SVidya Sagar pcie@141e0000 { 2698ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie"; 2699ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8B>; 2700ec142c44SVidya Sagar reg = <0x00 0x141e0000 0x0 0x00020000>, /* appl registers (128K) */ 2701ec142c44SVidya Sagar <0x00 0x3e000000 0x0 0x00040000>, /* configuration space (256K) */ 2702ec142c44SVidya Sagar <0x00 0x3e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2703794b834dSVidya Sagar <0x00 0x3e080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2704794b834dSVidya Sagar <0x32 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2705794b834dSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2706ec142c44SVidya Sagar 2707ec142c44SVidya Sagar #address-cells = <3>; 2708ec142c44SVidya Sagar #size-cells = <2>; 2709ec142c44SVidya Sagar device_type = "pci"; 2710ec142c44SVidya Sagar num-lanes = <8>; 2711ec142c44SVidya Sagar num-viewport = <8>; 2712ec142c44SVidya Sagar linux,pci-domain = <7>; 2713ec142c44SVidya Sagar 2714ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX2_C7_CORE>; 2715ec142c44SVidya Sagar clock-names = "core"; 2716ec142c44SVidya Sagar 2717ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX2_CORE_7_APB>, 2718ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX2_CORE_7>; 2719ec142c44SVidya Sagar reset-names = "apb", "core"; 2720ec142c44SVidya Sagar 2721ec142c44SVidya Sagar interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2722ec142c44SVidya Sagar <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2723ec142c44SVidya Sagar interrupt-names = "intr", "msi"; 2724ec142c44SVidya Sagar 2725ec142c44SVidya Sagar #interrupt-cells = <1>; 2726ec142c44SVidya Sagar interrupt-map-mask = <0 0 0 0>; 2727ec142c44SVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 2728ec142c44SVidya Sagar 2729ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 7>; 2730ec142c44SVidya Sagar 2731ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2732ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2733ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2734ec142c44SVidya Sagar 2735ec142c44SVidya Sagar bus-range = <0x0 0xff>; 2736ec142c44SVidya Sagar 273724840065SVidya Sagar ranges = <0x43000000 0x30 0x00000000 0x30 0x00000000 0x2 0x28000000>, /* prefetchable memory (8832 MB) */ 2738ec142c44SVidya Sagar <0x02000000 0x0 0x40000000 0x32 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2739ec142c44SVidya Sagar <0x01000000 0x0 0x3e100000 0x00 0x3e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2740ec142c44SVidya Sagar 2741ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE7AR &emc>, 2742ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE7AW &emc>; 2743ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2744ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>; 2745ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2746ec142c44SVidya Sagar dma-coherent; 2747ec142c44SVidya Sagar 2748ec142c44SVidya Sagar status = "disabled"; 2749ec142c44SVidya Sagar }; 2750ec142c44SVidya Sagar 2751ec142c44SVidya Sagar pcie-ep@141e0000 { 2752ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie-ep"; 2753ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8B>; 2754ec142c44SVidya Sagar reg = <0x00 0x141e0000 0x0 0x00020000>, /* appl registers (128K) */ 2755ec142c44SVidya Sagar <0x00 0x3e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2756ec142c44SVidya Sagar <0x00 0x3e080000 0x0 0x00040000>, /* DBI space (256K) */ 2757ec142c44SVidya Sagar <0x2e 0x40000000 0x4 0x00000000>; /* Address Space (16G) */ 2758ec142c44SVidya Sagar reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2759ec142c44SVidya Sagar 2760ec142c44SVidya Sagar num-lanes = <8>; 2761ec142c44SVidya Sagar 2762ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX2_C7_CORE>; 2763ec142c44SVidya Sagar clock-names = "core"; 2764ec142c44SVidya Sagar 2765ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX2_CORE_7_APB>, 2766ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX2_CORE_7>; 2767ec142c44SVidya Sagar reset-names = "apb", "core"; 2768ec142c44SVidya Sagar 2769ec142c44SVidya Sagar interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2770ec142c44SVidya Sagar interrupt-names = "intr"; 2771ec142c44SVidya Sagar 2772ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 7>; 2773ec142c44SVidya Sagar 2774ec142c44SVidya Sagar nvidia,enable-ext-refclk; 2775ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2776ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2777ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2778ec142c44SVidya Sagar 2779ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE7AR &emc>, 2780ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE7AW &emc>; 2781ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2782ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>; 2783ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2784ec142c44SVidya Sagar dma-coherent; 2785ec142c44SVidya Sagar 2786ec142c44SVidya Sagar status = "disabled"; 2787ec142c44SVidya Sagar }; 2788ec142c44SVidya Sagar }; 2789ec142c44SVidya Sagar 27907fa30752SThierry Reding sram@40000000 { 279163944891SThierry Reding compatible = "nvidia,tegra234-sysram", "mmio-sram"; 279298094be1SMikko Perttunen reg = <0x0 0x40000000 0x0 0x80000>; 27932838cfddSThierry Reding 279463944891SThierry Reding #address-cells = <1>; 279563944891SThierry Reding #size-cells = <1>; 279698094be1SMikko Perttunen ranges = <0x0 0x0 0x40000000 0x80000>; 27972838cfddSThierry Reding 279861192a9dSMikko Perttunen no-memory-wc; 279963944891SThierry Reding 280098094be1SMikko Perttunen cpu_bpmp_tx: sram@70000 { 280198094be1SMikko Perttunen reg = <0x70000 0x1000>; 280263944891SThierry Reding label = "cpu-bpmp-tx"; 280363944891SThierry Reding pool; 280463944891SThierry Reding }; 280563944891SThierry Reding 280698094be1SMikko Perttunen cpu_bpmp_rx: sram@71000 { 280798094be1SMikko Perttunen reg = <0x71000 0x1000>; 280863944891SThierry Reding label = "cpu-bpmp-rx"; 280963944891SThierry Reding pool; 281063944891SThierry Reding }; 281163944891SThierry Reding }; 281263944891SThierry Reding 281363944891SThierry Reding bpmp: bpmp { 281463944891SThierry Reding compatible = "nvidia,tegra234-bpmp", "nvidia,tegra186-bpmp"; 281563944891SThierry Reding mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 281663944891SThierry Reding TEGRA_HSP_DB_MASTER_BPMP>; 28177fa30752SThierry Reding shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; 281863944891SThierry Reding #clock-cells = <1>; 281963944891SThierry Reding #reset-cells = <1>; 282063944891SThierry Reding #power-domain-cells = <1>; 28216de481e5SThierry Reding interconnects = <&mc TEGRA234_MEMORY_CLIENT_BPMPR &emc>, 28226de481e5SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_BPMPW &emc>, 28236de481e5SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAR &emc>, 28246de481e5SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAW &emc>; 28256de481e5SThierry Reding interconnect-names = "read", "write", "dma-mem", "dma-write"; 28265710e16aSThierry Reding iommus = <&smmu_niso1 TEGRA234_SID_BPMP>; 282763944891SThierry Reding 282863944891SThierry Reding bpmp_i2c: i2c { 282963944891SThierry Reding compatible = "nvidia,tegra186-bpmp-i2c"; 283063944891SThierry Reding nvidia,bpmp-bus-id = <5>; 283163944891SThierry Reding #address-cells = <1>; 283263944891SThierry Reding #size-cells = <0>; 283363944891SThierry Reding }; 283463944891SThierry Reding }; 283563944891SThierry Reding 283663944891SThierry Reding cpus { 283763944891SThierry Reding #address-cells = <1>; 283863944891SThierry Reding #size-cells = <0>; 283963944891SThierry Reding 2840a12cf5c3SThierry Reding cpu0_0: cpu@0 { 2841a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 284263944891SThierry Reding device_type = "cpu"; 2843a12cf5c3SThierry Reding reg = <0x00000>; 284463944891SThierry Reding 284563944891SThierry Reding enable-method = "psci"; 2846a12cf5c3SThierry Reding 2847a12cf5c3SThierry Reding i-cache-size = <65536>; 2848a12cf5c3SThierry Reding i-cache-line-size = <64>; 2849a12cf5c3SThierry Reding i-cache-sets = <256>; 2850a12cf5c3SThierry Reding d-cache-size = <65536>; 2851a12cf5c3SThierry Reding d-cache-line-size = <64>; 2852a12cf5c3SThierry Reding d-cache-sets = <256>; 2853a12cf5c3SThierry Reding next-level-cache = <&l2c0_0>; 285463944891SThierry Reding }; 2855a12cf5c3SThierry Reding 2856a12cf5c3SThierry Reding cpu0_1: cpu@100 { 2857a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 2858a12cf5c3SThierry Reding device_type = "cpu"; 2859a12cf5c3SThierry Reding reg = <0x00100>; 2860a12cf5c3SThierry Reding 2861a12cf5c3SThierry Reding enable-method = "psci"; 2862a12cf5c3SThierry Reding 2863a12cf5c3SThierry Reding i-cache-size = <65536>; 2864a12cf5c3SThierry Reding i-cache-line-size = <64>; 2865a12cf5c3SThierry Reding i-cache-sets = <256>; 2866a12cf5c3SThierry Reding d-cache-size = <65536>; 2867a12cf5c3SThierry Reding d-cache-line-size = <64>; 2868a12cf5c3SThierry Reding d-cache-sets = <256>; 2869a12cf5c3SThierry Reding next-level-cache = <&l2c0_1>; 2870a12cf5c3SThierry Reding }; 2871a12cf5c3SThierry Reding 2872a12cf5c3SThierry Reding cpu0_2: cpu@200 { 2873a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 2874a12cf5c3SThierry Reding device_type = "cpu"; 2875a12cf5c3SThierry Reding reg = <0x00200>; 2876a12cf5c3SThierry Reding 2877a12cf5c3SThierry Reding enable-method = "psci"; 2878a12cf5c3SThierry Reding 2879a12cf5c3SThierry Reding i-cache-size = <65536>; 2880a12cf5c3SThierry Reding i-cache-line-size = <64>; 2881a12cf5c3SThierry Reding i-cache-sets = <256>; 2882a12cf5c3SThierry Reding d-cache-size = <65536>; 2883a12cf5c3SThierry Reding d-cache-line-size = <64>; 2884a12cf5c3SThierry Reding d-cache-sets = <256>; 2885a12cf5c3SThierry Reding next-level-cache = <&l2c0_2>; 2886a12cf5c3SThierry Reding }; 2887a12cf5c3SThierry Reding 2888a12cf5c3SThierry Reding cpu0_3: cpu@300 { 2889a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 2890a12cf5c3SThierry Reding device_type = "cpu"; 2891a12cf5c3SThierry Reding reg = <0x00300>; 2892a12cf5c3SThierry Reding 2893a12cf5c3SThierry Reding enable-method = "psci"; 2894a12cf5c3SThierry Reding 2895a12cf5c3SThierry Reding i-cache-size = <65536>; 2896a12cf5c3SThierry Reding i-cache-line-size = <64>; 2897a12cf5c3SThierry Reding i-cache-sets = <256>; 2898a12cf5c3SThierry Reding d-cache-size = <65536>; 2899a12cf5c3SThierry Reding d-cache-line-size = <64>; 2900a12cf5c3SThierry Reding d-cache-sets = <256>; 2901a12cf5c3SThierry Reding next-level-cache = <&l2c0_3>; 2902a12cf5c3SThierry Reding }; 2903a12cf5c3SThierry Reding 2904a12cf5c3SThierry Reding cpu1_0: cpu@10000 { 2905a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 2906a12cf5c3SThierry Reding device_type = "cpu"; 2907a12cf5c3SThierry Reding reg = <0x10000>; 2908a12cf5c3SThierry Reding 2909a12cf5c3SThierry Reding enable-method = "psci"; 2910a12cf5c3SThierry Reding 2911a12cf5c3SThierry Reding i-cache-size = <65536>; 2912a12cf5c3SThierry Reding i-cache-line-size = <64>; 2913a12cf5c3SThierry Reding i-cache-sets = <256>; 2914a12cf5c3SThierry Reding d-cache-size = <65536>; 2915a12cf5c3SThierry Reding d-cache-line-size = <64>; 2916a12cf5c3SThierry Reding d-cache-sets = <256>; 2917a12cf5c3SThierry Reding next-level-cache = <&l2c1_0>; 2918a12cf5c3SThierry Reding }; 2919a12cf5c3SThierry Reding 2920a12cf5c3SThierry Reding cpu1_1: cpu@10100 { 2921a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 2922a12cf5c3SThierry Reding device_type = "cpu"; 2923a12cf5c3SThierry Reding reg = <0x10100>; 2924a12cf5c3SThierry Reding 2925a12cf5c3SThierry Reding enable-method = "psci"; 2926a12cf5c3SThierry Reding 2927a12cf5c3SThierry Reding i-cache-size = <65536>; 2928a12cf5c3SThierry Reding i-cache-line-size = <64>; 2929a12cf5c3SThierry Reding i-cache-sets = <256>; 2930a12cf5c3SThierry Reding d-cache-size = <65536>; 2931a12cf5c3SThierry Reding d-cache-line-size = <64>; 2932a12cf5c3SThierry Reding d-cache-sets = <256>; 2933a12cf5c3SThierry Reding next-level-cache = <&l2c1_1>; 2934a12cf5c3SThierry Reding }; 2935a12cf5c3SThierry Reding 2936a12cf5c3SThierry Reding cpu1_2: cpu@10200 { 2937a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 2938a12cf5c3SThierry Reding device_type = "cpu"; 2939a12cf5c3SThierry Reding reg = <0x10200>; 2940a12cf5c3SThierry Reding 2941a12cf5c3SThierry Reding enable-method = "psci"; 2942a12cf5c3SThierry Reding 2943a12cf5c3SThierry Reding i-cache-size = <65536>; 2944a12cf5c3SThierry Reding i-cache-line-size = <64>; 2945a12cf5c3SThierry Reding i-cache-sets = <256>; 2946a12cf5c3SThierry Reding d-cache-size = <65536>; 2947a12cf5c3SThierry Reding d-cache-line-size = <64>; 2948a12cf5c3SThierry Reding d-cache-sets = <256>; 2949a12cf5c3SThierry Reding next-level-cache = <&l2c1_2>; 2950a12cf5c3SThierry Reding }; 2951a12cf5c3SThierry Reding 2952a12cf5c3SThierry Reding cpu1_3: cpu@10300 { 2953a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 2954a12cf5c3SThierry Reding device_type = "cpu"; 2955a12cf5c3SThierry Reding reg = <0x10300>; 2956a12cf5c3SThierry Reding 2957a12cf5c3SThierry Reding enable-method = "psci"; 2958a12cf5c3SThierry Reding 2959a12cf5c3SThierry Reding i-cache-size = <65536>; 2960a12cf5c3SThierry Reding i-cache-line-size = <64>; 2961a12cf5c3SThierry Reding i-cache-sets = <256>; 2962a12cf5c3SThierry Reding d-cache-size = <65536>; 2963a12cf5c3SThierry Reding d-cache-line-size = <64>; 2964a12cf5c3SThierry Reding d-cache-sets = <256>; 2965a12cf5c3SThierry Reding next-level-cache = <&l2c1_3>; 2966a12cf5c3SThierry Reding }; 2967a12cf5c3SThierry Reding 2968a12cf5c3SThierry Reding cpu2_0: cpu@20000 { 2969a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 2970a12cf5c3SThierry Reding device_type = "cpu"; 2971a12cf5c3SThierry Reding reg = <0x20000>; 2972a12cf5c3SThierry Reding 2973a12cf5c3SThierry Reding enable-method = "psci"; 2974a12cf5c3SThierry Reding 2975a12cf5c3SThierry Reding i-cache-size = <65536>; 2976a12cf5c3SThierry Reding i-cache-line-size = <64>; 2977a12cf5c3SThierry Reding i-cache-sets = <256>; 2978a12cf5c3SThierry Reding d-cache-size = <65536>; 2979a12cf5c3SThierry Reding d-cache-line-size = <64>; 2980a12cf5c3SThierry Reding d-cache-sets = <256>; 2981a12cf5c3SThierry Reding next-level-cache = <&l2c2_0>; 2982a12cf5c3SThierry Reding }; 2983a12cf5c3SThierry Reding 2984a12cf5c3SThierry Reding cpu2_1: cpu@20100 { 2985a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 2986a12cf5c3SThierry Reding device_type = "cpu"; 2987a12cf5c3SThierry Reding reg = <0x20100>; 2988a12cf5c3SThierry Reding 2989a12cf5c3SThierry Reding enable-method = "psci"; 2990a12cf5c3SThierry Reding 2991a12cf5c3SThierry Reding i-cache-size = <65536>; 2992a12cf5c3SThierry Reding i-cache-line-size = <64>; 2993a12cf5c3SThierry Reding i-cache-sets = <256>; 2994a12cf5c3SThierry Reding d-cache-size = <65536>; 2995a12cf5c3SThierry Reding d-cache-line-size = <64>; 2996a12cf5c3SThierry Reding d-cache-sets = <256>; 2997a12cf5c3SThierry Reding next-level-cache = <&l2c2_1>; 2998a12cf5c3SThierry Reding }; 2999a12cf5c3SThierry Reding 3000a12cf5c3SThierry Reding cpu2_2: cpu@20200 { 3001a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 3002a12cf5c3SThierry Reding device_type = "cpu"; 3003a12cf5c3SThierry Reding reg = <0x20200>; 3004a12cf5c3SThierry Reding 3005a12cf5c3SThierry Reding enable-method = "psci"; 3006a12cf5c3SThierry Reding 3007a12cf5c3SThierry Reding i-cache-size = <65536>; 3008a12cf5c3SThierry Reding i-cache-line-size = <64>; 3009a12cf5c3SThierry Reding i-cache-sets = <256>; 3010a12cf5c3SThierry Reding d-cache-size = <65536>; 3011a12cf5c3SThierry Reding d-cache-line-size = <64>; 3012a12cf5c3SThierry Reding d-cache-sets = <256>; 3013a12cf5c3SThierry Reding next-level-cache = <&l2c2_2>; 3014a12cf5c3SThierry Reding }; 3015a12cf5c3SThierry Reding 3016a12cf5c3SThierry Reding cpu2_3: cpu@20300 { 3017a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 3018a12cf5c3SThierry Reding device_type = "cpu"; 3019a12cf5c3SThierry Reding reg = <0x20300>; 3020a12cf5c3SThierry Reding 3021a12cf5c3SThierry Reding enable-method = "psci"; 3022a12cf5c3SThierry Reding 3023a12cf5c3SThierry Reding i-cache-size = <65536>; 3024a12cf5c3SThierry Reding i-cache-line-size = <64>; 3025a12cf5c3SThierry Reding i-cache-sets = <256>; 3026a12cf5c3SThierry Reding d-cache-size = <65536>; 3027a12cf5c3SThierry Reding d-cache-line-size = <64>; 3028a12cf5c3SThierry Reding d-cache-sets = <256>; 3029a12cf5c3SThierry Reding next-level-cache = <&l2c2_3>; 3030a12cf5c3SThierry Reding }; 3031a12cf5c3SThierry Reding 3032a12cf5c3SThierry Reding cpu-map { 3033a12cf5c3SThierry Reding cluster0 { 3034a12cf5c3SThierry Reding core0 { 3035a12cf5c3SThierry Reding cpu = <&cpu0_0>; 3036a12cf5c3SThierry Reding }; 3037a12cf5c3SThierry Reding 3038a12cf5c3SThierry Reding core1 { 3039a12cf5c3SThierry Reding cpu = <&cpu0_1>; 3040a12cf5c3SThierry Reding }; 3041a12cf5c3SThierry Reding 3042a12cf5c3SThierry Reding core2 { 3043a12cf5c3SThierry Reding cpu = <&cpu0_2>; 3044a12cf5c3SThierry Reding }; 3045a12cf5c3SThierry Reding 3046a12cf5c3SThierry Reding core3 { 3047a12cf5c3SThierry Reding cpu = <&cpu0_3>; 3048a12cf5c3SThierry Reding }; 3049a12cf5c3SThierry Reding }; 3050a12cf5c3SThierry Reding 3051a12cf5c3SThierry Reding cluster1 { 3052a12cf5c3SThierry Reding core0 { 3053a12cf5c3SThierry Reding cpu = <&cpu1_0>; 3054a12cf5c3SThierry Reding }; 3055a12cf5c3SThierry Reding 3056a12cf5c3SThierry Reding core1 { 3057a12cf5c3SThierry Reding cpu = <&cpu1_1>; 3058a12cf5c3SThierry Reding }; 3059a12cf5c3SThierry Reding 3060a12cf5c3SThierry Reding core2 { 3061a12cf5c3SThierry Reding cpu = <&cpu1_2>; 3062a12cf5c3SThierry Reding }; 3063a12cf5c3SThierry Reding 3064a12cf5c3SThierry Reding core3 { 3065a12cf5c3SThierry Reding cpu = <&cpu1_3>; 3066a12cf5c3SThierry Reding }; 3067a12cf5c3SThierry Reding }; 3068a12cf5c3SThierry Reding 3069a12cf5c3SThierry Reding cluster2 { 3070a12cf5c3SThierry Reding core0 { 3071a12cf5c3SThierry Reding cpu = <&cpu2_0>; 3072a12cf5c3SThierry Reding }; 3073a12cf5c3SThierry Reding 3074a12cf5c3SThierry Reding core1 { 3075a12cf5c3SThierry Reding cpu = <&cpu2_1>; 3076a12cf5c3SThierry Reding }; 3077a12cf5c3SThierry Reding 3078a12cf5c3SThierry Reding core2 { 3079a12cf5c3SThierry Reding cpu = <&cpu2_2>; 3080a12cf5c3SThierry Reding }; 3081a12cf5c3SThierry Reding 3082a12cf5c3SThierry Reding core3 { 3083a12cf5c3SThierry Reding cpu = <&cpu2_3>; 3084a12cf5c3SThierry Reding }; 3085a12cf5c3SThierry Reding }; 3086a12cf5c3SThierry Reding }; 3087a12cf5c3SThierry Reding 3088a12cf5c3SThierry Reding l2c0_0: l2-cache00 { 308927f1568bSPierre Gondois compatible = "cache"; 3090a12cf5c3SThierry Reding cache-size = <262144>; 3091a12cf5c3SThierry Reding cache-line-size = <64>; 3092a12cf5c3SThierry Reding cache-sets = <512>; 3093a12cf5c3SThierry Reding cache-unified; 309427f1568bSPierre Gondois cache-level = <2>; 3095a12cf5c3SThierry Reding next-level-cache = <&l3c0>; 3096a12cf5c3SThierry Reding }; 3097a12cf5c3SThierry Reding 3098a12cf5c3SThierry Reding l2c0_1: l2-cache01 { 309927f1568bSPierre Gondois compatible = "cache"; 3100a12cf5c3SThierry Reding cache-size = <262144>; 3101a12cf5c3SThierry Reding cache-line-size = <64>; 3102a12cf5c3SThierry Reding cache-sets = <512>; 3103a12cf5c3SThierry Reding cache-unified; 310427f1568bSPierre Gondois cache-level = <2>; 3105a12cf5c3SThierry Reding next-level-cache = <&l3c0>; 3106a12cf5c3SThierry Reding }; 3107a12cf5c3SThierry Reding 3108a12cf5c3SThierry Reding l2c0_2: l2-cache02 { 310927f1568bSPierre Gondois compatible = "cache"; 3110a12cf5c3SThierry Reding cache-size = <262144>; 3111a12cf5c3SThierry Reding cache-line-size = <64>; 3112a12cf5c3SThierry Reding cache-sets = <512>; 3113a12cf5c3SThierry Reding cache-unified; 311427f1568bSPierre Gondois cache-level = <2>; 3115a12cf5c3SThierry Reding next-level-cache = <&l3c0>; 3116a12cf5c3SThierry Reding }; 3117a12cf5c3SThierry Reding 3118a12cf5c3SThierry Reding l2c0_3: l2-cache03 { 311927f1568bSPierre Gondois compatible = "cache"; 3120a12cf5c3SThierry Reding cache-size = <262144>; 3121a12cf5c3SThierry Reding cache-line-size = <64>; 3122a12cf5c3SThierry Reding cache-sets = <512>; 3123a12cf5c3SThierry Reding cache-unified; 312427f1568bSPierre Gondois cache-level = <2>; 3125a12cf5c3SThierry Reding next-level-cache = <&l3c0>; 3126a12cf5c3SThierry Reding }; 3127a12cf5c3SThierry Reding 3128a12cf5c3SThierry Reding l2c1_0: l2-cache10 { 312927f1568bSPierre Gondois compatible = "cache"; 3130a12cf5c3SThierry Reding cache-size = <262144>; 3131a12cf5c3SThierry Reding cache-line-size = <64>; 3132a12cf5c3SThierry Reding cache-sets = <512>; 3133a12cf5c3SThierry Reding cache-unified; 313427f1568bSPierre Gondois cache-level = <2>; 3135a12cf5c3SThierry Reding next-level-cache = <&l3c1>; 3136a12cf5c3SThierry Reding }; 3137a12cf5c3SThierry Reding 3138a12cf5c3SThierry Reding l2c1_1: l2-cache11 { 313927f1568bSPierre Gondois compatible = "cache"; 3140a12cf5c3SThierry Reding cache-size = <262144>; 3141a12cf5c3SThierry Reding cache-line-size = <64>; 3142a12cf5c3SThierry Reding cache-sets = <512>; 3143a12cf5c3SThierry Reding cache-unified; 314427f1568bSPierre Gondois cache-level = <2>; 3145a12cf5c3SThierry Reding next-level-cache = <&l3c1>; 3146a12cf5c3SThierry Reding }; 3147a12cf5c3SThierry Reding 3148a12cf5c3SThierry Reding l2c1_2: l2-cache12 { 314927f1568bSPierre Gondois compatible = "cache"; 3150a12cf5c3SThierry Reding cache-size = <262144>; 3151a12cf5c3SThierry Reding cache-line-size = <64>; 3152a12cf5c3SThierry Reding cache-sets = <512>; 3153a12cf5c3SThierry Reding cache-unified; 315427f1568bSPierre Gondois cache-level = <2>; 3155a12cf5c3SThierry Reding next-level-cache = <&l3c1>; 3156a12cf5c3SThierry Reding }; 3157a12cf5c3SThierry Reding 3158a12cf5c3SThierry Reding l2c1_3: l2-cache13 { 315927f1568bSPierre Gondois compatible = "cache"; 3160a12cf5c3SThierry Reding cache-size = <262144>; 3161a12cf5c3SThierry Reding cache-line-size = <64>; 3162a12cf5c3SThierry Reding cache-sets = <512>; 3163a12cf5c3SThierry Reding cache-unified; 316427f1568bSPierre Gondois cache-level = <2>; 3165a12cf5c3SThierry Reding next-level-cache = <&l3c1>; 3166a12cf5c3SThierry Reding }; 3167a12cf5c3SThierry Reding 3168a12cf5c3SThierry Reding l2c2_0: l2-cache20 { 316927f1568bSPierre Gondois compatible = "cache"; 3170a12cf5c3SThierry Reding cache-size = <262144>; 3171a12cf5c3SThierry Reding cache-line-size = <64>; 3172a12cf5c3SThierry Reding cache-sets = <512>; 3173a12cf5c3SThierry Reding cache-unified; 317427f1568bSPierre Gondois cache-level = <2>; 3175a12cf5c3SThierry Reding next-level-cache = <&l3c2>; 3176a12cf5c3SThierry Reding }; 3177a12cf5c3SThierry Reding 3178a12cf5c3SThierry Reding l2c2_1: l2-cache21 { 317927f1568bSPierre Gondois compatible = "cache"; 3180a12cf5c3SThierry Reding cache-size = <262144>; 3181a12cf5c3SThierry Reding cache-line-size = <64>; 3182a12cf5c3SThierry Reding cache-sets = <512>; 3183a12cf5c3SThierry Reding cache-unified; 318427f1568bSPierre Gondois cache-level = <2>; 3185a12cf5c3SThierry Reding next-level-cache = <&l3c2>; 3186a12cf5c3SThierry Reding }; 3187a12cf5c3SThierry Reding 3188a12cf5c3SThierry Reding l2c2_2: l2-cache22 { 318927f1568bSPierre Gondois compatible = "cache"; 3190a12cf5c3SThierry Reding cache-size = <262144>; 3191a12cf5c3SThierry Reding cache-line-size = <64>; 3192a12cf5c3SThierry Reding cache-sets = <512>; 3193a12cf5c3SThierry Reding cache-unified; 319427f1568bSPierre Gondois cache-level = <2>; 3195a12cf5c3SThierry Reding next-level-cache = <&l3c2>; 3196a12cf5c3SThierry Reding }; 3197a12cf5c3SThierry Reding 3198a12cf5c3SThierry Reding l2c2_3: l2-cache23 { 319927f1568bSPierre Gondois compatible = "cache"; 3200a12cf5c3SThierry Reding cache-size = <262144>; 3201a12cf5c3SThierry Reding cache-line-size = <64>; 3202a12cf5c3SThierry Reding cache-sets = <512>; 3203a12cf5c3SThierry Reding cache-unified; 320427f1568bSPierre Gondois cache-level = <2>; 3205a12cf5c3SThierry Reding next-level-cache = <&l3c2>; 3206a12cf5c3SThierry Reding }; 3207a12cf5c3SThierry Reding 3208a12cf5c3SThierry Reding l3c0: l3-cache0 { 320927f1568bSPierre Gondois compatible = "cache"; 321027f1568bSPierre Gondois cache-unified; 3211a12cf5c3SThierry Reding cache-size = <2097152>; 3212a12cf5c3SThierry Reding cache-line-size = <64>; 3213a12cf5c3SThierry Reding cache-sets = <2048>; 321427f1568bSPierre Gondois cache-level = <3>; 3215a12cf5c3SThierry Reding }; 3216a12cf5c3SThierry Reding 3217a12cf5c3SThierry Reding l3c1: l3-cache1 { 321827f1568bSPierre Gondois compatible = "cache"; 321927f1568bSPierre Gondois cache-unified; 3220a12cf5c3SThierry Reding cache-size = <2097152>; 3221a12cf5c3SThierry Reding cache-line-size = <64>; 3222a12cf5c3SThierry Reding cache-sets = <2048>; 322327f1568bSPierre Gondois cache-level = <3>; 3224a12cf5c3SThierry Reding }; 3225a12cf5c3SThierry Reding 3226a12cf5c3SThierry Reding l3c2: l3-cache2 { 322727f1568bSPierre Gondois compatible = "cache"; 322827f1568bSPierre Gondois cache-unified; 3229a12cf5c3SThierry Reding cache-size = <2097152>; 3230a12cf5c3SThierry Reding cache-line-size = <64>; 3231a12cf5c3SThierry Reding cache-sets = <2048>; 323227f1568bSPierre Gondois cache-level = <3>; 3233a12cf5c3SThierry Reding }; 3234a12cf5c3SThierry Reding }; 3235a12cf5c3SThierry Reding 3236a12cf5c3SThierry Reding pmu { 3237a12cf5c3SThierry Reding compatible = "arm,cortex-a78-pmu"; 3238a12cf5c3SThierry Reding interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 3239a12cf5c3SThierry Reding status = "okay"; 324063944891SThierry Reding }; 324163944891SThierry Reding 324263944891SThierry Reding psci { 324363944891SThierry Reding compatible = "arm,psci-1.0"; 324463944891SThierry Reding status = "okay"; 324563944891SThierry Reding method = "smc"; 324663944891SThierry Reding }; 324763944891SThierry Reding 324806ad2ec4SMikko Perttunen tcu: serial { 324906ad2ec4SMikko Perttunen compatible = "nvidia,tegra234-tcu", "nvidia,tegra194-tcu"; 325006ad2ec4SMikko Perttunen mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 325106ad2ec4SMikko Perttunen <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 325206ad2ec4SMikko Perttunen mbox-names = "rx", "tx"; 325306ad2ec4SMikko Perttunen status = "disabled"; 325406ad2ec4SMikko Perttunen }; 325506ad2ec4SMikko Perttunen 325609614acdSSameer Pujar sound { 325709614acdSSameer Pujar status = "disabled"; 325809614acdSSameer Pujar 325909614acdSSameer Pujar clocks = <&bpmp TEGRA234_CLK_PLLA>, 326009614acdSSameer Pujar <&bpmp TEGRA234_CLK_PLLA_OUT0>; 326109614acdSSameer Pujar clock-names = "pll_a", "plla_out0"; 326209614acdSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_PLLA>, 326309614acdSSameer Pujar <&bpmp TEGRA234_CLK_PLLA_OUT0>, 326409614acdSSameer Pujar <&bpmp TEGRA234_CLK_AUD_MCLK>; 326509614acdSSameer Pujar assigned-clock-parents = <0>, 326609614acdSSameer Pujar <&bpmp TEGRA234_CLK_PLLA>, 326709614acdSSameer Pujar <&bpmp TEGRA234_CLK_PLLA_OUT0>; 326809614acdSSameer Pujar }; 326909614acdSSameer Pujar 327063944891SThierry Reding timer { 327163944891SThierry Reding compatible = "arm,armv8-timer"; 327263944891SThierry Reding interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 327363944891SThierry Reding <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 327463944891SThierry Reding <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 327563944891SThierry Reding <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 327663944891SThierry Reding interrupt-parent = <&gic>; 327763944891SThierry Reding always-on; 327863944891SThierry Reding }; 327963944891SThierry Reding}; 3280