163944891SThierry Reding// SPDX-License-Identifier: GPL-2.0
263944891SThierry Reding
363944891SThierry Reding#include <dt-bindings/clock/tegra234-clock.h>
4699349e0SThierry Reding#include <dt-bindings/gpio/tegra234-gpio.h>
563944891SThierry Reding#include <dt-bindings/interrupt-controller/arm-gic.h>
663944891SThierry Reding#include <dt-bindings/mailbox/tegra186-hsp.h>
7eed280dfSThierry Reding#include <dt-bindings/memory/tegra234-mc.h>
8dc94a94dSSameer Pujar#include <dt-bindings/power/tegra234-powergate.h>
963944891SThierry Reding#include <dt-bindings/reset/tegra234-reset.h>
10d71b893aSPrathamesh Shete#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
1163944891SThierry Reding
1263944891SThierry Reding/ {
1363944891SThierry Reding	compatible = "nvidia,tegra234";
1463944891SThierry Reding	interrupt-parent = <&gic>;
1563944891SThierry Reding	#address-cells = <2>;
1663944891SThierry Reding	#size-cells = <2>;
1763944891SThierry Reding
1863944891SThierry Reding	bus@0 {
1963944891SThierry Reding		compatible = "simple-bus";
2063944891SThierry Reding		#address-cells = <1>;
2163944891SThierry Reding		#size-cells = <1>;
2263944891SThierry Reding
2363944891SThierry Reding		ranges = <0x0 0x0 0x0 0x40000000>;
2463944891SThierry Reding
2560d2016aSAkhil R		gpcdma: dma-controller@2600000 {
26f7b93a08SAkhil R			compatible = "nvidia,tegra234-gpcdma",
2760d2016aSAkhil R				     "nvidia,tegra186-gpcdma";
2860d2016aSAkhil R			reg = <0x2600000 0x210000>;
2960d2016aSAkhil R			resets = <&bpmp TEGRA234_RESET_GPCDMA>;
3060d2016aSAkhil R			reset-names = "gpcdma";
3160d2016aSAkhil R			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
3260d2016aSAkhil R				     <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
3360d2016aSAkhil R				     <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
3460d2016aSAkhil R				     <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
3560d2016aSAkhil R				     <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
3660d2016aSAkhil R				     <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
3760d2016aSAkhil R				     <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
3860d2016aSAkhil R				     <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
3960d2016aSAkhil R				     <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
4060d2016aSAkhil R				     <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
4160d2016aSAkhil R				     <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
4260d2016aSAkhil R				     <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
4360d2016aSAkhil R				     <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
4460d2016aSAkhil R				     <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
4560d2016aSAkhil R				     <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
4660d2016aSAkhil R				     <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
4760d2016aSAkhil R				     <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
4860d2016aSAkhil R				     <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
4960d2016aSAkhil R				     <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
5060d2016aSAkhil R				     <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
5160d2016aSAkhil R				     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
5260d2016aSAkhil R				     <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
5360d2016aSAkhil R				     <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
5460d2016aSAkhil R				     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
5560d2016aSAkhil R				     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
5660d2016aSAkhil R				     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
5760d2016aSAkhil R				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
5860d2016aSAkhil R				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
5960d2016aSAkhil R				     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
6060d2016aSAkhil R				     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
6160d2016aSAkhil R				     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
6260d2016aSAkhil R			#dma-cells = <1>;
6360d2016aSAkhil R			iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
6460d2016aSAkhil R			dma-coherent;
6560d2016aSAkhil R		};
6660d2016aSAkhil R
67dc94a94dSSameer Pujar		aconnect@2900000 {
68dc94a94dSSameer Pujar			compatible = "nvidia,tegra234-aconnect",
69dc94a94dSSameer Pujar				     "nvidia,tegra210-aconnect";
70dc94a94dSSameer Pujar			clocks = <&bpmp TEGRA234_CLK_APE>,
71dc94a94dSSameer Pujar				 <&bpmp TEGRA234_CLK_APB2APE>;
72dc94a94dSSameer Pujar			clock-names = "ape", "apb2ape";
73dc94a94dSSameer Pujar			power-domains = <&bpmp TEGRA234_POWER_DOMAIN_AUD>;
74dc94a94dSSameer Pujar			#address-cells = <1>;
75dc94a94dSSameer Pujar			#size-cells = <1>;
76dc94a94dSSameer Pujar			ranges = <0x02900000 0x02900000 0x200000>;
77dc94a94dSSameer Pujar			status = "disabled";
78dc94a94dSSameer Pujar
79dc94a94dSSameer Pujar			tegra_ahub: ahub@2900800 {
80dc94a94dSSameer Pujar				compatible = "nvidia,tegra234-ahub";
81dc94a94dSSameer Pujar				reg = <0x02900800 0x800>;
82dc94a94dSSameer Pujar				clocks = <&bpmp TEGRA234_CLK_AHUB>;
83dc94a94dSSameer Pujar				clock-names = "ahub";
84dc94a94dSSameer Pujar				assigned-clocks = <&bpmp TEGRA234_CLK_AHUB>;
85dc94a94dSSameer Pujar				assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
86dc94a94dSSameer Pujar				#address-cells = <1>;
87dc94a94dSSameer Pujar				#size-cells = <1>;
88dc94a94dSSameer Pujar				ranges = <0x02900800 0x02900800 0x11800>;
89dc94a94dSSameer Pujar				status = "disabled";
90dc94a94dSSameer Pujar
91dc94a94dSSameer Pujar				tegra_i2s1: i2s@2901000 {
92dc94a94dSSameer Pujar					compatible = "nvidia,tegra234-i2s",
93dc94a94dSSameer Pujar						     "nvidia,tegra210-i2s";
94dc94a94dSSameer Pujar					reg = <0x2901000 0x100>;
95dc94a94dSSameer Pujar					clocks = <&bpmp TEGRA234_CLK_I2S1>,
96dc94a94dSSameer Pujar						 <&bpmp TEGRA234_CLK_I2S1_SYNC_INPUT>;
97dc94a94dSSameer Pujar					clock-names = "i2s", "sync_input";
98dc94a94dSSameer Pujar					assigned-clocks = <&bpmp TEGRA234_CLK_I2S1>;
99dc94a94dSSameer Pujar					assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
100dc94a94dSSameer Pujar					assigned-clock-rates = <1536000>;
101dc94a94dSSameer Pujar					sound-name-prefix = "I2S1";
102dc94a94dSSameer Pujar					status = "disabled";
103dc94a94dSSameer Pujar				};
104dc94a94dSSameer Pujar
105dc94a94dSSameer Pujar				tegra_i2s2: i2s@2901100 {
106dc94a94dSSameer Pujar					compatible = "nvidia,tegra234-i2s",
107dc94a94dSSameer Pujar						     "nvidia,tegra210-i2s";
108dc94a94dSSameer Pujar					reg = <0x2901100 0x100>;
109dc94a94dSSameer Pujar					clocks = <&bpmp TEGRA234_CLK_I2S2>,
110dc94a94dSSameer Pujar						 <&bpmp TEGRA234_CLK_I2S2_SYNC_INPUT>;
111dc94a94dSSameer Pujar					clock-names = "i2s", "sync_input";
112dc94a94dSSameer Pujar					assigned-clocks = <&bpmp TEGRA234_CLK_I2S2>;
113dc94a94dSSameer Pujar					assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
114dc94a94dSSameer Pujar					assigned-clock-rates = <1536000>;
115dc94a94dSSameer Pujar					sound-name-prefix = "I2S2";
116dc94a94dSSameer Pujar					status = "disabled";
117dc94a94dSSameer Pujar				};
118dc94a94dSSameer Pujar
119dc94a94dSSameer Pujar				tegra_i2s3: i2s@2901200 {
120dc94a94dSSameer Pujar					compatible = "nvidia,tegra234-i2s",
121dc94a94dSSameer Pujar						     "nvidia,tegra210-i2s";
122dc94a94dSSameer Pujar					reg = <0x2901200 0x100>;
123dc94a94dSSameer Pujar					clocks = <&bpmp TEGRA234_CLK_I2S3>,
124dc94a94dSSameer Pujar						 <&bpmp TEGRA234_CLK_I2S3_SYNC_INPUT>;
125dc94a94dSSameer Pujar					clock-names = "i2s", "sync_input";
126dc94a94dSSameer Pujar					assigned-clocks = <&bpmp TEGRA234_CLK_I2S3>;
127dc94a94dSSameer Pujar					assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
128dc94a94dSSameer Pujar					assigned-clock-rates = <1536000>;
129dc94a94dSSameer Pujar					sound-name-prefix = "I2S3";
130dc94a94dSSameer Pujar					status = "disabled";
131dc94a94dSSameer Pujar				};
132dc94a94dSSameer Pujar
133dc94a94dSSameer Pujar				tegra_i2s4: i2s@2901300 {
134dc94a94dSSameer Pujar					compatible = "nvidia,tegra234-i2s",
135dc94a94dSSameer Pujar						     "nvidia,tegra210-i2s";
136dc94a94dSSameer Pujar					reg = <0x2901300 0x100>;
137dc94a94dSSameer Pujar					clocks = <&bpmp TEGRA234_CLK_I2S4>,
138dc94a94dSSameer Pujar						 <&bpmp TEGRA234_CLK_I2S4_SYNC_INPUT>;
139dc94a94dSSameer Pujar					clock-names = "i2s", "sync_input";
140dc94a94dSSameer Pujar					assigned-clocks = <&bpmp TEGRA234_CLK_I2S4>;
141dc94a94dSSameer Pujar					assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
142dc94a94dSSameer Pujar					assigned-clock-rates = <1536000>;
143dc94a94dSSameer Pujar					sound-name-prefix = "I2S4";
144dc94a94dSSameer Pujar					status = "disabled";
145dc94a94dSSameer Pujar				};
146dc94a94dSSameer Pujar
147dc94a94dSSameer Pujar				tegra_i2s5: i2s@2901400 {
148dc94a94dSSameer Pujar					compatible = "nvidia,tegra234-i2s",
149dc94a94dSSameer Pujar						     "nvidia,tegra210-i2s";
150dc94a94dSSameer Pujar					reg = <0x2901400 0x100>;
151dc94a94dSSameer Pujar					clocks = <&bpmp TEGRA234_CLK_I2S5>,
152dc94a94dSSameer Pujar						 <&bpmp TEGRA234_CLK_I2S5_SYNC_INPUT>;
153dc94a94dSSameer Pujar					clock-names = "i2s", "sync_input";
154dc94a94dSSameer Pujar					assigned-clocks = <&bpmp TEGRA234_CLK_I2S5>;
155dc94a94dSSameer Pujar					assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
156dc94a94dSSameer Pujar					assigned-clock-rates = <1536000>;
157dc94a94dSSameer Pujar					sound-name-prefix = "I2S5";
158dc94a94dSSameer Pujar					status = "disabled";
159dc94a94dSSameer Pujar				};
160dc94a94dSSameer Pujar
161dc94a94dSSameer Pujar				tegra_i2s6: i2s@2901500 {
162dc94a94dSSameer Pujar					compatible = "nvidia,tegra234-i2s",
163dc94a94dSSameer Pujar						     "nvidia,tegra210-i2s";
164dc94a94dSSameer Pujar					reg = <0x2901500 0x100>;
165dc94a94dSSameer Pujar					clocks = <&bpmp TEGRA234_CLK_I2S6>,
166dc94a94dSSameer Pujar						 <&bpmp TEGRA234_CLK_I2S6_SYNC_INPUT>;
167dc94a94dSSameer Pujar					clock-names = "i2s", "sync_input";
168dc94a94dSSameer Pujar					assigned-clocks = <&bpmp TEGRA234_CLK_I2S6>;
169dc94a94dSSameer Pujar					assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
170dc94a94dSSameer Pujar					assigned-clock-rates = <1536000>;
171dc94a94dSSameer Pujar					sound-name-prefix = "I2S6";
172dc94a94dSSameer Pujar					status = "disabled";
173dc94a94dSSameer Pujar				};
174dc94a94dSSameer Pujar
175dc94a94dSSameer Pujar				tegra_sfc1: sfc@2902000 {
176dc94a94dSSameer Pujar					compatible = "nvidia,tegra234-sfc",
177dc94a94dSSameer Pujar						     "nvidia,tegra210-sfc";
178dc94a94dSSameer Pujar					reg = <0x2902000 0x200>;
179dc94a94dSSameer Pujar					sound-name-prefix = "SFC1";
180dc94a94dSSameer Pujar					status = "disabled";
181dc94a94dSSameer Pujar				};
182dc94a94dSSameer Pujar
183dc94a94dSSameer Pujar				tegra_sfc2: sfc@2902200 {
184dc94a94dSSameer Pujar					compatible = "nvidia,tegra234-sfc",
185dc94a94dSSameer Pujar						     "nvidia,tegra210-sfc";
186dc94a94dSSameer Pujar					reg = <0x2902200 0x200>;
187dc94a94dSSameer Pujar					sound-name-prefix = "SFC2";
188dc94a94dSSameer Pujar					status = "disabled";
189dc94a94dSSameer Pujar				};
190dc94a94dSSameer Pujar
191dc94a94dSSameer Pujar				tegra_sfc3: sfc@2902400 {
192dc94a94dSSameer Pujar					compatible = "nvidia,tegra234-sfc",
193dc94a94dSSameer Pujar						     "nvidia,tegra210-sfc";
194dc94a94dSSameer Pujar					reg = <0x2902400 0x200>;
195dc94a94dSSameer Pujar					sound-name-prefix = "SFC3";
196dc94a94dSSameer Pujar					status = "disabled";
197dc94a94dSSameer Pujar				};
198dc94a94dSSameer Pujar
199dc94a94dSSameer Pujar				tegra_sfc4: sfc@2902600 {
200dc94a94dSSameer Pujar					compatible = "nvidia,tegra234-sfc",
201dc94a94dSSameer Pujar						     "nvidia,tegra210-sfc";
202dc94a94dSSameer Pujar					reg = <0x2902600 0x200>;
203dc94a94dSSameer Pujar					sound-name-prefix = "SFC4";
204dc94a94dSSameer Pujar					status = "disabled";
205dc94a94dSSameer Pujar				};
206dc94a94dSSameer Pujar
207dc94a94dSSameer Pujar				tegra_amx1: amx@2903000 {
208dc94a94dSSameer Pujar					compatible = "nvidia,tegra234-amx",
209dc94a94dSSameer Pujar						     "nvidia,tegra194-amx";
210dc94a94dSSameer Pujar					reg = <0x2903000 0x100>;
211dc94a94dSSameer Pujar					sound-name-prefix = "AMX1";
212dc94a94dSSameer Pujar					status = "disabled";
213dc94a94dSSameer Pujar				};
214dc94a94dSSameer Pujar
215dc94a94dSSameer Pujar				tegra_amx2: amx@2903100 {
216dc94a94dSSameer Pujar					compatible = "nvidia,tegra234-amx",
217dc94a94dSSameer Pujar						     "nvidia,tegra194-amx";
218dc94a94dSSameer Pujar					reg = <0x2903100 0x100>;
219dc94a94dSSameer Pujar					sound-name-prefix = "AMX2";
220dc94a94dSSameer Pujar					status = "disabled";
221dc94a94dSSameer Pujar				};
222dc94a94dSSameer Pujar
223dc94a94dSSameer Pujar				tegra_amx3: amx@2903200 {
224dc94a94dSSameer Pujar					compatible = "nvidia,tegra234-amx",
225dc94a94dSSameer Pujar						     "nvidia,tegra194-amx";
226dc94a94dSSameer Pujar					reg = <0x2903200 0x100>;
227dc94a94dSSameer Pujar					sound-name-prefix = "AMX3";
228dc94a94dSSameer Pujar					status = "disabled";
229dc94a94dSSameer Pujar				};
230dc94a94dSSameer Pujar
231dc94a94dSSameer Pujar				tegra_amx4: amx@2903300 {
232dc94a94dSSameer Pujar					compatible = "nvidia,tegra234-amx",
233dc94a94dSSameer Pujar						     "nvidia,tegra194-amx";
234dc94a94dSSameer Pujar					reg = <0x2903300 0x100>;
235dc94a94dSSameer Pujar					sound-name-prefix = "AMX4";
236dc94a94dSSameer Pujar					status = "disabled";
237dc94a94dSSameer Pujar				};
238dc94a94dSSameer Pujar
239dc94a94dSSameer Pujar				tegra_adx1: adx@2903800 {
240dc94a94dSSameer Pujar					compatible = "nvidia,tegra234-adx",
241dc94a94dSSameer Pujar						     "nvidia,tegra210-adx";
242dc94a94dSSameer Pujar					reg = <0x2903800 0x100>;
243dc94a94dSSameer Pujar					sound-name-prefix = "ADX1";
244dc94a94dSSameer Pujar					status = "disabled";
245dc94a94dSSameer Pujar				};
246dc94a94dSSameer Pujar
247dc94a94dSSameer Pujar				tegra_adx2: adx@2903900 {
248dc94a94dSSameer Pujar					compatible = "nvidia,tegra234-adx",
249dc94a94dSSameer Pujar						     "nvidia,tegra210-adx";
250dc94a94dSSameer Pujar					reg = <0x2903900 0x100>;
251dc94a94dSSameer Pujar					sound-name-prefix = "ADX2";
252dc94a94dSSameer Pujar					status = "disabled";
253dc94a94dSSameer Pujar				};
254dc94a94dSSameer Pujar
255dc94a94dSSameer Pujar				tegra_adx3: adx@2903a00 {
256dc94a94dSSameer Pujar					compatible = "nvidia,tegra234-adx",
257dc94a94dSSameer Pujar						     "nvidia,tegra210-adx";
258dc94a94dSSameer Pujar					reg = <0x2903a00 0x100>;
259dc94a94dSSameer Pujar					sound-name-prefix = "ADX3";
260dc94a94dSSameer Pujar					status = "disabled";
261dc94a94dSSameer Pujar				};
262dc94a94dSSameer Pujar
263dc94a94dSSameer Pujar				tegra_adx4: adx@2903b00 {
264dc94a94dSSameer Pujar					compatible = "nvidia,tegra234-adx",
265dc94a94dSSameer Pujar						     "nvidia,tegra210-adx";
266dc94a94dSSameer Pujar					reg = <0x2903b00 0x100>;
267dc94a94dSSameer Pujar					sound-name-prefix = "ADX4";
268dc94a94dSSameer Pujar					status = "disabled";
269dc94a94dSSameer Pujar				};
270dc94a94dSSameer Pujar
271dc94a94dSSameer Pujar
272dc94a94dSSameer Pujar				tegra_dmic1: dmic@2904000 {
273dc94a94dSSameer Pujar					compatible = "nvidia,tegra234-dmic",
274dc94a94dSSameer Pujar						     "nvidia,tegra210-dmic";
275dc94a94dSSameer Pujar					reg = <0x2904000 0x100>;
276dc94a94dSSameer Pujar					clocks = <&bpmp TEGRA234_CLK_DMIC1>;
277dc94a94dSSameer Pujar					clock-names = "dmic";
278dc94a94dSSameer Pujar					assigned-clocks = <&bpmp TEGRA234_CLK_DMIC1>;
279dc94a94dSSameer Pujar					assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
280dc94a94dSSameer Pujar					assigned-clock-rates = <3072000>;
281dc94a94dSSameer Pujar					sound-name-prefix = "DMIC1";
282dc94a94dSSameer Pujar					status = "disabled";
283dc94a94dSSameer Pujar				};
284dc94a94dSSameer Pujar
285dc94a94dSSameer Pujar				tegra_dmic2: dmic@2904100 {
286dc94a94dSSameer Pujar					compatible = "nvidia,tegra234-dmic",
287dc94a94dSSameer Pujar						     "nvidia,tegra210-dmic";
288dc94a94dSSameer Pujar					reg = <0x2904100 0x100>;
289dc94a94dSSameer Pujar					clocks = <&bpmp TEGRA234_CLK_DMIC2>;
290dc94a94dSSameer Pujar					clock-names = "dmic";
291dc94a94dSSameer Pujar					assigned-clocks = <&bpmp TEGRA234_CLK_DMIC2>;
292dc94a94dSSameer Pujar					assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
293dc94a94dSSameer Pujar					assigned-clock-rates = <3072000>;
294dc94a94dSSameer Pujar					sound-name-prefix = "DMIC2";
295dc94a94dSSameer Pujar					status = "disabled";
296dc94a94dSSameer Pujar				};
297dc94a94dSSameer Pujar
298dc94a94dSSameer Pujar				tegra_dmic3: dmic@2904200 {
299dc94a94dSSameer Pujar					compatible = "nvidia,tegra234-dmic",
300dc94a94dSSameer Pujar						     "nvidia,tegra210-dmic";
301dc94a94dSSameer Pujar					reg = <0x2904200 0x100>;
302dc94a94dSSameer Pujar					clocks = <&bpmp TEGRA234_CLK_DMIC3>;
303dc94a94dSSameer Pujar					clock-names = "dmic";
304dc94a94dSSameer Pujar					assigned-clocks = <&bpmp TEGRA234_CLK_DMIC3>;
305dc94a94dSSameer Pujar					assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
306dc94a94dSSameer Pujar					assigned-clock-rates = <3072000>;
307dc94a94dSSameer Pujar					sound-name-prefix = "DMIC3";
308dc94a94dSSameer Pujar					status = "disabled";
309dc94a94dSSameer Pujar				};
310dc94a94dSSameer Pujar
311dc94a94dSSameer Pujar				tegra_dmic4: dmic@2904300 {
312dc94a94dSSameer Pujar					compatible = "nvidia,tegra234-dmic",
313dc94a94dSSameer Pujar						     "nvidia,tegra210-dmic";
314dc94a94dSSameer Pujar					reg = <0x2904300 0x100>;
315dc94a94dSSameer Pujar					clocks = <&bpmp TEGRA234_CLK_DMIC4>;
316dc94a94dSSameer Pujar					clock-names = "dmic";
317dc94a94dSSameer Pujar					assigned-clocks = <&bpmp TEGRA234_CLK_DMIC4>;
318dc94a94dSSameer Pujar					assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
319dc94a94dSSameer Pujar					assigned-clock-rates = <3072000>;
320dc94a94dSSameer Pujar					sound-name-prefix = "DMIC4";
321dc94a94dSSameer Pujar					status = "disabled";
322dc94a94dSSameer Pujar				};
323dc94a94dSSameer Pujar
324dc94a94dSSameer Pujar				tegra_dspk1: dspk@2905000 {
325dc94a94dSSameer Pujar					compatible = "nvidia,tegra234-dspk",
326dc94a94dSSameer Pujar						     "nvidia,tegra186-dspk";
327dc94a94dSSameer Pujar					reg = <0x2905000 0x100>;
328dc94a94dSSameer Pujar					clocks = <&bpmp TEGRA234_CLK_DSPK1>;
329dc94a94dSSameer Pujar					clock-names = "dspk";
330dc94a94dSSameer Pujar					assigned-clocks = <&bpmp TEGRA234_CLK_DSPK1>;
331dc94a94dSSameer Pujar					assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
332dc94a94dSSameer Pujar					assigned-clock-rates = <12288000>;
333dc94a94dSSameer Pujar					sound-name-prefix = "DSPK1";
334dc94a94dSSameer Pujar					status = "disabled";
335dc94a94dSSameer Pujar				};
336dc94a94dSSameer Pujar
337dc94a94dSSameer Pujar				tegra_dspk2: dspk@2905100 {
338dc94a94dSSameer Pujar					compatible = "nvidia,tegra234-dspk",
339dc94a94dSSameer Pujar						     "nvidia,tegra186-dspk";
340dc94a94dSSameer Pujar					reg = <0x2905100 0x100>;
341dc94a94dSSameer Pujar					clocks = <&bpmp TEGRA234_CLK_DSPK2>;
342dc94a94dSSameer Pujar					clock-names = "dspk";
343dc94a94dSSameer Pujar					assigned-clocks = <&bpmp TEGRA234_CLK_DSPK2>;
344dc94a94dSSameer Pujar					assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
345dc94a94dSSameer Pujar					assigned-clock-rates = <12288000>;
346dc94a94dSSameer Pujar					sound-name-prefix = "DSPK2";
347dc94a94dSSameer Pujar					status = "disabled";
348dc94a94dSSameer Pujar				};
349dc94a94dSSameer Pujar
3504b6a1b7cSSameer Pujar				tegra_ope1: processing-engine@2908000 {
3514b6a1b7cSSameer Pujar					compatible = "nvidia,tegra234-ope",
3524b6a1b7cSSameer Pujar						     "nvidia,tegra210-ope";
3534b6a1b7cSSameer Pujar					reg = <0x2908000 0x100>;
3544b6a1b7cSSameer Pujar					#address-cells = <1>;
3554b6a1b7cSSameer Pujar					#size-cells = <1>;
3564b6a1b7cSSameer Pujar					ranges;
3574b6a1b7cSSameer Pujar					sound-name-prefix = "OPE1";
3584b6a1b7cSSameer Pujar					status = "disabled";
3594b6a1b7cSSameer Pujar
3604b6a1b7cSSameer Pujar					equalizer@2908100 {
3614b6a1b7cSSameer Pujar						compatible = "nvidia,tegra234-peq",
3624b6a1b7cSSameer Pujar							     "nvidia,tegra210-peq";
3634b6a1b7cSSameer Pujar						reg = <0x2908100 0x100>;
3644b6a1b7cSSameer Pujar					};
3654b6a1b7cSSameer Pujar
3664b6a1b7cSSameer Pujar					dynamic-range-compressor@2908200 {
3674b6a1b7cSSameer Pujar						compatible = "nvidia,tegra234-mbdrc",
3684b6a1b7cSSameer Pujar							     "nvidia,tegra210-mbdrc";
3694b6a1b7cSSameer Pujar						reg = <0x2908200 0x200>;
3704b6a1b7cSSameer Pujar					};
3714b6a1b7cSSameer Pujar				};
3724b6a1b7cSSameer Pujar
373dc94a94dSSameer Pujar				tegra_mvc1: mvc@290a000 {
374dc94a94dSSameer Pujar					compatible = "nvidia,tegra234-mvc",
375dc94a94dSSameer Pujar						     "nvidia,tegra210-mvc";
376dc94a94dSSameer Pujar					reg = <0x290a000 0x200>;
377dc94a94dSSameer Pujar					sound-name-prefix = "MVC1";
378dc94a94dSSameer Pujar					status = "disabled";
379dc94a94dSSameer Pujar				};
380dc94a94dSSameer Pujar
381dc94a94dSSameer Pujar				tegra_mvc2: mvc@290a200 {
382dc94a94dSSameer Pujar					compatible = "nvidia,tegra234-mvc",
383dc94a94dSSameer Pujar						     "nvidia,tegra210-mvc";
384dc94a94dSSameer Pujar					reg = <0x290a200 0x200>;
385dc94a94dSSameer Pujar					sound-name-prefix = "MVC2";
386dc94a94dSSameer Pujar					status = "disabled";
387dc94a94dSSameer Pujar				};
388dc94a94dSSameer Pujar
389dc94a94dSSameer Pujar				tegra_amixer: amixer@290bb00 {
390dc94a94dSSameer Pujar					compatible = "nvidia,tegra234-amixer",
391dc94a94dSSameer Pujar						     "nvidia,tegra210-amixer";
392dc94a94dSSameer Pujar					reg = <0x290bb00 0x800>;
393dc94a94dSSameer Pujar					sound-name-prefix = "MIXER1";
394dc94a94dSSameer Pujar					status = "disabled";
395dc94a94dSSameer Pujar				};
396dc94a94dSSameer Pujar
397dc94a94dSSameer Pujar				tegra_admaif: admaif@290f000 {
398dc94a94dSSameer Pujar					compatible = "nvidia,tegra234-admaif",
399dc94a94dSSameer Pujar						     "nvidia,tegra186-admaif";
400dc94a94dSSameer Pujar					reg = <0x0290f000 0x1000>;
401dc94a94dSSameer Pujar					dmas = <&adma 1>, <&adma 1>,
402dc94a94dSSameer Pujar					       <&adma 2>, <&adma 2>,
403dc94a94dSSameer Pujar					       <&adma 3>, <&adma 3>,
404dc94a94dSSameer Pujar					       <&adma 4>, <&adma 4>,
405dc94a94dSSameer Pujar					       <&adma 5>, <&adma 5>,
406dc94a94dSSameer Pujar					       <&adma 6>, <&adma 6>,
407dc94a94dSSameer Pujar					       <&adma 7>, <&adma 7>,
408dc94a94dSSameer Pujar					       <&adma 8>, <&adma 8>,
409dc94a94dSSameer Pujar					       <&adma 9>, <&adma 9>,
410dc94a94dSSameer Pujar					       <&adma 10>, <&adma 10>,
411dc94a94dSSameer Pujar					       <&adma 11>, <&adma 11>,
412dc94a94dSSameer Pujar					       <&adma 12>, <&adma 12>,
413dc94a94dSSameer Pujar					       <&adma 13>, <&adma 13>,
414dc94a94dSSameer Pujar					       <&adma 14>, <&adma 14>,
415dc94a94dSSameer Pujar					       <&adma 15>, <&adma 15>,
416dc94a94dSSameer Pujar					       <&adma 16>, <&adma 16>,
417dc94a94dSSameer Pujar					       <&adma 17>, <&adma 17>,
418dc94a94dSSameer Pujar					       <&adma 18>, <&adma 18>,
419dc94a94dSSameer Pujar					       <&adma 19>, <&adma 19>,
420dc94a94dSSameer Pujar					       <&adma 20>, <&adma 20>;
421dc94a94dSSameer Pujar					dma-names = "rx1", "tx1",
422dc94a94dSSameer Pujar						    "rx2", "tx2",
423dc94a94dSSameer Pujar						    "rx3", "tx3",
424dc94a94dSSameer Pujar						    "rx4", "tx4",
425dc94a94dSSameer Pujar						    "rx5", "tx5",
426dc94a94dSSameer Pujar						    "rx6", "tx6",
427dc94a94dSSameer Pujar						    "rx7", "tx7",
428dc94a94dSSameer Pujar						    "rx8", "tx8",
429dc94a94dSSameer Pujar						    "rx9", "tx9",
430dc94a94dSSameer Pujar						    "rx10", "tx10",
431dc94a94dSSameer Pujar						    "rx11", "tx11",
432dc94a94dSSameer Pujar						    "rx12", "tx12",
433dc94a94dSSameer Pujar						    "rx13", "tx13",
434dc94a94dSSameer Pujar						    "rx14", "tx14",
435dc94a94dSSameer Pujar						    "rx15", "tx15",
436dc94a94dSSameer Pujar						    "rx16", "tx16",
437dc94a94dSSameer Pujar						    "rx17", "tx17",
438dc94a94dSSameer Pujar						    "rx18", "tx18",
439dc94a94dSSameer Pujar						    "rx19", "tx19",
440dc94a94dSSameer Pujar						    "rx20", "tx20";
441dc94a94dSSameer Pujar					interconnects = <&mc TEGRA234_MEMORY_CLIENT_APEDMAR &emc>,
442dc94a94dSSameer Pujar							<&mc TEGRA234_MEMORY_CLIENT_APEDMAW &emc>;
443dc94a94dSSameer Pujar					interconnect-names = "dma-mem", "write";
444dc94a94dSSameer Pujar					iommus = <&smmu_niso0 TEGRA234_SID_APE>;
445dc94a94dSSameer Pujar					status = "disabled";
446dc94a94dSSameer Pujar				};
44747a08153SSameer Pujar
44847a08153SSameer Pujar				tegra_asrc: asrc@2910000 {
44947a08153SSameer Pujar					compatible = "nvidia,tegra234-asrc",
45047a08153SSameer Pujar						     "nvidia,tegra186-asrc";
45147a08153SSameer Pujar					reg = <0x2910000 0x2000>;
45247a08153SSameer Pujar					sound-name-prefix = "ASRC1";
45347a08153SSameer Pujar					status = "disabled";
45447a08153SSameer Pujar				};
455dc94a94dSSameer Pujar			};
456dc94a94dSSameer Pujar
457dc94a94dSSameer Pujar			adma: dma-controller@2930000 {
458dc94a94dSSameer Pujar				compatible = "nvidia,tegra234-adma",
459dc94a94dSSameer Pujar					     "nvidia,tegra186-adma";
460dc94a94dSSameer Pujar				reg = <0x02930000 0x20000>;
461dc94a94dSSameer Pujar				interrupt-parent = <&agic>;
462dc94a94dSSameer Pujar				interrupts =  <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
463dc94a94dSSameer Pujar					      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
464dc94a94dSSameer Pujar					      <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
465dc94a94dSSameer Pujar					      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
466dc94a94dSSameer Pujar					      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
467dc94a94dSSameer Pujar					      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
468dc94a94dSSameer Pujar					      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
469dc94a94dSSameer Pujar					      <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
470dc94a94dSSameer Pujar					      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
471dc94a94dSSameer Pujar					      <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
472dc94a94dSSameer Pujar					      <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
473dc94a94dSSameer Pujar					      <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
474dc94a94dSSameer Pujar					      <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
475dc94a94dSSameer Pujar					      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
476dc94a94dSSameer Pujar					      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
477dc94a94dSSameer Pujar					      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
478dc94a94dSSameer Pujar					      <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
479dc94a94dSSameer Pujar					      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
480dc94a94dSSameer Pujar					      <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
481dc94a94dSSameer Pujar					      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
482dc94a94dSSameer Pujar					      <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
483dc94a94dSSameer Pujar					      <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
484dc94a94dSSameer Pujar					      <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
485dc94a94dSSameer Pujar					      <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
486dc94a94dSSameer Pujar					      <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
487dc94a94dSSameer Pujar					      <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
488dc94a94dSSameer Pujar					      <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
489dc94a94dSSameer Pujar					      <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
490dc94a94dSSameer Pujar					      <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
491dc94a94dSSameer Pujar					      <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
492dc94a94dSSameer Pujar					      <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
493dc94a94dSSameer Pujar					      <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
494dc94a94dSSameer Pujar				#dma-cells = <1>;
495dc94a94dSSameer Pujar				clocks = <&bpmp TEGRA234_CLK_AHUB>;
496dc94a94dSSameer Pujar				clock-names = "d_audio";
497dc94a94dSSameer Pujar				status = "disabled";
498dc94a94dSSameer Pujar			};
499dc94a94dSSameer Pujar
500dc94a94dSSameer Pujar			agic: interrupt-controller@2a40000 {
501dc94a94dSSameer Pujar				compatible = "nvidia,tegra234-agic",
502dc94a94dSSameer Pujar					     "nvidia,tegra210-agic";
503dc94a94dSSameer Pujar				#interrupt-cells = <3>;
504dc94a94dSSameer Pujar				interrupt-controller;
505dc94a94dSSameer Pujar				reg = <0x02a41000 0x1000>,
506dc94a94dSSameer Pujar				      <0x02a42000 0x2000>;
507dc94a94dSSameer Pujar				interrupts = <GIC_SPI 145
508dc94a94dSSameer Pujar					      (GIC_CPU_MASK_SIMPLE(4) |
509dc94a94dSSameer Pujar					       IRQ_TYPE_LEVEL_HIGH)>;
510dc94a94dSSameer Pujar				clocks = <&bpmp TEGRA234_CLK_APE>;
511dc94a94dSSameer Pujar				clock-names = "clk";
512dc94a94dSSameer Pujar				status = "disabled";
513dc94a94dSSameer Pujar			};
514dc94a94dSSameer Pujar		};
515dc94a94dSSameer Pujar
51663944891SThierry Reding		misc@100000 {
51763944891SThierry Reding			compatible = "nvidia,tegra234-misc";
51863944891SThierry Reding			reg = <0x00100000 0xf000>,
51963944891SThierry Reding			      <0x0010f000 0x1000>;
52063944891SThierry Reding			status = "okay";
52163944891SThierry Reding		};
52263944891SThierry Reding
52328d860edSKartik		timer@2080000 {
52428d860edSKartik			compatible = "nvidia,tegra234-timer";
52528d860edSKartik			reg = <0x02080000 0x00121000>;
52628d860edSKartik			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
52728d860edSKartik				     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
52828d860edSKartik				     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
52928d860edSKartik				     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
53028d860edSKartik				     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
53128d860edSKartik				     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
53228d860edSKartik				     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
53328d860edSKartik				     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
53428d860edSKartik				     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
53528d860edSKartik				     <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
53628d860edSKartik				     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
53728d860edSKartik				     <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
53828d860edSKartik				     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
53928d860edSKartik				     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
54028d860edSKartik				     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
54128d860edSKartik				     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
54228d860edSKartik			status = "okay";
54328d860edSKartik		};
54428d860edSKartik
5454bb39ca2SMikko Perttunen		host1x@13e00000 {
5464bb39ca2SMikko Perttunen			compatible = "nvidia,tegra234-host1x";
5474bb39ca2SMikko Perttunen			reg = <0x13e00000 0x10000>,
5484bb39ca2SMikko Perttunen			      <0x13e10000 0x10000>,
5494bb39ca2SMikko Perttunen			      <0x13e40000 0x10000>;
5504bb39ca2SMikko Perttunen			reg-names = "common", "hypervisor", "vm";
5514bb39ca2SMikko Perttunen			interrupts = <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
5524bb39ca2SMikko Perttunen				     <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
5534bb39ca2SMikko Perttunen				     <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
5544bb39ca2SMikko Perttunen				     <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
5554bb39ca2SMikko Perttunen				     <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
5564bb39ca2SMikko Perttunen				     <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>,
5574bb39ca2SMikko Perttunen				     <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>,
5584bb39ca2SMikko Perttunen				     <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
5594bb39ca2SMikko Perttunen				     <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
5604bb39ca2SMikko Perttunen			interrupt-names = "syncpt0", "syncpt1", "syncpt2", "syncpt3", "syncpt4",
5614bb39ca2SMikko Perttunen					  "syncpt5", "syncpt6", "syncpt7", "host1x";
5624bb39ca2SMikko Perttunen			clocks = <&bpmp TEGRA234_CLK_HOST1X>;
5634bb39ca2SMikko Perttunen			clock-names = "host1x";
5644bb39ca2SMikko Perttunen
5654bb39ca2SMikko Perttunen			#address-cells = <1>;
5664bb39ca2SMikko Perttunen			#size-cells = <1>;
5674bb39ca2SMikko Perttunen
568e25770feSMikko Perttunen			ranges = <0x14800000 0x14800000 0x02000000>;
5694bb39ca2SMikko Perttunen			interconnects = <&mc TEGRA234_MEMORY_CLIENT_HOST1XDMAR &emc>;
5704bb39ca2SMikko Perttunen			interconnect-names = "dma-mem";
5714bb39ca2SMikko Perttunen			iommus = <&smmu_niso1 TEGRA234_SID_HOST1X>;
5724bb39ca2SMikko Perttunen
573b35f5b53SMikko Perttunen			/* Context isolation domains */
574b35f5b53SMikko Perttunen			iommu-map = <0 &smmu_niso0 TEGRA234_SID_HOST1X_CTX0 1>,
575b35f5b53SMikko Perttunen				    <1 &smmu_niso0 TEGRA234_SID_HOST1X_CTX1 1>,
576b35f5b53SMikko Perttunen				    <2 &smmu_niso0 TEGRA234_SID_HOST1X_CTX2 1>,
577b35f5b53SMikko Perttunen				    <3 &smmu_niso0 TEGRA234_SID_HOST1X_CTX3 1>,
578b35f5b53SMikko Perttunen				    <4 &smmu_niso0 TEGRA234_SID_HOST1X_CTX4 1>,
579b35f5b53SMikko Perttunen				    <5 &smmu_niso0 TEGRA234_SID_HOST1X_CTX5 1>,
580b35f5b53SMikko Perttunen				    <6 &smmu_niso0 TEGRA234_SID_HOST1X_CTX6 1>,
581b35f5b53SMikko Perttunen				    <7 &smmu_niso0 TEGRA234_SID_HOST1X_CTX7 1>,
582b35f5b53SMikko Perttunen				    <8 &smmu_niso1 TEGRA234_SID_HOST1X_CTX0 1>,
583b35f5b53SMikko Perttunen				    <9 &smmu_niso1 TEGRA234_SID_HOST1X_CTX1 1>,
584b35f5b53SMikko Perttunen				    <10 &smmu_niso1 TEGRA234_SID_HOST1X_CTX2 1>,
585b35f5b53SMikko Perttunen				    <11 &smmu_niso1 TEGRA234_SID_HOST1X_CTX3 1>,
586b35f5b53SMikko Perttunen				    <12 &smmu_niso1 TEGRA234_SID_HOST1X_CTX4 1>,
587b35f5b53SMikko Perttunen				    <13 &smmu_niso1 TEGRA234_SID_HOST1X_CTX5 1>,
588b35f5b53SMikko Perttunen				    <14 &smmu_niso1 TEGRA234_SID_HOST1X_CTX6 1>,
589b35f5b53SMikko Perttunen				    <15 &smmu_niso1 TEGRA234_SID_HOST1X_CTX7 1>;
590b35f5b53SMikko Perttunen
5914bb39ca2SMikko Perttunen			vic@15340000 {
5924bb39ca2SMikko Perttunen				compatible = "nvidia,tegra234-vic";
5934bb39ca2SMikko Perttunen				reg = <0x15340000 0x00040000>;
5944bb39ca2SMikko Perttunen				interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
5954bb39ca2SMikko Perttunen				clocks = <&bpmp TEGRA234_CLK_VIC>;
5964bb39ca2SMikko Perttunen				clock-names = "vic";
5974bb39ca2SMikko Perttunen				resets = <&bpmp TEGRA234_RESET_VIC>;
5984bb39ca2SMikko Perttunen				reset-names = "vic";
5994bb39ca2SMikko Perttunen
6004bb39ca2SMikko Perttunen				power-domains = <&bpmp TEGRA234_POWER_DOMAIN_VIC>;
6014bb39ca2SMikko Perttunen				interconnects = <&mc TEGRA234_MEMORY_CLIENT_VICSRD &emc>,
6024bb39ca2SMikko Perttunen						<&mc TEGRA234_MEMORY_CLIENT_VICSWR &emc>;
6034bb39ca2SMikko Perttunen				interconnect-names = "dma-mem", "write";
6044bb39ca2SMikko Perttunen				iommus = <&smmu_niso1 TEGRA234_SID_VIC>;
6054bb39ca2SMikko Perttunen				dma-coherent;
6064bb39ca2SMikko Perttunen			};
60768c31ad0SMikko Perttunen
60868c31ad0SMikko Perttunen			nvdec@15480000 {
60968c31ad0SMikko Perttunen				compatible = "nvidia,tegra234-nvdec";
61068c31ad0SMikko Perttunen				reg = <0x15480000 0x00040000>;
61168c31ad0SMikko Perttunen				clocks = <&bpmp TEGRA234_CLK_NVDEC>,
61268c31ad0SMikko Perttunen					 <&bpmp TEGRA234_CLK_FUSE>,
61368c31ad0SMikko Perttunen					 <&bpmp TEGRA234_CLK_TSEC_PKA>;
61468c31ad0SMikko Perttunen				clock-names = "nvdec", "fuse", "tsec_pka";
61568c31ad0SMikko Perttunen				resets = <&bpmp TEGRA234_RESET_NVDEC>;
61668c31ad0SMikko Perttunen				reset-names = "nvdec";
61768c31ad0SMikko Perttunen				power-domains = <&bpmp TEGRA234_POWER_DOMAIN_NVDEC>;
61868c31ad0SMikko Perttunen				interconnects = <&mc TEGRA234_MEMORY_CLIENT_NVDECSRD &emc>,
61968c31ad0SMikko Perttunen						<&mc TEGRA234_MEMORY_CLIENT_NVDECSWR &emc>;
62068c31ad0SMikko Perttunen				interconnect-names = "dma-mem", "write";
62168c31ad0SMikko Perttunen				iommus = <&smmu_niso1 TEGRA234_SID_NVDEC>;
62268c31ad0SMikko Perttunen				dma-coherent;
62368c31ad0SMikko Perttunen
62468c31ad0SMikko Perttunen				nvidia,memory-controller = <&mc>;
62568c31ad0SMikko Perttunen
62668c31ad0SMikko Perttunen				/*
62768c31ad0SMikko Perttunen				 * Placeholder values that firmware needs to update with the real
62868c31ad0SMikko Perttunen				 * offsets parsed from the microcode headers.
62968c31ad0SMikko Perttunen				 */
63068c31ad0SMikko Perttunen				nvidia,bl-manifest-offset = <0>;
63168c31ad0SMikko Perttunen				nvidia,bl-data-offset = <0>;
63268c31ad0SMikko Perttunen				nvidia,bl-code-offset = <0>;
63368c31ad0SMikko Perttunen				nvidia,os-manifest-offset = <0>;
63468c31ad0SMikko Perttunen				nvidia,os-data-offset = <0>;
63568c31ad0SMikko Perttunen				nvidia,os-code-offset = <0>;
63668c31ad0SMikko Perttunen
63768c31ad0SMikko Perttunen				/*
63868c31ad0SMikko Perttunen				 * Firmware needs to set this to "okay" once the above values have
63968c31ad0SMikko Perttunen				 * been updated.
64068c31ad0SMikko Perttunen				 */
64168c31ad0SMikko Perttunen				status = "disabled";
64268c31ad0SMikko Perttunen			};
6434bb39ca2SMikko Perttunen		};
6444bb39ca2SMikko Perttunen
645f0e12668SThierry Reding		gpio: gpio@2200000 {
646f0e12668SThierry Reding			compatible = "nvidia,tegra234-gpio";
647f0e12668SThierry Reding			reg-names = "security", "gpio";
648f0e12668SThierry Reding			reg = <0x02200000 0x10000>,
649f0e12668SThierry Reding			      <0x02210000 0x10000>;
650f0e12668SThierry Reding			interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>,
651f0e12668SThierry Reding				     <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
652f0e12668SThierry Reding				     <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>,
653f0e12668SThierry Reding				     <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>,
654f0e12668SThierry Reding				     <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>,
655f0e12668SThierry Reding				     <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
656f0e12668SThierry Reding				     <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
657f0e12668SThierry Reding				     <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
658f0e12668SThierry Reding				     <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
659f0e12668SThierry Reding				     <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
660f0e12668SThierry Reding				     <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
661f0e12668SThierry Reding				     <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,
662f0e12668SThierry Reding				     <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
663f0e12668SThierry Reding				     <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
664f0e12668SThierry Reding				     <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
665f0e12668SThierry Reding				     <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
666f0e12668SThierry Reding				     <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
667f0e12668SThierry Reding				     <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
668f0e12668SThierry Reding				     <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
669f0e12668SThierry Reding				     <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
670f0e12668SThierry Reding				     <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
671f0e12668SThierry Reding				     <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
672f0e12668SThierry Reding				     <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
673f0e12668SThierry Reding				     <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
674f0e12668SThierry Reding				     <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
675f0e12668SThierry Reding				     <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
676f0e12668SThierry Reding				     <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
677f0e12668SThierry Reding				     <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
678f0e12668SThierry Reding				     <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
679f0e12668SThierry Reding				     <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
680f0e12668SThierry Reding				     <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
681f0e12668SThierry Reding				     <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
682f0e12668SThierry Reding				     <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
683f0e12668SThierry Reding				     <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
684f0e12668SThierry Reding				     <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
685f0e12668SThierry Reding				     <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
686f0e12668SThierry Reding				     <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
687f0e12668SThierry Reding				     <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
688f0e12668SThierry Reding				     <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
689f0e12668SThierry Reding				     <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
690f0e12668SThierry Reding				     <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
691f0e12668SThierry Reding				     <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
692f0e12668SThierry Reding				     <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
693f0e12668SThierry Reding				     <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
694f0e12668SThierry Reding				     <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
695f0e12668SThierry Reding				     <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
696f0e12668SThierry Reding				     <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
697f0e12668SThierry Reding				     <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
698f0e12668SThierry Reding			#interrupt-cells = <2>;
699f0e12668SThierry Reding			interrupt-controller;
700f0e12668SThierry Reding			#gpio-cells = <2>;
701f0e12668SThierry Reding			gpio-controller;
702f0e12668SThierry Reding		};
703f0e12668SThierry Reding
704eed280dfSThierry Reding		mc: memory-controller@2c00000 {
705eed280dfSThierry Reding			compatible = "nvidia,tegra234-mc";
706000b99e5SAshish Mhetre			reg = <0x02c00000 0x10000>,   /* MC-SID */
707000b99e5SAshish Mhetre			      <0x02c10000 0x10000>,   /* MC Broadcast*/
708000b99e5SAshish Mhetre			      <0x02c20000 0x10000>,   /* MC0 */
709000b99e5SAshish Mhetre			      <0x02c30000 0x10000>,   /* MC1 */
710000b99e5SAshish Mhetre			      <0x02c40000 0x10000>,   /* MC2 */
711000b99e5SAshish Mhetre			      <0x02c50000 0x10000>,   /* MC3 */
712000b99e5SAshish Mhetre			      <0x02b80000 0x10000>,   /* MC4 */
713000b99e5SAshish Mhetre			      <0x02b90000 0x10000>,   /* MC5 */
714000b99e5SAshish Mhetre			      <0x02ba0000 0x10000>,   /* MC6 */
715000b99e5SAshish Mhetre			      <0x02bb0000 0x10000>,   /* MC7 */
716000b99e5SAshish Mhetre			      <0x01700000 0x10000>,   /* MC8 */
717000b99e5SAshish Mhetre			      <0x01710000 0x10000>,   /* MC9 */
718000b99e5SAshish Mhetre			      <0x01720000 0x10000>,   /* MC10 */
719000b99e5SAshish Mhetre			      <0x01730000 0x10000>,   /* MC11 */
720000b99e5SAshish Mhetre			      <0x01740000 0x10000>,   /* MC12 */
721000b99e5SAshish Mhetre			      <0x01750000 0x10000>,   /* MC13 */
722000b99e5SAshish Mhetre			      <0x01760000 0x10000>,   /* MC14 */
723000b99e5SAshish Mhetre			      <0x01770000 0x10000>;   /* MC15 */
724000b99e5SAshish Mhetre			reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3",
725000b99e5SAshish Mhetre				    "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10",
726000b99e5SAshish Mhetre				    "ch11", "ch12", "ch13", "ch14", "ch15";
727eed280dfSThierry Reding			interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
728eed280dfSThierry Reding			#interconnect-cells = <1>;
729eed280dfSThierry Reding			status = "okay";
730eed280dfSThierry Reding
731eed280dfSThierry Reding			#address-cells = <2>;
732eed280dfSThierry Reding			#size-cells = <2>;
733eed280dfSThierry Reding
734eed280dfSThierry Reding			ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>,
735eed280dfSThierry Reding				 <0x02b80000 0x0 0x02b80000 0x0 0x040000>,
736eed280dfSThierry Reding				 <0x02c00000 0x0 0x02c00000 0x0 0x100000>;
737eed280dfSThierry Reding
738eed280dfSThierry Reding			/*
739eed280dfSThierry Reding			 * Bit 39 of addresses passing through the memory
740eed280dfSThierry Reding			 * controller selects the XBAR format used when memory
741eed280dfSThierry Reding			 * is accessed. This is used to transparently access
742eed280dfSThierry Reding			 * memory in the XBAR format used by the discrete GPU
743eed280dfSThierry Reding			 * (bit 39 set) or Tegra (bit 39 clear).
744eed280dfSThierry Reding			 *
745eed280dfSThierry Reding			 * As a consequence, the operating system must ensure
746eed280dfSThierry Reding			 * that bit 39 is never used implicitly, for example
747eed280dfSThierry Reding			 * via an I/O virtual address mapping of an IOMMU. If
748eed280dfSThierry Reding			 * devices require access to the XBAR switch, their
749eed280dfSThierry Reding			 * drivers must set this bit explicitly.
750eed280dfSThierry Reding			 *
751eed280dfSThierry Reding			 * Limit the DMA range for memory clients to [38:0].
752eed280dfSThierry Reding			 */
753eed280dfSThierry Reding			dma-ranges = <0x0 0x0 0x0 0x80 0x0>;
754eed280dfSThierry Reding
755eed280dfSThierry Reding			emc: external-memory-controller@2c60000 {
756eed280dfSThierry Reding				compatible = "nvidia,tegra234-emc";
757eed280dfSThierry Reding				reg = <0x0 0x02c60000 0x0 0x90000>,
758eed280dfSThierry Reding				      <0x0 0x01780000 0x0 0x80000>;
759eed280dfSThierry Reding				interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
760eed280dfSThierry Reding				clocks = <&bpmp TEGRA234_CLK_EMC>;
761eed280dfSThierry Reding				clock-names = "emc";
762eed280dfSThierry Reding				status = "okay";
763eed280dfSThierry Reding
764eed280dfSThierry Reding				#interconnect-cells = <0>;
765eed280dfSThierry Reding
766eed280dfSThierry Reding				nvidia,bpmp = <&bpmp>;
767eed280dfSThierry Reding			};
768eed280dfSThierry Reding		};
769eed280dfSThierry Reding
77063944891SThierry Reding		uarta: serial@3100000 {
77163944891SThierry Reding			compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart";
77263944891SThierry Reding			reg = <0x03100000 0x10000>;
77363944891SThierry Reding			interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
77463944891SThierry Reding			clocks = <&bpmp TEGRA234_CLK_UARTA>;
77563944891SThierry Reding			clock-names = "serial";
77663944891SThierry Reding			resets = <&bpmp TEGRA234_RESET_UARTA>;
77763944891SThierry Reding			reset-names = "serial";
77863944891SThierry Reding			status = "disabled";
77963944891SThierry Reding		};
78063944891SThierry Reding
781156af9deSAkhil R		gen1_i2c: i2c@3160000 {
782156af9deSAkhil R			compatible = "nvidia,tegra194-i2c";
783156af9deSAkhil R			reg = <0x3160000 0x100>;
784156af9deSAkhil R			status = "disabled";
785156af9deSAkhil R			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
786156af9deSAkhil R			clock-frequency = <400000>;
787156af9deSAkhil R			clocks = <&bpmp TEGRA234_CLK_I2C1
788156af9deSAkhil R				  &bpmp TEGRA234_CLK_PLLP_OUT0>;
789156af9deSAkhil R			assigned-clocks = <&bpmp TEGRA234_CLK_I2C1>;
790156af9deSAkhil R			assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
791156af9deSAkhil R			clock-names = "div-clk", "parent";
792156af9deSAkhil R			resets = <&bpmp TEGRA234_RESET_I2C1>;
793156af9deSAkhil R			reset-names = "i2c";
7948e442805SAkhil R			iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
7958e442805SAkhil R			dma-coherent;
7968e442805SAkhil R			dmas = <&gpcdma 21>, <&gpcdma 21>;
7978e442805SAkhil R			dma-names = "rx", "tx";
798156af9deSAkhil R		};
799156af9deSAkhil R
800156af9deSAkhil R		cam_i2c: i2c@3180000 {
801156af9deSAkhil R			compatible = "nvidia,tegra194-i2c";
802156af9deSAkhil R			reg = <0x3180000 0x100>;
803156af9deSAkhil R			interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
804156af9deSAkhil R			status = "disabled";
805156af9deSAkhil R			clock-frequency = <400000>;
806156af9deSAkhil R			clocks = <&bpmp TEGRA234_CLK_I2C3
807156af9deSAkhil R				&bpmp TEGRA234_CLK_PLLP_OUT0>;
808156af9deSAkhil R			assigned-clocks = <&bpmp TEGRA234_CLK_I2C3>;
809156af9deSAkhil R			assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
810156af9deSAkhil R			clock-names = "div-clk", "parent";
811156af9deSAkhil R			resets = <&bpmp TEGRA234_RESET_I2C3>;
812156af9deSAkhil R			reset-names = "i2c";
8138e442805SAkhil R			iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
8148e442805SAkhil R			dma-coherent;
8158e442805SAkhil R			dmas = <&gpcdma 23>, <&gpcdma 23>;
8168e442805SAkhil R			dma-names = "rx", "tx";
817156af9deSAkhil R		};
818156af9deSAkhil R
819156af9deSAkhil R		dp_aux_ch1_i2c: i2c@3190000 {
820156af9deSAkhil R			compatible = "nvidia,tegra194-i2c";
821156af9deSAkhil R			reg = <0x3190000 0x100>;
822156af9deSAkhil R			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
823156af9deSAkhil R			status = "disabled";
824156af9deSAkhil R			clock-frequency = <100000>;
825156af9deSAkhil R			clocks = <&bpmp TEGRA234_CLK_I2C4
826156af9deSAkhil R				&bpmp TEGRA234_CLK_PLLP_OUT0>;
827156af9deSAkhil R			assigned-clocks = <&bpmp TEGRA234_CLK_I2C4>;
828156af9deSAkhil R			assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
829156af9deSAkhil R			clock-names = "div-clk", "parent";
830156af9deSAkhil R			resets = <&bpmp TEGRA234_RESET_I2C4>;
831156af9deSAkhil R			reset-names = "i2c";
8328e442805SAkhil R			iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
8338e442805SAkhil R			dma-coherent;
8348e442805SAkhil R			dmas = <&gpcdma 26>, <&gpcdma 26>;
8358e442805SAkhil R			dma-names = "rx", "tx";
836156af9deSAkhil R		};
837156af9deSAkhil R
838156af9deSAkhil R		dp_aux_ch0_i2c: i2c@31b0000 {
839156af9deSAkhil R			compatible = "nvidia,tegra194-i2c";
840156af9deSAkhil R			reg = <0x31b0000 0x100>;
841156af9deSAkhil R			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
842156af9deSAkhil R			status = "disabled";
843156af9deSAkhil R			clock-frequency = <100000>;
844156af9deSAkhil R			clocks = <&bpmp TEGRA234_CLK_I2C6
845156af9deSAkhil R				&bpmp TEGRA234_CLK_PLLP_OUT0>;
846156af9deSAkhil R			assigned-clocks = <&bpmp TEGRA234_CLK_I2C6>;
847156af9deSAkhil R			assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
848156af9deSAkhil R			clock-names = "div-clk", "parent";
849156af9deSAkhil R			resets = <&bpmp TEGRA234_RESET_I2C6>;
850156af9deSAkhil R			reset-names = "i2c";
8518e442805SAkhil R			iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
8528e442805SAkhil R			dma-coherent;
8538e442805SAkhil R			dmas = <&gpcdma 30>, <&gpcdma 30>;
8548e442805SAkhil R			dma-names = "rx", "tx";
855156af9deSAkhil R		};
856156af9deSAkhil R
857156af9deSAkhil R		dp_aux_ch2_i2c: i2c@31c0000 {
858156af9deSAkhil R			compatible = "nvidia,tegra194-i2c";
859156af9deSAkhil R			reg = <0x31c0000 0x100>;
860156af9deSAkhil R			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
861156af9deSAkhil R			status = "disabled";
862156af9deSAkhil R			clock-frequency = <100000>;
863156af9deSAkhil R			clocks = <&bpmp TEGRA234_CLK_I2C7
864156af9deSAkhil R				&bpmp TEGRA234_CLK_PLLP_OUT0>;
865156af9deSAkhil R			assigned-clocks = <&bpmp TEGRA234_CLK_I2C7>;
866156af9deSAkhil R			assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
867156af9deSAkhil R			clock-names = "div-clk", "parent";
868156af9deSAkhil R			resets = <&bpmp TEGRA234_RESET_I2C7>;
869156af9deSAkhil R			reset-names = "i2c";
8708e442805SAkhil R			iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
8718e442805SAkhil R			dma-coherent;
8728e442805SAkhil R			dmas = <&gpcdma 27>, <&gpcdma 27>;
8738e442805SAkhil R			dma-names = "rx", "tx";
874156af9deSAkhil R		};
875156af9deSAkhil R
8761bbba854SJon Hunter		uarti: serial@31d0000 {
8771bbba854SJon Hunter			compatible = "arm,sbsa-uart";
8781bbba854SJon Hunter			reg = <0x31d0000 0x10000>;
8791bbba854SJon Hunter			interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
8801bbba854SJon Hunter			status = "disabled";
8811bbba854SJon Hunter		};
8821bbba854SJon Hunter
883156af9deSAkhil R		dp_aux_ch3_i2c: i2c@31e0000 {
884156af9deSAkhil R			compatible = "nvidia,tegra194-i2c";
885156af9deSAkhil R			reg = <0x31e0000 0x100>;
886156af9deSAkhil R			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
887156af9deSAkhil R			status = "disabled";
888156af9deSAkhil R			clock-frequency = <100000>;
889156af9deSAkhil R			clocks = <&bpmp TEGRA234_CLK_I2C9
890156af9deSAkhil R				&bpmp TEGRA234_CLK_PLLP_OUT0>;
891156af9deSAkhil R			assigned-clocks = <&bpmp TEGRA234_CLK_I2C9>;
892156af9deSAkhil R			assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
893156af9deSAkhil R			clock-names = "div-clk", "parent";
894156af9deSAkhil R			resets = <&bpmp TEGRA234_RESET_I2C9>;
895156af9deSAkhil R			reset-names = "i2c";
8968e442805SAkhil R			iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
8978e442805SAkhil R			dma-coherent;
8988e442805SAkhil R			dmas = <&gpcdma 31>, <&gpcdma 31>;
8998e442805SAkhil R			dma-names = "rx", "tx";
900156af9deSAkhil R		};
901156af9deSAkhil R
90271f69ffaSAshish Singhal		spi@3270000 {
90371f69ffaSAshish Singhal			compatible = "nvidia,tegra234-qspi";
90471f69ffaSAshish Singhal			reg = <0x3270000 0x1000>;
90571f69ffaSAshish Singhal			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
90671f69ffaSAshish Singhal			#address-cells = <1>;
90771f69ffaSAshish Singhal			#size-cells = <0>;
90871f69ffaSAshish Singhal			clocks = <&bpmp TEGRA234_CLK_QSPI0_2X_PM>,
90971f69ffaSAshish Singhal				 <&bpmp TEGRA234_CLK_QSPI0_PM>;
91071f69ffaSAshish Singhal			clock-names = "qspi", "qspi_out";
91171f69ffaSAshish Singhal			resets = <&bpmp TEGRA234_RESET_QSPI0>;
91271f69ffaSAshish Singhal			reset-names = "qspi";
91371f69ffaSAshish Singhal			status = "disabled";
91471f69ffaSAshish Singhal		};
91571f69ffaSAshish Singhal
9165e69088dSAkhil R		pwm1: pwm@3280000 {
9172566d28cSJon Hunter			compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
9185e69088dSAkhil R			reg = <0x3280000 0x10000>;
9195e69088dSAkhil R			clocks = <&bpmp TEGRA234_CLK_PWM1>;
9205e69088dSAkhil R			resets = <&bpmp TEGRA234_RESET_PWM1>;
9215e69088dSAkhil R			reset-names = "pwm";
9225e69088dSAkhil R			status = "disabled";
9235e69088dSAkhil R			#pwm-cells = <2>;
9245e69088dSAkhil R		};
9255e69088dSAkhil R
9262566d28cSJon Hunter		pwm2: pwm@3290000 {
9272566d28cSJon Hunter			compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
9282566d28cSJon Hunter			reg = <0x3290000 0x10000>;
9292566d28cSJon Hunter			clocks = <&bpmp TEGRA234_CLK_PWM2>;
9302566d28cSJon Hunter			resets = <&bpmp TEGRA234_RESET_PWM2>;
9312566d28cSJon Hunter			reset-names = "pwm";
9322566d28cSJon Hunter			status = "disabled";
9332566d28cSJon Hunter			#pwm-cells = <2>;
9342566d28cSJon Hunter		};
9352566d28cSJon Hunter
9362566d28cSJon Hunter		pwm3: pwm@32a0000 {
9372566d28cSJon Hunter			compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
9382566d28cSJon Hunter			reg = <0x32a0000 0x10000>;
9392566d28cSJon Hunter			clocks = <&bpmp TEGRA234_CLK_PWM3>;
9402566d28cSJon Hunter			resets = <&bpmp TEGRA234_RESET_PWM3>;
9412566d28cSJon Hunter			reset-names = "pwm";
9422566d28cSJon Hunter			status = "disabled";
9432566d28cSJon Hunter			#pwm-cells = <2>;
9442566d28cSJon Hunter		};
9452566d28cSJon Hunter
9462566d28cSJon Hunter		pwm5: pwm@32c0000 {
9472566d28cSJon Hunter			compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
9482566d28cSJon Hunter			reg = <0x32c0000 0x10000>;
9492566d28cSJon Hunter			clocks = <&bpmp TEGRA234_CLK_PWM5>;
9502566d28cSJon Hunter			resets = <&bpmp TEGRA234_RESET_PWM5>;
9512566d28cSJon Hunter			reset-names = "pwm";
9522566d28cSJon Hunter			status = "disabled";
9532566d28cSJon Hunter			#pwm-cells = <2>;
9542566d28cSJon Hunter		};
9552566d28cSJon Hunter
9562566d28cSJon Hunter		pwm6: pwm@32d0000 {
9572566d28cSJon Hunter			compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
9582566d28cSJon Hunter			reg = <0x32d0000 0x10000>;
9592566d28cSJon Hunter			clocks = <&bpmp TEGRA234_CLK_PWM6>;
9602566d28cSJon Hunter			resets = <&bpmp TEGRA234_RESET_PWM6>;
9612566d28cSJon Hunter			reset-names = "pwm";
9622566d28cSJon Hunter			status = "disabled";
9632566d28cSJon Hunter			#pwm-cells = <2>;
9642566d28cSJon Hunter		};
9652566d28cSJon Hunter
9662566d28cSJon Hunter		pwm7: pwm@32e0000 {
9672566d28cSJon Hunter			compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
9682566d28cSJon Hunter			reg = <0x32e0000 0x10000>;
9692566d28cSJon Hunter			clocks = <&bpmp TEGRA234_CLK_PWM7>;
9702566d28cSJon Hunter			resets = <&bpmp TEGRA234_RESET_PWM7>;
9712566d28cSJon Hunter			reset-names = "pwm";
9722566d28cSJon Hunter			status = "disabled";
9732566d28cSJon Hunter			#pwm-cells = <2>;
9742566d28cSJon Hunter		};
9752566d28cSJon Hunter
9762566d28cSJon Hunter		pwm8: pwm@32f0000 {
9772566d28cSJon Hunter			compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
9782566d28cSJon Hunter			reg = <0x32f0000 0x10000>;
9792566d28cSJon Hunter			clocks = <&bpmp TEGRA234_CLK_PWM8>;
9802566d28cSJon Hunter			resets = <&bpmp TEGRA234_RESET_PWM8>;
9812566d28cSJon Hunter			reset-names = "pwm";
9822566d28cSJon Hunter			status = "disabled";
9832566d28cSJon Hunter			#pwm-cells = <2>;
9842566d28cSJon Hunter		};
9852566d28cSJon Hunter
98671f69ffaSAshish Singhal		spi@3300000 {
98771f69ffaSAshish Singhal			compatible = "nvidia,tegra234-qspi";
98871f69ffaSAshish Singhal			reg = <0x3300000 0x1000>;
98971f69ffaSAshish Singhal			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
99071f69ffaSAshish Singhal			#address-cells = <1>;
99171f69ffaSAshish Singhal			#size-cells = <0>;
99271f69ffaSAshish Singhal			clocks = <&bpmp TEGRA234_CLK_QSPI1_2X_PM>,
99371f69ffaSAshish Singhal				 <&bpmp TEGRA234_CLK_QSPI1_PM>;
99471f69ffaSAshish Singhal			clock-names = "qspi", "qspi_out";
99571f69ffaSAshish Singhal			resets = <&bpmp TEGRA234_RESET_QSPI1>;
99671f69ffaSAshish Singhal			reset-names = "qspi";
99771f69ffaSAshish Singhal			status = "disabled";
99871f69ffaSAshish Singhal		};
99971f69ffaSAshish Singhal
1000d71b893aSPrathamesh Shete		mmc@3400000 {
1001d71b893aSPrathamesh Shete			compatible = "nvidia,tegra194-sdhci", "nvidia,tegra234-sdhci";
1002d71b893aSPrathamesh Shete			reg = <0x03400000 0x20000>;
1003d71b893aSPrathamesh Shete			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1004d71b893aSPrathamesh Shete			clocks = <&bpmp TEGRA234_CLK_SDMMC1>,
1005d71b893aSPrathamesh Shete				 <&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>;
1006d71b893aSPrathamesh Shete			clock-names = "sdhci", "tmclk";
1007d71b893aSPrathamesh Shete			assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC1>,
1008d71b893aSPrathamesh Shete					  <&bpmp TEGRA234_CLK_PLLC4_MUXED>;
1009d71b893aSPrathamesh Shete			assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4_MUXED>,
1010d71b893aSPrathamesh Shete						 <&bpmp TEGRA234_CLK_PLLC4_VCO_DIV2>;
1011d71b893aSPrathamesh Shete			resets = <&bpmp TEGRA234_RESET_SDMMC1>;
1012d71b893aSPrathamesh Shete			reset-names = "sdhci";
1013d71b893aSPrathamesh Shete			interconnects = <&mc TEGRA234_MEMORY_CLIENT_SDMMCRA &emc>,
1014d71b893aSPrathamesh Shete					<&mc TEGRA234_MEMORY_CLIENT_SDMMCWA &emc>;
1015d71b893aSPrathamesh Shete			interconnect-names = "dma-mem", "write";
1016d71b893aSPrathamesh Shete			iommus = <&smmu_niso1 TEGRA234_SID_SDMMC1A>;
1017d71b893aSPrathamesh Shete			pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
1018d71b893aSPrathamesh Shete			pinctrl-0 = <&sdmmc1_3v3>;
1019d71b893aSPrathamesh Shete			pinctrl-1 = <&sdmmc1_1v8>;
1020d71b893aSPrathamesh Shete			nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
1021d71b893aSPrathamesh Shete			nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x07>;
1022d71b893aSPrathamesh Shete			nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
1023d71b893aSPrathamesh Shete			nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
1024d71b893aSPrathamesh Shete			nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
1025d71b893aSPrathamesh Shete			nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
1026d71b893aSPrathamesh Shete			nvidia,default-tap = <14>;
1027d71b893aSPrathamesh Shete			nvidia,default-trim = <0x8>;
1028d71b893aSPrathamesh Shete			sd-uhs-sdr25;
1029d71b893aSPrathamesh Shete			sd-uhs-sdr50;
1030d71b893aSPrathamesh Shete			sd-uhs-ddr50;
1031d71b893aSPrathamesh Shete			sd-uhs-sdr104;
1032d71b893aSPrathamesh Shete			status = "disabled";
1033d71b893aSPrathamesh Shete		};
1034d71b893aSPrathamesh Shete
103563944891SThierry Reding		mmc@3460000 {
103663944891SThierry Reding			compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci";
103763944891SThierry Reding			reg = <0x03460000 0x20000>;
103863944891SThierry Reding			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
1039e086d82dSMikko Perttunen			clocks = <&bpmp TEGRA234_CLK_SDMMC4>,
1040e086d82dSMikko Perttunen				 <&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>;
1041e086d82dSMikko Perttunen			clock-names = "sdhci", "tmclk";
1042e086d82dSMikko Perttunen			assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC4>,
1043e086d82dSMikko Perttunen					  <&bpmp TEGRA234_CLK_PLLC4>;
1044e086d82dSMikko Perttunen			assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4>;
104563944891SThierry Reding			resets = <&bpmp TEGRA234_RESET_SDMMC4>;
104663944891SThierry Reding			reset-names = "sdhci";
10476de481e5SThierry Reding			interconnects = <&mc TEGRA234_MEMORY_CLIENT_SDMMCRAB &emc>,
10486de481e5SThierry Reding					<&mc TEGRA234_MEMORY_CLIENT_SDMMCWAB &emc>;
10496de481e5SThierry Reding			interconnect-names = "dma-mem", "write";
10505710e16aSThierry Reding			iommus = <&smmu_niso1 TEGRA234_SID_SDMMC4>;
1051e086d82dSMikko Perttunen			nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>;
1052e086d82dSMikko Perttunen			nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>;
1053e086d82dSMikko Perttunen			nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
1054e086d82dSMikko Perttunen			nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>;
1055e086d82dSMikko Perttunen			nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
1056e086d82dSMikko Perttunen			nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>;
1057e086d82dSMikko Perttunen			nvidia,default-tap = <0x8>;
1058e086d82dSMikko Perttunen			nvidia,default-trim = <0x14>;
1059e086d82dSMikko Perttunen			nvidia,dqs-trim = <40>;
1060e086d82dSMikko Perttunen			supports-cqe;
106163944891SThierry Reding			status = "disabled";
106263944891SThierry Reding		};
106363944891SThierry Reding
1064621e12a1SMohan Kumar		hda@3510000 {
1065621e12a1SMohan Kumar			compatible = "nvidia,tegra234-hda", "nvidia,tegra30-hda";
1066621e12a1SMohan Kumar			reg = <0x3510000 0x10000>;
1067621e12a1SMohan Kumar			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
1068621e12a1SMohan Kumar			clocks = <&bpmp TEGRA234_CLK_AZA_BIT>,
1069621e12a1SMohan Kumar				 <&bpmp TEGRA234_CLK_AZA_2XBIT>;
1070621e12a1SMohan Kumar			clock-names = "hda", "hda2codec_2x";
1071621e12a1SMohan Kumar			resets = <&bpmp TEGRA234_RESET_HDA>,
1072621e12a1SMohan Kumar				 <&bpmp TEGRA234_RESET_HDACODEC>;
1073621e12a1SMohan Kumar			reset-names = "hda", "hda2codec_2x";
1074621e12a1SMohan Kumar			power-domains = <&bpmp TEGRA234_POWER_DOMAIN_DISP>;
1075621e12a1SMohan Kumar			interconnects = <&mc TEGRA234_MEMORY_CLIENT_HDAR &emc>,
1076621e12a1SMohan Kumar					<&mc TEGRA234_MEMORY_CLIENT_HDAW &emc>;
1077621e12a1SMohan Kumar			interconnect-names = "dma-mem", "write";
1078af4c2773SMohan Kumar			iommus = <&smmu_niso0 TEGRA234_SID_HDA>;
1079621e12a1SMohan Kumar			status = "disabled";
1080621e12a1SMohan Kumar		};
1081621e12a1SMohan Kumar
108263944891SThierry Reding		fuse@3810000 {
108363944891SThierry Reding			compatible = "nvidia,tegra234-efuse";
108463944891SThierry Reding			reg = <0x03810000 0x10000>;
108563944891SThierry Reding			clocks = <&bpmp TEGRA234_CLK_FUSE>;
108663944891SThierry Reding			clock-names = "fuse";
108763944891SThierry Reding		};
108863944891SThierry Reding
108963944891SThierry Reding		hsp_top0: hsp@3c00000 {
109063944891SThierry Reding			compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp";
109163944891SThierry Reding			reg = <0x03c00000 0xa0000>;
109263944891SThierry Reding			interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
109363944891SThierry Reding				     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
109463944891SThierry Reding				     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
109563944891SThierry Reding				     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
109663944891SThierry Reding				     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
109763944891SThierry Reding				     <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
109863944891SThierry Reding				     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
109963944891SThierry Reding				     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
110063944891SThierry Reding				     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
110163944891SThierry Reding			interrupt-names = "doorbell", "shared0", "shared1", "shared2",
110263944891SThierry Reding					  "shared3", "shared4", "shared5", "shared6",
110363944891SThierry Reding					  "shared7";
110463944891SThierry Reding			#mbox-cells = <2>;
110563944891SThierry Reding		};
110663944891SThierry Reding
110778159542SThierry Reding		p2u_hsio_0: phy@3e00000 {
110878159542SThierry Reding			compatible = "nvidia,tegra234-p2u";
110978159542SThierry Reding			reg = <0x03e00000 0x10000>;
111078159542SThierry Reding			reg-names = "ctl";
111178159542SThierry Reding
111278159542SThierry Reding			#phy-cells = <0>;
111378159542SThierry Reding		};
111478159542SThierry Reding
111578159542SThierry Reding		p2u_hsio_1: phy@3e10000 {
111678159542SThierry Reding			compatible = "nvidia,tegra234-p2u";
111778159542SThierry Reding			reg = <0x03e10000 0x10000>;
111878159542SThierry Reding			reg-names = "ctl";
111978159542SThierry Reding
112078159542SThierry Reding			#phy-cells = <0>;
112178159542SThierry Reding		};
112278159542SThierry Reding
112378159542SThierry Reding		p2u_hsio_2: phy@3e20000 {
112478159542SThierry Reding			compatible = "nvidia,tegra234-p2u";
112578159542SThierry Reding			reg = <0x03e20000 0x10000>;
112678159542SThierry Reding			reg-names = "ctl";
112778159542SThierry Reding
112878159542SThierry Reding			#phy-cells = <0>;
112978159542SThierry Reding		};
113078159542SThierry Reding
113178159542SThierry Reding		p2u_hsio_3: phy@3e30000 {
113278159542SThierry Reding			compatible = "nvidia,tegra234-p2u";
113378159542SThierry Reding			reg = <0x03e30000 0x10000>;
113478159542SThierry Reding			reg-names = "ctl";
113578159542SThierry Reding
113678159542SThierry Reding			#phy-cells = <0>;
113778159542SThierry Reding		};
113878159542SThierry Reding
113978159542SThierry Reding		p2u_hsio_4: phy@3e40000 {
114078159542SThierry Reding			compatible = "nvidia,tegra234-p2u";
114178159542SThierry Reding			reg = <0x03e40000 0x10000>;
114278159542SThierry Reding			reg-names = "ctl";
114378159542SThierry Reding
114478159542SThierry Reding			#phy-cells = <0>;
114578159542SThierry Reding		};
114678159542SThierry Reding
114778159542SThierry Reding		p2u_hsio_5: phy@3e50000 {
114878159542SThierry Reding			compatible = "nvidia,tegra234-p2u";
114978159542SThierry Reding			reg = <0x03e50000 0x10000>;
115078159542SThierry Reding			reg-names = "ctl";
115178159542SThierry Reding
115278159542SThierry Reding			#phy-cells = <0>;
115378159542SThierry Reding		};
115478159542SThierry Reding
115578159542SThierry Reding		p2u_hsio_6: phy@3e60000 {
115678159542SThierry Reding			compatible = "nvidia,tegra234-p2u";
115778159542SThierry Reding			reg = <0x03e60000 0x10000>;
115878159542SThierry Reding			reg-names = "ctl";
115978159542SThierry Reding
116078159542SThierry Reding			#phy-cells = <0>;
116178159542SThierry Reding		};
116278159542SThierry Reding
116378159542SThierry Reding		p2u_hsio_7: phy@3e70000 {
116478159542SThierry Reding			compatible = "nvidia,tegra234-p2u";
116578159542SThierry Reding			reg = <0x03e70000 0x10000>;
116678159542SThierry Reding			reg-names = "ctl";
116778159542SThierry Reding
116878159542SThierry Reding			#phy-cells = <0>;
116978159542SThierry Reding		};
117078159542SThierry Reding
117178159542SThierry Reding		p2u_nvhs_0: phy@3e90000 {
117278159542SThierry Reding			compatible = "nvidia,tegra234-p2u";
117378159542SThierry Reding			reg = <0x03e90000 0x10000>;
117478159542SThierry Reding			reg-names = "ctl";
117578159542SThierry Reding
117678159542SThierry Reding			#phy-cells = <0>;
117778159542SThierry Reding		};
117878159542SThierry Reding
117978159542SThierry Reding		p2u_nvhs_1: phy@3ea0000 {
118078159542SThierry Reding			compatible = "nvidia,tegra234-p2u";
118178159542SThierry Reding			reg = <0x03ea0000 0x10000>;
118278159542SThierry Reding			reg-names = "ctl";
118378159542SThierry Reding
118478159542SThierry Reding			#phy-cells = <0>;
118578159542SThierry Reding		};
118678159542SThierry Reding
118778159542SThierry Reding		p2u_nvhs_2: phy@3eb0000 {
118878159542SThierry Reding			compatible = "nvidia,tegra234-p2u";
118978159542SThierry Reding			reg = <0x03eb0000 0x10000>;
119078159542SThierry Reding			reg-names = "ctl";
119178159542SThierry Reding
119278159542SThierry Reding			#phy-cells = <0>;
119378159542SThierry Reding		};
119478159542SThierry Reding
119578159542SThierry Reding		p2u_nvhs_3: phy@3ec0000 {
119678159542SThierry Reding			compatible = "nvidia,tegra234-p2u";
119778159542SThierry Reding			reg = <0x03ec0000 0x10000>;
119878159542SThierry Reding			reg-names = "ctl";
119978159542SThierry Reding
120078159542SThierry Reding			#phy-cells = <0>;
120178159542SThierry Reding		};
120278159542SThierry Reding
120378159542SThierry Reding		p2u_nvhs_4: phy@3ed0000 {
120478159542SThierry Reding			compatible = "nvidia,tegra234-p2u";
120578159542SThierry Reding			reg = <0x03ed0000 0x10000>;
120678159542SThierry Reding			reg-names = "ctl";
120778159542SThierry Reding
120878159542SThierry Reding			#phy-cells = <0>;
120978159542SThierry Reding		};
121078159542SThierry Reding
121178159542SThierry Reding		p2u_nvhs_5: phy@3ee0000 {
121278159542SThierry Reding			compatible = "nvidia,tegra234-p2u";
121378159542SThierry Reding			reg = <0x03ee0000 0x10000>;
121478159542SThierry Reding			reg-names = "ctl";
121578159542SThierry Reding
121678159542SThierry Reding			#phy-cells = <0>;
121778159542SThierry Reding		};
121878159542SThierry Reding
121978159542SThierry Reding		p2u_nvhs_6: phy@3ef0000 {
122078159542SThierry Reding			compatible = "nvidia,tegra234-p2u";
122178159542SThierry Reding			reg = <0x03ef0000 0x10000>;
122278159542SThierry Reding			reg-names = "ctl";
122378159542SThierry Reding
122478159542SThierry Reding			#phy-cells = <0>;
122578159542SThierry Reding		};
122678159542SThierry Reding
122778159542SThierry Reding		p2u_nvhs_7: phy@3f00000 {
122878159542SThierry Reding			compatible = "nvidia,tegra234-p2u";
122978159542SThierry Reding			reg = <0x03f00000 0x10000>;
123078159542SThierry Reding			reg-names = "ctl";
123178159542SThierry Reding
123278159542SThierry Reding			#phy-cells = <0>;
123378159542SThierry Reding		};
123478159542SThierry Reding
123578159542SThierry Reding		p2u_gbe_0: phy@3f20000 {
123678159542SThierry Reding			compatible = "nvidia,tegra234-p2u";
123778159542SThierry Reding			reg = <0x03f20000 0x10000>;
123878159542SThierry Reding			reg-names = "ctl";
123978159542SThierry Reding
124078159542SThierry Reding			#phy-cells = <0>;
124178159542SThierry Reding		};
124278159542SThierry Reding
124378159542SThierry Reding		p2u_gbe_1: phy@3f30000 {
124478159542SThierry Reding			compatible = "nvidia,tegra234-p2u";
124578159542SThierry Reding			reg = <0x03f30000 0x10000>;
124678159542SThierry Reding			reg-names = "ctl";
124778159542SThierry Reding
124878159542SThierry Reding			#phy-cells = <0>;
124978159542SThierry Reding		};
125078159542SThierry Reding
125178159542SThierry Reding		p2u_gbe_2: phy@3f40000 {
125278159542SThierry Reding			compatible = "nvidia,tegra234-p2u";
125378159542SThierry Reding			reg = <0x03f40000 0x10000>;
125478159542SThierry Reding			reg-names = "ctl";
125578159542SThierry Reding
125678159542SThierry Reding			#phy-cells = <0>;
125778159542SThierry Reding		};
125878159542SThierry Reding
125978159542SThierry Reding		p2u_gbe_3: phy@3f50000 {
126078159542SThierry Reding			compatible = "nvidia,tegra234-p2u";
126178159542SThierry Reding			reg = <0x03f50000 0x10000>;
126278159542SThierry Reding			reg-names = "ctl";
126378159542SThierry Reding
126478159542SThierry Reding			#phy-cells = <0>;
126578159542SThierry Reding		};
126678159542SThierry Reding
126778159542SThierry Reding		p2u_gbe_4: phy@3f60000 {
126878159542SThierry Reding			compatible = "nvidia,tegra234-p2u";
126978159542SThierry Reding			reg = <0x03f60000 0x10000>;
127078159542SThierry Reding			reg-names = "ctl";
127178159542SThierry Reding
127278159542SThierry Reding			#phy-cells = <0>;
127378159542SThierry Reding		};
127478159542SThierry Reding
127578159542SThierry Reding		p2u_gbe_5: phy@3f70000 {
127678159542SThierry Reding			compatible = "nvidia,tegra234-p2u";
127778159542SThierry Reding			reg = <0x03f70000 0x10000>;
127878159542SThierry Reding			reg-names = "ctl";
127978159542SThierry Reding
128078159542SThierry Reding			#phy-cells = <0>;
128178159542SThierry Reding		};
128278159542SThierry Reding
128378159542SThierry Reding		p2u_gbe_6: phy@3f80000 {
128478159542SThierry Reding			compatible = "nvidia,tegra234-p2u";
128578159542SThierry Reding			reg = <0x03f80000 0x10000>;
128678159542SThierry Reding			reg-names = "ctl";
128778159542SThierry Reding
128878159542SThierry Reding			#phy-cells = <0>;
128978159542SThierry Reding		};
129078159542SThierry Reding
129178159542SThierry Reding		p2u_gbe_7: phy@3f90000 {
129278159542SThierry Reding			compatible = "nvidia,tegra234-p2u";
129378159542SThierry Reding			reg = <0x03f90000 0x10000>;
129478159542SThierry Reding			reg-names = "ctl";
129578159542SThierry Reding
129678159542SThierry Reding			#phy-cells = <0>;
129778159542SThierry Reding		};
129878159542SThierry Reding
1299610cdf31SThierry Reding		ethernet@6800000 {
1300610cdf31SThierry Reding			compatible = "nvidia,tegra234-mgbe";
1301610cdf31SThierry Reding			reg = <0x06800000 0x10000>,
1302610cdf31SThierry Reding			      <0x06810000 0x10000>,
1303610cdf31SThierry Reding			      <0x068a0000 0x10000>;
1304610cdf31SThierry Reding			reg-names = "hypervisor", "mac", "xpcs";
1305610cdf31SThierry Reding			interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
1306610cdf31SThierry Reding			interrupt-names = "common";
1307610cdf31SThierry Reding			clocks = <&bpmp TEGRA234_CLK_MGBE0_APP>,
1308610cdf31SThierry Reding				 <&bpmp TEGRA234_CLK_MGBE0_MAC>,
1309610cdf31SThierry Reding				 <&bpmp TEGRA234_CLK_MGBE0_MAC_DIVIDER>,
1310610cdf31SThierry Reding				 <&bpmp TEGRA234_CLK_MGBE0_PTP_REF>,
1311610cdf31SThierry Reding				 <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT_M>,
1312610cdf31SThierry Reding				 <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT>,
1313610cdf31SThierry Reding				 <&bpmp TEGRA234_CLK_MGBE0_TX>,
1314610cdf31SThierry Reding				 <&bpmp TEGRA234_CLK_MGBE0_EEE_PCS>,
1315610cdf31SThierry Reding				 <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_INPUT>,
1316610cdf31SThierry Reding				 <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_M>,
1317610cdf31SThierry Reding				 <&bpmp TEGRA234_CLK_MGBE0_RX_PCS>,
1318610cdf31SThierry Reding				 <&bpmp TEGRA234_CLK_MGBE0_TX_PCS>;
1319610cdf31SThierry Reding			clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",
1320610cdf31SThierry Reding				      "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
1321610cdf31SThierry Reding				      "rx-pcs", "tx-pcs";
1322610cdf31SThierry Reding			resets = <&bpmp TEGRA234_RESET_MGBE0_MAC>,
1323610cdf31SThierry Reding				 <&bpmp TEGRA234_RESET_MGBE0_PCS>;
1324610cdf31SThierry Reding			reset-names = "mac", "pcs";
1325610cdf31SThierry Reding			interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEARD &emc>,
1326610cdf31SThierry Reding					<&mc TEGRA234_MEMORY_CLIENT_MGBEAWR &emc>;
1327610cdf31SThierry Reding			interconnect-names = "dma-mem", "write";
1328610cdf31SThierry Reding			iommus = <&smmu_niso0 TEGRA234_SID_MGBE>;
1329610cdf31SThierry Reding			power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEA>;
1330610cdf31SThierry Reding			status = "disabled";
1331610cdf31SThierry Reding		};
1332610cdf31SThierry Reding
1333610cdf31SThierry Reding		ethernet@6900000 {
1334610cdf31SThierry Reding			compatible = "nvidia,tegra234-mgbe";
1335610cdf31SThierry Reding			reg = <0x06900000 0x10000>,
1336610cdf31SThierry Reding			      <0x06910000 0x10000>,
1337610cdf31SThierry Reding			      <0x069a0000 0x10000>;
1338610cdf31SThierry Reding			reg-names = "hypervisor", "mac", "xpcs";
1339610cdf31SThierry Reding			interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>;
1340610cdf31SThierry Reding			interrupt-names = "common";
1341610cdf31SThierry Reding			clocks = <&bpmp TEGRA234_CLK_MGBE1_APP>,
1342610cdf31SThierry Reding				 <&bpmp TEGRA234_CLK_MGBE1_MAC>,
1343610cdf31SThierry Reding				 <&bpmp TEGRA234_CLK_MGBE1_MAC_DIVIDER>,
1344610cdf31SThierry Reding				 <&bpmp TEGRA234_CLK_MGBE1_PTP_REF>,
1345610cdf31SThierry Reding				 <&bpmp TEGRA234_CLK_MGBE1_RX_INPUT_M>,
1346610cdf31SThierry Reding				 <&bpmp TEGRA234_CLK_MGBE1_RX_INPUT>,
1347610cdf31SThierry Reding				 <&bpmp TEGRA234_CLK_MGBE1_TX>,
1348610cdf31SThierry Reding				 <&bpmp TEGRA234_CLK_MGBE1_EEE_PCS>,
1349610cdf31SThierry Reding				 <&bpmp TEGRA234_CLK_MGBE1_RX_PCS_INPUT>,
1350610cdf31SThierry Reding				 <&bpmp TEGRA234_CLK_MGBE1_RX_PCS_M>,
1351610cdf31SThierry Reding				 <&bpmp TEGRA234_CLK_MGBE1_RX_PCS>,
1352610cdf31SThierry Reding				 <&bpmp TEGRA234_CLK_MGBE1_TX_PCS>;
1353610cdf31SThierry Reding			clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",
1354610cdf31SThierry Reding				      "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
1355610cdf31SThierry Reding				      "rx-pcs", "tx-pcs";
1356610cdf31SThierry Reding			resets = <&bpmp TEGRA234_RESET_MGBE1_MAC>,
1357610cdf31SThierry Reding				 <&bpmp TEGRA234_RESET_MGBE1_PCS>;
1358610cdf31SThierry Reding			reset-names = "mac", "pcs";
1359610cdf31SThierry Reding			interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEBRD &emc>,
1360610cdf31SThierry Reding					<&mc TEGRA234_MEMORY_CLIENT_MGBEBWR &emc>;
1361610cdf31SThierry Reding			interconnect-names = "dma-mem", "write";
1362610cdf31SThierry Reding			iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF1>;
1363610cdf31SThierry Reding			power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEB>;
1364610cdf31SThierry Reding			status = "disabled";
1365610cdf31SThierry Reding		};
1366610cdf31SThierry Reding
1367610cdf31SThierry Reding		ethernet@6a00000 {
1368610cdf31SThierry Reding			compatible = "nvidia,tegra234-mgbe";
1369610cdf31SThierry Reding			reg = <0x06a00000 0x10000>,
1370610cdf31SThierry Reding			      <0x06a10000 0x10000>,
1371610cdf31SThierry Reding			      <0x06aa0000 0x10000>;
1372610cdf31SThierry Reding			reg-names = "hypervisor", "mac", "xpcs";
1373610cdf31SThierry Reding			interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>;
1374610cdf31SThierry Reding			interrupt-names = "common";
1375610cdf31SThierry Reding			clocks = <&bpmp TEGRA234_CLK_MGBE2_APP>,
1376610cdf31SThierry Reding				 <&bpmp TEGRA234_CLK_MGBE2_MAC>,
1377610cdf31SThierry Reding				 <&bpmp TEGRA234_CLK_MGBE2_MAC_DIVIDER>,
1378610cdf31SThierry Reding				 <&bpmp TEGRA234_CLK_MGBE2_PTP_REF>,
1379610cdf31SThierry Reding				 <&bpmp TEGRA234_CLK_MGBE2_RX_INPUT_M>,
1380610cdf31SThierry Reding				 <&bpmp TEGRA234_CLK_MGBE2_RX_INPUT>,
1381610cdf31SThierry Reding				 <&bpmp TEGRA234_CLK_MGBE2_TX>,
1382610cdf31SThierry Reding				 <&bpmp TEGRA234_CLK_MGBE2_EEE_PCS>,
1383610cdf31SThierry Reding				 <&bpmp TEGRA234_CLK_MGBE2_RX_PCS_INPUT>,
1384610cdf31SThierry Reding				 <&bpmp TEGRA234_CLK_MGBE2_RX_PCS_M>,
1385610cdf31SThierry Reding				 <&bpmp TEGRA234_CLK_MGBE2_RX_PCS>,
1386610cdf31SThierry Reding				 <&bpmp TEGRA234_CLK_MGBE2_TX_PCS>;
1387610cdf31SThierry Reding			clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",
1388610cdf31SThierry Reding				      "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
1389610cdf31SThierry Reding				      "rx-pcs", "tx-pcs";
1390610cdf31SThierry Reding			resets = <&bpmp TEGRA234_RESET_MGBE2_MAC>,
1391610cdf31SThierry Reding				 <&bpmp TEGRA234_RESET_MGBE2_PCS>;
1392610cdf31SThierry Reding			reset-names = "mac", "pcs";
1393610cdf31SThierry Reding			interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBECRD &emc>,
1394610cdf31SThierry Reding					<&mc TEGRA234_MEMORY_CLIENT_MGBECWR &emc>;
1395610cdf31SThierry Reding			interconnect-names = "dma-mem", "write";
1396610cdf31SThierry Reding			iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF2>;
1397610cdf31SThierry Reding			power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEC>;
1398610cdf31SThierry Reding			status = "disabled";
1399610cdf31SThierry Reding		};
1400610cdf31SThierry Reding
1401610cdf31SThierry Reding		ethernet@6b00000 {
1402610cdf31SThierry Reding			compatible = "nvidia,tegra234-mgbe";
1403610cdf31SThierry Reding			reg = <0x06b00000 0x10000>,
1404610cdf31SThierry Reding			      <0x06b10000 0x10000>,
1405610cdf31SThierry Reding			      <0x06ba0000 0x10000>;
1406610cdf31SThierry Reding			reg-names = "hypervisor", "mac", "xpcs";
1407610cdf31SThierry Reding			interrupts = <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
1408610cdf31SThierry Reding			interrupt-names = "common";
1409610cdf31SThierry Reding			clocks = <&bpmp TEGRA234_CLK_MGBE3_APP>,
1410610cdf31SThierry Reding				 <&bpmp TEGRA234_CLK_MGBE3_MAC>,
1411610cdf31SThierry Reding				 <&bpmp TEGRA234_CLK_MGBE3_MAC_DIVIDER>,
1412610cdf31SThierry Reding				 <&bpmp TEGRA234_CLK_MGBE3_PTP_REF>,
1413610cdf31SThierry Reding				 <&bpmp TEGRA234_CLK_MGBE3_RX_INPUT_M>,
1414610cdf31SThierry Reding				 <&bpmp TEGRA234_CLK_MGBE3_RX_INPUT>,
1415610cdf31SThierry Reding				 <&bpmp TEGRA234_CLK_MGBE3_TX>,
1416610cdf31SThierry Reding				 <&bpmp TEGRA234_CLK_MGBE3_EEE_PCS>,
1417610cdf31SThierry Reding				 <&bpmp TEGRA234_CLK_MGBE3_RX_PCS_INPUT>,
1418610cdf31SThierry Reding				 <&bpmp TEGRA234_CLK_MGBE3_RX_PCS_M>,
1419610cdf31SThierry Reding				 <&bpmp TEGRA234_CLK_MGBE3_RX_PCS>,
1420610cdf31SThierry Reding				 <&bpmp TEGRA234_CLK_MGBE3_TX_PCS>;
1421610cdf31SThierry Reding			clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",
1422610cdf31SThierry Reding				      "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
1423610cdf31SThierry Reding				      "rx-pcs", "tx-pcs";
1424610cdf31SThierry Reding			resets = <&bpmp TEGRA234_RESET_MGBE3_MAC>,
1425610cdf31SThierry Reding				 <&bpmp TEGRA234_RESET_MGBE3_PCS>;
1426610cdf31SThierry Reding			reset-names = "mac", "pcs";
1427610cdf31SThierry Reding			interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEDRD &emc>,
1428610cdf31SThierry Reding					<&mc TEGRA234_MEMORY_CLIENT_MGBEDWR &emc>;
1429610cdf31SThierry Reding			interconnect-names = "dma-mem", "write";
1430610cdf31SThierry Reding			iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF3>;
1431610cdf31SThierry Reding			power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBED>;
1432610cdf31SThierry Reding			status = "disabled";
1433610cdf31SThierry Reding		};
1434610cdf31SThierry Reding
14355710e16aSThierry Reding		smmu_niso1: iommu@8000000 {
14365710e16aSThierry Reding			compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500";
14375710e16aSThierry Reding			reg = <0x8000000 0x1000000>,
14385710e16aSThierry Reding			      <0x7000000 0x1000000>;
14395710e16aSThierry Reding			interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
14405710e16aSThierry Reding				     <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
14415710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
14425710e16aSThierry Reding				     <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
14435710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
14445710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
14455710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
14465710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
14475710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
14485710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
14495710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
14505710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
14515710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
14525710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
14535710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
14545710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
14555710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
14565710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
14575710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
14585710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
14595710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
14605710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
14615710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
14625710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
14635710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
14645710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
14655710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
14665710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
14675710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
14685710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
14695710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
14705710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
14715710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
14725710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
14735710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
14745710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
14755710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
14765710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
14775710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
14785710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
14795710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
14805710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
14815710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
14825710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
14835710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
14845710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
14855710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
14865710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
14875710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
14885710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
14895710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
14905710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
14915710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
14925710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
14935710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
14945710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
14955710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
14965710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
14975710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
14985710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
14995710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
15005710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
15015710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
15025710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
15035710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
15045710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
15055710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
15065710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
15075710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
15085710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
15095710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
15105710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
15115710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
15125710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
15135710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
15145710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
15155710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
15165710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
15175710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
15185710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
15195710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
15205710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
15215710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
15225710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
15235710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
15245710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
15255710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
15265710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
15275710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
15285710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
15295710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
15305710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
15315710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
15325710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
15335710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
15345710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
15355710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
15365710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
15375710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
15385710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
15395710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
15405710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
15415710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
15425710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
15435710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
15445710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
15455710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
15465710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
15475710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
15485710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
15495710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
15505710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
15515710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
15525710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
15535710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
15545710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
15555710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
15565710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
15575710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
15585710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
15595710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
15605710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
15615710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
15625710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
15635710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
15645710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
15655710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
15665710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
15675710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
15685710e16aSThierry Reding				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
15695710e16aSThierry Reding			stream-match-mask = <0x7f80>;
15705710e16aSThierry Reding			#global-interrupts = <2>;
15715710e16aSThierry Reding			#iommu-cells = <1>;
15725710e16aSThierry Reding
15735710e16aSThierry Reding			nvidia,memory-controller = <&mc>;
15745710e16aSThierry Reding			status = "okay";
15755710e16aSThierry Reding		};
15765710e16aSThierry Reding
1577302e1540SSumit Gupta		sce-fabric@b600000 {
1578302e1540SSumit Gupta			compatible = "nvidia,tegra234-sce-fabric";
1579302e1540SSumit Gupta			reg = <0xb600000 0x40000>;
1580302e1540SSumit Gupta			interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
1581302e1540SSumit Gupta			status = "okay";
1582302e1540SSumit Gupta		};
1583302e1540SSumit Gupta
1584302e1540SSumit Gupta		rce-fabric@be00000 {
1585302e1540SSumit Gupta			compatible = "nvidia,tegra234-rce-fabric";
1586302e1540SSumit Gupta			reg = <0xbe00000 0x40000>;
1587302e1540SSumit Gupta			interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
1588302e1540SSumit Gupta			status = "okay";
1589302e1540SSumit Gupta		};
1590302e1540SSumit Gupta
159163944891SThierry Reding		hsp_aon: hsp@c150000 {
159263944891SThierry Reding			compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp";
159363944891SThierry Reding			reg = <0x0c150000 0x90000>;
159463944891SThierry Reding			interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
159563944891SThierry Reding				     <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
159663944891SThierry Reding				     <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
159763944891SThierry Reding				     <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
159863944891SThierry Reding			/*
159963944891SThierry Reding			 * Shared interrupt 0 is routed only to AON/SPE, so
160063944891SThierry Reding			 * we only have 4 shared interrupts for the CCPLEX.
160163944891SThierry Reding			 */
160263944891SThierry Reding			interrupt-names = "shared1", "shared2", "shared3", "shared4";
160363944891SThierry Reding			#mbox-cells = <2>;
160463944891SThierry Reding		};
160563944891SThierry Reding
1606156af9deSAkhil R		gen2_i2c: i2c@c240000 {
1607156af9deSAkhil R			compatible = "nvidia,tegra194-i2c";
1608156af9deSAkhil R			reg = <0xc240000 0x100>;
1609156af9deSAkhil R			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1610156af9deSAkhil R			status = "disabled";
1611156af9deSAkhil R			clock-frequency = <100000>;
1612156af9deSAkhil R			clocks = <&bpmp TEGRA234_CLK_I2C2
1613156af9deSAkhil R				&bpmp TEGRA234_CLK_PLLP_OUT0>;
1614156af9deSAkhil R			clock-names = "div-clk", "parent";
1615156af9deSAkhil R			assigned-clocks = <&bpmp TEGRA234_CLK_I2C2>;
1616156af9deSAkhil R			assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
1617156af9deSAkhil R			resets = <&bpmp TEGRA234_RESET_I2C2>;
1618156af9deSAkhil R			reset-names = "i2c";
16198e442805SAkhil R			iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
16208e442805SAkhil R			dma-coherent;
16218e442805SAkhil R			dmas = <&gpcdma 22>, <&gpcdma 22>;
16228e442805SAkhil R			dma-names = "rx", "tx";
1623156af9deSAkhil R		};
1624156af9deSAkhil R
1625156af9deSAkhil R		gen8_i2c: i2c@c250000 {
1626156af9deSAkhil R			compatible = "nvidia,tegra194-i2c";
1627156af9deSAkhil R			reg = <0xc250000 0x100>;
1628156af9deSAkhil R			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1629156af9deSAkhil R			status = "disabled";
1630156af9deSAkhil R			clock-frequency = <400000>;
1631156af9deSAkhil R			clocks = <&bpmp TEGRA234_CLK_I2C8
1632156af9deSAkhil R				&bpmp TEGRA234_CLK_PLLP_OUT0>;
1633156af9deSAkhil R			clock-names = "div-clk", "parent";
1634156af9deSAkhil R			assigned-clocks = <&bpmp TEGRA234_CLK_I2C8>;
1635156af9deSAkhil R			assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
1636156af9deSAkhil R			resets = <&bpmp TEGRA234_RESET_I2C8>;
1637156af9deSAkhil R			reset-names = "i2c";
16388e442805SAkhil R			iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
16398e442805SAkhil R			dma-coherent;
16408e442805SAkhil R			dmas = <&gpcdma 0>, <&gpcdma 0>;
16418e442805SAkhil R			dma-names = "rx", "tx";
1642156af9deSAkhil R		};
1643156af9deSAkhil R
164463944891SThierry Reding		rtc@c2a0000 {
164563944891SThierry Reding			compatible = "nvidia,tegra234-rtc", "nvidia,tegra20-rtc";
164663944891SThierry Reding			reg = <0x0c2a0000 0x10000>;
164763944891SThierry Reding			interrupt-parent = <&pmc>;
164863944891SThierry Reding			interrupts = <73 IRQ_TYPE_LEVEL_HIGH>;
1649e537addeSMikko Perttunen			clocks = <&bpmp TEGRA234_CLK_CLK_32K>;
1650e537addeSMikko Perttunen			clock-names = "rtc";
165163944891SThierry Reding			status = "disabled";
165263944891SThierry Reding		};
165363944891SThierry Reding
1654f0e12668SThierry Reding		gpio_aon: gpio@c2f0000 {
1655f0e12668SThierry Reding			compatible = "nvidia,tegra234-gpio-aon";
1656f0e12668SThierry Reding			reg-names = "security", "gpio";
1657f0e12668SThierry Reding			reg = <0x0c2f0000 0x1000>,
1658f0e12668SThierry Reding			      <0x0c2f1000 0x1000>;
1659f0e12668SThierry Reding			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
1660f0e12668SThierry Reding				     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
1661f0e12668SThierry Reding				     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
1662f0e12668SThierry Reding				     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
1663f0e12668SThierry Reding			#interrupt-cells = <2>;
1664f0e12668SThierry Reding			interrupt-controller;
1665f0e12668SThierry Reding			#gpio-cells = <2>;
1666f0e12668SThierry Reding			gpio-controller;
1667f0e12668SThierry Reding		};
1668f0e12668SThierry Reding
16692566d28cSJon Hunter		pwm4: pwm@c340000 {
16702566d28cSJon Hunter			compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
16712566d28cSJon Hunter			reg = <0xc340000 0x10000>;
16722566d28cSJon Hunter			clocks = <&bpmp TEGRA234_CLK_PWM4>;
16732566d28cSJon Hunter			resets = <&bpmp TEGRA234_RESET_PWM4>;
16742566d28cSJon Hunter			reset-names = "pwm";
16752566d28cSJon Hunter			status = "disabled";
16762566d28cSJon Hunter			#pwm-cells = <2>;
16772566d28cSJon Hunter		};
16782566d28cSJon Hunter
167963944891SThierry Reding		pmc: pmc@c360000 {
168063944891SThierry Reding			compatible = "nvidia,tegra234-pmc";
168163944891SThierry Reding			reg = <0x0c360000 0x10000>,
168263944891SThierry Reding			      <0x0c370000 0x10000>,
168363944891SThierry Reding			      <0x0c380000 0x10000>,
168463944891SThierry Reding			      <0x0c390000 0x10000>,
168563944891SThierry Reding			      <0x0c3a0000 0x10000>;
168663944891SThierry Reding			reg-names = "pmc", "wake", "aotag", "scratch", "misc";
168763944891SThierry Reding
168863944891SThierry Reding			#interrupt-cells = <2>;
168963944891SThierry Reding			interrupt-controller;
1690d71b893aSPrathamesh Shete
1691d71b893aSPrathamesh Shete			sdmmc1_3v3: sdmmc1-3v3 {
1692d71b893aSPrathamesh Shete				pins = "sdmmc1-hv";
1693d71b893aSPrathamesh Shete				power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
1694d71b893aSPrathamesh Shete			};
1695d71b893aSPrathamesh Shete
1696d71b893aSPrathamesh Shete			sdmmc1_1v8: sdmmc1-1v8 {
1697d71b893aSPrathamesh Shete				pins = "sdmmc1-hv";
1698d71b893aSPrathamesh Shete				power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
1699d71b893aSPrathamesh Shete			};
1700d71b893aSPrathamesh Shete
1701d71b893aSPrathamesh Shete			sdmmc3_3v3: sdmmc3-3v3 {
1702d71b893aSPrathamesh Shete				pins = "sdmmc3-hv";
1703d71b893aSPrathamesh Shete				power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
1704d71b893aSPrathamesh Shete			};
1705d71b893aSPrathamesh Shete
1706d71b893aSPrathamesh Shete			sdmmc3_1v8: sdmmc3-1v8 {
1707d71b893aSPrathamesh Shete				pins = "sdmmc3-hv";
1708d71b893aSPrathamesh Shete				power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
1709d71b893aSPrathamesh Shete			};
171063944891SThierry Reding		};
171163944891SThierry Reding
1712302e1540SSumit Gupta		aon-fabric@c600000 {
1713302e1540SSumit Gupta			compatible = "nvidia,tegra234-aon-fabric";
1714302e1540SSumit Gupta			reg = <0xc600000 0x40000>;
1715302e1540SSumit Gupta			interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
1716302e1540SSumit Gupta			status = "okay";
1717302e1540SSumit Gupta		};
1718302e1540SSumit Gupta
1719302e1540SSumit Gupta		bpmp-fabric@d600000 {
1720302e1540SSumit Gupta			compatible = "nvidia,tegra234-bpmp-fabric";
1721302e1540SSumit Gupta			reg = <0xd600000 0x40000>;
1722302e1540SSumit Gupta			interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
1723302e1540SSumit Gupta			status = "okay";
1724302e1540SSumit Gupta		};
1725302e1540SSumit Gupta
1726302e1540SSumit Gupta		dce-fabric@de00000 {
1727302e1540SSumit Gupta			compatible = "nvidia,tegra234-sce-fabric";
1728302e1540SSumit Gupta			reg = <0xde00000 0x40000>;
1729302e1540SSumit Gupta			interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>;
1730302e1540SSumit Gupta			status = "okay";
1731302e1540SSumit Gupta		};
1732302e1540SSumit Gupta
173363944891SThierry Reding		gic: interrupt-controller@f400000 {
173463944891SThierry Reding			compatible = "arm,gic-v3";
173563944891SThierry Reding			reg = <0x0f400000 0x010000>, /* GICD */
173663944891SThierry Reding			      <0x0f440000 0x200000>; /* GICR */
173763944891SThierry Reding			interrupt-parent = <&gic>;
173863944891SThierry Reding			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
173963944891SThierry Reding
174063944891SThierry Reding			#redistributor-regions = <1>;
174163944891SThierry Reding			#interrupt-cells = <3>;
174263944891SThierry Reding			interrupt-controller;
174363944891SThierry Reding		};
17445710e16aSThierry Reding
17455710e16aSThierry Reding		smmu_iso: iommu@10000000 {
17465710e16aSThierry Reding			compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500";
17475710e16aSThierry Reding			reg = <0x10000000 0x1000000>;
17485710e16aSThierry Reding			interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
17495710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
17505710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
17515710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
17525710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
17535710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
17545710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
17555710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
17565710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
17575710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
17585710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
17595710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
17605710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
17615710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
17625710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
17635710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
17645710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
17655710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
17665710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
17675710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
17685710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
17695710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
17705710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
17715710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
17725710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
17735710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
17745710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
17755710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
17765710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
17775710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
17785710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
17795710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
17805710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
17815710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
17825710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
17835710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
17845710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
17855710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
17865710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
17875710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
17885710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
17895710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
17905710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
17915710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
17925710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
17935710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
17945710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
17955710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
17965710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
17975710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
17985710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
17995710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
18005710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
18015710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
18025710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
18035710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
18045710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
18055710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
18065710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
18075710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
18085710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
18095710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
18105710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
18115710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
18125710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
18135710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
18145710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
18155710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
18165710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
18175710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
18185710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
18195710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
18205710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
18215710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
18225710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
18235710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
18245710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
18255710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
18265710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
18275710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
18285710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
18295710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
18305710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
18315710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
18325710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
18335710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
18345710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
18355710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
18365710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
18375710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
18385710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
18395710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
18405710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
18415710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
18425710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
18435710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
18445710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
18455710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
18465710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
18475710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
18485710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
18495710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
18505710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
18515710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
18525710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
18535710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
18545710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
18555710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
18565710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
18575710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
18585710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
18595710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
18605710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
18615710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
18625710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
18635710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
18645710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
18655710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
18665710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
18675710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
18685710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
18695710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
18705710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
18715710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
18725710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
18735710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
18745710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
18755710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
18765710e16aSThierry Reding				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
18775710e16aSThierry Reding			stream-match-mask = <0x7f80>;
18785710e16aSThierry Reding			#global-interrupts = <1>;
18795710e16aSThierry Reding			#iommu-cells = <1>;
18805710e16aSThierry Reding
18815710e16aSThierry Reding			nvidia,memory-controller = <&mc>;
18825710e16aSThierry Reding			status = "okay";
18835710e16aSThierry Reding		};
18845710e16aSThierry Reding
18855710e16aSThierry Reding		smmu_niso0: iommu@12000000 {
18865710e16aSThierry Reding			compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500";
18875710e16aSThierry Reding			reg = <0x12000000 0x1000000>,
18885710e16aSThierry Reding			      <0x11000000 0x1000000>;
18895710e16aSThierry Reding			interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
18905710e16aSThierry Reding				     <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,
18915710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
18925710e16aSThierry Reding				     <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,
18935710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
18945710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
18955710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
18965710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
18975710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
18985710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
18995710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19005710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19015710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19025710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19035710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19045710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19055710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19065710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19075710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19085710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19095710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19105710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19115710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19125710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19135710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19145710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19155710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19165710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19175710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19185710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19195710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19205710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19215710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19225710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19235710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19245710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19255710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19265710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19275710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19285710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19295710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19305710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19315710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19325710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19335710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19345710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19355710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19365710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19375710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19385710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19395710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19405710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19415710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19425710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19435710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19445710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19455710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19465710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19475710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19485710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19495710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19505710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19515710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19525710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19535710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19545710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19555710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19565710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19575710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19585710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19595710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19605710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19615710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19625710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19635710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19645710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19655710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19665710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19675710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19685710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19695710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19705710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19715710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19725710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19735710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19745710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19755710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19765710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19775710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19785710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19795710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19805710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19815710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19825710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19835710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19845710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19855710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19865710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19875710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19885710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19895710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19905710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19915710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19925710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19935710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19945710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19955710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19965710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19975710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19985710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
19995710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
20005710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
20015710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
20025710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
20035710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
20045710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
20055710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
20065710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
20075710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
20085710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
20095710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
20105710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
20115710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
20125710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
20135710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
20145710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
20155710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
20165710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
20175710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
20185710e16aSThierry Reding				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
20195710e16aSThierry Reding			stream-match-mask = <0x7f80>;
20205710e16aSThierry Reding			#global-interrupts = <2>;
20215710e16aSThierry Reding			#iommu-cells = <1>;
20225710e16aSThierry Reding
20235710e16aSThierry Reding			nvidia,memory-controller = <&mc>;
20245710e16aSThierry Reding			status = "okay";
20255710e16aSThierry Reding		};
2026302e1540SSumit Gupta
2027302e1540SSumit Gupta		cbb-fabric@13a00000 {
2028302e1540SSumit Gupta			compatible = "nvidia,tegra234-cbb-fabric";
2029302e1540SSumit Gupta			reg = <0x13a00000 0x400000>;
2030302e1540SSumit Gupta			interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
2031302e1540SSumit Gupta			status = "okay";
2032302e1540SSumit Gupta		};
203363944891SThierry Reding	};
203463944891SThierry Reding
2035962c400dSSumit Gupta	ccplex@e000000 {
2036962c400dSSumit Gupta		compatible = "nvidia,tegra234-ccplex-cluster";
2037962c400dSSumit Gupta		reg = <0x0 0x0e000000 0x0 0x5ffff>;
2038962c400dSSumit Gupta		nvidia,bpmp = <&bpmp>;
2039962c400dSSumit Gupta		status = "okay";
2040962c400dSSumit Gupta	};
2041962c400dSSumit Gupta
2042ec142c44SVidya Sagar	pcie@140a0000 {
2043ec142c44SVidya Sagar		compatible = "nvidia,tegra234-pcie";
2044ec142c44SVidya Sagar		power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CA>;
2045ec142c44SVidya Sagar		reg = <0x00 0x140a0000 0x0 0x00020000>, /* appl registers (128K)      */
2046ec142c44SVidya Sagar		      <0x00 0x2a000000 0x0 0x00040000>, /* configuration space (256K) */
2047ec142c44SVidya Sagar		      <0x00 0x2a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
2048*794b834dSVidya Sagar		      <0x00 0x2a080000 0x0 0x00040000>, /* DBI reg space (256K)       */
2049*794b834dSVidya Sagar		      <0x35 0x30000000 0x0 0x10000000>; /* ECAM (256MB)               */
2050*794b834dSVidya Sagar		reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
2051ec142c44SVidya Sagar
2052ec142c44SVidya Sagar		#address-cells = <3>;
2053ec142c44SVidya Sagar		#size-cells = <2>;
2054ec142c44SVidya Sagar		device_type = "pci";
2055ec142c44SVidya Sagar		num-lanes = <4>;
2056ec142c44SVidya Sagar		num-viewport = <8>;
2057ec142c44SVidya Sagar		linux,pci-domain = <8>;
2058ec142c44SVidya Sagar
2059ec142c44SVidya Sagar		clocks = <&bpmp TEGRA234_CLK_PEX2_C8_CORE>;
2060ec142c44SVidya Sagar		clock-names = "core";
2061ec142c44SVidya Sagar
2062ec142c44SVidya Sagar		resets = <&bpmp TEGRA234_RESET_PEX2_CORE_8_APB>,
2063ec142c44SVidya Sagar			 <&bpmp TEGRA234_RESET_PEX2_CORE_8>;
2064ec142c44SVidya Sagar		reset-names = "apb", "core";
2065ec142c44SVidya Sagar
2066ec142c44SVidya Sagar		interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2067ec142c44SVidya Sagar			     <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2068ec142c44SVidya Sagar		interrupt-names = "intr", "msi";
2069ec142c44SVidya Sagar
2070ec142c44SVidya Sagar		#interrupt-cells = <1>;
2071ec142c44SVidya Sagar		interrupt-map-mask = <0 0 0 0>;
2072ec142c44SVidya Sagar		interrupt-map = <0 0 0 0 &gic GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
2073ec142c44SVidya Sagar
2074ec142c44SVidya Sagar		nvidia,bpmp = <&bpmp 8>;
2075ec142c44SVidya Sagar
2076ec142c44SVidya Sagar		nvidia,aspm-cmrt-us = <60>;
2077ec142c44SVidya Sagar		nvidia,aspm-pwr-on-t-us = <20>;
2078ec142c44SVidya Sagar		nvidia,aspm-l0s-entrance-latency-us = <3>;
2079ec142c44SVidya Sagar
2080ec142c44SVidya Sagar		bus-range = <0x0 0xff>;
2081ec142c44SVidya Sagar
2082ec142c44SVidya Sagar		ranges = <0x43000000 0x32 0x40000000 0x32 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */
2083ec142c44SVidya Sagar			 <0x02000000 0x0  0x40000000 0x35 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2084ec142c44SVidya Sagar			 <0x01000000 0x0  0x2a100000 0x00 0x2a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
2085ec142c44SVidya Sagar
2086ec142c44SVidya Sagar		interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE8AR &emc>,
2087ec142c44SVidya Sagar				<&mc TEGRA234_MEMORY_CLIENT_PCIE8AW &emc>;
2088ec142c44SVidya Sagar		interconnect-names = "dma-mem", "write";
2089ec142c44SVidya Sagar		iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE8 0x1000>;
2090ec142c44SVidya Sagar		iommu-map-mask = <0x0>;
2091ec142c44SVidya Sagar		dma-coherent;
2092ec142c44SVidya Sagar
2093ec142c44SVidya Sagar		status = "disabled";
2094ec142c44SVidya Sagar	};
2095ec142c44SVidya Sagar
2096ec142c44SVidya Sagar	pcie@140c0000 {
2097ec142c44SVidya Sagar		compatible = "nvidia,tegra234-pcie";
2098ec142c44SVidya Sagar		power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CB>;
2099ec142c44SVidya Sagar		reg = <0x00 0x140c0000 0x0 0x00020000>, /* appl registers (128K)      */
2100ec142c44SVidya Sagar		      <0x00 0x2c000000 0x0 0x00040000>, /* configuration space (256K) */
2101ec142c44SVidya Sagar		      <0x00 0x2c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
2102*794b834dSVidya Sagar		      <0x00 0x2c080000 0x0 0x00040000>, /* DBI reg space (256K)       */
2103*794b834dSVidya Sagar		      <0x38 0x30000000 0x0 0x10000000>; /* ECAM (256MB)               */
2104*794b834dSVidya Sagar		reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
2105ec142c44SVidya Sagar
2106ec142c44SVidya Sagar		#address-cells = <3>;
2107ec142c44SVidya Sagar		#size-cells = <2>;
2108ec142c44SVidya Sagar		device_type = "pci";
2109ec142c44SVidya Sagar		num-lanes = <4>;
2110ec142c44SVidya Sagar		num-viewport = <8>;
2111ec142c44SVidya Sagar		linux,pci-domain = <9>;
2112ec142c44SVidya Sagar
2113ec142c44SVidya Sagar		clocks = <&bpmp TEGRA234_CLK_PEX2_C9_CORE>;
2114ec142c44SVidya Sagar		clock-names = "core";
2115ec142c44SVidya Sagar
2116ec142c44SVidya Sagar		resets = <&bpmp TEGRA234_RESET_PEX2_CORE_9_APB>,
2117ec142c44SVidya Sagar			 <&bpmp TEGRA234_RESET_PEX2_CORE_9>;
2118ec142c44SVidya Sagar		reset-names = "apb", "core";
2119ec142c44SVidya Sagar
2120ec142c44SVidya Sagar		interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2121ec142c44SVidya Sagar			     <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2122ec142c44SVidya Sagar		interrupt-names = "intr", "msi";
2123ec142c44SVidya Sagar
2124ec142c44SVidya Sagar		#interrupt-cells = <1>;
2125ec142c44SVidya Sagar		interrupt-map-mask = <0 0 0 0>;
2126ec142c44SVidya Sagar		interrupt-map = <0 0 0 0 &gic GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2127ec142c44SVidya Sagar
2128ec142c44SVidya Sagar		nvidia,bpmp = <&bpmp 9>;
2129ec142c44SVidya Sagar
2130ec142c44SVidya Sagar		nvidia,aspm-cmrt-us = <60>;
2131ec142c44SVidya Sagar		nvidia,aspm-pwr-on-t-us = <20>;
2132ec142c44SVidya Sagar		nvidia,aspm-l0s-entrance-latency-us = <3>;
2133ec142c44SVidya Sagar
2134ec142c44SVidya Sagar		bus-range = <0x0 0xff>;
2135ec142c44SVidya Sagar
213624840065SVidya Sagar		ranges = <0x43000000 0x35 0x40000000 0x35 0x40000000 0x2 0xc0000000>, /* prefetchable memory (11264 MB) */
2137ec142c44SVidya Sagar			 <0x02000000 0x0  0x40000000 0x38 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2138ec142c44SVidya Sagar			 <0x01000000 0x0  0x2c100000 0x00 0x2c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
2139ec142c44SVidya Sagar
2140ec142c44SVidya Sagar		interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE9AR &emc>,
2141ec142c44SVidya Sagar				<&mc TEGRA234_MEMORY_CLIENT_PCIE9AW &emc>;
2142ec142c44SVidya Sagar		interconnect-names = "dma-mem", "write";
2143ec142c44SVidya Sagar		iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE9 0x1000>;
2144ec142c44SVidya Sagar		iommu-map-mask = <0x0>;
2145ec142c44SVidya Sagar		dma-coherent;
2146ec142c44SVidya Sagar
2147ec142c44SVidya Sagar		status = "disabled";
2148ec142c44SVidya Sagar	};
2149ec142c44SVidya Sagar
2150ec142c44SVidya Sagar	pcie@140e0000 {
2151ec142c44SVidya Sagar		compatible = "nvidia,tegra234-pcie";
2152ec142c44SVidya Sagar		power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CC>;
2153ec142c44SVidya Sagar		reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K)      */
2154ec142c44SVidya Sagar		      <0x00 0x2e000000 0x0 0x00040000>, /* configuration space (256K) */
2155ec142c44SVidya Sagar		      <0x00 0x2e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
2156*794b834dSVidya Sagar		      <0x00 0x2e080000 0x0 0x00040000>, /* DBI reg space (256K)       */
2157*794b834dSVidya Sagar		      <0x3b 0x30000000 0x0 0x10000000>; /* ECAM (256MB)               */
2158*794b834dSVidya Sagar		reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
2159ec142c44SVidya Sagar
2160ec142c44SVidya Sagar		#address-cells = <3>;
2161ec142c44SVidya Sagar		#size-cells = <2>;
2162ec142c44SVidya Sagar		device_type = "pci";
2163ec142c44SVidya Sagar		num-lanes = <4>;
2164ec142c44SVidya Sagar		num-viewport = <8>;
2165ec142c44SVidya Sagar		linux,pci-domain = <10>;
2166ec142c44SVidya Sagar
2167ec142c44SVidya Sagar		clocks = <&bpmp TEGRA234_CLK_PEX2_C10_CORE>;
2168ec142c44SVidya Sagar		clock-names = "core";
2169ec142c44SVidya Sagar
2170ec142c44SVidya Sagar		resets = <&bpmp TEGRA234_RESET_PEX2_CORE_10_APB>,
2171ec142c44SVidya Sagar			 <&bpmp TEGRA234_RESET_PEX2_CORE_10>;
2172ec142c44SVidya Sagar		reset-names = "apb", "core";
2173ec142c44SVidya Sagar
2174ec142c44SVidya Sagar		interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2175ec142c44SVidya Sagar			     <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2176ec142c44SVidya Sagar		interrupt-names = "intr", "msi";
2177ec142c44SVidya Sagar
2178ec142c44SVidya Sagar		#interrupt-cells = <1>;
2179ec142c44SVidya Sagar		interrupt-map-mask = <0 0 0 0>;
2180ec142c44SVidya Sagar		interrupt-map = <0 0 0 0 &gic GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
2181ec142c44SVidya Sagar
2182ec142c44SVidya Sagar		nvidia,bpmp = <&bpmp 10>;
2183ec142c44SVidya Sagar
2184ec142c44SVidya Sagar		nvidia,aspm-cmrt-us = <60>;
2185ec142c44SVidya Sagar		nvidia,aspm-pwr-on-t-us = <20>;
2186ec142c44SVidya Sagar		nvidia,aspm-l0s-entrance-latency-us = <3>;
2187ec142c44SVidya Sagar
2188ec142c44SVidya Sagar		bus-range = <0x0 0xff>;
2189ec142c44SVidya Sagar
2190ec142c44SVidya Sagar		ranges = <0x43000000 0x38 0x40000000 0x38 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */
2191ec142c44SVidya Sagar			 <0x02000000 0x0  0x40000000 0x3b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2192ec142c44SVidya Sagar			 <0x01000000 0x0  0x2e100000 0x00 0x2e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
2193ec142c44SVidya Sagar
2194ec142c44SVidya Sagar		interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE10AR &emc>,
2195ec142c44SVidya Sagar				<&mc TEGRA234_MEMORY_CLIENT_PCIE10AW &emc>;
2196ec142c44SVidya Sagar		interconnect-names = "dma-mem", "write";
2197ec142c44SVidya Sagar		iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>;
2198ec142c44SVidya Sagar		iommu-map-mask = <0x0>;
2199ec142c44SVidya Sagar		dma-coherent;
2200ec142c44SVidya Sagar
2201ec142c44SVidya Sagar		status = "disabled";
2202ec142c44SVidya Sagar	};
2203ec142c44SVidya Sagar
2204ec142c44SVidya Sagar	pcie@14100000 {
2205ec142c44SVidya Sagar		compatible = "nvidia,tegra234-pcie";
2206ec142c44SVidya Sagar		power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>;
2207ec142c44SVidya Sagar		reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K)      */
2208ec142c44SVidya Sagar		      <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */
2209ec142c44SVidya Sagar		      <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
2210*794b834dSVidya Sagar		      <0x00 0x30080000 0x0 0x00040000>, /* DBI reg space (256K)       */
2211*794b834dSVidya Sagar		      <0x20 0xb0000000 0x0 0x10000000>; /* ECAM (256MB)               */
2212*794b834dSVidya Sagar		reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
2213ec142c44SVidya Sagar
2214ec142c44SVidya Sagar		#address-cells = <3>;
2215ec142c44SVidya Sagar		#size-cells = <2>;
2216ec142c44SVidya Sagar		device_type = "pci";
2217ec142c44SVidya Sagar		num-lanes = <1>;
2218ec142c44SVidya Sagar		num-viewport = <8>;
2219ec142c44SVidya Sagar		linux,pci-domain = <1>;
2220ec142c44SVidya Sagar
2221ec142c44SVidya Sagar		clocks = <&bpmp TEGRA234_CLK_PEX0_C1_CORE>;
2222ec142c44SVidya Sagar		clock-names = "core";
2223ec142c44SVidya Sagar
2224ec142c44SVidya Sagar		resets = <&bpmp TEGRA234_RESET_PEX0_CORE_1_APB>,
2225ec142c44SVidya Sagar			 <&bpmp TEGRA234_RESET_PEX0_CORE_1>;
2226ec142c44SVidya Sagar		reset-names = "apb", "core";
2227ec142c44SVidya Sagar
2228ec142c44SVidya Sagar		interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2229ec142c44SVidya Sagar			     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2230ec142c44SVidya Sagar		interrupt-names = "intr", "msi";
2231ec142c44SVidya Sagar
2232ec142c44SVidya Sagar		#interrupt-cells = <1>;
2233ec142c44SVidya Sagar		interrupt-map-mask = <0 0 0 0>;
2234ec142c44SVidya Sagar		interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
2235ec142c44SVidya Sagar
2236ec142c44SVidya Sagar		nvidia,bpmp = <&bpmp 1>;
2237ec142c44SVidya Sagar
2238ec142c44SVidya Sagar		nvidia,aspm-cmrt-us = <60>;
2239ec142c44SVidya Sagar		nvidia,aspm-pwr-on-t-us = <20>;
2240ec142c44SVidya Sagar		nvidia,aspm-l0s-entrance-latency-us = <3>;
2241ec142c44SVidya Sagar
2242ec142c44SVidya Sagar		bus-range = <0x0 0xff>;
2243ec142c44SVidya Sagar
2244ec142c44SVidya Sagar		ranges = <0x43000000 0x20 0x80000000 0x20 0x80000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */
2245ec142c44SVidya Sagar			 <0x02000000 0x0  0x40000000 0x20 0xa8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2246ec142c44SVidya Sagar			 <0x01000000 0x0  0x30100000 0x00 0x30100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
2247ec142c44SVidya Sagar
2248ec142c44SVidya Sagar		interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE1R &emc>,
2249ec142c44SVidya Sagar				<&mc TEGRA234_MEMORY_CLIENT_PCIE1W &emc>;
2250ec142c44SVidya Sagar		interconnect-names = "dma-mem", "write";
2251ec142c44SVidya Sagar		iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE1 0x1000>;
2252ec142c44SVidya Sagar		iommu-map-mask = <0x0>;
2253ec142c44SVidya Sagar		dma-coherent;
2254ec142c44SVidya Sagar
2255ec142c44SVidya Sagar		status = "disabled";
2256ec142c44SVidya Sagar	};
2257ec142c44SVidya Sagar
2258ec142c44SVidya Sagar	pcie@14120000 {
2259ec142c44SVidya Sagar		compatible = "nvidia,tegra234-pcie";
2260ec142c44SVidya Sagar		power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>;
2261ec142c44SVidya Sagar		reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K)      */
2262ec142c44SVidya Sagar		      <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */
2263ec142c44SVidya Sagar		      <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
2264*794b834dSVidya Sagar		      <0x00 0x32080000 0x0 0x00040000>, /* DBI reg space (256K)       */
2265*794b834dSVidya Sagar		      <0x20 0xf0000000 0x0 0x10000000>; /* ECAM (256MB)               */
2266*794b834dSVidya Sagar		reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
2267ec142c44SVidya Sagar
2268ec142c44SVidya Sagar		#address-cells = <3>;
2269ec142c44SVidya Sagar		#size-cells = <2>;
2270ec142c44SVidya Sagar		device_type = "pci";
2271ec142c44SVidya Sagar		num-lanes = <1>;
2272ec142c44SVidya Sagar		num-viewport = <8>;
2273ec142c44SVidya Sagar		linux,pci-domain = <2>;
2274ec142c44SVidya Sagar
2275ec142c44SVidya Sagar		clocks = <&bpmp TEGRA234_CLK_PEX0_C2_CORE>;
2276ec142c44SVidya Sagar		clock-names = "core";
2277ec142c44SVidya Sagar
2278ec142c44SVidya Sagar		resets = <&bpmp TEGRA234_RESET_PEX0_CORE_2_APB>,
2279ec142c44SVidya Sagar			 <&bpmp TEGRA234_RESET_PEX0_CORE_2>;
2280ec142c44SVidya Sagar		reset-names = "apb", "core";
2281ec142c44SVidya Sagar
2282ec142c44SVidya Sagar		interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2283ec142c44SVidya Sagar			     <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2284ec142c44SVidya Sagar		interrupt-names = "intr", "msi";
2285ec142c44SVidya Sagar
2286ec142c44SVidya Sagar		#interrupt-cells = <1>;
2287ec142c44SVidya Sagar		interrupt-map-mask = <0 0 0 0>;
2288ec142c44SVidya Sagar		interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
2289ec142c44SVidya Sagar
2290ec142c44SVidya Sagar		nvidia,bpmp = <&bpmp 2>;
2291ec142c44SVidya Sagar
2292ec142c44SVidya Sagar		nvidia,aspm-cmrt-us = <60>;
2293ec142c44SVidya Sagar		nvidia,aspm-pwr-on-t-us = <20>;
2294ec142c44SVidya Sagar		nvidia,aspm-l0s-entrance-latency-us = <3>;
2295ec142c44SVidya Sagar
2296ec142c44SVidya Sagar		bus-range = <0x0 0xff>;
2297ec142c44SVidya Sagar
2298ec142c44SVidya Sagar		ranges = <0x43000000 0x20 0xc0000000 0x20 0xc0000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */
2299ec142c44SVidya Sagar			 <0x02000000 0x0  0x40000000 0x20 0xe8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2300ec142c44SVidya Sagar			 <0x01000000 0x0  0x32100000 0x00 0x32100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
2301ec142c44SVidya Sagar
2302ec142c44SVidya Sagar		interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE2AR &emc>,
2303ec142c44SVidya Sagar				<&mc TEGRA234_MEMORY_CLIENT_PCIE2AW &emc>;
2304ec142c44SVidya Sagar		interconnect-names = "dma-mem", "write";
2305ec142c44SVidya Sagar		iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE2 0x1000>;
2306ec142c44SVidya Sagar		iommu-map-mask = <0x0>;
2307ec142c44SVidya Sagar		dma-coherent;
2308ec142c44SVidya Sagar
2309ec142c44SVidya Sagar		status = "disabled";
2310ec142c44SVidya Sagar	};
2311ec142c44SVidya Sagar
2312ec142c44SVidya Sagar	pcie@14140000 {
2313ec142c44SVidya Sagar		compatible = "nvidia,tegra234-pcie";
2314ec142c44SVidya Sagar		power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>;
2315ec142c44SVidya Sagar		reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K)      */
2316ec142c44SVidya Sagar		      <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */
2317ec142c44SVidya Sagar		      <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
2318*794b834dSVidya Sagar		      <0x00 0x34080000 0x0 0x00040000>, /* DBI reg space (256K)       */
2319*794b834dSVidya Sagar		      <0x21 0x30000000 0x0 0x10000000>; /* ECAM (256MB)               */
2320*794b834dSVidya Sagar		reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
2321ec142c44SVidya Sagar
2322ec142c44SVidya Sagar		#address-cells = <3>;
2323ec142c44SVidya Sagar		#size-cells = <2>;
2324ec142c44SVidya Sagar		device_type = "pci";
2325ec142c44SVidya Sagar		num-lanes = <1>;
2326ec142c44SVidya Sagar		num-viewport = <8>;
2327ec142c44SVidya Sagar		linux,pci-domain = <3>;
2328ec142c44SVidya Sagar
2329ec142c44SVidya Sagar		clocks = <&bpmp TEGRA234_CLK_PEX0_C3_CORE>;
2330ec142c44SVidya Sagar		clock-names = "core";
2331ec142c44SVidya Sagar
2332ec142c44SVidya Sagar		resets = <&bpmp TEGRA234_RESET_PEX0_CORE_3_APB>,
2333ec142c44SVidya Sagar			 <&bpmp TEGRA234_RESET_PEX0_CORE_3>;
2334ec142c44SVidya Sagar		reset-names = "apb", "core";
2335ec142c44SVidya Sagar
2336ec142c44SVidya Sagar		interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2337ec142c44SVidya Sagar			     <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2338ec142c44SVidya Sagar		interrupt-names = "intr", "msi";
2339ec142c44SVidya Sagar
2340ec142c44SVidya Sagar		#interrupt-cells = <1>;
2341ec142c44SVidya Sagar		interrupt-map-mask = <0 0 0 0>;
2342ec142c44SVidya Sagar		interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
2343ec142c44SVidya Sagar
2344ec142c44SVidya Sagar		nvidia,bpmp = <&bpmp 3>;
2345ec142c44SVidya Sagar
2346ec142c44SVidya Sagar		nvidia,aspm-cmrt-us = <60>;
2347ec142c44SVidya Sagar		nvidia,aspm-pwr-on-t-us = <20>;
2348ec142c44SVidya Sagar		nvidia,aspm-l0s-entrance-latency-us = <3>;
2349ec142c44SVidya Sagar
2350ec142c44SVidya Sagar		bus-range = <0x0 0xff>;
2351ec142c44SVidya Sagar
2352ec142c44SVidya Sagar		ranges = <0x43000000 0x21 0x00000000 0x21 0x00000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */
2353ec142c44SVidya Sagar			 <0x02000000 0x0  0x40000000 0x21 0xe8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2354ec142c44SVidya Sagar			 <0x01000000 0x0  0x34100000 0x00 0x34100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
2355ec142c44SVidya Sagar
2356ec142c44SVidya Sagar		interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE3R &emc>,
2357ec142c44SVidya Sagar				<&mc TEGRA234_MEMORY_CLIENT_PCIE3W &emc>;
2358ec142c44SVidya Sagar		interconnect-names = "dma-mem", "write";
2359ec142c44SVidya Sagar		iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE3 0x1000>;
2360ec142c44SVidya Sagar		iommu-map-mask = <0x0>;
2361ec142c44SVidya Sagar		dma-coherent;
2362ec142c44SVidya Sagar
2363ec142c44SVidya Sagar		status = "disabled";
2364ec142c44SVidya Sagar	};
2365ec142c44SVidya Sagar
2366ec142c44SVidya Sagar	pcie@14160000 {
2367ec142c44SVidya Sagar		compatible = "nvidia,tegra234-pcie";
2368ec142c44SVidya Sagar		power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BB>;
2369ec142c44SVidya Sagar		reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K)      */
2370ec142c44SVidya Sagar		      <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */
2371ec142c44SVidya Sagar		      <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
2372*794b834dSVidya Sagar		      <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K)       */
2373*794b834dSVidya Sagar		      <0x24 0x30000000 0x0 0x10000000>; /* ECAM (256MB)               */
2374*794b834dSVidya Sagar		reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
2375ec142c44SVidya Sagar
2376ec142c44SVidya Sagar		#address-cells = <3>;
2377ec142c44SVidya Sagar		#size-cells = <2>;
2378ec142c44SVidya Sagar		device_type = "pci";
2379ec142c44SVidya Sagar		num-lanes = <4>;
2380ec142c44SVidya Sagar		num-viewport = <8>;
2381ec142c44SVidya Sagar		linux,pci-domain = <4>;
2382ec142c44SVidya Sagar
2383ec142c44SVidya Sagar		clocks = <&bpmp TEGRA234_CLK_PEX0_C4_CORE>;
2384ec142c44SVidya Sagar		clock-names = "core";
2385ec142c44SVidya Sagar
2386ec142c44SVidya Sagar		resets = <&bpmp TEGRA234_RESET_PEX0_CORE_4_APB>,
2387ec142c44SVidya Sagar			 <&bpmp TEGRA234_RESET_PEX0_CORE_4>;
2388ec142c44SVidya Sagar		reset-names = "apb", "core";
2389ec142c44SVidya Sagar
2390ec142c44SVidya Sagar		interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2391ec142c44SVidya Sagar			     <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2392ec142c44SVidya Sagar		interrupt-names = "intr", "msi";
2393ec142c44SVidya Sagar
2394ec142c44SVidya Sagar		#interrupt-cells = <1>;
2395ec142c44SVidya Sagar		interrupt-map-mask = <0 0 0 0>;
2396ec142c44SVidya Sagar		interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
2397ec142c44SVidya Sagar
2398ec142c44SVidya Sagar		nvidia,bpmp = <&bpmp 4>;
2399ec142c44SVidya Sagar
2400ec142c44SVidya Sagar		nvidia,aspm-cmrt-us = <60>;
2401ec142c44SVidya Sagar		nvidia,aspm-pwr-on-t-us = <20>;
2402ec142c44SVidya Sagar		nvidia,aspm-l0s-entrance-latency-us = <3>;
2403ec142c44SVidya Sagar
2404ec142c44SVidya Sagar		bus-range = <0x0 0xff>;
2405ec142c44SVidya Sagar
2406ec142c44SVidya Sagar		ranges = <0x43000000 0x21 0x40000000 0x21 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */
2407ec142c44SVidya Sagar			 <0x02000000 0x0  0x40000000 0x24 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2408ec142c44SVidya Sagar			 <0x01000000 0x0  0x36100000 0x00 0x36100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
2409ec142c44SVidya Sagar
2410ec142c44SVidya Sagar		interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE4R &emc>,
2411ec142c44SVidya Sagar				<&mc TEGRA234_MEMORY_CLIENT_PCIE4W &emc>;
2412ec142c44SVidya Sagar		interconnect-names = "dma-mem", "write";
2413ec142c44SVidya Sagar		iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE4 0x1000>;
2414ec142c44SVidya Sagar		iommu-map-mask = <0x0>;
2415ec142c44SVidya Sagar		dma-coherent;
2416ec142c44SVidya Sagar
2417ec142c44SVidya Sagar		status = "disabled";
2418ec142c44SVidya Sagar	};
2419ec142c44SVidya Sagar
2420ec142c44SVidya Sagar	pcie@14180000 {
2421ec142c44SVidya Sagar		compatible = "nvidia,tegra234-pcie";
2422ec142c44SVidya Sagar		power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BA>;
2423ec142c44SVidya Sagar		reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K)      */
2424ec142c44SVidya Sagar		      <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */
2425ec142c44SVidya Sagar		      <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
2426*794b834dSVidya Sagar		      <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K)       */
2427*794b834dSVidya Sagar		      <0x27 0x30000000 0x0 0x10000000>; /* ECAM (256MB)               */
2428*794b834dSVidya Sagar		reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
2429ec142c44SVidya Sagar
2430ec142c44SVidya Sagar		#address-cells = <3>;
2431ec142c44SVidya Sagar		#size-cells = <2>;
2432ec142c44SVidya Sagar		device_type = "pci";
2433ec142c44SVidya Sagar		num-lanes = <4>;
2434ec142c44SVidya Sagar		num-viewport = <8>;
2435ec142c44SVidya Sagar		linux,pci-domain = <0>;
2436ec142c44SVidya Sagar
2437ec142c44SVidya Sagar		clocks = <&bpmp TEGRA234_CLK_PEX0_C0_CORE>;
2438ec142c44SVidya Sagar		clock-names = "core";
2439ec142c44SVidya Sagar
2440ec142c44SVidya Sagar		resets = <&bpmp TEGRA234_RESET_PEX0_CORE_0_APB>,
2441ec142c44SVidya Sagar			 <&bpmp TEGRA234_RESET_PEX0_CORE_0>;
2442ec142c44SVidya Sagar		reset-names = "apb", "core";
2443ec142c44SVidya Sagar
2444ec142c44SVidya Sagar		interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2445ec142c44SVidya Sagar			     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2446ec142c44SVidya Sagar		interrupt-names = "intr", "msi";
2447ec142c44SVidya Sagar
2448ec142c44SVidya Sagar		#interrupt-cells = <1>;
2449ec142c44SVidya Sagar		interrupt-map-mask = <0 0 0 0>;
2450ec142c44SVidya Sagar		interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
2451ec142c44SVidya Sagar
2452ec142c44SVidya Sagar		nvidia,bpmp = <&bpmp 0>;
2453ec142c44SVidya Sagar
2454ec142c44SVidya Sagar		nvidia,aspm-cmrt-us = <60>;
2455ec142c44SVidya Sagar		nvidia,aspm-pwr-on-t-us = <20>;
2456ec142c44SVidya Sagar		nvidia,aspm-l0s-entrance-latency-us = <3>;
2457ec142c44SVidya Sagar
2458ec142c44SVidya Sagar		bus-range = <0x0 0xff>;
2459ec142c44SVidya Sagar
2460ec142c44SVidya Sagar		ranges = <0x43000000 0x24 0x40000000 0x24 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */
2461ec142c44SVidya Sagar			 <0x02000000 0x0  0x40000000 0x27 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2462ec142c44SVidya Sagar			 <0x01000000 0x0  0x38100000 0x00 0x38100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
2463ec142c44SVidya Sagar
2464ec142c44SVidya Sagar		interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE0R &emc>,
2465ec142c44SVidya Sagar				<&mc TEGRA234_MEMORY_CLIENT_PCIE0W &emc>;
2466ec142c44SVidya Sagar		interconnect-names = "dma-mem", "write";
2467ec142c44SVidya Sagar		iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE0 0x1000>;
2468ec142c44SVidya Sagar		iommu-map-mask = <0x0>;
2469ec142c44SVidya Sagar		dma-coherent;
2470ec142c44SVidya Sagar
2471ec142c44SVidya Sagar		status = "disabled";
2472ec142c44SVidya Sagar	};
2473ec142c44SVidya Sagar
2474ec142c44SVidya Sagar	pcie@141a0000 {
2475ec142c44SVidya Sagar		compatible = "nvidia,tegra234-pcie";
2476ec142c44SVidya Sagar		power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>;
2477ec142c44SVidya Sagar		reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K)      */
2478ec142c44SVidya Sagar		      <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */
2479ec142c44SVidya Sagar		      <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
2480*794b834dSVidya Sagar		      <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K)       */
2481*794b834dSVidya Sagar		      <0x2b 0x30000000 0x0 0x10000000>; /* ECAM (256MB)               */
2482*794b834dSVidya Sagar		reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
2483ec142c44SVidya Sagar
2484ec142c44SVidya Sagar		#address-cells = <3>;
2485ec142c44SVidya Sagar		#size-cells = <2>;
2486ec142c44SVidya Sagar		device_type = "pci";
2487ec142c44SVidya Sagar		num-lanes = <8>;
2488ec142c44SVidya Sagar		num-viewport = <8>;
2489ec142c44SVidya Sagar		linux,pci-domain = <5>;
2490ec142c44SVidya Sagar
2491ec142c44SVidya Sagar		clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>;
2492ec142c44SVidya Sagar		clock-names = "core";
2493ec142c44SVidya Sagar
2494ec142c44SVidya Sagar		resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>,
2495ec142c44SVidya Sagar			 <&bpmp TEGRA234_RESET_PEX1_CORE_5>;
2496ec142c44SVidya Sagar		reset-names = "apb", "core";
2497ec142c44SVidya Sagar
2498ec142c44SVidya Sagar		interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2499ec142c44SVidya Sagar			     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2500ec142c44SVidya Sagar		interrupt-names = "intr", "msi";
2501ec142c44SVidya Sagar
2502ec142c44SVidya Sagar		#interrupt-cells = <1>;
2503ec142c44SVidya Sagar		interrupt-map-mask = <0 0 0 0>;
2504ec142c44SVidya Sagar		interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
2505ec142c44SVidya Sagar
2506ec142c44SVidya Sagar		nvidia,bpmp = <&bpmp 5>;
2507ec142c44SVidya Sagar
2508ec142c44SVidya Sagar		nvidia,aspm-cmrt-us = <60>;
2509ec142c44SVidya Sagar		nvidia,aspm-pwr-on-t-us = <20>;
2510ec142c44SVidya Sagar		nvidia,aspm-l0s-entrance-latency-us = <3>;
2511ec142c44SVidya Sagar
2512ec142c44SVidya Sagar		bus-range = <0x0 0xff>;
2513ec142c44SVidya Sagar
251424840065SVidya Sagar		ranges = <0x43000000 0x28 0x00000000 0x28 0x00000000 0x3 0x28000000>, /* prefetchable memory (12928 MB) */
2515ec142c44SVidya Sagar			 <0x02000000 0x0  0x40000000 0x2b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2516ec142c44SVidya Sagar			 <0x01000000 0x0  0x3a100000 0x00 0x3a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
2517ec142c44SVidya Sagar
2518ec142c44SVidya Sagar		interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE5R &emc>,
2519ec142c44SVidya Sagar				<&mc TEGRA234_MEMORY_CLIENT_PCIE5W &emc>;
2520ec142c44SVidya Sagar		interconnect-names = "dma-mem", "write";
2521ec142c44SVidya Sagar		iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>;
2522ec142c44SVidya Sagar		iommu-map-mask = <0x0>;
2523ec142c44SVidya Sagar		dma-coherent;
2524ec142c44SVidya Sagar
2525ec142c44SVidya Sagar		status = "disabled";
2526ec142c44SVidya Sagar	};
2527ec142c44SVidya Sagar
2528ec142c44SVidya Sagar	pcie@141c0000 {
2529ec142c44SVidya Sagar		compatible = "nvidia,tegra234-pcie";
2530ec142c44SVidya Sagar		power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4A>;
2531ec142c44SVidya Sagar		reg = <0x00 0x141c0000 0x0 0x00020000>, /* appl registers (128K)      */
2532ec142c44SVidya Sagar		      <0x00 0x3c000000 0x0 0x00040000>, /* configuration space (256K) */
2533ec142c44SVidya Sagar		      <0x00 0x3c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
2534*794b834dSVidya Sagar		      <0x00 0x3c080000 0x0 0x00040000>, /* DBI reg space (256K)       */
2535*794b834dSVidya Sagar		      <0x2e 0x30000000 0x0 0x10000000>; /* ECAM (256MB)               */
2536*794b834dSVidya Sagar		reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
2537ec142c44SVidya Sagar
2538ec142c44SVidya Sagar		#address-cells = <3>;
2539ec142c44SVidya Sagar		#size-cells = <2>;
2540ec142c44SVidya Sagar		device_type = "pci";
2541ec142c44SVidya Sagar		num-lanes = <4>;
2542ec142c44SVidya Sagar		num-viewport = <8>;
2543ec142c44SVidya Sagar		linux,pci-domain = <6>;
2544ec142c44SVidya Sagar
2545ec142c44SVidya Sagar		clocks = <&bpmp TEGRA234_CLK_PEX1_C6_CORE>;
2546ec142c44SVidya Sagar		clock-names = "core";
2547ec142c44SVidya Sagar
2548ec142c44SVidya Sagar		resets = <&bpmp TEGRA234_RESET_PEX1_CORE_6_APB>,
2549ec142c44SVidya Sagar			 <&bpmp TEGRA234_RESET_PEX1_CORE_6>;
2550ec142c44SVidya Sagar		reset-names = "apb", "core";
2551ec142c44SVidya Sagar
2552ec142c44SVidya Sagar		interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2553ec142c44SVidya Sagar			     <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2554ec142c44SVidya Sagar		interrupt-names = "intr", "msi";
2555ec142c44SVidya Sagar
2556ec142c44SVidya Sagar		#interrupt-cells = <1>;
2557ec142c44SVidya Sagar		interrupt-map-mask = <0 0 0 0>;
2558ec142c44SVidya Sagar		interrupt-map = <0 0 0 0 &gic GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
2559ec142c44SVidya Sagar
2560ec142c44SVidya Sagar		nvidia,bpmp = <&bpmp 6>;
2561ec142c44SVidya Sagar
2562ec142c44SVidya Sagar		nvidia,aspm-cmrt-us = <60>;
2563ec142c44SVidya Sagar		nvidia,aspm-pwr-on-t-us = <20>;
2564ec142c44SVidya Sagar		nvidia,aspm-l0s-entrance-latency-us = <3>;
2565ec142c44SVidya Sagar
2566ec142c44SVidya Sagar		bus-range = <0x0 0xff>;
2567ec142c44SVidya Sagar
2568ec142c44SVidya Sagar		ranges = <0x43000000 0x2b 0x40000000 0x2b 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */
2569ec142c44SVidya Sagar			 <0x02000000 0x0  0x40000000 0x2e 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2570ec142c44SVidya Sagar			 <0x01000000 0x0  0x3c100000 0x00 0x3c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
2571ec142c44SVidya Sagar
2572ec142c44SVidya Sagar		interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE6AR &emc>,
2573ec142c44SVidya Sagar				<&mc TEGRA234_MEMORY_CLIENT_PCIE6AW &emc>;
2574ec142c44SVidya Sagar		interconnect-names = "dma-mem", "write";
2575ec142c44SVidya Sagar		iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>;
2576ec142c44SVidya Sagar		iommu-map-mask = <0x0>;
2577ec142c44SVidya Sagar		dma-coherent;
2578ec142c44SVidya Sagar
2579ec142c44SVidya Sagar		status = "disabled";
2580ec142c44SVidya Sagar	};
2581ec142c44SVidya Sagar
2582ec142c44SVidya Sagar	pcie@141e0000 {
2583ec142c44SVidya Sagar		compatible = "nvidia,tegra234-pcie";
2584ec142c44SVidya Sagar		power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8B>;
2585ec142c44SVidya Sagar		reg = <0x00 0x141e0000 0x0 0x00020000>, /* appl registers (128K)      */
2586ec142c44SVidya Sagar		      <0x00 0x3e000000 0x0 0x00040000>, /* configuration space (256K) */
2587ec142c44SVidya Sagar		      <0x00 0x3e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
2588*794b834dSVidya Sagar		      <0x00 0x3e080000 0x0 0x00040000>, /* DBI reg space (256K)       */
2589*794b834dSVidya Sagar		      <0x32 0x30000000 0x0 0x10000000>; /* ECAM (256MB)               */
2590*794b834dSVidya Sagar		reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
2591ec142c44SVidya Sagar
2592ec142c44SVidya Sagar		#address-cells = <3>;
2593ec142c44SVidya Sagar		#size-cells = <2>;
2594ec142c44SVidya Sagar		device_type = "pci";
2595ec142c44SVidya Sagar		num-lanes = <8>;
2596ec142c44SVidya Sagar		num-viewport = <8>;
2597ec142c44SVidya Sagar		linux,pci-domain = <7>;
2598ec142c44SVidya Sagar
2599ec142c44SVidya Sagar		clocks = <&bpmp TEGRA234_CLK_PEX2_C7_CORE>;
2600ec142c44SVidya Sagar		clock-names = "core";
2601ec142c44SVidya Sagar
2602ec142c44SVidya Sagar		resets = <&bpmp TEGRA234_RESET_PEX2_CORE_7_APB>,
2603ec142c44SVidya Sagar			 <&bpmp TEGRA234_RESET_PEX2_CORE_7>;
2604ec142c44SVidya Sagar		reset-names = "apb", "core";
2605ec142c44SVidya Sagar
2606ec142c44SVidya Sagar		interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2607ec142c44SVidya Sagar			     <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2608ec142c44SVidya Sagar		interrupt-names = "intr", "msi";
2609ec142c44SVidya Sagar
2610ec142c44SVidya Sagar		#interrupt-cells = <1>;
2611ec142c44SVidya Sagar		interrupt-map-mask = <0 0 0 0>;
2612ec142c44SVidya Sagar		interrupt-map = <0 0 0 0 &gic GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
2613ec142c44SVidya Sagar
2614ec142c44SVidya Sagar		nvidia,bpmp = <&bpmp 7>;
2615ec142c44SVidya Sagar
2616ec142c44SVidya Sagar		nvidia,aspm-cmrt-us = <60>;
2617ec142c44SVidya Sagar		nvidia,aspm-pwr-on-t-us = <20>;
2618ec142c44SVidya Sagar		nvidia,aspm-l0s-entrance-latency-us = <3>;
2619ec142c44SVidya Sagar
2620ec142c44SVidya Sagar		bus-range = <0x0 0xff>;
2621ec142c44SVidya Sagar
262224840065SVidya Sagar		ranges = <0x43000000 0x30 0x00000000 0x30 0x00000000 0x2 0x28000000>, /* prefetchable memory (8832 MB) */
2623ec142c44SVidya Sagar			 <0x02000000 0x0  0x40000000 0x32 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2624ec142c44SVidya Sagar			 <0x01000000 0x0  0x3e100000 0x00 0x3e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
2625ec142c44SVidya Sagar
2626ec142c44SVidya Sagar		interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE7AR &emc>,
2627ec142c44SVidya Sagar				<&mc TEGRA234_MEMORY_CLIENT_PCIE7AW &emc>;
2628ec142c44SVidya Sagar		interconnect-names = "dma-mem", "write";
2629ec142c44SVidya Sagar		iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>;
2630ec142c44SVidya Sagar		iommu-map-mask = <0x0>;
2631ec142c44SVidya Sagar		dma-coherent;
2632ec142c44SVidya Sagar
2633ec142c44SVidya Sagar		status = "disabled";
2634ec142c44SVidya Sagar	};
2635ec142c44SVidya Sagar
2636ec142c44SVidya Sagar	pcie-ep@141a0000 {
2637ec142c44SVidya Sagar		compatible = "nvidia,tegra234-pcie-ep";
2638ec142c44SVidya Sagar		power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>;
2639ec142c44SVidya Sagar		reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K)      */
2640ec142c44SVidya Sagar		      <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
2641ec142c44SVidya Sagar		      <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K)       */
2642ec142c44SVidya Sagar		      <0x27 0x40000000 0x4 0x00000000>; /* Address Space (16G)        */
2643ec142c44SVidya Sagar		reg-names = "appl", "atu_dma", "dbi", "addr_space";
2644ec142c44SVidya Sagar
2645ec142c44SVidya Sagar		num-lanes = <8>;
2646ec142c44SVidya Sagar
2647ec142c44SVidya Sagar		clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>;
2648ec142c44SVidya Sagar		clock-names = "core";
2649ec142c44SVidya Sagar
2650ec142c44SVidya Sagar		resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>,
2651ec142c44SVidya Sagar			 <&bpmp TEGRA234_RESET_PEX1_CORE_5>;
2652ec142c44SVidya Sagar		reset-names = "apb", "core";
2653ec142c44SVidya Sagar
2654ec142c44SVidya Sagar		interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;	/* controller interrupt */
2655ec142c44SVidya Sagar		interrupt-names = "intr";
2656ec142c44SVidya Sagar
2657ec142c44SVidya Sagar		nvidia,bpmp = <&bpmp 5>;
2658ec142c44SVidya Sagar
2659ec142c44SVidya Sagar		nvidia,enable-ext-refclk;
2660ec142c44SVidya Sagar		nvidia,aspm-cmrt-us = <60>;
2661ec142c44SVidya Sagar		nvidia,aspm-pwr-on-t-us = <20>;
2662ec142c44SVidya Sagar		nvidia,aspm-l0s-entrance-latency-us = <3>;
2663ec142c44SVidya Sagar
2664ec142c44SVidya Sagar		interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE5R &emc>,
2665ec142c44SVidya Sagar				<&mc TEGRA234_MEMORY_CLIENT_PCIE5W &emc>;
2666ec142c44SVidya Sagar		interconnect-names = "dma-mem", "write";
2667ec142c44SVidya Sagar		iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>;
2668ec142c44SVidya Sagar		iommu-map-mask = <0x0>;
2669ec142c44SVidya Sagar		dma-coherent;
2670ec142c44SVidya Sagar
2671ec142c44SVidya Sagar		status = "disabled";
2672ec142c44SVidya Sagar	};
2673ec142c44SVidya Sagar
2674ec142c44SVidya Sagar	pcie-ep@141c0000{
2675ec142c44SVidya Sagar		compatible = "nvidia,tegra234-pcie-ep";
2676ec142c44SVidya Sagar		power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4A>;
2677ec142c44SVidya Sagar		reg = <0x00 0x141c0000 0x0 0x00020000>, /* appl registers (128K)      */
2678ec142c44SVidya Sagar		      <0x00 0x3c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
2679ec142c44SVidya Sagar		      <0x00 0x3c080000 0x0 0x00040000>, /* DBI space (256K)           */
2680ec142c44SVidya Sagar		      <0x2b 0x40000000 0x3 0x00000000>; /* Address Space (12G)        */
2681ec142c44SVidya Sagar		reg-names = "appl", "atu_dma", "dbi", "addr_space";
2682ec142c44SVidya Sagar
2683ec142c44SVidya Sagar		num-lanes = <4>;
2684ec142c44SVidya Sagar
2685ec142c44SVidya Sagar		clocks = <&bpmp TEGRA234_CLK_PEX1_C6_CORE>;
2686ec142c44SVidya Sagar		clock-names = "core";
2687ec142c44SVidya Sagar
2688ec142c44SVidya Sagar		resets = <&bpmp TEGRA234_RESET_PEX1_CORE_6_APB>,
2689ec142c44SVidya Sagar			 <&bpmp TEGRA234_RESET_PEX1_CORE_6>;
2690ec142c44SVidya Sagar		reset-names = "apb", "core";
2691ec142c44SVidya Sagar
2692ec142c44SVidya Sagar		interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;	/* controller interrupt */
2693ec142c44SVidya Sagar		interrupt-names = "intr";
2694ec142c44SVidya Sagar
2695ec142c44SVidya Sagar		nvidia,bpmp = <&bpmp 6>;
2696ec142c44SVidya Sagar
2697ec142c44SVidya Sagar		nvidia,enable-ext-refclk;
2698ec142c44SVidya Sagar		nvidia,aspm-cmrt-us = <60>;
2699ec142c44SVidya Sagar		nvidia,aspm-pwr-on-t-us = <20>;
2700ec142c44SVidya Sagar		nvidia,aspm-l0s-entrance-latency-us = <3>;
2701ec142c44SVidya Sagar
2702ec142c44SVidya Sagar		interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE6AR &emc>,
2703ec142c44SVidya Sagar				<&mc TEGRA234_MEMORY_CLIENT_PCIE6AW &emc>;
2704ec142c44SVidya Sagar		interconnect-names = "dma-mem", "write";
2705ec142c44SVidya Sagar		iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>;
2706ec142c44SVidya Sagar		iommu-map-mask = <0x0>;
2707ec142c44SVidya Sagar		dma-coherent;
2708ec142c44SVidya Sagar
2709ec142c44SVidya Sagar		status = "disabled";
2710ec142c44SVidya Sagar	};
2711ec142c44SVidya Sagar
2712ec142c44SVidya Sagar	pcie-ep@141e0000{
2713ec142c44SVidya Sagar		compatible = "nvidia,tegra234-pcie-ep";
2714ec142c44SVidya Sagar		power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8B>;
2715ec142c44SVidya Sagar		reg = <0x00 0x141e0000 0x0 0x00020000>, /* appl registers (128K)      */
2716ec142c44SVidya Sagar		      <0x00 0x3e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
2717ec142c44SVidya Sagar		      <0x00 0x3e080000 0x0 0x00040000>, /* DBI space (256K)           */
2718ec142c44SVidya Sagar		      <0x2e 0x40000000 0x4 0x00000000>; /* Address Space (16G)        */
2719ec142c44SVidya Sagar		reg-names = "appl", "atu_dma", "dbi", "addr_space";
2720ec142c44SVidya Sagar
2721ec142c44SVidya Sagar		num-lanes = <8>;
2722ec142c44SVidya Sagar
2723ec142c44SVidya Sagar		clocks = <&bpmp TEGRA234_CLK_PEX2_C7_CORE>;
2724ec142c44SVidya Sagar		clock-names = "core";
2725ec142c44SVidya Sagar
2726ec142c44SVidya Sagar		resets = <&bpmp TEGRA234_RESET_PEX2_CORE_7_APB>,
2727ec142c44SVidya Sagar			 <&bpmp TEGRA234_RESET_PEX2_CORE_7>;
2728ec142c44SVidya Sagar		reset-names = "apb", "core";
2729ec142c44SVidya Sagar
2730ec142c44SVidya Sagar		interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;	/* controller interrupt */
2731ec142c44SVidya Sagar		interrupt-names = "intr";
2732ec142c44SVidya Sagar
2733ec142c44SVidya Sagar		nvidia,bpmp = <&bpmp 7>;
2734ec142c44SVidya Sagar
2735ec142c44SVidya Sagar		nvidia,enable-ext-refclk;
2736ec142c44SVidya Sagar		nvidia,aspm-cmrt-us = <60>;
2737ec142c44SVidya Sagar		nvidia,aspm-pwr-on-t-us = <20>;
2738ec142c44SVidya Sagar		nvidia,aspm-l0s-entrance-latency-us = <3>;
2739ec142c44SVidya Sagar
2740ec142c44SVidya Sagar		interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE7AR &emc>,
2741ec142c44SVidya Sagar				<&mc TEGRA234_MEMORY_CLIENT_PCIE7AW &emc>;
2742ec142c44SVidya Sagar		interconnect-names = "dma-mem", "write";
2743ec142c44SVidya Sagar		iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>;
2744ec142c44SVidya Sagar		iommu-map-mask = <0x0>;
2745ec142c44SVidya Sagar		dma-coherent;
2746ec142c44SVidya Sagar
2747ec142c44SVidya Sagar		status = "disabled";
2748ec142c44SVidya Sagar	};
2749ec142c44SVidya Sagar
2750ec142c44SVidya Sagar	pcie-ep@140e0000{
2751ec142c44SVidya Sagar		compatible = "nvidia,tegra234-pcie-ep";
2752ec142c44SVidya Sagar		power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CC>;
2753ec142c44SVidya Sagar		reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K)      */
2754ec142c44SVidya Sagar		      <0x00 0x2e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
2755ec142c44SVidya Sagar		      <0x00 0x2e080000 0x0 0x00040000>, /* DBI space (256K)           */
2756ec142c44SVidya Sagar		      <0x38 0x40000000 0x3 0x00000000>; /* Address Space (12G)        */
2757ec142c44SVidya Sagar		reg-names = "appl", "atu_dma", "dbi", "addr_space";
2758ec142c44SVidya Sagar
2759ec142c44SVidya Sagar		num-lanes = <4>;
2760ec142c44SVidya Sagar
2761ec142c44SVidya Sagar		clocks = <&bpmp TEGRA234_CLK_PEX2_C10_CORE>;
2762ec142c44SVidya Sagar		clock-names = "core";
2763ec142c44SVidya Sagar
2764ec142c44SVidya Sagar		resets = <&bpmp TEGRA234_RESET_PEX2_CORE_10_APB>,
2765ec142c44SVidya Sagar			 <&bpmp TEGRA234_RESET_PEX2_CORE_10>;
2766ec142c44SVidya Sagar		reset-names = "apb", "core";
2767ec142c44SVidya Sagar
2768ec142c44SVidya Sagar		interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;	/* controller interrupt */
2769ec142c44SVidya Sagar		interrupt-names = "intr";
2770ec142c44SVidya Sagar
2771ec142c44SVidya Sagar		nvidia,bpmp = <&bpmp 10>;
2772ec142c44SVidya Sagar
2773ec142c44SVidya Sagar		nvidia,enable-ext-refclk;
2774ec142c44SVidya Sagar		nvidia,aspm-cmrt-us = <60>;
2775ec142c44SVidya Sagar		nvidia,aspm-pwr-on-t-us = <20>;
2776ec142c44SVidya Sagar		nvidia,aspm-l0s-entrance-latency-us = <3>;
2777ec142c44SVidya Sagar
2778ec142c44SVidya Sagar		interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE10AR &emc>,
2779ec142c44SVidya Sagar				<&mc TEGRA234_MEMORY_CLIENT_PCIE10AW &emc>;
2780ec142c44SVidya Sagar		interconnect-names = "dma-mem", "write";
2781ec142c44SVidya Sagar		iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>;
2782ec142c44SVidya Sagar		iommu-map-mask = <0x0>;
2783ec142c44SVidya Sagar		dma-coherent;
2784ec142c44SVidya Sagar
2785ec142c44SVidya Sagar		status = "disabled";
2786ec142c44SVidya Sagar	};
2787ec142c44SVidya Sagar
27887fa30752SThierry Reding	sram@40000000 {
278963944891SThierry Reding		compatible = "nvidia,tegra234-sysram", "mmio-sram";
279098094be1SMikko Perttunen		reg = <0x0 0x40000000 0x0 0x80000>;
279163944891SThierry Reding		#address-cells = <1>;
279263944891SThierry Reding		#size-cells = <1>;
279398094be1SMikko Perttunen		ranges = <0x0 0x0 0x40000000 0x80000>;
279461192a9dSMikko Perttunen		no-memory-wc;
279563944891SThierry Reding
279698094be1SMikko Perttunen		cpu_bpmp_tx: sram@70000 {
279798094be1SMikko Perttunen			reg = <0x70000 0x1000>;
279863944891SThierry Reding			label = "cpu-bpmp-tx";
279963944891SThierry Reding			pool;
280063944891SThierry Reding		};
280163944891SThierry Reding
280298094be1SMikko Perttunen		cpu_bpmp_rx: sram@71000 {
280398094be1SMikko Perttunen			reg = <0x71000 0x1000>;
280463944891SThierry Reding			label = "cpu-bpmp-rx";
280563944891SThierry Reding			pool;
280663944891SThierry Reding		};
280763944891SThierry Reding	};
280863944891SThierry Reding
280963944891SThierry Reding	bpmp: bpmp {
281063944891SThierry Reding		compatible = "nvidia,tegra234-bpmp", "nvidia,tegra186-bpmp";
281163944891SThierry Reding		mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
281263944891SThierry Reding				    TEGRA_HSP_DB_MASTER_BPMP>;
28137fa30752SThierry Reding		shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>;
281463944891SThierry Reding		#clock-cells = <1>;
281563944891SThierry Reding		#reset-cells = <1>;
281663944891SThierry Reding		#power-domain-cells = <1>;
28176de481e5SThierry Reding		interconnects = <&mc TEGRA234_MEMORY_CLIENT_BPMPR &emc>,
28186de481e5SThierry Reding				<&mc TEGRA234_MEMORY_CLIENT_BPMPW &emc>,
28196de481e5SThierry Reding				<&mc TEGRA234_MEMORY_CLIENT_BPMPDMAR &emc>,
28206de481e5SThierry Reding				<&mc TEGRA234_MEMORY_CLIENT_BPMPDMAW &emc>;
28216de481e5SThierry Reding		interconnect-names = "read", "write", "dma-mem", "dma-write";
28225710e16aSThierry Reding		iommus = <&smmu_niso1 TEGRA234_SID_BPMP>;
282363944891SThierry Reding
282463944891SThierry Reding		bpmp_i2c: i2c {
282563944891SThierry Reding			compatible = "nvidia,tegra186-bpmp-i2c";
282663944891SThierry Reding			nvidia,bpmp-bus-id = <5>;
282763944891SThierry Reding			#address-cells = <1>;
282863944891SThierry Reding			#size-cells = <0>;
282963944891SThierry Reding		};
283063944891SThierry Reding	};
283163944891SThierry Reding
283263944891SThierry Reding	cpus {
283363944891SThierry Reding		#address-cells = <1>;
283463944891SThierry Reding		#size-cells = <0>;
283563944891SThierry Reding
2836a12cf5c3SThierry Reding		cpu0_0: cpu@0 {
2837a12cf5c3SThierry Reding			compatible = "arm,cortex-a78";
283863944891SThierry Reding			device_type = "cpu";
2839a12cf5c3SThierry Reding			reg = <0x00000>;
284063944891SThierry Reding
284163944891SThierry Reding			enable-method = "psci";
2842a12cf5c3SThierry Reding
2843a12cf5c3SThierry Reding			i-cache-size = <65536>;
2844a12cf5c3SThierry Reding			i-cache-line-size = <64>;
2845a12cf5c3SThierry Reding			i-cache-sets = <256>;
2846a12cf5c3SThierry Reding			d-cache-size = <65536>;
2847a12cf5c3SThierry Reding			d-cache-line-size = <64>;
2848a12cf5c3SThierry Reding			d-cache-sets = <256>;
2849a12cf5c3SThierry Reding			next-level-cache = <&l2c0_0>;
285063944891SThierry Reding		};
2851a12cf5c3SThierry Reding
2852a12cf5c3SThierry Reding		cpu0_1: cpu@100 {
2853a12cf5c3SThierry Reding			compatible = "arm,cortex-a78";
2854a12cf5c3SThierry Reding			device_type = "cpu";
2855a12cf5c3SThierry Reding			reg = <0x00100>;
2856a12cf5c3SThierry Reding
2857a12cf5c3SThierry Reding			enable-method = "psci";
2858a12cf5c3SThierry Reding
2859a12cf5c3SThierry Reding			i-cache-size = <65536>;
2860a12cf5c3SThierry Reding			i-cache-line-size = <64>;
2861a12cf5c3SThierry Reding			i-cache-sets = <256>;
2862a12cf5c3SThierry Reding			d-cache-size = <65536>;
2863a12cf5c3SThierry Reding			d-cache-line-size = <64>;
2864a12cf5c3SThierry Reding			d-cache-sets = <256>;
2865a12cf5c3SThierry Reding			next-level-cache = <&l2c0_1>;
2866a12cf5c3SThierry Reding		};
2867a12cf5c3SThierry Reding
2868a12cf5c3SThierry Reding		cpu0_2: cpu@200 {
2869a12cf5c3SThierry Reding			compatible = "arm,cortex-a78";
2870a12cf5c3SThierry Reding			device_type = "cpu";
2871a12cf5c3SThierry Reding			reg = <0x00200>;
2872a12cf5c3SThierry Reding
2873a12cf5c3SThierry Reding			enable-method = "psci";
2874a12cf5c3SThierry Reding
2875a12cf5c3SThierry Reding			i-cache-size = <65536>;
2876a12cf5c3SThierry Reding			i-cache-line-size = <64>;
2877a12cf5c3SThierry Reding			i-cache-sets = <256>;
2878a12cf5c3SThierry Reding			d-cache-size = <65536>;
2879a12cf5c3SThierry Reding			d-cache-line-size = <64>;
2880a12cf5c3SThierry Reding			d-cache-sets = <256>;
2881a12cf5c3SThierry Reding			next-level-cache = <&l2c0_2>;
2882a12cf5c3SThierry Reding		};
2883a12cf5c3SThierry Reding
2884a12cf5c3SThierry Reding		cpu0_3: cpu@300 {
2885a12cf5c3SThierry Reding			compatible = "arm,cortex-a78";
2886a12cf5c3SThierry Reding			device_type = "cpu";
2887a12cf5c3SThierry Reding			reg = <0x00300>;
2888a12cf5c3SThierry Reding
2889a12cf5c3SThierry Reding			enable-method = "psci";
2890a12cf5c3SThierry Reding
2891a12cf5c3SThierry Reding			i-cache-size = <65536>;
2892a12cf5c3SThierry Reding			i-cache-line-size = <64>;
2893a12cf5c3SThierry Reding			i-cache-sets = <256>;
2894a12cf5c3SThierry Reding			d-cache-size = <65536>;
2895a12cf5c3SThierry Reding			d-cache-line-size = <64>;
2896a12cf5c3SThierry Reding			d-cache-sets = <256>;
2897a12cf5c3SThierry Reding			next-level-cache = <&l2c0_3>;
2898a12cf5c3SThierry Reding		};
2899a12cf5c3SThierry Reding
2900a12cf5c3SThierry Reding		cpu1_0: cpu@10000 {
2901a12cf5c3SThierry Reding			compatible = "arm,cortex-a78";
2902a12cf5c3SThierry Reding			device_type = "cpu";
2903a12cf5c3SThierry Reding			reg = <0x10000>;
2904a12cf5c3SThierry Reding
2905a12cf5c3SThierry Reding			enable-method = "psci";
2906a12cf5c3SThierry Reding
2907a12cf5c3SThierry Reding			i-cache-size = <65536>;
2908a12cf5c3SThierry Reding			i-cache-line-size = <64>;
2909a12cf5c3SThierry Reding			i-cache-sets = <256>;
2910a12cf5c3SThierry Reding			d-cache-size = <65536>;
2911a12cf5c3SThierry Reding			d-cache-line-size = <64>;
2912a12cf5c3SThierry Reding			d-cache-sets = <256>;
2913a12cf5c3SThierry Reding			next-level-cache = <&l2c1_0>;
2914a12cf5c3SThierry Reding		};
2915a12cf5c3SThierry Reding
2916a12cf5c3SThierry Reding		cpu1_1: cpu@10100 {
2917a12cf5c3SThierry Reding			compatible = "arm,cortex-a78";
2918a12cf5c3SThierry Reding			device_type = "cpu";
2919a12cf5c3SThierry Reding			reg = <0x10100>;
2920a12cf5c3SThierry Reding
2921a12cf5c3SThierry Reding			enable-method = "psci";
2922a12cf5c3SThierry Reding
2923a12cf5c3SThierry Reding			i-cache-size = <65536>;
2924a12cf5c3SThierry Reding			i-cache-line-size = <64>;
2925a12cf5c3SThierry Reding			i-cache-sets = <256>;
2926a12cf5c3SThierry Reding			d-cache-size = <65536>;
2927a12cf5c3SThierry Reding			d-cache-line-size = <64>;
2928a12cf5c3SThierry Reding			d-cache-sets = <256>;
2929a12cf5c3SThierry Reding			next-level-cache = <&l2c1_1>;
2930a12cf5c3SThierry Reding		};
2931a12cf5c3SThierry Reding
2932a12cf5c3SThierry Reding		cpu1_2: cpu@10200 {
2933a12cf5c3SThierry Reding			compatible = "arm,cortex-a78";
2934a12cf5c3SThierry Reding			device_type = "cpu";
2935a12cf5c3SThierry Reding			reg = <0x10200>;
2936a12cf5c3SThierry Reding
2937a12cf5c3SThierry Reding			enable-method = "psci";
2938a12cf5c3SThierry Reding
2939a12cf5c3SThierry Reding			i-cache-size = <65536>;
2940a12cf5c3SThierry Reding			i-cache-line-size = <64>;
2941a12cf5c3SThierry Reding			i-cache-sets = <256>;
2942a12cf5c3SThierry Reding			d-cache-size = <65536>;
2943a12cf5c3SThierry Reding			d-cache-line-size = <64>;
2944a12cf5c3SThierry Reding			d-cache-sets = <256>;
2945a12cf5c3SThierry Reding			next-level-cache = <&l2c1_2>;
2946a12cf5c3SThierry Reding		};
2947a12cf5c3SThierry Reding
2948a12cf5c3SThierry Reding		cpu1_3: cpu@10300 {
2949a12cf5c3SThierry Reding			compatible = "arm,cortex-a78";
2950a12cf5c3SThierry Reding			device_type = "cpu";
2951a12cf5c3SThierry Reding			reg = <0x10300>;
2952a12cf5c3SThierry Reding
2953a12cf5c3SThierry Reding			enable-method = "psci";
2954a12cf5c3SThierry Reding
2955a12cf5c3SThierry Reding			i-cache-size = <65536>;
2956a12cf5c3SThierry Reding			i-cache-line-size = <64>;
2957a12cf5c3SThierry Reding			i-cache-sets = <256>;
2958a12cf5c3SThierry Reding			d-cache-size = <65536>;
2959a12cf5c3SThierry Reding			d-cache-line-size = <64>;
2960a12cf5c3SThierry Reding			d-cache-sets = <256>;
2961a12cf5c3SThierry Reding			next-level-cache = <&l2c1_3>;
2962a12cf5c3SThierry Reding		};
2963a12cf5c3SThierry Reding
2964a12cf5c3SThierry Reding		cpu2_0: cpu@20000 {
2965a12cf5c3SThierry Reding			compatible = "arm,cortex-a78";
2966a12cf5c3SThierry Reding			device_type = "cpu";
2967a12cf5c3SThierry Reding			reg = <0x20000>;
2968a12cf5c3SThierry Reding
2969a12cf5c3SThierry Reding			enable-method = "psci";
2970a12cf5c3SThierry Reding
2971a12cf5c3SThierry Reding			i-cache-size = <65536>;
2972a12cf5c3SThierry Reding			i-cache-line-size = <64>;
2973a12cf5c3SThierry Reding			i-cache-sets = <256>;
2974a12cf5c3SThierry Reding			d-cache-size = <65536>;
2975a12cf5c3SThierry Reding			d-cache-line-size = <64>;
2976a12cf5c3SThierry Reding			d-cache-sets = <256>;
2977a12cf5c3SThierry Reding			next-level-cache = <&l2c2_0>;
2978a12cf5c3SThierry Reding		};
2979a12cf5c3SThierry Reding
2980a12cf5c3SThierry Reding		cpu2_1: cpu@20100 {
2981a12cf5c3SThierry Reding			compatible = "arm,cortex-a78";
2982a12cf5c3SThierry Reding			device_type = "cpu";
2983a12cf5c3SThierry Reding			reg = <0x20100>;
2984a12cf5c3SThierry Reding
2985a12cf5c3SThierry Reding			enable-method = "psci";
2986a12cf5c3SThierry Reding
2987a12cf5c3SThierry Reding			i-cache-size = <65536>;
2988a12cf5c3SThierry Reding			i-cache-line-size = <64>;
2989a12cf5c3SThierry Reding			i-cache-sets = <256>;
2990a12cf5c3SThierry Reding			d-cache-size = <65536>;
2991a12cf5c3SThierry Reding			d-cache-line-size = <64>;
2992a12cf5c3SThierry Reding			d-cache-sets = <256>;
2993a12cf5c3SThierry Reding			next-level-cache = <&l2c2_1>;
2994a12cf5c3SThierry Reding		};
2995a12cf5c3SThierry Reding
2996a12cf5c3SThierry Reding		cpu2_2: cpu@20200 {
2997a12cf5c3SThierry Reding			compatible = "arm,cortex-a78";
2998a12cf5c3SThierry Reding			device_type = "cpu";
2999a12cf5c3SThierry Reding			reg = <0x20200>;
3000a12cf5c3SThierry Reding
3001a12cf5c3SThierry Reding			enable-method = "psci";
3002a12cf5c3SThierry Reding
3003a12cf5c3SThierry Reding			i-cache-size = <65536>;
3004a12cf5c3SThierry Reding			i-cache-line-size = <64>;
3005a12cf5c3SThierry Reding			i-cache-sets = <256>;
3006a12cf5c3SThierry Reding			d-cache-size = <65536>;
3007a12cf5c3SThierry Reding			d-cache-line-size = <64>;
3008a12cf5c3SThierry Reding			d-cache-sets = <256>;
3009a12cf5c3SThierry Reding			next-level-cache = <&l2c2_2>;
3010a12cf5c3SThierry Reding		};
3011a12cf5c3SThierry Reding
3012a12cf5c3SThierry Reding		cpu2_3: cpu@20300 {
3013a12cf5c3SThierry Reding			compatible = "arm,cortex-a78";
3014a12cf5c3SThierry Reding			device_type = "cpu";
3015a12cf5c3SThierry Reding			reg = <0x20300>;
3016a12cf5c3SThierry Reding
3017a12cf5c3SThierry Reding			enable-method = "psci";
3018a12cf5c3SThierry Reding
3019a12cf5c3SThierry Reding			i-cache-size = <65536>;
3020a12cf5c3SThierry Reding			i-cache-line-size = <64>;
3021a12cf5c3SThierry Reding			i-cache-sets = <256>;
3022a12cf5c3SThierry Reding			d-cache-size = <65536>;
3023a12cf5c3SThierry Reding			d-cache-line-size = <64>;
3024a12cf5c3SThierry Reding			d-cache-sets = <256>;
3025a12cf5c3SThierry Reding			next-level-cache = <&l2c2_3>;
3026a12cf5c3SThierry Reding		};
3027a12cf5c3SThierry Reding
3028a12cf5c3SThierry Reding		cpu-map {
3029a12cf5c3SThierry Reding			cluster0 {
3030a12cf5c3SThierry Reding				core0 {
3031a12cf5c3SThierry Reding					cpu = <&cpu0_0>;
3032a12cf5c3SThierry Reding				};
3033a12cf5c3SThierry Reding
3034a12cf5c3SThierry Reding				core1 {
3035a12cf5c3SThierry Reding					cpu = <&cpu0_1>;
3036a12cf5c3SThierry Reding				};
3037a12cf5c3SThierry Reding
3038a12cf5c3SThierry Reding				core2 {
3039a12cf5c3SThierry Reding					cpu = <&cpu0_2>;
3040a12cf5c3SThierry Reding				};
3041a12cf5c3SThierry Reding
3042a12cf5c3SThierry Reding				core3 {
3043a12cf5c3SThierry Reding					cpu = <&cpu0_3>;
3044a12cf5c3SThierry Reding				};
3045a12cf5c3SThierry Reding			};
3046a12cf5c3SThierry Reding
3047a12cf5c3SThierry Reding			cluster1 {
3048a12cf5c3SThierry Reding				core0 {
3049a12cf5c3SThierry Reding					cpu = <&cpu1_0>;
3050a12cf5c3SThierry Reding				};
3051a12cf5c3SThierry Reding
3052a12cf5c3SThierry Reding				core1 {
3053a12cf5c3SThierry Reding					cpu = <&cpu1_1>;
3054a12cf5c3SThierry Reding				};
3055a12cf5c3SThierry Reding
3056a12cf5c3SThierry Reding				core2 {
3057a12cf5c3SThierry Reding					cpu = <&cpu1_2>;
3058a12cf5c3SThierry Reding				};
3059a12cf5c3SThierry Reding
3060a12cf5c3SThierry Reding				core3 {
3061a12cf5c3SThierry Reding					cpu = <&cpu1_3>;
3062a12cf5c3SThierry Reding				};
3063a12cf5c3SThierry Reding			};
3064a12cf5c3SThierry Reding
3065a12cf5c3SThierry Reding			cluster2 {
3066a12cf5c3SThierry Reding				core0 {
3067a12cf5c3SThierry Reding					cpu = <&cpu2_0>;
3068a12cf5c3SThierry Reding				};
3069a12cf5c3SThierry Reding
3070a12cf5c3SThierry Reding				core1 {
3071a12cf5c3SThierry Reding					cpu = <&cpu2_1>;
3072a12cf5c3SThierry Reding				};
3073a12cf5c3SThierry Reding
3074a12cf5c3SThierry Reding				core2 {
3075a12cf5c3SThierry Reding					cpu = <&cpu2_2>;
3076a12cf5c3SThierry Reding				};
3077a12cf5c3SThierry Reding
3078a12cf5c3SThierry Reding				core3 {
3079a12cf5c3SThierry Reding					cpu = <&cpu2_3>;
3080a12cf5c3SThierry Reding				};
3081a12cf5c3SThierry Reding			};
3082a12cf5c3SThierry Reding		};
3083a12cf5c3SThierry Reding
3084a12cf5c3SThierry Reding		l2c0_0: l2-cache00 {
3085a12cf5c3SThierry Reding			cache-size = <262144>;
3086a12cf5c3SThierry Reding			cache-line-size = <64>;
3087a12cf5c3SThierry Reding			cache-sets = <512>;
3088a12cf5c3SThierry Reding			cache-unified;
3089a12cf5c3SThierry Reding			next-level-cache = <&l3c0>;
3090a12cf5c3SThierry Reding		};
3091a12cf5c3SThierry Reding
3092a12cf5c3SThierry Reding		l2c0_1: l2-cache01 {
3093a12cf5c3SThierry Reding			cache-size = <262144>;
3094a12cf5c3SThierry Reding			cache-line-size = <64>;
3095a12cf5c3SThierry Reding			cache-sets = <512>;
3096a12cf5c3SThierry Reding			cache-unified;
3097a12cf5c3SThierry Reding			next-level-cache = <&l3c0>;
3098a12cf5c3SThierry Reding		};
3099a12cf5c3SThierry Reding
3100a12cf5c3SThierry Reding		l2c0_2: l2-cache02 {
3101a12cf5c3SThierry Reding			cache-size = <262144>;
3102a12cf5c3SThierry Reding			cache-line-size = <64>;
3103a12cf5c3SThierry Reding			cache-sets = <512>;
3104a12cf5c3SThierry Reding			cache-unified;
3105a12cf5c3SThierry Reding			next-level-cache = <&l3c0>;
3106a12cf5c3SThierry Reding		};
3107a12cf5c3SThierry Reding
3108a12cf5c3SThierry Reding		l2c0_3: l2-cache03 {
3109a12cf5c3SThierry Reding			cache-size = <262144>;
3110a12cf5c3SThierry Reding			cache-line-size = <64>;
3111a12cf5c3SThierry Reding			cache-sets = <512>;
3112a12cf5c3SThierry Reding			cache-unified;
3113a12cf5c3SThierry Reding			next-level-cache = <&l3c0>;
3114a12cf5c3SThierry Reding		};
3115a12cf5c3SThierry Reding
3116a12cf5c3SThierry Reding		l2c1_0: l2-cache10 {
3117a12cf5c3SThierry Reding			cache-size = <262144>;
3118a12cf5c3SThierry Reding			cache-line-size = <64>;
3119a12cf5c3SThierry Reding			cache-sets = <512>;
3120a12cf5c3SThierry Reding			cache-unified;
3121a12cf5c3SThierry Reding			next-level-cache = <&l3c1>;
3122a12cf5c3SThierry Reding		};
3123a12cf5c3SThierry Reding
3124a12cf5c3SThierry Reding		l2c1_1: l2-cache11 {
3125a12cf5c3SThierry Reding			cache-size = <262144>;
3126a12cf5c3SThierry Reding			cache-line-size = <64>;
3127a12cf5c3SThierry Reding			cache-sets = <512>;
3128a12cf5c3SThierry Reding			cache-unified;
3129a12cf5c3SThierry Reding			next-level-cache = <&l3c1>;
3130a12cf5c3SThierry Reding		};
3131a12cf5c3SThierry Reding
3132a12cf5c3SThierry Reding		l2c1_2: l2-cache12 {
3133a12cf5c3SThierry Reding			cache-size = <262144>;
3134a12cf5c3SThierry Reding			cache-line-size = <64>;
3135a12cf5c3SThierry Reding			cache-sets = <512>;
3136a12cf5c3SThierry Reding			cache-unified;
3137a12cf5c3SThierry Reding			next-level-cache = <&l3c1>;
3138a12cf5c3SThierry Reding		};
3139a12cf5c3SThierry Reding
3140a12cf5c3SThierry Reding		l2c1_3: l2-cache13 {
3141a12cf5c3SThierry Reding			cache-size = <262144>;
3142a12cf5c3SThierry Reding			cache-line-size = <64>;
3143a12cf5c3SThierry Reding			cache-sets = <512>;
3144a12cf5c3SThierry Reding			cache-unified;
3145a12cf5c3SThierry Reding			next-level-cache = <&l3c1>;
3146a12cf5c3SThierry Reding		};
3147a12cf5c3SThierry Reding
3148a12cf5c3SThierry Reding		l2c2_0: l2-cache20 {
3149a12cf5c3SThierry Reding			cache-size = <262144>;
3150a12cf5c3SThierry Reding			cache-line-size = <64>;
3151a12cf5c3SThierry Reding			cache-sets = <512>;
3152a12cf5c3SThierry Reding			cache-unified;
3153a12cf5c3SThierry Reding			next-level-cache = <&l3c2>;
3154a12cf5c3SThierry Reding		};
3155a12cf5c3SThierry Reding
3156a12cf5c3SThierry Reding		l2c2_1: l2-cache21 {
3157a12cf5c3SThierry Reding			cache-size = <262144>;
3158a12cf5c3SThierry Reding			cache-line-size = <64>;
3159a12cf5c3SThierry Reding			cache-sets = <512>;
3160a12cf5c3SThierry Reding			cache-unified;
3161a12cf5c3SThierry Reding			next-level-cache = <&l3c2>;
3162a12cf5c3SThierry Reding		};
3163a12cf5c3SThierry Reding
3164a12cf5c3SThierry Reding		l2c2_2: l2-cache22 {
3165a12cf5c3SThierry Reding			cache-size = <262144>;
3166a12cf5c3SThierry Reding			cache-line-size = <64>;
3167a12cf5c3SThierry Reding			cache-sets = <512>;
3168a12cf5c3SThierry Reding			cache-unified;
3169a12cf5c3SThierry Reding			next-level-cache = <&l3c2>;
3170a12cf5c3SThierry Reding		};
3171a12cf5c3SThierry Reding
3172a12cf5c3SThierry Reding		l2c2_3: l2-cache23 {
3173a12cf5c3SThierry Reding			cache-size = <262144>;
3174a12cf5c3SThierry Reding			cache-line-size = <64>;
3175a12cf5c3SThierry Reding			cache-sets = <512>;
3176a12cf5c3SThierry Reding			cache-unified;
3177a12cf5c3SThierry Reding			next-level-cache = <&l3c2>;
3178a12cf5c3SThierry Reding		};
3179a12cf5c3SThierry Reding
3180a12cf5c3SThierry Reding		l3c0: l3-cache0 {
3181a12cf5c3SThierry Reding			cache-size = <2097152>;
3182a12cf5c3SThierry Reding			cache-line-size = <64>;
3183a12cf5c3SThierry Reding			cache-sets = <2048>;
3184a12cf5c3SThierry Reding		};
3185a12cf5c3SThierry Reding
3186a12cf5c3SThierry Reding		l3c1: l3-cache1 {
3187a12cf5c3SThierry Reding			cache-size = <2097152>;
3188a12cf5c3SThierry Reding			cache-line-size = <64>;
3189a12cf5c3SThierry Reding			cache-sets = <2048>;
3190a12cf5c3SThierry Reding		};
3191a12cf5c3SThierry Reding
3192a12cf5c3SThierry Reding		l3c2: l3-cache2 {
3193a12cf5c3SThierry Reding			cache-size = <2097152>;
3194a12cf5c3SThierry Reding			cache-line-size = <64>;
3195a12cf5c3SThierry Reding			cache-sets = <2048>;
3196a12cf5c3SThierry Reding		};
3197a12cf5c3SThierry Reding	};
3198a12cf5c3SThierry Reding
3199a12cf5c3SThierry Reding	pmu {
3200a12cf5c3SThierry Reding		compatible = "arm,cortex-a78-pmu";
3201a12cf5c3SThierry Reding		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
3202a12cf5c3SThierry Reding		status = "okay";
320363944891SThierry Reding	};
320463944891SThierry Reding
320563944891SThierry Reding	psci {
320663944891SThierry Reding		compatible = "arm,psci-1.0";
320763944891SThierry Reding		status = "okay";
320863944891SThierry Reding		method = "smc";
320963944891SThierry Reding	};
321063944891SThierry Reding
321106ad2ec4SMikko Perttunen	tcu: serial {
321206ad2ec4SMikko Perttunen		compatible = "nvidia,tegra234-tcu", "nvidia,tegra194-tcu";
321306ad2ec4SMikko Perttunen		mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>,
321406ad2ec4SMikko Perttunen			 <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>;
321506ad2ec4SMikko Perttunen		mbox-names = "rx", "tx";
321606ad2ec4SMikko Perttunen		status = "disabled";
321706ad2ec4SMikko Perttunen	};
321806ad2ec4SMikko Perttunen
321909614acdSSameer Pujar	sound {
322009614acdSSameer Pujar		status = "disabled";
322109614acdSSameer Pujar
322209614acdSSameer Pujar		clocks = <&bpmp TEGRA234_CLK_PLLA>,
322309614acdSSameer Pujar			 <&bpmp TEGRA234_CLK_PLLA_OUT0>;
322409614acdSSameer Pujar		clock-names = "pll_a", "plla_out0";
322509614acdSSameer Pujar		assigned-clocks = <&bpmp TEGRA234_CLK_PLLA>,
322609614acdSSameer Pujar				  <&bpmp TEGRA234_CLK_PLLA_OUT0>,
322709614acdSSameer Pujar				  <&bpmp TEGRA234_CLK_AUD_MCLK>;
322809614acdSSameer Pujar		assigned-clock-parents = <0>,
322909614acdSSameer Pujar					 <&bpmp TEGRA234_CLK_PLLA>,
323009614acdSSameer Pujar					 <&bpmp TEGRA234_CLK_PLLA_OUT0>;
323109614acdSSameer Pujar	};
323209614acdSSameer Pujar
323363944891SThierry Reding	timer {
323463944891SThierry Reding		compatible = "arm,armv8-timer";
323563944891SThierry Reding		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
323663944891SThierry Reding			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
323763944891SThierry Reding			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
323863944891SThierry Reding			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
323963944891SThierry Reding		interrupt-parent = <&gic>;
324063944891SThierry Reding		always-on;
324163944891SThierry Reding	};
324263944891SThierry Reding};
3243