163944891SThierry Reding// SPDX-License-Identifier: GPL-2.0 263944891SThierry Reding 363944891SThierry Reding#include <dt-bindings/clock/tegra234-clock.h> 4*699349e0SThierry Reding#include <dt-bindings/gpio/tegra234-gpio.h> 563944891SThierry Reding#include <dt-bindings/interrupt-controller/arm-gic.h> 663944891SThierry Reding#include <dt-bindings/mailbox/tegra186-hsp.h> 7eed280dfSThierry Reding#include <dt-bindings/memory/tegra234-mc.h> 863944891SThierry Reding#include <dt-bindings/reset/tegra234-reset.h> 963944891SThierry Reding 1063944891SThierry Reding/ { 1163944891SThierry Reding compatible = "nvidia,tegra234"; 1263944891SThierry Reding interrupt-parent = <&gic>; 1363944891SThierry Reding #address-cells = <2>; 1463944891SThierry Reding #size-cells = <2>; 1563944891SThierry Reding 1663944891SThierry Reding bus@0 { 1763944891SThierry Reding compatible = "simple-bus"; 1863944891SThierry Reding #address-cells = <1>; 1963944891SThierry Reding #size-cells = <1>; 2063944891SThierry Reding 2163944891SThierry Reding ranges = <0x0 0x0 0x0 0x40000000>; 2263944891SThierry Reding 2363944891SThierry Reding misc@100000 { 2463944891SThierry Reding compatible = "nvidia,tegra234-misc"; 2563944891SThierry Reding reg = <0x00100000 0xf000>, 2663944891SThierry Reding <0x0010f000 0x1000>; 2763944891SThierry Reding status = "okay"; 2863944891SThierry Reding }; 2963944891SThierry Reding 30f0e12668SThierry Reding gpio: gpio@2200000 { 31f0e12668SThierry Reding compatible = "nvidia,tegra234-gpio"; 32f0e12668SThierry Reding reg-names = "security", "gpio"; 33f0e12668SThierry Reding reg = <0x02200000 0x10000>, 34f0e12668SThierry Reding <0x02210000 0x10000>; 35f0e12668SThierry Reding interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 36f0e12668SThierry Reding <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 37f0e12668SThierry Reding <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 38f0e12668SThierry Reding <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, 39f0e12668SThierry Reding <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 40f0e12668SThierry Reding <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 41f0e12668SThierry Reding <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 42f0e12668SThierry Reding <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 43f0e12668SThierry Reding <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 44f0e12668SThierry Reding <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 45f0e12668SThierry Reding <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 46f0e12668SThierry Reding <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 47f0e12668SThierry Reding <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 48f0e12668SThierry Reding <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 49f0e12668SThierry Reding <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 50f0e12668SThierry Reding <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 51f0e12668SThierry Reding <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 52f0e12668SThierry Reding <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 53f0e12668SThierry Reding <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 54f0e12668SThierry Reding <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 55f0e12668SThierry Reding <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 56f0e12668SThierry Reding <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 57f0e12668SThierry Reding <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 58f0e12668SThierry Reding <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 59f0e12668SThierry Reding <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 60f0e12668SThierry Reding <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 61f0e12668SThierry Reding <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 62f0e12668SThierry Reding <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 63f0e12668SThierry Reding <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 64f0e12668SThierry Reding <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 65f0e12668SThierry Reding <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 66f0e12668SThierry Reding <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 67f0e12668SThierry Reding <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 68f0e12668SThierry Reding <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 69f0e12668SThierry Reding <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 70f0e12668SThierry Reding <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 71f0e12668SThierry Reding <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 72f0e12668SThierry Reding <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 73f0e12668SThierry Reding <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 74f0e12668SThierry Reding <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 75f0e12668SThierry Reding <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 76f0e12668SThierry Reding <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 77f0e12668SThierry Reding <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 78f0e12668SThierry Reding <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 79f0e12668SThierry Reding <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 80f0e12668SThierry Reding <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 81f0e12668SThierry Reding <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 82f0e12668SThierry Reding <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 83f0e12668SThierry Reding #interrupt-cells = <2>; 84f0e12668SThierry Reding interrupt-controller; 85f0e12668SThierry Reding #gpio-cells = <2>; 86f0e12668SThierry Reding gpio-controller; 87f0e12668SThierry Reding }; 88f0e12668SThierry Reding 89eed280dfSThierry Reding mc: memory-controller@2c00000 { 90eed280dfSThierry Reding compatible = "nvidia,tegra234-mc"; 91eed280dfSThierry Reding reg = <0x02c00000 0x100000>, 92eed280dfSThierry Reding <0x02b80000 0x040000>, 93eed280dfSThierry Reding <0x01700000 0x100000>; 94eed280dfSThierry Reding interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 95eed280dfSThierry Reding #interconnect-cells = <1>; 96eed280dfSThierry Reding status = "okay"; 97eed280dfSThierry Reding 98eed280dfSThierry Reding #address-cells = <2>; 99eed280dfSThierry Reding #size-cells = <2>; 100eed280dfSThierry Reding 101eed280dfSThierry Reding ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>, 102eed280dfSThierry Reding <0x02b80000 0x0 0x02b80000 0x0 0x040000>, 103eed280dfSThierry Reding <0x02c00000 0x0 0x02c00000 0x0 0x100000>; 104eed280dfSThierry Reding 105eed280dfSThierry Reding /* 106eed280dfSThierry Reding * Bit 39 of addresses passing through the memory 107eed280dfSThierry Reding * controller selects the XBAR format used when memory 108eed280dfSThierry Reding * is accessed. This is used to transparently access 109eed280dfSThierry Reding * memory in the XBAR format used by the discrete GPU 110eed280dfSThierry Reding * (bit 39 set) or Tegra (bit 39 clear). 111eed280dfSThierry Reding * 112eed280dfSThierry Reding * As a consequence, the operating system must ensure 113eed280dfSThierry Reding * that bit 39 is never used implicitly, for example 114eed280dfSThierry Reding * via an I/O virtual address mapping of an IOMMU. If 115eed280dfSThierry Reding * devices require access to the XBAR switch, their 116eed280dfSThierry Reding * drivers must set this bit explicitly. 117eed280dfSThierry Reding * 118eed280dfSThierry Reding * Limit the DMA range for memory clients to [38:0]. 119eed280dfSThierry Reding */ 120eed280dfSThierry Reding dma-ranges = <0x0 0x0 0x0 0x80 0x0>; 121eed280dfSThierry Reding 122eed280dfSThierry Reding emc: external-memory-controller@2c60000 { 123eed280dfSThierry Reding compatible = "nvidia,tegra234-emc"; 124eed280dfSThierry Reding reg = <0x0 0x02c60000 0x0 0x90000>, 125eed280dfSThierry Reding <0x0 0x01780000 0x0 0x80000>; 126eed280dfSThierry Reding interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 127eed280dfSThierry Reding clocks = <&bpmp TEGRA234_CLK_EMC>; 128eed280dfSThierry Reding clock-names = "emc"; 129eed280dfSThierry Reding status = "okay"; 130eed280dfSThierry Reding 131eed280dfSThierry Reding #interconnect-cells = <0>; 132eed280dfSThierry Reding 133eed280dfSThierry Reding nvidia,bpmp = <&bpmp>; 134eed280dfSThierry Reding }; 135eed280dfSThierry Reding }; 136eed280dfSThierry Reding 13763944891SThierry Reding uarta: serial@3100000 { 13863944891SThierry Reding compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart"; 13963944891SThierry Reding reg = <0x03100000 0x10000>; 14063944891SThierry Reding interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 14163944891SThierry Reding clocks = <&bpmp TEGRA234_CLK_UARTA>; 14263944891SThierry Reding clock-names = "serial"; 14363944891SThierry Reding resets = <&bpmp TEGRA234_RESET_UARTA>; 14463944891SThierry Reding reset-names = "serial"; 14563944891SThierry Reding status = "disabled"; 14663944891SThierry Reding }; 14763944891SThierry Reding 148156af9deSAkhil R gen1_i2c: i2c@3160000 { 149156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 150156af9deSAkhil R reg = <0x3160000 0x100>; 151156af9deSAkhil R status = "disabled"; 152156af9deSAkhil R interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 153156af9deSAkhil R clock-frequency = <400000>; 154156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C1 155156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 156156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C1>; 157156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 158156af9deSAkhil R clock-names = "div-clk", "parent"; 159156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C1>; 160156af9deSAkhil R reset-names = "i2c"; 161156af9deSAkhil R }; 162156af9deSAkhil R 163156af9deSAkhil R cam_i2c: i2c@3180000 { 164156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 165156af9deSAkhil R reg = <0x3180000 0x100>; 166156af9deSAkhil R interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 167156af9deSAkhil R status = "disabled"; 168156af9deSAkhil R clock-frequency = <400000>; 169156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C3 170156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 171156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C3>; 172156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 173156af9deSAkhil R clock-names = "div-clk", "parent"; 174156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C3>; 175156af9deSAkhil R reset-names = "i2c"; 176156af9deSAkhil R }; 177156af9deSAkhil R 178156af9deSAkhil R dp_aux_ch1_i2c: i2c@3190000 { 179156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 180156af9deSAkhil R reg = <0x3190000 0x100>; 181156af9deSAkhil R interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 182156af9deSAkhil R status = "disabled"; 183156af9deSAkhil R clock-frequency = <100000>; 184156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C4 185156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 186156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C4>; 187156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 188156af9deSAkhil R clock-names = "div-clk", "parent"; 189156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C4>; 190156af9deSAkhil R reset-names = "i2c"; 191156af9deSAkhil R }; 192156af9deSAkhil R 193156af9deSAkhil R dp_aux_ch0_i2c: i2c@31b0000 { 194156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 195156af9deSAkhil R reg = <0x31b0000 0x100>; 196156af9deSAkhil R interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 197156af9deSAkhil R status = "disabled"; 198156af9deSAkhil R clock-frequency = <100000>; 199156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C6 200156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 201156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C6>; 202156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 203156af9deSAkhil R clock-names = "div-clk", "parent"; 204156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C6>; 205156af9deSAkhil R reset-names = "i2c"; 206156af9deSAkhil R }; 207156af9deSAkhil R 208156af9deSAkhil R dp_aux_ch2_i2c: i2c@31c0000 { 209156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 210156af9deSAkhil R reg = <0x31c0000 0x100>; 211156af9deSAkhil R interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 212156af9deSAkhil R status = "disabled"; 213156af9deSAkhil R clock-frequency = <100000>; 214156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C7 215156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 216156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C7>; 217156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 218156af9deSAkhil R clock-names = "div-clk", "parent"; 219156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C7>; 220156af9deSAkhil R reset-names = "i2c"; 221156af9deSAkhil R }; 222156af9deSAkhil R 223156af9deSAkhil R dp_aux_ch3_i2c: i2c@31e0000 { 224156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 225156af9deSAkhil R reg = <0x31e0000 0x100>; 226156af9deSAkhil R interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 227156af9deSAkhil R status = "disabled"; 228156af9deSAkhil R clock-frequency = <100000>; 229156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C9 230156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 231156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C9>; 232156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 233156af9deSAkhil R clock-names = "div-clk", "parent"; 234156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C9>; 235156af9deSAkhil R reset-names = "i2c"; 236156af9deSAkhil R }; 237156af9deSAkhil R 2385e69088dSAkhil R pwm1: pwm@3280000 { 2395e69088dSAkhil R compatible = "nvidia,tegra194-pwm", 2405e69088dSAkhil R "nvidia,tegra186-pwm"; 2415e69088dSAkhil R reg = <0x3280000 0x10000>; 2425e69088dSAkhil R clocks = <&bpmp TEGRA234_CLK_PWM1>; 2435e69088dSAkhil R clock-names = "pwm"; 2445e69088dSAkhil R resets = <&bpmp TEGRA234_RESET_PWM1>; 2455e69088dSAkhil R reset-names = "pwm"; 2465e69088dSAkhil R status = "disabled"; 2475e69088dSAkhil R #pwm-cells = <2>; 2485e69088dSAkhil R }; 2495e69088dSAkhil R 25063944891SThierry Reding mmc@3460000 { 25163944891SThierry Reding compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci"; 25263944891SThierry Reding reg = <0x03460000 0x20000>; 25363944891SThierry Reding interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 254e086d82dSMikko Perttunen clocks = <&bpmp TEGRA234_CLK_SDMMC4>, 255e086d82dSMikko Perttunen <&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>; 256e086d82dSMikko Perttunen clock-names = "sdhci", "tmclk"; 257e086d82dSMikko Perttunen assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC4>, 258e086d82dSMikko Perttunen <&bpmp TEGRA234_CLK_PLLC4>; 259e086d82dSMikko Perttunen assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4>; 26063944891SThierry Reding resets = <&bpmp TEGRA234_RESET_SDMMC4>; 26163944891SThierry Reding reset-names = "sdhci"; 2626de481e5SThierry Reding interconnects = <&mc TEGRA234_MEMORY_CLIENT_SDMMCRAB &emc>, 2636de481e5SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_SDMMCWAB &emc>; 2646de481e5SThierry Reding interconnect-names = "dma-mem", "write"; 265e086d82dSMikko Perttunen nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 266e086d82dSMikko Perttunen nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 267e086d82dSMikko Perttunen nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 268e086d82dSMikko Perttunen nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; 269e086d82dSMikko Perttunen nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 270e086d82dSMikko Perttunen nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>; 271e086d82dSMikko Perttunen nvidia,default-tap = <0x8>; 272e086d82dSMikko Perttunen nvidia,default-trim = <0x14>; 273e086d82dSMikko Perttunen nvidia,dqs-trim = <40>; 274e086d82dSMikko Perttunen supports-cqe; 27563944891SThierry Reding status = "disabled"; 27663944891SThierry Reding }; 27763944891SThierry Reding 27863944891SThierry Reding fuse@3810000 { 27963944891SThierry Reding compatible = "nvidia,tegra234-efuse"; 28063944891SThierry Reding reg = <0x03810000 0x10000>; 28163944891SThierry Reding clocks = <&bpmp TEGRA234_CLK_FUSE>; 28263944891SThierry Reding clock-names = "fuse"; 28363944891SThierry Reding }; 28463944891SThierry Reding 28563944891SThierry Reding hsp_top0: hsp@3c00000 { 28663944891SThierry Reding compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; 28763944891SThierry Reding reg = <0x03c00000 0xa0000>; 28863944891SThierry Reding interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 28963944891SThierry Reding <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 29063944891SThierry Reding <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 29163944891SThierry Reding <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 29263944891SThierry Reding <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 29363944891SThierry Reding <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 29463944891SThierry Reding <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 29563944891SThierry Reding <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 29663944891SThierry Reding <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 29763944891SThierry Reding interrupt-names = "doorbell", "shared0", "shared1", "shared2", 29863944891SThierry Reding "shared3", "shared4", "shared5", "shared6", 29963944891SThierry Reding "shared7"; 30063944891SThierry Reding #mbox-cells = <2>; 30163944891SThierry Reding }; 30263944891SThierry Reding 30363944891SThierry Reding hsp_aon: hsp@c150000 { 30463944891SThierry Reding compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; 30563944891SThierry Reding reg = <0x0c150000 0x90000>; 30663944891SThierry Reding interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 30763944891SThierry Reding <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 30863944891SThierry Reding <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 30963944891SThierry Reding <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 31063944891SThierry Reding /* 31163944891SThierry Reding * Shared interrupt 0 is routed only to AON/SPE, so 31263944891SThierry Reding * we only have 4 shared interrupts for the CCPLEX. 31363944891SThierry Reding */ 31463944891SThierry Reding interrupt-names = "shared1", "shared2", "shared3", "shared4"; 31563944891SThierry Reding #mbox-cells = <2>; 31663944891SThierry Reding }; 31763944891SThierry Reding 318156af9deSAkhil R gen2_i2c: i2c@c240000 { 319156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 320156af9deSAkhil R reg = <0xc240000 0x100>; 321156af9deSAkhil R interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 322156af9deSAkhil R status = "disabled"; 323156af9deSAkhil R clock-frequency = <100000>; 324156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C2 325156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 326156af9deSAkhil R clock-names = "div-clk", "parent"; 327156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C2>; 328156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 329156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C2>; 330156af9deSAkhil R reset-names = "i2c"; 331156af9deSAkhil R }; 332156af9deSAkhil R 333156af9deSAkhil R gen8_i2c: i2c@c250000 { 334156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 335156af9deSAkhil R reg = <0xc250000 0x100>; 336156af9deSAkhil R nvidia,hw-instance-id = <0x7>; 337156af9deSAkhil R interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 338156af9deSAkhil R status = "disabled"; 339156af9deSAkhil R clock-frequency = <400000>; 340156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C8 341156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 342156af9deSAkhil R clock-names = "div-clk", "parent"; 343156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C8>; 344156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 345156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C8>; 346156af9deSAkhil R reset-names = "i2c"; 347156af9deSAkhil R }; 348156af9deSAkhil R 34963944891SThierry Reding rtc@c2a0000 { 35063944891SThierry Reding compatible = "nvidia,tegra234-rtc", "nvidia,tegra20-rtc"; 35163944891SThierry Reding reg = <0x0c2a0000 0x10000>; 35263944891SThierry Reding interrupt-parent = <&pmc>; 35363944891SThierry Reding interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 354e537addeSMikko Perttunen clocks = <&bpmp TEGRA234_CLK_CLK_32K>; 355e537addeSMikko Perttunen clock-names = "rtc"; 35663944891SThierry Reding status = "disabled"; 35763944891SThierry Reding }; 35863944891SThierry Reding 359f0e12668SThierry Reding gpio_aon: gpio@c2f0000 { 360f0e12668SThierry Reding compatible = "nvidia,tegra234-gpio-aon"; 361f0e12668SThierry Reding reg-names = "security", "gpio"; 362f0e12668SThierry Reding reg = <0x0c2f0000 0x1000>, 363f0e12668SThierry Reding <0x0c2f1000 0x1000>; 364f0e12668SThierry Reding interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 365f0e12668SThierry Reding <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 366f0e12668SThierry Reding <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 367f0e12668SThierry Reding <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 368f0e12668SThierry Reding #interrupt-cells = <2>; 369f0e12668SThierry Reding interrupt-controller; 370f0e12668SThierry Reding #gpio-cells = <2>; 371f0e12668SThierry Reding gpio-controller; 372f0e12668SThierry Reding }; 373f0e12668SThierry Reding 37463944891SThierry Reding pmc: pmc@c360000 { 37563944891SThierry Reding compatible = "nvidia,tegra234-pmc"; 37663944891SThierry Reding reg = <0x0c360000 0x10000>, 37763944891SThierry Reding <0x0c370000 0x10000>, 37863944891SThierry Reding <0x0c380000 0x10000>, 37963944891SThierry Reding <0x0c390000 0x10000>, 38063944891SThierry Reding <0x0c3a0000 0x10000>; 38163944891SThierry Reding reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 38263944891SThierry Reding 38363944891SThierry Reding #interrupt-cells = <2>; 38463944891SThierry Reding interrupt-controller; 38563944891SThierry Reding }; 38663944891SThierry Reding 38763944891SThierry Reding gic: interrupt-controller@f400000 { 38863944891SThierry Reding compatible = "arm,gic-v3"; 38963944891SThierry Reding reg = <0x0f400000 0x010000>, /* GICD */ 39063944891SThierry Reding <0x0f440000 0x200000>; /* GICR */ 39163944891SThierry Reding interrupt-parent = <&gic>; 39263944891SThierry Reding interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 39363944891SThierry Reding 39463944891SThierry Reding #redistributor-regions = <1>; 39563944891SThierry Reding #interrupt-cells = <3>; 39663944891SThierry Reding interrupt-controller; 39763944891SThierry Reding }; 39863944891SThierry Reding }; 39963944891SThierry Reding 4007fa30752SThierry Reding sram@40000000 { 40163944891SThierry Reding compatible = "nvidia,tegra234-sysram", "mmio-sram"; 40298094be1SMikko Perttunen reg = <0x0 0x40000000 0x0 0x80000>; 40363944891SThierry Reding #address-cells = <1>; 40463944891SThierry Reding #size-cells = <1>; 40598094be1SMikko Perttunen ranges = <0x0 0x0 0x40000000 0x80000>; 40663944891SThierry Reding 40798094be1SMikko Perttunen cpu_bpmp_tx: sram@70000 { 40898094be1SMikko Perttunen reg = <0x70000 0x1000>; 40963944891SThierry Reding label = "cpu-bpmp-tx"; 41063944891SThierry Reding pool; 41163944891SThierry Reding }; 41263944891SThierry Reding 41398094be1SMikko Perttunen cpu_bpmp_rx: sram@71000 { 41498094be1SMikko Perttunen reg = <0x71000 0x1000>; 41563944891SThierry Reding label = "cpu-bpmp-rx"; 41663944891SThierry Reding pool; 41763944891SThierry Reding }; 41863944891SThierry Reding }; 41963944891SThierry Reding 42063944891SThierry Reding bpmp: bpmp { 42163944891SThierry Reding compatible = "nvidia,tegra234-bpmp", "nvidia,tegra186-bpmp"; 42263944891SThierry Reding mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 42363944891SThierry Reding TEGRA_HSP_DB_MASTER_BPMP>; 4247fa30752SThierry Reding shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; 42563944891SThierry Reding #clock-cells = <1>; 42663944891SThierry Reding #reset-cells = <1>; 42763944891SThierry Reding #power-domain-cells = <1>; 4286de481e5SThierry Reding interconnects = <&mc TEGRA234_MEMORY_CLIENT_BPMPR &emc>, 4296de481e5SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_BPMPW &emc>, 4306de481e5SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAR &emc>, 4316de481e5SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAW &emc>; 4326de481e5SThierry Reding interconnect-names = "read", "write", "dma-mem", "dma-write"; 43363944891SThierry Reding 43463944891SThierry Reding bpmp_i2c: i2c { 43563944891SThierry Reding compatible = "nvidia,tegra186-bpmp-i2c"; 43663944891SThierry Reding nvidia,bpmp-bus-id = <5>; 43763944891SThierry Reding #address-cells = <1>; 43863944891SThierry Reding #size-cells = <0>; 43963944891SThierry Reding }; 44063944891SThierry Reding }; 44163944891SThierry Reding 44263944891SThierry Reding cpus { 44363944891SThierry Reding #address-cells = <1>; 44463944891SThierry Reding #size-cells = <0>; 44563944891SThierry Reding 446a12cf5c3SThierry Reding cpu0_0: cpu@0 { 447a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 44863944891SThierry Reding device_type = "cpu"; 449a12cf5c3SThierry Reding reg = <0x00000>; 45063944891SThierry Reding 45163944891SThierry Reding enable-method = "psci"; 452a12cf5c3SThierry Reding 453a12cf5c3SThierry Reding i-cache-size = <65536>; 454a12cf5c3SThierry Reding i-cache-line-size = <64>; 455a12cf5c3SThierry Reding i-cache-sets = <256>; 456a12cf5c3SThierry Reding d-cache-size = <65536>; 457a12cf5c3SThierry Reding d-cache-line-size = <64>; 458a12cf5c3SThierry Reding d-cache-sets = <256>; 459a12cf5c3SThierry Reding next-level-cache = <&l2c0_0>; 46063944891SThierry Reding }; 461a12cf5c3SThierry Reding 462a12cf5c3SThierry Reding cpu0_1: cpu@100 { 463a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 464a12cf5c3SThierry Reding device_type = "cpu"; 465a12cf5c3SThierry Reding reg = <0x00100>; 466a12cf5c3SThierry Reding 467a12cf5c3SThierry Reding enable-method = "psci"; 468a12cf5c3SThierry Reding 469a12cf5c3SThierry Reding i-cache-size = <65536>; 470a12cf5c3SThierry Reding i-cache-line-size = <64>; 471a12cf5c3SThierry Reding i-cache-sets = <256>; 472a12cf5c3SThierry Reding d-cache-size = <65536>; 473a12cf5c3SThierry Reding d-cache-line-size = <64>; 474a12cf5c3SThierry Reding d-cache-sets = <256>; 475a12cf5c3SThierry Reding next-level-cache = <&l2c0_1>; 476a12cf5c3SThierry Reding }; 477a12cf5c3SThierry Reding 478a12cf5c3SThierry Reding cpu0_2: cpu@200 { 479a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 480a12cf5c3SThierry Reding device_type = "cpu"; 481a12cf5c3SThierry Reding reg = <0x00200>; 482a12cf5c3SThierry Reding 483a12cf5c3SThierry Reding enable-method = "psci"; 484a12cf5c3SThierry Reding 485a12cf5c3SThierry Reding i-cache-size = <65536>; 486a12cf5c3SThierry Reding i-cache-line-size = <64>; 487a12cf5c3SThierry Reding i-cache-sets = <256>; 488a12cf5c3SThierry Reding d-cache-size = <65536>; 489a12cf5c3SThierry Reding d-cache-line-size = <64>; 490a12cf5c3SThierry Reding d-cache-sets = <256>; 491a12cf5c3SThierry Reding next-level-cache = <&l2c0_2>; 492a12cf5c3SThierry Reding }; 493a12cf5c3SThierry Reding 494a12cf5c3SThierry Reding cpu0_3: cpu@300 { 495a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 496a12cf5c3SThierry Reding device_type = "cpu"; 497a12cf5c3SThierry Reding reg = <0x00300>; 498a12cf5c3SThierry Reding 499a12cf5c3SThierry Reding enable-method = "psci"; 500a12cf5c3SThierry Reding 501a12cf5c3SThierry Reding i-cache-size = <65536>; 502a12cf5c3SThierry Reding i-cache-line-size = <64>; 503a12cf5c3SThierry Reding i-cache-sets = <256>; 504a12cf5c3SThierry Reding d-cache-size = <65536>; 505a12cf5c3SThierry Reding d-cache-line-size = <64>; 506a12cf5c3SThierry Reding d-cache-sets = <256>; 507a12cf5c3SThierry Reding next-level-cache = <&l2c0_3>; 508a12cf5c3SThierry Reding }; 509a12cf5c3SThierry Reding 510a12cf5c3SThierry Reding cpu1_0: cpu@10000 { 511a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 512a12cf5c3SThierry Reding device_type = "cpu"; 513a12cf5c3SThierry Reding reg = <0x10000>; 514a12cf5c3SThierry Reding 515a12cf5c3SThierry Reding enable-method = "psci"; 516a12cf5c3SThierry Reding 517a12cf5c3SThierry Reding i-cache-size = <65536>; 518a12cf5c3SThierry Reding i-cache-line-size = <64>; 519a12cf5c3SThierry Reding i-cache-sets = <256>; 520a12cf5c3SThierry Reding d-cache-size = <65536>; 521a12cf5c3SThierry Reding d-cache-line-size = <64>; 522a12cf5c3SThierry Reding d-cache-sets = <256>; 523a12cf5c3SThierry Reding next-level-cache = <&l2c1_0>; 524a12cf5c3SThierry Reding }; 525a12cf5c3SThierry Reding 526a12cf5c3SThierry Reding cpu1_1: cpu@10100 { 527a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 528a12cf5c3SThierry Reding device_type = "cpu"; 529a12cf5c3SThierry Reding reg = <0x10100>; 530a12cf5c3SThierry Reding 531a12cf5c3SThierry Reding enable-method = "psci"; 532a12cf5c3SThierry Reding 533a12cf5c3SThierry Reding i-cache-size = <65536>; 534a12cf5c3SThierry Reding i-cache-line-size = <64>; 535a12cf5c3SThierry Reding i-cache-sets = <256>; 536a12cf5c3SThierry Reding d-cache-size = <65536>; 537a12cf5c3SThierry Reding d-cache-line-size = <64>; 538a12cf5c3SThierry Reding d-cache-sets = <256>; 539a12cf5c3SThierry Reding next-level-cache = <&l2c1_1>; 540a12cf5c3SThierry Reding }; 541a12cf5c3SThierry Reding 542a12cf5c3SThierry Reding cpu1_2: cpu@10200 { 543a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 544a12cf5c3SThierry Reding device_type = "cpu"; 545a12cf5c3SThierry Reding reg = <0x10200>; 546a12cf5c3SThierry Reding 547a12cf5c3SThierry Reding enable-method = "psci"; 548a12cf5c3SThierry Reding 549a12cf5c3SThierry Reding i-cache-size = <65536>; 550a12cf5c3SThierry Reding i-cache-line-size = <64>; 551a12cf5c3SThierry Reding i-cache-sets = <256>; 552a12cf5c3SThierry Reding d-cache-size = <65536>; 553a12cf5c3SThierry Reding d-cache-line-size = <64>; 554a12cf5c3SThierry Reding d-cache-sets = <256>; 555a12cf5c3SThierry Reding next-level-cache = <&l2c1_2>; 556a12cf5c3SThierry Reding }; 557a12cf5c3SThierry Reding 558a12cf5c3SThierry Reding cpu1_3: cpu@10300 { 559a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 560a12cf5c3SThierry Reding device_type = "cpu"; 561a12cf5c3SThierry Reding reg = <0x10300>; 562a12cf5c3SThierry Reding 563a12cf5c3SThierry Reding enable-method = "psci"; 564a12cf5c3SThierry Reding 565a12cf5c3SThierry Reding i-cache-size = <65536>; 566a12cf5c3SThierry Reding i-cache-line-size = <64>; 567a12cf5c3SThierry Reding i-cache-sets = <256>; 568a12cf5c3SThierry Reding d-cache-size = <65536>; 569a12cf5c3SThierry Reding d-cache-line-size = <64>; 570a12cf5c3SThierry Reding d-cache-sets = <256>; 571a12cf5c3SThierry Reding next-level-cache = <&l2c1_3>; 572a12cf5c3SThierry Reding }; 573a12cf5c3SThierry Reding 574a12cf5c3SThierry Reding cpu2_0: cpu@20000 { 575a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 576a12cf5c3SThierry Reding device_type = "cpu"; 577a12cf5c3SThierry Reding reg = <0x20000>; 578a12cf5c3SThierry Reding 579a12cf5c3SThierry Reding enable-method = "psci"; 580a12cf5c3SThierry Reding 581a12cf5c3SThierry Reding i-cache-size = <65536>; 582a12cf5c3SThierry Reding i-cache-line-size = <64>; 583a12cf5c3SThierry Reding i-cache-sets = <256>; 584a12cf5c3SThierry Reding d-cache-size = <65536>; 585a12cf5c3SThierry Reding d-cache-line-size = <64>; 586a12cf5c3SThierry Reding d-cache-sets = <256>; 587a12cf5c3SThierry Reding next-level-cache = <&l2c2_0>; 588a12cf5c3SThierry Reding }; 589a12cf5c3SThierry Reding 590a12cf5c3SThierry Reding cpu2_1: cpu@20100 { 591a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 592a12cf5c3SThierry Reding device_type = "cpu"; 593a12cf5c3SThierry Reding reg = <0x20100>; 594a12cf5c3SThierry Reding 595a12cf5c3SThierry Reding enable-method = "psci"; 596a12cf5c3SThierry Reding 597a12cf5c3SThierry Reding i-cache-size = <65536>; 598a12cf5c3SThierry Reding i-cache-line-size = <64>; 599a12cf5c3SThierry Reding i-cache-sets = <256>; 600a12cf5c3SThierry Reding d-cache-size = <65536>; 601a12cf5c3SThierry Reding d-cache-line-size = <64>; 602a12cf5c3SThierry Reding d-cache-sets = <256>; 603a12cf5c3SThierry Reding next-level-cache = <&l2c2_1>; 604a12cf5c3SThierry Reding }; 605a12cf5c3SThierry Reding 606a12cf5c3SThierry Reding cpu2_2: cpu@20200 { 607a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 608a12cf5c3SThierry Reding device_type = "cpu"; 609a12cf5c3SThierry Reding reg = <0x20200>; 610a12cf5c3SThierry Reding 611a12cf5c3SThierry Reding enable-method = "psci"; 612a12cf5c3SThierry Reding 613a12cf5c3SThierry Reding i-cache-size = <65536>; 614a12cf5c3SThierry Reding i-cache-line-size = <64>; 615a12cf5c3SThierry Reding i-cache-sets = <256>; 616a12cf5c3SThierry Reding d-cache-size = <65536>; 617a12cf5c3SThierry Reding d-cache-line-size = <64>; 618a12cf5c3SThierry Reding d-cache-sets = <256>; 619a12cf5c3SThierry Reding next-level-cache = <&l2c2_2>; 620a12cf5c3SThierry Reding }; 621a12cf5c3SThierry Reding 622a12cf5c3SThierry Reding cpu2_3: cpu@20300 { 623a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 624a12cf5c3SThierry Reding device_type = "cpu"; 625a12cf5c3SThierry Reding reg = <0x20300>; 626a12cf5c3SThierry Reding 627a12cf5c3SThierry Reding enable-method = "psci"; 628a12cf5c3SThierry Reding 629a12cf5c3SThierry Reding i-cache-size = <65536>; 630a12cf5c3SThierry Reding i-cache-line-size = <64>; 631a12cf5c3SThierry Reding i-cache-sets = <256>; 632a12cf5c3SThierry Reding d-cache-size = <65536>; 633a12cf5c3SThierry Reding d-cache-line-size = <64>; 634a12cf5c3SThierry Reding d-cache-sets = <256>; 635a12cf5c3SThierry Reding next-level-cache = <&l2c2_3>; 636a12cf5c3SThierry Reding }; 637a12cf5c3SThierry Reding 638a12cf5c3SThierry Reding cpu-map { 639a12cf5c3SThierry Reding cluster0 { 640a12cf5c3SThierry Reding core0 { 641a12cf5c3SThierry Reding cpu = <&cpu0_0>; 642a12cf5c3SThierry Reding }; 643a12cf5c3SThierry Reding 644a12cf5c3SThierry Reding core1 { 645a12cf5c3SThierry Reding cpu = <&cpu0_1>; 646a12cf5c3SThierry Reding }; 647a12cf5c3SThierry Reding 648a12cf5c3SThierry Reding core2 { 649a12cf5c3SThierry Reding cpu = <&cpu0_2>; 650a12cf5c3SThierry Reding }; 651a12cf5c3SThierry Reding 652a12cf5c3SThierry Reding core3 { 653a12cf5c3SThierry Reding cpu = <&cpu0_3>; 654a12cf5c3SThierry Reding }; 655a12cf5c3SThierry Reding }; 656a12cf5c3SThierry Reding 657a12cf5c3SThierry Reding cluster1 { 658a12cf5c3SThierry Reding core0 { 659a12cf5c3SThierry Reding cpu = <&cpu1_0>; 660a12cf5c3SThierry Reding }; 661a12cf5c3SThierry Reding 662a12cf5c3SThierry Reding core1 { 663a12cf5c3SThierry Reding cpu = <&cpu1_1>; 664a12cf5c3SThierry Reding }; 665a12cf5c3SThierry Reding 666a12cf5c3SThierry Reding core2 { 667a12cf5c3SThierry Reding cpu = <&cpu1_2>; 668a12cf5c3SThierry Reding }; 669a12cf5c3SThierry Reding 670a12cf5c3SThierry Reding core3 { 671a12cf5c3SThierry Reding cpu = <&cpu1_3>; 672a12cf5c3SThierry Reding }; 673a12cf5c3SThierry Reding }; 674a12cf5c3SThierry Reding 675a12cf5c3SThierry Reding cluster2 { 676a12cf5c3SThierry Reding core0 { 677a12cf5c3SThierry Reding cpu = <&cpu2_0>; 678a12cf5c3SThierry Reding }; 679a12cf5c3SThierry Reding 680a12cf5c3SThierry Reding core1 { 681a12cf5c3SThierry Reding cpu = <&cpu2_1>; 682a12cf5c3SThierry Reding }; 683a12cf5c3SThierry Reding 684a12cf5c3SThierry Reding core2 { 685a12cf5c3SThierry Reding cpu = <&cpu2_2>; 686a12cf5c3SThierry Reding }; 687a12cf5c3SThierry Reding 688a12cf5c3SThierry Reding core3 { 689a12cf5c3SThierry Reding cpu = <&cpu2_3>; 690a12cf5c3SThierry Reding }; 691a12cf5c3SThierry Reding }; 692a12cf5c3SThierry Reding }; 693a12cf5c3SThierry Reding 694a12cf5c3SThierry Reding l2c0_0: l2-cache00 { 695a12cf5c3SThierry Reding cache-size = <262144>; 696a12cf5c3SThierry Reding cache-line-size = <64>; 697a12cf5c3SThierry Reding cache-sets = <512>; 698a12cf5c3SThierry Reding cache-unified; 699a12cf5c3SThierry Reding next-level-cache = <&l3c0>; 700a12cf5c3SThierry Reding }; 701a12cf5c3SThierry Reding 702a12cf5c3SThierry Reding l2c0_1: l2-cache01 { 703a12cf5c3SThierry Reding cache-size = <262144>; 704a12cf5c3SThierry Reding cache-line-size = <64>; 705a12cf5c3SThierry Reding cache-sets = <512>; 706a12cf5c3SThierry Reding cache-unified; 707a12cf5c3SThierry Reding next-level-cache = <&l3c0>; 708a12cf5c3SThierry Reding }; 709a12cf5c3SThierry Reding 710a12cf5c3SThierry Reding l2c0_2: l2-cache02 { 711a12cf5c3SThierry Reding cache-size = <262144>; 712a12cf5c3SThierry Reding cache-line-size = <64>; 713a12cf5c3SThierry Reding cache-sets = <512>; 714a12cf5c3SThierry Reding cache-unified; 715a12cf5c3SThierry Reding next-level-cache = <&l3c0>; 716a12cf5c3SThierry Reding }; 717a12cf5c3SThierry Reding 718a12cf5c3SThierry Reding l2c0_3: l2-cache03 { 719a12cf5c3SThierry Reding cache-size = <262144>; 720a12cf5c3SThierry Reding cache-line-size = <64>; 721a12cf5c3SThierry Reding cache-sets = <512>; 722a12cf5c3SThierry Reding cache-unified; 723a12cf5c3SThierry Reding next-level-cache = <&l3c0>; 724a12cf5c3SThierry Reding }; 725a12cf5c3SThierry Reding 726a12cf5c3SThierry Reding l2c1_0: l2-cache10 { 727a12cf5c3SThierry Reding cache-size = <262144>; 728a12cf5c3SThierry Reding cache-line-size = <64>; 729a12cf5c3SThierry Reding cache-sets = <512>; 730a12cf5c3SThierry Reding cache-unified; 731a12cf5c3SThierry Reding next-level-cache = <&l3c1>; 732a12cf5c3SThierry Reding }; 733a12cf5c3SThierry Reding 734a12cf5c3SThierry Reding l2c1_1: l2-cache11 { 735a12cf5c3SThierry Reding cache-size = <262144>; 736a12cf5c3SThierry Reding cache-line-size = <64>; 737a12cf5c3SThierry Reding cache-sets = <512>; 738a12cf5c3SThierry Reding cache-unified; 739a12cf5c3SThierry Reding next-level-cache = <&l3c1>; 740a12cf5c3SThierry Reding }; 741a12cf5c3SThierry Reding 742a12cf5c3SThierry Reding l2c1_2: l2-cache12 { 743a12cf5c3SThierry Reding cache-size = <262144>; 744a12cf5c3SThierry Reding cache-line-size = <64>; 745a12cf5c3SThierry Reding cache-sets = <512>; 746a12cf5c3SThierry Reding cache-unified; 747a12cf5c3SThierry Reding next-level-cache = <&l3c1>; 748a12cf5c3SThierry Reding }; 749a12cf5c3SThierry Reding 750a12cf5c3SThierry Reding l2c1_3: l2-cache13 { 751a12cf5c3SThierry Reding cache-size = <262144>; 752a12cf5c3SThierry Reding cache-line-size = <64>; 753a12cf5c3SThierry Reding cache-sets = <512>; 754a12cf5c3SThierry Reding cache-unified; 755a12cf5c3SThierry Reding next-level-cache = <&l3c1>; 756a12cf5c3SThierry Reding }; 757a12cf5c3SThierry Reding 758a12cf5c3SThierry Reding l2c2_0: l2-cache20 { 759a12cf5c3SThierry Reding cache-size = <262144>; 760a12cf5c3SThierry Reding cache-line-size = <64>; 761a12cf5c3SThierry Reding cache-sets = <512>; 762a12cf5c3SThierry Reding cache-unified; 763a12cf5c3SThierry Reding next-level-cache = <&l3c2>; 764a12cf5c3SThierry Reding }; 765a12cf5c3SThierry Reding 766a12cf5c3SThierry Reding l2c2_1: l2-cache21 { 767a12cf5c3SThierry Reding cache-size = <262144>; 768a12cf5c3SThierry Reding cache-line-size = <64>; 769a12cf5c3SThierry Reding cache-sets = <512>; 770a12cf5c3SThierry Reding cache-unified; 771a12cf5c3SThierry Reding next-level-cache = <&l3c2>; 772a12cf5c3SThierry Reding }; 773a12cf5c3SThierry Reding 774a12cf5c3SThierry Reding l2c2_2: l2-cache22 { 775a12cf5c3SThierry Reding cache-size = <262144>; 776a12cf5c3SThierry Reding cache-line-size = <64>; 777a12cf5c3SThierry Reding cache-sets = <512>; 778a12cf5c3SThierry Reding cache-unified; 779a12cf5c3SThierry Reding next-level-cache = <&l3c2>; 780a12cf5c3SThierry Reding }; 781a12cf5c3SThierry Reding 782a12cf5c3SThierry Reding l2c2_3: l2-cache23 { 783a12cf5c3SThierry Reding cache-size = <262144>; 784a12cf5c3SThierry Reding cache-line-size = <64>; 785a12cf5c3SThierry Reding cache-sets = <512>; 786a12cf5c3SThierry Reding cache-unified; 787a12cf5c3SThierry Reding next-level-cache = <&l3c2>; 788a12cf5c3SThierry Reding }; 789a12cf5c3SThierry Reding 790a12cf5c3SThierry Reding l3c0: l3-cache0 { 791a12cf5c3SThierry Reding cache-size = <2097152>; 792a12cf5c3SThierry Reding cache-line-size = <64>; 793a12cf5c3SThierry Reding cache-sets = <2048>; 794a12cf5c3SThierry Reding }; 795a12cf5c3SThierry Reding 796a12cf5c3SThierry Reding l3c1: l3-cache1 { 797a12cf5c3SThierry Reding cache-size = <2097152>; 798a12cf5c3SThierry Reding cache-line-size = <64>; 799a12cf5c3SThierry Reding cache-sets = <2048>; 800a12cf5c3SThierry Reding }; 801a12cf5c3SThierry Reding 802a12cf5c3SThierry Reding l3c2: l3-cache2 { 803a12cf5c3SThierry Reding cache-size = <2097152>; 804a12cf5c3SThierry Reding cache-line-size = <64>; 805a12cf5c3SThierry Reding cache-sets = <2048>; 806a12cf5c3SThierry Reding }; 807a12cf5c3SThierry Reding }; 808a12cf5c3SThierry Reding 809a12cf5c3SThierry Reding pmu { 810a12cf5c3SThierry Reding compatible = "arm,cortex-a78-pmu"; 811a12cf5c3SThierry Reding interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 812a12cf5c3SThierry Reding status = "okay"; 81363944891SThierry Reding }; 81463944891SThierry Reding 81563944891SThierry Reding psci { 81663944891SThierry Reding compatible = "arm,psci-1.0"; 81763944891SThierry Reding status = "okay"; 81863944891SThierry Reding method = "smc"; 81963944891SThierry Reding }; 82063944891SThierry Reding 82106ad2ec4SMikko Perttunen tcu: serial { 82206ad2ec4SMikko Perttunen compatible = "nvidia,tegra234-tcu", "nvidia,tegra194-tcu"; 82306ad2ec4SMikko Perttunen mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 82406ad2ec4SMikko Perttunen <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 82506ad2ec4SMikko Perttunen mbox-names = "rx", "tx"; 82606ad2ec4SMikko Perttunen status = "disabled"; 82706ad2ec4SMikko Perttunen }; 82806ad2ec4SMikko Perttunen 82963944891SThierry Reding timer { 83063944891SThierry Reding compatible = "arm,armv8-timer"; 83163944891SThierry Reding interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 83263944891SThierry Reding <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 83363944891SThierry Reding <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 83463944891SThierry Reding <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 83563944891SThierry Reding interrupt-parent = <&gic>; 83663944891SThierry Reding always-on; 83763944891SThierry Reding }; 83863944891SThierry Reding}; 839