163944891SThierry Reding// SPDX-License-Identifier: GPL-2.0 263944891SThierry Reding 363944891SThierry Reding#include <dt-bindings/clock/tegra234-clock.h> 463944891SThierry Reding#include <dt-bindings/interrupt-controller/arm-gic.h> 563944891SThierry Reding#include <dt-bindings/mailbox/tegra186-hsp.h> 6eed280dfSThierry Reding#include <dt-bindings/memory/tegra234-mc.h> 763944891SThierry Reding#include <dt-bindings/reset/tegra234-reset.h> 863944891SThierry Reding 963944891SThierry Reding/ { 1063944891SThierry Reding compatible = "nvidia,tegra234"; 1163944891SThierry Reding interrupt-parent = <&gic>; 1263944891SThierry Reding #address-cells = <2>; 1363944891SThierry Reding #size-cells = <2>; 1463944891SThierry Reding 1563944891SThierry Reding bus@0 { 1663944891SThierry Reding compatible = "simple-bus"; 1763944891SThierry Reding #address-cells = <1>; 1863944891SThierry Reding #size-cells = <1>; 1963944891SThierry Reding 2063944891SThierry Reding ranges = <0x0 0x0 0x0 0x40000000>; 2163944891SThierry Reding 2263944891SThierry Reding misc@100000 { 2363944891SThierry Reding compatible = "nvidia,tegra234-misc"; 2463944891SThierry Reding reg = <0x00100000 0xf000>, 2563944891SThierry Reding <0x0010f000 0x1000>; 2663944891SThierry Reding status = "okay"; 2763944891SThierry Reding }; 2863944891SThierry Reding 29f0e12668SThierry Reding gpio: gpio@2200000 { 30f0e12668SThierry Reding compatible = "nvidia,tegra234-gpio"; 31f0e12668SThierry Reding reg-names = "security", "gpio"; 32f0e12668SThierry Reding reg = <0x02200000 0x10000>, 33f0e12668SThierry Reding <0x02210000 0x10000>; 34f0e12668SThierry Reding interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 35f0e12668SThierry Reding <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 36f0e12668SThierry Reding <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 37f0e12668SThierry Reding <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, 38f0e12668SThierry Reding <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 39f0e12668SThierry Reding <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 40f0e12668SThierry Reding <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 41f0e12668SThierry Reding <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 42f0e12668SThierry Reding <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 43f0e12668SThierry Reding <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 44f0e12668SThierry Reding <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 45f0e12668SThierry Reding <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 46f0e12668SThierry Reding <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 47f0e12668SThierry Reding <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 48f0e12668SThierry Reding <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 49f0e12668SThierry Reding <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 50f0e12668SThierry Reding <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 51f0e12668SThierry Reding <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 52f0e12668SThierry Reding <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 53f0e12668SThierry Reding <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 54f0e12668SThierry Reding <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 55f0e12668SThierry Reding <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 56f0e12668SThierry Reding <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 57f0e12668SThierry Reding <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 58f0e12668SThierry Reding <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 59f0e12668SThierry Reding <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 60f0e12668SThierry Reding <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 61f0e12668SThierry Reding <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 62f0e12668SThierry Reding <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 63f0e12668SThierry Reding <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 64f0e12668SThierry Reding <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 65f0e12668SThierry Reding <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 66f0e12668SThierry Reding <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 67f0e12668SThierry Reding <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 68f0e12668SThierry Reding <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 69f0e12668SThierry Reding <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 70f0e12668SThierry Reding <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 71f0e12668SThierry Reding <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 72f0e12668SThierry Reding <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 73f0e12668SThierry Reding <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 74f0e12668SThierry Reding <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 75f0e12668SThierry Reding <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 76f0e12668SThierry Reding <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 77f0e12668SThierry Reding <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 78f0e12668SThierry Reding <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 79f0e12668SThierry Reding <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 80f0e12668SThierry Reding <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 81f0e12668SThierry Reding <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 82f0e12668SThierry Reding #interrupt-cells = <2>; 83f0e12668SThierry Reding interrupt-controller; 84f0e12668SThierry Reding #gpio-cells = <2>; 85f0e12668SThierry Reding gpio-controller; 86f0e12668SThierry Reding }; 87f0e12668SThierry Reding 88eed280dfSThierry Reding mc: memory-controller@2c00000 { 89eed280dfSThierry Reding compatible = "nvidia,tegra234-mc"; 90eed280dfSThierry Reding reg = <0x02c00000 0x100000>, 91eed280dfSThierry Reding <0x02b80000 0x040000>, 92eed280dfSThierry Reding <0x01700000 0x100000>; 93eed280dfSThierry Reding interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 94eed280dfSThierry Reding #interconnect-cells = <1>; 95eed280dfSThierry Reding status = "okay"; 96eed280dfSThierry Reding 97eed280dfSThierry Reding #address-cells = <2>; 98eed280dfSThierry Reding #size-cells = <2>; 99eed280dfSThierry Reding 100eed280dfSThierry Reding ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>, 101eed280dfSThierry Reding <0x02b80000 0x0 0x02b80000 0x0 0x040000>, 102eed280dfSThierry Reding <0x02c00000 0x0 0x02c00000 0x0 0x100000>; 103eed280dfSThierry Reding 104eed280dfSThierry Reding /* 105eed280dfSThierry Reding * Bit 39 of addresses passing through the memory 106eed280dfSThierry Reding * controller selects the XBAR format used when memory 107eed280dfSThierry Reding * is accessed. This is used to transparently access 108eed280dfSThierry Reding * memory in the XBAR format used by the discrete GPU 109eed280dfSThierry Reding * (bit 39 set) or Tegra (bit 39 clear). 110eed280dfSThierry Reding * 111eed280dfSThierry Reding * As a consequence, the operating system must ensure 112eed280dfSThierry Reding * that bit 39 is never used implicitly, for example 113eed280dfSThierry Reding * via an I/O virtual address mapping of an IOMMU. If 114eed280dfSThierry Reding * devices require access to the XBAR switch, their 115eed280dfSThierry Reding * drivers must set this bit explicitly. 116eed280dfSThierry Reding * 117eed280dfSThierry Reding * Limit the DMA range for memory clients to [38:0]. 118eed280dfSThierry Reding */ 119eed280dfSThierry Reding dma-ranges = <0x0 0x0 0x0 0x80 0x0>; 120eed280dfSThierry Reding 121eed280dfSThierry Reding emc: external-memory-controller@2c60000 { 122eed280dfSThierry Reding compatible = "nvidia,tegra234-emc"; 123eed280dfSThierry Reding reg = <0x0 0x02c60000 0x0 0x90000>, 124eed280dfSThierry Reding <0x0 0x01780000 0x0 0x80000>; 125eed280dfSThierry Reding interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 126eed280dfSThierry Reding clocks = <&bpmp TEGRA234_CLK_EMC>; 127eed280dfSThierry Reding clock-names = "emc"; 128eed280dfSThierry Reding status = "okay"; 129eed280dfSThierry Reding 130eed280dfSThierry Reding #interconnect-cells = <0>; 131eed280dfSThierry Reding 132eed280dfSThierry Reding nvidia,bpmp = <&bpmp>; 133eed280dfSThierry Reding }; 134eed280dfSThierry Reding }; 135eed280dfSThierry Reding 13663944891SThierry Reding uarta: serial@3100000 { 13763944891SThierry Reding compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart"; 13863944891SThierry Reding reg = <0x03100000 0x10000>; 13963944891SThierry Reding interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 14063944891SThierry Reding clocks = <&bpmp TEGRA234_CLK_UARTA>; 14163944891SThierry Reding clock-names = "serial"; 14263944891SThierry Reding resets = <&bpmp TEGRA234_RESET_UARTA>; 14363944891SThierry Reding reset-names = "serial"; 14463944891SThierry Reding status = "disabled"; 14563944891SThierry Reding }; 14663944891SThierry Reding 147156af9deSAkhil R gen1_i2c: i2c@3160000 { 148156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 149156af9deSAkhil R reg = <0x3160000 0x100>; 150156af9deSAkhil R status = "disabled"; 151156af9deSAkhil R interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 152156af9deSAkhil R clock-frequency = <400000>; 153156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C1 154156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 155156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C1>; 156156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 157156af9deSAkhil R clock-names = "div-clk", "parent"; 158156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C1>; 159156af9deSAkhil R reset-names = "i2c"; 160156af9deSAkhil R }; 161156af9deSAkhil R 162156af9deSAkhil R cam_i2c: i2c@3180000 { 163156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 164156af9deSAkhil R reg = <0x3180000 0x100>; 165156af9deSAkhil R interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 166156af9deSAkhil R status = "disabled"; 167156af9deSAkhil R clock-frequency = <400000>; 168156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C3 169156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 170156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C3>; 171156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 172156af9deSAkhil R clock-names = "div-clk", "parent"; 173156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C3>; 174156af9deSAkhil R reset-names = "i2c"; 175156af9deSAkhil R }; 176156af9deSAkhil R 177156af9deSAkhil R dp_aux_ch1_i2c: i2c@3190000 { 178156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 179156af9deSAkhil R reg = <0x3190000 0x100>; 180156af9deSAkhil R interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 181156af9deSAkhil R status = "disabled"; 182156af9deSAkhil R clock-frequency = <100000>; 183156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C4 184156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 185156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C4>; 186156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 187156af9deSAkhil R clock-names = "div-clk", "parent"; 188156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C4>; 189156af9deSAkhil R reset-names = "i2c"; 190156af9deSAkhil R }; 191156af9deSAkhil R 192156af9deSAkhil R dp_aux_ch0_i2c: i2c@31b0000 { 193156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 194156af9deSAkhil R reg = <0x31b0000 0x100>; 195156af9deSAkhil R interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 196156af9deSAkhil R status = "disabled"; 197156af9deSAkhil R clock-frequency = <100000>; 198156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C6 199156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 200156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C6>; 201156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 202156af9deSAkhil R clock-names = "div-clk", "parent"; 203156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C6>; 204156af9deSAkhil R reset-names = "i2c"; 205156af9deSAkhil R }; 206156af9deSAkhil R 207156af9deSAkhil R dp_aux_ch2_i2c: i2c@31c0000 { 208156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 209156af9deSAkhil R reg = <0x31c0000 0x100>; 210156af9deSAkhil R interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 211156af9deSAkhil R status = "disabled"; 212156af9deSAkhil R clock-frequency = <100000>; 213156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C7 214156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 215156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C7>; 216156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 217156af9deSAkhil R clock-names = "div-clk", "parent"; 218156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C7>; 219156af9deSAkhil R reset-names = "i2c"; 220156af9deSAkhil R }; 221156af9deSAkhil R 222156af9deSAkhil R dp_aux_ch3_i2c: i2c@31e0000 { 223156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 224156af9deSAkhil R reg = <0x31e0000 0x100>; 225156af9deSAkhil R interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 226156af9deSAkhil R status = "disabled"; 227156af9deSAkhil R clock-frequency = <100000>; 228156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C9 229156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 230156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C9>; 231156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 232156af9deSAkhil R clock-names = "div-clk", "parent"; 233156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C9>; 234156af9deSAkhil R reset-names = "i2c"; 235156af9deSAkhil R }; 236156af9deSAkhil R 237*5e69088dSAkhil R pwm1: pwm@3280000 { 238*5e69088dSAkhil R compatible = "nvidia,tegra194-pwm", 239*5e69088dSAkhil R "nvidia,tegra186-pwm"; 240*5e69088dSAkhil R reg = <0x3280000 0x10000>; 241*5e69088dSAkhil R clocks = <&bpmp TEGRA234_CLK_PWM1>; 242*5e69088dSAkhil R clock-names = "pwm"; 243*5e69088dSAkhil R resets = <&bpmp TEGRA234_RESET_PWM1>; 244*5e69088dSAkhil R reset-names = "pwm"; 245*5e69088dSAkhil R status = "disabled"; 246*5e69088dSAkhil R #pwm-cells = <2>; 247*5e69088dSAkhil R }; 248*5e69088dSAkhil R 24963944891SThierry Reding mmc@3460000 { 25063944891SThierry Reding compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci"; 25163944891SThierry Reding reg = <0x03460000 0x20000>; 25263944891SThierry Reding interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 253e086d82dSMikko Perttunen clocks = <&bpmp TEGRA234_CLK_SDMMC4>, 254e086d82dSMikko Perttunen <&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>; 255e086d82dSMikko Perttunen clock-names = "sdhci", "tmclk"; 256e086d82dSMikko Perttunen assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC4>, 257e086d82dSMikko Perttunen <&bpmp TEGRA234_CLK_PLLC4>; 258e086d82dSMikko Perttunen assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4>; 25963944891SThierry Reding resets = <&bpmp TEGRA234_RESET_SDMMC4>; 26063944891SThierry Reding reset-names = "sdhci"; 2616de481e5SThierry Reding interconnects = <&mc TEGRA234_MEMORY_CLIENT_SDMMCRAB &emc>, 2626de481e5SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_SDMMCWAB &emc>; 2636de481e5SThierry Reding interconnect-names = "dma-mem", "write"; 264e086d82dSMikko Perttunen nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 265e086d82dSMikko Perttunen nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 266e086d82dSMikko Perttunen nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 267e086d82dSMikko Perttunen nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; 268e086d82dSMikko Perttunen nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 269e086d82dSMikko Perttunen nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>; 270e086d82dSMikko Perttunen nvidia,default-tap = <0x8>; 271e086d82dSMikko Perttunen nvidia,default-trim = <0x14>; 272e086d82dSMikko Perttunen nvidia,dqs-trim = <40>; 273e086d82dSMikko Perttunen supports-cqe; 27463944891SThierry Reding status = "disabled"; 27563944891SThierry Reding }; 27663944891SThierry Reding 27763944891SThierry Reding fuse@3810000 { 27863944891SThierry Reding compatible = "nvidia,tegra234-efuse"; 27963944891SThierry Reding reg = <0x03810000 0x10000>; 28063944891SThierry Reding clocks = <&bpmp TEGRA234_CLK_FUSE>; 28163944891SThierry Reding clock-names = "fuse"; 28263944891SThierry Reding }; 28363944891SThierry Reding 28463944891SThierry Reding hsp_top0: hsp@3c00000 { 28563944891SThierry Reding compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; 28663944891SThierry Reding reg = <0x03c00000 0xa0000>; 28763944891SThierry Reding interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 28863944891SThierry Reding <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 28963944891SThierry Reding <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 29063944891SThierry Reding <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 29163944891SThierry Reding <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 29263944891SThierry Reding <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 29363944891SThierry Reding <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 29463944891SThierry Reding <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 29563944891SThierry Reding <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 29663944891SThierry Reding interrupt-names = "doorbell", "shared0", "shared1", "shared2", 29763944891SThierry Reding "shared3", "shared4", "shared5", "shared6", 29863944891SThierry Reding "shared7"; 29963944891SThierry Reding #mbox-cells = <2>; 30063944891SThierry Reding }; 30163944891SThierry Reding 30263944891SThierry Reding hsp_aon: hsp@c150000 { 30363944891SThierry Reding compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; 30463944891SThierry Reding reg = <0x0c150000 0x90000>; 30563944891SThierry Reding interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 30663944891SThierry Reding <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 30763944891SThierry Reding <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 30863944891SThierry Reding <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 30963944891SThierry Reding /* 31063944891SThierry Reding * Shared interrupt 0 is routed only to AON/SPE, so 31163944891SThierry Reding * we only have 4 shared interrupts for the CCPLEX. 31263944891SThierry Reding */ 31363944891SThierry Reding interrupt-names = "shared1", "shared2", "shared3", "shared4"; 31463944891SThierry Reding #mbox-cells = <2>; 31563944891SThierry Reding }; 31663944891SThierry Reding 317156af9deSAkhil R gen2_i2c: i2c@c240000 { 318156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 319156af9deSAkhil R reg = <0xc240000 0x100>; 320156af9deSAkhil R interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 321156af9deSAkhil R status = "disabled"; 322156af9deSAkhil R clock-frequency = <100000>; 323156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C2 324156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 325156af9deSAkhil R clock-names = "div-clk", "parent"; 326156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C2>; 327156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 328156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C2>; 329156af9deSAkhil R reset-names = "i2c"; 330156af9deSAkhil R }; 331156af9deSAkhil R 332156af9deSAkhil R gen8_i2c: i2c@c250000 { 333156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 334156af9deSAkhil R reg = <0xc250000 0x100>; 335156af9deSAkhil R nvidia,hw-instance-id = <0x7>; 336156af9deSAkhil R interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 337156af9deSAkhil R status = "disabled"; 338156af9deSAkhil R clock-frequency = <400000>; 339156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C8 340156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 341156af9deSAkhil R clock-names = "div-clk", "parent"; 342156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C8>; 343156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 344156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C8>; 345156af9deSAkhil R reset-names = "i2c"; 346156af9deSAkhil R }; 347156af9deSAkhil R 34863944891SThierry Reding rtc@c2a0000 { 34963944891SThierry Reding compatible = "nvidia,tegra234-rtc", "nvidia,tegra20-rtc"; 35063944891SThierry Reding reg = <0x0c2a0000 0x10000>; 35163944891SThierry Reding interrupt-parent = <&pmc>; 35263944891SThierry Reding interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 353e537addeSMikko Perttunen clocks = <&bpmp TEGRA234_CLK_CLK_32K>; 354e537addeSMikko Perttunen clock-names = "rtc"; 35563944891SThierry Reding status = "disabled"; 35663944891SThierry Reding }; 35763944891SThierry Reding 358f0e12668SThierry Reding gpio_aon: gpio@c2f0000 { 359f0e12668SThierry Reding compatible = "nvidia,tegra234-gpio-aon"; 360f0e12668SThierry Reding reg-names = "security", "gpio"; 361f0e12668SThierry Reding reg = <0x0c2f0000 0x1000>, 362f0e12668SThierry Reding <0x0c2f1000 0x1000>; 363f0e12668SThierry Reding interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 364f0e12668SThierry Reding <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 365f0e12668SThierry Reding <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 366f0e12668SThierry Reding <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 367f0e12668SThierry Reding #interrupt-cells = <2>; 368f0e12668SThierry Reding interrupt-controller; 369f0e12668SThierry Reding #gpio-cells = <2>; 370f0e12668SThierry Reding gpio-controller; 371f0e12668SThierry Reding }; 372f0e12668SThierry Reding 37363944891SThierry Reding pmc: pmc@c360000 { 37463944891SThierry Reding compatible = "nvidia,tegra234-pmc"; 37563944891SThierry Reding reg = <0x0c360000 0x10000>, 37663944891SThierry Reding <0x0c370000 0x10000>, 37763944891SThierry Reding <0x0c380000 0x10000>, 37863944891SThierry Reding <0x0c390000 0x10000>, 37963944891SThierry Reding <0x0c3a0000 0x10000>; 38063944891SThierry Reding reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 38163944891SThierry Reding 38263944891SThierry Reding #interrupt-cells = <2>; 38363944891SThierry Reding interrupt-controller; 38463944891SThierry Reding }; 38563944891SThierry Reding 38663944891SThierry Reding gic: interrupt-controller@f400000 { 38763944891SThierry Reding compatible = "arm,gic-v3"; 38863944891SThierry Reding reg = <0x0f400000 0x010000>, /* GICD */ 38963944891SThierry Reding <0x0f440000 0x200000>; /* GICR */ 39063944891SThierry Reding interrupt-parent = <&gic>; 39163944891SThierry Reding interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 39263944891SThierry Reding 39363944891SThierry Reding #redistributor-regions = <1>; 39463944891SThierry Reding #interrupt-cells = <3>; 39563944891SThierry Reding interrupt-controller; 39663944891SThierry Reding }; 39763944891SThierry Reding }; 39863944891SThierry Reding 3997fa30752SThierry Reding sram@40000000 { 40063944891SThierry Reding compatible = "nvidia,tegra234-sysram", "mmio-sram"; 40198094be1SMikko Perttunen reg = <0x0 0x40000000 0x0 0x80000>; 40263944891SThierry Reding #address-cells = <1>; 40363944891SThierry Reding #size-cells = <1>; 40498094be1SMikko Perttunen ranges = <0x0 0x0 0x40000000 0x80000>; 40563944891SThierry Reding 40698094be1SMikko Perttunen cpu_bpmp_tx: sram@70000 { 40798094be1SMikko Perttunen reg = <0x70000 0x1000>; 40863944891SThierry Reding label = "cpu-bpmp-tx"; 40963944891SThierry Reding pool; 41063944891SThierry Reding }; 41163944891SThierry Reding 41298094be1SMikko Perttunen cpu_bpmp_rx: sram@71000 { 41398094be1SMikko Perttunen reg = <0x71000 0x1000>; 41463944891SThierry Reding label = "cpu-bpmp-rx"; 41563944891SThierry Reding pool; 41663944891SThierry Reding }; 41763944891SThierry Reding }; 41863944891SThierry Reding 41963944891SThierry Reding bpmp: bpmp { 42063944891SThierry Reding compatible = "nvidia,tegra234-bpmp", "nvidia,tegra186-bpmp"; 42163944891SThierry Reding mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 42263944891SThierry Reding TEGRA_HSP_DB_MASTER_BPMP>; 4237fa30752SThierry Reding shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; 42463944891SThierry Reding #clock-cells = <1>; 42563944891SThierry Reding #reset-cells = <1>; 42663944891SThierry Reding #power-domain-cells = <1>; 4276de481e5SThierry Reding interconnects = <&mc TEGRA234_MEMORY_CLIENT_BPMPR &emc>, 4286de481e5SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_BPMPW &emc>, 4296de481e5SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAR &emc>, 4306de481e5SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAW &emc>; 4316de481e5SThierry Reding interconnect-names = "read", "write", "dma-mem", "dma-write"; 43263944891SThierry Reding 43363944891SThierry Reding bpmp_i2c: i2c { 43463944891SThierry Reding compatible = "nvidia,tegra186-bpmp-i2c"; 43563944891SThierry Reding nvidia,bpmp-bus-id = <5>; 43663944891SThierry Reding #address-cells = <1>; 43763944891SThierry Reding #size-cells = <0>; 43863944891SThierry Reding }; 43963944891SThierry Reding }; 44063944891SThierry Reding 44163944891SThierry Reding cpus { 44263944891SThierry Reding #address-cells = <1>; 44363944891SThierry Reding #size-cells = <0>; 44463944891SThierry Reding 445a12cf5c3SThierry Reding cpu0_0: cpu@0 { 446a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 44763944891SThierry Reding device_type = "cpu"; 448a12cf5c3SThierry Reding reg = <0x00000>; 44963944891SThierry Reding 45063944891SThierry Reding enable-method = "psci"; 451a12cf5c3SThierry Reding 452a12cf5c3SThierry Reding i-cache-size = <65536>; 453a12cf5c3SThierry Reding i-cache-line-size = <64>; 454a12cf5c3SThierry Reding i-cache-sets = <256>; 455a12cf5c3SThierry Reding d-cache-size = <65536>; 456a12cf5c3SThierry Reding d-cache-line-size = <64>; 457a12cf5c3SThierry Reding d-cache-sets = <256>; 458a12cf5c3SThierry Reding next-level-cache = <&l2c0_0>; 45963944891SThierry Reding }; 460a12cf5c3SThierry Reding 461a12cf5c3SThierry Reding cpu0_1: cpu@100 { 462a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 463a12cf5c3SThierry Reding device_type = "cpu"; 464a12cf5c3SThierry Reding reg = <0x00100>; 465a12cf5c3SThierry Reding 466a12cf5c3SThierry Reding enable-method = "psci"; 467a12cf5c3SThierry Reding 468a12cf5c3SThierry Reding i-cache-size = <65536>; 469a12cf5c3SThierry Reding i-cache-line-size = <64>; 470a12cf5c3SThierry Reding i-cache-sets = <256>; 471a12cf5c3SThierry Reding d-cache-size = <65536>; 472a12cf5c3SThierry Reding d-cache-line-size = <64>; 473a12cf5c3SThierry Reding d-cache-sets = <256>; 474a12cf5c3SThierry Reding next-level-cache = <&l2c0_1>; 475a12cf5c3SThierry Reding }; 476a12cf5c3SThierry Reding 477a12cf5c3SThierry Reding cpu0_2: cpu@200 { 478a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 479a12cf5c3SThierry Reding device_type = "cpu"; 480a12cf5c3SThierry Reding reg = <0x00200>; 481a12cf5c3SThierry Reding 482a12cf5c3SThierry Reding enable-method = "psci"; 483a12cf5c3SThierry Reding 484a12cf5c3SThierry Reding i-cache-size = <65536>; 485a12cf5c3SThierry Reding i-cache-line-size = <64>; 486a12cf5c3SThierry Reding i-cache-sets = <256>; 487a12cf5c3SThierry Reding d-cache-size = <65536>; 488a12cf5c3SThierry Reding d-cache-line-size = <64>; 489a12cf5c3SThierry Reding d-cache-sets = <256>; 490a12cf5c3SThierry Reding next-level-cache = <&l2c0_2>; 491a12cf5c3SThierry Reding }; 492a12cf5c3SThierry Reding 493a12cf5c3SThierry Reding cpu0_3: cpu@300 { 494a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 495a12cf5c3SThierry Reding device_type = "cpu"; 496a12cf5c3SThierry Reding reg = <0x00300>; 497a12cf5c3SThierry Reding 498a12cf5c3SThierry Reding enable-method = "psci"; 499a12cf5c3SThierry Reding 500a12cf5c3SThierry Reding i-cache-size = <65536>; 501a12cf5c3SThierry Reding i-cache-line-size = <64>; 502a12cf5c3SThierry Reding i-cache-sets = <256>; 503a12cf5c3SThierry Reding d-cache-size = <65536>; 504a12cf5c3SThierry Reding d-cache-line-size = <64>; 505a12cf5c3SThierry Reding d-cache-sets = <256>; 506a12cf5c3SThierry Reding next-level-cache = <&l2c0_3>; 507a12cf5c3SThierry Reding }; 508a12cf5c3SThierry Reding 509a12cf5c3SThierry Reding cpu1_0: cpu@10000 { 510a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 511a12cf5c3SThierry Reding device_type = "cpu"; 512a12cf5c3SThierry Reding reg = <0x10000>; 513a12cf5c3SThierry Reding 514a12cf5c3SThierry Reding enable-method = "psci"; 515a12cf5c3SThierry Reding 516a12cf5c3SThierry Reding i-cache-size = <65536>; 517a12cf5c3SThierry Reding i-cache-line-size = <64>; 518a12cf5c3SThierry Reding i-cache-sets = <256>; 519a12cf5c3SThierry Reding d-cache-size = <65536>; 520a12cf5c3SThierry Reding d-cache-line-size = <64>; 521a12cf5c3SThierry Reding d-cache-sets = <256>; 522a12cf5c3SThierry Reding next-level-cache = <&l2c1_0>; 523a12cf5c3SThierry Reding }; 524a12cf5c3SThierry Reding 525a12cf5c3SThierry Reding cpu1_1: cpu@10100 { 526a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 527a12cf5c3SThierry Reding device_type = "cpu"; 528a12cf5c3SThierry Reding reg = <0x10100>; 529a12cf5c3SThierry Reding 530a12cf5c3SThierry Reding enable-method = "psci"; 531a12cf5c3SThierry Reding 532a12cf5c3SThierry Reding i-cache-size = <65536>; 533a12cf5c3SThierry Reding i-cache-line-size = <64>; 534a12cf5c3SThierry Reding i-cache-sets = <256>; 535a12cf5c3SThierry Reding d-cache-size = <65536>; 536a12cf5c3SThierry Reding d-cache-line-size = <64>; 537a12cf5c3SThierry Reding d-cache-sets = <256>; 538a12cf5c3SThierry Reding next-level-cache = <&l2c1_1>; 539a12cf5c3SThierry Reding }; 540a12cf5c3SThierry Reding 541a12cf5c3SThierry Reding cpu1_2: cpu@10200 { 542a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 543a12cf5c3SThierry Reding device_type = "cpu"; 544a12cf5c3SThierry Reding reg = <0x10200>; 545a12cf5c3SThierry Reding 546a12cf5c3SThierry Reding enable-method = "psci"; 547a12cf5c3SThierry Reding 548a12cf5c3SThierry Reding i-cache-size = <65536>; 549a12cf5c3SThierry Reding i-cache-line-size = <64>; 550a12cf5c3SThierry Reding i-cache-sets = <256>; 551a12cf5c3SThierry Reding d-cache-size = <65536>; 552a12cf5c3SThierry Reding d-cache-line-size = <64>; 553a12cf5c3SThierry Reding d-cache-sets = <256>; 554a12cf5c3SThierry Reding next-level-cache = <&l2c1_2>; 555a12cf5c3SThierry Reding }; 556a12cf5c3SThierry Reding 557a12cf5c3SThierry Reding cpu1_3: cpu@10300 { 558a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 559a12cf5c3SThierry Reding device_type = "cpu"; 560a12cf5c3SThierry Reding reg = <0x10300>; 561a12cf5c3SThierry Reding 562a12cf5c3SThierry Reding enable-method = "psci"; 563a12cf5c3SThierry Reding 564a12cf5c3SThierry Reding i-cache-size = <65536>; 565a12cf5c3SThierry Reding i-cache-line-size = <64>; 566a12cf5c3SThierry Reding i-cache-sets = <256>; 567a12cf5c3SThierry Reding d-cache-size = <65536>; 568a12cf5c3SThierry Reding d-cache-line-size = <64>; 569a12cf5c3SThierry Reding d-cache-sets = <256>; 570a12cf5c3SThierry Reding next-level-cache = <&l2c1_3>; 571a12cf5c3SThierry Reding }; 572a12cf5c3SThierry Reding 573a12cf5c3SThierry Reding cpu2_0: cpu@20000 { 574a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 575a12cf5c3SThierry Reding device_type = "cpu"; 576a12cf5c3SThierry Reding reg = <0x20000>; 577a12cf5c3SThierry Reding 578a12cf5c3SThierry Reding enable-method = "psci"; 579a12cf5c3SThierry Reding 580a12cf5c3SThierry Reding i-cache-size = <65536>; 581a12cf5c3SThierry Reding i-cache-line-size = <64>; 582a12cf5c3SThierry Reding i-cache-sets = <256>; 583a12cf5c3SThierry Reding d-cache-size = <65536>; 584a12cf5c3SThierry Reding d-cache-line-size = <64>; 585a12cf5c3SThierry Reding d-cache-sets = <256>; 586a12cf5c3SThierry Reding next-level-cache = <&l2c2_0>; 587a12cf5c3SThierry Reding }; 588a12cf5c3SThierry Reding 589a12cf5c3SThierry Reding cpu2_1: cpu@20100 { 590a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 591a12cf5c3SThierry Reding device_type = "cpu"; 592a12cf5c3SThierry Reding reg = <0x20100>; 593a12cf5c3SThierry Reding 594a12cf5c3SThierry Reding enable-method = "psci"; 595a12cf5c3SThierry Reding 596a12cf5c3SThierry Reding i-cache-size = <65536>; 597a12cf5c3SThierry Reding i-cache-line-size = <64>; 598a12cf5c3SThierry Reding i-cache-sets = <256>; 599a12cf5c3SThierry Reding d-cache-size = <65536>; 600a12cf5c3SThierry Reding d-cache-line-size = <64>; 601a12cf5c3SThierry Reding d-cache-sets = <256>; 602a12cf5c3SThierry Reding next-level-cache = <&l2c2_1>; 603a12cf5c3SThierry Reding }; 604a12cf5c3SThierry Reding 605a12cf5c3SThierry Reding cpu2_2: cpu@20200 { 606a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 607a12cf5c3SThierry Reding device_type = "cpu"; 608a12cf5c3SThierry Reding reg = <0x20200>; 609a12cf5c3SThierry Reding 610a12cf5c3SThierry Reding enable-method = "psci"; 611a12cf5c3SThierry Reding 612a12cf5c3SThierry Reding i-cache-size = <65536>; 613a12cf5c3SThierry Reding i-cache-line-size = <64>; 614a12cf5c3SThierry Reding i-cache-sets = <256>; 615a12cf5c3SThierry Reding d-cache-size = <65536>; 616a12cf5c3SThierry Reding d-cache-line-size = <64>; 617a12cf5c3SThierry Reding d-cache-sets = <256>; 618a12cf5c3SThierry Reding next-level-cache = <&l2c2_2>; 619a12cf5c3SThierry Reding }; 620a12cf5c3SThierry Reding 621a12cf5c3SThierry Reding cpu2_3: cpu@20300 { 622a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 623a12cf5c3SThierry Reding device_type = "cpu"; 624a12cf5c3SThierry Reding reg = <0x20300>; 625a12cf5c3SThierry Reding 626a12cf5c3SThierry Reding enable-method = "psci"; 627a12cf5c3SThierry Reding 628a12cf5c3SThierry Reding i-cache-size = <65536>; 629a12cf5c3SThierry Reding i-cache-line-size = <64>; 630a12cf5c3SThierry Reding i-cache-sets = <256>; 631a12cf5c3SThierry Reding d-cache-size = <65536>; 632a12cf5c3SThierry Reding d-cache-line-size = <64>; 633a12cf5c3SThierry Reding d-cache-sets = <256>; 634a12cf5c3SThierry Reding next-level-cache = <&l2c2_3>; 635a12cf5c3SThierry Reding }; 636a12cf5c3SThierry Reding 637a12cf5c3SThierry Reding cpu-map { 638a12cf5c3SThierry Reding cluster0 { 639a12cf5c3SThierry Reding core0 { 640a12cf5c3SThierry Reding cpu = <&cpu0_0>; 641a12cf5c3SThierry Reding }; 642a12cf5c3SThierry Reding 643a12cf5c3SThierry Reding core1 { 644a12cf5c3SThierry Reding cpu = <&cpu0_1>; 645a12cf5c3SThierry Reding }; 646a12cf5c3SThierry Reding 647a12cf5c3SThierry Reding core2 { 648a12cf5c3SThierry Reding cpu = <&cpu0_2>; 649a12cf5c3SThierry Reding }; 650a12cf5c3SThierry Reding 651a12cf5c3SThierry Reding core3 { 652a12cf5c3SThierry Reding cpu = <&cpu0_3>; 653a12cf5c3SThierry Reding }; 654a12cf5c3SThierry Reding }; 655a12cf5c3SThierry Reding 656a12cf5c3SThierry Reding cluster1 { 657a12cf5c3SThierry Reding core0 { 658a12cf5c3SThierry Reding cpu = <&cpu1_0>; 659a12cf5c3SThierry Reding }; 660a12cf5c3SThierry Reding 661a12cf5c3SThierry Reding core1 { 662a12cf5c3SThierry Reding cpu = <&cpu1_1>; 663a12cf5c3SThierry Reding }; 664a12cf5c3SThierry Reding 665a12cf5c3SThierry Reding core2 { 666a12cf5c3SThierry Reding cpu = <&cpu1_2>; 667a12cf5c3SThierry Reding }; 668a12cf5c3SThierry Reding 669a12cf5c3SThierry Reding core3 { 670a12cf5c3SThierry Reding cpu = <&cpu1_3>; 671a12cf5c3SThierry Reding }; 672a12cf5c3SThierry Reding }; 673a12cf5c3SThierry Reding 674a12cf5c3SThierry Reding cluster2 { 675a12cf5c3SThierry Reding core0 { 676a12cf5c3SThierry Reding cpu = <&cpu2_0>; 677a12cf5c3SThierry Reding }; 678a12cf5c3SThierry Reding 679a12cf5c3SThierry Reding core1 { 680a12cf5c3SThierry Reding cpu = <&cpu2_1>; 681a12cf5c3SThierry Reding }; 682a12cf5c3SThierry Reding 683a12cf5c3SThierry Reding core2 { 684a12cf5c3SThierry Reding cpu = <&cpu2_2>; 685a12cf5c3SThierry Reding }; 686a12cf5c3SThierry Reding 687a12cf5c3SThierry Reding core3 { 688a12cf5c3SThierry Reding cpu = <&cpu2_3>; 689a12cf5c3SThierry Reding }; 690a12cf5c3SThierry Reding }; 691a12cf5c3SThierry Reding }; 692a12cf5c3SThierry Reding 693a12cf5c3SThierry Reding l2c0_0: l2-cache00 { 694a12cf5c3SThierry Reding cache-size = <262144>; 695a12cf5c3SThierry Reding cache-line-size = <64>; 696a12cf5c3SThierry Reding cache-sets = <512>; 697a12cf5c3SThierry Reding cache-unified; 698a12cf5c3SThierry Reding next-level-cache = <&l3c0>; 699a12cf5c3SThierry Reding }; 700a12cf5c3SThierry Reding 701a12cf5c3SThierry Reding l2c0_1: l2-cache01 { 702a12cf5c3SThierry Reding cache-size = <262144>; 703a12cf5c3SThierry Reding cache-line-size = <64>; 704a12cf5c3SThierry Reding cache-sets = <512>; 705a12cf5c3SThierry Reding cache-unified; 706a12cf5c3SThierry Reding next-level-cache = <&l3c0>; 707a12cf5c3SThierry Reding }; 708a12cf5c3SThierry Reding 709a12cf5c3SThierry Reding l2c0_2: l2-cache02 { 710a12cf5c3SThierry Reding cache-size = <262144>; 711a12cf5c3SThierry Reding cache-line-size = <64>; 712a12cf5c3SThierry Reding cache-sets = <512>; 713a12cf5c3SThierry Reding cache-unified; 714a12cf5c3SThierry Reding next-level-cache = <&l3c0>; 715a12cf5c3SThierry Reding }; 716a12cf5c3SThierry Reding 717a12cf5c3SThierry Reding l2c0_3: l2-cache03 { 718a12cf5c3SThierry Reding cache-size = <262144>; 719a12cf5c3SThierry Reding cache-line-size = <64>; 720a12cf5c3SThierry Reding cache-sets = <512>; 721a12cf5c3SThierry Reding cache-unified; 722a12cf5c3SThierry Reding next-level-cache = <&l3c0>; 723a12cf5c3SThierry Reding }; 724a12cf5c3SThierry Reding 725a12cf5c3SThierry Reding l2c1_0: l2-cache10 { 726a12cf5c3SThierry Reding cache-size = <262144>; 727a12cf5c3SThierry Reding cache-line-size = <64>; 728a12cf5c3SThierry Reding cache-sets = <512>; 729a12cf5c3SThierry Reding cache-unified; 730a12cf5c3SThierry Reding next-level-cache = <&l3c1>; 731a12cf5c3SThierry Reding }; 732a12cf5c3SThierry Reding 733a12cf5c3SThierry Reding l2c1_1: l2-cache11 { 734a12cf5c3SThierry Reding cache-size = <262144>; 735a12cf5c3SThierry Reding cache-line-size = <64>; 736a12cf5c3SThierry Reding cache-sets = <512>; 737a12cf5c3SThierry Reding cache-unified; 738a12cf5c3SThierry Reding next-level-cache = <&l3c1>; 739a12cf5c3SThierry Reding }; 740a12cf5c3SThierry Reding 741a12cf5c3SThierry Reding l2c1_2: l2-cache12 { 742a12cf5c3SThierry Reding cache-size = <262144>; 743a12cf5c3SThierry Reding cache-line-size = <64>; 744a12cf5c3SThierry Reding cache-sets = <512>; 745a12cf5c3SThierry Reding cache-unified; 746a12cf5c3SThierry Reding next-level-cache = <&l3c1>; 747a12cf5c3SThierry Reding }; 748a12cf5c3SThierry Reding 749a12cf5c3SThierry Reding l2c1_3: l2-cache13 { 750a12cf5c3SThierry Reding cache-size = <262144>; 751a12cf5c3SThierry Reding cache-line-size = <64>; 752a12cf5c3SThierry Reding cache-sets = <512>; 753a12cf5c3SThierry Reding cache-unified; 754a12cf5c3SThierry Reding next-level-cache = <&l3c1>; 755a12cf5c3SThierry Reding }; 756a12cf5c3SThierry Reding 757a12cf5c3SThierry Reding l2c2_0: l2-cache20 { 758a12cf5c3SThierry Reding cache-size = <262144>; 759a12cf5c3SThierry Reding cache-line-size = <64>; 760a12cf5c3SThierry Reding cache-sets = <512>; 761a12cf5c3SThierry Reding cache-unified; 762a12cf5c3SThierry Reding next-level-cache = <&l3c2>; 763a12cf5c3SThierry Reding }; 764a12cf5c3SThierry Reding 765a12cf5c3SThierry Reding l2c2_1: l2-cache21 { 766a12cf5c3SThierry Reding cache-size = <262144>; 767a12cf5c3SThierry Reding cache-line-size = <64>; 768a12cf5c3SThierry Reding cache-sets = <512>; 769a12cf5c3SThierry Reding cache-unified; 770a12cf5c3SThierry Reding next-level-cache = <&l3c2>; 771a12cf5c3SThierry Reding }; 772a12cf5c3SThierry Reding 773a12cf5c3SThierry Reding l2c2_2: l2-cache22 { 774a12cf5c3SThierry Reding cache-size = <262144>; 775a12cf5c3SThierry Reding cache-line-size = <64>; 776a12cf5c3SThierry Reding cache-sets = <512>; 777a12cf5c3SThierry Reding cache-unified; 778a12cf5c3SThierry Reding next-level-cache = <&l3c2>; 779a12cf5c3SThierry Reding }; 780a12cf5c3SThierry Reding 781a12cf5c3SThierry Reding l2c2_3: l2-cache23 { 782a12cf5c3SThierry Reding cache-size = <262144>; 783a12cf5c3SThierry Reding cache-line-size = <64>; 784a12cf5c3SThierry Reding cache-sets = <512>; 785a12cf5c3SThierry Reding cache-unified; 786a12cf5c3SThierry Reding next-level-cache = <&l3c2>; 787a12cf5c3SThierry Reding }; 788a12cf5c3SThierry Reding 789a12cf5c3SThierry Reding l3c0: l3-cache0 { 790a12cf5c3SThierry Reding cache-size = <2097152>; 791a12cf5c3SThierry Reding cache-line-size = <64>; 792a12cf5c3SThierry Reding cache-sets = <2048>; 793a12cf5c3SThierry Reding }; 794a12cf5c3SThierry Reding 795a12cf5c3SThierry Reding l3c1: l3-cache1 { 796a12cf5c3SThierry Reding cache-size = <2097152>; 797a12cf5c3SThierry Reding cache-line-size = <64>; 798a12cf5c3SThierry Reding cache-sets = <2048>; 799a12cf5c3SThierry Reding }; 800a12cf5c3SThierry Reding 801a12cf5c3SThierry Reding l3c2: l3-cache2 { 802a12cf5c3SThierry Reding cache-size = <2097152>; 803a12cf5c3SThierry Reding cache-line-size = <64>; 804a12cf5c3SThierry Reding cache-sets = <2048>; 805a12cf5c3SThierry Reding }; 806a12cf5c3SThierry Reding }; 807a12cf5c3SThierry Reding 808a12cf5c3SThierry Reding pmu { 809a12cf5c3SThierry Reding compatible = "arm,cortex-a78-pmu"; 810a12cf5c3SThierry Reding interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 811a12cf5c3SThierry Reding status = "okay"; 81263944891SThierry Reding }; 81363944891SThierry Reding 81463944891SThierry Reding psci { 81563944891SThierry Reding compatible = "arm,psci-1.0"; 81663944891SThierry Reding status = "okay"; 81763944891SThierry Reding method = "smc"; 81863944891SThierry Reding }; 81963944891SThierry Reding 82006ad2ec4SMikko Perttunen tcu: serial { 82106ad2ec4SMikko Perttunen compatible = "nvidia,tegra234-tcu", "nvidia,tegra194-tcu"; 82206ad2ec4SMikko Perttunen mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 82306ad2ec4SMikko Perttunen <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 82406ad2ec4SMikko Perttunen mbox-names = "rx", "tx"; 82506ad2ec4SMikko Perttunen status = "disabled"; 82606ad2ec4SMikko Perttunen }; 82706ad2ec4SMikko Perttunen 82863944891SThierry Reding timer { 82963944891SThierry Reding compatible = "arm,armv8-timer"; 83063944891SThierry Reding interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 83163944891SThierry Reding <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 83263944891SThierry Reding <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 83363944891SThierry Reding <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 83463944891SThierry Reding interrupt-parent = <&gic>; 83563944891SThierry Reding always-on; 83663944891SThierry Reding }; 83763944891SThierry Reding}; 838