163944891SThierry Reding// SPDX-License-Identifier: GPL-2.0 263944891SThierry Reding 363944891SThierry Reding#include <dt-bindings/clock/tegra234-clock.h> 4699349e0SThierry Reding#include <dt-bindings/gpio/tegra234-gpio.h> 563944891SThierry Reding#include <dt-bindings/interrupt-controller/arm-gic.h> 663944891SThierry Reding#include <dt-bindings/mailbox/tegra186-hsp.h> 7eed280dfSThierry Reding#include <dt-bindings/memory/tegra234-mc.h> 863944891SThierry Reding#include <dt-bindings/reset/tegra234-reset.h> 963944891SThierry Reding 1063944891SThierry Reding/ { 1163944891SThierry Reding compatible = "nvidia,tegra234"; 1263944891SThierry Reding interrupt-parent = <&gic>; 1363944891SThierry Reding #address-cells = <2>; 1463944891SThierry Reding #size-cells = <2>; 1563944891SThierry Reding 1663944891SThierry Reding bus@0 { 1763944891SThierry Reding compatible = "simple-bus"; 1863944891SThierry Reding #address-cells = <1>; 1963944891SThierry Reding #size-cells = <1>; 2063944891SThierry Reding 2163944891SThierry Reding ranges = <0x0 0x0 0x0 0x40000000>; 2263944891SThierry Reding 2363944891SThierry Reding misc@100000 { 2463944891SThierry Reding compatible = "nvidia,tegra234-misc"; 2563944891SThierry Reding reg = <0x00100000 0xf000>, 2663944891SThierry Reding <0x0010f000 0x1000>; 2763944891SThierry Reding status = "okay"; 2863944891SThierry Reding }; 2963944891SThierry Reding 30f0e12668SThierry Reding gpio: gpio@2200000 { 31f0e12668SThierry Reding compatible = "nvidia,tegra234-gpio"; 32f0e12668SThierry Reding reg-names = "security", "gpio"; 33f0e12668SThierry Reding reg = <0x02200000 0x10000>, 34f0e12668SThierry Reding <0x02210000 0x10000>; 35f0e12668SThierry Reding interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 36f0e12668SThierry Reding <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 37f0e12668SThierry Reding <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 38f0e12668SThierry Reding <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, 39f0e12668SThierry Reding <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 40f0e12668SThierry Reding <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 41f0e12668SThierry Reding <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 42f0e12668SThierry Reding <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 43f0e12668SThierry Reding <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 44f0e12668SThierry Reding <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 45f0e12668SThierry Reding <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 46f0e12668SThierry Reding <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 47f0e12668SThierry Reding <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 48f0e12668SThierry Reding <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 49f0e12668SThierry Reding <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 50f0e12668SThierry Reding <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 51f0e12668SThierry Reding <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 52f0e12668SThierry Reding <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 53f0e12668SThierry Reding <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 54f0e12668SThierry Reding <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 55f0e12668SThierry Reding <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 56f0e12668SThierry Reding <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 57f0e12668SThierry Reding <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 58f0e12668SThierry Reding <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 59f0e12668SThierry Reding <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 60f0e12668SThierry Reding <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 61f0e12668SThierry Reding <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 62f0e12668SThierry Reding <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 63f0e12668SThierry Reding <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 64f0e12668SThierry Reding <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 65f0e12668SThierry Reding <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 66f0e12668SThierry Reding <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 67f0e12668SThierry Reding <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 68f0e12668SThierry Reding <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 69f0e12668SThierry Reding <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 70f0e12668SThierry Reding <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 71f0e12668SThierry Reding <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 72f0e12668SThierry Reding <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 73f0e12668SThierry Reding <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 74f0e12668SThierry Reding <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 75f0e12668SThierry Reding <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 76f0e12668SThierry Reding <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 77f0e12668SThierry Reding <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 78f0e12668SThierry Reding <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 79f0e12668SThierry Reding <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 80f0e12668SThierry Reding <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 81f0e12668SThierry Reding <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 82f0e12668SThierry Reding <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 83f0e12668SThierry Reding #interrupt-cells = <2>; 84f0e12668SThierry Reding interrupt-controller; 85f0e12668SThierry Reding #gpio-cells = <2>; 86f0e12668SThierry Reding gpio-controller; 87f0e12668SThierry Reding }; 88f0e12668SThierry Reding 89eed280dfSThierry Reding mc: memory-controller@2c00000 { 90eed280dfSThierry Reding compatible = "nvidia,tegra234-mc"; 91eed280dfSThierry Reding reg = <0x02c00000 0x100000>, 92eed280dfSThierry Reding <0x02b80000 0x040000>, 93eed280dfSThierry Reding <0x01700000 0x100000>; 94eed280dfSThierry Reding interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 95eed280dfSThierry Reding #interconnect-cells = <1>; 96eed280dfSThierry Reding status = "okay"; 97eed280dfSThierry Reding 98eed280dfSThierry Reding #address-cells = <2>; 99eed280dfSThierry Reding #size-cells = <2>; 100eed280dfSThierry Reding 101eed280dfSThierry Reding ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>, 102eed280dfSThierry Reding <0x02b80000 0x0 0x02b80000 0x0 0x040000>, 103eed280dfSThierry Reding <0x02c00000 0x0 0x02c00000 0x0 0x100000>; 104eed280dfSThierry Reding 105eed280dfSThierry Reding /* 106eed280dfSThierry Reding * Bit 39 of addresses passing through the memory 107eed280dfSThierry Reding * controller selects the XBAR format used when memory 108eed280dfSThierry Reding * is accessed. This is used to transparently access 109eed280dfSThierry Reding * memory in the XBAR format used by the discrete GPU 110eed280dfSThierry Reding * (bit 39 set) or Tegra (bit 39 clear). 111eed280dfSThierry Reding * 112eed280dfSThierry Reding * As a consequence, the operating system must ensure 113eed280dfSThierry Reding * that bit 39 is never used implicitly, for example 114eed280dfSThierry Reding * via an I/O virtual address mapping of an IOMMU. If 115eed280dfSThierry Reding * devices require access to the XBAR switch, their 116eed280dfSThierry Reding * drivers must set this bit explicitly. 117eed280dfSThierry Reding * 118eed280dfSThierry Reding * Limit the DMA range for memory clients to [38:0]. 119eed280dfSThierry Reding */ 120eed280dfSThierry Reding dma-ranges = <0x0 0x0 0x0 0x80 0x0>; 121eed280dfSThierry Reding 122eed280dfSThierry Reding emc: external-memory-controller@2c60000 { 123eed280dfSThierry Reding compatible = "nvidia,tegra234-emc"; 124eed280dfSThierry Reding reg = <0x0 0x02c60000 0x0 0x90000>, 125eed280dfSThierry Reding <0x0 0x01780000 0x0 0x80000>; 126eed280dfSThierry Reding interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 127eed280dfSThierry Reding clocks = <&bpmp TEGRA234_CLK_EMC>; 128eed280dfSThierry Reding clock-names = "emc"; 129eed280dfSThierry Reding status = "okay"; 130eed280dfSThierry Reding 131eed280dfSThierry Reding #interconnect-cells = <0>; 132eed280dfSThierry Reding 133eed280dfSThierry Reding nvidia,bpmp = <&bpmp>; 134eed280dfSThierry Reding }; 135eed280dfSThierry Reding }; 136eed280dfSThierry Reding 13763944891SThierry Reding uarta: serial@3100000 { 13863944891SThierry Reding compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart"; 13963944891SThierry Reding reg = <0x03100000 0x10000>; 14063944891SThierry Reding interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 14163944891SThierry Reding clocks = <&bpmp TEGRA234_CLK_UARTA>; 14263944891SThierry Reding clock-names = "serial"; 14363944891SThierry Reding resets = <&bpmp TEGRA234_RESET_UARTA>; 14463944891SThierry Reding reset-names = "serial"; 14563944891SThierry Reding status = "disabled"; 14663944891SThierry Reding }; 14763944891SThierry Reding 148156af9deSAkhil R gen1_i2c: i2c@3160000 { 149156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 150156af9deSAkhil R reg = <0x3160000 0x100>; 151156af9deSAkhil R status = "disabled"; 152156af9deSAkhil R interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 153156af9deSAkhil R clock-frequency = <400000>; 154156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C1 155156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 156156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C1>; 157156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 158156af9deSAkhil R clock-names = "div-clk", "parent"; 159156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C1>; 160156af9deSAkhil R reset-names = "i2c"; 161156af9deSAkhil R }; 162156af9deSAkhil R 163156af9deSAkhil R cam_i2c: i2c@3180000 { 164156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 165156af9deSAkhil R reg = <0x3180000 0x100>; 166156af9deSAkhil R interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 167156af9deSAkhil R status = "disabled"; 168156af9deSAkhil R clock-frequency = <400000>; 169156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C3 170156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 171156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C3>; 172156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 173156af9deSAkhil R clock-names = "div-clk", "parent"; 174156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C3>; 175156af9deSAkhil R reset-names = "i2c"; 176156af9deSAkhil R }; 177156af9deSAkhil R 178156af9deSAkhil R dp_aux_ch1_i2c: i2c@3190000 { 179156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 180156af9deSAkhil R reg = <0x3190000 0x100>; 181156af9deSAkhil R interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 182156af9deSAkhil R status = "disabled"; 183156af9deSAkhil R clock-frequency = <100000>; 184156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C4 185156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 186156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C4>; 187156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 188156af9deSAkhil R clock-names = "div-clk", "parent"; 189156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C4>; 190156af9deSAkhil R reset-names = "i2c"; 191156af9deSAkhil R }; 192156af9deSAkhil R 193156af9deSAkhil R dp_aux_ch0_i2c: i2c@31b0000 { 194156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 195156af9deSAkhil R reg = <0x31b0000 0x100>; 196156af9deSAkhil R interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 197156af9deSAkhil R status = "disabled"; 198156af9deSAkhil R clock-frequency = <100000>; 199156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C6 200156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 201156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C6>; 202156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 203156af9deSAkhil R clock-names = "div-clk", "parent"; 204156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C6>; 205156af9deSAkhil R reset-names = "i2c"; 206156af9deSAkhil R }; 207156af9deSAkhil R 208156af9deSAkhil R dp_aux_ch2_i2c: i2c@31c0000 { 209156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 210156af9deSAkhil R reg = <0x31c0000 0x100>; 211156af9deSAkhil R interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 212156af9deSAkhil R status = "disabled"; 213156af9deSAkhil R clock-frequency = <100000>; 214156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C7 215156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 216156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C7>; 217156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 218156af9deSAkhil R clock-names = "div-clk", "parent"; 219156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C7>; 220156af9deSAkhil R reset-names = "i2c"; 221156af9deSAkhil R }; 222156af9deSAkhil R 223156af9deSAkhil R dp_aux_ch3_i2c: i2c@31e0000 { 224156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 225156af9deSAkhil R reg = <0x31e0000 0x100>; 226156af9deSAkhil R interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 227156af9deSAkhil R status = "disabled"; 228156af9deSAkhil R clock-frequency = <100000>; 229156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C9 230156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 231156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C9>; 232156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 233156af9deSAkhil R clock-names = "div-clk", "parent"; 234156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C9>; 235156af9deSAkhil R reset-names = "i2c"; 236156af9deSAkhil R }; 237156af9deSAkhil R 2385e69088dSAkhil R pwm1: pwm@3280000 { 2395e69088dSAkhil R compatible = "nvidia,tegra194-pwm", 2405e69088dSAkhil R "nvidia,tegra186-pwm"; 2415e69088dSAkhil R reg = <0x3280000 0x10000>; 2425e69088dSAkhil R clocks = <&bpmp TEGRA234_CLK_PWM1>; 2435e69088dSAkhil R clock-names = "pwm"; 2445e69088dSAkhil R resets = <&bpmp TEGRA234_RESET_PWM1>; 2455e69088dSAkhil R reset-names = "pwm"; 2465e69088dSAkhil R status = "disabled"; 2475e69088dSAkhil R #pwm-cells = <2>; 2485e69088dSAkhil R }; 2495e69088dSAkhil R 25063944891SThierry Reding mmc@3460000 { 25163944891SThierry Reding compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci"; 25263944891SThierry Reding reg = <0x03460000 0x20000>; 25363944891SThierry Reding interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 254e086d82dSMikko Perttunen clocks = <&bpmp TEGRA234_CLK_SDMMC4>, 255e086d82dSMikko Perttunen <&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>; 256e086d82dSMikko Perttunen clock-names = "sdhci", "tmclk"; 257e086d82dSMikko Perttunen assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC4>, 258e086d82dSMikko Perttunen <&bpmp TEGRA234_CLK_PLLC4>; 259e086d82dSMikko Perttunen assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4>; 26063944891SThierry Reding resets = <&bpmp TEGRA234_RESET_SDMMC4>; 26163944891SThierry Reding reset-names = "sdhci"; 2626de481e5SThierry Reding interconnects = <&mc TEGRA234_MEMORY_CLIENT_SDMMCRAB &emc>, 2636de481e5SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_SDMMCWAB &emc>; 2646de481e5SThierry Reding interconnect-names = "dma-mem", "write"; 265*5710e16aSThierry Reding iommus = <&smmu_niso1 TEGRA234_SID_SDMMC4>; 266e086d82dSMikko Perttunen nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 267e086d82dSMikko Perttunen nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 268e086d82dSMikko Perttunen nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 269e086d82dSMikko Perttunen nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; 270e086d82dSMikko Perttunen nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 271e086d82dSMikko Perttunen nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>; 272e086d82dSMikko Perttunen nvidia,default-tap = <0x8>; 273e086d82dSMikko Perttunen nvidia,default-trim = <0x14>; 274e086d82dSMikko Perttunen nvidia,dqs-trim = <40>; 275e086d82dSMikko Perttunen supports-cqe; 27663944891SThierry Reding status = "disabled"; 27763944891SThierry Reding }; 27863944891SThierry Reding 27963944891SThierry Reding fuse@3810000 { 28063944891SThierry Reding compatible = "nvidia,tegra234-efuse"; 28163944891SThierry Reding reg = <0x03810000 0x10000>; 28263944891SThierry Reding clocks = <&bpmp TEGRA234_CLK_FUSE>; 28363944891SThierry Reding clock-names = "fuse"; 28463944891SThierry Reding }; 28563944891SThierry Reding 28663944891SThierry Reding hsp_top0: hsp@3c00000 { 28763944891SThierry Reding compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; 28863944891SThierry Reding reg = <0x03c00000 0xa0000>; 28963944891SThierry Reding interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 29063944891SThierry Reding <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 29163944891SThierry Reding <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 29263944891SThierry Reding <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 29363944891SThierry Reding <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 29463944891SThierry Reding <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 29563944891SThierry Reding <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 29663944891SThierry Reding <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 29763944891SThierry Reding <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 29863944891SThierry Reding interrupt-names = "doorbell", "shared0", "shared1", "shared2", 29963944891SThierry Reding "shared3", "shared4", "shared5", "shared6", 30063944891SThierry Reding "shared7"; 30163944891SThierry Reding #mbox-cells = <2>; 30263944891SThierry Reding }; 30363944891SThierry Reding 304*5710e16aSThierry Reding smmu_niso1: iommu@8000000 { 305*5710e16aSThierry Reding compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; 306*5710e16aSThierry Reding reg = <0x8000000 0x1000000>, 307*5710e16aSThierry Reding <0x7000000 0x1000000>; 308*5710e16aSThierry Reding interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 309*5710e16aSThierry Reding <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, 310*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 311*5710e16aSThierry Reding <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, 312*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 313*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 314*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 315*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 316*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 317*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 318*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 319*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 320*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 321*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 322*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 323*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 324*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 325*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 326*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 327*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 328*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 329*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 330*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 331*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 332*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 333*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 334*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 335*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 336*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 337*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 338*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 339*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 340*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 341*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 342*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 343*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 344*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 345*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 346*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 347*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 348*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 349*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 350*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 351*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 352*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 353*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 354*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 355*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 356*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 357*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 358*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 359*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 360*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 361*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 362*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 363*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 364*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 365*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 366*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 367*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 368*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 369*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 370*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 371*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 372*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 373*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 374*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 375*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 376*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 377*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 378*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 379*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 380*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 381*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 382*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 383*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 384*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 385*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 386*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 387*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 388*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 389*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 390*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 391*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 392*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 393*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 394*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 395*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 396*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 397*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 398*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 399*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 400*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 401*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 402*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 403*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 404*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 405*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 406*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 407*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 408*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 409*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 410*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 411*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 412*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 413*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 414*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 415*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 416*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 417*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 418*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 419*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 420*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 421*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 422*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 423*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 424*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 425*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 426*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 427*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 428*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 429*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 430*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 431*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 432*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 433*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 434*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 435*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 436*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 437*5710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 438*5710e16aSThierry Reding stream-match-mask = <0x7f80>; 439*5710e16aSThierry Reding #global-interrupts = <2>; 440*5710e16aSThierry Reding #iommu-cells = <1>; 441*5710e16aSThierry Reding 442*5710e16aSThierry Reding nvidia,memory-controller = <&mc>; 443*5710e16aSThierry Reding status = "okay"; 444*5710e16aSThierry Reding }; 445*5710e16aSThierry Reding 44663944891SThierry Reding hsp_aon: hsp@c150000 { 44763944891SThierry Reding compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; 44863944891SThierry Reding reg = <0x0c150000 0x90000>; 44963944891SThierry Reding interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 45063944891SThierry Reding <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 45163944891SThierry Reding <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 45263944891SThierry Reding <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 45363944891SThierry Reding /* 45463944891SThierry Reding * Shared interrupt 0 is routed only to AON/SPE, so 45563944891SThierry Reding * we only have 4 shared interrupts for the CCPLEX. 45663944891SThierry Reding */ 45763944891SThierry Reding interrupt-names = "shared1", "shared2", "shared3", "shared4"; 45863944891SThierry Reding #mbox-cells = <2>; 45963944891SThierry Reding }; 46063944891SThierry Reding 461156af9deSAkhil R gen2_i2c: i2c@c240000 { 462156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 463156af9deSAkhil R reg = <0xc240000 0x100>; 464156af9deSAkhil R interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 465156af9deSAkhil R status = "disabled"; 466156af9deSAkhil R clock-frequency = <100000>; 467156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C2 468156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 469156af9deSAkhil R clock-names = "div-clk", "parent"; 470156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C2>; 471156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 472156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C2>; 473156af9deSAkhil R reset-names = "i2c"; 474156af9deSAkhil R }; 475156af9deSAkhil R 476156af9deSAkhil R gen8_i2c: i2c@c250000 { 477156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 478156af9deSAkhil R reg = <0xc250000 0x100>; 479156af9deSAkhil R nvidia,hw-instance-id = <0x7>; 480156af9deSAkhil R interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 481156af9deSAkhil R status = "disabled"; 482156af9deSAkhil R clock-frequency = <400000>; 483156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C8 484156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 485156af9deSAkhil R clock-names = "div-clk", "parent"; 486156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C8>; 487156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 488156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C8>; 489156af9deSAkhil R reset-names = "i2c"; 490156af9deSAkhil R }; 491156af9deSAkhil R 49263944891SThierry Reding rtc@c2a0000 { 49363944891SThierry Reding compatible = "nvidia,tegra234-rtc", "nvidia,tegra20-rtc"; 49463944891SThierry Reding reg = <0x0c2a0000 0x10000>; 49563944891SThierry Reding interrupt-parent = <&pmc>; 49663944891SThierry Reding interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 497e537addeSMikko Perttunen clocks = <&bpmp TEGRA234_CLK_CLK_32K>; 498e537addeSMikko Perttunen clock-names = "rtc"; 49963944891SThierry Reding status = "disabled"; 50063944891SThierry Reding }; 50163944891SThierry Reding 502f0e12668SThierry Reding gpio_aon: gpio@c2f0000 { 503f0e12668SThierry Reding compatible = "nvidia,tegra234-gpio-aon"; 504f0e12668SThierry Reding reg-names = "security", "gpio"; 505f0e12668SThierry Reding reg = <0x0c2f0000 0x1000>, 506f0e12668SThierry Reding <0x0c2f1000 0x1000>; 507f0e12668SThierry Reding interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 508f0e12668SThierry Reding <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 509f0e12668SThierry Reding <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 510f0e12668SThierry Reding <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 511f0e12668SThierry Reding #interrupt-cells = <2>; 512f0e12668SThierry Reding interrupt-controller; 513f0e12668SThierry Reding #gpio-cells = <2>; 514f0e12668SThierry Reding gpio-controller; 515f0e12668SThierry Reding }; 516f0e12668SThierry Reding 51763944891SThierry Reding pmc: pmc@c360000 { 51863944891SThierry Reding compatible = "nvidia,tegra234-pmc"; 51963944891SThierry Reding reg = <0x0c360000 0x10000>, 52063944891SThierry Reding <0x0c370000 0x10000>, 52163944891SThierry Reding <0x0c380000 0x10000>, 52263944891SThierry Reding <0x0c390000 0x10000>, 52363944891SThierry Reding <0x0c3a0000 0x10000>; 52463944891SThierry Reding reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 52563944891SThierry Reding 52663944891SThierry Reding #interrupt-cells = <2>; 52763944891SThierry Reding interrupt-controller; 52863944891SThierry Reding }; 52963944891SThierry Reding 53063944891SThierry Reding gic: interrupt-controller@f400000 { 53163944891SThierry Reding compatible = "arm,gic-v3"; 53263944891SThierry Reding reg = <0x0f400000 0x010000>, /* GICD */ 53363944891SThierry Reding <0x0f440000 0x200000>; /* GICR */ 53463944891SThierry Reding interrupt-parent = <&gic>; 53563944891SThierry Reding interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 53663944891SThierry Reding 53763944891SThierry Reding #redistributor-regions = <1>; 53863944891SThierry Reding #interrupt-cells = <3>; 53963944891SThierry Reding interrupt-controller; 54063944891SThierry Reding }; 541*5710e16aSThierry Reding 542*5710e16aSThierry Reding smmu_iso: iommu@10000000{ 543*5710e16aSThierry Reding compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; 544*5710e16aSThierry Reding reg = <0x10000000 0x1000000>; 545*5710e16aSThierry Reding interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 546*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 547*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 548*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 549*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 550*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 551*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 552*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 553*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 554*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 555*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 556*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 557*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 558*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 559*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 560*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 561*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 562*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 563*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 564*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 565*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 566*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 567*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 568*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 569*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 570*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 571*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 572*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 573*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 574*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 575*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 576*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 577*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 578*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 579*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 580*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 581*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 582*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 583*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 584*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 585*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 586*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 587*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 588*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 589*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 590*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 591*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 592*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 593*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 594*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 595*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 596*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 597*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 598*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 599*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 600*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 601*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 602*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 603*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 604*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 605*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 606*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 607*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 608*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 609*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 610*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 611*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 612*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 613*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 614*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 615*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 616*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 617*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 618*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 619*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 620*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 621*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 622*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 623*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 624*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 625*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 626*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 627*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 628*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 629*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 630*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 631*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 632*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 633*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 634*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 635*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 636*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 637*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 638*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 639*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 640*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 641*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 642*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 643*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 644*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 645*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 646*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 647*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 648*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 649*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 650*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 651*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 652*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 653*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 654*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 655*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 656*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 657*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 658*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 659*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 660*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 661*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 662*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 663*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 664*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 665*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 666*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 667*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 668*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 669*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 670*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 671*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 672*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 673*5710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 674*5710e16aSThierry Reding stream-match-mask = <0x7f80>; 675*5710e16aSThierry Reding #global-interrupts = <1>; 676*5710e16aSThierry Reding #iommu-cells = <1>; 677*5710e16aSThierry Reding 678*5710e16aSThierry Reding nvidia,memory-controller = <&mc>; 679*5710e16aSThierry Reding status = "okay"; 680*5710e16aSThierry Reding }; 681*5710e16aSThierry Reding 682*5710e16aSThierry Reding smmu_niso0: iommu@12000000 { 683*5710e16aSThierry Reding compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; 684*5710e16aSThierry Reding reg = <0x12000000 0x1000000>, 685*5710e16aSThierry Reding <0x11000000 0x1000000>; 686*5710e16aSThierry Reding interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 687*5710e16aSThierry Reding <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 688*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 689*5710e16aSThierry Reding <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 690*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 691*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 692*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 693*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 694*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 695*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 696*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 697*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 698*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 699*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 700*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 701*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 702*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 703*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 704*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 705*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 706*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 707*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 708*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 709*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 710*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 711*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 712*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 713*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 714*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 715*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 716*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 717*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 718*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 719*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 720*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 721*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 722*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 723*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 724*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 725*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 726*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 727*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 728*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 729*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 730*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 731*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 732*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 733*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 734*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 735*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 736*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 737*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 738*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 739*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 740*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 741*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 742*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 743*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 744*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 745*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 746*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 747*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 748*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 749*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 750*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 751*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 752*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 753*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 754*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 755*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 756*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 757*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 758*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 759*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 760*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 761*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 762*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 763*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 764*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 765*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 766*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 767*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 768*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 769*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 770*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 771*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 772*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 773*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 774*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 775*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 776*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 777*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 778*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 779*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 780*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 781*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 782*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 783*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 784*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 785*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 786*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 787*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 788*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 789*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 790*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 791*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 792*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 793*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 794*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 795*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 796*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 797*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 798*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 799*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 800*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 801*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 802*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 803*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 804*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 805*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 806*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 807*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 808*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 809*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 810*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 811*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 812*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 813*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 814*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 815*5710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 816*5710e16aSThierry Reding stream-match-mask = <0x7f80>; 817*5710e16aSThierry Reding #global-interrupts = <2>; 818*5710e16aSThierry Reding #iommu-cells = <1>; 819*5710e16aSThierry Reding 820*5710e16aSThierry Reding nvidia,memory-controller = <&mc>; 821*5710e16aSThierry Reding status = "okay"; 822*5710e16aSThierry Reding }; 82363944891SThierry Reding }; 82463944891SThierry Reding 8257fa30752SThierry Reding sram@40000000 { 82663944891SThierry Reding compatible = "nvidia,tegra234-sysram", "mmio-sram"; 82798094be1SMikko Perttunen reg = <0x0 0x40000000 0x0 0x80000>; 82863944891SThierry Reding #address-cells = <1>; 82963944891SThierry Reding #size-cells = <1>; 83098094be1SMikko Perttunen ranges = <0x0 0x0 0x40000000 0x80000>; 83163944891SThierry Reding 83298094be1SMikko Perttunen cpu_bpmp_tx: sram@70000 { 83398094be1SMikko Perttunen reg = <0x70000 0x1000>; 83463944891SThierry Reding label = "cpu-bpmp-tx"; 83563944891SThierry Reding pool; 83663944891SThierry Reding }; 83763944891SThierry Reding 83898094be1SMikko Perttunen cpu_bpmp_rx: sram@71000 { 83998094be1SMikko Perttunen reg = <0x71000 0x1000>; 84063944891SThierry Reding label = "cpu-bpmp-rx"; 84163944891SThierry Reding pool; 84263944891SThierry Reding }; 84363944891SThierry Reding }; 84463944891SThierry Reding 84563944891SThierry Reding bpmp: bpmp { 84663944891SThierry Reding compatible = "nvidia,tegra234-bpmp", "nvidia,tegra186-bpmp"; 84763944891SThierry Reding mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 84863944891SThierry Reding TEGRA_HSP_DB_MASTER_BPMP>; 8497fa30752SThierry Reding shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; 85063944891SThierry Reding #clock-cells = <1>; 85163944891SThierry Reding #reset-cells = <1>; 85263944891SThierry Reding #power-domain-cells = <1>; 8536de481e5SThierry Reding interconnects = <&mc TEGRA234_MEMORY_CLIENT_BPMPR &emc>, 8546de481e5SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_BPMPW &emc>, 8556de481e5SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAR &emc>, 8566de481e5SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAW &emc>; 8576de481e5SThierry Reding interconnect-names = "read", "write", "dma-mem", "dma-write"; 858*5710e16aSThierry Reding iommus = <&smmu_niso1 TEGRA234_SID_BPMP>; 85963944891SThierry Reding 86063944891SThierry Reding bpmp_i2c: i2c { 86163944891SThierry Reding compatible = "nvidia,tegra186-bpmp-i2c"; 86263944891SThierry Reding nvidia,bpmp-bus-id = <5>; 86363944891SThierry Reding #address-cells = <1>; 86463944891SThierry Reding #size-cells = <0>; 86563944891SThierry Reding }; 86663944891SThierry Reding }; 86763944891SThierry Reding 86863944891SThierry Reding cpus { 86963944891SThierry Reding #address-cells = <1>; 87063944891SThierry Reding #size-cells = <0>; 87163944891SThierry Reding 872a12cf5c3SThierry Reding cpu0_0: cpu@0 { 873a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 87463944891SThierry Reding device_type = "cpu"; 875a12cf5c3SThierry Reding reg = <0x00000>; 87663944891SThierry Reding 87763944891SThierry Reding enable-method = "psci"; 878a12cf5c3SThierry Reding 879a12cf5c3SThierry Reding i-cache-size = <65536>; 880a12cf5c3SThierry Reding i-cache-line-size = <64>; 881a12cf5c3SThierry Reding i-cache-sets = <256>; 882a12cf5c3SThierry Reding d-cache-size = <65536>; 883a12cf5c3SThierry Reding d-cache-line-size = <64>; 884a12cf5c3SThierry Reding d-cache-sets = <256>; 885a12cf5c3SThierry Reding next-level-cache = <&l2c0_0>; 88663944891SThierry Reding }; 887a12cf5c3SThierry Reding 888a12cf5c3SThierry Reding cpu0_1: cpu@100 { 889a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 890a12cf5c3SThierry Reding device_type = "cpu"; 891a12cf5c3SThierry Reding reg = <0x00100>; 892a12cf5c3SThierry Reding 893a12cf5c3SThierry Reding enable-method = "psci"; 894a12cf5c3SThierry Reding 895a12cf5c3SThierry Reding i-cache-size = <65536>; 896a12cf5c3SThierry Reding i-cache-line-size = <64>; 897a12cf5c3SThierry Reding i-cache-sets = <256>; 898a12cf5c3SThierry Reding d-cache-size = <65536>; 899a12cf5c3SThierry Reding d-cache-line-size = <64>; 900a12cf5c3SThierry Reding d-cache-sets = <256>; 901a12cf5c3SThierry Reding next-level-cache = <&l2c0_1>; 902a12cf5c3SThierry Reding }; 903a12cf5c3SThierry Reding 904a12cf5c3SThierry Reding cpu0_2: cpu@200 { 905a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 906a12cf5c3SThierry Reding device_type = "cpu"; 907a12cf5c3SThierry Reding reg = <0x00200>; 908a12cf5c3SThierry Reding 909a12cf5c3SThierry Reding enable-method = "psci"; 910a12cf5c3SThierry Reding 911a12cf5c3SThierry Reding i-cache-size = <65536>; 912a12cf5c3SThierry Reding i-cache-line-size = <64>; 913a12cf5c3SThierry Reding i-cache-sets = <256>; 914a12cf5c3SThierry Reding d-cache-size = <65536>; 915a12cf5c3SThierry Reding d-cache-line-size = <64>; 916a12cf5c3SThierry Reding d-cache-sets = <256>; 917a12cf5c3SThierry Reding next-level-cache = <&l2c0_2>; 918a12cf5c3SThierry Reding }; 919a12cf5c3SThierry Reding 920a12cf5c3SThierry Reding cpu0_3: cpu@300 { 921a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 922a12cf5c3SThierry Reding device_type = "cpu"; 923a12cf5c3SThierry Reding reg = <0x00300>; 924a12cf5c3SThierry Reding 925a12cf5c3SThierry Reding enable-method = "psci"; 926a12cf5c3SThierry Reding 927a12cf5c3SThierry Reding i-cache-size = <65536>; 928a12cf5c3SThierry Reding i-cache-line-size = <64>; 929a12cf5c3SThierry Reding i-cache-sets = <256>; 930a12cf5c3SThierry Reding d-cache-size = <65536>; 931a12cf5c3SThierry Reding d-cache-line-size = <64>; 932a12cf5c3SThierry Reding d-cache-sets = <256>; 933a12cf5c3SThierry Reding next-level-cache = <&l2c0_3>; 934a12cf5c3SThierry Reding }; 935a12cf5c3SThierry Reding 936a12cf5c3SThierry Reding cpu1_0: cpu@10000 { 937a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 938a12cf5c3SThierry Reding device_type = "cpu"; 939a12cf5c3SThierry Reding reg = <0x10000>; 940a12cf5c3SThierry Reding 941a12cf5c3SThierry Reding enable-method = "psci"; 942a12cf5c3SThierry Reding 943a12cf5c3SThierry Reding i-cache-size = <65536>; 944a12cf5c3SThierry Reding i-cache-line-size = <64>; 945a12cf5c3SThierry Reding i-cache-sets = <256>; 946a12cf5c3SThierry Reding d-cache-size = <65536>; 947a12cf5c3SThierry Reding d-cache-line-size = <64>; 948a12cf5c3SThierry Reding d-cache-sets = <256>; 949a12cf5c3SThierry Reding next-level-cache = <&l2c1_0>; 950a12cf5c3SThierry Reding }; 951a12cf5c3SThierry Reding 952a12cf5c3SThierry Reding cpu1_1: cpu@10100 { 953a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 954a12cf5c3SThierry Reding device_type = "cpu"; 955a12cf5c3SThierry Reding reg = <0x10100>; 956a12cf5c3SThierry Reding 957a12cf5c3SThierry Reding enable-method = "psci"; 958a12cf5c3SThierry Reding 959a12cf5c3SThierry Reding i-cache-size = <65536>; 960a12cf5c3SThierry Reding i-cache-line-size = <64>; 961a12cf5c3SThierry Reding i-cache-sets = <256>; 962a12cf5c3SThierry Reding d-cache-size = <65536>; 963a12cf5c3SThierry Reding d-cache-line-size = <64>; 964a12cf5c3SThierry Reding d-cache-sets = <256>; 965a12cf5c3SThierry Reding next-level-cache = <&l2c1_1>; 966a12cf5c3SThierry Reding }; 967a12cf5c3SThierry Reding 968a12cf5c3SThierry Reding cpu1_2: cpu@10200 { 969a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 970a12cf5c3SThierry Reding device_type = "cpu"; 971a12cf5c3SThierry Reding reg = <0x10200>; 972a12cf5c3SThierry Reding 973a12cf5c3SThierry Reding enable-method = "psci"; 974a12cf5c3SThierry Reding 975a12cf5c3SThierry Reding i-cache-size = <65536>; 976a12cf5c3SThierry Reding i-cache-line-size = <64>; 977a12cf5c3SThierry Reding i-cache-sets = <256>; 978a12cf5c3SThierry Reding d-cache-size = <65536>; 979a12cf5c3SThierry Reding d-cache-line-size = <64>; 980a12cf5c3SThierry Reding d-cache-sets = <256>; 981a12cf5c3SThierry Reding next-level-cache = <&l2c1_2>; 982a12cf5c3SThierry Reding }; 983a12cf5c3SThierry Reding 984a12cf5c3SThierry Reding cpu1_3: cpu@10300 { 985a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 986a12cf5c3SThierry Reding device_type = "cpu"; 987a12cf5c3SThierry Reding reg = <0x10300>; 988a12cf5c3SThierry Reding 989a12cf5c3SThierry Reding enable-method = "psci"; 990a12cf5c3SThierry Reding 991a12cf5c3SThierry Reding i-cache-size = <65536>; 992a12cf5c3SThierry Reding i-cache-line-size = <64>; 993a12cf5c3SThierry Reding i-cache-sets = <256>; 994a12cf5c3SThierry Reding d-cache-size = <65536>; 995a12cf5c3SThierry Reding d-cache-line-size = <64>; 996a12cf5c3SThierry Reding d-cache-sets = <256>; 997a12cf5c3SThierry Reding next-level-cache = <&l2c1_3>; 998a12cf5c3SThierry Reding }; 999a12cf5c3SThierry Reding 1000a12cf5c3SThierry Reding cpu2_0: cpu@20000 { 1001a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 1002a12cf5c3SThierry Reding device_type = "cpu"; 1003a12cf5c3SThierry Reding reg = <0x20000>; 1004a12cf5c3SThierry Reding 1005a12cf5c3SThierry Reding enable-method = "psci"; 1006a12cf5c3SThierry Reding 1007a12cf5c3SThierry Reding i-cache-size = <65536>; 1008a12cf5c3SThierry Reding i-cache-line-size = <64>; 1009a12cf5c3SThierry Reding i-cache-sets = <256>; 1010a12cf5c3SThierry Reding d-cache-size = <65536>; 1011a12cf5c3SThierry Reding d-cache-line-size = <64>; 1012a12cf5c3SThierry Reding d-cache-sets = <256>; 1013a12cf5c3SThierry Reding next-level-cache = <&l2c2_0>; 1014a12cf5c3SThierry Reding }; 1015a12cf5c3SThierry Reding 1016a12cf5c3SThierry Reding cpu2_1: cpu@20100 { 1017a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 1018a12cf5c3SThierry Reding device_type = "cpu"; 1019a12cf5c3SThierry Reding reg = <0x20100>; 1020a12cf5c3SThierry Reding 1021a12cf5c3SThierry Reding enable-method = "psci"; 1022a12cf5c3SThierry Reding 1023a12cf5c3SThierry Reding i-cache-size = <65536>; 1024a12cf5c3SThierry Reding i-cache-line-size = <64>; 1025a12cf5c3SThierry Reding i-cache-sets = <256>; 1026a12cf5c3SThierry Reding d-cache-size = <65536>; 1027a12cf5c3SThierry Reding d-cache-line-size = <64>; 1028a12cf5c3SThierry Reding d-cache-sets = <256>; 1029a12cf5c3SThierry Reding next-level-cache = <&l2c2_1>; 1030a12cf5c3SThierry Reding }; 1031a12cf5c3SThierry Reding 1032a12cf5c3SThierry Reding cpu2_2: cpu@20200 { 1033a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 1034a12cf5c3SThierry Reding device_type = "cpu"; 1035a12cf5c3SThierry Reding reg = <0x20200>; 1036a12cf5c3SThierry Reding 1037a12cf5c3SThierry Reding enable-method = "psci"; 1038a12cf5c3SThierry Reding 1039a12cf5c3SThierry Reding i-cache-size = <65536>; 1040a12cf5c3SThierry Reding i-cache-line-size = <64>; 1041a12cf5c3SThierry Reding i-cache-sets = <256>; 1042a12cf5c3SThierry Reding d-cache-size = <65536>; 1043a12cf5c3SThierry Reding d-cache-line-size = <64>; 1044a12cf5c3SThierry Reding d-cache-sets = <256>; 1045a12cf5c3SThierry Reding next-level-cache = <&l2c2_2>; 1046a12cf5c3SThierry Reding }; 1047a12cf5c3SThierry Reding 1048a12cf5c3SThierry Reding cpu2_3: cpu@20300 { 1049a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 1050a12cf5c3SThierry Reding device_type = "cpu"; 1051a12cf5c3SThierry Reding reg = <0x20300>; 1052a12cf5c3SThierry Reding 1053a12cf5c3SThierry Reding enable-method = "psci"; 1054a12cf5c3SThierry Reding 1055a12cf5c3SThierry Reding i-cache-size = <65536>; 1056a12cf5c3SThierry Reding i-cache-line-size = <64>; 1057a12cf5c3SThierry Reding i-cache-sets = <256>; 1058a12cf5c3SThierry Reding d-cache-size = <65536>; 1059a12cf5c3SThierry Reding d-cache-line-size = <64>; 1060a12cf5c3SThierry Reding d-cache-sets = <256>; 1061a12cf5c3SThierry Reding next-level-cache = <&l2c2_3>; 1062a12cf5c3SThierry Reding }; 1063a12cf5c3SThierry Reding 1064a12cf5c3SThierry Reding cpu-map { 1065a12cf5c3SThierry Reding cluster0 { 1066a12cf5c3SThierry Reding core0 { 1067a12cf5c3SThierry Reding cpu = <&cpu0_0>; 1068a12cf5c3SThierry Reding }; 1069a12cf5c3SThierry Reding 1070a12cf5c3SThierry Reding core1 { 1071a12cf5c3SThierry Reding cpu = <&cpu0_1>; 1072a12cf5c3SThierry Reding }; 1073a12cf5c3SThierry Reding 1074a12cf5c3SThierry Reding core2 { 1075a12cf5c3SThierry Reding cpu = <&cpu0_2>; 1076a12cf5c3SThierry Reding }; 1077a12cf5c3SThierry Reding 1078a12cf5c3SThierry Reding core3 { 1079a12cf5c3SThierry Reding cpu = <&cpu0_3>; 1080a12cf5c3SThierry Reding }; 1081a12cf5c3SThierry Reding }; 1082a12cf5c3SThierry Reding 1083a12cf5c3SThierry Reding cluster1 { 1084a12cf5c3SThierry Reding core0 { 1085a12cf5c3SThierry Reding cpu = <&cpu1_0>; 1086a12cf5c3SThierry Reding }; 1087a12cf5c3SThierry Reding 1088a12cf5c3SThierry Reding core1 { 1089a12cf5c3SThierry Reding cpu = <&cpu1_1>; 1090a12cf5c3SThierry Reding }; 1091a12cf5c3SThierry Reding 1092a12cf5c3SThierry Reding core2 { 1093a12cf5c3SThierry Reding cpu = <&cpu1_2>; 1094a12cf5c3SThierry Reding }; 1095a12cf5c3SThierry Reding 1096a12cf5c3SThierry Reding core3 { 1097a12cf5c3SThierry Reding cpu = <&cpu1_3>; 1098a12cf5c3SThierry Reding }; 1099a12cf5c3SThierry Reding }; 1100a12cf5c3SThierry Reding 1101a12cf5c3SThierry Reding cluster2 { 1102a12cf5c3SThierry Reding core0 { 1103a12cf5c3SThierry Reding cpu = <&cpu2_0>; 1104a12cf5c3SThierry Reding }; 1105a12cf5c3SThierry Reding 1106a12cf5c3SThierry Reding core1 { 1107a12cf5c3SThierry Reding cpu = <&cpu2_1>; 1108a12cf5c3SThierry Reding }; 1109a12cf5c3SThierry Reding 1110a12cf5c3SThierry Reding core2 { 1111a12cf5c3SThierry Reding cpu = <&cpu2_2>; 1112a12cf5c3SThierry Reding }; 1113a12cf5c3SThierry Reding 1114a12cf5c3SThierry Reding core3 { 1115a12cf5c3SThierry Reding cpu = <&cpu2_3>; 1116a12cf5c3SThierry Reding }; 1117a12cf5c3SThierry Reding }; 1118a12cf5c3SThierry Reding }; 1119a12cf5c3SThierry Reding 1120a12cf5c3SThierry Reding l2c0_0: l2-cache00 { 1121a12cf5c3SThierry Reding cache-size = <262144>; 1122a12cf5c3SThierry Reding cache-line-size = <64>; 1123a12cf5c3SThierry Reding cache-sets = <512>; 1124a12cf5c3SThierry Reding cache-unified; 1125a12cf5c3SThierry Reding next-level-cache = <&l3c0>; 1126a12cf5c3SThierry Reding }; 1127a12cf5c3SThierry Reding 1128a12cf5c3SThierry Reding l2c0_1: l2-cache01 { 1129a12cf5c3SThierry Reding cache-size = <262144>; 1130a12cf5c3SThierry Reding cache-line-size = <64>; 1131a12cf5c3SThierry Reding cache-sets = <512>; 1132a12cf5c3SThierry Reding cache-unified; 1133a12cf5c3SThierry Reding next-level-cache = <&l3c0>; 1134a12cf5c3SThierry Reding }; 1135a12cf5c3SThierry Reding 1136a12cf5c3SThierry Reding l2c0_2: l2-cache02 { 1137a12cf5c3SThierry Reding cache-size = <262144>; 1138a12cf5c3SThierry Reding cache-line-size = <64>; 1139a12cf5c3SThierry Reding cache-sets = <512>; 1140a12cf5c3SThierry Reding cache-unified; 1141a12cf5c3SThierry Reding next-level-cache = <&l3c0>; 1142a12cf5c3SThierry Reding }; 1143a12cf5c3SThierry Reding 1144a12cf5c3SThierry Reding l2c0_3: l2-cache03 { 1145a12cf5c3SThierry Reding cache-size = <262144>; 1146a12cf5c3SThierry Reding cache-line-size = <64>; 1147a12cf5c3SThierry Reding cache-sets = <512>; 1148a12cf5c3SThierry Reding cache-unified; 1149a12cf5c3SThierry Reding next-level-cache = <&l3c0>; 1150a12cf5c3SThierry Reding }; 1151a12cf5c3SThierry Reding 1152a12cf5c3SThierry Reding l2c1_0: l2-cache10 { 1153a12cf5c3SThierry Reding cache-size = <262144>; 1154a12cf5c3SThierry Reding cache-line-size = <64>; 1155a12cf5c3SThierry Reding cache-sets = <512>; 1156a12cf5c3SThierry Reding cache-unified; 1157a12cf5c3SThierry Reding next-level-cache = <&l3c1>; 1158a12cf5c3SThierry Reding }; 1159a12cf5c3SThierry Reding 1160a12cf5c3SThierry Reding l2c1_1: l2-cache11 { 1161a12cf5c3SThierry Reding cache-size = <262144>; 1162a12cf5c3SThierry Reding cache-line-size = <64>; 1163a12cf5c3SThierry Reding cache-sets = <512>; 1164a12cf5c3SThierry Reding cache-unified; 1165a12cf5c3SThierry Reding next-level-cache = <&l3c1>; 1166a12cf5c3SThierry Reding }; 1167a12cf5c3SThierry Reding 1168a12cf5c3SThierry Reding l2c1_2: l2-cache12 { 1169a12cf5c3SThierry Reding cache-size = <262144>; 1170a12cf5c3SThierry Reding cache-line-size = <64>; 1171a12cf5c3SThierry Reding cache-sets = <512>; 1172a12cf5c3SThierry Reding cache-unified; 1173a12cf5c3SThierry Reding next-level-cache = <&l3c1>; 1174a12cf5c3SThierry Reding }; 1175a12cf5c3SThierry Reding 1176a12cf5c3SThierry Reding l2c1_3: l2-cache13 { 1177a12cf5c3SThierry Reding cache-size = <262144>; 1178a12cf5c3SThierry Reding cache-line-size = <64>; 1179a12cf5c3SThierry Reding cache-sets = <512>; 1180a12cf5c3SThierry Reding cache-unified; 1181a12cf5c3SThierry Reding next-level-cache = <&l3c1>; 1182a12cf5c3SThierry Reding }; 1183a12cf5c3SThierry Reding 1184a12cf5c3SThierry Reding l2c2_0: l2-cache20 { 1185a12cf5c3SThierry Reding cache-size = <262144>; 1186a12cf5c3SThierry Reding cache-line-size = <64>; 1187a12cf5c3SThierry Reding cache-sets = <512>; 1188a12cf5c3SThierry Reding cache-unified; 1189a12cf5c3SThierry Reding next-level-cache = <&l3c2>; 1190a12cf5c3SThierry Reding }; 1191a12cf5c3SThierry Reding 1192a12cf5c3SThierry Reding l2c2_1: l2-cache21 { 1193a12cf5c3SThierry Reding cache-size = <262144>; 1194a12cf5c3SThierry Reding cache-line-size = <64>; 1195a12cf5c3SThierry Reding cache-sets = <512>; 1196a12cf5c3SThierry Reding cache-unified; 1197a12cf5c3SThierry Reding next-level-cache = <&l3c2>; 1198a12cf5c3SThierry Reding }; 1199a12cf5c3SThierry Reding 1200a12cf5c3SThierry Reding l2c2_2: l2-cache22 { 1201a12cf5c3SThierry Reding cache-size = <262144>; 1202a12cf5c3SThierry Reding cache-line-size = <64>; 1203a12cf5c3SThierry Reding cache-sets = <512>; 1204a12cf5c3SThierry Reding cache-unified; 1205a12cf5c3SThierry Reding next-level-cache = <&l3c2>; 1206a12cf5c3SThierry Reding }; 1207a12cf5c3SThierry Reding 1208a12cf5c3SThierry Reding l2c2_3: l2-cache23 { 1209a12cf5c3SThierry Reding cache-size = <262144>; 1210a12cf5c3SThierry Reding cache-line-size = <64>; 1211a12cf5c3SThierry Reding cache-sets = <512>; 1212a12cf5c3SThierry Reding cache-unified; 1213a12cf5c3SThierry Reding next-level-cache = <&l3c2>; 1214a12cf5c3SThierry Reding }; 1215a12cf5c3SThierry Reding 1216a12cf5c3SThierry Reding l3c0: l3-cache0 { 1217a12cf5c3SThierry Reding cache-size = <2097152>; 1218a12cf5c3SThierry Reding cache-line-size = <64>; 1219a12cf5c3SThierry Reding cache-sets = <2048>; 1220a12cf5c3SThierry Reding }; 1221a12cf5c3SThierry Reding 1222a12cf5c3SThierry Reding l3c1: l3-cache1 { 1223a12cf5c3SThierry Reding cache-size = <2097152>; 1224a12cf5c3SThierry Reding cache-line-size = <64>; 1225a12cf5c3SThierry Reding cache-sets = <2048>; 1226a12cf5c3SThierry Reding }; 1227a12cf5c3SThierry Reding 1228a12cf5c3SThierry Reding l3c2: l3-cache2 { 1229a12cf5c3SThierry Reding cache-size = <2097152>; 1230a12cf5c3SThierry Reding cache-line-size = <64>; 1231a12cf5c3SThierry Reding cache-sets = <2048>; 1232a12cf5c3SThierry Reding }; 1233a12cf5c3SThierry Reding }; 1234a12cf5c3SThierry Reding 1235a12cf5c3SThierry Reding pmu { 1236a12cf5c3SThierry Reding compatible = "arm,cortex-a78-pmu"; 1237a12cf5c3SThierry Reding interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 1238a12cf5c3SThierry Reding status = "okay"; 123963944891SThierry Reding }; 124063944891SThierry Reding 124163944891SThierry Reding psci { 124263944891SThierry Reding compatible = "arm,psci-1.0"; 124363944891SThierry Reding status = "okay"; 124463944891SThierry Reding method = "smc"; 124563944891SThierry Reding }; 124663944891SThierry Reding 124706ad2ec4SMikko Perttunen tcu: serial { 124806ad2ec4SMikko Perttunen compatible = "nvidia,tegra234-tcu", "nvidia,tegra194-tcu"; 124906ad2ec4SMikko Perttunen mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 125006ad2ec4SMikko Perttunen <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 125106ad2ec4SMikko Perttunen mbox-names = "rx", "tx"; 125206ad2ec4SMikko Perttunen status = "disabled"; 125306ad2ec4SMikko Perttunen }; 125406ad2ec4SMikko Perttunen 125563944891SThierry Reding timer { 125663944891SThierry Reding compatible = "arm,armv8-timer"; 125763944891SThierry Reding interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 125863944891SThierry Reding <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 125963944891SThierry Reding <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 126063944891SThierry Reding <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 126163944891SThierry Reding interrupt-parent = <&gic>; 126263944891SThierry Reding always-on; 126363944891SThierry Reding }; 126463944891SThierry Reding}; 1265