163944891SThierry Reding// SPDX-License-Identifier: GPL-2.0 263944891SThierry Reding 363944891SThierry Reding#include <dt-bindings/clock/tegra234-clock.h> 4699349e0SThierry Reding#include <dt-bindings/gpio/tegra234-gpio.h> 563944891SThierry Reding#include <dt-bindings/interrupt-controller/arm-gic.h> 663944891SThierry Reding#include <dt-bindings/mailbox/tegra186-hsp.h> 7eed280dfSThierry Reding#include <dt-bindings/memory/tegra234-mc.h> 8dc94a94dSSameer Pujar#include <dt-bindings/power/tegra234-powergate.h> 963944891SThierry Reding#include <dt-bindings/reset/tegra234-reset.h> 1063944891SThierry Reding 1163944891SThierry Reding/ { 1263944891SThierry Reding compatible = "nvidia,tegra234"; 1363944891SThierry Reding interrupt-parent = <&gic>; 1463944891SThierry Reding #address-cells = <2>; 1563944891SThierry Reding #size-cells = <2>; 1663944891SThierry Reding 1763944891SThierry Reding bus@0 { 1863944891SThierry Reding compatible = "simple-bus"; 1963944891SThierry Reding #address-cells = <1>; 2063944891SThierry Reding #size-cells = <1>; 2163944891SThierry Reding 2263944891SThierry Reding ranges = <0x0 0x0 0x0 0x40000000>; 2363944891SThierry Reding 24dc94a94dSSameer Pujar aconnect@2900000 { 25dc94a94dSSameer Pujar compatible = "nvidia,tegra234-aconnect", 26dc94a94dSSameer Pujar "nvidia,tegra210-aconnect"; 27dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_APE>, 28dc94a94dSSameer Pujar <&bpmp TEGRA234_CLK_APB2APE>; 29dc94a94dSSameer Pujar clock-names = "ape", "apb2ape"; 30dc94a94dSSameer Pujar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_AUD>; 31dc94a94dSSameer Pujar #address-cells = <1>; 32dc94a94dSSameer Pujar #size-cells = <1>; 33dc94a94dSSameer Pujar ranges = <0x02900000 0x02900000 0x200000>; 34dc94a94dSSameer Pujar status = "disabled"; 35dc94a94dSSameer Pujar 36dc94a94dSSameer Pujar tegra_ahub: ahub@2900800 { 37dc94a94dSSameer Pujar compatible = "nvidia,tegra234-ahub"; 38dc94a94dSSameer Pujar reg = <0x02900800 0x800>; 39dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_AHUB>; 40dc94a94dSSameer Pujar clock-names = "ahub"; 41dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_AHUB>; 42dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 43dc94a94dSSameer Pujar #address-cells = <1>; 44dc94a94dSSameer Pujar #size-cells = <1>; 45dc94a94dSSameer Pujar ranges = <0x02900800 0x02900800 0x11800>; 46dc94a94dSSameer Pujar status = "disabled"; 47dc94a94dSSameer Pujar 48dc94a94dSSameer Pujar tegra_i2s1: i2s@2901000 { 49dc94a94dSSameer Pujar compatible = "nvidia,tegra234-i2s", 50dc94a94dSSameer Pujar "nvidia,tegra210-i2s"; 51dc94a94dSSameer Pujar reg = <0x2901000 0x100>; 52dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_I2S1>, 53dc94a94dSSameer Pujar <&bpmp TEGRA234_CLK_I2S1_SYNC_INPUT>; 54dc94a94dSSameer Pujar clock-names = "i2s", "sync_input"; 55dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_I2S1>; 56dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 57dc94a94dSSameer Pujar assigned-clock-rates = <1536000>; 58dc94a94dSSameer Pujar sound-name-prefix = "I2S1"; 59dc94a94dSSameer Pujar status = "disabled"; 60dc94a94dSSameer Pujar }; 61dc94a94dSSameer Pujar 62dc94a94dSSameer Pujar tegra_i2s2: i2s@2901100 { 63dc94a94dSSameer Pujar compatible = "nvidia,tegra234-i2s", 64dc94a94dSSameer Pujar "nvidia,tegra210-i2s"; 65dc94a94dSSameer Pujar reg = <0x2901100 0x100>; 66dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_I2S2>, 67dc94a94dSSameer Pujar <&bpmp TEGRA234_CLK_I2S2_SYNC_INPUT>; 68dc94a94dSSameer Pujar clock-names = "i2s", "sync_input"; 69dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_I2S2>; 70dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 71dc94a94dSSameer Pujar assigned-clock-rates = <1536000>; 72dc94a94dSSameer Pujar sound-name-prefix = "I2S2"; 73dc94a94dSSameer Pujar status = "disabled"; 74dc94a94dSSameer Pujar }; 75dc94a94dSSameer Pujar 76dc94a94dSSameer Pujar tegra_i2s3: i2s@2901200 { 77dc94a94dSSameer Pujar compatible = "nvidia,tegra234-i2s", 78dc94a94dSSameer Pujar "nvidia,tegra210-i2s"; 79dc94a94dSSameer Pujar reg = <0x2901200 0x100>; 80dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_I2S3>, 81dc94a94dSSameer Pujar <&bpmp TEGRA234_CLK_I2S3_SYNC_INPUT>; 82dc94a94dSSameer Pujar clock-names = "i2s", "sync_input"; 83dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_I2S3>; 84dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 85dc94a94dSSameer Pujar assigned-clock-rates = <1536000>; 86dc94a94dSSameer Pujar sound-name-prefix = "I2S3"; 87dc94a94dSSameer Pujar status = "disabled"; 88dc94a94dSSameer Pujar }; 89dc94a94dSSameer Pujar 90dc94a94dSSameer Pujar tegra_i2s4: i2s@2901300 { 91dc94a94dSSameer Pujar compatible = "nvidia,tegra234-i2s", 92dc94a94dSSameer Pujar "nvidia,tegra210-i2s"; 93dc94a94dSSameer Pujar reg = <0x2901300 0x100>; 94dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_I2S4>, 95dc94a94dSSameer Pujar <&bpmp TEGRA234_CLK_I2S4_SYNC_INPUT>; 96dc94a94dSSameer Pujar clock-names = "i2s", "sync_input"; 97dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_I2S4>; 98dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 99dc94a94dSSameer Pujar assigned-clock-rates = <1536000>; 100dc94a94dSSameer Pujar sound-name-prefix = "I2S4"; 101dc94a94dSSameer Pujar status = "disabled"; 102dc94a94dSSameer Pujar }; 103dc94a94dSSameer Pujar 104dc94a94dSSameer Pujar tegra_i2s5: i2s@2901400 { 105dc94a94dSSameer Pujar compatible = "nvidia,tegra234-i2s", 106dc94a94dSSameer Pujar "nvidia,tegra210-i2s"; 107dc94a94dSSameer Pujar reg = <0x2901400 0x100>; 108dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_I2S5>, 109dc94a94dSSameer Pujar <&bpmp TEGRA234_CLK_I2S5_SYNC_INPUT>; 110dc94a94dSSameer Pujar clock-names = "i2s", "sync_input"; 111dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_I2S5>; 112dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 113dc94a94dSSameer Pujar assigned-clock-rates = <1536000>; 114dc94a94dSSameer Pujar sound-name-prefix = "I2S5"; 115dc94a94dSSameer Pujar status = "disabled"; 116dc94a94dSSameer Pujar }; 117dc94a94dSSameer Pujar 118dc94a94dSSameer Pujar tegra_i2s6: i2s@2901500 { 119dc94a94dSSameer Pujar compatible = "nvidia,tegra234-i2s", 120dc94a94dSSameer Pujar "nvidia,tegra210-i2s"; 121dc94a94dSSameer Pujar reg = <0x2901500 0x100>; 122dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_I2S6>, 123dc94a94dSSameer Pujar <&bpmp TEGRA234_CLK_I2S6_SYNC_INPUT>; 124dc94a94dSSameer Pujar clock-names = "i2s", "sync_input"; 125dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_I2S6>; 126dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 127dc94a94dSSameer Pujar assigned-clock-rates = <1536000>; 128dc94a94dSSameer Pujar sound-name-prefix = "I2S6"; 129dc94a94dSSameer Pujar status = "disabled"; 130dc94a94dSSameer Pujar }; 131dc94a94dSSameer Pujar 132dc94a94dSSameer Pujar tegra_sfc1: sfc@2902000 { 133dc94a94dSSameer Pujar compatible = "nvidia,tegra234-sfc", 134dc94a94dSSameer Pujar "nvidia,tegra210-sfc"; 135dc94a94dSSameer Pujar reg = <0x2902000 0x200>; 136dc94a94dSSameer Pujar sound-name-prefix = "SFC1"; 137dc94a94dSSameer Pujar status = "disabled"; 138dc94a94dSSameer Pujar }; 139dc94a94dSSameer Pujar 140dc94a94dSSameer Pujar tegra_sfc2: sfc@2902200 { 141dc94a94dSSameer Pujar compatible = "nvidia,tegra234-sfc", 142dc94a94dSSameer Pujar "nvidia,tegra210-sfc"; 143dc94a94dSSameer Pujar reg = <0x2902200 0x200>; 144dc94a94dSSameer Pujar sound-name-prefix = "SFC2"; 145dc94a94dSSameer Pujar status = "disabled"; 146dc94a94dSSameer Pujar }; 147dc94a94dSSameer Pujar 148dc94a94dSSameer Pujar tegra_sfc3: sfc@2902400 { 149dc94a94dSSameer Pujar compatible = "nvidia,tegra234-sfc", 150dc94a94dSSameer Pujar "nvidia,tegra210-sfc"; 151dc94a94dSSameer Pujar reg = <0x2902400 0x200>; 152dc94a94dSSameer Pujar sound-name-prefix = "SFC3"; 153dc94a94dSSameer Pujar status = "disabled"; 154dc94a94dSSameer Pujar }; 155dc94a94dSSameer Pujar 156dc94a94dSSameer Pujar tegra_sfc4: sfc@2902600 { 157dc94a94dSSameer Pujar compatible = "nvidia,tegra234-sfc", 158dc94a94dSSameer Pujar "nvidia,tegra210-sfc"; 159dc94a94dSSameer Pujar reg = <0x2902600 0x200>; 160dc94a94dSSameer Pujar sound-name-prefix = "SFC4"; 161dc94a94dSSameer Pujar status = "disabled"; 162dc94a94dSSameer Pujar }; 163dc94a94dSSameer Pujar 164dc94a94dSSameer Pujar tegra_amx1: amx@2903000 { 165dc94a94dSSameer Pujar compatible = "nvidia,tegra234-amx", 166dc94a94dSSameer Pujar "nvidia,tegra194-amx"; 167dc94a94dSSameer Pujar reg = <0x2903000 0x100>; 168dc94a94dSSameer Pujar sound-name-prefix = "AMX1"; 169dc94a94dSSameer Pujar status = "disabled"; 170dc94a94dSSameer Pujar }; 171dc94a94dSSameer Pujar 172dc94a94dSSameer Pujar tegra_amx2: amx@2903100 { 173dc94a94dSSameer Pujar compatible = "nvidia,tegra234-amx", 174dc94a94dSSameer Pujar "nvidia,tegra194-amx"; 175dc94a94dSSameer Pujar reg = <0x2903100 0x100>; 176dc94a94dSSameer Pujar sound-name-prefix = "AMX2"; 177dc94a94dSSameer Pujar status = "disabled"; 178dc94a94dSSameer Pujar }; 179dc94a94dSSameer Pujar 180dc94a94dSSameer Pujar tegra_amx3: amx@2903200 { 181dc94a94dSSameer Pujar compatible = "nvidia,tegra234-amx", 182dc94a94dSSameer Pujar "nvidia,tegra194-amx"; 183dc94a94dSSameer Pujar reg = <0x2903200 0x100>; 184dc94a94dSSameer Pujar sound-name-prefix = "AMX3"; 185dc94a94dSSameer Pujar status = "disabled"; 186dc94a94dSSameer Pujar }; 187dc94a94dSSameer Pujar 188dc94a94dSSameer Pujar tegra_amx4: amx@2903300 { 189dc94a94dSSameer Pujar compatible = "nvidia,tegra234-amx", 190dc94a94dSSameer Pujar "nvidia,tegra194-amx"; 191dc94a94dSSameer Pujar reg = <0x2903300 0x100>; 192dc94a94dSSameer Pujar sound-name-prefix = "AMX4"; 193dc94a94dSSameer Pujar status = "disabled"; 194dc94a94dSSameer Pujar }; 195dc94a94dSSameer Pujar 196dc94a94dSSameer Pujar tegra_adx1: adx@2903800 { 197dc94a94dSSameer Pujar compatible = "nvidia,tegra234-adx", 198dc94a94dSSameer Pujar "nvidia,tegra210-adx"; 199dc94a94dSSameer Pujar reg = <0x2903800 0x100>; 200dc94a94dSSameer Pujar sound-name-prefix = "ADX1"; 201dc94a94dSSameer Pujar status = "disabled"; 202dc94a94dSSameer Pujar }; 203dc94a94dSSameer Pujar 204dc94a94dSSameer Pujar tegra_adx2: adx@2903900 { 205dc94a94dSSameer Pujar compatible = "nvidia,tegra234-adx", 206dc94a94dSSameer Pujar "nvidia,tegra210-adx"; 207dc94a94dSSameer Pujar reg = <0x2903900 0x100>; 208dc94a94dSSameer Pujar sound-name-prefix = "ADX2"; 209dc94a94dSSameer Pujar status = "disabled"; 210dc94a94dSSameer Pujar }; 211dc94a94dSSameer Pujar 212dc94a94dSSameer Pujar tegra_adx3: adx@2903a00 { 213dc94a94dSSameer Pujar compatible = "nvidia,tegra234-adx", 214dc94a94dSSameer Pujar "nvidia,tegra210-adx"; 215dc94a94dSSameer Pujar reg = <0x2903a00 0x100>; 216dc94a94dSSameer Pujar sound-name-prefix = "ADX3"; 217dc94a94dSSameer Pujar status = "disabled"; 218dc94a94dSSameer Pujar }; 219dc94a94dSSameer Pujar 220dc94a94dSSameer Pujar tegra_adx4: adx@2903b00 { 221dc94a94dSSameer Pujar compatible = "nvidia,tegra234-adx", 222dc94a94dSSameer Pujar "nvidia,tegra210-adx"; 223dc94a94dSSameer Pujar reg = <0x2903b00 0x100>; 224dc94a94dSSameer Pujar sound-name-prefix = "ADX4"; 225dc94a94dSSameer Pujar status = "disabled"; 226dc94a94dSSameer Pujar }; 227dc94a94dSSameer Pujar 228dc94a94dSSameer Pujar 229dc94a94dSSameer Pujar tegra_dmic1: dmic@2904000 { 230dc94a94dSSameer Pujar compatible = "nvidia,tegra234-dmic", 231dc94a94dSSameer Pujar "nvidia,tegra210-dmic"; 232dc94a94dSSameer Pujar reg = <0x2904000 0x100>; 233dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_DMIC1>; 234dc94a94dSSameer Pujar clock-names = "dmic"; 235dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_DMIC1>; 236dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 237dc94a94dSSameer Pujar assigned-clock-rates = <3072000>; 238dc94a94dSSameer Pujar sound-name-prefix = "DMIC1"; 239dc94a94dSSameer Pujar status = "disabled"; 240dc94a94dSSameer Pujar }; 241dc94a94dSSameer Pujar 242dc94a94dSSameer Pujar tegra_dmic2: dmic@2904100 { 243dc94a94dSSameer Pujar compatible = "nvidia,tegra234-dmic", 244dc94a94dSSameer Pujar "nvidia,tegra210-dmic"; 245dc94a94dSSameer Pujar reg = <0x2904100 0x100>; 246dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_DMIC2>; 247dc94a94dSSameer Pujar clock-names = "dmic"; 248dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_DMIC2>; 249dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 250dc94a94dSSameer Pujar assigned-clock-rates = <3072000>; 251dc94a94dSSameer Pujar sound-name-prefix = "DMIC2"; 252dc94a94dSSameer Pujar status = "disabled"; 253dc94a94dSSameer Pujar }; 254dc94a94dSSameer Pujar 255dc94a94dSSameer Pujar tegra_dmic3: dmic@2904200 { 256dc94a94dSSameer Pujar compatible = "nvidia,tegra234-dmic", 257dc94a94dSSameer Pujar "nvidia,tegra210-dmic"; 258dc94a94dSSameer Pujar reg = <0x2904200 0x100>; 259dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_DMIC3>; 260dc94a94dSSameer Pujar clock-names = "dmic"; 261dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_DMIC3>; 262dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 263dc94a94dSSameer Pujar assigned-clock-rates = <3072000>; 264dc94a94dSSameer Pujar sound-name-prefix = "DMIC3"; 265dc94a94dSSameer Pujar status = "disabled"; 266dc94a94dSSameer Pujar }; 267dc94a94dSSameer Pujar 268dc94a94dSSameer Pujar tegra_dmic4: dmic@2904300 { 269dc94a94dSSameer Pujar compatible = "nvidia,tegra234-dmic", 270dc94a94dSSameer Pujar "nvidia,tegra210-dmic"; 271dc94a94dSSameer Pujar reg = <0x2904300 0x100>; 272dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_DMIC4>; 273dc94a94dSSameer Pujar clock-names = "dmic"; 274dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_DMIC4>; 275dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 276dc94a94dSSameer Pujar assigned-clock-rates = <3072000>; 277dc94a94dSSameer Pujar sound-name-prefix = "DMIC4"; 278dc94a94dSSameer Pujar status = "disabled"; 279dc94a94dSSameer Pujar }; 280dc94a94dSSameer Pujar 281dc94a94dSSameer Pujar tegra_dspk1: dspk@2905000 { 282dc94a94dSSameer Pujar compatible = "nvidia,tegra234-dspk", 283dc94a94dSSameer Pujar "nvidia,tegra186-dspk"; 284dc94a94dSSameer Pujar reg = <0x2905000 0x100>; 285dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_DSPK1>; 286dc94a94dSSameer Pujar clock-names = "dspk"; 287dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_DSPK1>; 288dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 289dc94a94dSSameer Pujar assigned-clock-rates = <12288000>; 290dc94a94dSSameer Pujar sound-name-prefix = "DSPK1"; 291dc94a94dSSameer Pujar status = "disabled"; 292dc94a94dSSameer Pujar }; 293dc94a94dSSameer Pujar 294dc94a94dSSameer Pujar tegra_dspk2: dspk@2905100 { 295dc94a94dSSameer Pujar compatible = "nvidia,tegra234-dspk", 296dc94a94dSSameer Pujar "nvidia,tegra186-dspk"; 297dc94a94dSSameer Pujar reg = <0x2905100 0x100>; 298dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_DSPK2>; 299dc94a94dSSameer Pujar clock-names = "dspk"; 300dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_DSPK2>; 301dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 302dc94a94dSSameer Pujar assigned-clock-rates = <12288000>; 303dc94a94dSSameer Pujar sound-name-prefix = "DSPK2"; 304dc94a94dSSameer Pujar status = "disabled"; 305dc94a94dSSameer Pujar }; 306dc94a94dSSameer Pujar 307dc94a94dSSameer Pujar tegra_mvc1: mvc@290a000 { 308dc94a94dSSameer Pujar compatible = "nvidia,tegra234-mvc", 309dc94a94dSSameer Pujar "nvidia,tegra210-mvc"; 310dc94a94dSSameer Pujar reg = <0x290a000 0x200>; 311dc94a94dSSameer Pujar sound-name-prefix = "MVC1"; 312dc94a94dSSameer Pujar status = "disabled"; 313dc94a94dSSameer Pujar }; 314dc94a94dSSameer Pujar 315dc94a94dSSameer Pujar tegra_mvc2: mvc@290a200 { 316dc94a94dSSameer Pujar compatible = "nvidia,tegra234-mvc", 317dc94a94dSSameer Pujar "nvidia,tegra210-mvc"; 318dc94a94dSSameer Pujar reg = <0x290a200 0x200>; 319dc94a94dSSameer Pujar sound-name-prefix = "MVC2"; 320dc94a94dSSameer Pujar status = "disabled"; 321dc94a94dSSameer Pujar }; 322dc94a94dSSameer Pujar 323dc94a94dSSameer Pujar tegra_amixer: amixer@290bb00 { 324dc94a94dSSameer Pujar compatible = "nvidia,tegra234-amixer", 325dc94a94dSSameer Pujar "nvidia,tegra210-amixer"; 326dc94a94dSSameer Pujar reg = <0x290bb00 0x800>; 327dc94a94dSSameer Pujar sound-name-prefix = "MIXER1"; 328dc94a94dSSameer Pujar status = "disabled"; 329dc94a94dSSameer Pujar }; 330dc94a94dSSameer Pujar 331dc94a94dSSameer Pujar tegra_admaif: admaif@290f000 { 332dc94a94dSSameer Pujar compatible = "nvidia,tegra234-admaif", 333dc94a94dSSameer Pujar "nvidia,tegra186-admaif"; 334dc94a94dSSameer Pujar reg = <0x0290f000 0x1000>; 335dc94a94dSSameer Pujar dmas = <&adma 1>, <&adma 1>, 336dc94a94dSSameer Pujar <&adma 2>, <&adma 2>, 337dc94a94dSSameer Pujar <&adma 3>, <&adma 3>, 338dc94a94dSSameer Pujar <&adma 4>, <&adma 4>, 339dc94a94dSSameer Pujar <&adma 5>, <&adma 5>, 340dc94a94dSSameer Pujar <&adma 6>, <&adma 6>, 341dc94a94dSSameer Pujar <&adma 7>, <&adma 7>, 342dc94a94dSSameer Pujar <&adma 8>, <&adma 8>, 343dc94a94dSSameer Pujar <&adma 9>, <&adma 9>, 344dc94a94dSSameer Pujar <&adma 10>, <&adma 10>, 345dc94a94dSSameer Pujar <&adma 11>, <&adma 11>, 346dc94a94dSSameer Pujar <&adma 12>, <&adma 12>, 347dc94a94dSSameer Pujar <&adma 13>, <&adma 13>, 348dc94a94dSSameer Pujar <&adma 14>, <&adma 14>, 349dc94a94dSSameer Pujar <&adma 15>, <&adma 15>, 350dc94a94dSSameer Pujar <&adma 16>, <&adma 16>, 351dc94a94dSSameer Pujar <&adma 17>, <&adma 17>, 352dc94a94dSSameer Pujar <&adma 18>, <&adma 18>, 353dc94a94dSSameer Pujar <&adma 19>, <&adma 19>, 354dc94a94dSSameer Pujar <&adma 20>, <&adma 20>; 355dc94a94dSSameer Pujar dma-names = "rx1", "tx1", 356dc94a94dSSameer Pujar "rx2", "tx2", 357dc94a94dSSameer Pujar "rx3", "tx3", 358dc94a94dSSameer Pujar "rx4", "tx4", 359dc94a94dSSameer Pujar "rx5", "tx5", 360dc94a94dSSameer Pujar "rx6", "tx6", 361dc94a94dSSameer Pujar "rx7", "tx7", 362dc94a94dSSameer Pujar "rx8", "tx8", 363dc94a94dSSameer Pujar "rx9", "tx9", 364dc94a94dSSameer Pujar "rx10", "tx10", 365dc94a94dSSameer Pujar "rx11", "tx11", 366dc94a94dSSameer Pujar "rx12", "tx12", 367dc94a94dSSameer Pujar "rx13", "tx13", 368dc94a94dSSameer Pujar "rx14", "tx14", 369dc94a94dSSameer Pujar "rx15", "tx15", 370dc94a94dSSameer Pujar "rx16", "tx16", 371dc94a94dSSameer Pujar "rx17", "tx17", 372dc94a94dSSameer Pujar "rx18", "tx18", 373dc94a94dSSameer Pujar "rx19", "tx19", 374dc94a94dSSameer Pujar "rx20", "tx20"; 375dc94a94dSSameer Pujar interconnects = <&mc TEGRA234_MEMORY_CLIENT_APEDMAR &emc>, 376dc94a94dSSameer Pujar <&mc TEGRA234_MEMORY_CLIENT_APEDMAW &emc>; 377dc94a94dSSameer Pujar interconnect-names = "dma-mem", "write"; 378dc94a94dSSameer Pujar iommus = <&smmu_niso0 TEGRA234_SID_APE>; 379dc94a94dSSameer Pujar status = "disabled"; 380dc94a94dSSameer Pujar }; 381*47a08153SSameer Pujar 382*47a08153SSameer Pujar tegra_asrc: asrc@2910000 { 383*47a08153SSameer Pujar compatible = "nvidia,tegra234-asrc", 384*47a08153SSameer Pujar "nvidia,tegra186-asrc"; 385*47a08153SSameer Pujar reg = <0x2910000 0x2000>; 386*47a08153SSameer Pujar sound-name-prefix = "ASRC1"; 387*47a08153SSameer Pujar status = "disabled"; 388*47a08153SSameer Pujar }; 389dc94a94dSSameer Pujar }; 390dc94a94dSSameer Pujar 391dc94a94dSSameer Pujar adma: dma-controller@2930000 { 392dc94a94dSSameer Pujar compatible = "nvidia,tegra234-adma", 393dc94a94dSSameer Pujar "nvidia,tegra186-adma"; 394dc94a94dSSameer Pujar reg = <0x02930000 0x20000>; 395dc94a94dSSameer Pujar interrupt-parent = <&agic>; 396dc94a94dSSameer Pujar interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 397dc94a94dSSameer Pujar <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 398dc94a94dSSameer Pujar <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 399dc94a94dSSameer Pujar <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 400dc94a94dSSameer Pujar <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 401dc94a94dSSameer Pujar <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 402dc94a94dSSameer Pujar <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 403dc94a94dSSameer Pujar <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 404dc94a94dSSameer Pujar <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 405dc94a94dSSameer Pujar <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 406dc94a94dSSameer Pujar <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 407dc94a94dSSameer Pujar <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 408dc94a94dSSameer Pujar <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 409dc94a94dSSameer Pujar <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 410dc94a94dSSameer Pujar <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 411dc94a94dSSameer Pujar <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 412dc94a94dSSameer Pujar <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 413dc94a94dSSameer Pujar <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 414dc94a94dSSameer Pujar <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 415dc94a94dSSameer Pujar <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 416dc94a94dSSameer Pujar <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 417dc94a94dSSameer Pujar <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 418dc94a94dSSameer Pujar <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 419dc94a94dSSameer Pujar <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 420dc94a94dSSameer Pujar <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 421dc94a94dSSameer Pujar <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 422dc94a94dSSameer Pujar <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 423dc94a94dSSameer Pujar <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 424dc94a94dSSameer Pujar <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 425dc94a94dSSameer Pujar <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 426dc94a94dSSameer Pujar <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 427dc94a94dSSameer Pujar <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 428dc94a94dSSameer Pujar #dma-cells = <1>; 429dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_AHUB>; 430dc94a94dSSameer Pujar clock-names = "d_audio"; 431dc94a94dSSameer Pujar status = "disabled"; 432dc94a94dSSameer Pujar }; 433dc94a94dSSameer Pujar 434dc94a94dSSameer Pujar agic: interrupt-controller@2a40000 { 435dc94a94dSSameer Pujar compatible = "nvidia,tegra234-agic", 436dc94a94dSSameer Pujar "nvidia,tegra210-agic"; 437dc94a94dSSameer Pujar #interrupt-cells = <3>; 438dc94a94dSSameer Pujar interrupt-controller; 439dc94a94dSSameer Pujar reg = <0x02a41000 0x1000>, 440dc94a94dSSameer Pujar <0x02a42000 0x2000>; 441dc94a94dSSameer Pujar interrupts = <GIC_SPI 145 442dc94a94dSSameer Pujar (GIC_CPU_MASK_SIMPLE(4) | 443dc94a94dSSameer Pujar IRQ_TYPE_LEVEL_HIGH)>; 444dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_APE>; 445dc94a94dSSameer Pujar clock-names = "clk"; 446dc94a94dSSameer Pujar status = "disabled"; 447dc94a94dSSameer Pujar }; 448dc94a94dSSameer Pujar }; 449dc94a94dSSameer Pujar 45063944891SThierry Reding misc@100000 { 45163944891SThierry Reding compatible = "nvidia,tegra234-misc"; 45263944891SThierry Reding reg = <0x00100000 0xf000>, 45363944891SThierry Reding <0x0010f000 0x1000>; 45463944891SThierry Reding status = "okay"; 45563944891SThierry Reding }; 45663944891SThierry Reding 457f0e12668SThierry Reding gpio: gpio@2200000 { 458f0e12668SThierry Reding compatible = "nvidia,tegra234-gpio"; 459f0e12668SThierry Reding reg-names = "security", "gpio"; 460f0e12668SThierry Reding reg = <0x02200000 0x10000>, 461f0e12668SThierry Reding <0x02210000 0x10000>; 462f0e12668SThierry Reding interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 463f0e12668SThierry Reding <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 464f0e12668SThierry Reding <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 465f0e12668SThierry Reding <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, 466f0e12668SThierry Reding <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 467f0e12668SThierry Reding <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 468f0e12668SThierry Reding <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 469f0e12668SThierry Reding <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 470f0e12668SThierry Reding <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 471f0e12668SThierry Reding <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 472f0e12668SThierry Reding <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 473f0e12668SThierry Reding <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 474f0e12668SThierry Reding <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 475f0e12668SThierry Reding <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 476f0e12668SThierry Reding <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 477f0e12668SThierry Reding <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 478f0e12668SThierry Reding <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 479f0e12668SThierry Reding <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 480f0e12668SThierry Reding <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 481f0e12668SThierry Reding <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 482f0e12668SThierry Reding <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 483f0e12668SThierry Reding <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 484f0e12668SThierry Reding <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 485f0e12668SThierry Reding <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 486f0e12668SThierry Reding <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 487f0e12668SThierry Reding <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 488f0e12668SThierry Reding <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 489f0e12668SThierry Reding <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 490f0e12668SThierry Reding <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 491f0e12668SThierry Reding <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 492f0e12668SThierry Reding <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 493f0e12668SThierry Reding <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 494f0e12668SThierry Reding <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 495f0e12668SThierry Reding <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 496f0e12668SThierry Reding <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 497f0e12668SThierry Reding <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 498f0e12668SThierry Reding <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 499f0e12668SThierry Reding <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 500f0e12668SThierry Reding <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 501f0e12668SThierry Reding <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 502f0e12668SThierry Reding <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 503f0e12668SThierry Reding <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 504f0e12668SThierry Reding <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 505f0e12668SThierry Reding <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 506f0e12668SThierry Reding <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 507f0e12668SThierry Reding <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 508f0e12668SThierry Reding <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 509f0e12668SThierry Reding <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 510f0e12668SThierry Reding #interrupt-cells = <2>; 511f0e12668SThierry Reding interrupt-controller; 512f0e12668SThierry Reding #gpio-cells = <2>; 513f0e12668SThierry Reding gpio-controller; 514f0e12668SThierry Reding }; 515f0e12668SThierry Reding 516eed280dfSThierry Reding mc: memory-controller@2c00000 { 517eed280dfSThierry Reding compatible = "nvidia,tegra234-mc"; 518eed280dfSThierry Reding reg = <0x02c00000 0x100000>, 519eed280dfSThierry Reding <0x02b80000 0x040000>, 520eed280dfSThierry Reding <0x01700000 0x100000>; 521eed280dfSThierry Reding interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 522eed280dfSThierry Reding #interconnect-cells = <1>; 523eed280dfSThierry Reding status = "okay"; 524eed280dfSThierry Reding 525eed280dfSThierry Reding #address-cells = <2>; 526eed280dfSThierry Reding #size-cells = <2>; 527eed280dfSThierry Reding 528eed280dfSThierry Reding ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>, 529eed280dfSThierry Reding <0x02b80000 0x0 0x02b80000 0x0 0x040000>, 530eed280dfSThierry Reding <0x02c00000 0x0 0x02c00000 0x0 0x100000>; 531eed280dfSThierry Reding 532eed280dfSThierry Reding /* 533eed280dfSThierry Reding * Bit 39 of addresses passing through the memory 534eed280dfSThierry Reding * controller selects the XBAR format used when memory 535eed280dfSThierry Reding * is accessed. This is used to transparently access 536eed280dfSThierry Reding * memory in the XBAR format used by the discrete GPU 537eed280dfSThierry Reding * (bit 39 set) or Tegra (bit 39 clear). 538eed280dfSThierry Reding * 539eed280dfSThierry Reding * As a consequence, the operating system must ensure 540eed280dfSThierry Reding * that bit 39 is never used implicitly, for example 541eed280dfSThierry Reding * via an I/O virtual address mapping of an IOMMU. If 542eed280dfSThierry Reding * devices require access to the XBAR switch, their 543eed280dfSThierry Reding * drivers must set this bit explicitly. 544eed280dfSThierry Reding * 545eed280dfSThierry Reding * Limit the DMA range for memory clients to [38:0]. 546eed280dfSThierry Reding */ 547eed280dfSThierry Reding dma-ranges = <0x0 0x0 0x0 0x80 0x0>; 548eed280dfSThierry Reding 549eed280dfSThierry Reding emc: external-memory-controller@2c60000 { 550eed280dfSThierry Reding compatible = "nvidia,tegra234-emc"; 551eed280dfSThierry Reding reg = <0x0 0x02c60000 0x0 0x90000>, 552eed280dfSThierry Reding <0x0 0x01780000 0x0 0x80000>; 553eed280dfSThierry Reding interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 554eed280dfSThierry Reding clocks = <&bpmp TEGRA234_CLK_EMC>; 555eed280dfSThierry Reding clock-names = "emc"; 556eed280dfSThierry Reding status = "okay"; 557eed280dfSThierry Reding 558eed280dfSThierry Reding #interconnect-cells = <0>; 559eed280dfSThierry Reding 560eed280dfSThierry Reding nvidia,bpmp = <&bpmp>; 561eed280dfSThierry Reding }; 562eed280dfSThierry Reding }; 563eed280dfSThierry Reding 56463944891SThierry Reding uarta: serial@3100000 { 56563944891SThierry Reding compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart"; 56663944891SThierry Reding reg = <0x03100000 0x10000>; 56763944891SThierry Reding interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 56863944891SThierry Reding clocks = <&bpmp TEGRA234_CLK_UARTA>; 56963944891SThierry Reding clock-names = "serial"; 57063944891SThierry Reding resets = <&bpmp TEGRA234_RESET_UARTA>; 57163944891SThierry Reding reset-names = "serial"; 57263944891SThierry Reding status = "disabled"; 57363944891SThierry Reding }; 57463944891SThierry Reding 575156af9deSAkhil R gen1_i2c: i2c@3160000 { 576156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 577156af9deSAkhil R reg = <0x3160000 0x100>; 578156af9deSAkhil R status = "disabled"; 579156af9deSAkhil R interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 580156af9deSAkhil R clock-frequency = <400000>; 581156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C1 582156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 583156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C1>; 584156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 585156af9deSAkhil R clock-names = "div-clk", "parent"; 586156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C1>; 587156af9deSAkhil R reset-names = "i2c"; 588156af9deSAkhil R }; 589156af9deSAkhil R 590156af9deSAkhil R cam_i2c: i2c@3180000 { 591156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 592156af9deSAkhil R reg = <0x3180000 0x100>; 593156af9deSAkhil R interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 594156af9deSAkhil R status = "disabled"; 595156af9deSAkhil R clock-frequency = <400000>; 596156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C3 597156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 598156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C3>; 599156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 600156af9deSAkhil R clock-names = "div-clk", "parent"; 601156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C3>; 602156af9deSAkhil R reset-names = "i2c"; 603156af9deSAkhil R }; 604156af9deSAkhil R 605156af9deSAkhil R dp_aux_ch1_i2c: i2c@3190000 { 606156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 607156af9deSAkhil R reg = <0x3190000 0x100>; 608156af9deSAkhil R interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 609156af9deSAkhil R status = "disabled"; 610156af9deSAkhil R clock-frequency = <100000>; 611156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C4 612156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 613156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C4>; 614156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 615156af9deSAkhil R clock-names = "div-clk", "parent"; 616156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C4>; 617156af9deSAkhil R reset-names = "i2c"; 618156af9deSAkhil R }; 619156af9deSAkhil R 620156af9deSAkhil R dp_aux_ch0_i2c: i2c@31b0000 { 621156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 622156af9deSAkhil R reg = <0x31b0000 0x100>; 623156af9deSAkhil R interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 624156af9deSAkhil R status = "disabled"; 625156af9deSAkhil R clock-frequency = <100000>; 626156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C6 627156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 628156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C6>; 629156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 630156af9deSAkhil R clock-names = "div-clk", "parent"; 631156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C6>; 632156af9deSAkhil R reset-names = "i2c"; 633156af9deSAkhil R }; 634156af9deSAkhil R 635156af9deSAkhil R dp_aux_ch2_i2c: i2c@31c0000 { 636156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 637156af9deSAkhil R reg = <0x31c0000 0x100>; 638156af9deSAkhil R interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 639156af9deSAkhil R status = "disabled"; 640156af9deSAkhil R clock-frequency = <100000>; 641156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C7 642156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 643156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C7>; 644156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 645156af9deSAkhil R clock-names = "div-clk", "parent"; 646156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C7>; 647156af9deSAkhil R reset-names = "i2c"; 648156af9deSAkhil R }; 649156af9deSAkhil R 650156af9deSAkhil R dp_aux_ch3_i2c: i2c@31e0000 { 651156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 652156af9deSAkhil R reg = <0x31e0000 0x100>; 653156af9deSAkhil R interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 654156af9deSAkhil R status = "disabled"; 655156af9deSAkhil R clock-frequency = <100000>; 656156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C9 657156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 658156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C9>; 659156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 660156af9deSAkhil R clock-names = "div-clk", "parent"; 661156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C9>; 662156af9deSAkhil R reset-names = "i2c"; 663156af9deSAkhil R }; 664156af9deSAkhil R 66571f69ffaSAshish Singhal spi@3270000 { 66671f69ffaSAshish Singhal compatible = "nvidia,tegra234-qspi"; 66771f69ffaSAshish Singhal reg = <0x3270000 0x1000>; 66871f69ffaSAshish Singhal interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 66971f69ffaSAshish Singhal #address-cells = <1>; 67071f69ffaSAshish Singhal #size-cells = <0>; 67171f69ffaSAshish Singhal clocks = <&bpmp TEGRA234_CLK_QSPI0_2X_PM>, 67271f69ffaSAshish Singhal <&bpmp TEGRA234_CLK_QSPI0_PM>; 67371f69ffaSAshish Singhal clock-names = "qspi", "qspi_out"; 67471f69ffaSAshish Singhal resets = <&bpmp TEGRA234_RESET_QSPI0>; 67571f69ffaSAshish Singhal reset-names = "qspi"; 67671f69ffaSAshish Singhal status = "disabled"; 67771f69ffaSAshish Singhal }; 67871f69ffaSAshish Singhal 6795e69088dSAkhil R pwm1: pwm@3280000 { 6805e69088dSAkhil R compatible = "nvidia,tegra194-pwm", 6815e69088dSAkhil R "nvidia,tegra186-pwm"; 6825e69088dSAkhil R reg = <0x3280000 0x10000>; 6835e69088dSAkhil R clocks = <&bpmp TEGRA234_CLK_PWM1>; 6845e69088dSAkhil R clock-names = "pwm"; 6855e69088dSAkhil R resets = <&bpmp TEGRA234_RESET_PWM1>; 6865e69088dSAkhil R reset-names = "pwm"; 6875e69088dSAkhil R status = "disabled"; 6885e69088dSAkhil R #pwm-cells = <2>; 6895e69088dSAkhil R }; 6905e69088dSAkhil R 69171f69ffaSAshish Singhal spi@3300000 { 69271f69ffaSAshish Singhal compatible = "nvidia,tegra234-qspi"; 69371f69ffaSAshish Singhal reg = <0x3300000 0x1000>; 69471f69ffaSAshish Singhal interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 69571f69ffaSAshish Singhal #address-cells = <1>; 69671f69ffaSAshish Singhal #size-cells = <0>; 69771f69ffaSAshish Singhal clocks = <&bpmp TEGRA234_CLK_QSPI1_2X_PM>, 69871f69ffaSAshish Singhal <&bpmp TEGRA234_CLK_QSPI1_PM>; 69971f69ffaSAshish Singhal clock-names = "qspi", "qspi_out"; 70071f69ffaSAshish Singhal resets = <&bpmp TEGRA234_RESET_QSPI1>; 70171f69ffaSAshish Singhal reset-names = "qspi"; 70271f69ffaSAshish Singhal status = "disabled"; 70371f69ffaSAshish Singhal }; 70471f69ffaSAshish Singhal 70563944891SThierry Reding mmc@3460000 { 70663944891SThierry Reding compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci"; 70763944891SThierry Reding reg = <0x03460000 0x20000>; 70863944891SThierry Reding interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 709e086d82dSMikko Perttunen clocks = <&bpmp TEGRA234_CLK_SDMMC4>, 710e086d82dSMikko Perttunen <&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>; 711e086d82dSMikko Perttunen clock-names = "sdhci", "tmclk"; 712e086d82dSMikko Perttunen assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC4>, 713e086d82dSMikko Perttunen <&bpmp TEGRA234_CLK_PLLC4>; 714e086d82dSMikko Perttunen assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4>; 71563944891SThierry Reding resets = <&bpmp TEGRA234_RESET_SDMMC4>; 71663944891SThierry Reding reset-names = "sdhci"; 7176de481e5SThierry Reding interconnects = <&mc TEGRA234_MEMORY_CLIENT_SDMMCRAB &emc>, 7186de481e5SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_SDMMCWAB &emc>; 7196de481e5SThierry Reding interconnect-names = "dma-mem", "write"; 7205710e16aSThierry Reding iommus = <&smmu_niso1 TEGRA234_SID_SDMMC4>; 721e086d82dSMikko Perttunen nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 722e086d82dSMikko Perttunen nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 723e086d82dSMikko Perttunen nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 724e086d82dSMikko Perttunen nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; 725e086d82dSMikko Perttunen nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 726e086d82dSMikko Perttunen nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>; 727e086d82dSMikko Perttunen nvidia,default-tap = <0x8>; 728e086d82dSMikko Perttunen nvidia,default-trim = <0x14>; 729e086d82dSMikko Perttunen nvidia,dqs-trim = <40>; 730e086d82dSMikko Perttunen supports-cqe; 73163944891SThierry Reding status = "disabled"; 73263944891SThierry Reding }; 73363944891SThierry Reding 734621e12a1SMohan Kumar hda@3510000 { 735621e12a1SMohan Kumar compatible = "nvidia,tegra234-hda", "nvidia,tegra30-hda"; 736621e12a1SMohan Kumar reg = <0x3510000 0x10000>; 737621e12a1SMohan Kumar interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 738621e12a1SMohan Kumar clocks = <&bpmp TEGRA234_CLK_AZA_BIT>, 739621e12a1SMohan Kumar <&bpmp TEGRA234_CLK_AZA_2XBIT>; 740621e12a1SMohan Kumar clock-names = "hda", "hda2codec_2x"; 741621e12a1SMohan Kumar resets = <&bpmp TEGRA234_RESET_HDA>, 742621e12a1SMohan Kumar <&bpmp TEGRA234_RESET_HDACODEC>; 743621e12a1SMohan Kumar reset-names = "hda", "hda2codec_2x"; 744621e12a1SMohan Kumar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_DISP>; 745621e12a1SMohan Kumar interconnects = <&mc TEGRA234_MEMORY_CLIENT_HDAR &emc>, 746621e12a1SMohan Kumar <&mc TEGRA234_MEMORY_CLIENT_HDAW &emc>; 747621e12a1SMohan Kumar interconnect-names = "dma-mem", "write"; 748621e12a1SMohan Kumar status = "disabled"; 749621e12a1SMohan Kumar }; 750621e12a1SMohan Kumar 75163944891SThierry Reding fuse@3810000 { 75263944891SThierry Reding compatible = "nvidia,tegra234-efuse"; 75363944891SThierry Reding reg = <0x03810000 0x10000>; 75463944891SThierry Reding clocks = <&bpmp TEGRA234_CLK_FUSE>; 75563944891SThierry Reding clock-names = "fuse"; 75663944891SThierry Reding }; 75763944891SThierry Reding 75863944891SThierry Reding hsp_top0: hsp@3c00000 { 75963944891SThierry Reding compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; 76063944891SThierry Reding reg = <0x03c00000 0xa0000>; 76163944891SThierry Reding interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 76263944891SThierry Reding <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 76363944891SThierry Reding <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 76463944891SThierry Reding <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 76563944891SThierry Reding <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 76663944891SThierry Reding <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 76763944891SThierry Reding <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 76863944891SThierry Reding <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 76963944891SThierry Reding <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 77063944891SThierry Reding interrupt-names = "doorbell", "shared0", "shared1", "shared2", 77163944891SThierry Reding "shared3", "shared4", "shared5", "shared6", 77263944891SThierry Reding "shared7"; 77363944891SThierry Reding #mbox-cells = <2>; 77463944891SThierry Reding }; 77563944891SThierry Reding 7765710e16aSThierry Reding smmu_niso1: iommu@8000000 { 7775710e16aSThierry Reding compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; 7785710e16aSThierry Reding reg = <0x8000000 0x1000000>, 7795710e16aSThierry Reding <0x7000000 0x1000000>; 7805710e16aSThierry Reding interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 7815710e16aSThierry Reding <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, 7825710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 7835710e16aSThierry Reding <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, 7845710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 7855710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 7865710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 7875710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 7885710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 7895710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 7905710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 7915710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 7925710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 7935710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 7945710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 7955710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 7965710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 7975710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 7985710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 7995710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8005710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8015710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8025710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8035710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8045710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8055710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8065710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8075710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8085710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8095710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8105710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8115710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8125710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8135710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8145710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8155710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8165710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8175710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8185710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8195710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8205710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8215710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8225710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8235710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8245710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8255710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8265710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8275710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8285710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8295710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8305710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8315710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8325710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8335710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8345710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8355710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8365710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8375710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8385710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8395710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8405710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8415710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8425710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8435710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8445710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8455710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8465710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8475710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8485710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8495710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8505710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8515710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8525710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8535710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8545710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8555710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8565710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8575710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8585710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8595710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8605710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8615710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8625710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8635710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8645710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8655710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8665710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8675710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8685710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8695710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8705710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8715710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8725710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8735710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8745710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8755710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8765710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8775710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8785710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8795710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8805710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8815710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8825710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8835710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8845710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8855710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8865710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8875710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8885710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8895710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8905710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8915710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8925710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8935710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8945710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8955710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8965710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8975710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8985710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 8995710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 9005710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 9015710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 9025710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 9035710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 9045710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 9055710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 9065710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 9075710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 9085710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 9095710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 9105710e16aSThierry Reding stream-match-mask = <0x7f80>; 9115710e16aSThierry Reding #global-interrupts = <2>; 9125710e16aSThierry Reding #iommu-cells = <1>; 9135710e16aSThierry Reding 9145710e16aSThierry Reding nvidia,memory-controller = <&mc>; 9155710e16aSThierry Reding status = "okay"; 9165710e16aSThierry Reding }; 9175710e16aSThierry Reding 91863944891SThierry Reding hsp_aon: hsp@c150000 { 91963944891SThierry Reding compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; 92063944891SThierry Reding reg = <0x0c150000 0x90000>; 92163944891SThierry Reding interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 92263944891SThierry Reding <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 92363944891SThierry Reding <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 92463944891SThierry Reding <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 92563944891SThierry Reding /* 92663944891SThierry Reding * Shared interrupt 0 is routed only to AON/SPE, so 92763944891SThierry Reding * we only have 4 shared interrupts for the CCPLEX. 92863944891SThierry Reding */ 92963944891SThierry Reding interrupt-names = "shared1", "shared2", "shared3", "shared4"; 93063944891SThierry Reding #mbox-cells = <2>; 93163944891SThierry Reding }; 93263944891SThierry Reding 933156af9deSAkhil R gen2_i2c: i2c@c240000 { 934156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 935156af9deSAkhil R reg = <0xc240000 0x100>; 936156af9deSAkhil R interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 937156af9deSAkhil R status = "disabled"; 938156af9deSAkhil R clock-frequency = <100000>; 939156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C2 940156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 941156af9deSAkhil R clock-names = "div-clk", "parent"; 942156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C2>; 943156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 944156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C2>; 945156af9deSAkhil R reset-names = "i2c"; 946156af9deSAkhil R }; 947156af9deSAkhil R 948156af9deSAkhil R gen8_i2c: i2c@c250000 { 949156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 950156af9deSAkhil R reg = <0xc250000 0x100>; 951156af9deSAkhil R nvidia,hw-instance-id = <0x7>; 952156af9deSAkhil R interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 953156af9deSAkhil R status = "disabled"; 954156af9deSAkhil R clock-frequency = <400000>; 955156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C8 956156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 957156af9deSAkhil R clock-names = "div-clk", "parent"; 958156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C8>; 959156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 960156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C8>; 961156af9deSAkhil R reset-names = "i2c"; 962156af9deSAkhil R }; 963156af9deSAkhil R 96463944891SThierry Reding rtc@c2a0000 { 96563944891SThierry Reding compatible = "nvidia,tegra234-rtc", "nvidia,tegra20-rtc"; 96663944891SThierry Reding reg = <0x0c2a0000 0x10000>; 96763944891SThierry Reding interrupt-parent = <&pmc>; 96863944891SThierry Reding interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 969e537addeSMikko Perttunen clocks = <&bpmp TEGRA234_CLK_CLK_32K>; 970e537addeSMikko Perttunen clock-names = "rtc"; 97163944891SThierry Reding status = "disabled"; 97263944891SThierry Reding }; 97363944891SThierry Reding 974f0e12668SThierry Reding gpio_aon: gpio@c2f0000 { 975f0e12668SThierry Reding compatible = "nvidia,tegra234-gpio-aon"; 976f0e12668SThierry Reding reg-names = "security", "gpio"; 977f0e12668SThierry Reding reg = <0x0c2f0000 0x1000>, 978f0e12668SThierry Reding <0x0c2f1000 0x1000>; 979f0e12668SThierry Reding interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 980f0e12668SThierry Reding <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 981f0e12668SThierry Reding <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 982f0e12668SThierry Reding <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 983f0e12668SThierry Reding #interrupt-cells = <2>; 984f0e12668SThierry Reding interrupt-controller; 985f0e12668SThierry Reding #gpio-cells = <2>; 986f0e12668SThierry Reding gpio-controller; 987f0e12668SThierry Reding }; 988f0e12668SThierry Reding 98963944891SThierry Reding pmc: pmc@c360000 { 99063944891SThierry Reding compatible = "nvidia,tegra234-pmc"; 99163944891SThierry Reding reg = <0x0c360000 0x10000>, 99263944891SThierry Reding <0x0c370000 0x10000>, 99363944891SThierry Reding <0x0c380000 0x10000>, 99463944891SThierry Reding <0x0c390000 0x10000>, 99563944891SThierry Reding <0x0c3a0000 0x10000>; 99663944891SThierry Reding reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 99763944891SThierry Reding 99863944891SThierry Reding #interrupt-cells = <2>; 99963944891SThierry Reding interrupt-controller; 100063944891SThierry Reding }; 100163944891SThierry Reding 100263944891SThierry Reding gic: interrupt-controller@f400000 { 100363944891SThierry Reding compatible = "arm,gic-v3"; 100463944891SThierry Reding reg = <0x0f400000 0x010000>, /* GICD */ 100563944891SThierry Reding <0x0f440000 0x200000>; /* GICR */ 100663944891SThierry Reding interrupt-parent = <&gic>; 100763944891SThierry Reding interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 100863944891SThierry Reding 100963944891SThierry Reding #redistributor-regions = <1>; 101063944891SThierry Reding #interrupt-cells = <3>; 101163944891SThierry Reding interrupt-controller; 101263944891SThierry Reding }; 10135710e16aSThierry Reding 10145710e16aSThierry Reding smmu_iso: iommu@10000000{ 10155710e16aSThierry Reding compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; 10165710e16aSThierry Reding reg = <0x10000000 0x1000000>; 10175710e16aSThierry Reding interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10185710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10195710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10205710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10215710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10225710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10235710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10245710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10255710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10265710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10275710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10285710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10295710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10305710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10315710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10325710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10335710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10345710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10355710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10365710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10375710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10385710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10395710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10405710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10415710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10425710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10435710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10445710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10455710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10465710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10475710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10485710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10495710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10505710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10515710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10525710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10535710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10545710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10555710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10565710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10575710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10585710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10595710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10605710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10615710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10625710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10635710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10645710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10655710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10665710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10675710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10685710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10695710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10705710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10715710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10725710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10735710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10745710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10755710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10765710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10775710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10785710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10795710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10805710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10815710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10825710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10835710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10845710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10855710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10865710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10875710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10885710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10895710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10905710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10915710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10925710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10935710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10945710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10955710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10965710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10975710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10985710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 10995710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 11005710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 11015710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 11025710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 11035710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 11045710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 11055710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 11065710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 11075710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 11085710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 11095710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 11105710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 11115710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 11125710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 11135710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 11145710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 11155710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 11165710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 11175710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 11185710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 11195710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 11205710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 11215710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 11225710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 11235710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 11245710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 11255710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 11265710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 11275710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 11285710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 11295710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 11305710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 11315710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 11325710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 11335710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 11345710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 11355710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 11365710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 11375710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 11385710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 11395710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 11405710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 11415710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 11425710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 11435710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 11445710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 11455710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 11465710e16aSThierry Reding stream-match-mask = <0x7f80>; 11475710e16aSThierry Reding #global-interrupts = <1>; 11485710e16aSThierry Reding #iommu-cells = <1>; 11495710e16aSThierry Reding 11505710e16aSThierry Reding nvidia,memory-controller = <&mc>; 11515710e16aSThierry Reding status = "okay"; 11525710e16aSThierry Reding }; 11535710e16aSThierry Reding 11545710e16aSThierry Reding smmu_niso0: iommu@12000000 { 11555710e16aSThierry Reding compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; 11565710e16aSThierry Reding reg = <0x12000000 0x1000000>, 11575710e16aSThierry Reding <0x11000000 0x1000000>; 11585710e16aSThierry Reding interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11595710e16aSThierry Reding <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 11605710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11615710e16aSThierry Reding <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 11625710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11635710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11645710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11655710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11665710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11675710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11685710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11695710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11705710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11715710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11725710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11735710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11745710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11755710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11765710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11775710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11785710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11795710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11805710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11815710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11825710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11835710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11845710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11855710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11865710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11875710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11885710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11895710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11905710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11915710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11925710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11935710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11945710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11955710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11965710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11975710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11985710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 11995710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12005710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12015710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12025710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12035710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12045710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12055710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12065710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12075710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12085710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12095710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12105710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12115710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12125710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12135710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12145710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12155710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12165710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12175710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12185710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12195710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12205710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12215710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12225710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12235710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12245710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12255710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12265710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12275710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12285710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12295710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12305710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12315710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12325710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12335710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12345710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12355710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12365710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12375710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12385710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12395710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12405710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12415710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12425710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12435710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12445710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12455710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12465710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12475710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12485710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12495710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12505710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12515710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12525710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12535710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12545710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12555710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12565710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12575710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12585710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12595710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12605710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12615710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12625710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12635710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12645710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12655710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12665710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12675710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12685710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12695710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12705710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12715710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12725710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12735710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12745710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12755710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12765710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12775710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12785710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12795710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12805710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12815710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12825710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12835710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12845710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12855710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12865710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 12875710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 12885710e16aSThierry Reding stream-match-mask = <0x7f80>; 12895710e16aSThierry Reding #global-interrupts = <2>; 12905710e16aSThierry Reding #iommu-cells = <1>; 12915710e16aSThierry Reding 12925710e16aSThierry Reding nvidia,memory-controller = <&mc>; 12935710e16aSThierry Reding status = "okay"; 12945710e16aSThierry Reding }; 129563944891SThierry Reding }; 129663944891SThierry Reding 1297962c400dSSumit Gupta ccplex@e000000 { 1298962c400dSSumit Gupta compatible = "nvidia,tegra234-ccplex-cluster"; 1299962c400dSSumit Gupta reg = <0x0 0x0e000000 0x0 0x5ffff>; 1300962c400dSSumit Gupta nvidia,bpmp = <&bpmp>; 1301962c400dSSumit Gupta status = "okay"; 1302962c400dSSumit Gupta }; 1303962c400dSSumit Gupta 13047fa30752SThierry Reding sram@40000000 { 130563944891SThierry Reding compatible = "nvidia,tegra234-sysram", "mmio-sram"; 130698094be1SMikko Perttunen reg = <0x0 0x40000000 0x0 0x80000>; 130763944891SThierry Reding #address-cells = <1>; 130863944891SThierry Reding #size-cells = <1>; 130998094be1SMikko Perttunen ranges = <0x0 0x0 0x40000000 0x80000>; 131063944891SThierry Reding 131198094be1SMikko Perttunen cpu_bpmp_tx: sram@70000 { 131298094be1SMikko Perttunen reg = <0x70000 0x1000>; 131363944891SThierry Reding label = "cpu-bpmp-tx"; 131463944891SThierry Reding pool; 131563944891SThierry Reding }; 131663944891SThierry Reding 131798094be1SMikko Perttunen cpu_bpmp_rx: sram@71000 { 131898094be1SMikko Perttunen reg = <0x71000 0x1000>; 131963944891SThierry Reding label = "cpu-bpmp-rx"; 132063944891SThierry Reding pool; 132163944891SThierry Reding }; 132263944891SThierry Reding }; 132363944891SThierry Reding 132463944891SThierry Reding bpmp: bpmp { 132563944891SThierry Reding compatible = "nvidia,tegra234-bpmp", "nvidia,tegra186-bpmp"; 132663944891SThierry Reding mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 132763944891SThierry Reding TEGRA_HSP_DB_MASTER_BPMP>; 13287fa30752SThierry Reding shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; 132963944891SThierry Reding #clock-cells = <1>; 133063944891SThierry Reding #reset-cells = <1>; 133163944891SThierry Reding #power-domain-cells = <1>; 13326de481e5SThierry Reding interconnects = <&mc TEGRA234_MEMORY_CLIENT_BPMPR &emc>, 13336de481e5SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_BPMPW &emc>, 13346de481e5SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAR &emc>, 13356de481e5SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAW &emc>; 13366de481e5SThierry Reding interconnect-names = "read", "write", "dma-mem", "dma-write"; 13375710e16aSThierry Reding iommus = <&smmu_niso1 TEGRA234_SID_BPMP>; 133863944891SThierry Reding 133963944891SThierry Reding bpmp_i2c: i2c { 134063944891SThierry Reding compatible = "nvidia,tegra186-bpmp-i2c"; 134163944891SThierry Reding nvidia,bpmp-bus-id = <5>; 134263944891SThierry Reding #address-cells = <1>; 134363944891SThierry Reding #size-cells = <0>; 134463944891SThierry Reding }; 134563944891SThierry Reding }; 134663944891SThierry Reding 134763944891SThierry Reding cpus { 134863944891SThierry Reding #address-cells = <1>; 134963944891SThierry Reding #size-cells = <0>; 135063944891SThierry Reding 1351a12cf5c3SThierry Reding cpu0_0: cpu@0 { 1352a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 135363944891SThierry Reding device_type = "cpu"; 1354a12cf5c3SThierry Reding reg = <0x00000>; 135563944891SThierry Reding 135663944891SThierry Reding enable-method = "psci"; 1357a12cf5c3SThierry Reding 1358a12cf5c3SThierry Reding i-cache-size = <65536>; 1359a12cf5c3SThierry Reding i-cache-line-size = <64>; 1360a12cf5c3SThierry Reding i-cache-sets = <256>; 1361a12cf5c3SThierry Reding d-cache-size = <65536>; 1362a12cf5c3SThierry Reding d-cache-line-size = <64>; 1363a12cf5c3SThierry Reding d-cache-sets = <256>; 1364a12cf5c3SThierry Reding next-level-cache = <&l2c0_0>; 136563944891SThierry Reding }; 1366a12cf5c3SThierry Reding 1367a12cf5c3SThierry Reding cpu0_1: cpu@100 { 1368a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 1369a12cf5c3SThierry Reding device_type = "cpu"; 1370a12cf5c3SThierry Reding reg = <0x00100>; 1371a12cf5c3SThierry Reding 1372a12cf5c3SThierry Reding enable-method = "psci"; 1373a12cf5c3SThierry Reding 1374a12cf5c3SThierry Reding i-cache-size = <65536>; 1375a12cf5c3SThierry Reding i-cache-line-size = <64>; 1376a12cf5c3SThierry Reding i-cache-sets = <256>; 1377a12cf5c3SThierry Reding d-cache-size = <65536>; 1378a12cf5c3SThierry Reding d-cache-line-size = <64>; 1379a12cf5c3SThierry Reding d-cache-sets = <256>; 1380a12cf5c3SThierry Reding next-level-cache = <&l2c0_1>; 1381a12cf5c3SThierry Reding }; 1382a12cf5c3SThierry Reding 1383a12cf5c3SThierry Reding cpu0_2: cpu@200 { 1384a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 1385a12cf5c3SThierry Reding device_type = "cpu"; 1386a12cf5c3SThierry Reding reg = <0x00200>; 1387a12cf5c3SThierry Reding 1388a12cf5c3SThierry Reding enable-method = "psci"; 1389a12cf5c3SThierry Reding 1390a12cf5c3SThierry Reding i-cache-size = <65536>; 1391a12cf5c3SThierry Reding i-cache-line-size = <64>; 1392a12cf5c3SThierry Reding i-cache-sets = <256>; 1393a12cf5c3SThierry Reding d-cache-size = <65536>; 1394a12cf5c3SThierry Reding d-cache-line-size = <64>; 1395a12cf5c3SThierry Reding d-cache-sets = <256>; 1396a12cf5c3SThierry Reding next-level-cache = <&l2c0_2>; 1397a12cf5c3SThierry Reding }; 1398a12cf5c3SThierry Reding 1399a12cf5c3SThierry Reding cpu0_3: cpu@300 { 1400a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 1401a12cf5c3SThierry Reding device_type = "cpu"; 1402a12cf5c3SThierry Reding reg = <0x00300>; 1403a12cf5c3SThierry Reding 1404a12cf5c3SThierry Reding enable-method = "psci"; 1405a12cf5c3SThierry Reding 1406a12cf5c3SThierry Reding i-cache-size = <65536>; 1407a12cf5c3SThierry Reding i-cache-line-size = <64>; 1408a12cf5c3SThierry Reding i-cache-sets = <256>; 1409a12cf5c3SThierry Reding d-cache-size = <65536>; 1410a12cf5c3SThierry Reding d-cache-line-size = <64>; 1411a12cf5c3SThierry Reding d-cache-sets = <256>; 1412a12cf5c3SThierry Reding next-level-cache = <&l2c0_3>; 1413a12cf5c3SThierry Reding }; 1414a12cf5c3SThierry Reding 1415a12cf5c3SThierry Reding cpu1_0: cpu@10000 { 1416a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 1417a12cf5c3SThierry Reding device_type = "cpu"; 1418a12cf5c3SThierry Reding reg = <0x10000>; 1419a12cf5c3SThierry Reding 1420a12cf5c3SThierry Reding enable-method = "psci"; 1421a12cf5c3SThierry Reding 1422a12cf5c3SThierry Reding i-cache-size = <65536>; 1423a12cf5c3SThierry Reding i-cache-line-size = <64>; 1424a12cf5c3SThierry Reding i-cache-sets = <256>; 1425a12cf5c3SThierry Reding d-cache-size = <65536>; 1426a12cf5c3SThierry Reding d-cache-line-size = <64>; 1427a12cf5c3SThierry Reding d-cache-sets = <256>; 1428a12cf5c3SThierry Reding next-level-cache = <&l2c1_0>; 1429a12cf5c3SThierry Reding }; 1430a12cf5c3SThierry Reding 1431a12cf5c3SThierry Reding cpu1_1: cpu@10100 { 1432a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 1433a12cf5c3SThierry Reding device_type = "cpu"; 1434a12cf5c3SThierry Reding reg = <0x10100>; 1435a12cf5c3SThierry Reding 1436a12cf5c3SThierry Reding enable-method = "psci"; 1437a12cf5c3SThierry Reding 1438a12cf5c3SThierry Reding i-cache-size = <65536>; 1439a12cf5c3SThierry Reding i-cache-line-size = <64>; 1440a12cf5c3SThierry Reding i-cache-sets = <256>; 1441a12cf5c3SThierry Reding d-cache-size = <65536>; 1442a12cf5c3SThierry Reding d-cache-line-size = <64>; 1443a12cf5c3SThierry Reding d-cache-sets = <256>; 1444a12cf5c3SThierry Reding next-level-cache = <&l2c1_1>; 1445a12cf5c3SThierry Reding }; 1446a12cf5c3SThierry Reding 1447a12cf5c3SThierry Reding cpu1_2: cpu@10200 { 1448a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 1449a12cf5c3SThierry Reding device_type = "cpu"; 1450a12cf5c3SThierry Reding reg = <0x10200>; 1451a12cf5c3SThierry Reding 1452a12cf5c3SThierry Reding enable-method = "psci"; 1453a12cf5c3SThierry Reding 1454a12cf5c3SThierry Reding i-cache-size = <65536>; 1455a12cf5c3SThierry Reding i-cache-line-size = <64>; 1456a12cf5c3SThierry Reding i-cache-sets = <256>; 1457a12cf5c3SThierry Reding d-cache-size = <65536>; 1458a12cf5c3SThierry Reding d-cache-line-size = <64>; 1459a12cf5c3SThierry Reding d-cache-sets = <256>; 1460a12cf5c3SThierry Reding next-level-cache = <&l2c1_2>; 1461a12cf5c3SThierry Reding }; 1462a12cf5c3SThierry Reding 1463a12cf5c3SThierry Reding cpu1_3: cpu@10300 { 1464a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 1465a12cf5c3SThierry Reding device_type = "cpu"; 1466a12cf5c3SThierry Reding reg = <0x10300>; 1467a12cf5c3SThierry Reding 1468a12cf5c3SThierry Reding enable-method = "psci"; 1469a12cf5c3SThierry Reding 1470a12cf5c3SThierry Reding i-cache-size = <65536>; 1471a12cf5c3SThierry Reding i-cache-line-size = <64>; 1472a12cf5c3SThierry Reding i-cache-sets = <256>; 1473a12cf5c3SThierry Reding d-cache-size = <65536>; 1474a12cf5c3SThierry Reding d-cache-line-size = <64>; 1475a12cf5c3SThierry Reding d-cache-sets = <256>; 1476a12cf5c3SThierry Reding next-level-cache = <&l2c1_3>; 1477a12cf5c3SThierry Reding }; 1478a12cf5c3SThierry Reding 1479a12cf5c3SThierry Reding cpu2_0: cpu@20000 { 1480a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 1481a12cf5c3SThierry Reding device_type = "cpu"; 1482a12cf5c3SThierry Reding reg = <0x20000>; 1483a12cf5c3SThierry Reding 1484a12cf5c3SThierry Reding enable-method = "psci"; 1485a12cf5c3SThierry Reding 1486a12cf5c3SThierry Reding i-cache-size = <65536>; 1487a12cf5c3SThierry Reding i-cache-line-size = <64>; 1488a12cf5c3SThierry Reding i-cache-sets = <256>; 1489a12cf5c3SThierry Reding d-cache-size = <65536>; 1490a12cf5c3SThierry Reding d-cache-line-size = <64>; 1491a12cf5c3SThierry Reding d-cache-sets = <256>; 1492a12cf5c3SThierry Reding next-level-cache = <&l2c2_0>; 1493a12cf5c3SThierry Reding }; 1494a12cf5c3SThierry Reding 1495a12cf5c3SThierry Reding cpu2_1: cpu@20100 { 1496a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 1497a12cf5c3SThierry Reding device_type = "cpu"; 1498a12cf5c3SThierry Reding reg = <0x20100>; 1499a12cf5c3SThierry Reding 1500a12cf5c3SThierry Reding enable-method = "psci"; 1501a12cf5c3SThierry Reding 1502a12cf5c3SThierry Reding i-cache-size = <65536>; 1503a12cf5c3SThierry Reding i-cache-line-size = <64>; 1504a12cf5c3SThierry Reding i-cache-sets = <256>; 1505a12cf5c3SThierry Reding d-cache-size = <65536>; 1506a12cf5c3SThierry Reding d-cache-line-size = <64>; 1507a12cf5c3SThierry Reding d-cache-sets = <256>; 1508a12cf5c3SThierry Reding next-level-cache = <&l2c2_1>; 1509a12cf5c3SThierry Reding }; 1510a12cf5c3SThierry Reding 1511a12cf5c3SThierry Reding cpu2_2: cpu@20200 { 1512a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 1513a12cf5c3SThierry Reding device_type = "cpu"; 1514a12cf5c3SThierry Reding reg = <0x20200>; 1515a12cf5c3SThierry Reding 1516a12cf5c3SThierry Reding enable-method = "psci"; 1517a12cf5c3SThierry Reding 1518a12cf5c3SThierry Reding i-cache-size = <65536>; 1519a12cf5c3SThierry Reding i-cache-line-size = <64>; 1520a12cf5c3SThierry Reding i-cache-sets = <256>; 1521a12cf5c3SThierry Reding d-cache-size = <65536>; 1522a12cf5c3SThierry Reding d-cache-line-size = <64>; 1523a12cf5c3SThierry Reding d-cache-sets = <256>; 1524a12cf5c3SThierry Reding next-level-cache = <&l2c2_2>; 1525a12cf5c3SThierry Reding }; 1526a12cf5c3SThierry Reding 1527a12cf5c3SThierry Reding cpu2_3: cpu@20300 { 1528a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 1529a12cf5c3SThierry Reding device_type = "cpu"; 1530a12cf5c3SThierry Reding reg = <0x20300>; 1531a12cf5c3SThierry Reding 1532a12cf5c3SThierry Reding enable-method = "psci"; 1533a12cf5c3SThierry Reding 1534a12cf5c3SThierry Reding i-cache-size = <65536>; 1535a12cf5c3SThierry Reding i-cache-line-size = <64>; 1536a12cf5c3SThierry Reding i-cache-sets = <256>; 1537a12cf5c3SThierry Reding d-cache-size = <65536>; 1538a12cf5c3SThierry Reding d-cache-line-size = <64>; 1539a12cf5c3SThierry Reding d-cache-sets = <256>; 1540a12cf5c3SThierry Reding next-level-cache = <&l2c2_3>; 1541a12cf5c3SThierry Reding }; 1542a12cf5c3SThierry Reding 1543a12cf5c3SThierry Reding cpu-map { 1544a12cf5c3SThierry Reding cluster0 { 1545a12cf5c3SThierry Reding core0 { 1546a12cf5c3SThierry Reding cpu = <&cpu0_0>; 1547a12cf5c3SThierry Reding }; 1548a12cf5c3SThierry Reding 1549a12cf5c3SThierry Reding core1 { 1550a12cf5c3SThierry Reding cpu = <&cpu0_1>; 1551a12cf5c3SThierry Reding }; 1552a12cf5c3SThierry Reding 1553a12cf5c3SThierry Reding core2 { 1554a12cf5c3SThierry Reding cpu = <&cpu0_2>; 1555a12cf5c3SThierry Reding }; 1556a12cf5c3SThierry Reding 1557a12cf5c3SThierry Reding core3 { 1558a12cf5c3SThierry Reding cpu = <&cpu0_3>; 1559a12cf5c3SThierry Reding }; 1560a12cf5c3SThierry Reding }; 1561a12cf5c3SThierry Reding 1562a12cf5c3SThierry Reding cluster1 { 1563a12cf5c3SThierry Reding core0 { 1564a12cf5c3SThierry Reding cpu = <&cpu1_0>; 1565a12cf5c3SThierry Reding }; 1566a12cf5c3SThierry Reding 1567a12cf5c3SThierry Reding core1 { 1568a12cf5c3SThierry Reding cpu = <&cpu1_1>; 1569a12cf5c3SThierry Reding }; 1570a12cf5c3SThierry Reding 1571a12cf5c3SThierry Reding core2 { 1572a12cf5c3SThierry Reding cpu = <&cpu1_2>; 1573a12cf5c3SThierry Reding }; 1574a12cf5c3SThierry Reding 1575a12cf5c3SThierry Reding core3 { 1576a12cf5c3SThierry Reding cpu = <&cpu1_3>; 1577a12cf5c3SThierry Reding }; 1578a12cf5c3SThierry Reding }; 1579a12cf5c3SThierry Reding 1580a12cf5c3SThierry Reding cluster2 { 1581a12cf5c3SThierry Reding core0 { 1582a12cf5c3SThierry Reding cpu = <&cpu2_0>; 1583a12cf5c3SThierry Reding }; 1584a12cf5c3SThierry Reding 1585a12cf5c3SThierry Reding core1 { 1586a12cf5c3SThierry Reding cpu = <&cpu2_1>; 1587a12cf5c3SThierry Reding }; 1588a12cf5c3SThierry Reding 1589a12cf5c3SThierry Reding core2 { 1590a12cf5c3SThierry Reding cpu = <&cpu2_2>; 1591a12cf5c3SThierry Reding }; 1592a12cf5c3SThierry Reding 1593a12cf5c3SThierry Reding core3 { 1594a12cf5c3SThierry Reding cpu = <&cpu2_3>; 1595a12cf5c3SThierry Reding }; 1596a12cf5c3SThierry Reding }; 1597a12cf5c3SThierry Reding }; 1598a12cf5c3SThierry Reding 1599a12cf5c3SThierry Reding l2c0_0: l2-cache00 { 1600a12cf5c3SThierry Reding cache-size = <262144>; 1601a12cf5c3SThierry Reding cache-line-size = <64>; 1602a12cf5c3SThierry Reding cache-sets = <512>; 1603a12cf5c3SThierry Reding cache-unified; 1604a12cf5c3SThierry Reding next-level-cache = <&l3c0>; 1605a12cf5c3SThierry Reding }; 1606a12cf5c3SThierry Reding 1607a12cf5c3SThierry Reding l2c0_1: l2-cache01 { 1608a12cf5c3SThierry Reding cache-size = <262144>; 1609a12cf5c3SThierry Reding cache-line-size = <64>; 1610a12cf5c3SThierry Reding cache-sets = <512>; 1611a12cf5c3SThierry Reding cache-unified; 1612a12cf5c3SThierry Reding next-level-cache = <&l3c0>; 1613a12cf5c3SThierry Reding }; 1614a12cf5c3SThierry Reding 1615a12cf5c3SThierry Reding l2c0_2: l2-cache02 { 1616a12cf5c3SThierry Reding cache-size = <262144>; 1617a12cf5c3SThierry Reding cache-line-size = <64>; 1618a12cf5c3SThierry Reding cache-sets = <512>; 1619a12cf5c3SThierry Reding cache-unified; 1620a12cf5c3SThierry Reding next-level-cache = <&l3c0>; 1621a12cf5c3SThierry Reding }; 1622a12cf5c3SThierry Reding 1623a12cf5c3SThierry Reding l2c0_3: l2-cache03 { 1624a12cf5c3SThierry Reding cache-size = <262144>; 1625a12cf5c3SThierry Reding cache-line-size = <64>; 1626a12cf5c3SThierry Reding cache-sets = <512>; 1627a12cf5c3SThierry Reding cache-unified; 1628a12cf5c3SThierry Reding next-level-cache = <&l3c0>; 1629a12cf5c3SThierry Reding }; 1630a12cf5c3SThierry Reding 1631a12cf5c3SThierry Reding l2c1_0: l2-cache10 { 1632a12cf5c3SThierry Reding cache-size = <262144>; 1633a12cf5c3SThierry Reding cache-line-size = <64>; 1634a12cf5c3SThierry Reding cache-sets = <512>; 1635a12cf5c3SThierry Reding cache-unified; 1636a12cf5c3SThierry Reding next-level-cache = <&l3c1>; 1637a12cf5c3SThierry Reding }; 1638a12cf5c3SThierry Reding 1639a12cf5c3SThierry Reding l2c1_1: l2-cache11 { 1640a12cf5c3SThierry Reding cache-size = <262144>; 1641a12cf5c3SThierry Reding cache-line-size = <64>; 1642a12cf5c3SThierry Reding cache-sets = <512>; 1643a12cf5c3SThierry Reding cache-unified; 1644a12cf5c3SThierry Reding next-level-cache = <&l3c1>; 1645a12cf5c3SThierry Reding }; 1646a12cf5c3SThierry Reding 1647a12cf5c3SThierry Reding l2c1_2: l2-cache12 { 1648a12cf5c3SThierry Reding cache-size = <262144>; 1649a12cf5c3SThierry Reding cache-line-size = <64>; 1650a12cf5c3SThierry Reding cache-sets = <512>; 1651a12cf5c3SThierry Reding cache-unified; 1652a12cf5c3SThierry Reding next-level-cache = <&l3c1>; 1653a12cf5c3SThierry Reding }; 1654a12cf5c3SThierry Reding 1655a12cf5c3SThierry Reding l2c1_3: l2-cache13 { 1656a12cf5c3SThierry Reding cache-size = <262144>; 1657a12cf5c3SThierry Reding cache-line-size = <64>; 1658a12cf5c3SThierry Reding cache-sets = <512>; 1659a12cf5c3SThierry Reding cache-unified; 1660a12cf5c3SThierry Reding next-level-cache = <&l3c1>; 1661a12cf5c3SThierry Reding }; 1662a12cf5c3SThierry Reding 1663a12cf5c3SThierry Reding l2c2_0: l2-cache20 { 1664a12cf5c3SThierry Reding cache-size = <262144>; 1665a12cf5c3SThierry Reding cache-line-size = <64>; 1666a12cf5c3SThierry Reding cache-sets = <512>; 1667a12cf5c3SThierry Reding cache-unified; 1668a12cf5c3SThierry Reding next-level-cache = <&l3c2>; 1669a12cf5c3SThierry Reding }; 1670a12cf5c3SThierry Reding 1671a12cf5c3SThierry Reding l2c2_1: l2-cache21 { 1672a12cf5c3SThierry Reding cache-size = <262144>; 1673a12cf5c3SThierry Reding cache-line-size = <64>; 1674a12cf5c3SThierry Reding cache-sets = <512>; 1675a12cf5c3SThierry Reding cache-unified; 1676a12cf5c3SThierry Reding next-level-cache = <&l3c2>; 1677a12cf5c3SThierry Reding }; 1678a12cf5c3SThierry Reding 1679a12cf5c3SThierry Reding l2c2_2: l2-cache22 { 1680a12cf5c3SThierry Reding cache-size = <262144>; 1681a12cf5c3SThierry Reding cache-line-size = <64>; 1682a12cf5c3SThierry Reding cache-sets = <512>; 1683a12cf5c3SThierry Reding cache-unified; 1684a12cf5c3SThierry Reding next-level-cache = <&l3c2>; 1685a12cf5c3SThierry Reding }; 1686a12cf5c3SThierry Reding 1687a12cf5c3SThierry Reding l2c2_3: l2-cache23 { 1688a12cf5c3SThierry Reding cache-size = <262144>; 1689a12cf5c3SThierry Reding cache-line-size = <64>; 1690a12cf5c3SThierry Reding cache-sets = <512>; 1691a12cf5c3SThierry Reding cache-unified; 1692a12cf5c3SThierry Reding next-level-cache = <&l3c2>; 1693a12cf5c3SThierry Reding }; 1694a12cf5c3SThierry Reding 1695a12cf5c3SThierry Reding l3c0: l3-cache0 { 1696a12cf5c3SThierry Reding cache-size = <2097152>; 1697a12cf5c3SThierry Reding cache-line-size = <64>; 1698a12cf5c3SThierry Reding cache-sets = <2048>; 1699a12cf5c3SThierry Reding }; 1700a12cf5c3SThierry Reding 1701a12cf5c3SThierry Reding l3c1: l3-cache1 { 1702a12cf5c3SThierry Reding cache-size = <2097152>; 1703a12cf5c3SThierry Reding cache-line-size = <64>; 1704a12cf5c3SThierry Reding cache-sets = <2048>; 1705a12cf5c3SThierry Reding }; 1706a12cf5c3SThierry Reding 1707a12cf5c3SThierry Reding l3c2: l3-cache2 { 1708a12cf5c3SThierry Reding cache-size = <2097152>; 1709a12cf5c3SThierry Reding cache-line-size = <64>; 1710a12cf5c3SThierry Reding cache-sets = <2048>; 1711a12cf5c3SThierry Reding }; 1712a12cf5c3SThierry Reding }; 1713a12cf5c3SThierry Reding 1714a12cf5c3SThierry Reding pmu { 1715a12cf5c3SThierry Reding compatible = "arm,cortex-a78-pmu"; 1716a12cf5c3SThierry Reding interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 1717a12cf5c3SThierry Reding status = "okay"; 171863944891SThierry Reding }; 171963944891SThierry Reding 172063944891SThierry Reding psci { 172163944891SThierry Reding compatible = "arm,psci-1.0"; 172263944891SThierry Reding status = "okay"; 172363944891SThierry Reding method = "smc"; 172463944891SThierry Reding }; 172563944891SThierry Reding 172606ad2ec4SMikko Perttunen tcu: serial { 172706ad2ec4SMikko Perttunen compatible = "nvidia,tegra234-tcu", "nvidia,tegra194-tcu"; 172806ad2ec4SMikko Perttunen mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 172906ad2ec4SMikko Perttunen <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 173006ad2ec4SMikko Perttunen mbox-names = "rx", "tx"; 173106ad2ec4SMikko Perttunen status = "disabled"; 173206ad2ec4SMikko Perttunen }; 173306ad2ec4SMikko Perttunen 173409614acdSSameer Pujar sound { 173509614acdSSameer Pujar status = "disabled"; 173609614acdSSameer Pujar 173709614acdSSameer Pujar clocks = <&bpmp TEGRA234_CLK_PLLA>, 173809614acdSSameer Pujar <&bpmp TEGRA234_CLK_PLLA_OUT0>; 173909614acdSSameer Pujar clock-names = "pll_a", "plla_out0"; 174009614acdSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_PLLA>, 174109614acdSSameer Pujar <&bpmp TEGRA234_CLK_PLLA_OUT0>, 174209614acdSSameer Pujar <&bpmp TEGRA234_CLK_AUD_MCLK>; 174309614acdSSameer Pujar assigned-clock-parents = <0>, 174409614acdSSameer Pujar <&bpmp TEGRA234_CLK_PLLA>, 174509614acdSSameer Pujar <&bpmp TEGRA234_CLK_PLLA_OUT0>; 174609614acdSSameer Pujar }; 174709614acdSSameer Pujar 174863944891SThierry Reding timer { 174963944891SThierry Reding compatible = "arm,armv8-timer"; 175063944891SThierry Reding interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 175163944891SThierry Reding <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 175263944891SThierry Reding <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 175363944891SThierry Reding <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 175463944891SThierry Reding interrupt-parent = <&gic>; 175563944891SThierry Reding always-on; 175663944891SThierry Reding }; 175763944891SThierry Reding}; 1758