163944891SThierry Reding// SPDX-License-Identifier: GPL-2.0 263944891SThierry Reding 363944891SThierry Reding#include <dt-bindings/clock/tegra234-clock.h> 4699349e0SThierry Reding#include <dt-bindings/gpio/tegra234-gpio.h> 563944891SThierry Reding#include <dt-bindings/interrupt-controller/arm-gic.h> 663944891SThierry Reding#include <dt-bindings/mailbox/tegra186-hsp.h> 7eed280dfSThierry Reding#include <dt-bindings/memory/tegra234-mc.h> 8c71e1897SThierry Reding#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 9dc94a94dSSameer Pujar#include <dt-bindings/power/tegra234-powergate.h> 1063944891SThierry Reding#include <dt-bindings/reset/tegra234-reset.h> 1163944891SThierry Reding 1263944891SThierry Reding/ { 1363944891SThierry Reding compatible = "nvidia,tegra234"; 1463944891SThierry Reding interrupt-parent = <&gic>; 1563944891SThierry Reding #address-cells = <2>; 1663944891SThierry Reding #size-cells = <2>; 1763944891SThierry Reding 1863944891SThierry Reding bus@0 { 1963944891SThierry Reding compatible = "simple-bus"; 2063944891SThierry Reding 212838cfddSThierry Reding #address-cells = <2>; 222838cfddSThierry Reding #size-cells = <2>; 232838cfddSThierry Reding ranges = <0x0 0x0 0x0 0x0 0x0 0x40000000>; 2463944891SThierry Reding 2579ed18d9SThierry Reding misc@100000 { 2679ed18d9SThierry Reding compatible = "nvidia,tegra234-misc"; 2779ed18d9SThierry Reding reg = <0x0 0x00100000 0x0 0xf000>, 2879ed18d9SThierry Reding <0x0 0x0010f000 0x0 0x1000>; 2979ed18d9SThierry Reding status = "okay"; 3079ed18d9SThierry Reding }; 3179ed18d9SThierry Reding 3279ed18d9SThierry Reding timer@2080000 { 3379ed18d9SThierry Reding compatible = "nvidia,tegra234-timer"; 3479ed18d9SThierry Reding reg = <0x0 0x02080000 0x0 0x00121000>; 3579ed18d9SThierry Reding interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 3679ed18d9SThierry Reding <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 3779ed18d9SThierry Reding <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 3879ed18d9SThierry Reding <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3979ed18d9SThierry Reding <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 4079ed18d9SThierry Reding <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 4179ed18d9SThierry Reding <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 4279ed18d9SThierry Reding <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 4379ed18d9SThierry Reding <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 4479ed18d9SThierry Reding <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 4579ed18d9SThierry Reding <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 4679ed18d9SThierry Reding <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 4779ed18d9SThierry Reding <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 4879ed18d9SThierry Reding <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 4979ed18d9SThierry Reding <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 5079ed18d9SThierry Reding <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 5179ed18d9SThierry Reding status = "okay"; 5279ed18d9SThierry Reding }; 5379ed18d9SThierry Reding 5479ed18d9SThierry Reding gpio: gpio@2200000 { 5579ed18d9SThierry Reding compatible = "nvidia,tegra234-gpio"; 5679ed18d9SThierry Reding reg-names = "security", "gpio"; 5779ed18d9SThierry Reding reg = <0x0 0x02200000 0x0 0x10000>, 5879ed18d9SThierry Reding <0x0 0x02210000 0x0 0x10000>; 5979ed18d9SThierry Reding interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 6079ed18d9SThierry Reding <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 6179ed18d9SThierry Reding <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 6279ed18d9SThierry Reding <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, 6379ed18d9SThierry Reding <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 6479ed18d9SThierry Reding <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 6579ed18d9SThierry Reding <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 6679ed18d9SThierry Reding <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 6779ed18d9SThierry Reding <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 6879ed18d9SThierry Reding <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 6979ed18d9SThierry Reding <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 7079ed18d9SThierry Reding <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 7179ed18d9SThierry Reding <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 7279ed18d9SThierry Reding <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 7379ed18d9SThierry Reding <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 7479ed18d9SThierry Reding <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 7579ed18d9SThierry Reding <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 7679ed18d9SThierry Reding <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 7779ed18d9SThierry Reding <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 7879ed18d9SThierry Reding <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 7979ed18d9SThierry Reding <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 8079ed18d9SThierry Reding <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 8179ed18d9SThierry Reding <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 8279ed18d9SThierry Reding <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 8379ed18d9SThierry Reding <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 8479ed18d9SThierry Reding <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 8579ed18d9SThierry Reding <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 8679ed18d9SThierry Reding <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 8779ed18d9SThierry Reding <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 8879ed18d9SThierry Reding <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 8979ed18d9SThierry Reding <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 9079ed18d9SThierry Reding <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 9179ed18d9SThierry Reding <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 9279ed18d9SThierry Reding <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 9379ed18d9SThierry Reding <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 9479ed18d9SThierry Reding <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 9579ed18d9SThierry Reding <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 9679ed18d9SThierry Reding <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 9779ed18d9SThierry Reding <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 9879ed18d9SThierry Reding <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 9979ed18d9SThierry Reding <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 10079ed18d9SThierry Reding <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 10179ed18d9SThierry Reding <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 10279ed18d9SThierry Reding <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 10379ed18d9SThierry Reding <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 10479ed18d9SThierry Reding <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 10579ed18d9SThierry Reding <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 10679ed18d9SThierry Reding <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 10779ed18d9SThierry Reding #interrupt-cells = <2>; 10879ed18d9SThierry Reding interrupt-controller; 10979ed18d9SThierry Reding #gpio-cells = <2>; 11079ed18d9SThierry Reding gpio-controller; 11179ed18d9SThierry Reding }; 11279ed18d9SThierry Reding 11360d2016aSAkhil R gpcdma: dma-controller@2600000 { 114f7b93a08SAkhil R compatible = "nvidia,tegra234-gpcdma", 11560d2016aSAkhil R "nvidia,tegra186-gpcdma"; 1162838cfddSThierry Reding reg = <0x0 0x2600000 0x0 0x210000>; 11760d2016aSAkhil R resets = <&bpmp TEGRA234_RESET_GPCDMA>; 11860d2016aSAkhil R reset-names = "gpcdma"; 119dd0be827SAkhil R interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 120dd0be827SAkhil R <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 12160d2016aSAkhil R <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 12260d2016aSAkhil R <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 12360d2016aSAkhil R <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 12460d2016aSAkhil R <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 12560d2016aSAkhil R <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 12660d2016aSAkhil R <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 12760d2016aSAkhil R <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 12860d2016aSAkhil R <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 12960d2016aSAkhil R <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 13060d2016aSAkhil R <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 13160d2016aSAkhil R <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 13260d2016aSAkhil R <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 13360d2016aSAkhil R <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 13460d2016aSAkhil R <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 13560d2016aSAkhil R <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 13660d2016aSAkhil R <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 13760d2016aSAkhil R <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 13860d2016aSAkhil R <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 13960d2016aSAkhil R <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 14060d2016aSAkhil R <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 14160d2016aSAkhil R <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 14260d2016aSAkhil R <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 14360d2016aSAkhil R <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 14460d2016aSAkhil R <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 14560d2016aSAkhil R <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 14660d2016aSAkhil R <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 14760d2016aSAkhil R <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 14860d2016aSAkhil R <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 14960d2016aSAkhil R <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 15060d2016aSAkhil R <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 15160d2016aSAkhil R #dma-cells = <1>; 15260d2016aSAkhil R iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 153dd0be827SAkhil R dma-channel-mask = <0xfffffffe>; 15460d2016aSAkhil R dma-coherent; 15560d2016aSAkhil R }; 15660d2016aSAkhil R 157dc94a94dSSameer Pujar aconnect@2900000 { 158dc94a94dSSameer Pujar compatible = "nvidia,tegra234-aconnect", 159dc94a94dSSameer Pujar "nvidia,tegra210-aconnect"; 160dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_APE>, 161dc94a94dSSameer Pujar <&bpmp TEGRA234_CLK_APB2APE>; 162dc94a94dSSameer Pujar clock-names = "ape", "apb2ape"; 163dc94a94dSSameer Pujar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_AUD>; 164dc94a94dSSameer Pujar status = "disabled"; 165dc94a94dSSameer Pujar 1662838cfddSThierry Reding #address-cells = <2>; 1672838cfddSThierry Reding #size-cells = <2>; 1682838cfddSThierry Reding ranges = <0x0 0x02900000 0x0 0x02900000 0x0 0x200000>; 1692838cfddSThierry Reding 170dc94a94dSSameer Pujar tegra_ahub: ahub@2900800 { 171dc94a94dSSameer Pujar compatible = "nvidia,tegra234-ahub"; 1722838cfddSThierry Reding reg = <0x0 0x02900800 0x0 0x800>; 173dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_AHUB>; 174dc94a94dSSameer Pujar clock-names = "ahub"; 175dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_AHUB>; 176dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 177dc94a94dSSameer Pujar status = "disabled"; 178dc94a94dSSameer Pujar 1792838cfddSThierry Reding #address-cells = <2>; 1802838cfddSThierry Reding #size-cells = <2>; 1812838cfddSThierry Reding ranges = <0x0 0x02900800 0x0 0x02900800 0x0 0x11800>; 1822838cfddSThierry Reding 183dc94a94dSSameer Pujar tegra_i2s1: i2s@2901000 { 184dc94a94dSSameer Pujar compatible = "nvidia,tegra234-i2s", 185dc94a94dSSameer Pujar "nvidia,tegra210-i2s"; 1862838cfddSThierry Reding reg = <0x0 0x2901000 0x0 0x100>; 187dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_I2S1>, 188dc94a94dSSameer Pujar <&bpmp TEGRA234_CLK_I2S1_SYNC_INPUT>; 189dc94a94dSSameer Pujar clock-names = "i2s", "sync_input"; 190dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_I2S1>; 191dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 192dc94a94dSSameer Pujar assigned-clock-rates = <1536000>; 193dc94a94dSSameer Pujar sound-name-prefix = "I2S1"; 194dc94a94dSSameer Pujar status = "disabled"; 195dc94a94dSSameer Pujar }; 196dc94a94dSSameer Pujar 197dc94a94dSSameer Pujar tegra_i2s2: i2s@2901100 { 198dc94a94dSSameer Pujar compatible = "nvidia,tegra234-i2s", 199dc94a94dSSameer Pujar "nvidia,tegra210-i2s"; 2002838cfddSThierry Reding reg = <0x0 0x2901100 0x0 0x100>; 201dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_I2S2>, 202dc94a94dSSameer Pujar <&bpmp TEGRA234_CLK_I2S2_SYNC_INPUT>; 203dc94a94dSSameer Pujar clock-names = "i2s", "sync_input"; 204dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_I2S2>; 205dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 206dc94a94dSSameer Pujar assigned-clock-rates = <1536000>; 207dc94a94dSSameer Pujar sound-name-prefix = "I2S2"; 208dc94a94dSSameer Pujar status = "disabled"; 209dc94a94dSSameer Pujar }; 210dc94a94dSSameer Pujar 211dc94a94dSSameer Pujar tegra_i2s3: i2s@2901200 { 212dc94a94dSSameer Pujar compatible = "nvidia,tegra234-i2s", 213dc94a94dSSameer Pujar "nvidia,tegra210-i2s"; 2142838cfddSThierry Reding reg = <0x0 0x2901200 0x0 0x100>; 215dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_I2S3>, 216dc94a94dSSameer Pujar <&bpmp TEGRA234_CLK_I2S3_SYNC_INPUT>; 217dc94a94dSSameer Pujar clock-names = "i2s", "sync_input"; 218dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_I2S3>; 219dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 220dc94a94dSSameer Pujar assigned-clock-rates = <1536000>; 221dc94a94dSSameer Pujar sound-name-prefix = "I2S3"; 222dc94a94dSSameer Pujar status = "disabled"; 223dc94a94dSSameer Pujar }; 224dc94a94dSSameer Pujar 225dc94a94dSSameer Pujar tegra_i2s4: i2s@2901300 { 226dc94a94dSSameer Pujar compatible = "nvidia,tegra234-i2s", 227dc94a94dSSameer Pujar "nvidia,tegra210-i2s"; 2282838cfddSThierry Reding reg = <0x0 0x2901300 0x0 0x100>; 229dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_I2S4>, 230dc94a94dSSameer Pujar <&bpmp TEGRA234_CLK_I2S4_SYNC_INPUT>; 231dc94a94dSSameer Pujar clock-names = "i2s", "sync_input"; 232dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_I2S4>; 233dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 234dc94a94dSSameer Pujar assigned-clock-rates = <1536000>; 235dc94a94dSSameer Pujar sound-name-prefix = "I2S4"; 236dc94a94dSSameer Pujar status = "disabled"; 237dc94a94dSSameer Pujar }; 238dc94a94dSSameer Pujar 239dc94a94dSSameer Pujar tegra_i2s5: i2s@2901400 { 240dc94a94dSSameer Pujar compatible = "nvidia,tegra234-i2s", 241dc94a94dSSameer Pujar "nvidia,tegra210-i2s"; 2422838cfddSThierry Reding reg = <0x0 0x2901400 0x0 0x100>; 243dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_I2S5>, 244dc94a94dSSameer Pujar <&bpmp TEGRA234_CLK_I2S5_SYNC_INPUT>; 245dc94a94dSSameer Pujar clock-names = "i2s", "sync_input"; 246dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_I2S5>; 247dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 248dc94a94dSSameer Pujar assigned-clock-rates = <1536000>; 249dc94a94dSSameer Pujar sound-name-prefix = "I2S5"; 250dc94a94dSSameer Pujar status = "disabled"; 251dc94a94dSSameer Pujar }; 252dc94a94dSSameer Pujar 253dc94a94dSSameer Pujar tegra_i2s6: i2s@2901500 { 254dc94a94dSSameer Pujar compatible = "nvidia,tegra234-i2s", 255dc94a94dSSameer Pujar "nvidia,tegra210-i2s"; 2562838cfddSThierry Reding reg = <0x0 0x2901500 0x0 0x100>; 257dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_I2S6>, 258dc94a94dSSameer Pujar <&bpmp TEGRA234_CLK_I2S6_SYNC_INPUT>; 259dc94a94dSSameer Pujar clock-names = "i2s", "sync_input"; 260dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_I2S6>; 261dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 262dc94a94dSSameer Pujar assigned-clock-rates = <1536000>; 263dc94a94dSSameer Pujar sound-name-prefix = "I2S6"; 264dc94a94dSSameer Pujar status = "disabled"; 265dc94a94dSSameer Pujar }; 266dc94a94dSSameer Pujar 267dc94a94dSSameer Pujar tegra_sfc1: sfc@2902000 { 268dc94a94dSSameer Pujar compatible = "nvidia,tegra234-sfc", 269dc94a94dSSameer Pujar "nvidia,tegra210-sfc"; 2702838cfddSThierry Reding reg = <0x0 0x2902000 0x0 0x200>; 271dc94a94dSSameer Pujar sound-name-prefix = "SFC1"; 272dc94a94dSSameer Pujar status = "disabled"; 273dc94a94dSSameer Pujar }; 274dc94a94dSSameer Pujar 275dc94a94dSSameer Pujar tegra_sfc2: sfc@2902200 { 276dc94a94dSSameer Pujar compatible = "nvidia,tegra234-sfc", 277dc94a94dSSameer Pujar "nvidia,tegra210-sfc"; 2782838cfddSThierry Reding reg = <0x0 0x2902200 0x0 0x200>; 279dc94a94dSSameer Pujar sound-name-prefix = "SFC2"; 280dc94a94dSSameer Pujar status = "disabled"; 281dc94a94dSSameer Pujar }; 282dc94a94dSSameer Pujar 283dc94a94dSSameer Pujar tegra_sfc3: sfc@2902400 { 284dc94a94dSSameer Pujar compatible = "nvidia,tegra234-sfc", 285dc94a94dSSameer Pujar "nvidia,tegra210-sfc"; 2862838cfddSThierry Reding reg = <0x0 0x2902400 0x0 0x200>; 287dc94a94dSSameer Pujar sound-name-prefix = "SFC3"; 288dc94a94dSSameer Pujar status = "disabled"; 289dc94a94dSSameer Pujar }; 290dc94a94dSSameer Pujar 291dc94a94dSSameer Pujar tegra_sfc4: sfc@2902600 { 292dc94a94dSSameer Pujar compatible = "nvidia,tegra234-sfc", 293dc94a94dSSameer Pujar "nvidia,tegra210-sfc"; 2942838cfddSThierry Reding reg = <0x0 0x2902600 0x0 0x200>; 295dc94a94dSSameer Pujar sound-name-prefix = "SFC4"; 296dc94a94dSSameer Pujar status = "disabled"; 297dc94a94dSSameer Pujar }; 298dc94a94dSSameer Pujar 299dc94a94dSSameer Pujar tegra_amx1: amx@2903000 { 300dc94a94dSSameer Pujar compatible = "nvidia,tegra234-amx", 301dc94a94dSSameer Pujar "nvidia,tegra194-amx"; 3022838cfddSThierry Reding reg = <0x0 0x2903000 0x0 0x100>; 303dc94a94dSSameer Pujar sound-name-prefix = "AMX1"; 304dc94a94dSSameer Pujar status = "disabled"; 305dc94a94dSSameer Pujar }; 306dc94a94dSSameer Pujar 307dc94a94dSSameer Pujar tegra_amx2: amx@2903100 { 308dc94a94dSSameer Pujar compatible = "nvidia,tegra234-amx", 309dc94a94dSSameer Pujar "nvidia,tegra194-amx"; 3102838cfddSThierry Reding reg = <0x0 0x2903100 0x0 0x100>; 311dc94a94dSSameer Pujar sound-name-prefix = "AMX2"; 312dc94a94dSSameer Pujar status = "disabled"; 313dc94a94dSSameer Pujar }; 314dc94a94dSSameer Pujar 315dc94a94dSSameer Pujar tegra_amx3: amx@2903200 { 316dc94a94dSSameer Pujar compatible = "nvidia,tegra234-amx", 317dc94a94dSSameer Pujar "nvidia,tegra194-amx"; 3182838cfddSThierry Reding reg = <0x0 0x2903200 0x0 0x100>; 319dc94a94dSSameer Pujar sound-name-prefix = "AMX3"; 320dc94a94dSSameer Pujar status = "disabled"; 321dc94a94dSSameer Pujar }; 322dc94a94dSSameer Pujar 323dc94a94dSSameer Pujar tegra_amx4: amx@2903300 { 324dc94a94dSSameer Pujar compatible = "nvidia,tegra234-amx", 325dc94a94dSSameer Pujar "nvidia,tegra194-amx"; 3262838cfddSThierry Reding reg = <0x0 0x2903300 0x0 0x100>; 327dc94a94dSSameer Pujar sound-name-prefix = "AMX4"; 328dc94a94dSSameer Pujar status = "disabled"; 329dc94a94dSSameer Pujar }; 330dc94a94dSSameer Pujar 331dc94a94dSSameer Pujar tegra_adx1: adx@2903800 { 332dc94a94dSSameer Pujar compatible = "nvidia,tegra234-adx", 333dc94a94dSSameer Pujar "nvidia,tegra210-adx"; 3342838cfddSThierry Reding reg = <0x0 0x2903800 0x0 0x100>; 335dc94a94dSSameer Pujar sound-name-prefix = "ADX1"; 336dc94a94dSSameer Pujar status = "disabled"; 337dc94a94dSSameer Pujar }; 338dc94a94dSSameer Pujar 339dc94a94dSSameer Pujar tegra_adx2: adx@2903900 { 340dc94a94dSSameer Pujar compatible = "nvidia,tegra234-adx", 341dc94a94dSSameer Pujar "nvidia,tegra210-adx"; 3422838cfddSThierry Reding reg = <0x0 0x2903900 0x0 0x100>; 343dc94a94dSSameer Pujar sound-name-prefix = "ADX2"; 344dc94a94dSSameer Pujar status = "disabled"; 345dc94a94dSSameer Pujar }; 346dc94a94dSSameer Pujar 347dc94a94dSSameer Pujar tegra_adx3: adx@2903a00 { 348dc94a94dSSameer Pujar compatible = "nvidia,tegra234-adx", 349dc94a94dSSameer Pujar "nvidia,tegra210-adx"; 3502838cfddSThierry Reding reg = <0x0 0x2903a00 0x0 0x100>; 351dc94a94dSSameer Pujar sound-name-prefix = "ADX3"; 352dc94a94dSSameer Pujar status = "disabled"; 353dc94a94dSSameer Pujar }; 354dc94a94dSSameer Pujar 355dc94a94dSSameer Pujar tegra_adx4: adx@2903b00 { 356dc94a94dSSameer Pujar compatible = "nvidia,tegra234-adx", 357dc94a94dSSameer Pujar "nvidia,tegra210-adx"; 3582838cfddSThierry Reding reg = <0x0 0x2903b00 0x0 0x100>; 359dc94a94dSSameer Pujar sound-name-prefix = "ADX4"; 360dc94a94dSSameer Pujar status = "disabled"; 361dc94a94dSSameer Pujar }; 362dc94a94dSSameer Pujar 363dc94a94dSSameer Pujar 364dc94a94dSSameer Pujar tegra_dmic1: dmic@2904000 { 365dc94a94dSSameer Pujar compatible = "nvidia,tegra234-dmic", 366dc94a94dSSameer Pujar "nvidia,tegra210-dmic"; 3672838cfddSThierry Reding reg = <0x0 0x2904000 0x0 0x100>; 368dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_DMIC1>; 369dc94a94dSSameer Pujar clock-names = "dmic"; 370dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_DMIC1>; 371dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 372dc94a94dSSameer Pujar assigned-clock-rates = <3072000>; 373dc94a94dSSameer Pujar sound-name-prefix = "DMIC1"; 374dc94a94dSSameer Pujar status = "disabled"; 375dc94a94dSSameer Pujar }; 376dc94a94dSSameer Pujar 377dc94a94dSSameer Pujar tegra_dmic2: dmic@2904100 { 378dc94a94dSSameer Pujar compatible = "nvidia,tegra234-dmic", 379dc94a94dSSameer Pujar "nvidia,tegra210-dmic"; 3802838cfddSThierry Reding reg = <0x0 0x2904100 0x0 0x100>; 381dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_DMIC2>; 382dc94a94dSSameer Pujar clock-names = "dmic"; 383dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_DMIC2>; 384dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 385dc94a94dSSameer Pujar assigned-clock-rates = <3072000>; 386dc94a94dSSameer Pujar sound-name-prefix = "DMIC2"; 387dc94a94dSSameer Pujar status = "disabled"; 388dc94a94dSSameer Pujar }; 389dc94a94dSSameer Pujar 390dc94a94dSSameer Pujar tegra_dmic3: dmic@2904200 { 391dc94a94dSSameer Pujar compatible = "nvidia,tegra234-dmic", 392dc94a94dSSameer Pujar "nvidia,tegra210-dmic"; 3932838cfddSThierry Reding reg = <0x0 0x2904200 0x0 0x100>; 394dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_DMIC3>; 395dc94a94dSSameer Pujar clock-names = "dmic"; 396dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_DMIC3>; 397dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 398dc94a94dSSameer Pujar assigned-clock-rates = <3072000>; 399dc94a94dSSameer Pujar sound-name-prefix = "DMIC3"; 400dc94a94dSSameer Pujar status = "disabled"; 401dc94a94dSSameer Pujar }; 402dc94a94dSSameer Pujar 403dc94a94dSSameer Pujar tegra_dmic4: dmic@2904300 { 404dc94a94dSSameer Pujar compatible = "nvidia,tegra234-dmic", 405dc94a94dSSameer Pujar "nvidia,tegra210-dmic"; 4062838cfddSThierry Reding reg = <0x0 0x2904300 0x0 0x100>; 407dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_DMIC4>; 408dc94a94dSSameer Pujar clock-names = "dmic"; 409dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_DMIC4>; 410dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 411dc94a94dSSameer Pujar assigned-clock-rates = <3072000>; 412dc94a94dSSameer Pujar sound-name-prefix = "DMIC4"; 413dc94a94dSSameer Pujar status = "disabled"; 414dc94a94dSSameer Pujar }; 415dc94a94dSSameer Pujar 416dc94a94dSSameer Pujar tegra_dspk1: dspk@2905000 { 417dc94a94dSSameer Pujar compatible = "nvidia,tegra234-dspk", 418dc94a94dSSameer Pujar "nvidia,tegra186-dspk"; 4192838cfddSThierry Reding reg = <0x0 0x2905000 0x0 0x100>; 420dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_DSPK1>; 421dc94a94dSSameer Pujar clock-names = "dspk"; 422dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_DSPK1>; 423dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 424dc94a94dSSameer Pujar assigned-clock-rates = <12288000>; 425dc94a94dSSameer Pujar sound-name-prefix = "DSPK1"; 426dc94a94dSSameer Pujar status = "disabled"; 427dc94a94dSSameer Pujar }; 428dc94a94dSSameer Pujar 429dc94a94dSSameer Pujar tegra_dspk2: dspk@2905100 { 430dc94a94dSSameer Pujar compatible = "nvidia,tegra234-dspk", 431dc94a94dSSameer Pujar "nvidia,tegra186-dspk"; 4322838cfddSThierry Reding reg = <0x0 0x2905100 0x0 0x100>; 433dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_DSPK2>; 434dc94a94dSSameer Pujar clock-names = "dspk"; 435dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_DSPK2>; 436dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 437dc94a94dSSameer Pujar assigned-clock-rates = <12288000>; 438dc94a94dSSameer Pujar sound-name-prefix = "DSPK2"; 439dc94a94dSSameer Pujar status = "disabled"; 440dc94a94dSSameer Pujar }; 441dc94a94dSSameer Pujar 4424b6a1b7cSSameer Pujar tegra_ope1: processing-engine@2908000 { 4434b6a1b7cSSameer Pujar compatible = "nvidia,tegra234-ope", 4444b6a1b7cSSameer Pujar "nvidia,tegra210-ope"; 4452838cfddSThierry Reding reg = <0x0 0x2908000 0x0 0x100>; 4464b6a1b7cSSameer Pujar sound-name-prefix = "OPE1"; 4474b6a1b7cSSameer Pujar status = "disabled"; 4484b6a1b7cSSameer Pujar 4492838cfddSThierry Reding #address-cells = <2>; 4502838cfddSThierry Reding #size-cells = <2>; 4512838cfddSThierry Reding ranges; 4522838cfddSThierry Reding 4534b6a1b7cSSameer Pujar equalizer@2908100 { 4544b6a1b7cSSameer Pujar compatible = "nvidia,tegra234-peq", 4554b6a1b7cSSameer Pujar "nvidia,tegra210-peq"; 4562838cfddSThierry Reding reg = <0x0 0x2908100 0x0 0x100>; 4574b6a1b7cSSameer Pujar }; 4584b6a1b7cSSameer Pujar 4594b6a1b7cSSameer Pujar dynamic-range-compressor@2908200 { 4604b6a1b7cSSameer Pujar compatible = "nvidia,tegra234-mbdrc", 4614b6a1b7cSSameer Pujar "nvidia,tegra210-mbdrc"; 4622838cfddSThierry Reding reg = <0x0 0x2908200 0x0 0x200>; 4634b6a1b7cSSameer Pujar }; 4644b6a1b7cSSameer Pujar }; 4654b6a1b7cSSameer Pujar 466dc94a94dSSameer Pujar tegra_mvc1: mvc@290a000 { 467dc94a94dSSameer Pujar compatible = "nvidia,tegra234-mvc", 468dc94a94dSSameer Pujar "nvidia,tegra210-mvc"; 4692838cfddSThierry Reding reg = <0x0 0x290a000 0x0 0x200>; 470dc94a94dSSameer Pujar sound-name-prefix = "MVC1"; 471dc94a94dSSameer Pujar status = "disabled"; 472dc94a94dSSameer Pujar }; 473dc94a94dSSameer Pujar 474dc94a94dSSameer Pujar tegra_mvc2: mvc@290a200 { 475dc94a94dSSameer Pujar compatible = "nvidia,tegra234-mvc", 476dc94a94dSSameer Pujar "nvidia,tegra210-mvc"; 4772838cfddSThierry Reding reg = <0x0 0x290a200 0x0 0x200>; 478dc94a94dSSameer Pujar sound-name-prefix = "MVC2"; 479dc94a94dSSameer Pujar status = "disabled"; 480dc94a94dSSameer Pujar }; 481dc94a94dSSameer Pujar 482dc94a94dSSameer Pujar tegra_amixer: amixer@290bb00 { 483dc94a94dSSameer Pujar compatible = "nvidia,tegra234-amixer", 484dc94a94dSSameer Pujar "nvidia,tegra210-amixer"; 4852838cfddSThierry Reding reg = <0x0 0x290bb00 0x0 0x800>; 486dc94a94dSSameer Pujar sound-name-prefix = "MIXER1"; 487dc94a94dSSameer Pujar status = "disabled"; 488dc94a94dSSameer Pujar }; 489dc94a94dSSameer Pujar 490dc94a94dSSameer Pujar tegra_admaif: admaif@290f000 { 491dc94a94dSSameer Pujar compatible = "nvidia,tegra234-admaif", 492dc94a94dSSameer Pujar "nvidia,tegra186-admaif"; 4932838cfddSThierry Reding reg = <0x0 0x0290f000 0x0 0x1000>; 494dc94a94dSSameer Pujar dmas = <&adma 1>, <&adma 1>, 495dc94a94dSSameer Pujar <&adma 2>, <&adma 2>, 496dc94a94dSSameer Pujar <&adma 3>, <&adma 3>, 497dc94a94dSSameer Pujar <&adma 4>, <&adma 4>, 498dc94a94dSSameer Pujar <&adma 5>, <&adma 5>, 499dc94a94dSSameer Pujar <&adma 6>, <&adma 6>, 500dc94a94dSSameer Pujar <&adma 7>, <&adma 7>, 501dc94a94dSSameer Pujar <&adma 8>, <&adma 8>, 502dc94a94dSSameer Pujar <&adma 9>, <&adma 9>, 503dc94a94dSSameer Pujar <&adma 10>, <&adma 10>, 504dc94a94dSSameer Pujar <&adma 11>, <&adma 11>, 505dc94a94dSSameer Pujar <&adma 12>, <&adma 12>, 506dc94a94dSSameer Pujar <&adma 13>, <&adma 13>, 507dc94a94dSSameer Pujar <&adma 14>, <&adma 14>, 508dc94a94dSSameer Pujar <&adma 15>, <&adma 15>, 509dc94a94dSSameer Pujar <&adma 16>, <&adma 16>, 510dc94a94dSSameer Pujar <&adma 17>, <&adma 17>, 511dc94a94dSSameer Pujar <&adma 18>, <&adma 18>, 512dc94a94dSSameer Pujar <&adma 19>, <&adma 19>, 513dc94a94dSSameer Pujar <&adma 20>, <&adma 20>; 514dc94a94dSSameer Pujar dma-names = "rx1", "tx1", 515dc94a94dSSameer Pujar "rx2", "tx2", 516dc94a94dSSameer Pujar "rx3", "tx3", 517dc94a94dSSameer Pujar "rx4", "tx4", 518dc94a94dSSameer Pujar "rx5", "tx5", 519dc94a94dSSameer Pujar "rx6", "tx6", 520dc94a94dSSameer Pujar "rx7", "tx7", 521dc94a94dSSameer Pujar "rx8", "tx8", 522dc94a94dSSameer Pujar "rx9", "tx9", 523dc94a94dSSameer Pujar "rx10", "tx10", 524dc94a94dSSameer Pujar "rx11", "tx11", 525dc94a94dSSameer Pujar "rx12", "tx12", 526dc94a94dSSameer Pujar "rx13", "tx13", 527dc94a94dSSameer Pujar "rx14", "tx14", 528dc94a94dSSameer Pujar "rx15", "tx15", 529dc94a94dSSameer Pujar "rx16", "tx16", 530dc94a94dSSameer Pujar "rx17", "tx17", 531dc94a94dSSameer Pujar "rx18", "tx18", 532dc94a94dSSameer Pujar "rx19", "tx19", 533dc94a94dSSameer Pujar "rx20", "tx20"; 534dc94a94dSSameer Pujar interconnects = <&mc TEGRA234_MEMORY_CLIENT_APEDMAR &emc>, 535dc94a94dSSameer Pujar <&mc TEGRA234_MEMORY_CLIENT_APEDMAW &emc>; 536dc94a94dSSameer Pujar interconnect-names = "dma-mem", "write"; 537dc94a94dSSameer Pujar iommus = <&smmu_niso0 TEGRA234_SID_APE>; 538dc94a94dSSameer Pujar status = "disabled"; 539dc94a94dSSameer Pujar }; 54047a08153SSameer Pujar 54147a08153SSameer Pujar tegra_asrc: asrc@2910000 { 54247a08153SSameer Pujar compatible = "nvidia,tegra234-asrc", 54347a08153SSameer Pujar "nvidia,tegra186-asrc"; 5442838cfddSThierry Reding reg = <0x0 0x2910000 0x0 0x2000>; 54547a08153SSameer Pujar sound-name-prefix = "ASRC1"; 54647a08153SSameer Pujar status = "disabled"; 54747a08153SSameer Pujar }; 548dc94a94dSSameer Pujar }; 549dc94a94dSSameer Pujar 550dc94a94dSSameer Pujar adma: dma-controller@2930000 { 551dc94a94dSSameer Pujar compatible = "nvidia,tegra234-adma", 552dc94a94dSSameer Pujar "nvidia,tegra186-adma"; 5532838cfddSThierry Reding reg = <0x0 0x02930000 0x0 0x20000>; 554dc94a94dSSameer Pujar interrupt-parent = <&agic>; 555dc94a94dSSameer Pujar interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 556dc94a94dSSameer Pujar <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 557dc94a94dSSameer Pujar <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 558dc94a94dSSameer Pujar <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 559dc94a94dSSameer Pujar <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 560dc94a94dSSameer Pujar <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 561dc94a94dSSameer Pujar <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 562dc94a94dSSameer Pujar <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 563dc94a94dSSameer Pujar <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 564dc94a94dSSameer Pujar <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 565dc94a94dSSameer Pujar <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 566dc94a94dSSameer Pujar <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 567dc94a94dSSameer Pujar <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 568dc94a94dSSameer Pujar <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 569dc94a94dSSameer Pujar <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 570dc94a94dSSameer Pujar <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 571dc94a94dSSameer Pujar <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 572dc94a94dSSameer Pujar <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 573dc94a94dSSameer Pujar <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 574dc94a94dSSameer Pujar <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 575dc94a94dSSameer Pujar <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 576dc94a94dSSameer Pujar <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 577dc94a94dSSameer Pujar <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 578dc94a94dSSameer Pujar <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 579dc94a94dSSameer Pujar <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 580dc94a94dSSameer Pujar <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 581dc94a94dSSameer Pujar <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 582dc94a94dSSameer Pujar <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 583dc94a94dSSameer Pujar <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 584dc94a94dSSameer Pujar <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 585dc94a94dSSameer Pujar <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 586dc94a94dSSameer Pujar <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 587dc94a94dSSameer Pujar #dma-cells = <1>; 588dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_AHUB>; 589dc94a94dSSameer Pujar clock-names = "d_audio"; 590dc94a94dSSameer Pujar status = "disabled"; 591dc94a94dSSameer Pujar }; 592dc94a94dSSameer Pujar 593dc94a94dSSameer Pujar agic: interrupt-controller@2a40000 { 594dc94a94dSSameer Pujar compatible = "nvidia,tegra234-agic", 595dc94a94dSSameer Pujar "nvidia,tegra210-agic"; 596dc94a94dSSameer Pujar #interrupt-cells = <3>; 597dc94a94dSSameer Pujar interrupt-controller; 5982838cfddSThierry Reding reg = <0x0 0x02a41000 0x0 0x1000>, 5992838cfddSThierry Reding <0x0 0x02a42000 0x0 0x2000>; 600dc94a94dSSameer Pujar interrupts = <GIC_SPI 145 601dc94a94dSSameer Pujar (GIC_CPU_MASK_SIMPLE(4) | 602dc94a94dSSameer Pujar IRQ_TYPE_LEVEL_HIGH)>; 603dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_APE>; 604dc94a94dSSameer Pujar clock-names = "clk"; 605dc94a94dSSameer Pujar status = "disabled"; 606dc94a94dSSameer Pujar }; 607dc94a94dSSameer Pujar }; 608dc94a94dSSameer Pujar 609eed280dfSThierry Reding mc: memory-controller@2c00000 { 610eed280dfSThierry Reding compatible = "nvidia,tegra234-mc"; 6112838cfddSThierry Reding reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */ 6122838cfddSThierry Reding <0x0 0x02c10000 0x0 0x10000>, /* MC Broadcast*/ 6132838cfddSThierry Reding <0x0 0x02c20000 0x0 0x10000>, /* MC0 */ 6142838cfddSThierry Reding <0x0 0x02c30000 0x0 0x10000>, /* MC1 */ 6152838cfddSThierry Reding <0x0 0x02c40000 0x0 0x10000>, /* MC2 */ 6162838cfddSThierry Reding <0x0 0x02c50000 0x0 0x10000>, /* MC3 */ 6172838cfddSThierry Reding <0x0 0x02b80000 0x0 0x10000>, /* MC4 */ 6182838cfddSThierry Reding <0x0 0x02b90000 0x0 0x10000>, /* MC5 */ 6192838cfddSThierry Reding <0x0 0x02ba0000 0x0 0x10000>, /* MC6 */ 6202838cfddSThierry Reding <0x0 0x02bb0000 0x0 0x10000>, /* MC7 */ 6212838cfddSThierry Reding <0x0 0x01700000 0x0 0x10000>, /* MC8 */ 6222838cfddSThierry Reding <0x0 0x01710000 0x0 0x10000>, /* MC9 */ 6232838cfddSThierry Reding <0x0 0x01720000 0x0 0x10000>, /* MC10 */ 6242838cfddSThierry Reding <0x0 0x01730000 0x0 0x10000>, /* MC11 */ 6252838cfddSThierry Reding <0x0 0x01740000 0x0 0x10000>, /* MC12 */ 6262838cfddSThierry Reding <0x0 0x01750000 0x0 0x10000>, /* MC13 */ 6272838cfddSThierry Reding <0x0 0x01760000 0x0 0x10000>, /* MC14 */ 6282838cfddSThierry Reding <0x0 0x01770000 0x0 0x10000>; /* MC15 */ 629000b99e5SAshish Mhetre reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3", 630000b99e5SAshish Mhetre "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", 631000b99e5SAshish Mhetre "ch11", "ch12", "ch13", "ch14", "ch15"; 632eed280dfSThierry Reding interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 633eed280dfSThierry Reding #interconnect-cells = <1>; 634eed280dfSThierry Reding status = "okay"; 635eed280dfSThierry Reding 636eed280dfSThierry Reding #address-cells = <2>; 637eed280dfSThierry Reding #size-cells = <2>; 6382838cfddSThierry Reding ranges = <0x0 0x01700000 0x0 0x01700000 0x0 0x100000>, 6392838cfddSThierry Reding <0x0 0x02b80000 0x0 0x02b80000 0x0 0x040000>, 6402838cfddSThierry Reding <0x0 0x02c00000 0x0 0x02c00000 0x0 0x100000>; 641eed280dfSThierry Reding 642eed280dfSThierry Reding /* 643eed280dfSThierry Reding * Bit 39 of addresses passing through the memory 644eed280dfSThierry Reding * controller selects the XBAR format used when memory 645eed280dfSThierry Reding * is accessed. This is used to transparently access 646eed280dfSThierry Reding * memory in the XBAR format used by the discrete GPU 647eed280dfSThierry Reding * (bit 39 set) or Tegra (bit 39 clear). 648eed280dfSThierry Reding * 649eed280dfSThierry Reding * As a consequence, the operating system must ensure 650eed280dfSThierry Reding * that bit 39 is never used implicitly, for example 651eed280dfSThierry Reding * via an I/O virtual address mapping of an IOMMU. If 652eed280dfSThierry Reding * devices require access to the XBAR switch, their 653eed280dfSThierry Reding * drivers must set this bit explicitly. 654eed280dfSThierry Reding * 655eed280dfSThierry Reding * Limit the DMA range for memory clients to [38:0]. 656eed280dfSThierry Reding */ 6572838cfddSThierry Reding dma-ranges = <0x0 0x0 0x0 0x0 0x80 0x0>; 658eed280dfSThierry Reding 659eed280dfSThierry Reding emc: external-memory-controller@2c60000 { 660eed280dfSThierry Reding compatible = "nvidia,tegra234-emc"; 661eed280dfSThierry Reding reg = <0x0 0x02c60000 0x0 0x90000>, 662eed280dfSThierry Reding <0x0 0x01780000 0x0 0x80000>; 663eed280dfSThierry Reding interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 664eed280dfSThierry Reding clocks = <&bpmp TEGRA234_CLK_EMC>; 665eed280dfSThierry Reding clock-names = "emc"; 666eed280dfSThierry Reding status = "okay"; 667eed280dfSThierry Reding 668eed280dfSThierry Reding #interconnect-cells = <0>; 669eed280dfSThierry Reding 670eed280dfSThierry Reding nvidia,bpmp = <&bpmp>; 671eed280dfSThierry Reding }; 672eed280dfSThierry Reding }; 673eed280dfSThierry Reding 67463944891SThierry Reding uarta: serial@3100000 { 67563944891SThierry Reding compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart"; 6762838cfddSThierry Reding reg = <0x0 0x03100000 0x0 0x10000>; 67763944891SThierry Reding interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 67863944891SThierry Reding clocks = <&bpmp TEGRA234_CLK_UARTA>; 67963944891SThierry Reding clock-names = "serial"; 68063944891SThierry Reding resets = <&bpmp TEGRA234_RESET_UARTA>; 68163944891SThierry Reding reset-names = "serial"; 68263944891SThierry Reding status = "disabled"; 68363944891SThierry Reding }; 68463944891SThierry Reding 685156af9deSAkhil R gen1_i2c: i2c@3160000 { 686156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 6872838cfddSThierry Reding reg = <0x0 0x3160000 0x0 0x100>; 688156af9deSAkhil R status = "disabled"; 689156af9deSAkhil R interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 690260e8d42SJon Hunter #address-cells = <1>; 691260e8d42SJon Hunter #size-cells = <0>; 692156af9deSAkhil R clock-frequency = <400000>; 693156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C1 694156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 695156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C1>; 696156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 697156af9deSAkhil R clock-names = "div-clk", "parent"; 698156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C1>; 699156af9deSAkhil R reset-names = "i2c"; 7008e442805SAkhil R iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 7018e442805SAkhil R dma-coherent; 7028e442805SAkhil R dmas = <&gpcdma 21>, <&gpcdma 21>; 7038e442805SAkhil R dma-names = "rx", "tx"; 704156af9deSAkhil R }; 705156af9deSAkhil R 706156af9deSAkhil R cam_i2c: i2c@3180000 { 707156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 7082838cfddSThierry Reding reg = <0x0 0x3180000 0x0 0x100>; 709156af9deSAkhil R interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 710260e8d42SJon Hunter #address-cells = <1>; 711260e8d42SJon Hunter #size-cells = <0>; 712156af9deSAkhil R status = "disabled"; 713156af9deSAkhil R clock-frequency = <400000>; 714156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C3 715156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 716156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C3>; 717156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 718156af9deSAkhil R clock-names = "div-clk", "parent"; 719156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C3>; 720156af9deSAkhil R reset-names = "i2c"; 7218e442805SAkhil R iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 7228e442805SAkhil R dma-coherent; 7238e442805SAkhil R dmas = <&gpcdma 23>, <&gpcdma 23>; 7248e442805SAkhil R dma-names = "rx", "tx"; 725156af9deSAkhil R }; 726156af9deSAkhil R 727156af9deSAkhil R dp_aux_ch1_i2c: i2c@3190000 { 728156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 7292838cfddSThierry Reding reg = <0x0 0x3190000 0x0 0x100>; 730156af9deSAkhil R interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 731260e8d42SJon Hunter #address-cells = <1>; 732260e8d42SJon Hunter #size-cells = <0>; 733156af9deSAkhil R status = "disabled"; 734156af9deSAkhil R clock-frequency = <100000>; 735156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C4 736156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 737156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C4>; 738156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 739156af9deSAkhil R clock-names = "div-clk", "parent"; 740156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C4>; 741156af9deSAkhil R reset-names = "i2c"; 7428e442805SAkhil R iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 7438e442805SAkhil R dma-coherent; 7448e442805SAkhil R dmas = <&gpcdma 26>, <&gpcdma 26>; 7458e442805SAkhil R dma-names = "rx", "tx"; 746156af9deSAkhil R }; 747156af9deSAkhil R 748156af9deSAkhil R dp_aux_ch0_i2c: i2c@31b0000 { 749156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 7502838cfddSThierry Reding reg = <0x0 0x31b0000 0x0 0x100>; 751156af9deSAkhil R interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 752260e8d42SJon Hunter #address-cells = <1>; 753260e8d42SJon Hunter #size-cells = <0>; 754156af9deSAkhil R status = "disabled"; 755156af9deSAkhil R clock-frequency = <100000>; 756156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C6 757156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 758156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C6>; 759156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 760156af9deSAkhil R clock-names = "div-clk", "parent"; 761156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C6>; 762156af9deSAkhil R reset-names = "i2c"; 7638e442805SAkhil R iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 7648e442805SAkhil R dma-coherent; 7658e442805SAkhil R dmas = <&gpcdma 30>, <&gpcdma 30>; 7668e442805SAkhil R dma-names = "rx", "tx"; 767156af9deSAkhil R }; 768156af9deSAkhil R 769156af9deSAkhil R dp_aux_ch2_i2c: i2c@31c0000 { 770156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 7712838cfddSThierry Reding reg = <0x0 0x31c0000 0x0 0x100>; 772156af9deSAkhil R interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 773260e8d42SJon Hunter #address-cells = <1>; 774260e8d42SJon Hunter #size-cells = <0>; 775156af9deSAkhil R status = "disabled"; 776156af9deSAkhil R clock-frequency = <100000>; 777156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C7 778156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 779156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C7>; 780156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 781156af9deSAkhil R clock-names = "div-clk", "parent"; 782156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C7>; 783156af9deSAkhil R reset-names = "i2c"; 7848e442805SAkhil R iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 7858e442805SAkhil R dma-coherent; 7868e442805SAkhil R dmas = <&gpcdma 27>, <&gpcdma 27>; 7878e442805SAkhil R dma-names = "rx", "tx"; 788156af9deSAkhil R }; 789156af9deSAkhil R 7901bbba854SJon Hunter uarti: serial@31d0000 { 7911bbba854SJon Hunter compatible = "arm,sbsa-uart"; 7922838cfddSThierry Reding reg = <0x0 0x31d0000 0x0 0x10000>; 7931bbba854SJon Hunter interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; 7941bbba854SJon Hunter status = "disabled"; 7951bbba854SJon Hunter }; 7961bbba854SJon Hunter 797156af9deSAkhil R dp_aux_ch3_i2c: i2c@31e0000 { 798156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 7992838cfddSThierry Reding reg = <0x0 0x31e0000 0x0 0x100>; 800156af9deSAkhil R interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 801260e8d42SJon Hunter #address-cells = <1>; 802260e8d42SJon Hunter #size-cells = <0>; 803156af9deSAkhil R status = "disabled"; 804156af9deSAkhil R clock-frequency = <100000>; 805156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C9 806156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 807156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C9>; 808156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 809156af9deSAkhil R clock-names = "div-clk", "parent"; 810156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C9>; 811156af9deSAkhil R reset-names = "i2c"; 8128e442805SAkhil R iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 8138e442805SAkhil R dma-coherent; 8148e442805SAkhil R dmas = <&gpcdma 31>, <&gpcdma 31>; 8158e442805SAkhil R dma-names = "rx", "tx"; 816156af9deSAkhil R }; 817156af9deSAkhil R 81871f69ffaSAshish Singhal spi@3270000 { 81971f69ffaSAshish Singhal compatible = "nvidia,tegra234-qspi"; 8202838cfddSThierry Reding reg = <0x0 0x3270000 0x0 0x1000>; 82171f69ffaSAshish Singhal interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 82271f69ffaSAshish Singhal #address-cells = <1>; 82371f69ffaSAshish Singhal #size-cells = <0>; 82471f69ffaSAshish Singhal clocks = <&bpmp TEGRA234_CLK_QSPI0_2X_PM>, 82571f69ffaSAshish Singhal <&bpmp TEGRA234_CLK_QSPI0_PM>; 82671f69ffaSAshish Singhal clock-names = "qspi", "qspi_out"; 82771f69ffaSAshish Singhal resets = <&bpmp TEGRA234_RESET_QSPI0>; 82871f69ffaSAshish Singhal status = "disabled"; 82971f69ffaSAshish Singhal }; 83071f69ffaSAshish Singhal 8315e69088dSAkhil R pwm1: pwm@3280000 { 8322566d28cSJon Hunter compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 8332838cfddSThierry Reding reg = <0x0 0x3280000 0x0 0x10000>; 8345e69088dSAkhil R clocks = <&bpmp TEGRA234_CLK_PWM1>; 8355e69088dSAkhil R resets = <&bpmp TEGRA234_RESET_PWM1>; 8365e69088dSAkhil R reset-names = "pwm"; 8375e69088dSAkhil R status = "disabled"; 8385e69088dSAkhil R #pwm-cells = <2>; 8395e69088dSAkhil R }; 8405e69088dSAkhil R 8412566d28cSJon Hunter pwm2: pwm@3290000 { 8422566d28cSJon Hunter compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 8432838cfddSThierry Reding reg = <0x0 0x3290000 0x0 0x10000>; 8442566d28cSJon Hunter clocks = <&bpmp TEGRA234_CLK_PWM2>; 8452566d28cSJon Hunter resets = <&bpmp TEGRA234_RESET_PWM2>; 8462566d28cSJon Hunter reset-names = "pwm"; 8472566d28cSJon Hunter status = "disabled"; 8482566d28cSJon Hunter #pwm-cells = <2>; 8492566d28cSJon Hunter }; 8502566d28cSJon Hunter 8512566d28cSJon Hunter pwm3: pwm@32a0000 { 8522566d28cSJon Hunter compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 8532838cfddSThierry Reding reg = <0x0 0x32a0000 0x0 0x10000>; 8542566d28cSJon Hunter clocks = <&bpmp TEGRA234_CLK_PWM3>; 8552566d28cSJon Hunter resets = <&bpmp TEGRA234_RESET_PWM3>; 8562566d28cSJon Hunter reset-names = "pwm"; 8572566d28cSJon Hunter status = "disabled"; 8582566d28cSJon Hunter #pwm-cells = <2>; 8592566d28cSJon Hunter }; 8602566d28cSJon Hunter 8612566d28cSJon Hunter pwm5: pwm@32c0000 { 8622566d28cSJon Hunter compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 8632838cfddSThierry Reding reg = <0x0 0x32c0000 0x0 0x10000>; 8642566d28cSJon Hunter clocks = <&bpmp TEGRA234_CLK_PWM5>; 8652566d28cSJon Hunter resets = <&bpmp TEGRA234_RESET_PWM5>; 8662566d28cSJon Hunter reset-names = "pwm"; 8672566d28cSJon Hunter status = "disabled"; 8682566d28cSJon Hunter #pwm-cells = <2>; 8692566d28cSJon Hunter }; 8702566d28cSJon Hunter 8712566d28cSJon Hunter pwm6: pwm@32d0000 { 8722566d28cSJon Hunter compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 8732838cfddSThierry Reding reg = <0x0 0x32d0000 0x0 0x10000>; 8742566d28cSJon Hunter clocks = <&bpmp TEGRA234_CLK_PWM6>; 8752566d28cSJon Hunter resets = <&bpmp TEGRA234_RESET_PWM6>; 8762566d28cSJon Hunter reset-names = "pwm"; 8772566d28cSJon Hunter status = "disabled"; 8782566d28cSJon Hunter #pwm-cells = <2>; 8792566d28cSJon Hunter }; 8802566d28cSJon Hunter 8812566d28cSJon Hunter pwm7: pwm@32e0000 { 8822566d28cSJon Hunter compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 8832838cfddSThierry Reding reg = <0x0 0x32e0000 0x0 0x10000>; 8842566d28cSJon Hunter clocks = <&bpmp TEGRA234_CLK_PWM7>; 8852566d28cSJon Hunter resets = <&bpmp TEGRA234_RESET_PWM7>; 8862566d28cSJon Hunter reset-names = "pwm"; 8872566d28cSJon Hunter status = "disabled"; 8882566d28cSJon Hunter #pwm-cells = <2>; 8892566d28cSJon Hunter }; 8902566d28cSJon Hunter 8912566d28cSJon Hunter pwm8: pwm@32f0000 { 8922566d28cSJon Hunter compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 8932838cfddSThierry Reding reg = <0x0 0x32f0000 0x0 0x10000>; 8942566d28cSJon Hunter clocks = <&bpmp TEGRA234_CLK_PWM8>; 8952566d28cSJon Hunter resets = <&bpmp TEGRA234_RESET_PWM8>; 8962566d28cSJon Hunter reset-names = "pwm"; 8972566d28cSJon Hunter status = "disabled"; 8982566d28cSJon Hunter #pwm-cells = <2>; 8992566d28cSJon Hunter }; 9002566d28cSJon Hunter 90171f69ffaSAshish Singhal spi@3300000 { 90271f69ffaSAshish Singhal compatible = "nvidia,tegra234-qspi"; 9032838cfddSThierry Reding reg = <0x0 0x3300000 0x0 0x1000>; 90471f69ffaSAshish Singhal interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 90571f69ffaSAshish Singhal #address-cells = <1>; 90671f69ffaSAshish Singhal #size-cells = <0>; 90771f69ffaSAshish Singhal clocks = <&bpmp TEGRA234_CLK_QSPI1_2X_PM>, 90871f69ffaSAshish Singhal <&bpmp TEGRA234_CLK_QSPI1_PM>; 90971f69ffaSAshish Singhal clock-names = "qspi", "qspi_out"; 91071f69ffaSAshish Singhal resets = <&bpmp TEGRA234_RESET_QSPI1>; 91171f69ffaSAshish Singhal status = "disabled"; 91271f69ffaSAshish Singhal }; 91371f69ffaSAshish Singhal 914d71b893aSPrathamesh Shete mmc@3400000 { 915132b552cSThierry Reding compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci"; 9162838cfddSThierry Reding reg = <0x0 0x03400000 0x0 0x20000>; 917d71b893aSPrathamesh Shete interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 918d71b893aSPrathamesh Shete clocks = <&bpmp TEGRA234_CLK_SDMMC1>, 919d71b893aSPrathamesh Shete <&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>; 920d71b893aSPrathamesh Shete clock-names = "sdhci", "tmclk"; 921d71b893aSPrathamesh Shete assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC1>, 922d71b893aSPrathamesh Shete <&bpmp TEGRA234_CLK_PLLC4_MUXED>; 923d71b893aSPrathamesh Shete assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4_MUXED>, 924d71b893aSPrathamesh Shete <&bpmp TEGRA234_CLK_PLLC4_VCO_DIV2>; 925d71b893aSPrathamesh Shete resets = <&bpmp TEGRA234_RESET_SDMMC1>; 926d71b893aSPrathamesh Shete reset-names = "sdhci"; 927d71b893aSPrathamesh Shete interconnects = <&mc TEGRA234_MEMORY_CLIENT_SDMMCRA &emc>, 928d71b893aSPrathamesh Shete <&mc TEGRA234_MEMORY_CLIENT_SDMMCWA &emc>; 929d71b893aSPrathamesh Shete interconnect-names = "dma-mem", "write"; 930d71b893aSPrathamesh Shete iommus = <&smmu_niso1 TEGRA234_SID_SDMMC1A>; 931d71b893aSPrathamesh Shete pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 932d71b893aSPrathamesh Shete pinctrl-0 = <&sdmmc1_3v3>; 933d71b893aSPrathamesh Shete pinctrl-1 = <&sdmmc1_1v8>; 934d71b893aSPrathamesh Shete nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 935d71b893aSPrathamesh Shete nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x07>; 936d71b893aSPrathamesh Shete nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 937d71b893aSPrathamesh Shete nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 938d71b893aSPrathamesh Shete nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 939d71b893aSPrathamesh Shete nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 940d71b893aSPrathamesh Shete nvidia,default-tap = <14>; 941d71b893aSPrathamesh Shete nvidia,default-trim = <0x8>; 942d71b893aSPrathamesh Shete sd-uhs-sdr25; 943d71b893aSPrathamesh Shete sd-uhs-sdr50; 944d71b893aSPrathamesh Shete sd-uhs-ddr50; 945d71b893aSPrathamesh Shete sd-uhs-sdr104; 946d71b893aSPrathamesh Shete status = "disabled"; 947d71b893aSPrathamesh Shete }; 948d71b893aSPrathamesh Shete 94963944891SThierry Reding mmc@3460000 { 95063944891SThierry Reding compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci"; 9512838cfddSThierry Reding reg = <0x0 0x03460000 0x0 0x20000>; 95263944891SThierry Reding interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 953e086d82dSMikko Perttunen clocks = <&bpmp TEGRA234_CLK_SDMMC4>, 954e086d82dSMikko Perttunen <&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>; 955e086d82dSMikko Perttunen clock-names = "sdhci", "tmclk"; 956e086d82dSMikko Perttunen assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC4>, 957e086d82dSMikko Perttunen <&bpmp TEGRA234_CLK_PLLC4>; 958e086d82dSMikko Perttunen assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4>; 95963944891SThierry Reding resets = <&bpmp TEGRA234_RESET_SDMMC4>; 96063944891SThierry Reding reset-names = "sdhci"; 9616de481e5SThierry Reding interconnects = <&mc TEGRA234_MEMORY_CLIENT_SDMMCRAB &emc>, 9626de481e5SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_SDMMCWAB &emc>; 9636de481e5SThierry Reding interconnect-names = "dma-mem", "write"; 9645710e16aSThierry Reding iommus = <&smmu_niso1 TEGRA234_SID_SDMMC4>; 965e086d82dSMikko Perttunen nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 966e086d82dSMikko Perttunen nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 967e086d82dSMikko Perttunen nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 968e086d82dSMikko Perttunen nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; 969e086d82dSMikko Perttunen nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 970e086d82dSMikko Perttunen nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>; 971e086d82dSMikko Perttunen nvidia,default-tap = <0x8>; 972e086d82dSMikko Perttunen nvidia,default-trim = <0x14>; 973e086d82dSMikko Perttunen nvidia,dqs-trim = <40>; 974e086d82dSMikko Perttunen supports-cqe; 97563944891SThierry Reding status = "disabled"; 97663944891SThierry Reding }; 97763944891SThierry Reding 978621e12a1SMohan Kumar hda@3510000 { 979b2fbcbe1SThierry Reding compatible = "nvidia,tegra234-hda"; 9802838cfddSThierry Reding reg = <0x0 0x3510000 0x0 0x10000>; 981621e12a1SMohan Kumar interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 982621e12a1SMohan Kumar clocks = <&bpmp TEGRA234_CLK_AZA_BIT>, 983621e12a1SMohan Kumar <&bpmp TEGRA234_CLK_AZA_2XBIT>; 984621e12a1SMohan Kumar clock-names = "hda", "hda2codec_2x"; 985621e12a1SMohan Kumar resets = <&bpmp TEGRA234_RESET_HDA>, 986621e12a1SMohan Kumar <&bpmp TEGRA234_RESET_HDACODEC>; 987621e12a1SMohan Kumar reset-names = "hda", "hda2codec_2x"; 988621e12a1SMohan Kumar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_DISP>; 989621e12a1SMohan Kumar interconnects = <&mc TEGRA234_MEMORY_CLIENT_HDAR &emc>, 990621e12a1SMohan Kumar <&mc TEGRA234_MEMORY_CLIENT_HDAW &emc>; 991621e12a1SMohan Kumar interconnect-names = "dma-mem", "write"; 992af4c2773SMohan Kumar iommus = <&smmu_niso0 TEGRA234_SID_HDA>; 993621e12a1SMohan Kumar status = "disabled"; 994621e12a1SMohan Kumar }; 995621e12a1SMohan Kumar 9966e505dd6SWayne Chang xusb_padctl: padctl@3520000 { 9976e505dd6SWayne Chang compatible = "nvidia,tegra234-xusb-padctl"; 9986e505dd6SWayne Chang reg = <0x0 0x03520000 0x0 0x20000>, 9996e505dd6SWayne Chang <0x0 0x03540000 0x0 0x10000>; 10006e505dd6SWayne Chang reg-names = "padctl", "ao"; 10016e505dd6SWayne Chang interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 10026e505dd6SWayne Chang 10036e505dd6SWayne Chang resets = <&bpmp TEGRA234_RESET_XUSB_PADCTL>; 10046e505dd6SWayne Chang reset-names = "padctl"; 10056e505dd6SWayne Chang 10066e505dd6SWayne Chang status = "disabled"; 10076e505dd6SWayne Chang 10086e505dd6SWayne Chang pads { 10096e505dd6SWayne Chang usb2 { 10106e505dd6SWayne Chang clocks = <&bpmp TEGRA234_CLK_USB2_TRK>; 10116e505dd6SWayne Chang clock-names = "trk"; 10126e505dd6SWayne Chang 10136e505dd6SWayne Chang lanes { 10146e505dd6SWayne Chang usb2-0 { 10156e505dd6SWayne Chang nvidia,function = "xusb"; 10166e505dd6SWayne Chang status = "disabled"; 10176e505dd6SWayne Chang #phy-cells = <0>; 10186e505dd6SWayne Chang }; 10196e505dd6SWayne Chang 10206e505dd6SWayne Chang usb2-1 { 10216e505dd6SWayne Chang nvidia,function = "xusb"; 10226e505dd6SWayne Chang status = "disabled"; 10236e505dd6SWayne Chang #phy-cells = <0>; 10246e505dd6SWayne Chang }; 10256e505dd6SWayne Chang 10266e505dd6SWayne Chang usb2-2 { 10276e505dd6SWayne Chang nvidia,function = "xusb"; 10286e505dd6SWayne Chang status = "disabled"; 10296e505dd6SWayne Chang #phy-cells = <0>; 10306e505dd6SWayne Chang }; 10316e505dd6SWayne Chang 10326e505dd6SWayne Chang usb2-3 { 10336e505dd6SWayne Chang nvidia,function = "xusb"; 10346e505dd6SWayne Chang status = "disabled"; 10356e505dd6SWayne Chang #phy-cells = <0>; 10366e505dd6SWayne Chang }; 10376e505dd6SWayne Chang }; 10386e505dd6SWayne Chang }; 10396e505dd6SWayne Chang 10406e505dd6SWayne Chang usb3 { 10416e505dd6SWayne Chang lanes { 10426e505dd6SWayne Chang usb3-0 { 10436e505dd6SWayne Chang nvidia,function = "xusb"; 10446e505dd6SWayne Chang status = "disabled"; 10456e505dd6SWayne Chang #phy-cells = <0>; 10466e505dd6SWayne Chang }; 10476e505dd6SWayne Chang 10486e505dd6SWayne Chang usb3-1 { 10496e505dd6SWayne Chang nvidia,function = "xusb"; 10506e505dd6SWayne Chang status = "disabled"; 10516e505dd6SWayne Chang #phy-cells = <0>; 10526e505dd6SWayne Chang }; 10536e505dd6SWayne Chang 10546e505dd6SWayne Chang usb3-2 { 10556e505dd6SWayne Chang nvidia,function = "xusb"; 10566e505dd6SWayne Chang status = "disabled"; 10576e505dd6SWayne Chang #phy-cells = <0>; 10586e505dd6SWayne Chang }; 10596e505dd6SWayne Chang 10606e505dd6SWayne Chang usb3-3 { 10616e505dd6SWayne Chang nvidia,function = "xusb"; 10626e505dd6SWayne Chang status = "disabled"; 10636e505dd6SWayne Chang #phy-cells = <0>; 10646e505dd6SWayne Chang }; 10656e505dd6SWayne Chang }; 10666e505dd6SWayne Chang }; 10676e505dd6SWayne Chang }; 10686e505dd6SWayne Chang 10696e505dd6SWayne Chang ports { 10706e505dd6SWayne Chang usb2-0 { 10716e505dd6SWayne Chang status = "disabled"; 10726e505dd6SWayne Chang }; 10736e505dd6SWayne Chang 10746e505dd6SWayne Chang usb2-1 { 10756e505dd6SWayne Chang status = "disabled"; 10766e505dd6SWayne Chang }; 10776e505dd6SWayne Chang 10786e505dd6SWayne Chang usb2-2 { 10796e505dd6SWayne Chang status = "disabled"; 10806e505dd6SWayne Chang }; 10816e505dd6SWayne Chang 10826e505dd6SWayne Chang usb2-3 { 10836e505dd6SWayne Chang status = "disabled"; 10846e505dd6SWayne Chang }; 10856e505dd6SWayne Chang 10866e505dd6SWayne Chang usb3-0 { 10876e505dd6SWayne Chang status = "disabled"; 10886e505dd6SWayne Chang }; 10896e505dd6SWayne Chang 10906e505dd6SWayne Chang usb3-1 { 10916e505dd6SWayne Chang status = "disabled"; 10926e505dd6SWayne Chang }; 10936e505dd6SWayne Chang 10946e505dd6SWayne Chang usb3-2 { 10956e505dd6SWayne Chang status = "disabled"; 10966e505dd6SWayne Chang }; 10976e505dd6SWayne Chang 10986e505dd6SWayne Chang usb3-3 { 10996e505dd6SWayne Chang status = "disabled"; 11006e505dd6SWayne Chang }; 11016e505dd6SWayne Chang }; 11026e505dd6SWayne Chang }; 11036e505dd6SWayne Chang 1104320e0a70SJon Hunter usb@3550000 { 1105320e0a70SJon Hunter compatible = "nvidia,tegra234-xudc"; 1106320e0a70SJon Hunter reg = <0x0 0x03550000 0x0 0x8000>, 1107320e0a70SJon Hunter <0x0 0x03558000 0x0 0x8000>; 1108320e0a70SJon Hunter reg-names = "base", "fpci"; 1109320e0a70SJon Hunter interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1110320e0a70SJon Hunter clocks = <&bpmp TEGRA234_CLK_XUSB_CORE_DEV>, 1111320e0a70SJon Hunter <&bpmp TEGRA234_CLK_XUSB_CORE_SS>, 1112320e0a70SJon Hunter <&bpmp TEGRA234_CLK_XUSB_SS>, 1113320e0a70SJon Hunter <&bpmp TEGRA234_CLK_XUSB_FS>; 1114320e0a70SJon Hunter clock-names = "dev", "ss", "ss_src", "fs_src"; 1115320e0a70SJon Hunter interconnects = <&mc TEGRA234_MEMORY_CLIENT_XUSB_DEVR &emc>, 1116320e0a70SJon Hunter <&mc TEGRA234_MEMORY_CLIENT_XUSB_DEVW &emc>; 1117320e0a70SJon Hunter interconnect-names = "dma-mem", "write"; 1118320e0a70SJon Hunter iommus = <&smmu_niso1 TEGRA234_SID_XUSB_DEV>; 1119320e0a70SJon Hunter power-domains = <&bpmp TEGRA234_POWER_DOMAIN_XUSBB>, 1120320e0a70SJon Hunter <&bpmp TEGRA234_POWER_DOMAIN_XUSBA>; 1121320e0a70SJon Hunter power-domain-names = "dev", "ss"; 1122320e0a70SJon Hunter nvidia,xusb-padctl = <&xusb_padctl>; 1123320e0a70SJon Hunter dma-coherent; 1124320e0a70SJon Hunter status = "disabled"; 1125320e0a70SJon Hunter }; 1126320e0a70SJon Hunter 11276e505dd6SWayne Chang usb@3610000 { 11286e505dd6SWayne Chang compatible = "nvidia,tegra234-xusb"; 11296e505dd6SWayne Chang reg = <0x0 0x03610000 0x0 0x40000>, 11306e505dd6SWayne Chang <0x0 0x03600000 0x0 0x10000>, 11316e505dd6SWayne Chang <0x0 0x03650000 0x0 0x10000>; 11326e505dd6SWayne Chang reg-names = "hcd", "fpci", "bar2"; 11336e505dd6SWayne Chang 11346e505dd6SWayne Chang interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 11356e505dd6SWayne Chang <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 11366e505dd6SWayne Chang 11376e505dd6SWayne Chang clocks = <&bpmp TEGRA234_CLK_XUSB_CORE_HOST>, 11386e505dd6SWayne Chang <&bpmp TEGRA234_CLK_XUSB_FALCON>, 11396e505dd6SWayne Chang <&bpmp TEGRA234_CLK_XUSB_CORE_SS>, 11406e505dd6SWayne Chang <&bpmp TEGRA234_CLK_XUSB_SS>, 11416e505dd6SWayne Chang <&bpmp TEGRA234_CLK_CLK_M>, 11426e505dd6SWayne Chang <&bpmp TEGRA234_CLK_XUSB_FS>, 11436e505dd6SWayne Chang <&bpmp TEGRA234_CLK_UTMIP_PLL>, 11446e505dd6SWayne Chang <&bpmp TEGRA234_CLK_CLK_M>, 11456e505dd6SWayne Chang <&bpmp TEGRA234_CLK_PLLE>; 11466e505dd6SWayne Chang clock-names = "xusb_host", "xusb_falcon_src", 11476e505dd6SWayne Chang "xusb_ss", "xusb_ss_src", "xusb_hs_src", 11486e505dd6SWayne Chang "xusb_fs_src", "pll_u_480m", "clk_m", 11496e505dd6SWayne Chang "pll_e"; 11506e505dd6SWayne Chang interconnects = <&mc TEGRA234_MEMORY_CLIENT_XUSB_HOSTR &emc>, 11516e505dd6SWayne Chang <&mc TEGRA234_MEMORY_CLIENT_XUSB_HOSTW &emc>; 11526e505dd6SWayne Chang interconnect-names = "dma-mem", "write"; 11536e505dd6SWayne Chang iommus = <&smmu_niso1 TEGRA234_SID_XUSB_HOST>; 11546e505dd6SWayne Chang 11556e505dd6SWayne Chang power-domains = <&bpmp TEGRA234_POWER_DOMAIN_XUSBC>, 11566e505dd6SWayne Chang <&bpmp TEGRA234_POWER_DOMAIN_XUSBA>; 11576e505dd6SWayne Chang power-domain-names = "xusb_host", "xusb_ss"; 11586e505dd6SWayne Chang 11596e505dd6SWayne Chang nvidia,xusb-padctl = <&xusb_padctl>; 11606e505dd6SWayne Chang dma-coherent; 11616e505dd6SWayne Chang status = "disabled"; 11626e505dd6SWayne Chang }; 11636e505dd6SWayne Chang 116463944891SThierry Reding fuse@3810000 { 116563944891SThierry Reding compatible = "nvidia,tegra234-efuse"; 11662838cfddSThierry Reding reg = <0x0 0x03810000 0x0 0x10000>; 116763944891SThierry Reding clocks = <&bpmp TEGRA234_CLK_FUSE>; 116863944891SThierry Reding clock-names = "fuse"; 116963944891SThierry Reding }; 117063944891SThierry Reding 117163944891SThierry Reding hsp_top0: hsp@3c00000 { 117263944891SThierry Reding compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; 11732838cfddSThierry Reding reg = <0x0 0x03c00000 0x0 0xa0000>; 117463944891SThierry Reding interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 117563944891SThierry Reding <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 117663944891SThierry Reding <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 117763944891SThierry Reding <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 117863944891SThierry Reding <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 117963944891SThierry Reding <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 118063944891SThierry Reding <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 118163944891SThierry Reding <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 118263944891SThierry Reding <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 118363944891SThierry Reding interrupt-names = "doorbell", "shared0", "shared1", "shared2", 118463944891SThierry Reding "shared3", "shared4", "shared5", "shared6", 118563944891SThierry Reding "shared7"; 118663944891SThierry Reding #mbox-cells = <2>; 118763944891SThierry Reding }; 118863944891SThierry Reding 118978159542SThierry Reding p2u_hsio_0: phy@3e00000 { 119078159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 11912838cfddSThierry Reding reg = <0x0 0x03e00000 0x0 0x10000>; 119278159542SThierry Reding reg-names = "ctl"; 119378159542SThierry Reding 119478159542SThierry Reding #phy-cells = <0>; 119578159542SThierry Reding }; 119678159542SThierry Reding 119778159542SThierry Reding p2u_hsio_1: phy@3e10000 { 119878159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 11992838cfddSThierry Reding reg = <0x0 0x03e10000 0x0 0x10000>; 120078159542SThierry Reding reg-names = "ctl"; 120178159542SThierry Reding 120278159542SThierry Reding #phy-cells = <0>; 120378159542SThierry Reding }; 120478159542SThierry Reding 120578159542SThierry Reding p2u_hsio_2: phy@3e20000 { 120678159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 12072838cfddSThierry Reding reg = <0x0 0x03e20000 0x0 0x10000>; 120878159542SThierry Reding reg-names = "ctl"; 120978159542SThierry Reding 121078159542SThierry Reding #phy-cells = <0>; 121178159542SThierry Reding }; 121278159542SThierry Reding 121378159542SThierry Reding p2u_hsio_3: phy@3e30000 { 121478159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 12152838cfddSThierry Reding reg = <0x0 0x03e30000 0x0 0x10000>; 121678159542SThierry Reding reg-names = "ctl"; 121778159542SThierry Reding 121878159542SThierry Reding #phy-cells = <0>; 121978159542SThierry Reding }; 122078159542SThierry Reding 122178159542SThierry Reding p2u_hsio_4: phy@3e40000 { 122278159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 12232838cfddSThierry Reding reg = <0x0 0x03e40000 0x0 0x10000>; 122478159542SThierry Reding reg-names = "ctl"; 122578159542SThierry Reding 122678159542SThierry Reding #phy-cells = <0>; 122778159542SThierry Reding }; 122878159542SThierry Reding 122978159542SThierry Reding p2u_hsio_5: phy@3e50000 { 123078159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 12312838cfddSThierry Reding reg = <0x0 0x03e50000 0x0 0x10000>; 123278159542SThierry Reding reg-names = "ctl"; 123378159542SThierry Reding 123478159542SThierry Reding #phy-cells = <0>; 123578159542SThierry Reding }; 123678159542SThierry Reding 123778159542SThierry Reding p2u_hsio_6: phy@3e60000 { 123878159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 12392838cfddSThierry Reding reg = <0x0 0x03e60000 0x0 0x10000>; 124078159542SThierry Reding reg-names = "ctl"; 124178159542SThierry Reding 124278159542SThierry Reding #phy-cells = <0>; 124378159542SThierry Reding }; 124478159542SThierry Reding 124578159542SThierry Reding p2u_hsio_7: phy@3e70000 { 124678159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 12472838cfddSThierry Reding reg = <0x0 0x03e70000 0x0 0x10000>; 124878159542SThierry Reding reg-names = "ctl"; 124978159542SThierry Reding 125078159542SThierry Reding #phy-cells = <0>; 125178159542SThierry Reding }; 125278159542SThierry Reding 125378159542SThierry Reding p2u_nvhs_0: phy@3e90000 { 125478159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 12552838cfddSThierry Reding reg = <0x0 0x03e90000 0x0 0x10000>; 125678159542SThierry Reding reg-names = "ctl"; 125778159542SThierry Reding 125878159542SThierry Reding #phy-cells = <0>; 125978159542SThierry Reding }; 126078159542SThierry Reding 126178159542SThierry Reding p2u_nvhs_1: phy@3ea0000 { 126278159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 12632838cfddSThierry Reding reg = <0x0 0x03ea0000 0x0 0x10000>; 126478159542SThierry Reding reg-names = "ctl"; 126578159542SThierry Reding 126678159542SThierry Reding #phy-cells = <0>; 126778159542SThierry Reding }; 126878159542SThierry Reding 126978159542SThierry Reding p2u_nvhs_2: phy@3eb0000 { 127078159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 12712838cfddSThierry Reding reg = <0x0 0x03eb0000 0x0 0x10000>; 127278159542SThierry Reding reg-names = "ctl"; 127378159542SThierry Reding 127478159542SThierry Reding #phy-cells = <0>; 127578159542SThierry Reding }; 127678159542SThierry Reding 127778159542SThierry Reding p2u_nvhs_3: phy@3ec0000 { 127878159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 12792838cfddSThierry Reding reg = <0x0 0x03ec0000 0x0 0x10000>; 128078159542SThierry Reding reg-names = "ctl"; 128178159542SThierry Reding 128278159542SThierry Reding #phy-cells = <0>; 128378159542SThierry Reding }; 128478159542SThierry Reding 128578159542SThierry Reding p2u_nvhs_4: phy@3ed0000 { 128678159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 12872838cfddSThierry Reding reg = <0x0 0x03ed0000 0x0 0x10000>; 128878159542SThierry Reding reg-names = "ctl"; 128978159542SThierry Reding 129078159542SThierry Reding #phy-cells = <0>; 129178159542SThierry Reding }; 129278159542SThierry Reding 129378159542SThierry Reding p2u_nvhs_5: phy@3ee0000 { 129478159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 12952838cfddSThierry Reding reg = <0x0 0x03ee0000 0x0 0x10000>; 129678159542SThierry Reding reg-names = "ctl"; 129778159542SThierry Reding 129878159542SThierry Reding #phy-cells = <0>; 129978159542SThierry Reding }; 130078159542SThierry Reding 130178159542SThierry Reding p2u_nvhs_6: phy@3ef0000 { 130278159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 13032838cfddSThierry Reding reg = <0x0 0x03ef0000 0x0 0x10000>; 130478159542SThierry Reding reg-names = "ctl"; 130578159542SThierry Reding 130678159542SThierry Reding #phy-cells = <0>; 130778159542SThierry Reding }; 130878159542SThierry Reding 130978159542SThierry Reding p2u_nvhs_7: phy@3f00000 { 131078159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 13112838cfddSThierry Reding reg = <0x0 0x03f00000 0x0 0x10000>; 131278159542SThierry Reding reg-names = "ctl"; 131378159542SThierry Reding 131478159542SThierry Reding #phy-cells = <0>; 131578159542SThierry Reding }; 131678159542SThierry Reding 131778159542SThierry Reding p2u_gbe_0: phy@3f20000 { 131878159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 13192838cfddSThierry Reding reg = <0x0 0x03f20000 0x0 0x10000>; 132078159542SThierry Reding reg-names = "ctl"; 132178159542SThierry Reding 132278159542SThierry Reding #phy-cells = <0>; 132378159542SThierry Reding }; 132478159542SThierry Reding 132578159542SThierry Reding p2u_gbe_1: phy@3f30000 { 132678159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 13272838cfddSThierry Reding reg = <0x0 0x03f30000 0x0 0x10000>; 132878159542SThierry Reding reg-names = "ctl"; 132978159542SThierry Reding 133078159542SThierry Reding #phy-cells = <0>; 133178159542SThierry Reding }; 133278159542SThierry Reding 133378159542SThierry Reding p2u_gbe_2: phy@3f40000 { 133478159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 13352838cfddSThierry Reding reg = <0x0 0x03f40000 0x0 0x10000>; 133678159542SThierry Reding reg-names = "ctl"; 133778159542SThierry Reding 133878159542SThierry Reding #phy-cells = <0>; 133978159542SThierry Reding }; 134078159542SThierry Reding 134178159542SThierry Reding p2u_gbe_3: phy@3f50000 { 134278159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 13432838cfddSThierry Reding reg = <0x0 0x03f50000 0x0 0x10000>; 134478159542SThierry Reding reg-names = "ctl"; 134578159542SThierry Reding 134678159542SThierry Reding #phy-cells = <0>; 134778159542SThierry Reding }; 134878159542SThierry Reding 134978159542SThierry Reding p2u_gbe_4: phy@3f60000 { 135078159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 13512838cfddSThierry Reding reg = <0x0 0x03f60000 0x0 0x10000>; 135278159542SThierry Reding reg-names = "ctl"; 135378159542SThierry Reding 135478159542SThierry Reding #phy-cells = <0>; 135578159542SThierry Reding }; 135678159542SThierry Reding 135778159542SThierry Reding p2u_gbe_5: phy@3f70000 { 135878159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 13592838cfddSThierry Reding reg = <0x0 0x03f70000 0x0 0x10000>; 136078159542SThierry Reding reg-names = "ctl"; 136178159542SThierry Reding 136278159542SThierry Reding #phy-cells = <0>; 136378159542SThierry Reding }; 136478159542SThierry Reding 136578159542SThierry Reding p2u_gbe_6: phy@3f80000 { 136678159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 13672838cfddSThierry Reding reg = <0x0 0x03f80000 0x0 0x10000>; 136878159542SThierry Reding reg-names = "ctl"; 136978159542SThierry Reding 137078159542SThierry Reding #phy-cells = <0>; 137178159542SThierry Reding }; 137278159542SThierry Reding 137378159542SThierry Reding p2u_gbe_7: phy@3f90000 { 137478159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 13752838cfddSThierry Reding reg = <0x0 0x03f90000 0x0 0x10000>; 137678159542SThierry Reding reg-names = "ctl"; 137778159542SThierry Reding 137878159542SThierry Reding #phy-cells = <0>; 137978159542SThierry Reding }; 138078159542SThierry Reding 1381610cdf31SThierry Reding ethernet@6800000 { 1382610cdf31SThierry Reding compatible = "nvidia,tegra234-mgbe"; 13832838cfddSThierry Reding reg = <0x0 0x06800000 0x0 0x10000>, 13842838cfddSThierry Reding <0x0 0x06810000 0x0 0x10000>, 13852838cfddSThierry Reding <0x0 0x068a0000 0x0 0x10000>; 1386610cdf31SThierry Reding reg-names = "hypervisor", "mac", "xpcs"; 1387610cdf31SThierry Reding interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>; 1388610cdf31SThierry Reding interrupt-names = "common"; 1389610cdf31SThierry Reding clocks = <&bpmp TEGRA234_CLK_MGBE0_APP>, 1390610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE0_MAC>, 1391610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE0_MAC_DIVIDER>, 1392610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE0_PTP_REF>, 1393610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT_M>, 1394610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT>, 1395610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE0_TX>, 1396610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE0_EEE_PCS>, 1397610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_INPUT>, 1398610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_M>, 1399610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE0_RX_PCS>, 1400610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE0_TX_PCS>; 1401610cdf31SThierry Reding clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", 1402610cdf31SThierry Reding "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", 1403610cdf31SThierry Reding "rx-pcs", "tx-pcs"; 1404610cdf31SThierry Reding resets = <&bpmp TEGRA234_RESET_MGBE0_MAC>, 1405610cdf31SThierry Reding <&bpmp TEGRA234_RESET_MGBE0_PCS>; 1406610cdf31SThierry Reding reset-names = "mac", "pcs"; 1407610cdf31SThierry Reding interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEARD &emc>, 1408610cdf31SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_MGBEAWR &emc>; 1409610cdf31SThierry Reding interconnect-names = "dma-mem", "write"; 1410610cdf31SThierry Reding iommus = <&smmu_niso0 TEGRA234_SID_MGBE>; 1411610cdf31SThierry Reding power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEA>; 1412610cdf31SThierry Reding status = "disabled"; 1413610cdf31SThierry Reding }; 1414610cdf31SThierry Reding 1415610cdf31SThierry Reding ethernet@6900000 { 1416610cdf31SThierry Reding compatible = "nvidia,tegra234-mgbe"; 14172838cfddSThierry Reding reg = <0x0 0x06900000 0x0 0x10000>, 14182838cfddSThierry Reding <0x0 0x06910000 0x0 0x10000>, 14192838cfddSThierry Reding <0x0 0x069a0000 0x0 0x10000>; 1420610cdf31SThierry Reding reg-names = "hypervisor", "mac", "xpcs"; 1421610cdf31SThierry Reding interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>; 1422610cdf31SThierry Reding interrupt-names = "common"; 1423610cdf31SThierry Reding clocks = <&bpmp TEGRA234_CLK_MGBE1_APP>, 1424610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE1_MAC>, 1425610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE1_MAC_DIVIDER>, 1426610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE1_PTP_REF>, 1427610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE1_RX_INPUT_M>, 1428610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE1_RX_INPUT>, 1429610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE1_TX>, 1430610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE1_EEE_PCS>, 1431610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE1_RX_PCS_INPUT>, 1432610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE1_RX_PCS_M>, 1433610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE1_RX_PCS>, 1434610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE1_TX_PCS>; 1435610cdf31SThierry Reding clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", 1436610cdf31SThierry Reding "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", 1437610cdf31SThierry Reding "rx-pcs", "tx-pcs"; 1438610cdf31SThierry Reding resets = <&bpmp TEGRA234_RESET_MGBE1_MAC>, 1439610cdf31SThierry Reding <&bpmp TEGRA234_RESET_MGBE1_PCS>; 1440610cdf31SThierry Reding reset-names = "mac", "pcs"; 1441610cdf31SThierry Reding interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEBRD &emc>, 1442610cdf31SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_MGBEBWR &emc>; 1443610cdf31SThierry Reding interconnect-names = "dma-mem", "write"; 1444610cdf31SThierry Reding iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF1>; 1445610cdf31SThierry Reding power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEB>; 1446610cdf31SThierry Reding status = "disabled"; 1447610cdf31SThierry Reding }; 1448610cdf31SThierry Reding 1449610cdf31SThierry Reding ethernet@6a00000 { 1450610cdf31SThierry Reding compatible = "nvidia,tegra234-mgbe"; 14512838cfddSThierry Reding reg = <0x0 0x06a00000 0x0 0x10000>, 14522838cfddSThierry Reding <0x0 0x06a10000 0x0 0x10000>, 14532838cfddSThierry Reding <0x0 0x06aa0000 0x0 0x10000>; 1454610cdf31SThierry Reding reg-names = "hypervisor", "mac", "xpcs"; 1455610cdf31SThierry Reding interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>; 1456610cdf31SThierry Reding interrupt-names = "common"; 1457610cdf31SThierry Reding clocks = <&bpmp TEGRA234_CLK_MGBE2_APP>, 1458610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE2_MAC>, 1459610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE2_MAC_DIVIDER>, 1460610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE2_PTP_REF>, 1461610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE2_RX_INPUT_M>, 1462610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE2_RX_INPUT>, 1463610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE2_TX>, 1464610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE2_EEE_PCS>, 1465610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE2_RX_PCS_INPUT>, 1466610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE2_RX_PCS_M>, 1467610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE2_RX_PCS>, 1468610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE2_TX_PCS>; 1469610cdf31SThierry Reding clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", 1470610cdf31SThierry Reding "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", 1471610cdf31SThierry Reding "rx-pcs", "tx-pcs"; 1472610cdf31SThierry Reding resets = <&bpmp TEGRA234_RESET_MGBE2_MAC>, 1473610cdf31SThierry Reding <&bpmp TEGRA234_RESET_MGBE2_PCS>; 1474610cdf31SThierry Reding reset-names = "mac", "pcs"; 1475610cdf31SThierry Reding interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBECRD &emc>, 1476610cdf31SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_MGBECWR &emc>; 1477610cdf31SThierry Reding interconnect-names = "dma-mem", "write"; 1478610cdf31SThierry Reding iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF2>; 1479610cdf31SThierry Reding power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEC>; 1480610cdf31SThierry Reding status = "disabled"; 1481610cdf31SThierry Reding }; 1482610cdf31SThierry Reding 1483610cdf31SThierry Reding ethernet@6b00000 { 1484610cdf31SThierry Reding compatible = "nvidia,tegra234-mgbe"; 14852838cfddSThierry Reding reg = <0x0 0x06b00000 0x0 0x10000>, 14862838cfddSThierry Reding <0x0 0x06b10000 0x0 0x10000>, 14872838cfddSThierry Reding <0x0 0x06ba0000 0x0 0x10000>; 1488610cdf31SThierry Reding reg-names = "hypervisor", "mac", "xpcs"; 1489610cdf31SThierry Reding interrupts = <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 1490610cdf31SThierry Reding interrupt-names = "common"; 1491610cdf31SThierry Reding clocks = <&bpmp TEGRA234_CLK_MGBE3_APP>, 1492610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE3_MAC>, 1493610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE3_MAC_DIVIDER>, 1494610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE3_PTP_REF>, 1495610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE3_RX_INPUT_M>, 1496610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE3_RX_INPUT>, 1497610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE3_TX>, 1498610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE3_EEE_PCS>, 1499610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE3_RX_PCS_INPUT>, 1500610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE3_RX_PCS_M>, 1501610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE3_RX_PCS>, 1502610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE3_TX_PCS>; 1503610cdf31SThierry Reding clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", 1504610cdf31SThierry Reding "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", 1505610cdf31SThierry Reding "rx-pcs", "tx-pcs"; 1506610cdf31SThierry Reding resets = <&bpmp TEGRA234_RESET_MGBE3_MAC>, 1507610cdf31SThierry Reding <&bpmp TEGRA234_RESET_MGBE3_PCS>; 1508610cdf31SThierry Reding reset-names = "mac", "pcs"; 1509610cdf31SThierry Reding interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEDRD &emc>, 1510610cdf31SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_MGBEDWR &emc>; 1511610cdf31SThierry Reding interconnect-names = "dma-mem", "write"; 1512610cdf31SThierry Reding iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF3>; 1513610cdf31SThierry Reding power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBED>; 1514610cdf31SThierry Reding status = "disabled"; 1515610cdf31SThierry Reding }; 1516610cdf31SThierry Reding 15175710e16aSThierry Reding smmu_niso1: iommu@8000000 { 15185710e16aSThierry Reding compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; 15192838cfddSThierry Reding reg = <0x0 0x8000000 0x0 0x1000000>, 15202838cfddSThierry Reding <0x0 0x7000000 0x0 0x1000000>; 15215710e16aSThierry Reding interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15225710e16aSThierry Reding <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, 15235710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15245710e16aSThierry Reding <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, 15255710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15265710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15275710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15285710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15295710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15305710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15315710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15325710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15335710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15345710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15355710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15365710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15375710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15385710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15395710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15405710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15415710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15425710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15435710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15445710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15455710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15465710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15475710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15485710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15495710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15505710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15515710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15525710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15535710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15545710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15555710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15565710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15575710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15585710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15595710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15605710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15615710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15625710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15635710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15645710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15655710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15665710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15675710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15685710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15695710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15705710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15715710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15725710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15735710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15745710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15755710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15765710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15775710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15785710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15795710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15805710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15815710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15825710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15835710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15845710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15855710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15865710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15875710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15885710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15895710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15905710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15915710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15925710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15935710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15945710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15955710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15965710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15975710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15985710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15995710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16005710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16015710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16025710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16035710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16045710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16055710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16065710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16075710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16085710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16095710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16105710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16115710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16125710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16135710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16145710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16155710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16165710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16175710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16185710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16195710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16205710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16215710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16225710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16235710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16245710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16255710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16265710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16275710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16285710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16295710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16305710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16315710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16325710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16335710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16345710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16355710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16365710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16375710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16385710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16395710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16405710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16415710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16425710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16435710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16445710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16455710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16465710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16475710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16485710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16495710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16505710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 16515710e16aSThierry Reding stream-match-mask = <0x7f80>; 16525710e16aSThierry Reding #global-interrupts = <2>; 16535710e16aSThierry Reding #iommu-cells = <1>; 16545710e16aSThierry Reding 16555710e16aSThierry Reding nvidia,memory-controller = <&mc>; 16565710e16aSThierry Reding status = "okay"; 16575710e16aSThierry Reding }; 16585710e16aSThierry Reding 1659302e1540SSumit Gupta sce-fabric@b600000 { 1660302e1540SSumit Gupta compatible = "nvidia,tegra234-sce-fabric"; 16612838cfddSThierry Reding reg = <0x0 0xb600000 0x0 0x40000>; 1662302e1540SSumit Gupta interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 1663302e1540SSumit Gupta status = "okay"; 1664302e1540SSumit Gupta }; 1665302e1540SSumit Gupta 1666302e1540SSumit Gupta rce-fabric@be00000 { 1667302e1540SSumit Gupta compatible = "nvidia,tegra234-rce-fabric"; 16682838cfddSThierry Reding reg = <0x0 0xbe00000 0x0 0x40000>; 1669302e1540SSumit Gupta interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 1670302e1540SSumit Gupta status = "okay"; 1671302e1540SSumit Gupta }; 1672302e1540SSumit Gupta 167363944891SThierry Reding hsp_aon: hsp@c150000 { 167463944891SThierry Reding compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; 16752838cfddSThierry Reding reg = <0x0 0x0c150000 0x0 0x90000>; 167663944891SThierry Reding interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 167763944891SThierry Reding <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 167863944891SThierry Reding <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 167963944891SThierry Reding <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 168063944891SThierry Reding /* 168163944891SThierry Reding * Shared interrupt 0 is routed only to AON/SPE, so 168263944891SThierry Reding * we only have 4 shared interrupts for the CCPLEX. 168363944891SThierry Reding */ 168463944891SThierry Reding interrupt-names = "shared1", "shared2", "shared3", "shared4"; 168563944891SThierry Reding #mbox-cells = <2>; 168663944891SThierry Reding }; 168763944891SThierry Reding 1688156af9deSAkhil R gen2_i2c: i2c@c240000 { 1689156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 16902838cfddSThierry Reding reg = <0x0 0xc240000 0x0 0x100>; 1691156af9deSAkhil R interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1692260e8d42SJon Hunter #address-cells = <1>; 1693260e8d42SJon Hunter #size-cells = <0>; 1694156af9deSAkhil R status = "disabled"; 1695156af9deSAkhil R clock-frequency = <100000>; 1696156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C2 1697156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 1698156af9deSAkhil R clock-names = "div-clk", "parent"; 1699156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C2>; 1700156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 1701156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C2>; 1702156af9deSAkhil R reset-names = "i2c"; 17038e442805SAkhil R iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 17048e442805SAkhil R dma-coherent; 17058e442805SAkhil R dmas = <&gpcdma 22>, <&gpcdma 22>; 17068e442805SAkhil R dma-names = "rx", "tx"; 1707156af9deSAkhil R }; 1708156af9deSAkhil R 1709156af9deSAkhil R gen8_i2c: i2c@c250000 { 1710156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 17112838cfddSThierry Reding reg = <0x0 0xc250000 0x0 0x100>; 1712156af9deSAkhil R interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1713260e8d42SJon Hunter #address-cells = <1>; 1714260e8d42SJon Hunter #size-cells = <0>; 1715156af9deSAkhil R status = "disabled"; 1716156af9deSAkhil R clock-frequency = <400000>; 1717156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C8 1718156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 1719156af9deSAkhil R clock-names = "div-clk", "parent"; 1720156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C8>; 1721156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 1722156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C8>; 1723156af9deSAkhil R reset-names = "i2c"; 17248e442805SAkhil R iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 17258e442805SAkhil R dma-coherent; 17268e442805SAkhil R dmas = <&gpcdma 0>, <&gpcdma 0>; 17278e442805SAkhil R dma-names = "rx", "tx"; 1728156af9deSAkhil R }; 1729156af9deSAkhil R 173063944891SThierry Reding rtc@c2a0000 { 173163944891SThierry Reding compatible = "nvidia,tegra234-rtc", "nvidia,tegra20-rtc"; 17322838cfddSThierry Reding reg = <0x0 0x0c2a0000 0x0 0x10000>; 173363944891SThierry Reding interrupt-parent = <&pmc>; 173463944891SThierry Reding interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 1735e537addeSMikko Perttunen clocks = <&bpmp TEGRA234_CLK_CLK_32K>; 1736e537addeSMikko Perttunen clock-names = "rtc"; 173763944891SThierry Reding status = "disabled"; 173863944891SThierry Reding }; 173963944891SThierry Reding 1740f0e12668SThierry Reding gpio_aon: gpio@c2f0000 { 1741f0e12668SThierry Reding compatible = "nvidia,tegra234-gpio-aon"; 1742f0e12668SThierry Reding reg-names = "security", "gpio"; 17432838cfddSThierry Reding reg = <0x0 0x0c2f0000 0x0 0x1000>, 17442838cfddSThierry Reding <0x0 0x0c2f1000 0x0 0x1000>; 1745f0e12668SThierry Reding interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1746f0e12668SThierry Reding <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1747f0e12668SThierry Reding <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1748f0e12668SThierry Reding <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 1749f0e12668SThierry Reding #interrupt-cells = <2>; 1750f0e12668SThierry Reding interrupt-controller; 1751f0e12668SThierry Reding #gpio-cells = <2>; 1752f0e12668SThierry Reding gpio-controller; 1753f0e12668SThierry Reding }; 1754f0e12668SThierry Reding 17552566d28cSJon Hunter pwm4: pwm@c340000 { 17562566d28cSJon Hunter compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 17572838cfddSThierry Reding reg = <0x0 0xc340000 0x0 0x10000>; 17582566d28cSJon Hunter clocks = <&bpmp TEGRA234_CLK_PWM4>; 17592566d28cSJon Hunter resets = <&bpmp TEGRA234_RESET_PWM4>; 17602566d28cSJon Hunter reset-names = "pwm"; 17612566d28cSJon Hunter status = "disabled"; 17622566d28cSJon Hunter #pwm-cells = <2>; 17632566d28cSJon Hunter }; 17642566d28cSJon Hunter 176563944891SThierry Reding pmc: pmc@c360000 { 176663944891SThierry Reding compatible = "nvidia,tegra234-pmc"; 17672838cfddSThierry Reding reg = <0x0 0x0c360000 0x0 0x10000>, 17682838cfddSThierry Reding <0x0 0x0c370000 0x0 0x10000>, 17692838cfddSThierry Reding <0x0 0x0c380000 0x0 0x10000>, 17702838cfddSThierry Reding <0x0 0x0c390000 0x0 0x10000>, 17712838cfddSThierry Reding <0x0 0x0c3a0000 0x0 0x10000>; 177263944891SThierry Reding reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 177363944891SThierry Reding 177463944891SThierry Reding #interrupt-cells = <2>; 177563944891SThierry Reding interrupt-controller; 1776d71b893aSPrathamesh Shete 1777d71b893aSPrathamesh Shete sdmmc1_1v8: sdmmc1-1v8 { 1778d71b893aSPrathamesh Shete pins = "sdmmc1-hv"; 1779d71b893aSPrathamesh Shete power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1780d71b893aSPrathamesh Shete }; 1781d71b893aSPrathamesh Shete 178279ed18d9SThierry Reding sdmmc1_3v3: sdmmc1-3v3 { 178379ed18d9SThierry Reding pins = "sdmmc1-hv"; 1784d71b893aSPrathamesh Shete power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1785d71b893aSPrathamesh Shete }; 1786d71b893aSPrathamesh Shete 1787d71b893aSPrathamesh Shete sdmmc3_1v8: sdmmc3-1v8 { 1788d71b893aSPrathamesh Shete pins = "sdmmc3-hv"; 1789d71b893aSPrathamesh Shete power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1790d71b893aSPrathamesh Shete }; 179179ed18d9SThierry Reding 179279ed18d9SThierry Reding sdmmc3_3v3: sdmmc3-3v3 { 179379ed18d9SThierry Reding pins = "sdmmc3-hv"; 179479ed18d9SThierry Reding power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 179579ed18d9SThierry Reding }; 179663944891SThierry Reding }; 179763944891SThierry Reding 1798302e1540SSumit Gupta aon-fabric@c600000 { 1799302e1540SSumit Gupta compatible = "nvidia,tegra234-aon-fabric"; 18002838cfddSThierry Reding reg = <0x0 0xc600000 0x0 0x40000>; 1801302e1540SSumit Gupta interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 1802302e1540SSumit Gupta status = "okay"; 1803302e1540SSumit Gupta }; 1804302e1540SSumit Gupta 1805302e1540SSumit Gupta bpmp-fabric@d600000 { 1806302e1540SSumit Gupta compatible = "nvidia,tegra234-bpmp-fabric"; 18072838cfddSThierry Reding reg = <0x0 0xd600000 0x0 0x40000>; 1808302e1540SSumit Gupta interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1809302e1540SSumit Gupta status = "okay"; 1810302e1540SSumit Gupta }; 1811302e1540SSumit Gupta 1812302e1540SSumit Gupta dce-fabric@de00000 { 1813302e1540SSumit Gupta compatible = "nvidia,tegra234-sce-fabric"; 18142838cfddSThierry Reding reg = <0x0 0xde00000 0x0 0x40000>; 1815302e1540SSumit Gupta interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>; 1816302e1540SSumit Gupta status = "okay"; 1817302e1540SSumit Gupta }; 1818302e1540SSumit Gupta 18192838cfddSThierry Reding ccplex@e000000 { 18202838cfddSThierry Reding compatible = "nvidia,tegra234-ccplex-cluster"; 18212838cfddSThierry Reding reg = <0x0 0x0e000000 0x0 0x5ffff>; 18222838cfddSThierry Reding nvidia,bpmp = <&bpmp>; 18232838cfddSThierry Reding status = "okay"; 18242838cfddSThierry Reding }; 18252838cfddSThierry Reding 182663944891SThierry Reding gic: interrupt-controller@f400000 { 182763944891SThierry Reding compatible = "arm,gic-v3"; 18282838cfddSThierry Reding reg = <0x0 0x0f400000 0x0 0x010000>, /* GICD */ 18292838cfddSThierry Reding <0x0 0x0f440000 0x0 0x200000>; /* GICR */ 183063944891SThierry Reding interrupt-parent = <&gic>; 183163944891SThierry Reding interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 183263944891SThierry Reding 183363944891SThierry Reding #redistributor-regions = <1>; 183463944891SThierry Reding #interrupt-cells = <3>; 183563944891SThierry Reding interrupt-controller; 183663944891SThierry Reding }; 18375710e16aSThierry Reding 18385710e16aSThierry Reding smmu_iso: iommu@10000000 { 18395710e16aSThierry Reding compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; 18402838cfddSThierry Reding reg = <0x0 0x10000000 0x0 0x1000000>; 18415710e16aSThierry Reding interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18425710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18435710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18445710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18455710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18465710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18475710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18485710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18495710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18505710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18515710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18525710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18535710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18545710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18555710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18565710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18575710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18585710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18595710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18605710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18615710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18625710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18635710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18645710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18655710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18665710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18675710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18685710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18695710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18705710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18715710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18725710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18735710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18745710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18755710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18765710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18775710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18785710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18795710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18805710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18815710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18825710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18835710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18845710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18855710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18865710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18875710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18885710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18895710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18905710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18915710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18925710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18935710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18945710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18955710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18965710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18975710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18985710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18995710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19005710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19015710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19025710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19035710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19045710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19055710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19065710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19075710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19085710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19095710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19105710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19115710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19125710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19135710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19145710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19155710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19165710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19175710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19185710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19195710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19205710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19215710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19225710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19235710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19245710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19255710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19265710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19275710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19285710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19295710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19305710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19315710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19325710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19335710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19345710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19355710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19365710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19375710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19385710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19395710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19405710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19415710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19425710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19435710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19445710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19455710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19465710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19475710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19485710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19495710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19505710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19515710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19525710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19535710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19545710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19555710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19565710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19575710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19585710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19595710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19605710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19615710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19625710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19635710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19645710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19655710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19665710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19675710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19685710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19695710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 19705710e16aSThierry Reding stream-match-mask = <0x7f80>; 19715710e16aSThierry Reding #global-interrupts = <1>; 19725710e16aSThierry Reding #iommu-cells = <1>; 19735710e16aSThierry Reding 19745710e16aSThierry Reding nvidia,memory-controller = <&mc>; 19755710e16aSThierry Reding status = "okay"; 19765710e16aSThierry Reding }; 19775710e16aSThierry Reding 19785710e16aSThierry Reding smmu_niso0: iommu@12000000 { 19795710e16aSThierry Reding compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; 19802838cfddSThierry Reding reg = <0x0 0x12000000 0x0 0x1000000>, 19812838cfddSThierry Reding <0x0 0x11000000 0x0 0x1000000>; 19825710e16aSThierry Reding interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19835710e16aSThierry Reding <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 19845710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19855710e16aSThierry Reding <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 19865710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19875710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19885710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19895710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19905710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19915710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19925710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19935710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19945710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19955710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19965710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19975710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19985710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19995710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20005710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20015710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20025710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20035710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20045710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20055710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20065710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20075710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20085710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20095710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20105710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20115710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20125710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20135710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20145710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20155710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20165710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20175710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20185710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20195710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20205710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20215710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20225710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20235710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20245710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20255710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20265710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20275710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20285710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20295710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20305710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20315710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20325710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20335710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20345710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20355710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20365710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20375710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20385710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20395710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20405710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20415710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20425710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20435710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20445710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20455710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20465710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20475710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20485710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20495710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20505710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20515710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20525710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20535710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20545710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20555710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20565710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20575710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20585710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20595710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20605710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20615710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20625710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20635710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20645710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20655710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20665710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20675710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20685710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20695710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20705710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20715710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20725710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20735710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20745710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20755710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20765710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20775710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20785710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20795710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20805710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20815710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20825710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20835710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20845710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20855710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20865710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20875710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20885710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20895710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20905710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20915710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20925710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20935710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20945710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20955710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20965710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20975710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20985710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20995710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21005710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21015710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21025710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21035710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21045710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21055710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21065710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21075710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21085710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21095710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21105710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21115710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 21125710e16aSThierry Reding stream-match-mask = <0x7f80>; 21135710e16aSThierry Reding #global-interrupts = <2>; 21145710e16aSThierry Reding #iommu-cells = <1>; 21155710e16aSThierry Reding 21165710e16aSThierry Reding nvidia,memory-controller = <&mc>; 21175710e16aSThierry Reding status = "okay"; 21185710e16aSThierry Reding }; 2119302e1540SSumit Gupta 2120302e1540SSumit Gupta cbb-fabric@13a00000 { 2121302e1540SSumit Gupta compatible = "nvidia,tegra234-cbb-fabric"; 21222838cfddSThierry Reding reg = <0x0 0x13a00000 0x0 0x400000>; 2123302e1540SSumit Gupta interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 2124302e1540SSumit Gupta status = "okay"; 2125302e1540SSumit Gupta }; 2126962c400dSSumit Gupta 212779ed18d9SThierry Reding host1x@13e00000 { 212879ed18d9SThierry Reding compatible = "nvidia,tegra234-host1x"; 212979ed18d9SThierry Reding reg = <0x0 0x13e00000 0x0 0x10000>, 213079ed18d9SThierry Reding <0x0 0x13e10000 0x0 0x10000>, 213179ed18d9SThierry Reding <0x0 0x13e40000 0x0 0x10000>; 213279ed18d9SThierry Reding reg-names = "common", "hypervisor", "vm"; 213379ed18d9SThierry Reding interrupts = <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, 213479ed18d9SThierry Reding <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, 213579ed18d9SThierry Reding <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, 213679ed18d9SThierry Reding <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, 213779ed18d9SThierry Reding <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, 213879ed18d9SThierry Reding <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>, 213979ed18d9SThierry Reding <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>, 214079ed18d9SThierry Reding <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>, 214179ed18d9SThierry Reding <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 214279ed18d9SThierry Reding interrupt-names = "syncpt0", "syncpt1", "syncpt2", "syncpt3", "syncpt4", 214379ed18d9SThierry Reding "syncpt5", "syncpt6", "syncpt7", "host1x"; 214479ed18d9SThierry Reding clocks = <&bpmp TEGRA234_CLK_HOST1X>; 214579ed18d9SThierry Reding clock-names = "host1x"; 214679ed18d9SThierry Reding 214779ed18d9SThierry Reding #address-cells = <2>; 214879ed18d9SThierry Reding #size-cells = <2>; 214979ed18d9SThierry Reding ranges = <0x0 0x14800000 0x0 0x14800000 0x0 0x02000000>; 215079ed18d9SThierry Reding 215179ed18d9SThierry Reding interconnects = <&mc TEGRA234_MEMORY_CLIENT_HOST1XDMAR &emc>; 215279ed18d9SThierry Reding interconnect-names = "dma-mem"; 215379ed18d9SThierry Reding iommus = <&smmu_niso1 TEGRA234_SID_HOST1X>; 2154*361238cdSMikko Perttunen dma-coherent; 215579ed18d9SThierry Reding 215679ed18d9SThierry Reding /* Context isolation domains */ 215779ed18d9SThierry Reding iommu-map = <0 &smmu_niso0 TEGRA234_SID_HOST1X_CTX0 1>, 215879ed18d9SThierry Reding <1 &smmu_niso0 TEGRA234_SID_HOST1X_CTX1 1>, 215979ed18d9SThierry Reding <2 &smmu_niso0 TEGRA234_SID_HOST1X_CTX2 1>, 216079ed18d9SThierry Reding <3 &smmu_niso0 TEGRA234_SID_HOST1X_CTX3 1>, 216179ed18d9SThierry Reding <4 &smmu_niso0 TEGRA234_SID_HOST1X_CTX4 1>, 216279ed18d9SThierry Reding <5 &smmu_niso0 TEGRA234_SID_HOST1X_CTX5 1>, 216379ed18d9SThierry Reding <6 &smmu_niso0 TEGRA234_SID_HOST1X_CTX6 1>, 216479ed18d9SThierry Reding <7 &smmu_niso0 TEGRA234_SID_HOST1X_CTX7 1>, 216579ed18d9SThierry Reding <8 &smmu_niso1 TEGRA234_SID_HOST1X_CTX0 1>, 216679ed18d9SThierry Reding <9 &smmu_niso1 TEGRA234_SID_HOST1X_CTX1 1>, 216779ed18d9SThierry Reding <10 &smmu_niso1 TEGRA234_SID_HOST1X_CTX2 1>, 216879ed18d9SThierry Reding <11 &smmu_niso1 TEGRA234_SID_HOST1X_CTX3 1>, 216979ed18d9SThierry Reding <12 &smmu_niso1 TEGRA234_SID_HOST1X_CTX4 1>, 217079ed18d9SThierry Reding <13 &smmu_niso1 TEGRA234_SID_HOST1X_CTX5 1>, 217179ed18d9SThierry Reding <14 &smmu_niso1 TEGRA234_SID_HOST1X_CTX6 1>, 217279ed18d9SThierry Reding <15 &smmu_niso1 TEGRA234_SID_HOST1X_CTX7 1>; 217379ed18d9SThierry Reding 217479ed18d9SThierry Reding vic@15340000 { 217579ed18d9SThierry Reding compatible = "nvidia,tegra234-vic"; 217679ed18d9SThierry Reding reg = <0x0 0x15340000 0x0 0x00040000>; 217779ed18d9SThierry Reding interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 217879ed18d9SThierry Reding clocks = <&bpmp TEGRA234_CLK_VIC>; 217979ed18d9SThierry Reding clock-names = "vic"; 218079ed18d9SThierry Reding resets = <&bpmp TEGRA234_RESET_VIC>; 218179ed18d9SThierry Reding reset-names = "vic"; 218279ed18d9SThierry Reding 218379ed18d9SThierry Reding power-domains = <&bpmp TEGRA234_POWER_DOMAIN_VIC>; 218479ed18d9SThierry Reding interconnects = <&mc TEGRA234_MEMORY_CLIENT_VICSRD &emc>, 218579ed18d9SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_VICSWR &emc>; 218679ed18d9SThierry Reding interconnect-names = "dma-mem", "write"; 218779ed18d9SThierry Reding iommus = <&smmu_niso1 TEGRA234_SID_VIC>; 218879ed18d9SThierry Reding dma-coherent; 218979ed18d9SThierry Reding }; 219079ed18d9SThierry Reding 219179ed18d9SThierry Reding nvdec@15480000 { 219279ed18d9SThierry Reding compatible = "nvidia,tegra234-nvdec"; 219379ed18d9SThierry Reding reg = <0x0 0x15480000 0x0 0x00040000>; 219479ed18d9SThierry Reding clocks = <&bpmp TEGRA234_CLK_NVDEC>, 219579ed18d9SThierry Reding <&bpmp TEGRA234_CLK_FUSE>, 219679ed18d9SThierry Reding <&bpmp TEGRA234_CLK_TSEC_PKA>; 219779ed18d9SThierry Reding clock-names = "nvdec", "fuse", "tsec_pka"; 219879ed18d9SThierry Reding resets = <&bpmp TEGRA234_RESET_NVDEC>; 219979ed18d9SThierry Reding reset-names = "nvdec"; 220079ed18d9SThierry Reding power-domains = <&bpmp TEGRA234_POWER_DOMAIN_NVDEC>; 220179ed18d9SThierry Reding interconnects = <&mc TEGRA234_MEMORY_CLIENT_NVDECSRD &emc>, 220279ed18d9SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_NVDECSWR &emc>; 220379ed18d9SThierry Reding interconnect-names = "dma-mem", "write"; 220479ed18d9SThierry Reding iommus = <&smmu_niso1 TEGRA234_SID_NVDEC>; 220579ed18d9SThierry Reding dma-coherent; 220679ed18d9SThierry Reding 220779ed18d9SThierry Reding nvidia,memory-controller = <&mc>; 220879ed18d9SThierry Reding 220979ed18d9SThierry Reding /* 221079ed18d9SThierry Reding * Placeholder values that firmware needs to update with the real 221179ed18d9SThierry Reding * offsets parsed from the microcode headers. 221279ed18d9SThierry Reding */ 221379ed18d9SThierry Reding nvidia,bl-manifest-offset = <0>; 221479ed18d9SThierry Reding nvidia,bl-data-offset = <0>; 221579ed18d9SThierry Reding nvidia,bl-code-offset = <0>; 221679ed18d9SThierry Reding nvidia,os-manifest-offset = <0>; 221779ed18d9SThierry Reding nvidia,os-data-offset = <0>; 221879ed18d9SThierry Reding nvidia,os-code-offset = <0>; 221979ed18d9SThierry Reding 222079ed18d9SThierry Reding /* 222179ed18d9SThierry Reding * Firmware needs to set this to "okay" once the above values have 222279ed18d9SThierry Reding * been updated. 222379ed18d9SThierry Reding */ 222479ed18d9SThierry Reding status = "disabled"; 222579ed18d9SThierry Reding }; 222679ed18d9SThierry Reding }; 222779ed18d9SThierry Reding 2228ec142c44SVidya Sagar pcie@140a0000 { 2229ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie"; 2230ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CA>; 2231ec142c44SVidya Sagar reg = <0x00 0x140a0000 0x0 0x00020000>, /* appl registers (128K) */ 2232ec142c44SVidya Sagar <0x00 0x2a000000 0x0 0x00040000>, /* configuration space (256K) */ 2233ec142c44SVidya Sagar <0x00 0x2a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2234794b834dSVidya Sagar <0x00 0x2a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2235794b834dSVidya Sagar <0x35 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2236794b834dSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2237ec142c44SVidya Sagar 2238ec142c44SVidya Sagar #address-cells = <3>; 2239ec142c44SVidya Sagar #size-cells = <2>; 2240ec142c44SVidya Sagar device_type = "pci"; 2241ec142c44SVidya Sagar num-lanes = <4>; 2242ec142c44SVidya Sagar num-viewport = <8>; 2243ec142c44SVidya Sagar linux,pci-domain = <8>; 2244ec142c44SVidya Sagar 2245ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX2_C8_CORE>; 2246ec142c44SVidya Sagar clock-names = "core"; 2247ec142c44SVidya Sagar 2248ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX2_CORE_8_APB>, 2249ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX2_CORE_8>; 2250ec142c44SVidya Sagar reset-names = "apb", "core"; 2251ec142c44SVidya Sagar 2252ec142c44SVidya Sagar interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2253ec142c44SVidya Sagar <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2254ec142c44SVidya Sagar interrupt-names = "intr", "msi"; 2255ec142c44SVidya Sagar 2256ec142c44SVidya Sagar #interrupt-cells = <1>; 2257ec142c44SVidya Sagar interrupt-map-mask = <0 0 0 0>; 2258ec142c44SVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 2259ec142c44SVidya Sagar 2260ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 8>; 2261ec142c44SVidya Sagar 2262ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2263ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2264ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2265ec142c44SVidya Sagar 2266ec142c44SVidya Sagar bus-range = <0x0 0xff>; 2267ec142c44SVidya Sagar 2268ec142c44SVidya Sagar ranges = <0x43000000 0x32 0x40000000 0x32 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2269ec142c44SVidya Sagar <0x02000000 0x0 0x40000000 0x35 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2270ec142c44SVidya Sagar <0x01000000 0x0 0x2a100000 0x00 0x2a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2271ec142c44SVidya Sagar 2272ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE8AR &emc>, 2273ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE8AW &emc>; 2274ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2275ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE8 0x1000>; 2276ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2277ec142c44SVidya Sagar dma-coherent; 2278ec142c44SVidya Sagar 2279ec142c44SVidya Sagar status = "disabled"; 2280ec142c44SVidya Sagar }; 2281ec142c44SVidya Sagar 2282ec142c44SVidya Sagar pcie@140c0000 { 2283ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie"; 2284ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CB>; 2285ec142c44SVidya Sagar reg = <0x00 0x140c0000 0x0 0x00020000>, /* appl registers (128K) */ 2286ec142c44SVidya Sagar <0x00 0x2c000000 0x0 0x00040000>, /* configuration space (256K) */ 2287ec142c44SVidya Sagar <0x00 0x2c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2288794b834dSVidya Sagar <0x00 0x2c080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2289794b834dSVidya Sagar <0x38 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2290794b834dSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2291ec142c44SVidya Sagar 2292ec142c44SVidya Sagar #address-cells = <3>; 2293ec142c44SVidya Sagar #size-cells = <2>; 2294ec142c44SVidya Sagar device_type = "pci"; 2295ec142c44SVidya Sagar num-lanes = <4>; 2296ec142c44SVidya Sagar num-viewport = <8>; 2297ec142c44SVidya Sagar linux,pci-domain = <9>; 2298ec142c44SVidya Sagar 2299ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX2_C9_CORE>; 2300ec142c44SVidya Sagar clock-names = "core"; 2301ec142c44SVidya Sagar 2302ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX2_CORE_9_APB>, 2303ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX2_CORE_9>; 2304ec142c44SVidya Sagar reset-names = "apb", "core"; 2305ec142c44SVidya Sagar 2306ec142c44SVidya Sagar interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2307ec142c44SVidya Sagar <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2308ec142c44SVidya Sagar interrupt-names = "intr", "msi"; 2309ec142c44SVidya Sagar 2310ec142c44SVidya Sagar #interrupt-cells = <1>; 2311ec142c44SVidya Sagar interrupt-map-mask = <0 0 0 0>; 2312ec142c44SVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2313ec142c44SVidya Sagar 2314ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 9>; 2315ec142c44SVidya Sagar 2316ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2317ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2318ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2319ec142c44SVidya Sagar 2320ec142c44SVidya Sagar bus-range = <0x0 0xff>; 2321ec142c44SVidya Sagar 232224840065SVidya Sagar ranges = <0x43000000 0x35 0x40000000 0x35 0x40000000 0x2 0xc0000000>, /* prefetchable memory (11264 MB) */ 2323ec142c44SVidya Sagar <0x02000000 0x0 0x40000000 0x38 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2324ec142c44SVidya Sagar <0x01000000 0x0 0x2c100000 0x00 0x2c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2325ec142c44SVidya Sagar 2326ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE9AR &emc>, 2327ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE9AW &emc>; 2328ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2329ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE9 0x1000>; 2330ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2331ec142c44SVidya Sagar dma-coherent; 2332ec142c44SVidya Sagar 2333ec142c44SVidya Sagar status = "disabled"; 2334ec142c44SVidya Sagar }; 2335ec142c44SVidya Sagar 2336ec142c44SVidya Sagar pcie@140e0000 { 2337ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie"; 2338ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CC>; 2339ec142c44SVidya Sagar reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K) */ 2340ec142c44SVidya Sagar <0x00 0x2e000000 0x0 0x00040000>, /* configuration space (256K) */ 2341ec142c44SVidya Sagar <0x00 0x2e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2342794b834dSVidya Sagar <0x00 0x2e080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2343794b834dSVidya Sagar <0x3b 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2344794b834dSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2345ec142c44SVidya Sagar 2346ec142c44SVidya Sagar #address-cells = <3>; 2347ec142c44SVidya Sagar #size-cells = <2>; 2348ec142c44SVidya Sagar device_type = "pci"; 2349ec142c44SVidya Sagar num-lanes = <4>; 2350ec142c44SVidya Sagar num-viewport = <8>; 2351ec142c44SVidya Sagar linux,pci-domain = <10>; 2352ec142c44SVidya Sagar 2353ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX2_C10_CORE>; 2354ec142c44SVidya Sagar clock-names = "core"; 2355ec142c44SVidya Sagar 2356ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX2_CORE_10_APB>, 2357ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX2_CORE_10>; 2358ec142c44SVidya Sagar reset-names = "apb", "core"; 2359ec142c44SVidya Sagar 2360ec142c44SVidya Sagar interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2361ec142c44SVidya Sagar <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2362ec142c44SVidya Sagar interrupt-names = "intr", "msi"; 2363ec142c44SVidya Sagar 2364ec142c44SVidya Sagar #interrupt-cells = <1>; 2365ec142c44SVidya Sagar interrupt-map-mask = <0 0 0 0>; 2366ec142c44SVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 2367ec142c44SVidya Sagar 2368ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 10>; 2369ec142c44SVidya Sagar 2370ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2371ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2372ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2373ec142c44SVidya Sagar 2374ec142c44SVidya Sagar bus-range = <0x0 0xff>; 2375ec142c44SVidya Sagar 2376ec142c44SVidya Sagar ranges = <0x43000000 0x38 0x40000000 0x38 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2377ec142c44SVidya Sagar <0x02000000 0x0 0x40000000 0x3b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2378ec142c44SVidya Sagar <0x01000000 0x0 0x2e100000 0x00 0x2e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2379ec142c44SVidya Sagar 2380ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE10AR &emc>, 2381ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE10AW &emc>; 2382ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2383ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>; 2384ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2385ec142c44SVidya Sagar dma-coherent; 2386ec142c44SVidya Sagar 2387ec142c44SVidya Sagar status = "disabled"; 2388ec142c44SVidya Sagar }; 2389ec142c44SVidya Sagar 23902838cfddSThierry Reding pcie-ep@140e0000 { 23912838cfddSThierry Reding compatible = "nvidia,tegra234-pcie-ep"; 23922838cfddSThierry Reding power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CC>; 23932838cfddSThierry Reding reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K) */ 23942838cfddSThierry Reding <0x00 0x2e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 23952838cfddSThierry Reding <0x00 0x2e080000 0x0 0x00040000>, /* DBI space (256K) */ 23962838cfddSThierry Reding <0x38 0x40000000 0x3 0x00000000>; /* Address Space (12G) */ 23972838cfddSThierry Reding reg-names = "appl", "atu_dma", "dbi", "addr_space"; 23982838cfddSThierry Reding 23992838cfddSThierry Reding num-lanes = <4>; 24002838cfddSThierry Reding 24012838cfddSThierry Reding clocks = <&bpmp TEGRA234_CLK_PEX2_C10_CORE>; 24022838cfddSThierry Reding clock-names = "core"; 24032838cfddSThierry Reding 24042838cfddSThierry Reding resets = <&bpmp TEGRA234_RESET_PEX2_CORE_10_APB>, 24052838cfddSThierry Reding <&bpmp TEGRA234_RESET_PEX2_CORE_10>; 24062838cfddSThierry Reding reset-names = "apb", "core"; 24072838cfddSThierry Reding 24082838cfddSThierry Reding interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 24092838cfddSThierry Reding interrupt-names = "intr"; 24102838cfddSThierry Reding 24112838cfddSThierry Reding nvidia,bpmp = <&bpmp 10>; 24122838cfddSThierry Reding 24132838cfddSThierry Reding nvidia,enable-ext-refclk; 24142838cfddSThierry Reding nvidia,aspm-cmrt-us = <60>; 24152838cfddSThierry Reding nvidia,aspm-pwr-on-t-us = <20>; 24162838cfddSThierry Reding nvidia,aspm-l0s-entrance-latency-us = <3>; 24172838cfddSThierry Reding 24182838cfddSThierry Reding interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE10AR &emc>, 24192838cfddSThierry Reding <&mc TEGRA234_MEMORY_CLIENT_PCIE10AW &emc>; 24202838cfddSThierry Reding interconnect-names = "dma-mem", "write"; 24212838cfddSThierry Reding iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>; 24222838cfddSThierry Reding iommu-map-mask = <0x0>; 24232838cfddSThierry Reding dma-coherent; 24242838cfddSThierry Reding 24252838cfddSThierry Reding status = "disabled"; 24262838cfddSThierry Reding }; 24272838cfddSThierry Reding 2428ec142c44SVidya Sagar pcie@14100000 { 2429ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie"; 2430ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>; 2431ec142c44SVidya Sagar reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */ 2432ec142c44SVidya Sagar <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */ 2433ec142c44SVidya Sagar <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2434794b834dSVidya Sagar <0x00 0x30080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2435794b834dSVidya Sagar <0x20 0xb0000000 0x0 0x10000000>; /* ECAM (256MB) */ 2436794b834dSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2437ec142c44SVidya Sagar 2438ec142c44SVidya Sagar #address-cells = <3>; 2439ec142c44SVidya Sagar #size-cells = <2>; 2440ec142c44SVidya Sagar device_type = "pci"; 2441ec142c44SVidya Sagar num-lanes = <1>; 2442ec142c44SVidya Sagar num-viewport = <8>; 2443ec142c44SVidya Sagar linux,pci-domain = <1>; 2444ec142c44SVidya Sagar 2445ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX0_C1_CORE>; 2446ec142c44SVidya Sagar clock-names = "core"; 2447ec142c44SVidya Sagar 2448ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX0_CORE_1_APB>, 2449ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX0_CORE_1>; 2450ec142c44SVidya Sagar reset-names = "apb", "core"; 2451ec142c44SVidya Sagar 2452ec142c44SVidya Sagar interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2453ec142c44SVidya Sagar <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2454ec142c44SVidya Sagar interrupt-names = "intr", "msi"; 2455ec142c44SVidya Sagar 2456ec142c44SVidya Sagar #interrupt-cells = <1>; 2457ec142c44SVidya Sagar interrupt-map-mask = <0 0 0 0>; 2458ec142c44SVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 2459ec142c44SVidya Sagar 2460ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 1>; 2461ec142c44SVidya Sagar 2462ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2463ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2464ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2465ec142c44SVidya Sagar 2466ec142c44SVidya Sagar bus-range = <0x0 0xff>; 2467ec142c44SVidya Sagar 2468ec142c44SVidya Sagar ranges = <0x43000000 0x20 0x80000000 0x20 0x80000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ 2469ec142c44SVidya Sagar <0x02000000 0x0 0x40000000 0x20 0xa8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2470ec142c44SVidya Sagar <0x01000000 0x0 0x30100000 0x00 0x30100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2471ec142c44SVidya Sagar 2472ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE1R &emc>, 2473ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE1W &emc>; 2474ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2475ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE1 0x1000>; 2476ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2477ec142c44SVidya Sagar dma-coherent; 2478ec142c44SVidya Sagar 2479ec142c44SVidya Sagar status = "disabled"; 2480ec142c44SVidya Sagar }; 2481ec142c44SVidya Sagar 2482ec142c44SVidya Sagar pcie@14120000 { 2483ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie"; 2484ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>; 2485ec142c44SVidya Sagar reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */ 2486ec142c44SVidya Sagar <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */ 2487ec142c44SVidya Sagar <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2488794b834dSVidya Sagar <0x00 0x32080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2489794b834dSVidya Sagar <0x20 0xf0000000 0x0 0x10000000>; /* ECAM (256MB) */ 2490794b834dSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2491ec142c44SVidya Sagar 2492ec142c44SVidya Sagar #address-cells = <3>; 2493ec142c44SVidya Sagar #size-cells = <2>; 2494ec142c44SVidya Sagar device_type = "pci"; 2495ec142c44SVidya Sagar num-lanes = <1>; 2496ec142c44SVidya Sagar num-viewport = <8>; 2497ec142c44SVidya Sagar linux,pci-domain = <2>; 2498ec142c44SVidya Sagar 2499ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX0_C2_CORE>; 2500ec142c44SVidya Sagar clock-names = "core"; 2501ec142c44SVidya Sagar 2502ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX0_CORE_2_APB>, 2503ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX0_CORE_2>; 2504ec142c44SVidya Sagar reset-names = "apb", "core"; 2505ec142c44SVidya Sagar 2506ec142c44SVidya Sagar interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2507ec142c44SVidya Sagar <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2508ec142c44SVidya Sagar interrupt-names = "intr", "msi"; 2509ec142c44SVidya Sagar 2510ec142c44SVidya Sagar #interrupt-cells = <1>; 2511ec142c44SVidya Sagar interrupt-map-mask = <0 0 0 0>; 2512ec142c44SVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 2513ec142c44SVidya Sagar 2514ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 2>; 2515ec142c44SVidya Sagar 2516ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2517ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2518ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2519ec142c44SVidya Sagar 2520ec142c44SVidya Sagar bus-range = <0x0 0xff>; 2521ec142c44SVidya Sagar 2522ec142c44SVidya Sagar ranges = <0x43000000 0x20 0xc0000000 0x20 0xc0000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ 2523ec142c44SVidya Sagar <0x02000000 0x0 0x40000000 0x20 0xe8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2524ec142c44SVidya Sagar <0x01000000 0x0 0x32100000 0x00 0x32100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2525ec142c44SVidya Sagar 2526ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE2AR &emc>, 2527ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE2AW &emc>; 2528ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2529ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE2 0x1000>; 2530ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2531ec142c44SVidya Sagar dma-coherent; 2532ec142c44SVidya Sagar 2533ec142c44SVidya Sagar status = "disabled"; 2534ec142c44SVidya Sagar }; 2535ec142c44SVidya Sagar 2536ec142c44SVidya Sagar pcie@14140000 { 2537ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie"; 2538ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>; 2539ec142c44SVidya Sagar reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */ 2540ec142c44SVidya Sagar <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */ 2541ec142c44SVidya Sagar <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2542794b834dSVidya Sagar <0x00 0x34080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2543794b834dSVidya Sagar <0x21 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2544794b834dSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2545ec142c44SVidya Sagar 2546ec142c44SVidya Sagar #address-cells = <3>; 2547ec142c44SVidya Sagar #size-cells = <2>; 2548ec142c44SVidya Sagar device_type = "pci"; 2549ec142c44SVidya Sagar num-lanes = <1>; 2550ec142c44SVidya Sagar num-viewport = <8>; 2551ec142c44SVidya Sagar linux,pci-domain = <3>; 2552ec142c44SVidya Sagar 2553ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX0_C3_CORE>; 2554ec142c44SVidya Sagar clock-names = "core"; 2555ec142c44SVidya Sagar 2556ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX0_CORE_3_APB>, 2557ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX0_CORE_3>; 2558ec142c44SVidya Sagar reset-names = "apb", "core"; 2559ec142c44SVidya Sagar 2560ec142c44SVidya Sagar interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2561ec142c44SVidya Sagar <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2562ec142c44SVidya Sagar interrupt-names = "intr", "msi"; 2563ec142c44SVidya Sagar 2564ec142c44SVidya Sagar #interrupt-cells = <1>; 2565ec142c44SVidya Sagar interrupt-map-mask = <0 0 0 0>; 2566ec142c44SVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 2567ec142c44SVidya Sagar 2568ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 3>; 2569ec142c44SVidya Sagar 2570ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2571ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2572ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2573ec142c44SVidya Sagar 2574ec142c44SVidya Sagar bus-range = <0x0 0xff>; 2575ec142c44SVidya Sagar 2576ec142c44SVidya Sagar ranges = <0x43000000 0x21 0x00000000 0x21 0x00000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ 257747a2f35dSVidya Sagar <0x02000000 0x0 0x40000000 0x21 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2578ec142c44SVidya Sagar <0x01000000 0x0 0x34100000 0x00 0x34100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2579ec142c44SVidya Sagar 2580ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE3R &emc>, 2581ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE3W &emc>; 2582ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2583ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE3 0x1000>; 2584ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2585ec142c44SVidya Sagar dma-coherent; 2586ec142c44SVidya Sagar 2587ec142c44SVidya Sagar status = "disabled"; 2588ec142c44SVidya Sagar }; 2589ec142c44SVidya Sagar 2590ec142c44SVidya Sagar pcie@14160000 { 2591ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie"; 2592ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BB>; 2593ec142c44SVidya Sagar reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2594ec142c44SVidya Sagar <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ 2595ec142c44SVidya Sagar <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2596794b834dSVidya Sagar <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2597794b834dSVidya Sagar <0x24 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2598794b834dSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2599ec142c44SVidya Sagar 2600ec142c44SVidya Sagar #address-cells = <3>; 2601ec142c44SVidya Sagar #size-cells = <2>; 2602ec142c44SVidya Sagar device_type = "pci"; 2603ec142c44SVidya Sagar num-lanes = <4>; 2604ec142c44SVidya Sagar num-viewport = <8>; 2605ec142c44SVidya Sagar linux,pci-domain = <4>; 2606ec142c44SVidya Sagar 2607ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX0_C4_CORE>; 2608ec142c44SVidya Sagar clock-names = "core"; 2609ec142c44SVidya Sagar 2610ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX0_CORE_4_APB>, 2611ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX0_CORE_4>; 2612ec142c44SVidya Sagar reset-names = "apb", "core"; 2613ec142c44SVidya Sagar 2614ec142c44SVidya Sagar interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2615ec142c44SVidya Sagar <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2616ec142c44SVidya Sagar interrupt-names = "intr", "msi"; 2617ec142c44SVidya Sagar 2618ec142c44SVidya Sagar #interrupt-cells = <1>; 2619ec142c44SVidya Sagar interrupt-map-mask = <0 0 0 0>; 2620ec142c44SVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 2621ec142c44SVidya Sagar 2622ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 4>; 2623ec142c44SVidya Sagar 2624ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2625ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2626ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2627ec142c44SVidya Sagar 2628ec142c44SVidya Sagar bus-range = <0x0 0xff>; 2629ec142c44SVidya Sagar 2630ec142c44SVidya Sagar ranges = <0x43000000 0x21 0x40000000 0x21 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2631ec142c44SVidya Sagar <0x02000000 0x0 0x40000000 0x24 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2632ec142c44SVidya Sagar <0x01000000 0x0 0x36100000 0x00 0x36100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2633ec142c44SVidya Sagar 2634ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE4R &emc>, 2635ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE4W &emc>; 2636ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2637ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE4 0x1000>; 2638ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2639ec142c44SVidya Sagar dma-coherent; 2640ec142c44SVidya Sagar 2641ec142c44SVidya Sagar status = "disabled"; 2642ec142c44SVidya Sagar }; 2643ec142c44SVidya Sagar 2644ec142c44SVidya Sagar pcie@14180000 { 2645ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie"; 2646ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BA>; 2647ec142c44SVidya Sagar reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2648ec142c44SVidya Sagar <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ 2649ec142c44SVidya Sagar <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2650794b834dSVidya Sagar <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2651794b834dSVidya Sagar <0x27 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2652794b834dSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2653ec142c44SVidya Sagar 2654ec142c44SVidya Sagar #address-cells = <3>; 2655ec142c44SVidya Sagar #size-cells = <2>; 2656ec142c44SVidya Sagar device_type = "pci"; 2657ec142c44SVidya Sagar num-lanes = <4>; 2658ec142c44SVidya Sagar num-viewport = <8>; 2659ec142c44SVidya Sagar linux,pci-domain = <0>; 2660ec142c44SVidya Sagar 2661ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX0_C0_CORE>; 2662ec142c44SVidya Sagar clock-names = "core"; 2663ec142c44SVidya Sagar 2664ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX0_CORE_0_APB>, 2665ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX0_CORE_0>; 2666ec142c44SVidya Sagar reset-names = "apb", "core"; 2667ec142c44SVidya Sagar 2668ec142c44SVidya Sagar interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2669ec142c44SVidya Sagar <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2670ec142c44SVidya Sagar interrupt-names = "intr", "msi"; 2671ec142c44SVidya Sagar 2672ec142c44SVidya Sagar #interrupt-cells = <1>; 2673ec142c44SVidya Sagar interrupt-map-mask = <0 0 0 0>; 2674ec142c44SVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 2675ec142c44SVidya Sagar 2676ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 0>; 2677ec142c44SVidya Sagar 2678ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2679ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2680ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2681ec142c44SVidya Sagar 2682ec142c44SVidya Sagar bus-range = <0x0 0xff>; 2683ec142c44SVidya Sagar 2684ec142c44SVidya Sagar ranges = <0x43000000 0x24 0x40000000 0x24 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2685ec142c44SVidya Sagar <0x02000000 0x0 0x40000000 0x27 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2686ec142c44SVidya Sagar <0x01000000 0x0 0x38100000 0x00 0x38100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2687ec142c44SVidya Sagar 2688ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE0R &emc>, 2689ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE0W &emc>; 2690ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2691ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE0 0x1000>; 2692ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2693ec142c44SVidya Sagar dma-coherent; 2694ec142c44SVidya Sagar 2695ec142c44SVidya Sagar status = "disabled"; 2696ec142c44SVidya Sagar }; 2697ec142c44SVidya Sagar 2698ec142c44SVidya Sagar pcie@141a0000 { 2699ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie"; 2700ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>; 2701ec142c44SVidya Sagar reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2702ec142c44SVidya Sagar <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */ 2703ec142c44SVidya Sagar <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2704794b834dSVidya Sagar <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2705794b834dSVidya Sagar <0x2b 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2706794b834dSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2707ec142c44SVidya Sagar 2708ec142c44SVidya Sagar #address-cells = <3>; 2709ec142c44SVidya Sagar #size-cells = <2>; 2710ec142c44SVidya Sagar device_type = "pci"; 2711ec142c44SVidya Sagar num-lanes = <8>; 2712ec142c44SVidya Sagar num-viewport = <8>; 2713ec142c44SVidya Sagar linux,pci-domain = <5>; 2714ec142c44SVidya Sagar 2715ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>; 2716ec142c44SVidya Sagar clock-names = "core"; 2717ec142c44SVidya Sagar 2718ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>, 2719ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX1_CORE_5>; 2720ec142c44SVidya Sagar reset-names = "apb", "core"; 2721ec142c44SVidya Sagar 2722ec142c44SVidya Sagar interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2723ec142c44SVidya Sagar <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2724ec142c44SVidya Sagar interrupt-names = "intr", "msi"; 2725ec142c44SVidya Sagar 2726ec142c44SVidya Sagar #interrupt-cells = <1>; 2727ec142c44SVidya Sagar interrupt-map-mask = <0 0 0 0>; 2728ec142c44SVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 2729ec142c44SVidya Sagar 2730ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 5>; 2731ec142c44SVidya Sagar 2732ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2733ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2734ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2735ec142c44SVidya Sagar 2736ec142c44SVidya Sagar bus-range = <0x0 0xff>; 2737ec142c44SVidya Sagar 273824840065SVidya Sagar ranges = <0x43000000 0x28 0x00000000 0x28 0x00000000 0x3 0x28000000>, /* prefetchable memory (12928 MB) */ 2739ec142c44SVidya Sagar <0x02000000 0x0 0x40000000 0x2b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2740ec142c44SVidya Sagar <0x01000000 0x0 0x3a100000 0x00 0x3a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2741ec142c44SVidya Sagar 2742ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE5R &emc>, 2743ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE5W &emc>; 2744ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2745ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>; 2746ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2747ec142c44SVidya Sagar dma-coherent; 2748ec142c44SVidya Sagar 2749ec142c44SVidya Sagar status = "disabled"; 2750ec142c44SVidya Sagar }; 2751ec142c44SVidya Sagar 27522838cfddSThierry Reding pcie-ep@141a0000 { 27532838cfddSThierry Reding compatible = "nvidia,tegra234-pcie-ep"; 27542838cfddSThierry Reding power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>; 27552838cfddSThierry Reding reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 27562838cfddSThierry Reding <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 27572838cfddSThierry Reding <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 27582838cfddSThierry Reding <0x27 0x40000000 0x4 0x00000000>; /* Address Space (16G) */ 27592838cfddSThierry Reding reg-names = "appl", "atu_dma", "dbi", "addr_space"; 27602838cfddSThierry Reding 27612838cfddSThierry Reding num-lanes = <8>; 27622838cfddSThierry Reding 27632838cfddSThierry Reding clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>; 27642838cfddSThierry Reding clock-names = "core"; 27652838cfddSThierry Reding 27662838cfddSThierry Reding resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>, 27672838cfddSThierry Reding <&bpmp TEGRA234_RESET_PEX1_CORE_5>; 27682838cfddSThierry Reding reset-names = "apb", "core"; 27692838cfddSThierry Reding 27702838cfddSThierry Reding interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 27712838cfddSThierry Reding interrupt-names = "intr"; 27722838cfddSThierry Reding 27732838cfddSThierry Reding nvidia,bpmp = <&bpmp 5>; 27742838cfddSThierry Reding 27752838cfddSThierry Reding nvidia,enable-ext-refclk; 27762838cfddSThierry Reding nvidia,aspm-cmrt-us = <60>; 27772838cfddSThierry Reding nvidia,aspm-pwr-on-t-us = <20>; 27782838cfddSThierry Reding nvidia,aspm-l0s-entrance-latency-us = <3>; 27792838cfddSThierry Reding 27802838cfddSThierry Reding interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE5R &emc>, 27812838cfddSThierry Reding <&mc TEGRA234_MEMORY_CLIENT_PCIE5W &emc>; 27822838cfddSThierry Reding interconnect-names = "dma-mem", "write"; 27832838cfddSThierry Reding iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>; 27842838cfddSThierry Reding iommu-map-mask = <0x0>; 27852838cfddSThierry Reding dma-coherent; 27862838cfddSThierry Reding 27872838cfddSThierry Reding status = "disabled"; 27882838cfddSThierry Reding }; 27892838cfddSThierry Reding 2790ec142c44SVidya Sagar pcie@141c0000 { 2791ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie"; 2792ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4A>; 2793ec142c44SVidya Sagar reg = <0x00 0x141c0000 0x0 0x00020000>, /* appl registers (128K) */ 2794ec142c44SVidya Sagar <0x00 0x3c000000 0x0 0x00040000>, /* configuration space (256K) */ 2795ec142c44SVidya Sagar <0x00 0x3c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2796794b834dSVidya Sagar <0x00 0x3c080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2797794b834dSVidya Sagar <0x2e 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2798794b834dSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2799ec142c44SVidya Sagar 2800ec142c44SVidya Sagar #address-cells = <3>; 2801ec142c44SVidya Sagar #size-cells = <2>; 2802ec142c44SVidya Sagar device_type = "pci"; 2803ec142c44SVidya Sagar num-lanes = <4>; 2804ec142c44SVidya Sagar num-viewport = <8>; 2805ec142c44SVidya Sagar linux,pci-domain = <6>; 2806ec142c44SVidya Sagar 2807ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX1_C6_CORE>; 2808ec142c44SVidya Sagar clock-names = "core"; 2809ec142c44SVidya Sagar 2810ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX1_CORE_6_APB>, 2811ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX1_CORE_6>; 2812ec142c44SVidya Sagar reset-names = "apb", "core"; 2813ec142c44SVidya Sagar 2814ec142c44SVidya Sagar interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2815ec142c44SVidya Sagar <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2816ec142c44SVidya Sagar interrupt-names = "intr", "msi"; 2817ec142c44SVidya Sagar 2818ec142c44SVidya Sagar #interrupt-cells = <1>; 2819ec142c44SVidya Sagar interrupt-map-mask = <0 0 0 0>; 2820ec142c44SVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 2821ec142c44SVidya Sagar 2822ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 6>; 2823ec142c44SVidya Sagar 2824ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2825ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2826ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2827ec142c44SVidya Sagar 2828ec142c44SVidya Sagar bus-range = <0x0 0xff>; 2829ec142c44SVidya Sagar 2830ec142c44SVidya Sagar ranges = <0x43000000 0x2b 0x40000000 0x2b 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2831ec142c44SVidya Sagar <0x02000000 0x0 0x40000000 0x2e 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2832ec142c44SVidya Sagar <0x01000000 0x0 0x3c100000 0x00 0x3c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2833ec142c44SVidya Sagar 2834ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE6AR &emc>, 2835ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE6AW &emc>; 2836ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2837ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>; 2838ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2839ec142c44SVidya Sagar dma-coherent; 2840ec142c44SVidya Sagar 2841ec142c44SVidya Sagar status = "disabled"; 2842ec142c44SVidya Sagar }; 2843ec142c44SVidya Sagar 28442838cfddSThierry Reding pcie-ep@141c0000 { 28452838cfddSThierry Reding compatible = "nvidia,tegra234-pcie-ep"; 28462838cfddSThierry Reding power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4A>; 28472838cfddSThierry Reding reg = <0x00 0x141c0000 0x0 0x00020000>, /* appl registers (128K) */ 28482838cfddSThierry Reding <0x00 0x3c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 28492838cfddSThierry Reding <0x00 0x3c080000 0x0 0x00040000>, /* DBI space (256K) */ 28502838cfddSThierry Reding <0x2b 0x40000000 0x3 0x00000000>; /* Address Space (12G) */ 28512838cfddSThierry Reding reg-names = "appl", "atu_dma", "dbi", "addr_space"; 28522838cfddSThierry Reding 28532838cfddSThierry Reding num-lanes = <4>; 28542838cfddSThierry Reding 28552838cfddSThierry Reding clocks = <&bpmp TEGRA234_CLK_PEX1_C6_CORE>; 28562838cfddSThierry Reding clock-names = "core"; 28572838cfddSThierry Reding 28582838cfddSThierry Reding resets = <&bpmp TEGRA234_RESET_PEX1_CORE_6_APB>, 28592838cfddSThierry Reding <&bpmp TEGRA234_RESET_PEX1_CORE_6>; 28602838cfddSThierry Reding reset-names = "apb", "core"; 28612838cfddSThierry Reding 28622838cfddSThierry Reding interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 28632838cfddSThierry Reding interrupt-names = "intr"; 28642838cfddSThierry Reding 28652838cfddSThierry Reding nvidia,bpmp = <&bpmp 6>; 28662838cfddSThierry Reding 28672838cfddSThierry Reding nvidia,enable-ext-refclk; 28682838cfddSThierry Reding nvidia,aspm-cmrt-us = <60>; 28692838cfddSThierry Reding nvidia,aspm-pwr-on-t-us = <20>; 28702838cfddSThierry Reding nvidia,aspm-l0s-entrance-latency-us = <3>; 28712838cfddSThierry Reding 28722838cfddSThierry Reding interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE6AR &emc>, 28732838cfddSThierry Reding <&mc TEGRA234_MEMORY_CLIENT_PCIE6AW &emc>; 28742838cfddSThierry Reding interconnect-names = "dma-mem", "write"; 28752838cfddSThierry Reding iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>; 28762838cfddSThierry Reding iommu-map-mask = <0x0>; 28772838cfddSThierry Reding dma-coherent; 28782838cfddSThierry Reding 28792838cfddSThierry Reding status = "disabled"; 28802838cfddSThierry Reding }; 28812838cfddSThierry Reding 2882ec142c44SVidya Sagar pcie@141e0000 { 2883ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie"; 2884ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8B>; 2885ec142c44SVidya Sagar reg = <0x00 0x141e0000 0x0 0x00020000>, /* appl registers (128K) */ 2886ec142c44SVidya Sagar <0x00 0x3e000000 0x0 0x00040000>, /* configuration space (256K) */ 2887ec142c44SVidya Sagar <0x00 0x3e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2888794b834dSVidya Sagar <0x00 0x3e080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2889794b834dSVidya Sagar <0x32 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2890794b834dSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2891ec142c44SVidya Sagar 2892ec142c44SVidya Sagar #address-cells = <3>; 2893ec142c44SVidya Sagar #size-cells = <2>; 2894ec142c44SVidya Sagar device_type = "pci"; 2895ec142c44SVidya Sagar num-lanes = <8>; 2896ec142c44SVidya Sagar num-viewport = <8>; 2897ec142c44SVidya Sagar linux,pci-domain = <7>; 2898ec142c44SVidya Sagar 2899ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX2_C7_CORE>; 2900ec142c44SVidya Sagar clock-names = "core"; 2901ec142c44SVidya Sagar 2902ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX2_CORE_7_APB>, 2903ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX2_CORE_7>; 2904ec142c44SVidya Sagar reset-names = "apb", "core"; 2905ec142c44SVidya Sagar 2906ec142c44SVidya Sagar interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2907ec142c44SVidya Sagar <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2908ec142c44SVidya Sagar interrupt-names = "intr", "msi"; 2909ec142c44SVidya Sagar 2910ec142c44SVidya Sagar #interrupt-cells = <1>; 2911ec142c44SVidya Sagar interrupt-map-mask = <0 0 0 0>; 2912ec142c44SVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 2913ec142c44SVidya Sagar 2914ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 7>; 2915ec142c44SVidya Sagar 2916ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2917ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2918ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2919ec142c44SVidya Sagar 2920ec142c44SVidya Sagar bus-range = <0x0 0xff>; 2921ec142c44SVidya Sagar 292224840065SVidya Sagar ranges = <0x43000000 0x30 0x00000000 0x30 0x00000000 0x2 0x28000000>, /* prefetchable memory (8832 MB) */ 2923ec142c44SVidya Sagar <0x02000000 0x0 0x40000000 0x32 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2924ec142c44SVidya Sagar <0x01000000 0x0 0x3e100000 0x00 0x3e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2925ec142c44SVidya Sagar 2926ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE7AR &emc>, 2927ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE7AW &emc>; 2928ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2929ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>; 2930ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2931ec142c44SVidya Sagar dma-coherent; 2932ec142c44SVidya Sagar 2933ec142c44SVidya Sagar status = "disabled"; 2934ec142c44SVidya Sagar }; 2935ec142c44SVidya Sagar 2936ec142c44SVidya Sagar pcie-ep@141e0000 { 2937ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie-ep"; 2938ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8B>; 2939ec142c44SVidya Sagar reg = <0x00 0x141e0000 0x0 0x00020000>, /* appl registers (128K) */ 2940ec142c44SVidya Sagar <0x00 0x3e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2941ec142c44SVidya Sagar <0x00 0x3e080000 0x0 0x00040000>, /* DBI space (256K) */ 2942ec142c44SVidya Sagar <0x2e 0x40000000 0x4 0x00000000>; /* Address Space (16G) */ 2943ec142c44SVidya Sagar reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2944ec142c44SVidya Sagar 2945ec142c44SVidya Sagar num-lanes = <8>; 2946ec142c44SVidya Sagar 2947ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX2_C7_CORE>; 2948ec142c44SVidya Sagar clock-names = "core"; 2949ec142c44SVidya Sagar 2950ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX2_CORE_7_APB>, 2951ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX2_CORE_7>; 2952ec142c44SVidya Sagar reset-names = "apb", "core"; 2953ec142c44SVidya Sagar 2954ec142c44SVidya Sagar interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2955ec142c44SVidya Sagar interrupt-names = "intr"; 2956ec142c44SVidya Sagar 2957ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 7>; 2958ec142c44SVidya Sagar 2959ec142c44SVidya Sagar nvidia,enable-ext-refclk; 2960ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2961ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2962ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2963ec142c44SVidya Sagar 2964ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE7AR &emc>, 2965ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE7AW &emc>; 2966ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2967ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>; 2968ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2969ec142c44SVidya Sagar dma-coherent; 2970ec142c44SVidya Sagar 2971ec142c44SVidya Sagar status = "disabled"; 2972ec142c44SVidya Sagar }; 2973ec142c44SVidya Sagar }; 2974ec142c44SVidya Sagar 29757fa30752SThierry Reding sram@40000000 { 297663944891SThierry Reding compatible = "nvidia,tegra234-sysram", "mmio-sram"; 297798094be1SMikko Perttunen reg = <0x0 0x40000000 0x0 0x80000>; 29782838cfddSThierry Reding 297963944891SThierry Reding #address-cells = <1>; 298063944891SThierry Reding #size-cells = <1>; 298198094be1SMikko Perttunen ranges = <0x0 0x0 0x40000000 0x80000>; 29822838cfddSThierry Reding 298361192a9dSMikko Perttunen no-memory-wc; 298463944891SThierry Reding 298598094be1SMikko Perttunen cpu_bpmp_tx: sram@70000 { 298698094be1SMikko Perttunen reg = <0x70000 0x1000>; 298763944891SThierry Reding label = "cpu-bpmp-tx"; 298863944891SThierry Reding pool; 298963944891SThierry Reding }; 299063944891SThierry Reding 299198094be1SMikko Perttunen cpu_bpmp_rx: sram@71000 { 299298094be1SMikko Perttunen reg = <0x71000 0x1000>; 299363944891SThierry Reding label = "cpu-bpmp-rx"; 299463944891SThierry Reding pool; 299563944891SThierry Reding }; 299663944891SThierry Reding }; 299763944891SThierry Reding 299863944891SThierry Reding bpmp: bpmp { 299963944891SThierry Reding compatible = "nvidia,tegra234-bpmp", "nvidia,tegra186-bpmp"; 300063944891SThierry Reding mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 300163944891SThierry Reding TEGRA_HSP_DB_MASTER_BPMP>; 30027fa30752SThierry Reding shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; 300363944891SThierry Reding #clock-cells = <1>; 300463944891SThierry Reding #reset-cells = <1>; 300563944891SThierry Reding #power-domain-cells = <1>; 30066de481e5SThierry Reding interconnects = <&mc TEGRA234_MEMORY_CLIENT_BPMPR &emc>, 30076de481e5SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_BPMPW &emc>, 30086de481e5SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAR &emc>, 30096de481e5SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAW &emc>; 30106de481e5SThierry Reding interconnect-names = "read", "write", "dma-mem", "dma-write"; 30115710e16aSThierry Reding iommus = <&smmu_niso1 TEGRA234_SID_BPMP>; 301263944891SThierry Reding 301363944891SThierry Reding bpmp_i2c: i2c { 301463944891SThierry Reding compatible = "nvidia,tegra186-bpmp-i2c"; 301563944891SThierry Reding nvidia,bpmp-bus-id = <5>; 301663944891SThierry Reding #address-cells = <1>; 301763944891SThierry Reding #size-cells = <0>; 301863944891SThierry Reding }; 301963944891SThierry Reding }; 302063944891SThierry Reding 302163944891SThierry Reding cpus { 302263944891SThierry Reding #address-cells = <1>; 302363944891SThierry Reding #size-cells = <0>; 302463944891SThierry Reding 3025a12cf5c3SThierry Reding cpu0_0: cpu@0 { 3026a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 302763944891SThierry Reding device_type = "cpu"; 3028a12cf5c3SThierry Reding reg = <0x00000>; 302963944891SThierry Reding 303063944891SThierry Reding enable-method = "psci"; 3031a12cf5c3SThierry Reding 3032a12cf5c3SThierry Reding i-cache-size = <65536>; 3033a12cf5c3SThierry Reding i-cache-line-size = <64>; 3034a12cf5c3SThierry Reding i-cache-sets = <256>; 3035a12cf5c3SThierry Reding d-cache-size = <65536>; 3036a12cf5c3SThierry Reding d-cache-line-size = <64>; 3037a12cf5c3SThierry Reding d-cache-sets = <256>; 3038a12cf5c3SThierry Reding next-level-cache = <&l2c0_0>; 303963944891SThierry Reding }; 3040a12cf5c3SThierry Reding 3041a12cf5c3SThierry Reding cpu0_1: cpu@100 { 3042a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 3043a12cf5c3SThierry Reding device_type = "cpu"; 3044a12cf5c3SThierry Reding reg = <0x00100>; 3045a12cf5c3SThierry Reding 3046a12cf5c3SThierry Reding enable-method = "psci"; 3047a12cf5c3SThierry Reding 3048a12cf5c3SThierry Reding i-cache-size = <65536>; 3049a12cf5c3SThierry Reding i-cache-line-size = <64>; 3050a12cf5c3SThierry Reding i-cache-sets = <256>; 3051a12cf5c3SThierry Reding d-cache-size = <65536>; 3052a12cf5c3SThierry Reding d-cache-line-size = <64>; 3053a12cf5c3SThierry Reding d-cache-sets = <256>; 3054a12cf5c3SThierry Reding next-level-cache = <&l2c0_1>; 3055a12cf5c3SThierry Reding }; 3056a12cf5c3SThierry Reding 3057a12cf5c3SThierry Reding cpu0_2: cpu@200 { 3058a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 3059a12cf5c3SThierry Reding device_type = "cpu"; 3060a12cf5c3SThierry Reding reg = <0x00200>; 3061a12cf5c3SThierry Reding 3062a12cf5c3SThierry Reding enable-method = "psci"; 3063a12cf5c3SThierry Reding 3064a12cf5c3SThierry Reding i-cache-size = <65536>; 3065a12cf5c3SThierry Reding i-cache-line-size = <64>; 3066a12cf5c3SThierry Reding i-cache-sets = <256>; 3067a12cf5c3SThierry Reding d-cache-size = <65536>; 3068a12cf5c3SThierry Reding d-cache-line-size = <64>; 3069a12cf5c3SThierry Reding d-cache-sets = <256>; 3070a12cf5c3SThierry Reding next-level-cache = <&l2c0_2>; 3071a12cf5c3SThierry Reding }; 3072a12cf5c3SThierry Reding 3073a12cf5c3SThierry Reding cpu0_3: cpu@300 { 3074a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 3075a12cf5c3SThierry Reding device_type = "cpu"; 3076a12cf5c3SThierry Reding reg = <0x00300>; 3077a12cf5c3SThierry Reding 3078a12cf5c3SThierry Reding enable-method = "psci"; 3079a12cf5c3SThierry Reding 3080a12cf5c3SThierry Reding i-cache-size = <65536>; 3081a12cf5c3SThierry Reding i-cache-line-size = <64>; 3082a12cf5c3SThierry Reding i-cache-sets = <256>; 3083a12cf5c3SThierry Reding d-cache-size = <65536>; 3084a12cf5c3SThierry Reding d-cache-line-size = <64>; 3085a12cf5c3SThierry Reding d-cache-sets = <256>; 3086a12cf5c3SThierry Reding next-level-cache = <&l2c0_3>; 3087a12cf5c3SThierry Reding }; 3088a12cf5c3SThierry Reding 3089a12cf5c3SThierry Reding cpu1_0: cpu@10000 { 3090a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 3091a12cf5c3SThierry Reding device_type = "cpu"; 3092a12cf5c3SThierry Reding reg = <0x10000>; 3093a12cf5c3SThierry Reding 3094a12cf5c3SThierry Reding enable-method = "psci"; 3095a12cf5c3SThierry Reding 3096a12cf5c3SThierry Reding i-cache-size = <65536>; 3097a12cf5c3SThierry Reding i-cache-line-size = <64>; 3098a12cf5c3SThierry Reding i-cache-sets = <256>; 3099a12cf5c3SThierry Reding d-cache-size = <65536>; 3100a12cf5c3SThierry Reding d-cache-line-size = <64>; 3101a12cf5c3SThierry Reding d-cache-sets = <256>; 3102a12cf5c3SThierry Reding next-level-cache = <&l2c1_0>; 3103a12cf5c3SThierry Reding }; 3104a12cf5c3SThierry Reding 3105a12cf5c3SThierry Reding cpu1_1: cpu@10100 { 3106a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 3107a12cf5c3SThierry Reding device_type = "cpu"; 3108a12cf5c3SThierry Reding reg = <0x10100>; 3109a12cf5c3SThierry Reding 3110a12cf5c3SThierry Reding enable-method = "psci"; 3111a12cf5c3SThierry Reding 3112a12cf5c3SThierry Reding i-cache-size = <65536>; 3113a12cf5c3SThierry Reding i-cache-line-size = <64>; 3114a12cf5c3SThierry Reding i-cache-sets = <256>; 3115a12cf5c3SThierry Reding d-cache-size = <65536>; 3116a12cf5c3SThierry Reding d-cache-line-size = <64>; 3117a12cf5c3SThierry Reding d-cache-sets = <256>; 3118a12cf5c3SThierry Reding next-level-cache = <&l2c1_1>; 3119a12cf5c3SThierry Reding }; 3120a12cf5c3SThierry Reding 3121a12cf5c3SThierry Reding cpu1_2: cpu@10200 { 3122a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 3123a12cf5c3SThierry Reding device_type = "cpu"; 3124a12cf5c3SThierry Reding reg = <0x10200>; 3125a12cf5c3SThierry Reding 3126a12cf5c3SThierry Reding enable-method = "psci"; 3127a12cf5c3SThierry Reding 3128a12cf5c3SThierry Reding i-cache-size = <65536>; 3129a12cf5c3SThierry Reding i-cache-line-size = <64>; 3130a12cf5c3SThierry Reding i-cache-sets = <256>; 3131a12cf5c3SThierry Reding d-cache-size = <65536>; 3132a12cf5c3SThierry Reding d-cache-line-size = <64>; 3133a12cf5c3SThierry Reding d-cache-sets = <256>; 3134a12cf5c3SThierry Reding next-level-cache = <&l2c1_2>; 3135a12cf5c3SThierry Reding }; 3136a12cf5c3SThierry Reding 3137a12cf5c3SThierry Reding cpu1_3: cpu@10300 { 3138a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 3139a12cf5c3SThierry Reding device_type = "cpu"; 3140a12cf5c3SThierry Reding reg = <0x10300>; 3141a12cf5c3SThierry Reding 3142a12cf5c3SThierry Reding enable-method = "psci"; 3143a12cf5c3SThierry Reding 3144a12cf5c3SThierry Reding i-cache-size = <65536>; 3145a12cf5c3SThierry Reding i-cache-line-size = <64>; 3146a12cf5c3SThierry Reding i-cache-sets = <256>; 3147a12cf5c3SThierry Reding d-cache-size = <65536>; 3148a12cf5c3SThierry Reding d-cache-line-size = <64>; 3149a12cf5c3SThierry Reding d-cache-sets = <256>; 3150a12cf5c3SThierry Reding next-level-cache = <&l2c1_3>; 3151a12cf5c3SThierry Reding }; 3152a12cf5c3SThierry Reding 3153a12cf5c3SThierry Reding cpu2_0: cpu@20000 { 3154a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 3155a12cf5c3SThierry Reding device_type = "cpu"; 3156a12cf5c3SThierry Reding reg = <0x20000>; 3157a12cf5c3SThierry Reding 3158a12cf5c3SThierry Reding enable-method = "psci"; 3159a12cf5c3SThierry Reding 3160a12cf5c3SThierry Reding i-cache-size = <65536>; 3161a12cf5c3SThierry Reding i-cache-line-size = <64>; 3162a12cf5c3SThierry Reding i-cache-sets = <256>; 3163a12cf5c3SThierry Reding d-cache-size = <65536>; 3164a12cf5c3SThierry Reding d-cache-line-size = <64>; 3165a12cf5c3SThierry Reding d-cache-sets = <256>; 3166a12cf5c3SThierry Reding next-level-cache = <&l2c2_0>; 3167a12cf5c3SThierry Reding }; 3168a12cf5c3SThierry Reding 3169a12cf5c3SThierry Reding cpu2_1: cpu@20100 { 3170a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 3171a12cf5c3SThierry Reding device_type = "cpu"; 3172a12cf5c3SThierry Reding reg = <0x20100>; 3173a12cf5c3SThierry Reding 3174a12cf5c3SThierry Reding enable-method = "psci"; 3175a12cf5c3SThierry Reding 3176a12cf5c3SThierry Reding i-cache-size = <65536>; 3177a12cf5c3SThierry Reding i-cache-line-size = <64>; 3178a12cf5c3SThierry Reding i-cache-sets = <256>; 3179a12cf5c3SThierry Reding d-cache-size = <65536>; 3180a12cf5c3SThierry Reding d-cache-line-size = <64>; 3181a12cf5c3SThierry Reding d-cache-sets = <256>; 3182a12cf5c3SThierry Reding next-level-cache = <&l2c2_1>; 3183a12cf5c3SThierry Reding }; 3184a12cf5c3SThierry Reding 3185a12cf5c3SThierry Reding cpu2_2: cpu@20200 { 3186a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 3187a12cf5c3SThierry Reding device_type = "cpu"; 3188a12cf5c3SThierry Reding reg = <0x20200>; 3189a12cf5c3SThierry Reding 3190a12cf5c3SThierry Reding enable-method = "psci"; 3191a12cf5c3SThierry Reding 3192a12cf5c3SThierry Reding i-cache-size = <65536>; 3193a12cf5c3SThierry Reding i-cache-line-size = <64>; 3194a12cf5c3SThierry Reding i-cache-sets = <256>; 3195a12cf5c3SThierry Reding d-cache-size = <65536>; 3196a12cf5c3SThierry Reding d-cache-line-size = <64>; 3197a12cf5c3SThierry Reding d-cache-sets = <256>; 3198a12cf5c3SThierry Reding next-level-cache = <&l2c2_2>; 3199a12cf5c3SThierry Reding }; 3200a12cf5c3SThierry Reding 3201a12cf5c3SThierry Reding cpu2_3: cpu@20300 { 3202a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 3203a12cf5c3SThierry Reding device_type = "cpu"; 3204a12cf5c3SThierry Reding reg = <0x20300>; 3205a12cf5c3SThierry Reding 3206a12cf5c3SThierry Reding enable-method = "psci"; 3207a12cf5c3SThierry Reding 3208a12cf5c3SThierry Reding i-cache-size = <65536>; 3209a12cf5c3SThierry Reding i-cache-line-size = <64>; 3210a12cf5c3SThierry Reding i-cache-sets = <256>; 3211a12cf5c3SThierry Reding d-cache-size = <65536>; 3212a12cf5c3SThierry Reding d-cache-line-size = <64>; 3213a12cf5c3SThierry Reding d-cache-sets = <256>; 3214a12cf5c3SThierry Reding next-level-cache = <&l2c2_3>; 3215a12cf5c3SThierry Reding }; 3216a12cf5c3SThierry Reding 3217a12cf5c3SThierry Reding cpu-map { 3218a12cf5c3SThierry Reding cluster0 { 3219a12cf5c3SThierry Reding core0 { 3220a12cf5c3SThierry Reding cpu = <&cpu0_0>; 3221a12cf5c3SThierry Reding }; 3222a12cf5c3SThierry Reding 3223a12cf5c3SThierry Reding core1 { 3224a12cf5c3SThierry Reding cpu = <&cpu0_1>; 3225a12cf5c3SThierry Reding }; 3226a12cf5c3SThierry Reding 3227a12cf5c3SThierry Reding core2 { 3228a12cf5c3SThierry Reding cpu = <&cpu0_2>; 3229a12cf5c3SThierry Reding }; 3230a12cf5c3SThierry Reding 3231a12cf5c3SThierry Reding core3 { 3232a12cf5c3SThierry Reding cpu = <&cpu0_3>; 3233a12cf5c3SThierry Reding }; 3234a12cf5c3SThierry Reding }; 3235a12cf5c3SThierry Reding 3236a12cf5c3SThierry Reding cluster1 { 3237a12cf5c3SThierry Reding core0 { 3238a12cf5c3SThierry Reding cpu = <&cpu1_0>; 3239a12cf5c3SThierry Reding }; 3240a12cf5c3SThierry Reding 3241a12cf5c3SThierry Reding core1 { 3242a12cf5c3SThierry Reding cpu = <&cpu1_1>; 3243a12cf5c3SThierry Reding }; 3244a12cf5c3SThierry Reding 3245a12cf5c3SThierry Reding core2 { 3246a12cf5c3SThierry Reding cpu = <&cpu1_2>; 3247a12cf5c3SThierry Reding }; 3248a12cf5c3SThierry Reding 3249a12cf5c3SThierry Reding core3 { 3250a12cf5c3SThierry Reding cpu = <&cpu1_3>; 3251a12cf5c3SThierry Reding }; 3252a12cf5c3SThierry Reding }; 3253a12cf5c3SThierry Reding 3254a12cf5c3SThierry Reding cluster2 { 3255a12cf5c3SThierry Reding core0 { 3256a12cf5c3SThierry Reding cpu = <&cpu2_0>; 3257a12cf5c3SThierry Reding }; 3258a12cf5c3SThierry Reding 3259a12cf5c3SThierry Reding core1 { 3260a12cf5c3SThierry Reding cpu = <&cpu2_1>; 3261a12cf5c3SThierry Reding }; 3262a12cf5c3SThierry Reding 3263a12cf5c3SThierry Reding core2 { 3264a12cf5c3SThierry Reding cpu = <&cpu2_2>; 3265a12cf5c3SThierry Reding }; 3266a12cf5c3SThierry Reding 3267a12cf5c3SThierry Reding core3 { 3268a12cf5c3SThierry Reding cpu = <&cpu2_3>; 3269a12cf5c3SThierry Reding }; 3270a12cf5c3SThierry Reding }; 3271a12cf5c3SThierry Reding }; 3272a12cf5c3SThierry Reding 3273a12cf5c3SThierry Reding l2c0_0: l2-cache00 { 327427f1568bSPierre Gondois compatible = "cache"; 3275a12cf5c3SThierry Reding cache-size = <262144>; 3276a12cf5c3SThierry Reding cache-line-size = <64>; 3277a12cf5c3SThierry Reding cache-sets = <512>; 3278a12cf5c3SThierry Reding cache-unified; 327927f1568bSPierre Gondois cache-level = <2>; 3280a12cf5c3SThierry Reding next-level-cache = <&l3c0>; 3281a12cf5c3SThierry Reding }; 3282a12cf5c3SThierry Reding 3283a12cf5c3SThierry Reding l2c0_1: l2-cache01 { 328427f1568bSPierre Gondois compatible = "cache"; 3285a12cf5c3SThierry Reding cache-size = <262144>; 3286a12cf5c3SThierry Reding cache-line-size = <64>; 3287a12cf5c3SThierry Reding cache-sets = <512>; 3288a12cf5c3SThierry Reding cache-unified; 328927f1568bSPierre Gondois cache-level = <2>; 3290a12cf5c3SThierry Reding next-level-cache = <&l3c0>; 3291a12cf5c3SThierry Reding }; 3292a12cf5c3SThierry Reding 3293a12cf5c3SThierry Reding l2c0_2: l2-cache02 { 329427f1568bSPierre Gondois compatible = "cache"; 3295a12cf5c3SThierry Reding cache-size = <262144>; 3296a12cf5c3SThierry Reding cache-line-size = <64>; 3297a12cf5c3SThierry Reding cache-sets = <512>; 3298a12cf5c3SThierry Reding cache-unified; 329927f1568bSPierre Gondois cache-level = <2>; 3300a12cf5c3SThierry Reding next-level-cache = <&l3c0>; 3301a12cf5c3SThierry Reding }; 3302a12cf5c3SThierry Reding 3303a12cf5c3SThierry Reding l2c0_3: l2-cache03 { 330427f1568bSPierre Gondois compatible = "cache"; 3305a12cf5c3SThierry Reding cache-size = <262144>; 3306a12cf5c3SThierry Reding cache-line-size = <64>; 3307a12cf5c3SThierry Reding cache-sets = <512>; 3308a12cf5c3SThierry Reding cache-unified; 330927f1568bSPierre Gondois cache-level = <2>; 3310a12cf5c3SThierry Reding next-level-cache = <&l3c0>; 3311a12cf5c3SThierry Reding }; 3312a12cf5c3SThierry Reding 3313a12cf5c3SThierry Reding l2c1_0: l2-cache10 { 331427f1568bSPierre Gondois compatible = "cache"; 3315a12cf5c3SThierry Reding cache-size = <262144>; 3316a12cf5c3SThierry Reding cache-line-size = <64>; 3317a12cf5c3SThierry Reding cache-sets = <512>; 3318a12cf5c3SThierry Reding cache-unified; 331927f1568bSPierre Gondois cache-level = <2>; 3320a12cf5c3SThierry Reding next-level-cache = <&l3c1>; 3321a12cf5c3SThierry Reding }; 3322a12cf5c3SThierry Reding 3323a12cf5c3SThierry Reding l2c1_1: l2-cache11 { 332427f1568bSPierre Gondois compatible = "cache"; 3325a12cf5c3SThierry Reding cache-size = <262144>; 3326a12cf5c3SThierry Reding cache-line-size = <64>; 3327a12cf5c3SThierry Reding cache-sets = <512>; 3328a12cf5c3SThierry Reding cache-unified; 332927f1568bSPierre Gondois cache-level = <2>; 3330a12cf5c3SThierry Reding next-level-cache = <&l3c1>; 3331a12cf5c3SThierry Reding }; 3332a12cf5c3SThierry Reding 3333a12cf5c3SThierry Reding l2c1_2: l2-cache12 { 333427f1568bSPierre Gondois compatible = "cache"; 3335a12cf5c3SThierry Reding cache-size = <262144>; 3336a12cf5c3SThierry Reding cache-line-size = <64>; 3337a12cf5c3SThierry Reding cache-sets = <512>; 3338a12cf5c3SThierry Reding cache-unified; 333927f1568bSPierre Gondois cache-level = <2>; 3340a12cf5c3SThierry Reding next-level-cache = <&l3c1>; 3341a12cf5c3SThierry Reding }; 3342a12cf5c3SThierry Reding 3343a12cf5c3SThierry Reding l2c1_3: l2-cache13 { 334427f1568bSPierre Gondois compatible = "cache"; 3345a12cf5c3SThierry Reding cache-size = <262144>; 3346a12cf5c3SThierry Reding cache-line-size = <64>; 3347a12cf5c3SThierry Reding cache-sets = <512>; 3348a12cf5c3SThierry Reding cache-unified; 334927f1568bSPierre Gondois cache-level = <2>; 3350a12cf5c3SThierry Reding next-level-cache = <&l3c1>; 3351a12cf5c3SThierry Reding }; 3352a12cf5c3SThierry Reding 3353a12cf5c3SThierry Reding l2c2_0: l2-cache20 { 335427f1568bSPierre Gondois compatible = "cache"; 3355a12cf5c3SThierry Reding cache-size = <262144>; 3356a12cf5c3SThierry Reding cache-line-size = <64>; 3357a12cf5c3SThierry Reding cache-sets = <512>; 3358a12cf5c3SThierry Reding cache-unified; 335927f1568bSPierre Gondois cache-level = <2>; 3360a12cf5c3SThierry Reding next-level-cache = <&l3c2>; 3361a12cf5c3SThierry Reding }; 3362a12cf5c3SThierry Reding 3363a12cf5c3SThierry Reding l2c2_1: l2-cache21 { 336427f1568bSPierre Gondois compatible = "cache"; 3365a12cf5c3SThierry Reding cache-size = <262144>; 3366a12cf5c3SThierry Reding cache-line-size = <64>; 3367a12cf5c3SThierry Reding cache-sets = <512>; 3368a12cf5c3SThierry Reding cache-unified; 336927f1568bSPierre Gondois cache-level = <2>; 3370a12cf5c3SThierry Reding next-level-cache = <&l3c2>; 3371a12cf5c3SThierry Reding }; 3372a12cf5c3SThierry Reding 3373a12cf5c3SThierry Reding l2c2_2: l2-cache22 { 337427f1568bSPierre Gondois compatible = "cache"; 3375a12cf5c3SThierry Reding cache-size = <262144>; 3376a12cf5c3SThierry Reding cache-line-size = <64>; 3377a12cf5c3SThierry Reding cache-sets = <512>; 3378a12cf5c3SThierry Reding cache-unified; 337927f1568bSPierre Gondois cache-level = <2>; 3380a12cf5c3SThierry Reding next-level-cache = <&l3c2>; 3381a12cf5c3SThierry Reding }; 3382a12cf5c3SThierry Reding 3383a12cf5c3SThierry Reding l2c2_3: l2-cache23 { 338427f1568bSPierre Gondois compatible = "cache"; 3385a12cf5c3SThierry Reding cache-size = <262144>; 3386a12cf5c3SThierry Reding cache-line-size = <64>; 3387a12cf5c3SThierry Reding cache-sets = <512>; 3388a12cf5c3SThierry Reding cache-unified; 338927f1568bSPierre Gondois cache-level = <2>; 3390a12cf5c3SThierry Reding next-level-cache = <&l3c2>; 3391a12cf5c3SThierry Reding }; 3392a12cf5c3SThierry Reding 3393a12cf5c3SThierry Reding l3c0: l3-cache0 { 339427f1568bSPierre Gondois compatible = "cache"; 339527f1568bSPierre Gondois cache-unified; 3396a12cf5c3SThierry Reding cache-size = <2097152>; 3397a12cf5c3SThierry Reding cache-line-size = <64>; 3398a12cf5c3SThierry Reding cache-sets = <2048>; 339927f1568bSPierre Gondois cache-level = <3>; 3400a12cf5c3SThierry Reding }; 3401a12cf5c3SThierry Reding 3402a12cf5c3SThierry Reding l3c1: l3-cache1 { 340327f1568bSPierre Gondois compatible = "cache"; 340427f1568bSPierre Gondois cache-unified; 3405a12cf5c3SThierry Reding cache-size = <2097152>; 3406a12cf5c3SThierry Reding cache-line-size = <64>; 3407a12cf5c3SThierry Reding cache-sets = <2048>; 340827f1568bSPierre Gondois cache-level = <3>; 3409a12cf5c3SThierry Reding }; 3410a12cf5c3SThierry Reding 3411a12cf5c3SThierry Reding l3c2: l3-cache2 { 341227f1568bSPierre Gondois compatible = "cache"; 341327f1568bSPierre Gondois cache-unified; 3414a12cf5c3SThierry Reding cache-size = <2097152>; 3415a12cf5c3SThierry Reding cache-line-size = <64>; 3416a12cf5c3SThierry Reding cache-sets = <2048>; 341727f1568bSPierre Gondois cache-level = <3>; 3418a12cf5c3SThierry Reding }; 3419a12cf5c3SThierry Reding }; 3420a12cf5c3SThierry Reding 3421a12cf5c3SThierry Reding pmu { 3422a12cf5c3SThierry Reding compatible = "arm,cortex-a78-pmu"; 3423a12cf5c3SThierry Reding interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 3424a12cf5c3SThierry Reding status = "okay"; 342563944891SThierry Reding }; 342663944891SThierry Reding 342763944891SThierry Reding psci { 342863944891SThierry Reding compatible = "arm,psci-1.0"; 342963944891SThierry Reding status = "okay"; 343063944891SThierry Reding method = "smc"; 343163944891SThierry Reding }; 343263944891SThierry Reding 343306ad2ec4SMikko Perttunen tcu: serial { 343406ad2ec4SMikko Perttunen compatible = "nvidia,tegra234-tcu", "nvidia,tegra194-tcu"; 343506ad2ec4SMikko Perttunen mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 343606ad2ec4SMikko Perttunen <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 343706ad2ec4SMikko Perttunen mbox-names = "rx", "tx"; 343806ad2ec4SMikko Perttunen status = "disabled"; 343906ad2ec4SMikko Perttunen }; 344006ad2ec4SMikko Perttunen 344109614acdSSameer Pujar sound { 344209614acdSSameer Pujar status = "disabled"; 344309614acdSSameer Pujar 344409614acdSSameer Pujar clocks = <&bpmp TEGRA234_CLK_PLLA>, 344509614acdSSameer Pujar <&bpmp TEGRA234_CLK_PLLA_OUT0>; 344609614acdSSameer Pujar clock-names = "pll_a", "plla_out0"; 344709614acdSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_PLLA>, 344809614acdSSameer Pujar <&bpmp TEGRA234_CLK_PLLA_OUT0>, 344909614acdSSameer Pujar <&bpmp TEGRA234_CLK_AUD_MCLK>; 345009614acdSSameer Pujar assigned-clock-parents = <0>, 345109614acdSSameer Pujar <&bpmp TEGRA234_CLK_PLLA>, 345209614acdSSameer Pujar <&bpmp TEGRA234_CLK_PLLA_OUT0>; 345309614acdSSameer Pujar }; 345409614acdSSameer Pujar 345563944891SThierry Reding timer { 345663944891SThierry Reding compatible = "arm,armv8-timer"; 345763944891SThierry Reding interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 345863944891SThierry Reding <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 345963944891SThierry Reding <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 346063944891SThierry Reding <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 346163944891SThierry Reding interrupt-parent = <&gic>; 346263944891SThierry Reding always-on; 346363944891SThierry Reding }; 346463944891SThierry Reding}; 3465