163944891SThierry Reding// SPDX-License-Identifier: GPL-2.0 263944891SThierry Reding 363944891SThierry Reding#include <dt-bindings/clock/tegra234-clock.h> 4699349e0SThierry Reding#include <dt-bindings/gpio/tegra234-gpio.h> 563944891SThierry Reding#include <dt-bindings/interrupt-controller/arm-gic.h> 663944891SThierry Reding#include <dt-bindings/mailbox/tegra186-hsp.h> 7eed280dfSThierry Reding#include <dt-bindings/memory/tegra234-mc.h> 8c71e1897SThierry Reding#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 9dc94a94dSSameer Pujar#include <dt-bindings/power/tegra234-powergate.h> 1063944891SThierry Reding#include <dt-bindings/reset/tegra234-reset.h> 1163944891SThierry Reding 1263944891SThierry Reding/ { 1363944891SThierry Reding compatible = "nvidia,tegra234"; 1463944891SThierry Reding interrupt-parent = <&gic>; 1563944891SThierry Reding #address-cells = <2>; 1663944891SThierry Reding #size-cells = <2>; 1763944891SThierry Reding 1863944891SThierry Reding bus@0 { 1963944891SThierry Reding compatible = "simple-bus"; 2063944891SThierry Reding 21*2838cfddSThierry Reding #address-cells = <2>; 22*2838cfddSThierry Reding #size-cells = <2>; 23*2838cfddSThierry Reding ranges = <0x0 0x0 0x0 0x0 0x0 0x40000000>; 2463944891SThierry Reding 2560d2016aSAkhil R gpcdma: dma-controller@2600000 { 26f7b93a08SAkhil R compatible = "nvidia,tegra234-gpcdma", 2760d2016aSAkhil R "nvidia,tegra186-gpcdma"; 28*2838cfddSThierry Reding reg = <0x0 0x2600000 0x0 0x210000>; 2960d2016aSAkhil R resets = <&bpmp TEGRA234_RESET_GPCDMA>; 3060d2016aSAkhil R reset-names = "gpcdma"; 31dd0be827SAkhil R interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 32dd0be827SAkhil R <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 3360d2016aSAkhil R <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 3460d2016aSAkhil R <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 3560d2016aSAkhil R <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 3660d2016aSAkhil R <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 3760d2016aSAkhil R <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 3860d2016aSAkhil R <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 3960d2016aSAkhil R <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 4060d2016aSAkhil R <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 4160d2016aSAkhil R <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 4260d2016aSAkhil R <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 4360d2016aSAkhil R <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 4460d2016aSAkhil R <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 4560d2016aSAkhil R <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 4660d2016aSAkhil R <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 4760d2016aSAkhil R <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 4860d2016aSAkhil R <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 4960d2016aSAkhil R <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 5060d2016aSAkhil R <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 5160d2016aSAkhil R <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 5260d2016aSAkhil R <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 5360d2016aSAkhil R <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 5460d2016aSAkhil R <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 5560d2016aSAkhil R <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 5660d2016aSAkhil R <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 5760d2016aSAkhil R <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 5860d2016aSAkhil R <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 5960d2016aSAkhil R <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 6060d2016aSAkhil R <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 6160d2016aSAkhil R <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 6260d2016aSAkhil R <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 6360d2016aSAkhil R #dma-cells = <1>; 6460d2016aSAkhil R iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 65dd0be827SAkhil R dma-channel-mask = <0xfffffffe>; 6660d2016aSAkhil R dma-coherent; 6760d2016aSAkhil R }; 6860d2016aSAkhil R 69dc94a94dSSameer Pujar aconnect@2900000 { 70dc94a94dSSameer Pujar compatible = "nvidia,tegra234-aconnect", 71dc94a94dSSameer Pujar "nvidia,tegra210-aconnect"; 72dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_APE>, 73dc94a94dSSameer Pujar <&bpmp TEGRA234_CLK_APB2APE>; 74dc94a94dSSameer Pujar clock-names = "ape", "apb2ape"; 75dc94a94dSSameer Pujar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_AUD>; 76dc94a94dSSameer Pujar status = "disabled"; 77dc94a94dSSameer Pujar 78*2838cfddSThierry Reding #address-cells = <2>; 79*2838cfddSThierry Reding #size-cells = <2>; 80*2838cfddSThierry Reding ranges = <0x0 0x02900000 0x0 0x02900000 0x0 0x200000>; 81*2838cfddSThierry Reding 82dc94a94dSSameer Pujar tegra_ahub: ahub@2900800 { 83dc94a94dSSameer Pujar compatible = "nvidia,tegra234-ahub"; 84*2838cfddSThierry Reding reg = <0x0 0x02900800 0x0 0x800>; 85dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_AHUB>; 86dc94a94dSSameer Pujar clock-names = "ahub"; 87dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_AHUB>; 88dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 89dc94a94dSSameer Pujar status = "disabled"; 90dc94a94dSSameer Pujar 91*2838cfddSThierry Reding #address-cells = <2>; 92*2838cfddSThierry Reding #size-cells = <2>; 93*2838cfddSThierry Reding ranges = <0x0 0x02900800 0x0 0x02900800 0x0 0x11800>; 94*2838cfddSThierry Reding 95dc94a94dSSameer Pujar tegra_i2s1: i2s@2901000 { 96dc94a94dSSameer Pujar compatible = "nvidia,tegra234-i2s", 97dc94a94dSSameer Pujar "nvidia,tegra210-i2s"; 98*2838cfddSThierry Reding reg = <0x0 0x2901000 0x0 0x100>; 99dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_I2S1>, 100dc94a94dSSameer Pujar <&bpmp TEGRA234_CLK_I2S1_SYNC_INPUT>; 101dc94a94dSSameer Pujar clock-names = "i2s", "sync_input"; 102dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_I2S1>; 103dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 104dc94a94dSSameer Pujar assigned-clock-rates = <1536000>; 105dc94a94dSSameer Pujar sound-name-prefix = "I2S1"; 106dc94a94dSSameer Pujar status = "disabled"; 107dc94a94dSSameer Pujar }; 108dc94a94dSSameer Pujar 109dc94a94dSSameer Pujar tegra_i2s2: i2s@2901100 { 110dc94a94dSSameer Pujar compatible = "nvidia,tegra234-i2s", 111dc94a94dSSameer Pujar "nvidia,tegra210-i2s"; 112*2838cfddSThierry Reding reg = <0x0 0x2901100 0x0 0x100>; 113dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_I2S2>, 114dc94a94dSSameer Pujar <&bpmp TEGRA234_CLK_I2S2_SYNC_INPUT>; 115dc94a94dSSameer Pujar clock-names = "i2s", "sync_input"; 116dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_I2S2>; 117dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 118dc94a94dSSameer Pujar assigned-clock-rates = <1536000>; 119dc94a94dSSameer Pujar sound-name-prefix = "I2S2"; 120dc94a94dSSameer Pujar status = "disabled"; 121dc94a94dSSameer Pujar }; 122dc94a94dSSameer Pujar 123dc94a94dSSameer Pujar tegra_i2s3: i2s@2901200 { 124dc94a94dSSameer Pujar compatible = "nvidia,tegra234-i2s", 125dc94a94dSSameer Pujar "nvidia,tegra210-i2s"; 126*2838cfddSThierry Reding reg = <0x0 0x2901200 0x0 0x100>; 127dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_I2S3>, 128dc94a94dSSameer Pujar <&bpmp TEGRA234_CLK_I2S3_SYNC_INPUT>; 129dc94a94dSSameer Pujar clock-names = "i2s", "sync_input"; 130dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_I2S3>; 131dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 132dc94a94dSSameer Pujar assigned-clock-rates = <1536000>; 133dc94a94dSSameer Pujar sound-name-prefix = "I2S3"; 134dc94a94dSSameer Pujar status = "disabled"; 135dc94a94dSSameer Pujar }; 136dc94a94dSSameer Pujar 137dc94a94dSSameer Pujar tegra_i2s4: i2s@2901300 { 138dc94a94dSSameer Pujar compatible = "nvidia,tegra234-i2s", 139dc94a94dSSameer Pujar "nvidia,tegra210-i2s"; 140*2838cfddSThierry Reding reg = <0x0 0x2901300 0x0 0x100>; 141dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_I2S4>, 142dc94a94dSSameer Pujar <&bpmp TEGRA234_CLK_I2S4_SYNC_INPUT>; 143dc94a94dSSameer Pujar clock-names = "i2s", "sync_input"; 144dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_I2S4>; 145dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 146dc94a94dSSameer Pujar assigned-clock-rates = <1536000>; 147dc94a94dSSameer Pujar sound-name-prefix = "I2S4"; 148dc94a94dSSameer Pujar status = "disabled"; 149dc94a94dSSameer Pujar }; 150dc94a94dSSameer Pujar 151dc94a94dSSameer Pujar tegra_i2s5: i2s@2901400 { 152dc94a94dSSameer Pujar compatible = "nvidia,tegra234-i2s", 153dc94a94dSSameer Pujar "nvidia,tegra210-i2s"; 154*2838cfddSThierry Reding reg = <0x0 0x2901400 0x0 0x100>; 155dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_I2S5>, 156dc94a94dSSameer Pujar <&bpmp TEGRA234_CLK_I2S5_SYNC_INPUT>; 157dc94a94dSSameer Pujar clock-names = "i2s", "sync_input"; 158dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_I2S5>; 159dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 160dc94a94dSSameer Pujar assigned-clock-rates = <1536000>; 161dc94a94dSSameer Pujar sound-name-prefix = "I2S5"; 162dc94a94dSSameer Pujar status = "disabled"; 163dc94a94dSSameer Pujar }; 164dc94a94dSSameer Pujar 165dc94a94dSSameer Pujar tegra_i2s6: i2s@2901500 { 166dc94a94dSSameer Pujar compatible = "nvidia,tegra234-i2s", 167dc94a94dSSameer Pujar "nvidia,tegra210-i2s"; 168*2838cfddSThierry Reding reg = <0x0 0x2901500 0x0 0x100>; 169dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_I2S6>, 170dc94a94dSSameer Pujar <&bpmp TEGRA234_CLK_I2S6_SYNC_INPUT>; 171dc94a94dSSameer Pujar clock-names = "i2s", "sync_input"; 172dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_I2S6>; 173dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 174dc94a94dSSameer Pujar assigned-clock-rates = <1536000>; 175dc94a94dSSameer Pujar sound-name-prefix = "I2S6"; 176dc94a94dSSameer Pujar status = "disabled"; 177dc94a94dSSameer Pujar }; 178dc94a94dSSameer Pujar 179dc94a94dSSameer Pujar tegra_sfc1: sfc@2902000 { 180dc94a94dSSameer Pujar compatible = "nvidia,tegra234-sfc", 181dc94a94dSSameer Pujar "nvidia,tegra210-sfc"; 182*2838cfddSThierry Reding reg = <0x0 0x2902000 0x0 0x200>; 183dc94a94dSSameer Pujar sound-name-prefix = "SFC1"; 184dc94a94dSSameer Pujar status = "disabled"; 185dc94a94dSSameer Pujar }; 186dc94a94dSSameer Pujar 187dc94a94dSSameer Pujar tegra_sfc2: sfc@2902200 { 188dc94a94dSSameer Pujar compatible = "nvidia,tegra234-sfc", 189dc94a94dSSameer Pujar "nvidia,tegra210-sfc"; 190*2838cfddSThierry Reding reg = <0x0 0x2902200 0x0 0x200>; 191dc94a94dSSameer Pujar sound-name-prefix = "SFC2"; 192dc94a94dSSameer Pujar status = "disabled"; 193dc94a94dSSameer Pujar }; 194dc94a94dSSameer Pujar 195dc94a94dSSameer Pujar tegra_sfc3: sfc@2902400 { 196dc94a94dSSameer Pujar compatible = "nvidia,tegra234-sfc", 197dc94a94dSSameer Pujar "nvidia,tegra210-sfc"; 198*2838cfddSThierry Reding reg = <0x0 0x2902400 0x0 0x200>; 199dc94a94dSSameer Pujar sound-name-prefix = "SFC3"; 200dc94a94dSSameer Pujar status = "disabled"; 201dc94a94dSSameer Pujar }; 202dc94a94dSSameer Pujar 203dc94a94dSSameer Pujar tegra_sfc4: sfc@2902600 { 204dc94a94dSSameer Pujar compatible = "nvidia,tegra234-sfc", 205dc94a94dSSameer Pujar "nvidia,tegra210-sfc"; 206*2838cfddSThierry Reding reg = <0x0 0x2902600 0x0 0x200>; 207dc94a94dSSameer Pujar sound-name-prefix = "SFC4"; 208dc94a94dSSameer Pujar status = "disabled"; 209dc94a94dSSameer Pujar }; 210dc94a94dSSameer Pujar 211dc94a94dSSameer Pujar tegra_amx1: amx@2903000 { 212dc94a94dSSameer Pujar compatible = "nvidia,tegra234-amx", 213dc94a94dSSameer Pujar "nvidia,tegra194-amx"; 214*2838cfddSThierry Reding reg = <0x0 0x2903000 0x0 0x100>; 215dc94a94dSSameer Pujar sound-name-prefix = "AMX1"; 216dc94a94dSSameer Pujar status = "disabled"; 217dc94a94dSSameer Pujar }; 218dc94a94dSSameer Pujar 219dc94a94dSSameer Pujar tegra_amx2: amx@2903100 { 220dc94a94dSSameer Pujar compatible = "nvidia,tegra234-amx", 221dc94a94dSSameer Pujar "nvidia,tegra194-amx"; 222*2838cfddSThierry Reding reg = <0x0 0x2903100 0x0 0x100>; 223dc94a94dSSameer Pujar sound-name-prefix = "AMX2"; 224dc94a94dSSameer Pujar status = "disabled"; 225dc94a94dSSameer Pujar }; 226dc94a94dSSameer Pujar 227dc94a94dSSameer Pujar tegra_amx3: amx@2903200 { 228dc94a94dSSameer Pujar compatible = "nvidia,tegra234-amx", 229dc94a94dSSameer Pujar "nvidia,tegra194-amx"; 230*2838cfddSThierry Reding reg = <0x0 0x2903200 0x0 0x100>; 231dc94a94dSSameer Pujar sound-name-prefix = "AMX3"; 232dc94a94dSSameer Pujar status = "disabled"; 233dc94a94dSSameer Pujar }; 234dc94a94dSSameer Pujar 235dc94a94dSSameer Pujar tegra_amx4: amx@2903300 { 236dc94a94dSSameer Pujar compatible = "nvidia,tegra234-amx", 237dc94a94dSSameer Pujar "nvidia,tegra194-amx"; 238*2838cfddSThierry Reding reg = <0x0 0x2903300 0x0 0x100>; 239dc94a94dSSameer Pujar sound-name-prefix = "AMX4"; 240dc94a94dSSameer Pujar status = "disabled"; 241dc94a94dSSameer Pujar }; 242dc94a94dSSameer Pujar 243dc94a94dSSameer Pujar tegra_adx1: adx@2903800 { 244dc94a94dSSameer Pujar compatible = "nvidia,tegra234-adx", 245dc94a94dSSameer Pujar "nvidia,tegra210-adx"; 246*2838cfddSThierry Reding reg = <0x0 0x2903800 0x0 0x100>; 247dc94a94dSSameer Pujar sound-name-prefix = "ADX1"; 248dc94a94dSSameer Pujar status = "disabled"; 249dc94a94dSSameer Pujar }; 250dc94a94dSSameer Pujar 251dc94a94dSSameer Pujar tegra_adx2: adx@2903900 { 252dc94a94dSSameer Pujar compatible = "nvidia,tegra234-adx", 253dc94a94dSSameer Pujar "nvidia,tegra210-adx"; 254*2838cfddSThierry Reding reg = <0x0 0x2903900 0x0 0x100>; 255dc94a94dSSameer Pujar sound-name-prefix = "ADX2"; 256dc94a94dSSameer Pujar status = "disabled"; 257dc94a94dSSameer Pujar }; 258dc94a94dSSameer Pujar 259dc94a94dSSameer Pujar tegra_adx3: adx@2903a00 { 260dc94a94dSSameer Pujar compatible = "nvidia,tegra234-adx", 261dc94a94dSSameer Pujar "nvidia,tegra210-adx"; 262*2838cfddSThierry Reding reg = <0x0 0x2903a00 0x0 0x100>; 263dc94a94dSSameer Pujar sound-name-prefix = "ADX3"; 264dc94a94dSSameer Pujar status = "disabled"; 265dc94a94dSSameer Pujar }; 266dc94a94dSSameer Pujar 267dc94a94dSSameer Pujar tegra_adx4: adx@2903b00 { 268dc94a94dSSameer Pujar compatible = "nvidia,tegra234-adx", 269dc94a94dSSameer Pujar "nvidia,tegra210-adx"; 270*2838cfddSThierry Reding reg = <0x0 0x2903b00 0x0 0x100>; 271dc94a94dSSameer Pujar sound-name-prefix = "ADX4"; 272dc94a94dSSameer Pujar status = "disabled"; 273dc94a94dSSameer Pujar }; 274dc94a94dSSameer Pujar 275dc94a94dSSameer Pujar 276dc94a94dSSameer Pujar tegra_dmic1: dmic@2904000 { 277dc94a94dSSameer Pujar compatible = "nvidia,tegra234-dmic", 278dc94a94dSSameer Pujar "nvidia,tegra210-dmic"; 279*2838cfddSThierry Reding reg = <0x0 0x2904000 0x0 0x100>; 280dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_DMIC1>; 281dc94a94dSSameer Pujar clock-names = "dmic"; 282dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_DMIC1>; 283dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 284dc94a94dSSameer Pujar assigned-clock-rates = <3072000>; 285dc94a94dSSameer Pujar sound-name-prefix = "DMIC1"; 286dc94a94dSSameer Pujar status = "disabled"; 287dc94a94dSSameer Pujar }; 288dc94a94dSSameer Pujar 289dc94a94dSSameer Pujar tegra_dmic2: dmic@2904100 { 290dc94a94dSSameer Pujar compatible = "nvidia,tegra234-dmic", 291dc94a94dSSameer Pujar "nvidia,tegra210-dmic"; 292*2838cfddSThierry Reding reg = <0x0 0x2904100 0x0 0x100>; 293dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_DMIC2>; 294dc94a94dSSameer Pujar clock-names = "dmic"; 295dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_DMIC2>; 296dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 297dc94a94dSSameer Pujar assigned-clock-rates = <3072000>; 298dc94a94dSSameer Pujar sound-name-prefix = "DMIC2"; 299dc94a94dSSameer Pujar status = "disabled"; 300dc94a94dSSameer Pujar }; 301dc94a94dSSameer Pujar 302dc94a94dSSameer Pujar tegra_dmic3: dmic@2904200 { 303dc94a94dSSameer Pujar compatible = "nvidia,tegra234-dmic", 304dc94a94dSSameer Pujar "nvidia,tegra210-dmic"; 305*2838cfddSThierry Reding reg = <0x0 0x2904200 0x0 0x100>; 306dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_DMIC3>; 307dc94a94dSSameer Pujar clock-names = "dmic"; 308dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_DMIC3>; 309dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 310dc94a94dSSameer Pujar assigned-clock-rates = <3072000>; 311dc94a94dSSameer Pujar sound-name-prefix = "DMIC3"; 312dc94a94dSSameer Pujar status = "disabled"; 313dc94a94dSSameer Pujar }; 314dc94a94dSSameer Pujar 315dc94a94dSSameer Pujar tegra_dmic4: dmic@2904300 { 316dc94a94dSSameer Pujar compatible = "nvidia,tegra234-dmic", 317dc94a94dSSameer Pujar "nvidia,tegra210-dmic"; 318*2838cfddSThierry Reding reg = <0x0 0x2904300 0x0 0x100>; 319dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_DMIC4>; 320dc94a94dSSameer Pujar clock-names = "dmic"; 321dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_DMIC4>; 322dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 323dc94a94dSSameer Pujar assigned-clock-rates = <3072000>; 324dc94a94dSSameer Pujar sound-name-prefix = "DMIC4"; 325dc94a94dSSameer Pujar status = "disabled"; 326dc94a94dSSameer Pujar }; 327dc94a94dSSameer Pujar 328dc94a94dSSameer Pujar tegra_dspk1: dspk@2905000 { 329dc94a94dSSameer Pujar compatible = "nvidia,tegra234-dspk", 330dc94a94dSSameer Pujar "nvidia,tegra186-dspk"; 331*2838cfddSThierry Reding reg = <0x0 0x2905000 0x0 0x100>; 332dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_DSPK1>; 333dc94a94dSSameer Pujar clock-names = "dspk"; 334dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_DSPK1>; 335dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 336dc94a94dSSameer Pujar assigned-clock-rates = <12288000>; 337dc94a94dSSameer Pujar sound-name-prefix = "DSPK1"; 338dc94a94dSSameer Pujar status = "disabled"; 339dc94a94dSSameer Pujar }; 340dc94a94dSSameer Pujar 341dc94a94dSSameer Pujar tegra_dspk2: dspk@2905100 { 342dc94a94dSSameer Pujar compatible = "nvidia,tegra234-dspk", 343dc94a94dSSameer Pujar "nvidia,tegra186-dspk"; 344*2838cfddSThierry Reding reg = <0x0 0x2905100 0x0 0x100>; 345dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_DSPK2>; 346dc94a94dSSameer Pujar clock-names = "dspk"; 347dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_DSPK2>; 348dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 349dc94a94dSSameer Pujar assigned-clock-rates = <12288000>; 350dc94a94dSSameer Pujar sound-name-prefix = "DSPK2"; 351dc94a94dSSameer Pujar status = "disabled"; 352dc94a94dSSameer Pujar }; 353dc94a94dSSameer Pujar 3544b6a1b7cSSameer Pujar tegra_ope1: processing-engine@2908000 { 3554b6a1b7cSSameer Pujar compatible = "nvidia,tegra234-ope", 3564b6a1b7cSSameer Pujar "nvidia,tegra210-ope"; 357*2838cfddSThierry Reding reg = <0x0 0x2908000 0x0 0x100>; 3584b6a1b7cSSameer Pujar sound-name-prefix = "OPE1"; 3594b6a1b7cSSameer Pujar status = "disabled"; 3604b6a1b7cSSameer Pujar 361*2838cfddSThierry Reding #address-cells = <2>; 362*2838cfddSThierry Reding #size-cells = <2>; 363*2838cfddSThierry Reding ranges; 364*2838cfddSThierry Reding 3654b6a1b7cSSameer Pujar equalizer@2908100 { 3664b6a1b7cSSameer Pujar compatible = "nvidia,tegra234-peq", 3674b6a1b7cSSameer Pujar "nvidia,tegra210-peq"; 368*2838cfddSThierry Reding reg = <0x0 0x2908100 0x0 0x100>; 3694b6a1b7cSSameer Pujar }; 3704b6a1b7cSSameer Pujar 3714b6a1b7cSSameer Pujar dynamic-range-compressor@2908200 { 3724b6a1b7cSSameer Pujar compatible = "nvidia,tegra234-mbdrc", 3734b6a1b7cSSameer Pujar "nvidia,tegra210-mbdrc"; 374*2838cfddSThierry Reding reg = <0x0 0x2908200 0x0 0x200>; 3754b6a1b7cSSameer Pujar }; 3764b6a1b7cSSameer Pujar }; 3774b6a1b7cSSameer Pujar 378dc94a94dSSameer Pujar tegra_mvc1: mvc@290a000 { 379dc94a94dSSameer Pujar compatible = "nvidia,tegra234-mvc", 380dc94a94dSSameer Pujar "nvidia,tegra210-mvc"; 381*2838cfddSThierry Reding reg = <0x0 0x290a000 0x0 0x200>; 382dc94a94dSSameer Pujar sound-name-prefix = "MVC1"; 383dc94a94dSSameer Pujar status = "disabled"; 384dc94a94dSSameer Pujar }; 385dc94a94dSSameer Pujar 386dc94a94dSSameer Pujar tegra_mvc2: mvc@290a200 { 387dc94a94dSSameer Pujar compatible = "nvidia,tegra234-mvc", 388dc94a94dSSameer Pujar "nvidia,tegra210-mvc"; 389*2838cfddSThierry Reding reg = <0x0 0x290a200 0x0 0x200>; 390dc94a94dSSameer Pujar sound-name-prefix = "MVC2"; 391dc94a94dSSameer Pujar status = "disabled"; 392dc94a94dSSameer Pujar }; 393dc94a94dSSameer Pujar 394dc94a94dSSameer Pujar tegra_amixer: amixer@290bb00 { 395dc94a94dSSameer Pujar compatible = "nvidia,tegra234-amixer", 396dc94a94dSSameer Pujar "nvidia,tegra210-amixer"; 397*2838cfddSThierry Reding reg = <0x0 0x290bb00 0x0 0x800>; 398dc94a94dSSameer Pujar sound-name-prefix = "MIXER1"; 399dc94a94dSSameer Pujar status = "disabled"; 400dc94a94dSSameer Pujar }; 401dc94a94dSSameer Pujar 402dc94a94dSSameer Pujar tegra_admaif: admaif@290f000 { 403dc94a94dSSameer Pujar compatible = "nvidia,tegra234-admaif", 404dc94a94dSSameer Pujar "nvidia,tegra186-admaif"; 405*2838cfddSThierry Reding reg = <0x0 0x0290f000 0x0 0x1000>; 406dc94a94dSSameer Pujar dmas = <&adma 1>, <&adma 1>, 407dc94a94dSSameer Pujar <&adma 2>, <&adma 2>, 408dc94a94dSSameer Pujar <&adma 3>, <&adma 3>, 409dc94a94dSSameer Pujar <&adma 4>, <&adma 4>, 410dc94a94dSSameer Pujar <&adma 5>, <&adma 5>, 411dc94a94dSSameer Pujar <&adma 6>, <&adma 6>, 412dc94a94dSSameer Pujar <&adma 7>, <&adma 7>, 413dc94a94dSSameer Pujar <&adma 8>, <&adma 8>, 414dc94a94dSSameer Pujar <&adma 9>, <&adma 9>, 415dc94a94dSSameer Pujar <&adma 10>, <&adma 10>, 416dc94a94dSSameer Pujar <&adma 11>, <&adma 11>, 417dc94a94dSSameer Pujar <&adma 12>, <&adma 12>, 418dc94a94dSSameer Pujar <&adma 13>, <&adma 13>, 419dc94a94dSSameer Pujar <&adma 14>, <&adma 14>, 420dc94a94dSSameer Pujar <&adma 15>, <&adma 15>, 421dc94a94dSSameer Pujar <&adma 16>, <&adma 16>, 422dc94a94dSSameer Pujar <&adma 17>, <&adma 17>, 423dc94a94dSSameer Pujar <&adma 18>, <&adma 18>, 424dc94a94dSSameer Pujar <&adma 19>, <&adma 19>, 425dc94a94dSSameer Pujar <&adma 20>, <&adma 20>; 426dc94a94dSSameer Pujar dma-names = "rx1", "tx1", 427dc94a94dSSameer Pujar "rx2", "tx2", 428dc94a94dSSameer Pujar "rx3", "tx3", 429dc94a94dSSameer Pujar "rx4", "tx4", 430dc94a94dSSameer Pujar "rx5", "tx5", 431dc94a94dSSameer Pujar "rx6", "tx6", 432dc94a94dSSameer Pujar "rx7", "tx7", 433dc94a94dSSameer Pujar "rx8", "tx8", 434dc94a94dSSameer Pujar "rx9", "tx9", 435dc94a94dSSameer Pujar "rx10", "tx10", 436dc94a94dSSameer Pujar "rx11", "tx11", 437dc94a94dSSameer Pujar "rx12", "tx12", 438dc94a94dSSameer Pujar "rx13", "tx13", 439dc94a94dSSameer Pujar "rx14", "tx14", 440dc94a94dSSameer Pujar "rx15", "tx15", 441dc94a94dSSameer Pujar "rx16", "tx16", 442dc94a94dSSameer Pujar "rx17", "tx17", 443dc94a94dSSameer Pujar "rx18", "tx18", 444dc94a94dSSameer Pujar "rx19", "tx19", 445dc94a94dSSameer Pujar "rx20", "tx20"; 446dc94a94dSSameer Pujar interconnects = <&mc TEGRA234_MEMORY_CLIENT_APEDMAR &emc>, 447dc94a94dSSameer Pujar <&mc TEGRA234_MEMORY_CLIENT_APEDMAW &emc>; 448dc94a94dSSameer Pujar interconnect-names = "dma-mem", "write"; 449dc94a94dSSameer Pujar iommus = <&smmu_niso0 TEGRA234_SID_APE>; 450dc94a94dSSameer Pujar status = "disabled"; 451dc94a94dSSameer Pujar }; 45247a08153SSameer Pujar 45347a08153SSameer Pujar tegra_asrc: asrc@2910000 { 45447a08153SSameer Pujar compatible = "nvidia,tegra234-asrc", 45547a08153SSameer Pujar "nvidia,tegra186-asrc"; 456*2838cfddSThierry Reding reg = <0x0 0x2910000 0x0 0x2000>; 45747a08153SSameer Pujar sound-name-prefix = "ASRC1"; 45847a08153SSameer Pujar status = "disabled"; 45947a08153SSameer Pujar }; 460dc94a94dSSameer Pujar }; 461dc94a94dSSameer Pujar 462dc94a94dSSameer Pujar adma: dma-controller@2930000 { 463dc94a94dSSameer Pujar compatible = "nvidia,tegra234-adma", 464dc94a94dSSameer Pujar "nvidia,tegra186-adma"; 465*2838cfddSThierry Reding reg = <0x0 0x02930000 0x0 0x20000>; 466dc94a94dSSameer Pujar interrupt-parent = <&agic>; 467dc94a94dSSameer Pujar interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 468dc94a94dSSameer Pujar <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 469dc94a94dSSameer Pujar <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 470dc94a94dSSameer Pujar <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 471dc94a94dSSameer Pujar <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 472dc94a94dSSameer Pujar <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 473dc94a94dSSameer Pujar <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 474dc94a94dSSameer Pujar <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 475dc94a94dSSameer Pujar <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 476dc94a94dSSameer Pujar <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 477dc94a94dSSameer Pujar <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 478dc94a94dSSameer Pujar <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 479dc94a94dSSameer Pujar <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 480dc94a94dSSameer Pujar <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 481dc94a94dSSameer Pujar <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 482dc94a94dSSameer Pujar <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 483dc94a94dSSameer Pujar <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 484dc94a94dSSameer Pujar <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 485dc94a94dSSameer Pujar <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 486dc94a94dSSameer Pujar <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 487dc94a94dSSameer Pujar <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 488dc94a94dSSameer Pujar <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 489dc94a94dSSameer Pujar <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 490dc94a94dSSameer Pujar <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 491dc94a94dSSameer Pujar <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 492dc94a94dSSameer Pujar <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 493dc94a94dSSameer Pujar <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 494dc94a94dSSameer Pujar <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 495dc94a94dSSameer Pujar <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 496dc94a94dSSameer Pujar <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 497dc94a94dSSameer Pujar <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 498dc94a94dSSameer Pujar <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 499dc94a94dSSameer Pujar #dma-cells = <1>; 500dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_AHUB>; 501dc94a94dSSameer Pujar clock-names = "d_audio"; 502dc94a94dSSameer Pujar status = "disabled"; 503dc94a94dSSameer Pujar }; 504dc94a94dSSameer Pujar 505dc94a94dSSameer Pujar agic: interrupt-controller@2a40000 { 506dc94a94dSSameer Pujar compatible = "nvidia,tegra234-agic", 507dc94a94dSSameer Pujar "nvidia,tegra210-agic"; 508dc94a94dSSameer Pujar #interrupt-cells = <3>; 509dc94a94dSSameer Pujar interrupt-controller; 510*2838cfddSThierry Reding reg = <0x0 0x02a41000 0x0 0x1000>, 511*2838cfddSThierry Reding <0x0 0x02a42000 0x0 0x2000>; 512dc94a94dSSameer Pujar interrupts = <GIC_SPI 145 513dc94a94dSSameer Pujar (GIC_CPU_MASK_SIMPLE(4) | 514dc94a94dSSameer Pujar IRQ_TYPE_LEVEL_HIGH)>; 515dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_APE>; 516dc94a94dSSameer Pujar clock-names = "clk"; 517dc94a94dSSameer Pujar status = "disabled"; 518dc94a94dSSameer Pujar }; 519dc94a94dSSameer Pujar }; 520dc94a94dSSameer Pujar 52163944891SThierry Reding misc@100000 { 52263944891SThierry Reding compatible = "nvidia,tegra234-misc"; 523*2838cfddSThierry Reding reg = <0x0 0x00100000 0x0 0xf000>, 524*2838cfddSThierry Reding <0x0 0x0010f000 0x0 0x1000>; 52563944891SThierry Reding status = "okay"; 52663944891SThierry Reding }; 52763944891SThierry Reding 52828d860edSKartik timer@2080000 { 52928d860edSKartik compatible = "nvidia,tegra234-timer"; 530*2838cfddSThierry Reding reg = <0x0 0x02080000 0x0 0x00121000>; 53128d860edSKartik interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 53228d860edSKartik <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 53328d860edSKartik <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 53428d860edSKartik <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 53528d860edSKartik <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 53628d860edSKartik <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 53728d860edSKartik <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 53828d860edSKartik <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 53928d860edSKartik <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 54028d860edSKartik <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 54128d860edSKartik <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 54228d860edSKartik <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 54328d860edSKartik <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 54428d860edSKartik <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 54528d860edSKartik <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 54628d860edSKartik <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 54728d860edSKartik status = "okay"; 54828d860edSKartik }; 54928d860edSKartik 5504bb39ca2SMikko Perttunen host1x@13e00000 { 5514bb39ca2SMikko Perttunen compatible = "nvidia,tegra234-host1x"; 552*2838cfddSThierry Reding reg = <0x0 0x13e00000 0x0 0x10000>, 553*2838cfddSThierry Reding <0x0 0x13e10000 0x0 0x10000>, 554*2838cfddSThierry Reding <0x0 0x13e40000 0x0 0x10000>; 5554bb39ca2SMikko Perttunen reg-names = "common", "hypervisor", "vm"; 5564bb39ca2SMikko Perttunen interrupts = <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, 5574bb39ca2SMikko Perttunen <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, 5584bb39ca2SMikko Perttunen <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, 5594bb39ca2SMikko Perttunen <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, 5604bb39ca2SMikko Perttunen <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, 5614bb39ca2SMikko Perttunen <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>, 5624bb39ca2SMikko Perttunen <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>, 5634bb39ca2SMikko Perttunen <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>, 5644bb39ca2SMikko Perttunen <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 5654bb39ca2SMikko Perttunen interrupt-names = "syncpt0", "syncpt1", "syncpt2", "syncpt3", "syncpt4", 5664bb39ca2SMikko Perttunen "syncpt5", "syncpt6", "syncpt7", "host1x"; 5674bb39ca2SMikko Perttunen clocks = <&bpmp TEGRA234_CLK_HOST1X>; 5684bb39ca2SMikko Perttunen clock-names = "host1x"; 5694bb39ca2SMikko Perttunen 570*2838cfddSThierry Reding #address-cells = <2>; 571*2838cfddSThierry Reding #size-cells = <2>; 572*2838cfddSThierry Reding ranges = <0x0 0x14800000 0x0 0x14800000 0x0 0x02000000>; 5734bb39ca2SMikko Perttunen 5744bb39ca2SMikko Perttunen interconnects = <&mc TEGRA234_MEMORY_CLIENT_HOST1XDMAR &emc>; 5754bb39ca2SMikko Perttunen interconnect-names = "dma-mem"; 5764bb39ca2SMikko Perttunen iommus = <&smmu_niso1 TEGRA234_SID_HOST1X>; 5774bb39ca2SMikko Perttunen 578b35f5b53SMikko Perttunen /* Context isolation domains */ 579b35f5b53SMikko Perttunen iommu-map = <0 &smmu_niso0 TEGRA234_SID_HOST1X_CTX0 1>, 580b35f5b53SMikko Perttunen <1 &smmu_niso0 TEGRA234_SID_HOST1X_CTX1 1>, 581b35f5b53SMikko Perttunen <2 &smmu_niso0 TEGRA234_SID_HOST1X_CTX2 1>, 582b35f5b53SMikko Perttunen <3 &smmu_niso0 TEGRA234_SID_HOST1X_CTX3 1>, 583b35f5b53SMikko Perttunen <4 &smmu_niso0 TEGRA234_SID_HOST1X_CTX4 1>, 584b35f5b53SMikko Perttunen <5 &smmu_niso0 TEGRA234_SID_HOST1X_CTX5 1>, 585b35f5b53SMikko Perttunen <6 &smmu_niso0 TEGRA234_SID_HOST1X_CTX6 1>, 586b35f5b53SMikko Perttunen <7 &smmu_niso0 TEGRA234_SID_HOST1X_CTX7 1>, 587b35f5b53SMikko Perttunen <8 &smmu_niso1 TEGRA234_SID_HOST1X_CTX0 1>, 588b35f5b53SMikko Perttunen <9 &smmu_niso1 TEGRA234_SID_HOST1X_CTX1 1>, 589b35f5b53SMikko Perttunen <10 &smmu_niso1 TEGRA234_SID_HOST1X_CTX2 1>, 590b35f5b53SMikko Perttunen <11 &smmu_niso1 TEGRA234_SID_HOST1X_CTX3 1>, 591b35f5b53SMikko Perttunen <12 &smmu_niso1 TEGRA234_SID_HOST1X_CTX4 1>, 592b35f5b53SMikko Perttunen <13 &smmu_niso1 TEGRA234_SID_HOST1X_CTX5 1>, 593b35f5b53SMikko Perttunen <14 &smmu_niso1 TEGRA234_SID_HOST1X_CTX6 1>, 594b35f5b53SMikko Perttunen <15 &smmu_niso1 TEGRA234_SID_HOST1X_CTX7 1>; 595b35f5b53SMikko Perttunen 5964bb39ca2SMikko Perttunen vic@15340000 { 5974bb39ca2SMikko Perttunen compatible = "nvidia,tegra234-vic"; 598*2838cfddSThierry Reding reg = <0x0 0x15340000 0x0 0x00040000>; 5994bb39ca2SMikko Perttunen interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 6004bb39ca2SMikko Perttunen clocks = <&bpmp TEGRA234_CLK_VIC>; 6014bb39ca2SMikko Perttunen clock-names = "vic"; 6024bb39ca2SMikko Perttunen resets = <&bpmp TEGRA234_RESET_VIC>; 6034bb39ca2SMikko Perttunen reset-names = "vic"; 6044bb39ca2SMikko Perttunen 6054bb39ca2SMikko Perttunen power-domains = <&bpmp TEGRA234_POWER_DOMAIN_VIC>; 6064bb39ca2SMikko Perttunen interconnects = <&mc TEGRA234_MEMORY_CLIENT_VICSRD &emc>, 6074bb39ca2SMikko Perttunen <&mc TEGRA234_MEMORY_CLIENT_VICSWR &emc>; 6084bb39ca2SMikko Perttunen interconnect-names = "dma-mem", "write"; 6094bb39ca2SMikko Perttunen iommus = <&smmu_niso1 TEGRA234_SID_VIC>; 6104bb39ca2SMikko Perttunen dma-coherent; 6114bb39ca2SMikko Perttunen }; 61268c31ad0SMikko Perttunen 61368c31ad0SMikko Perttunen nvdec@15480000 { 61468c31ad0SMikko Perttunen compatible = "nvidia,tegra234-nvdec"; 615*2838cfddSThierry Reding reg = <0x0 0x15480000 0x0 0x00040000>; 61668c31ad0SMikko Perttunen clocks = <&bpmp TEGRA234_CLK_NVDEC>, 61768c31ad0SMikko Perttunen <&bpmp TEGRA234_CLK_FUSE>, 61868c31ad0SMikko Perttunen <&bpmp TEGRA234_CLK_TSEC_PKA>; 61968c31ad0SMikko Perttunen clock-names = "nvdec", "fuse", "tsec_pka"; 62068c31ad0SMikko Perttunen resets = <&bpmp TEGRA234_RESET_NVDEC>; 62168c31ad0SMikko Perttunen reset-names = "nvdec"; 62268c31ad0SMikko Perttunen power-domains = <&bpmp TEGRA234_POWER_DOMAIN_NVDEC>; 62368c31ad0SMikko Perttunen interconnects = <&mc TEGRA234_MEMORY_CLIENT_NVDECSRD &emc>, 62468c31ad0SMikko Perttunen <&mc TEGRA234_MEMORY_CLIENT_NVDECSWR &emc>; 62568c31ad0SMikko Perttunen interconnect-names = "dma-mem", "write"; 62668c31ad0SMikko Perttunen iommus = <&smmu_niso1 TEGRA234_SID_NVDEC>; 62768c31ad0SMikko Perttunen dma-coherent; 62868c31ad0SMikko Perttunen 62968c31ad0SMikko Perttunen nvidia,memory-controller = <&mc>; 63068c31ad0SMikko Perttunen 63168c31ad0SMikko Perttunen /* 63268c31ad0SMikko Perttunen * Placeholder values that firmware needs to update with the real 63368c31ad0SMikko Perttunen * offsets parsed from the microcode headers. 63468c31ad0SMikko Perttunen */ 63568c31ad0SMikko Perttunen nvidia,bl-manifest-offset = <0>; 63668c31ad0SMikko Perttunen nvidia,bl-data-offset = <0>; 63768c31ad0SMikko Perttunen nvidia,bl-code-offset = <0>; 63868c31ad0SMikko Perttunen nvidia,os-manifest-offset = <0>; 63968c31ad0SMikko Perttunen nvidia,os-data-offset = <0>; 64068c31ad0SMikko Perttunen nvidia,os-code-offset = <0>; 64168c31ad0SMikko Perttunen 64268c31ad0SMikko Perttunen /* 64368c31ad0SMikko Perttunen * Firmware needs to set this to "okay" once the above values have 64468c31ad0SMikko Perttunen * been updated. 64568c31ad0SMikko Perttunen */ 64668c31ad0SMikko Perttunen status = "disabled"; 64768c31ad0SMikko Perttunen }; 6484bb39ca2SMikko Perttunen }; 6494bb39ca2SMikko Perttunen 650f0e12668SThierry Reding gpio: gpio@2200000 { 651f0e12668SThierry Reding compatible = "nvidia,tegra234-gpio"; 652f0e12668SThierry Reding reg-names = "security", "gpio"; 653*2838cfddSThierry Reding reg = <0x0 0x02200000 0x0 0x10000>, 654*2838cfddSThierry Reding <0x0 0x02210000 0x0 0x10000>; 655f0e12668SThierry Reding interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 656f0e12668SThierry Reding <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 657f0e12668SThierry Reding <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 658f0e12668SThierry Reding <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, 659f0e12668SThierry Reding <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 660f0e12668SThierry Reding <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 661f0e12668SThierry Reding <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 662f0e12668SThierry Reding <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 663f0e12668SThierry Reding <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 664f0e12668SThierry Reding <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 665f0e12668SThierry Reding <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 666f0e12668SThierry Reding <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 667f0e12668SThierry Reding <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 668f0e12668SThierry Reding <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 669f0e12668SThierry Reding <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 670f0e12668SThierry Reding <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 671f0e12668SThierry Reding <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 672f0e12668SThierry Reding <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 673f0e12668SThierry Reding <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 674f0e12668SThierry Reding <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 675f0e12668SThierry Reding <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 676f0e12668SThierry Reding <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 677f0e12668SThierry Reding <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 678f0e12668SThierry Reding <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 679f0e12668SThierry Reding <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 680f0e12668SThierry Reding <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 681f0e12668SThierry Reding <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 682f0e12668SThierry Reding <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 683f0e12668SThierry Reding <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 684f0e12668SThierry Reding <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 685f0e12668SThierry Reding <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 686f0e12668SThierry Reding <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 687f0e12668SThierry Reding <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 688f0e12668SThierry Reding <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 689f0e12668SThierry Reding <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 690f0e12668SThierry Reding <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 691f0e12668SThierry Reding <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 692f0e12668SThierry Reding <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 693f0e12668SThierry Reding <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 694f0e12668SThierry Reding <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 695f0e12668SThierry Reding <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 696f0e12668SThierry Reding <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 697f0e12668SThierry Reding <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 698f0e12668SThierry Reding <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 699f0e12668SThierry Reding <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 700f0e12668SThierry Reding <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 701f0e12668SThierry Reding <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 702f0e12668SThierry Reding <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 703f0e12668SThierry Reding #interrupt-cells = <2>; 704f0e12668SThierry Reding interrupt-controller; 705f0e12668SThierry Reding #gpio-cells = <2>; 706f0e12668SThierry Reding gpio-controller; 707f0e12668SThierry Reding }; 708f0e12668SThierry Reding 709eed280dfSThierry Reding mc: memory-controller@2c00000 { 710eed280dfSThierry Reding compatible = "nvidia,tegra234-mc"; 711*2838cfddSThierry Reding reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */ 712*2838cfddSThierry Reding <0x0 0x02c10000 0x0 0x10000>, /* MC Broadcast*/ 713*2838cfddSThierry Reding <0x0 0x02c20000 0x0 0x10000>, /* MC0 */ 714*2838cfddSThierry Reding <0x0 0x02c30000 0x0 0x10000>, /* MC1 */ 715*2838cfddSThierry Reding <0x0 0x02c40000 0x0 0x10000>, /* MC2 */ 716*2838cfddSThierry Reding <0x0 0x02c50000 0x0 0x10000>, /* MC3 */ 717*2838cfddSThierry Reding <0x0 0x02b80000 0x0 0x10000>, /* MC4 */ 718*2838cfddSThierry Reding <0x0 0x02b90000 0x0 0x10000>, /* MC5 */ 719*2838cfddSThierry Reding <0x0 0x02ba0000 0x0 0x10000>, /* MC6 */ 720*2838cfddSThierry Reding <0x0 0x02bb0000 0x0 0x10000>, /* MC7 */ 721*2838cfddSThierry Reding <0x0 0x01700000 0x0 0x10000>, /* MC8 */ 722*2838cfddSThierry Reding <0x0 0x01710000 0x0 0x10000>, /* MC9 */ 723*2838cfddSThierry Reding <0x0 0x01720000 0x0 0x10000>, /* MC10 */ 724*2838cfddSThierry Reding <0x0 0x01730000 0x0 0x10000>, /* MC11 */ 725*2838cfddSThierry Reding <0x0 0x01740000 0x0 0x10000>, /* MC12 */ 726*2838cfddSThierry Reding <0x0 0x01750000 0x0 0x10000>, /* MC13 */ 727*2838cfddSThierry Reding <0x0 0x01760000 0x0 0x10000>, /* MC14 */ 728*2838cfddSThierry Reding <0x0 0x01770000 0x0 0x10000>; /* MC15 */ 729000b99e5SAshish Mhetre reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3", 730000b99e5SAshish Mhetre "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", 731000b99e5SAshish Mhetre "ch11", "ch12", "ch13", "ch14", "ch15"; 732eed280dfSThierry Reding interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 733eed280dfSThierry Reding #interconnect-cells = <1>; 734eed280dfSThierry Reding status = "okay"; 735eed280dfSThierry Reding 736eed280dfSThierry Reding #address-cells = <2>; 737eed280dfSThierry Reding #size-cells = <2>; 738*2838cfddSThierry Reding ranges = <0x0 0x01700000 0x0 0x01700000 0x0 0x100000>, 739*2838cfddSThierry Reding <0x0 0x02b80000 0x0 0x02b80000 0x0 0x040000>, 740*2838cfddSThierry Reding <0x0 0x02c00000 0x0 0x02c00000 0x0 0x100000>; 741eed280dfSThierry Reding 742eed280dfSThierry Reding /* 743eed280dfSThierry Reding * Bit 39 of addresses passing through the memory 744eed280dfSThierry Reding * controller selects the XBAR format used when memory 745eed280dfSThierry Reding * is accessed. This is used to transparently access 746eed280dfSThierry Reding * memory in the XBAR format used by the discrete GPU 747eed280dfSThierry Reding * (bit 39 set) or Tegra (bit 39 clear). 748eed280dfSThierry Reding * 749eed280dfSThierry Reding * As a consequence, the operating system must ensure 750eed280dfSThierry Reding * that bit 39 is never used implicitly, for example 751eed280dfSThierry Reding * via an I/O virtual address mapping of an IOMMU. If 752eed280dfSThierry Reding * devices require access to the XBAR switch, their 753eed280dfSThierry Reding * drivers must set this bit explicitly. 754eed280dfSThierry Reding * 755eed280dfSThierry Reding * Limit the DMA range for memory clients to [38:0]. 756eed280dfSThierry Reding */ 757*2838cfddSThierry Reding dma-ranges = <0x0 0x0 0x0 0x0 0x80 0x0>; 758eed280dfSThierry Reding 759eed280dfSThierry Reding emc: external-memory-controller@2c60000 { 760eed280dfSThierry Reding compatible = "nvidia,tegra234-emc"; 761eed280dfSThierry Reding reg = <0x0 0x02c60000 0x0 0x90000>, 762eed280dfSThierry Reding <0x0 0x01780000 0x0 0x80000>; 763eed280dfSThierry Reding interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 764eed280dfSThierry Reding clocks = <&bpmp TEGRA234_CLK_EMC>; 765eed280dfSThierry Reding clock-names = "emc"; 766eed280dfSThierry Reding status = "okay"; 767eed280dfSThierry Reding 768eed280dfSThierry Reding #interconnect-cells = <0>; 769eed280dfSThierry Reding 770eed280dfSThierry Reding nvidia,bpmp = <&bpmp>; 771eed280dfSThierry Reding }; 772eed280dfSThierry Reding }; 773eed280dfSThierry Reding 77463944891SThierry Reding uarta: serial@3100000 { 77563944891SThierry Reding compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart"; 776*2838cfddSThierry Reding reg = <0x0 0x03100000 0x0 0x10000>; 77763944891SThierry Reding interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 77863944891SThierry Reding clocks = <&bpmp TEGRA234_CLK_UARTA>; 77963944891SThierry Reding clock-names = "serial"; 78063944891SThierry Reding resets = <&bpmp TEGRA234_RESET_UARTA>; 78163944891SThierry Reding reset-names = "serial"; 78263944891SThierry Reding status = "disabled"; 78363944891SThierry Reding }; 78463944891SThierry Reding 785156af9deSAkhil R gen1_i2c: i2c@3160000 { 786156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 787*2838cfddSThierry Reding reg = <0x0 0x3160000 0x0 0x100>; 788156af9deSAkhil R status = "disabled"; 789156af9deSAkhil R interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 790156af9deSAkhil R clock-frequency = <400000>; 791156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C1 792156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 793156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C1>; 794156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 795156af9deSAkhil R clock-names = "div-clk", "parent"; 796156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C1>; 797156af9deSAkhil R reset-names = "i2c"; 7988e442805SAkhil R iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 7998e442805SAkhil R dma-coherent; 8008e442805SAkhil R dmas = <&gpcdma 21>, <&gpcdma 21>; 8018e442805SAkhil R dma-names = "rx", "tx"; 802156af9deSAkhil R }; 803156af9deSAkhil R 804156af9deSAkhil R cam_i2c: i2c@3180000 { 805156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 806*2838cfddSThierry Reding reg = <0x0 0x3180000 0x0 0x100>; 807156af9deSAkhil R interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 808156af9deSAkhil R status = "disabled"; 809156af9deSAkhil R clock-frequency = <400000>; 810156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C3 811156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 812156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C3>; 813156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 814156af9deSAkhil R clock-names = "div-clk", "parent"; 815156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C3>; 816156af9deSAkhil R reset-names = "i2c"; 8178e442805SAkhil R iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 8188e442805SAkhil R dma-coherent; 8198e442805SAkhil R dmas = <&gpcdma 23>, <&gpcdma 23>; 8208e442805SAkhil R dma-names = "rx", "tx"; 821156af9deSAkhil R }; 822156af9deSAkhil R 823156af9deSAkhil R dp_aux_ch1_i2c: i2c@3190000 { 824156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 825*2838cfddSThierry Reding reg = <0x0 0x3190000 0x0 0x100>; 826156af9deSAkhil R interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 827156af9deSAkhil R status = "disabled"; 828156af9deSAkhil R clock-frequency = <100000>; 829156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C4 830156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 831156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C4>; 832156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 833156af9deSAkhil R clock-names = "div-clk", "parent"; 834156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C4>; 835156af9deSAkhil R reset-names = "i2c"; 8368e442805SAkhil R iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 8378e442805SAkhil R dma-coherent; 8388e442805SAkhil R dmas = <&gpcdma 26>, <&gpcdma 26>; 8398e442805SAkhil R dma-names = "rx", "tx"; 840156af9deSAkhil R }; 841156af9deSAkhil R 842156af9deSAkhil R dp_aux_ch0_i2c: i2c@31b0000 { 843156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 844*2838cfddSThierry Reding reg = <0x0 0x31b0000 0x0 0x100>; 845156af9deSAkhil R interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 846156af9deSAkhil R status = "disabled"; 847156af9deSAkhil R clock-frequency = <100000>; 848156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C6 849156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 850156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C6>; 851156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 852156af9deSAkhil R clock-names = "div-clk", "parent"; 853156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C6>; 854156af9deSAkhil R reset-names = "i2c"; 8558e442805SAkhil R iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 8568e442805SAkhil R dma-coherent; 8578e442805SAkhil R dmas = <&gpcdma 30>, <&gpcdma 30>; 8588e442805SAkhil R dma-names = "rx", "tx"; 859156af9deSAkhil R }; 860156af9deSAkhil R 861156af9deSAkhil R dp_aux_ch2_i2c: i2c@31c0000 { 862156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 863*2838cfddSThierry Reding reg = <0x0 0x31c0000 0x0 0x100>; 864156af9deSAkhil R interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 865156af9deSAkhil R status = "disabled"; 866156af9deSAkhil R clock-frequency = <100000>; 867156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C7 868156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 869156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C7>; 870156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 871156af9deSAkhil R clock-names = "div-clk", "parent"; 872156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C7>; 873156af9deSAkhil R reset-names = "i2c"; 8748e442805SAkhil R iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 8758e442805SAkhil R dma-coherent; 8768e442805SAkhil R dmas = <&gpcdma 27>, <&gpcdma 27>; 8778e442805SAkhil R dma-names = "rx", "tx"; 878156af9deSAkhil R }; 879156af9deSAkhil R 8801bbba854SJon Hunter uarti: serial@31d0000 { 8811bbba854SJon Hunter compatible = "arm,sbsa-uart"; 882*2838cfddSThierry Reding reg = <0x0 0x31d0000 0x0 0x10000>; 8831bbba854SJon Hunter interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; 8841bbba854SJon Hunter status = "disabled"; 8851bbba854SJon Hunter }; 8861bbba854SJon Hunter 887156af9deSAkhil R dp_aux_ch3_i2c: i2c@31e0000 { 888156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 889*2838cfddSThierry Reding reg = <0x0 0x31e0000 0x0 0x100>; 890156af9deSAkhil R interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 891156af9deSAkhil R status = "disabled"; 892156af9deSAkhil R clock-frequency = <100000>; 893156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C9 894156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 895156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C9>; 896156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 897156af9deSAkhil R clock-names = "div-clk", "parent"; 898156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C9>; 899156af9deSAkhil R reset-names = "i2c"; 9008e442805SAkhil R iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 9018e442805SAkhil R dma-coherent; 9028e442805SAkhil R dmas = <&gpcdma 31>, <&gpcdma 31>; 9038e442805SAkhil R dma-names = "rx", "tx"; 904156af9deSAkhil R }; 905156af9deSAkhil R 90671f69ffaSAshish Singhal spi@3270000 { 90771f69ffaSAshish Singhal compatible = "nvidia,tegra234-qspi"; 908*2838cfddSThierry Reding reg = <0x0 0x3270000 0x0 0x1000>; 90971f69ffaSAshish Singhal interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 91071f69ffaSAshish Singhal #address-cells = <1>; 91171f69ffaSAshish Singhal #size-cells = <0>; 91271f69ffaSAshish Singhal clocks = <&bpmp TEGRA234_CLK_QSPI0_2X_PM>, 91371f69ffaSAshish Singhal <&bpmp TEGRA234_CLK_QSPI0_PM>; 91471f69ffaSAshish Singhal clock-names = "qspi", "qspi_out"; 91571f69ffaSAshish Singhal resets = <&bpmp TEGRA234_RESET_QSPI0>; 91671f69ffaSAshish Singhal status = "disabled"; 91771f69ffaSAshish Singhal }; 91871f69ffaSAshish Singhal 9195e69088dSAkhil R pwm1: pwm@3280000 { 9202566d28cSJon Hunter compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 921*2838cfddSThierry Reding reg = <0x0 0x3280000 0x0 0x10000>; 9225e69088dSAkhil R clocks = <&bpmp TEGRA234_CLK_PWM1>; 9235e69088dSAkhil R resets = <&bpmp TEGRA234_RESET_PWM1>; 9245e69088dSAkhil R reset-names = "pwm"; 9255e69088dSAkhil R status = "disabled"; 9265e69088dSAkhil R #pwm-cells = <2>; 9275e69088dSAkhil R }; 9285e69088dSAkhil R 9292566d28cSJon Hunter pwm2: pwm@3290000 { 9302566d28cSJon Hunter compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 931*2838cfddSThierry Reding reg = <0x0 0x3290000 0x0 0x10000>; 9322566d28cSJon Hunter clocks = <&bpmp TEGRA234_CLK_PWM2>; 9332566d28cSJon Hunter resets = <&bpmp TEGRA234_RESET_PWM2>; 9342566d28cSJon Hunter reset-names = "pwm"; 9352566d28cSJon Hunter status = "disabled"; 9362566d28cSJon Hunter #pwm-cells = <2>; 9372566d28cSJon Hunter }; 9382566d28cSJon Hunter 9392566d28cSJon Hunter pwm3: pwm@32a0000 { 9402566d28cSJon Hunter compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 941*2838cfddSThierry Reding reg = <0x0 0x32a0000 0x0 0x10000>; 9422566d28cSJon Hunter clocks = <&bpmp TEGRA234_CLK_PWM3>; 9432566d28cSJon Hunter resets = <&bpmp TEGRA234_RESET_PWM3>; 9442566d28cSJon Hunter reset-names = "pwm"; 9452566d28cSJon Hunter status = "disabled"; 9462566d28cSJon Hunter #pwm-cells = <2>; 9472566d28cSJon Hunter }; 9482566d28cSJon Hunter 9492566d28cSJon Hunter pwm5: pwm@32c0000 { 9502566d28cSJon Hunter compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 951*2838cfddSThierry Reding reg = <0x0 0x32c0000 0x0 0x10000>; 9522566d28cSJon Hunter clocks = <&bpmp TEGRA234_CLK_PWM5>; 9532566d28cSJon Hunter resets = <&bpmp TEGRA234_RESET_PWM5>; 9542566d28cSJon Hunter reset-names = "pwm"; 9552566d28cSJon Hunter status = "disabled"; 9562566d28cSJon Hunter #pwm-cells = <2>; 9572566d28cSJon Hunter }; 9582566d28cSJon Hunter 9592566d28cSJon Hunter pwm6: pwm@32d0000 { 9602566d28cSJon Hunter compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 961*2838cfddSThierry Reding reg = <0x0 0x32d0000 0x0 0x10000>; 9622566d28cSJon Hunter clocks = <&bpmp TEGRA234_CLK_PWM6>; 9632566d28cSJon Hunter resets = <&bpmp TEGRA234_RESET_PWM6>; 9642566d28cSJon Hunter reset-names = "pwm"; 9652566d28cSJon Hunter status = "disabled"; 9662566d28cSJon Hunter #pwm-cells = <2>; 9672566d28cSJon Hunter }; 9682566d28cSJon Hunter 9692566d28cSJon Hunter pwm7: pwm@32e0000 { 9702566d28cSJon Hunter compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 971*2838cfddSThierry Reding reg = <0x0 0x32e0000 0x0 0x10000>; 9722566d28cSJon Hunter clocks = <&bpmp TEGRA234_CLK_PWM7>; 9732566d28cSJon Hunter resets = <&bpmp TEGRA234_RESET_PWM7>; 9742566d28cSJon Hunter reset-names = "pwm"; 9752566d28cSJon Hunter status = "disabled"; 9762566d28cSJon Hunter #pwm-cells = <2>; 9772566d28cSJon Hunter }; 9782566d28cSJon Hunter 9792566d28cSJon Hunter pwm8: pwm@32f0000 { 9802566d28cSJon Hunter compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 981*2838cfddSThierry Reding reg = <0x0 0x32f0000 0x0 0x10000>; 9822566d28cSJon Hunter clocks = <&bpmp TEGRA234_CLK_PWM8>; 9832566d28cSJon Hunter resets = <&bpmp TEGRA234_RESET_PWM8>; 9842566d28cSJon Hunter reset-names = "pwm"; 9852566d28cSJon Hunter status = "disabled"; 9862566d28cSJon Hunter #pwm-cells = <2>; 9872566d28cSJon Hunter }; 9882566d28cSJon Hunter 98971f69ffaSAshish Singhal spi@3300000 { 99071f69ffaSAshish Singhal compatible = "nvidia,tegra234-qspi"; 991*2838cfddSThierry Reding reg = <0x0 0x3300000 0x0 0x1000>; 99271f69ffaSAshish Singhal interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 99371f69ffaSAshish Singhal #address-cells = <1>; 99471f69ffaSAshish Singhal #size-cells = <0>; 99571f69ffaSAshish Singhal clocks = <&bpmp TEGRA234_CLK_QSPI1_2X_PM>, 99671f69ffaSAshish Singhal <&bpmp TEGRA234_CLK_QSPI1_PM>; 99771f69ffaSAshish Singhal clock-names = "qspi", "qspi_out"; 99871f69ffaSAshish Singhal resets = <&bpmp TEGRA234_RESET_QSPI1>; 99971f69ffaSAshish Singhal status = "disabled"; 100071f69ffaSAshish Singhal }; 100171f69ffaSAshish Singhal 1002d71b893aSPrathamesh Shete mmc@3400000 { 1003132b552cSThierry Reding compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci"; 1004*2838cfddSThierry Reding reg = <0x0 0x03400000 0x0 0x20000>; 1005d71b893aSPrathamesh Shete interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 1006d71b893aSPrathamesh Shete clocks = <&bpmp TEGRA234_CLK_SDMMC1>, 1007d71b893aSPrathamesh Shete <&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>; 1008d71b893aSPrathamesh Shete clock-names = "sdhci", "tmclk"; 1009d71b893aSPrathamesh Shete assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC1>, 1010d71b893aSPrathamesh Shete <&bpmp TEGRA234_CLK_PLLC4_MUXED>; 1011d71b893aSPrathamesh Shete assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4_MUXED>, 1012d71b893aSPrathamesh Shete <&bpmp TEGRA234_CLK_PLLC4_VCO_DIV2>; 1013d71b893aSPrathamesh Shete resets = <&bpmp TEGRA234_RESET_SDMMC1>; 1014d71b893aSPrathamesh Shete reset-names = "sdhci"; 1015d71b893aSPrathamesh Shete interconnects = <&mc TEGRA234_MEMORY_CLIENT_SDMMCRA &emc>, 1016d71b893aSPrathamesh Shete <&mc TEGRA234_MEMORY_CLIENT_SDMMCWA &emc>; 1017d71b893aSPrathamesh Shete interconnect-names = "dma-mem", "write"; 1018d71b893aSPrathamesh Shete iommus = <&smmu_niso1 TEGRA234_SID_SDMMC1A>; 1019d71b893aSPrathamesh Shete pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 1020d71b893aSPrathamesh Shete pinctrl-0 = <&sdmmc1_3v3>; 1021d71b893aSPrathamesh Shete pinctrl-1 = <&sdmmc1_1v8>; 1022d71b893aSPrathamesh Shete nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 1023d71b893aSPrathamesh Shete nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x07>; 1024d71b893aSPrathamesh Shete nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 1025d71b893aSPrathamesh Shete nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 1026d71b893aSPrathamesh Shete nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 1027d71b893aSPrathamesh Shete nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 1028d71b893aSPrathamesh Shete nvidia,default-tap = <14>; 1029d71b893aSPrathamesh Shete nvidia,default-trim = <0x8>; 1030d71b893aSPrathamesh Shete sd-uhs-sdr25; 1031d71b893aSPrathamesh Shete sd-uhs-sdr50; 1032d71b893aSPrathamesh Shete sd-uhs-ddr50; 1033d71b893aSPrathamesh Shete sd-uhs-sdr104; 1034d71b893aSPrathamesh Shete status = "disabled"; 1035d71b893aSPrathamesh Shete }; 1036d71b893aSPrathamesh Shete 103763944891SThierry Reding mmc@3460000 { 103863944891SThierry Reding compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci"; 1039*2838cfddSThierry Reding reg = <0x0 0x03460000 0x0 0x20000>; 104063944891SThierry Reding interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 1041e086d82dSMikko Perttunen clocks = <&bpmp TEGRA234_CLK_SDMMC4>, 1042e086d82dSMikko Perttunen <&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>; 1043e086d82dSMikko Perttunen clock-names = "sdhci", "tmclk"; 1044e086d82dSMikko Perttunen assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC4>, 1045e086d82dSMikko Perttunen <&bpmp TEGRA234_CLK_PLLC4>; 1046e086d82dSMikko Perttunen assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4>; 104763944891SThierry Reding resets = <&bpmp TEGRA234_RESET_SDMMC4>; 104863944891SThierry Reding reset-names = "sdhci"; 10496de481e5SThierry Reding interconnects = <&mc TEGRA234_MEMORY_CLIENT_SDMMCRAB &emc>, 10506de481e5SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_SDMMCWAB &emc>; 10516de481e5SThierry Reding interconnect-names = "dma-mem", "write"; 10525710e16aSThierry Reding iommus = <&smmu_niso1 TEGRA234_SID_SDMMC4>; 1053e086d82dSMikko Perttunen nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 1054e086d82dSMikko Perttunen nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 1055e086d82dSMikko Perttunen nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 1056e086d82dSMikko Perttunen nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; 1057e086d82dSMikko Perttunen nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 1058e086d82dSMikko Perttunen nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>; 1059e086d82dSMikko Perttunen nvidia,default-tap = <0x8>; 1060e086d82dSMikko Perttunen nvidia,default-trim = <0x14>; 1061e086d82dSMikko Perttunen nvidia,dqs-trim = <40>; 1062e086d82dSMikko Perttunen supports-cqe; 106363944891SThierry Reding status = "disabled"; 106463944891SThierry Reding }; 106563944891SThierry Reding 1066621e12a1SMohan Kumar hda@3510000 { 1067b2fbcbe1SThierry Reding compatible = "nvidia,tegra234-hda"; 1068*2838cfddSThierry Reding reg = <0x0 0x3510000 0x0 0x10000>; 1069621e12a1SMohan Kumar interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 1070621e12a1SMohan Kumar clocks = <&bpmp TEGRA234_CLK_AZA_BIT>, 1071621e12a1SMohan Kumar <&bpmp TEGRA234_CLK_AZA_2XBIT>; 1072621e12a1SMohan Kumar clock-names = "hda", "hda2codec_2x"; 1073621e12a1SMohan Kumar resets = <&bpmp TEGRA234_RESET_HDA>, 1074621e12a1SMohan Kumar <&bpmp TEGRA234_RESET_HDACODEC>; 1075621e12a1SMohan Kumar reset-names = "hda", "hda2codec_2x"; 1076621e12a1SMohan Kumar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_DISP>; 1077621e12a1SMohan Kumar interconnects = <&mc TEGRA234_MEMORY_CLIENT_HDAR &emc>, 1078621e12a1SMohan Kumar <&mc TEGRA234_MEMORY_CLIENT_HDAW &emc>; 1079621e12a1SMohan Kumar interconnect-names = "dma-mem", "write"; 1080af4c2773SMohan Kumar iommus = <&smmu_niso0 TEGRA234_SID_HDA>; 1081621e12a1SMohan Kumar status = "disabled"; 1082621e12a1SMohan Kumar }; 1083621e12a1SMohan Kumar 108463944891SThierry Reding fuse@3810000 { 108563944891SThierry Reding compatible = "nvidia,tegra234-efuse"; 1086*2838cfddSThierry Reding reg = <0x0 0x03810000 0x0 0x10000>; 108763944891SThierry Reding clocks = <&bpmp TEGRA234_CLK_FUSE>; 108863944891SThierry Reding clock-names = "fuse"; 108963944891SThierry Reding }; 109063944891SThierry Reding 109163944891SThierry Reding hsp_top0: hsp@3c00000 { 109263944891SThierry Reding compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; 1093*2838cfddSThierry Reding reg = <0x0 0x03c00000 0x0 0xa0000>; 109463944891SThierry Reding interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 109563944891SThierry Reding <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 109663944891SThierry Reding <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 109763944891SThierry Reding <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 109863944891SThierry Reding <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 109963944891SThierry Reding <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 110063944891SThierry Reding <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 110163944891SThierry Reding <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 110263944891SThierry Reding <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 110363944891SThierry Reding interrupt-names = "doorbell", "shared0", "shared1", "shared2", 110463944891SThierry Reding "shared3", "shared4", "shared5", "shared6", 110563944891SThierry Reding "shared7"; 110663944891SThierry Reding #mbox-cells = <2>; 110763944891SThierry Reding }; 110863944891SThierry Reding 110978159542SThierry Reding p2u_hsio_0: phy@3e00000 { 111078159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 1111*2838cfddSThierry Reding reg = <0x0 0x03e00000 0x0 0x10000>; 111278159542SThierry Reding reg-names = "ctl"; 111378159542SThierry Reding 111478159542SThierry Reding #phy-cells = <0>; 111578159542SThierry Reding }; 111678159542SThierry Reding 111778159542SThierry Reding p2u_hsio_1: phy@3e10000 { 111878159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 1119*2838cfddSThierry Reding reg = <0x0 0x03e10000 0x0 0x10000>; 112078159542SThierry Reding reg-names = "ctl"; 112178159542SThierry Reding 112278159542SThierry Reding #phy-cells = <0>; 112378159542SThierry Reding }; 112478159542SThierry Reding 112578159542SThierry Reding p2u_hsio_2: phy@3e20000 { 112678159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 1127*2838cfddSThierry Reding reg = <0x0 0x03e20000 0x0 0x10000>; 112878159542SThierry Reding reg-names = "ctl"; 112978159542SThierry Reding 113078159542SThierry Reding #phy-cells = <0>; 113178159542SThierry Reding }; 113278159542SThierry Reding 113378159542SThierry Reding p2u_hsio_3: phy@3e30000 { 113478159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 1135*2838cfddSThierry Reding reg = <0x0 0x03e30000 0x0 0x10000>; 113678159542SThierry Reding reg-names = "ctl"; 113778159542SThierry Reding 113878159542SThierry Reding #phy-cells = <0>; 113978159542SThierry Reding }; 114078159542SThierry Reding 114178159542SThierry Reding p2u_hsio_4: phy@3e40000 { 114278159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 1143*2838cfddSThierry Reding reg = <0x0 0x03e40000 0x0 0x10000>; 114478159542SThierry Reding reg-names = "ctl"; 114578159542SThierry Reding 114678159542SThierry Reding #phy-cells = <0>; 114778159542SThierry Reding }; 114878159542SThierry Reding 114978159542SThierry Reding p2u_hsio_5: phy@3e50000 { 115078159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 1151*2838cfddSThierry Reding reg = <0x0 0x03e50000 0x0 0x10000>; 115278159542SThierry Reding reg-names = "ctl"; 115378159542SThierry Reding 115478159542SThierry Reding #phy-cells = <0>; 115578159542SThierry Reding }; 115678159542SThierry Reding 115778159542SThierry Reding p2u_hsio_6: phy@3e60000 { 115878159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 1159*2838cfddSThierry Reding reg = <0x0 0x03e60000 0x0 0x10000>; 116078159542SThierry Reding reg-names = "ctl"; 116178159542SThierry Reding 116278159542SThierry Reding #phy-cells = <0>; 116378159542SThierry Reding }; 116478159542SThierry Reding 116578159542SThierry Reding p2u_hsio_7: phy@3e70000 { 116678159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 1167*2838cfddSThierry Reding reg = <0x0 0x03e70000 0x0 0x10000>; 116878159542SThierry Reding reg-names = "ctl"; 116978159542SThierry Reding 117078159542SThierry Reding #phy-cells = <0>; 117178159542SThierry Reding }; 117278159542SThierry Reding 117378159542SThierry Reding p2u_nvhs_0: phy@3e90000 { 117478159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 1175*2838cfddSThierry Reding reg = <0x0 0x03e90000 0x0 0x10000>; 117678159542SThierry Reding reg-names = "ctl"; 117778159542SThierry Reding 117878159542SThierry Reding #phy-cells = <0>; 117978159542SThierry Reding }; 118078159542SThierry Reding 118178159542SThierry Reding p2u_nvhs_1: phy@3ea0000 { 118278159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 1183*2838cfddSThierry Reding reg = <0x0 0x03ea0000 0x0 0x10000>; 118478159542SThierry Reding reg-names = "ctl"; 118578159542SThierry Reding 118678159542SThierry Reding #phy-cells = <0>; 118778159542SThierry Reding }; 118878159542SThierry Reding 118978159542SThierry Reding p2u_nvhs_2: phy@3eb0000 { 119078159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 1191*2838cfddSThierry Reding reg = <0x0 0x03eb0000 0x0 0x10000>; 119278159542SThierry Reding reg-names = "ctl"; 119378159542SThierry Reding 119478159542SThierry Reding #phy-cells = <0>; 119578159542SThierry Reding }; 119678159542SThierry Reding 119778159542SThierry Reding p2u_nvhs_3: phy@3ec0000 { 119878159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 1199*2838cfddSThierry Reding reg = <0x0 0x03ec0000 0x0 0x10000>; 120078159542SThierry Reding reg-names = "ctl"; 120178159542SThierry Reding 120278159542SThierry Reding #phy-cells = <0>; 120378159542SThierry Reding }; 120478159542SThierry Reding 120578159542SThierry Reding p2u_nvhs_4: phy@3ed0000 { 120678159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 1207*2838cfddSThierry Reding reg = <0x0 0x03ed0000 0x0 0x10000>; 120878159542SThierry Reding reg-names = "ctl"; 120978159542SThierry Reding 121078159542SThierry Reding #phy-cells = <0>; 121178159542SThierry Reding }; 121278159542SThierry Reding 121378159542SThierry Reding p2u_nvhs_5: phy@3ee0000 { 121478159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 1215*2838cfddSThierry Reding reg = <0x0 0x03ee0000 0x0 0x10000>; 121678159542SThierry Reding reg-names = "ctl"; 121778159542SThierry Reding 121878159542SThierry Reding #phy-cells = <0>; 121978159542SThierry Reding }; 122078159542SThierry Reding 122178159542SThierry Reding p2u_nvhs_6: phy@3ef0000 { 122278159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 1223*2838cfddSThierry Reding reg = <0x0 0x03ef0000 0x0 0x10000>; 122478159542SThierry Reding reg-names = "ctl"; 122578159542SThierry Reding 122678159542SThierry Reding #phy-cells = <0>; 122778159542SThierry Reding }; 122878159542SThierry Reding 122978159542SThierry Reding p2u_nvhs_7: phy@3f00000 { 123078159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 1231*2838cfddSThierry Reding reg = <0x0 0x03f00000 0x0 0x10000>; 123278159542SThierry Reding reg-names = "ctl"; 123378159542SThierry Reding 123478159542SThierry Reding #phy-cells = <0>; 123578159542SThierry Reding }; 123678159542SThierry Reding 123778159542SThierry Reding p2u_gbe_0: phy@3f20000 { 123878159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 1239*2838cfddSThierry Reding reg = <0x0 0x03f20000 0x0 0x10000>; 124078159542SThierry Reding reg-names = "ctl"; 124178159542SThierry Reding 124278159542SThierry Reding #phy-cells = <0>; 124378159542SThierry Reding }; 124478159542SThierry Reding 124578159542SThierry Reding p2u_gbe_1: phy@3f30000 { 124678159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 1247*2838cfddSThierry Reding reg = <0x0 0x03f30000 0x0 0x10000>; 124878159542SThierry Reding reg-names = "ctl"; 124978159542SThierry Reding 125078159542SThierry Reding #phy-cells = <0>; 125178159542SThierry Reding }; 125278159542SThierry Reding 125378159542SThierry Reding p2u_gbe_2: phy@3f40000 { 125478159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 1255*2838cfddSThierry Reding reg = <0x0 0x03f40000 0x0 0x10000>; 125678159542SThierry Reding reg-names = "ctl"; 125778159542SThierry Reding 125878159542SThierry Reding #phy-cells = <0>; 125978159542SThierry Reding }; 126078159542SThierry Reding 126178159542SThierry Reding p2u_gbe_3: phy@3f50000 { 126278159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 1263*2838cfddSThierry Reding reg = <0x0 0x03f50000 0x0 0x10000>; 126478159542SThierry Reding reg-names = "ctl"; 126578159542SThierry Reding 126678159542SThierry Reding #phy-cells = <0>; 126778159542SThierry Reding }; 126878159542SThierry Reding 126978159542SThierry Reding p2u_gbe_4: phy@3f60000 { 127078159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 1271*2838cfddSThierry Reding reg = <0x0 0x03f60000 0x0 0x10000>; 127278159542SThierry Reding reg-names = "ctl"; 127378159542SThierry Reding 127478159542SThierry Reding #phy-cells = <0>; 127578159542SThierry Reding }; 127678159542SThierry Reding 127778159542SThierry Reding p2u_gbe_5: phy@3f70000 { 127878159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 1279*2838cfddSThierry Reding reg = <0x0 0x03f70000 0x0 0x10000>; 128078159542SThierry Reding reg-names = "ctl"; 128178159542SThierry Reding 128278159542SThierry Reding #phy-cells = <0>; 128378159542SThierry Reding }; 128478159542SThierry Reding 128578159542SThierry Reding p2u_gbe_6: phy@3f80000 { 128678159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 1287*2838cfddSThierry Reding reg = <0x0 0x03f80000 0x0 0x10000>; 128878159542SThierry Reding reg-names = "ctl"; 128978159542SThierry Reding 129078159542SThierry Reding #phy-cells = <0>; 129178159542SThierry Reding }; 129278159542SThierry Reding 129378159542SThierry Reding p2u_gbe_7: phy@3f90000 { 129478159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 1295*2838cfddSThierry Reding reg = <0x0 0x03f90000 0x0 0x10000>; 129678159542SThierry Reding reg-names = "ctl"; 129778159542SThierry Reding 129878159542SThierry Reding #phy-cells = <0>; 129978159542SThierry Reding }; 130078159542SThierry Reding 1301610cdf31SThierry Reding ethernet@6800000 { 1302610cdf31SThierry Reding compatible = "nvidia,tegra234-mgbe"; 1303*2838cfddSThierry Reding reg = <0x0 0x06800000 0x0 0x10000>, 1304*2838cfddSThierry Reding <0x0 0x06810000 0x0 0x10000>, 1305*2838cfddSThierry Reding <0x0 0x068a0000 0x0 0x10000>; 1306610cdf31SThierry Reding reg-names = "hypervisor", "mac", "xpcs"; 1307610cdf31SThierry Reding interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>; 1308610cdf31SThierry Reding interrupt-names = "common"; 1309610cdf31SThierry Reding clocks = <&bpmp TEGRA234_CLK_MGBE0_APP>, 1310610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE0_MAC>, 1311610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE0_MAC_DIVIDER>, 1312610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE0_PTP_REF>, 1313610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT_M>, 1314610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT>, 1315610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE0_TX>, 1316610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE0_EEE_PCS>, 1317610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_INPUT>, 1318610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_M>, 1319610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE0_RX_PCS>, 1320610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE0_TX_PCS>; 1321610cdf31SThierry Reding clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", 1322610cdf31SThierry Reding "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", 1323610cdf31SThierry Reding "rx-pcs", "tx-pcs"; 1324610cdf31SThierry Reding resets = <&bpmp TEGRA234_RESET_MGBE0_MAC>, 1325610cdf31SThierry Reding <&bpmp TEGRA234_RESET_MGBE0_PCS>; 1326610cdf31SThierry Reding reset-names = "mac", "pcs"; 1327610cdf31SThierry Reding interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEARD &emc>, 1328610cdf31SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_MGBEAWR &emc>; 1329610cdf31SThierry Reding interconnect-names = "dma-mem", "write"; 1330610cdf31SThierry Reding iommus = <&smmu_niso0 TEGRA234_SID_MGBE>; 1331610cdf31SThierry Reding power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEA>; 1332610cdf31SThierry Reding status = "disabled"; 1333610cdf31SThierry Reding }; 1334610cdf31SThierry Reding 1335610cdf31SThierry Reding ethernet@6900000 { 1336610cdf31SThierry Reding compatible = "nvidia,tegra234-mgbe"; 1337*2838cfddSThierry Reding reg = <0x0 0x06900000 0x0 0x10000>, 1338*2838cfddSThierry Reding <0x0 0x06910000 0x0 0x10000>, 1339*2838cfddSThierry Reding <0x0 0x069a0000 0x0 0x10000>; 1340610cdf31SThierry Reding reg-names = "hypervisor", "mac", "xpcs"; 1341610cdf31SThierry Reding interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>; 1342610cdf31SThierry Reding interrupt-names = "common"; 1343610cdf31SThierry Reding clocks = <&bpmp TEGRA234_CLK_MGBE1_APP>, 1344610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE1_MAC>, 1345610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE1_MAC_DIVIDER>, 1346610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE1_PTP_REF>, 1347610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE1_RX_INPUT_M>, 1348610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE1_RX_INPUT>, 1349610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE1_TX>, 1350610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE1_EEE_PCS>, 1351610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE1_RX_PCS_INPUT>, 1352610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE1_RX_PCS_M>, 1353610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE1_RX_PCS>, 1354610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE1_TX_PCS>; 1355610cdf31SThierry Reding clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", 1356610cdf31SThierry Reding "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", 1357610cdf31SThierry Reding "rx-pcs", "tx-pcs"; 1358610cdf31SThierry Reding resets = <&bpmp TEGRA234_RESET_MGBE1_MAC>, 1359610cdf31SThierry Reding <&bpmp TEGRA234_RESET_MGBE1_PCS>; 1360610cdf31SThierry Reding reset-names = "mac", "pcs"; 1361610cdf31SThierry Reding interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEBRD &emc>, 1362610cdf31SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_MGBEBWR &emc>; 1363610cdf31SThierry Reding interconnect-names = "dma-mem", "write"; 1364610cdf31SThierry Reding iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF1>; 1365610cdf31SThierry Reding power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEB>; 1366610cdf31SThierry Reding status = "disabled"; 1367610cdf31SThierry Reding }; 1368610cdf31SThierry Reding 1369610cdf31SThierry Reding ethernet@6a00000 { 1370610cdf31SThierry Reding compatible = "nvidia,tegra234-mgbe"; 1371*2838cfddSThierry Reding reg = <0x0 0x06a00000 0x0 0x10000>, 1372*2838cfddSThierry Reding <0x0 0x06a10000 0x0 0x10000>, 1373*2838cfddSThierry Reding <0x0 0x06aa0000 0x0 0x10000>; 1374610cdf31SThierry Reding reg-names = "hypervisor", "mac", "xpcs"; 1375610cdf31SThierry Reding interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>; 1376610cdf31SThierry Reding interrupt-names = "common"; 1377610cdf31SThierry Reding clocks = <&bpmp TEGRA234_CLK_MGBE2_APP>, 1378610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE2_MAC>, 1379610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE2_MAC_DIVIDER>, 1380610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE2_PTP_REF>, 1381610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE2_RX_INPUT_M>, 1382610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE2_RX_INPUT>, 1383610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE2_TX>, 1384610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE2_EEE_PCS>, 1385610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE2_RX_PCS_INPUT>, 1386610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE2_RX_PCS_M>, 1387610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE2_RX_PCS>, 1388610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE2_TX_PCS>; 1389610cdf31SThierry Reding clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", 1390610cdf31SThierry Reding "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", 1391610cdf31SThierry Reding "rx-pcs", "tx-pcs"; 1392610cdf31SThierry Reding resets = <&bpmp TEGRA234_RESET_MGBE2_MAC>, 1393610cdf31SThierry Reding <&bpmp TEGRA234_RESET_MGBE2_PCS>; 1394610cdf31SThierry Reding reset-names = "mac", "pcs"; 1395610cdf31SThierry Reding interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBECRD &emc>, 1396610cdf31SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_MGBECWR &emc>; 1397610cdf31SThierry Reding interconnect-names = "dma-mem", "write"; 1398610cdf31SThierry Reding iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF2>; 1399610cdf31SThierry Reding power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEC>; 1400610cdf31SThierry Reding status = "disabled"; 1401610cdf31SThierry Reding }; 1402610cdf31SThierry Reding 1403610cdf31SThierry Reding ethernet@6b00000 { 1404610cdf31SThierry Reding compatible = "nvidia,tegra234-mgbe"; 1405*2838cfddSThierry Reding reg = <0x0 0x06b00000 0x0 0x10000>, 1406*2838cfddSThierry Reding <0x0 0x06b10000 0x0 0x10000>, 1407*2838cfddSThierry Reding <0x0 0x06ba0000 0x0 0x10000>; 1408610cdf31SThierry Reding reg-names = "hypervisor", "mac", "xpcs"; 1409610cdf31SThierry Reding interrupts = <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 1410610cdf31SThierry Reding interrupt-names = "common"; 1411610cdf31SThierry Reding clocks = <&bpmp TEGRA234_CLK_MGBE3_APP>, 1412610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE3_MAC>, 1413610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE3_MAC_DIVIDER>, 1414610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE3_PTP_REF>, 1415610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE3_RX_INPUT_M>, 1416610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE3_RX_INPUT>, 1417610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE3_TX>, 1418610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE3_EEE_PCS>, 1419610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE3_RX_PCS_INPUT>, 1420610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE3_RX_PCS_M>, 1421610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE3_RX_PCS>, 1422610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE3_TX_PCS>; 1423610cdf31SThierry Reding clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", 1424610cdf31SThierry Reding "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", 1425610cdf31SThierry Reding "rx-pcs", "tx-pcs"; 1426610cdf31SThierry Reding resets = <&bpmp TEGRA234_RESET_MGBE3_MAC>, 1427610cdf31SThierry Reding <&bpmp TEGRA234_RESET_MGBE3_PCS>; 1428610cdf31SThierry Reding reset-names = "mac", "pcs"; 1429610cdf31SThierry Reding interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEDRD &emc>, 1430610cdf31SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_MGBEDWR &emc>; 1431610cdf31SThierry Reding interconnect-names = "dma-mem", "write"; 1432610cdf31SThierry Reding iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF3>; 1433610cdf31SThierry Reding power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBED>; 1434610cdf31SThierry Reding status = "disabled"; 1435610cdf31SThierry Reding }; 1436610cdf31SThierry Reding 14375710e16aSThierry Reding smmu_niso1: iommu@8000000 { 14385710e16aSThierry Reding compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; 1439*2838cfddSThierry Reding reg = <0x0 0x8000000 0x0 0x1000000>, 1440*2838cfddSThierry Reding <0x0 0x7000000 0x0 0x1000000>; 14415710e16aSThierry Reding interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14425710e16aSThierry Reding <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, 14435710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14445710e16aSThierry Reding <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, 14455710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14465710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14475710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14485710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14495710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14505710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14515710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14525710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14535710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14545710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14555710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14565710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14575710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14585710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14595710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14605710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14615710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14625710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14635710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14645710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14655710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14665710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14675710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14685710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14695710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14705710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14715710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14725710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14735710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14745710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14755710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14765710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14775710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14785710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14795710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14805710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14815710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14825710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14835710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14845710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14855710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14865710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14875710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14885710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14895710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14905710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14915710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14925710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14935710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14945710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14955710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14965710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14975710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14985710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 14995710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15005710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15015710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15025710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15035710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15045710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15055710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15065710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15075710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15085710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15095710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15105710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15115710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15125710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15135710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15145710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15155710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15165710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15175710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15185710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15195710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15205710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15215710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15225710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15235710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15245710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15255710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15265710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15275710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15285710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15295710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15305710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15315710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15325710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15335710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15345710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15355710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15365710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15375710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15385710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15395710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15405710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15415710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15425710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15435710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15445710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15455710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15465710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15475710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15485710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15495710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15505710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15515710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15525710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15535710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15545710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15555710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15565710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15575710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15585710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15595710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15605710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15615710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15625710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15635710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15645710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15655710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15665710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15675710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15685710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15695710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15705710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 15715710e16aSThierry Reding stream-match-mask = <0x7f80>; 15725710e16aSThierry Reding #global-interrupts = <2>; 15735710e16aSThierry Reding #iommu-cells = <1>; 15745710e16aSThierry Reding 15755710e16aSThierry Reding nvidia,memory-controller = <&mc>; 15765710e16aSThierry Reding status = "okay"; 15775710e16aSThierry Reding }; 15785710e16aSThierry Reding 1579302e1540SSumit Gupta sce-fabric@b600000 { 1580302e1540SSumit Gupta compatible = "nvidia,tegra234-sce-fabric"; 1581*2838cfddSThierry Reding reg = <0x0 0xb600000 0x0 0x40000>; 1582302e1540SSumit Gupta interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 1583302e1540SSumit Gupta status = "okay"; 1584302e1540SSumit Gupta }; 1585302e1540SSumit Gupta 1586302e1540SSumit Gupta rce-fabric@be00000 { 1587302e1540SSumit Gupta compatible = "nvidia,tegra234-rce-fabric"; 1588*2838cfddSThierry Reding reg = <0x0 0xbe00000 0x0 0x40000>; 1589302e1540SSumit Gupta interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 1590302e1540SSumit Gupta status = "okay"; 1591302e1540SSumit Gupta }; 1592302e1540SSumit Gupta 159363944891SThierry Reding hsp_aon: hsp@c150000 { 159463944891SThierry Reding compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; 1595*2838cfddSThierry Reding reg = <0x0 0x0c150000 0x0 0x90000>; 159663944891SThierry Reding interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 159763944891SThierry Reding <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 159863944891SThierry Reding <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 159963944891SThierry Reding <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 160063944891SThierry Reding /* 160163944891SThierry Reding * Shared interrupt 0 is routed only to AON/SPE, so 160263944891SThierry Reding * we only have 4 shared interrupts for the CCPLEX. 160363944891SThierry Reding */ 160463944891SThierry Reding interrupt-names = "shared1", "shared2", "shared3", "shared4"; 160563944891SThierry Reding #mbox-cells = <2>; 160663944891SThierry Reding }; 160763944891SThierry Reding 1608156af9deSAkhil R gen2_i2c: i2c@c240000 { 1609156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 1610*2838cfddSThierry Reding reg = <0x0 0xc240000 0x0 0x100>; 1611156af9deSAkhil R interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1612156af9deSAkhil R status = "disabled"; 1613156af9deSAkhil R clock-frequency = <100000>; 1614156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C2 1615156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 1616156af9deSAkhil R clock-names = "div-clk", "parent"; 1617156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C2>; 1618156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 1619156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C2>; 1620156af9deSAkhil R reset-names = "i2c"; 16218e442805SAkhil R iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 16228e442805SAkhil R dma-coherent; 16238e442805SAkhil R dmas = <&gpcdma 22>, <&gpcdma 22>; 16248e442805SAkhil R dma-names = "rx", "tx"; 1625156af9deSAkhil R }; 1626156af9deSAkhil R 1627156af9deSAkhil R gen8_i2c: i2c@c250000 { 1628156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 1629*2838cfddSThierry Reding reg = <0x0 0xc250000 0x0 0x100>; 1630156af9deSAkhil R interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1631156af9deSAkhil R status = "disabled"; 1632156af9deSAkhil R clock-frequency = <400000>; 1633156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C8 1634156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 1635156af9deSAkhil R clock-names = "div-clk", "parent"; 1636156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C8>; 1637156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 1638156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C8>; 1639156af9deSAkhil R reset-names = "i2c"; 16408e442805SAkhil R iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 16418e442805SAkhil R dma-coherent; 16428e442805SAkhil R dmas = <&gpcdma 0>, <&gpcdma 0>; 16438e442805SAkhil R dma-names = "rx", "tx"; 1644156af9deSAkhil R }; 1645156af9deSAkhil R 164663944891SThierry Reding rtc@c2a0000 { 164763944891SThierry Reding compatible = "nvidia,tegra234-rtc", "nvidia,tegra20-rtc"; 1648*2838cfddSThierry Reding reg = <0x0 0x0c2a0000 0x0 0x10000>; 164963944891SThierry Reding interrupt-parent = <&pmc>; 165063944891SThierry Reding interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 1651e537addeSMikko Perttunen clocks = <&bpmp TEGRA234_CLK_CLK_32K>; 1652e537addeSMikko Perttunen clock-names = "rtc"; 165363944891SThierry Reding status = "disabled"; 165463944891SThierry Reding }; 165563944891SThierry Reding 1656f0e12668SThierry Reding gpio_aon: gpio@c2f0000 { 1657f0e12668SThierry Reding compatible = "nvidia,tegra234-gpio-aon"; 1658f0e12668SThierry Reding reg-names = "security", "gpio"; 1659*2838cfddSThierry Reding reg = <0x0 0x0c2f0000 0x0 0x1000>, 1660*2838cfddSThierry Reding <0x0 0x0c2f1000 0x0 0x1000>; 1661f0e12668SThierry Reding interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1662f0e12668SThierry Reding <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1663f0e12668SThierry Reding <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1664f0e12668SThierry Reding <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 1665f0e12668SThierry Reding #interrupt-cells = <2>; 1666f0e12668SThierry Reding interrupt-controller; 1667f0e12668SThierry Reding #gpio-cells = <2>; 1668f0e12668SThierry Reding gpio-controller; 1669f0e12668SThierry Reding }; 1670f0e12668SThierry Reding 16712566d28cSJon Hunter pwm4: pwm@c340000 { 16722566d28cSJon Hunter compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 1673*2838cfddSThierry Reding reg = <0x0 0xc340000 0x0 0x10000>; 16742566d28cSJon Hunter clocks = <&bpmp TEGRA234_CLK_PWM4>; 16752566d28cSJon Hunter resets = <&bpmp TEGRA234_RESET_PWM4>; 16762566d28cSJon Hunter reset-names = "pwm"; 16772566d28cSJon Hunter status = "disabled"; 16782566d28cSJon Hunter #pwm-cells = <2>; 16792566d28cSJon Hunter }; 16802566d28cSJon Hunter 168163944891SThierry Reding pmc: pmc@c360000 { 168263944891SThierry Reding compatible = "nvidia,tegra234-pmc"; 1683*2838cfddSThierry Reding reg = <0x0 0x0c360000 0x0 0x10000>, 1684*2838cfddSThierry Reding <0x0 0x0c370000 0x0 0x10000>, 1685*2838cfddSThierry Reding <0x0 0x0c380000 0x0 0x10000>, 1686*2838cfddSThierry Reding <0x0 0x0c390000 0x0 0x10000>, 1687*2838cfddSThierry Reding <0x0 0x0c3a0000 0x0 0x10000>; 168863944891SThierry Reding reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 168963944891SThierry Reding 169063944891SThierry Reding #interrupt-cells = <2>; 169163944891SThierry Reding interrupt-controller; 1692d71b893aSPrathamesh Shete 1693d71b893aSPrathamesh Shete sdmmc1_3v3: sdmmc1-3v3 { 1694d71b893aSPrathamesh Shete pins = "sdmmc1-hv"; 1695d71b893aSPrathamesh Shete power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1696d71b893aSPrathamesh Shete }; 1697d71b893aSPrathamesh Shete 1698d71b893aSPrathamesh Shete sdmmc1_1v8: sdmmc1-1v8 { 1699d71b893aSPrathamesh Shete pins = "sdmmc1-hv"; 1700d71b893aSPrathamesh Shete power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1701d71b893aSPrathamesh Shete }; 1702d71b893aSPrathamesh Shete 1703d71b893aSPrathamesh Shete sdmmc3_3v3: sdmmc3-3v3 { 1704d71b893aSPrathamesh Shete pins = "sdmmc3-hv"; 1705d71b893aSPrathamesh Shete power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1706d71b893aSPrathamesh Shete }; 1707d71b893aSPrathamesh Shete 1708d71b893aSPrathamesh Shete sdmmc3_1v8: sdmmc3-1v8 { 1709d71b893aSPrathamesh Shete pins = "sdmmc3-hv"; 1710d71b893aSPrathamesh Shete power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1711d71b893aSPrathamesh Shete }; 171263944891SThierry Reding }; 171363944891SThierry Reding 1714302e1540SSumit Gupta aon-fabric@c600000 { 1715302e1540SSumit Gupta compatible = "nvidia,tegra234-aon-fabric"; 1716*2838cfddSThierry Reding reg = <0x0 0xc600000 0x0 0x40000>; 1717302e1540SSumit Gupta interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 1718302e1540SSumit Gupta status = "okay"; 1719302e1540SSumit Gupta }; 1720302e1540SSumit Gupta 1721302e1540SSumit Gupta bpmp-fabric@d600000 { 1722302e1540SSumit Gupta compatible = "nvidia,tegra234-bpmp-fabric"; 1723*2838cfddSThierry Reding reg = <0x0 0xd600000 0x0 0x40000>; 1724302e1540SSumit Gupta interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1725302e1540SSumit Gupta status = "okay"; 1726302e1540SSumit Gupta }; 1727302e1540SSumit Gupta 1728302e1540SSumit Gupta dce-fabric@de00000 { 1729302e1540SSumit Gupta compatible = "nvidia,tegra234-sce-fabric"; 1730*2838cfddSThierry Reding reg = <0x0 0xde00000 0x0 0x40000>; 1731302e1540SSumit Gupta interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>; 1732302e1540SSumit Gupta status = "okay"; 1733302e1540SSumit Gupta }; 1734302e1540SSumit Gupta 1735*2838cfddSThierry Reding ccplex@e000000 { 1736*2838cfddSThierry Reding compatible = "nvidia,tegra234-ccplex-cluster"; 1737*2838cfddSThierry Reding reg = <0x0 0x0e000000 0x0 0x5ffff>; 1738*2838cfddSThierry Reding nvidia,bpmp = <&bpmp>; 1739*2838cfddSThierry Reding status = "okay"; 1740*2838cfddSThierry Reding }; 1741*2838cfddSThierry Reding 174263944891SThierry Reding gic: interrupt-controller@f400000 { 174363944891SThierry Reding compatible = "arm,gic-v3"; 1744*2838cfddSThierry Reding reg = <0x0 0x0f400000 0x0 0x010000>, /* GICD */ 1745*2838cfddSThierry Reding <0x0 0x0f440000 0x0 0x200000>; /* GICR */ 174663944891SThierry Reding interrupt-parent = <&gic>; 174763944891SThierry Reding interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 174863944891SThierry Reding 174963944891SThierry Reding #redistributor-regions = <1>; 175063944891SThierry Reding #interrupt-cells = <3>; 175163944891SThierry Reding interrupt-controller; 175263944891SThierry Reding }; 17535710e16aSThierry Reding 17545710e16aSThierry Reding smmu_iso: iommu@10000000 { 17555710e16aSThierry Reding compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; 1756*2838cfddSThierry Reding reg = <0x0 0x10000000 0x0 0x1000000>; 17575710e16aSThierry Reding interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17585710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17595710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17605710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17615710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17625710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17635710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17645710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17655710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17665710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17675710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17685710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17695710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17705710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17715710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17725710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17735710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17745710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17755710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17765710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17775710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17785710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17795710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17805710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17815710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17825710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17835710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17845710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17855710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17865710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17875710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17885710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17895710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17905710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17915710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17925710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17935710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17945710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17955710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17965710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17975710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17985710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17995710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18005710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18015710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18025710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18035710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18045710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18055710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18065710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18075710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18085710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18095710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18105710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18115710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18125710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18135710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18145710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18155710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18165710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18175710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18185710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18195710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18205710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18215710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18225710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18235710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18245710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18255710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18265710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18275710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18285710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18295710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18305710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18315710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18325710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18335710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18345710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18355710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18365710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18375710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18385710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18395710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18405710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18415710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18425710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18435710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18445710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18455710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18465710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18475710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18485710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18495710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18505710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18515710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18525710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18535710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18545710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18555710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18565710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18575710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18585710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18595710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18605710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18615710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18625710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18635710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18645710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18655710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18665710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18675710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18685710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18695710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18705710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18715710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18725710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18735710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18745710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18755710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18765710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18775710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18785710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18795710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18805710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18815710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18825710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18835710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18845710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18855710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 18865710e16aSThierry Reding stream-match-mask = <0x7f80>; 18875710e16aSThierry Reding #global-interrupts = <1>; 18885710e16aSThierry Reding #iommu-cells = <1>; 18895710e16aSThierry Reding 18905710e16aSThierry Reding nvidia,memory-controller = <&mc>; 18915710e16aSThierry Reding status = "okay"; 18925710e16aSThierry Reding }; 18935710e16aSThierry Reding 18945710e16aSThierry Reding smmu_niso0: iommu@12000000 { 18955710e16aSThierry Reding compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; 1896*2838cfddSThierry Reding reg = <0x0 0x12000000 0x0 0x1000000>, 1897*2838cfddSThierry Reding <0x0 0x11000000 0x0 0x1000000>; 18985710e16aSThierry Reding interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18995710e16aSThierry Reding <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 19005710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19015710e16aSThierry Reding <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 19025710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19035710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19045710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19055710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19065710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19075710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19085710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19095710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19105710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19115710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19125710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19135710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19145710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19155710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19165710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19175710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19185710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19195710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19205710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19215710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19225710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19235710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19245710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19255710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19265710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19275710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19285710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19295710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19305710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19315710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19325710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19335710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19345710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19355710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19365710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19375710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19385710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19395710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19405710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19415710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19425710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19435710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19445710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19455710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19465710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19475710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19485710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19495710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19505710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19515710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19525710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19535710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19545710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19555710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19565710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19575710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19585710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19595710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19605710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19615710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19625710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19635710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19645710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19655710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19665710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19675710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19685710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19695710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19705710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19715710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19725710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19735710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19745710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19755710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19765710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19775710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19785710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19795710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19805710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19815710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19825710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19835710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19845710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19855710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19865710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19875710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19885710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19895710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19905710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19915710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19925710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19935710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19945710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19955710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19965710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19975710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19985710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19995710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20005710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20015710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20025710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20035710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20045710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20055710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20065710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20075710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20085710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20095710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20105710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20115710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20125710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20135710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20145710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20155710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20165710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20175710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20185710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20195710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20205710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20215710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20225710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20235710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20245710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20255710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20265710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20275710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 20285710e16aSThierry Reding stream-match-mask = <0x7f80>; 20295710e16aSThierry Reding #global-interrupts = <2>; 20305710e16aSThierry Reding #iommu-cells = <1>; 20315710e16aSThierry Reding 20325710e16aSThierry Reding nvidia,memory-controller = <&mc>; 20335710e16aSThierry Reding status = "okay"; 20345710e16aSThierry Reding }; 2035302e1540SSumit Gupta 2036302e1540SSumit Gupta cbb-fabric@13a00000 { 2037302e1540SSumit Gupta compatible = "nvidia,tegra234-cbb-fabric"; 2038*2838cfddSThierry Reding reg = <0x0 0x13a00000 0x0 0x400000>; 2039302e1540SSumit Gupta interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 2040302e1540SSumit Gupta status = "okay"; 2041302e1540SSumit Gupta }; 2042962c400dSSumit Gupta 2043ec142c44SVidya Sagar pcie@140a0000 { 2044ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie"; 2045ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CA>; 2046ec142c44SVidya Sagar reg = <0x00 0x140a0000 0x0 0x00020000>, /* appl registers (128K) */ 2047ec142c44SVidya Sagar <0x00 0x2a000000 0x0 0x00040000>, /* configuration space (256K) */ 2048ec142c44SVidya Sagar <0x00 0x2a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2049794b834dSVidya Sagar <0x00 0x2a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2050794b834dSVidya Sagar <0x35 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2051794b834dSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2052ec142c44SVidya Sagar 2053ec142c44SVidya Sagar #address-cells = <3>; 2054ec142c44SVidya Sagar #size-cells = <2>; 2055ec142c44SVidya Sagar device_type = "pci"; 2056ec142c44SVidya Sagar num-lanes = <4>; 2057ec142c44SVidya Sagar num-viewport = <8>; 2058ec142c44SVidya Sagar linux,pci-domain = <8>; 2059ec142c44SVidya Sagar 2060ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX2_C8_CORE>; 2061ec142c44SVidya Sagar clock-names = "core"; 2062ec142c44SVidya Sagar 2063ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX2_CORE_8_APB>, 2064ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX2_CORE_8>; 2065ec142c44SVidya Sagar reset-names = "apb", "core"; 2066ec142c44SVidya Sagar 2067ec142c44SVidya Sagar interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2068ec142c44SVidya Sagar <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2069ec142c44SVidya Sagar interrupt-names = "intr", "msi"; 2070ec142c44SVidya Sagar 2071ec142c44SVidya Sagar #interrupt-cells = <1>; 2072ec142c44SVidya Sagar interrupt-map-mask = <0 0 0 0>; 2073ec142c44SVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 2074ec142c44SVidya Sagar 2075ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 8>; 2076ec142c44SVidya Sagar 2077ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2078ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2079ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2080ec142c44SVidya Sagar 2081ec142c44SVidya Sagar bus-range = <0x0 0xff>; 2082ec142c44SVidya Sagar 2083ec142c44SVidya Sagar ranges = <0x43000000 0x32 0x40000000 0x32 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2084ec142c44SVidya Sagar <0x02000000 0x0 0x40000000 0x35 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2085ec142c44SVidya Sagar <0x01000000 0x0 0x2a100000 0x00 0x2a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2086ec142c44SVidya Sagar 2087ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE8AR &emc>, 2088ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE8AW &emc>; 2089ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2090ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE8 0x1000>; 2091ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2092ec142c44SVidya Sagar dma-coherent; 2093ec142c44SVidya Sagar 2094ec142c44SVidya Sagar status = "disabled"; 2095ec142c44SVidya Sagar }; 2096ec142c44SVidya Sagar 2097ec142c44SVidya Sagar pcie@140c0000 { 2098ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie"; 2099ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CB>; 2100ec142c44SVidya Sagar reg = <0x00 0x140c0000 0x0 0x00020000>, /* appl registers (128K) */ 2101ec142c44SVidya Sagar <0x00 0x2c000000 0x0 0x00040000>, /* configuration space (256K) */ 2102ec142c44SVidya Sagar <0x00 0x2c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2103794b834dSVidya Sagar <0x00 0x2c080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2104794b834dSVidya Sagar <0x38 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2105794b834dSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2106ec142c44SVidya Sagar 2107ec142c44SVidya Sagar #address-cells = <3>; 2108ec142c44SVidya Sagar #size-cells = <2>; 2109ec142c44SVidya Sagar device_type = "pci"; 2110ec142c44SVidya Sagar num-lanes = <4>; 2111ec142c44SVidya Sagar num-viewport = <8>; 2112ec142c44SVidya Sagar linux,pci-domain = <9>; 2113ec142c44SVidya Sagar 2114ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX2_C9_CORE>; 2115ec142c44SVidya Sagar clock-names = "core"; 2116ec142c44SVidya Sagar 2117ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX2_CORE_9_APB>, 2118ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX2_CORE_9>; 2119ec142c44SVidya Sagar reset-names = "apb", "core"; 2120ec142c44SVidya Sagar 2121ec142c44SVidya Sagar interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2122ec142c44SVidya Sagar <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2123ec142c44SVidya Sagar interrupt-names = "intr", "msi"; 2124ec142c44SVidya Sagar 2125ec142c44SVidya Sagar #interrupt-cells = <1>; 2126ec142c44SVidya Sagar interrupt-map-mask = <0 0 0 0>; 2127ec142c44SVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2128ec142c44SVidya Sagar 2129ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 9>; 2130ec142c44SVidya Sagar 2131ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2132ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2133ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2134ec142c44SVidya Sagar 2135ec142c44SVidya Sagar bus-range = <0x0 0xff>; 2136ec142c44SVidya Sagar 213724840065SVidya Sagar ranges = <0x43000000 0x35 0x40000000 0x35 0x40000000 0x2 0xc0000000>, /* prefetchable memory (11264 MB) */ 2138ec142c44SVidya Sagar <0x02000000 0x0 0x40000000 0x38 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2139ec142c44SVidya Sagar <0x01000000 0x0 0x2c100000 0x00 0x2c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2140ec142c44SVidya Sagar 2141ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE9AR &emc>, 2142ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE9AW &emc>; 2143ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2144ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE9 0x1000>; 2145ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2146ec142c44SVidya Sagar dma-coherent; 2147ec142c44SVidya Sagar 2148ec142c44SVidya Sagar status = "disabled"; 2149ec142c44SVidya Sagar }; 2150ec142c44SVidya Sagar 2151ec142c44SVidya Sagar pcie@140e0000 { 2152ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie"; 2153ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CC>; 2154ec142c44SVidya Sagar reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K) */ 2155ec142c44SVidya Sagar <0x00 0x2e000000 0x0 0x00040000>, /* configuration space (256K) */ 2156ec142c44SVidya Sagar <0x00 0x2e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2157794b834dSVidya Sagar <0x00 0x2e080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2158794b834dSVidya Sagar <0x3b 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2159794b834dSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2160ec142c44SVidya Sagar 2161ec142c44SVidya Sagar #address-cells = <3>; 2162ec142c44SVidya Sagar #size-cells = <2>; 2163ec142c44SVidya Sagar device_type = "pci"; 2164ec142c44SVidya Sagar num-lanes = <4>; 2165ec142c44SVidya Sagar num-viewport = <8>; 2166ec142c44SVidya Sagar linux,pci-domain = <10>; 2167ec142c44SVidya Sagar 2168ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX2_C10_CORE>; 2169ec142c44SVidya Sagar clock-names = "core"; 2170ec142c44SVidya Sagar 2171ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX2_CORE_10_APB>, 2172ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX2_CORE_10>; 2173ec142c44SVidya Sagar reset-names = "apb", "core"; 2174ec142c44SVidya Sagar 2175ec142c44SVidya Sagar interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2176ec142c44SVidya Sagar <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2177ec142c44SVidya Sagar interrupt-names = "intr", "msi"; 2178ec142c44SVidya Sagar 2179ec142c44SVidya Sagar #interrupt-cells = <1>; 2180ec142c44SVidya Sagar interrupt-map-mask = <0 0 0 0>; 2181ec142c44SVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 2182ec142c44SVidya Sagar 2183ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 10>; 2184ec142c44SVidya Sagar 2185ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2186ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2187ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2188ec142c44SVidya Sagar 2189ec142c44SVidya Sagar bus-range = <0x0 0xff>; 2190ec142c44SVidya Sagar 2191ec142c44SVidya Sagar ranges = <0x43000000 0x38 0x40000000 0x38 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2192ec142c44SVidya Sagar <0x02000000 0x0 0x40000000 0x3b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2193ec142c44SVidya Sagar <0x01000000 0x0 0x2e100000 0x00 0x2e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2194ec142c44SVidya Sagar 2195ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE10AR &emc>, 2196ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE10AW &emc>; 2197ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2198ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>; 2199ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2200ec142c44SVidya Sagar dma-coherent; 2201ec142c44SVidya Sagar 2202ec142c44SVidya Sagar status = "disabled"; 2203ec142c44SVidya Sagar }; 2204ec142c44SVidya Sagar 2205*2838cfddSThierry Reding pcie-ep@140e0000 { 2206*2838cfddSThierry Reding compatible = "nvidia,tegra234-pcie-ep"; 2207*2838cfddSThierry Reding power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CC>; 2208*2838cfddSThierry Reding reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K) */ 2209*2838cfddSThierry Reding <0x00 0x2e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2210*2838cfddSThierry Reding <0x00 0x2e080000 0x0 0x00040000>, /* DBI space (256K) */ 2211*2838cfddSThierry Reding <0x38 0x40000000 0x3 0x00000000>; /* Address Space (12G) */ 2212*2838cfddSThierry Reding reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2213*2838cfddSThierry Reding 2214*2838cfddSThierry Reding num-lanes = <4>; 2215*2838cfddSThierry Reding 2216*2838cfddSThierry Reding clocks = <&bpmp TEGRA234_CLK_PEX2_C10_CORE>; 2217*2838cfddSThierry Reding clock-names = "core"; 2218*2838cfddSThierry Reding 2219*2838cfddSThierry Reding resets = <&bpmp TEGRA234_RESET_PEX2_CORE_10_APB>, 2220*2838cfddSThierry Reding <&bpmp TEGRA234_RESET_PEX2_CORE_10>; 2221*2838cfddSThierry Reding reset-names = "apb", "core"; 2222*2838cfddSThierry Reding 2223*2838cfddSThierry Reding interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2224*2838cfddSThierry Reding interrupt-names = "intr"; 2225*2838cfddSThierry Reding 2226*2838cfddSThierry Reding nvidia,bpmp = <&bpmp 10>; 2227*2838cfddSThierry Reding 2228*2838cfddSThierry Reding nvidia,enable-ext-refclk; 2229*2838cfddSThierry Reding nvidia,aspm-cmrt-us = <60>; 2230*2838cfddSThierry Reding nvidia,aspm-pwr-on-t-us = <20>; 2231*2838cfddSThierry Reding nvidia,aspm-l0s-entrance-latency-us = <3>; 2232*2838cfddSThierry Reding 2233*2838cfddSThierry Reding interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE10AR &emc>, 2234*2838cfddSThierry Reding <&mc TEGRA234_MEMORY_CLIENT_PCIE10AW &emc>; 2235*2838cfddSThierry Reding interconnect-names = "dma-mem", "write"; 2236*2838cfddSThierry Reding iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>; 2237*2838cfddSThierry Reding iommu-map-mask = <0x0>; 2238*2838cfddSThierry Reding dma-coherent; 2239*2838cfddSThierry Reding 2240*2838cfddSThierry Reding status = "disabled"; 2241*2838cfddSThierry Reding }; 2242*2838cfddSThierry Reding 2243ec142c44SVidya Sagar pcie@14100000 { 2244ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie"; 2245ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>; 2246ec142c44SVidya Sagar reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */ 2247ec142c44SVidya Sagar <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */ 2248ec142c44SVidya Sagar <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2249794b834dSVidya Sagar <0x00 0x30080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2250794b834dSVidya Sagar <0x20 0xb0000000 0x0 0x10000000>; /* ECAM (256MB) */ 2251794b834dSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2252ec142c44SVidya Sagar 2253ec142c44SVidya Sagar #address-cells = <3>; 2254ec142c44SVidya Sagar #size-cells = <2>; 2255ec142c44SVidya Sagar device_type = "pci"; 2256ec142c44SVidya Sagar num-lanes = <1>; 2257ec142c44SVidya Sagar num-viewport = <8>; 2258ec142c44SVidya Sagar linux,pci-domain = <1>; 2259ec142c44SVidya Sagar 2260ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX0_C1_CORE>; 2261ec142c44SVidya Sagar clock-names = "core"; 2262ec142c44SVidya Sagar 2263ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX0_CORE_1_APB>, 2264ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX0_CORE_1>; 2265ec142c44SVidya Sagar reset-names = "apb", "core"; 2266ec142c44SVidya Sagar 2267ec142c44SVidya Sagar interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2268ec142c44SVidya Sagar <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2269ec142c44SVidya Sagar interrupt-names = "intr", "msi"; 2270ec142c44SVidya Sagar 2271ec142c44SVidya Sagar #interrupt-cells = <1>; 2272ec142c44SVidya Sagar interrupt-map-mask = <0 0 0 0>; 2273ec142c44SVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 2274ec142c44SVidya Sagar 2275ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 1>; 2276ec142c44SVidya Sagar 2277ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2278ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2279ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2280ec142c44SVidya Sagar 2281ec142c44SVidya Sagar bus-range = <0x0 0xff>; 2282ec142c44SVidya Sagar 2283ec142c44SVidya Sagar ranges = <0x43000000 0x20 0x80000000 0x20 0x80000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ 2284ec142c44SVidya Sagar <0x02000000 0x0 0x40000000 0x20 0xa8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2285ec142c44SVidya Sagar <0x01000000 0x0 0x30100000 0x00 0x30100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2286ec142c44SVidya Sagar 2287ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE1R &emc>, 2288ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE1W &emc>; 2289ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2290ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE1 0x1000>; 2291ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2292ec142c44SVidya Sagar dma-coherent; 2293ec142c44SVidya Sagar 2294ec142c44SVidya Sagar status = "disabled"; 2295ec142c44SVidya Sagar }; 2296ec142c44SVidya Sagar 2297ec142c44SVidya Sagar pcie@14120000 { 2298ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie"; 2299ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>; 2300ec142c44SVidya Sagar reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */ 2301ec142c44SVidya Sagar <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */ 2302ec142c44SVidya Sagar <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2303794b834dSVidya Sagar <0x00 0x32080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2304794b834dSVidya Sagar <0x20 0xf0000000 0x0 0x10000000>; /* ECAM (256MB) */ 2305794b834dSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2306ec142c44SVidya Sagar 2307ec142c44SVidya Sagar #address-cells = <3>; 2308ec142c44SVidya Sagar #size-cells = <2>; 2309ec142c44SVidya Sagar device_type = "pci"; 2310ec142c44SVidya Sagar num-lanes = <1>; 2311ec142c44SVidya Sagar num-viewport = <8>; 2312ec142c44SVidya Sagar linux,pci-domain = <2>; 2313ec142c44SVidya Sagar 2314ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX0_C2_CORE>; 2315ec142c44SVidya Sagar clock-names = "core"; 2316ec142c44SVidya Sagar 2317ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX0_CORE_2_APB>, 2318ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX0_CORE_2>; 2319ec142c44SVidya Sagar reset-names = "apb", "core"; 2320ec142c44SVidya Sagar 2321ec142c44SVidya Sagar interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2322ec142c44SVidya Sagar <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2323ec142c44SVidya Sagar interrupt-names = "intr", "msi"; 2324ec142c44SVidya Sagar 2325ec142c44SVidya Sagar #interrupt-cells = <1>; 2326ec142c44SVidya Sagar interrupt-map-mask = <0 0 0 0>; 2327ec142c44SVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 2328ec142c44SVidya Sagar 2329ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 2>; 2330ec142c44SVidya Sagar 2331ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2332ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2333ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2334ec142c44SVidya Sagar 2335ec142c44SVidya Sagar bus-range = <0x0 0xff>; 2336ec142c44SVidya Sagar 2337ec142c44SVidya Sagar ranges = <0x43000000 0x20 0xc0000000 0x20 0xc0000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ 2338ec142c44SVidya Sagar <0x02000000 0x0 0x40000000 0x20 0xe8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2339ec142c44SVidya Sagar <0x01000000 0x0 0x32100000 0x00 0x32100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2340ec142c44SVidya Sagar 2341ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE2AR &emc>, 2342ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE2AW &emc>; 2343ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2344ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE2 0x1000>; 2345ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2346ec142c44SVidya Sagar dma-coherent; 2347ec142c44SVidya Sagar 2348ec142c44SVidya Sagar status = "disabled"; 2349ec142c44SVidya Sagar }; 2350ec142c44SVidya Sagar 2351ec142c44SVidya Sagar pcie@14140000 { 2352ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie"; 2353ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>; 2354ec142c44SVidya Sagar reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */ 2355ec142c44SVidya Sagar <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */ 2356ec142c44SVidya Sagar <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2357794b834dSVidya Sagar <0x00 0x34080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2358794b834dSVidya Sagar <0x21 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2359794b834dSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2360ec142c44SVidya Sagar 2361ec142c44SVidya Sagar #address-cells = <3>; 2362ec142c44SVidya Sagar #size-cells = <2>; 2363ec142c44SVidya Sagar device_type = "pci"; 2364ec142c44SVidya Sagar num-lanes = <1>; 2365ec142c44SVidya Sagar num-viewport = <8>; 2366ec142c44SVidya Sagar linux,pci-domain = <3>; 2367ec142c44SVidya Sagar 2368ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX0_C3_CORE>; 2369ec142c44SVidya Sagar clock-names = "core"; 2370ec142c44SVidya Sagar 2371ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX0_CORE_3_APB>, 2372ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX0_CORE_3>; 2373ec142c44SVidya Sagar reset-names = "apb", "core"; 2374ec142c44SVidya Sagar 2375ec142c44SVidya Sagar interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2376ec142c44SVidya Sagar <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2377ec142c44SVidya Sagar interrupt-names = "intr", "msi"; 2378ec142c44SVidya Sagar 2379ec142c44SVidya Sagar #interrupt-cells = <1>; 2380ec142c44SVidya Sagar interrupt-map-mask = <0 0 0 0>; 2381ec142c44SVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 2382ec142c44SVidya Sagar 2383ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 3>; 2384ec142c44SVidya Sagar 2385ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2386ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2387ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2388ec142c44SVidya Sagar 2389ec142c44SVidya Sagar bus-range = <0x0 0xff>; 2390ec142c44SVidya Sagar 2391ec142c44SVidya Sagar ranges = <0x43000000 0x21 0x00000000 0x21 0x00000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ 239247a2f35dSVidya Sagar <0x02000000 0x0 0x40000000 0x21 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2393ec142c44SVidya Sagar <0x01000000 0x0 0x34100000 0x00 0x34100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2394ec142c44SVidya Sagar 2395ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE3R &emc>, 2396ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE3W &emc>; 2397ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2398ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE3 0x1000>; 2399ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2400ec142c44SVidya Sagar dma-coherent; 2401ec142c44SVidya Sagar 2402ec142c44SVidya Sagar status = "disabled"; 2403ec142c44SVidya Sagar }; 2404ec142c44SVidya Sagar 2405ec142c44SVidya Sagar pcie@14160000 { 2406ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie"; 2407ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BB>; 2408ec142c44SVidya Sagar reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2409ec142c44SVidya Sagar <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ 2410ec142c44SVidya Sagar <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2411794b834dSVidya Sagar <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2412794b834dSVidya Sagar <0x24 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2413794b834dSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2414ec142c44SVidya Sagar 2415ec142c44SVidya Sagar #address-cells = <3>; 2416ec142c44SVidya Sagar #size-cells = <2>; 2417ec142c44SVidya Sagar device_type = "pci"; 2418ec142c44SVidya Sagar num-lanes = <4>; 2419ec142c44SVidya Sagar num-viewport = <8>; 2420ec142c44SVidya Sagar linux,pci-domain = <4>; 2421ec142c44SVidya Sagar 2422ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX0_C4_CORE>; 2423ec142c44SVidya Sagar clock-names = "core"; 2424ec142c44SVidya Sagar 2425ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX0_CORE_4_APB>, 2426ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX0_CORE_4>; 2427ec142c44SVidya Sagar reset-names = "apb", "core"; 2428ec142c44SVidya Sagar 2429ec142c44SVidya Sagar interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2430ec142c44SVidya Sagar <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2431ec142c44SVidya Sagar interrupt-names = "intr", "msi"; 2432ec142c44SVidya Sagar 2433ec142c44SVidya Sagar #interrupt-cells = <1>; 2434ec142c44SVidya Sagar interrupt-map-mask = <0 0 0 0>; 2435ec142c44SVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 2436ec142c44SVidya Sagar 2437ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 4>; 2438ec142c44SVidya Sagar 2439ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2440ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2441ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2442ec142c44SVidya Sagar 2443ec142c44SVidya Sagar bus-range = <0x0 0xff>; 2444ec142c44SVidya Sagar 2445ec142c44SVidya Sagar ranges = <0x43000000 0x21 0x40000000 0x21 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2446ec142c44SVidya Sagar <0x02000000 0x0 0x40000000 0x24 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2447ec142c44SVidya Sagar <0x01000000 0x0 0x36100000 0x00 0x36100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2448ec142c44SVidya Sagar 2449ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE4R &emc>, 2450ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE4W &emc>; 2451ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2452ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE4 0x1000>; 2453ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2454ec142c44SVidya Sagar dma-coherent; 2455ec142c44SVidya Sagar 2456ec142c44SVidya Sagar status = "disabled"; 2457ec142c44SVidya Sagar }; 2458ec142c44SVidya Sagar 2459ec142c44SVidya Sagar pcie@14180000 { 2460ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie"; 2461ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BA>; 2462ec142c44SVidya Sagar reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2463ec142c44SVidya Sagar <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ 2464ec142c44SVidya Sagar <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2465794b834dSVidya Sagar <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2466794b834dSVidya Sagar <0x27 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2467794b834dSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2468ec142c44SVidya Sagar 2469ec142c44SVidya Sagar #address-cells = <3>; 2470ec142c44SVidya Sagar #size-cells = <2>; 2471ec142c44SVidya Sagar device_type = "pci"; 2472ec142c44SVidya Sagar num-lanes = <4>; 2473ec142c44SVidya Sagar num-viewport = <8>; 2474ec142c44SVidya Sagar linux,pci-domain = <0>; 2475ec142c44SVidya Sagar 2476ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX0_C0_CORE>; 2477ec142c44SVidya Sagar clock-names = "core"; 2478ec142c44SVidya Sagar 2479ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX0_CORE_0_APB>, 2480ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX0_CORE_0>; 2481ec142c44SVidya Sagar reset-names = "apb", "core"; 2482ec142c44SVidya Sagar 2483ec142c44SVidya Sagar interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2484ec142c44SVidya Sagar <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2485ec142c44SVidya Sagar interrupt-names = "intr", "msi"; 2486ec142c44SVidya Sagar 2487ec142c44SVidya Sagar #interrupt-cells = <1>; 2488ec142c44SVidya Sagar interrupt-map-mask = <0 0 0 0>; 2489ec142c44SVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 2490ec142c44SVidya Sagar 2491ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 0>; 2492ec142c44SVidya Sagar 2493ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2494ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2495ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2496ec142c44SVidya Sagar 2497ec142c44SVidya Sagar bus-range = <0x0 0xff>; 2498ec142c44SVidya Sagar 2499ec142c44SVidya Sagar ranges = <0x43000000 0x24 0x40000000 0x24 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2500ec142c44SVidya Sagar <0x02000000 0x0 0x40000000 0x27 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2501ec142c44SVidya Sagar <0x01000000 0x0 0x38100000 0x00 0x38100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2502ec142c44SVidya Sagar 2503ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE0R &emc>, 2504ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE0W &emc>; 2505ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2506ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE0 0x1000>; 2507ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2508ec142c44SVidya Sagar dma-coherent; 2509ec142c44SVidya Sagar 2510ec142c44SVidya Sagar status = "disabled"; 2511ec142c44SVidya Sagar }; 2512ec142c44SVidya Sagar 2513ec142c44SVidya Sagar pcie@141a0000 { 2514ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie"; 2515ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>; 2516ec142c44SVidya Sagar reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2517ec142c44SVidya Sagar <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */ 2518ec142c44SVidya Sagar <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2519794b834dSVidya Sagar <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2520794b834dSVidya Sagar <0x2b 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2521794b834dSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2522ec142c44SVidya Sagar 2523ec142c44SVidya Sagar #address-cells = <3>; 2524ec142c44SVidya Sagar #size-cells = <2>; 2525ec142c44SVidya Sagar device_type = "pci"; 2526ec142c44SVidya Sagar num-lanes = <8>; 2527ec142c44SVidya Sagar num-viewport = <8>; 2528ec142c44SVidya Sagar linux,pci-domain = <5>; 2529ec142c44SVidya Sagar 2530ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>; 2531ec142c44SVidya Sagar clock-names = "core"; 2532ec142c44SVidya Sagar 2533ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>, 2534ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX1_CORE_5>; 2535ec142c44SVidya Sagar reset-names = "apb", "core"; 2536ec142c44SVidya Sagar 2537ec142c44SVidya Sagar interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2538ec142c44SVidya Sagar <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2539ec142c44SVidya Sagar interrupt-names = "intr", "msi"; 2540ec142c44SVidya Sagar 2541ec142c44SVidya Sagar #interrupt-cells = <1>; 2542ec142c44SVidya Sagar interrupt-map-mask = <0 0 0 0>; 2543ec142c44SVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 2544ec142c44SVidya Sagar 2545ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 5>; 2546ec142c44SVidya Sagar 2547ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2548ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2549ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2550ec142c44SVidya Sagar 2551ec142c44SVidya Sagar bus-range = <0x0 0xff>; 2552ec142c44SVidya Sagar 255324840065SVidya Sagar ranges = <0x43000000 0x28 0x00000000 0x28 0x00000000 0x3 0x28000000>, /* prefetchable memory (12928 MB) */ 2554ec142c44SVidya Sagar <0x02000000 0x0 0x40000000 0x2b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2555ec142c44SVidya Sagar <0x01000000 0x0 0x3a100000 0x00 0x3a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2556ec142c44SVidya Sagar 2557ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE5R &emc>, 2558ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE5W &emc>; 2559ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2560ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>; 2561ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2562ec142c44SVidya Sagar dma-coherent; 2563ec142c44SVidya Sagar 2564ec142c44SVidya Sagar status = "disabled"; 2565ec142c44SVidya Sagar }; 2566ec142c44SVidya Sagar 2567*2838cfddSThierry Reding pcie-ep@141a0000 { 2568*2838cfddSThierry Reding compatible = "nvidia,tegra234-pcie-ep"; 2569*2838cfddSThierry Reding power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>; 2570*2838cfddSThierry Reding reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2571*2838cfddSThierry Reding <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2572*2838cfddSThierry Reding <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2573*2838cfddSThierry Reding <0x27 0x40000000 0x4 0x00000000>; /* Address Space (16G) */ 2574*2838cfddSThierry Reding reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2575*2838cfddSThierry Reding 2576*2838cfddSThierry Reding num-lanes = <8>; 2577*2838cfddSThierry Reding 2578*2838cfddSThierry Reding clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>; 2579*2838cfddSThierry Reding clock-names = "core"; 2580*2838cfddSThierry Reding 2581*2838cfddSThierry Reding resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>, 2582*2838cfddSThierry Reding <&bpmp TEGRA234_RESET_PEX1_CORE_5>; 2583*2838cfddSThierry Reding reset-names = "apb", "core"; 2584*2838cfddSThierry Reding 2585*2838cfddSThierry Reding interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2586*2838cfddSThierry Reding interrupt-names = "intr"; 2587*2838cfddSThierry Reding 2588*2838cfddSThierry Reding nvidia,bpmp = <&bpmp 5>; 2589*2838cfddSThierry Reding 2590*2838cfddSThierry Reding nvidia,enable-ext-refclk; 2591*2838cfddSThierry Reding nvidia,aspm-cmrt-us = <60>; 2592*2838cfddSThierry Reding nvidia,aspm-pwr-on-t-us = <20>; 2593*2838cfddSThierry Reding nvidia,aspm-l0s-entrance-latency-us = <3>; 2594*2838cfddSThierry Reding 2595*2838cfddSThierry Reding interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE5R &emc>, 2596*2838cfddSThierry Reding <&mc TEGRA234_MEMORY_CLIENT_PCIE5W &emc>; 2597*2838cfddSThierry Reding interconnect-names = "dma-mem", "write"; 2598*2838cfddSThierry Reding iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>; 2599*2838cfddSThierry Reding iommu-map-mask = <0x0>; 2600*2838cfddSThierry Reding dma-coherent; 2601*2838cfddSThierry Reding 2602*2838cfddSThierry Reding status = "disabled"; 2603*2838cfddSThierry Reding }; 2604*2838cfddSThierry Reding 2605ec142c44SVidya Sagar pcie@141c0000 { 2606ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie"; 2607ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4A>; 2608ec142c44SVidya Sagar reg = <0x00 0x141c0000 0x0 0x00020000>, /* appl registers (128K) */ 2609ec142c44SVidya Sagar <0x00 0x3c000000 0x0 0x00040000>, /* configuration space (256K) */ 2610ec142c44SVidya Sagar <0x00 0x3c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2611794b834dSVidya Sagar <0x00 0x3c080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2612794b834dSVidya Sagar <0x2e 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2613794b834dSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2614ec142c44SVidya Sagar 2615ec142c44SVidya Sagar #address-cells = <3>; 2616ec142c44SVidya Sagar #size-cells = <2>; 2617ec142c44SVidya Sagar device_type = "pci"; 2618ec142c44SVidya Sagar num-lanes = <4>; 2619ec142c44SVidya Sagar num-viewport = <8>; 2620ec142c44SVidya Sagar linux,pci-domain = <6>; 2621ec142c44SVidya Sagar 2622ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX1_C6_CORE>; 2623ec142c44SVidya Sagar clock-names = "core"; 2624ec142c44SVidya Sagar 2625ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX1_CORE_6_APB>, 2626ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX1_CORE_6>; 2627ec142c44SVidya Sagar reset-names = "apb", "core"; 2628ec142c44SVidya Sagar 2629ec142c44SVidya Sagar interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2630ec142c44SVidya Sagar <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2631ec142c44SVidya Sagar interrupt-names = "intr", "msi"; 2632ec142c44SVidya Sagar 2633ec142c44SVidya Sagar #interrupt-cells = <1>; 2634ec142c44SVidya Sagar interrupt-map-mask = <0 0 0 0>; 2635ec142c44SVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 2636ec142c44SVidya Sagar 2637ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 6>; 2638ec142c44SVidya Sagar 2639ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2640ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2641ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2642ec142c44SVidya Sagar 2643ec142c44SVidya Sagar bus-range = <0x0 0xff>; 2644ec142c44SVidya Sagar 2645ec142c44SVidya Sagar ranges = <0x43000000 0x2b 0x40000000 0x2b 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2646ec142c44SVidya Sagar <0x02000000 0x0 0x40000000 0x2e 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2647ec142c44SVidya Sagar <0x01000000 0x0 0x3c100000 0x00 0x3c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2648ec142c44SVidya Sagar 2649ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE6AR &emc>, 2650ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE6AW &emc>; 2651ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2652ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>; 2653ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2654ec142c44SVidya Sagar dma-coherent; 2655ec142c44SVidya Sagar 2656ec142c44SVidya Sagar status = "disabled"; 2657ec142c44SVidya Sagar }; 2658ec142c44SVidya Sagar 2659*2838cfddSThierry Reding pcie-ep@141c0000 { 2660*2838cfddSThierry Reding compatible = "nvidia,tegra234-pcie-ep"; 2661*2838cfddSThierry Reding power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4A>; 2662*2838cfddSThierry Reding reg = <0x00 0x141c0000 0x0 0x00020000>, /* appl registers (128K) */ 2663*2838cfddSThierry Reding <0x00 0x3c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2664*2838cfddSThierry Reding <0x00 0x3c080000 0x0 0x00040000>, /* DBI space (256K) */ 2665*2838cfddSThierry Reding <0x2b 0x40000000 0x3 0x00000000>; /* Address Space (12G) */ 2666*2838cfddSThierry Reding reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2667*2838cfddSThierry Reding 2668*2838cfddSThierry Reding num-lanes = <4>; 2669*2838cfddSThierry Reding 2670*2838cfddSThierry Reding clocks = <&bpmp TEGRA234_CLK_PEX1_C6_CORE>; 2671*2838cfddSThierry Reding clock-names = "core"; 2672*2838cfddSThierry Reding 2673*2838cfddSThierry Reding resets = <&bpmp TEGRA234_RESET_PEX1_CORE_6_APB>, 2674*2838cfddSThierry Reding <&bpmp TEGRA234_RESET_PEX1_CORE_6>; 2675*2838cfddSThierry Reding reset-names = "apb", "core"; 2676*2838cfddSThierry Reding 2677*2838cfddSThierry Reding interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2678*2838cfddSThierry Reding interrupt-names = "intr"; 2679*2838cfddSThierry Reding 2680*2838cfddSThierry Reding nvidia,bpmp = <&bpmp 6>; 2681*2838cfddSThierry Reding 2682*2838cfddSThierry Reding nvidia,enable-ext-refclk; 2683*2838cfddSThierry Reding nvidia,aspm-cmrt-us = <60>; 2684*2838cfddSThierry Reding nvidia,aspm-pwr-on-t-us = <20>; 2685*2838cfddSThierry Reding nvidia,aspm-l0s-entrance-latency-us = <3>; 2686*2838cfddSThierry Reding 2687*2838cfddSThierry Reding interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE6AR &emc>, 2688*2838cfddSThierry Reding <&mc TEGRA234_MEMORY_CLIENT_PCIE6AW &emc>; 2689*2838cfddSThierry Reding interconnect-names = "dma-mem", "write"; 2690*2838cfddSThierry Reding iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>; 2691*2838cfddSThierry Reding iommu-map-mask = <0x0>; 2692*2838cfddSThierry Reding dma-coherent; 2693*2838cfddSThierry Reding 2694*2838cfddSThierry Reding status = "disabled"; 2695*2838cfddSThierry Reding }; 2696*2838cfddSThierry Reding 2697ec142c44SVidya Sagar pcie@141e0000 { 2698ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie"; 2699ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8B>; 2700ec142c44SVidya Sagar reg = <0x00 0x141e0000 0x0 0x00020000>, /* appl registers (128K) */ 2701ec142c44SVidya Sagar <0x00 0x3e000000 0x0 0x00040000>, /* configuration space (256K) */ 2702ec142c44SVidya Sagar <0x00 0x3e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2703794b834dSVidya Sagar <0x00 0x3e080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2704794b834dSVidya Sagar <0x32 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2705794b834dSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2706ec142c44SVidya Sagar 2707ec142c44SVidya Sagar #address-cells = <3>; 2708ec142c44SVidya Sagar #size-cells = <2>; 2709ec142c44SVidya Sagar device_type = "pci"; 2710ec142c44SVidya Sagar num-lanes = <8>; 2711ec142c44SVidya Sagar num-viewport = <8>; 2712ec142c44SVidya Sagar linux,pci-domain = <7>; 2713ec142c44SVidya Sagar 2714ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX2_C7_CORE>; 2715ec142c44SVidya Sagar clock-names = "core"; 2716ec142c44SVidya Sagar 2717ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX2_CORE_7_APB>, 2718ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX2_CORE_7>; 2719ec142c44SVidya Sagar reset-names = "apb", "core"; 2720ec142c44SVidya Sagar 2721ec142c44SVidya Sagar interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2722ec142c44SVidya Sagar <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2723ec142c44SVidya Sagar interrupt-names = "intr", "msi"; 2724ec142c44SVidya Sagar 2725ec142c44SVidya Sagar #interrupt-cells = <1>; 2726ec142c44SVidya Sagar interrupt-map-mask = <0 0 0 0>; 2727ec142c44SVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 2728ec142c44SVidya Sagar 2729ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 7>; 2730ec142c44SVidya Sagar 2731ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2732ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2733ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2734ec142c44SVidya Sagar 2735ec142c44SVidya Sagar bus-range = <0x0 0xff>; 2736ec142c44SVidya Sagar 273724840065SVidya Sagar ranges = <0x43000000 0x30 0x00000000 0x30 0x00000000 0x2 0x28000000>, /* prefetchable memory (8832 MB) */ 2738ec142c44SVidya Sagar <0x02000000 0x0 0x40000000 0x32 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2739ec142c44SVidya Sagar <0x01000000 0x0 0x3e100000 0x00 0x3e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2740ec142c44SVidya Sagar 2741ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE7AR &emc>, 2742ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE7AW &emc>; 2743ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2744ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>; 2745ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2746ec142c44SVidya Sagar dma-coherent; 2747ec142c44SVidya Sagar 2748ec142c44SVidya Sagar status = "disabled"; 2749ec142c44SVidya Sagar }; 2750ec142c44SVidya Sagar 2751ec142c44SVidya Sagar pcie-ep@141e0000 { 2752ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie-ep"; 2753ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8B>; 2754ec142c44SVidya Sagar reg = <0x00 0x141e0000 0x0 0x00020000>, /* appl registers (128K) */ 2755ec142c44SVidya Sagar <0x00 0x3e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2756ec142c44SVidya Sagar <0x00 0x3e080000 0x0 0x00040000>, /* DBI space (256K) */ 2757ec142c44SVidya Sagar <0x2e 0x40000000 0x4 0x00000000>; /* Address Space (16G) */ 2758ec142c44SVidya Sagar reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2759ec142c44SVidya Sagar 2760ec142c44SVidya Sagar num-lanes = <8>; 2761ec142c44SVidya Sagar 2762ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX2_C7_CORE>; 2763ec142c44SVidya Sagar clock-names = "core"; 2764ec142c44SVidya Sagar 2765ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX2_CORE_7_APB>, 2766ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX2_CORE_7>; 2767ec142c44SVidya Sagar reset-names = "apb", "core"; 2768ec142c44SVidya Sagar 2769ec142c44SVidya Sagar interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2770ec142c44SVidya Sagar interrupt-names = "intr"; 2771ec142c44SVidya Sagar 2772ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 7>; 2773ec142c44SVidya Sagar 2774ec142c44SVidya Sagar nvidia,enable-ext-refclk; 2775ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2776ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2777ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2778ec142c44SVidya Sagar 2779ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE7AR &emc>, 2780ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE7AW &emc>; 2781ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2782ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>; 2783ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2784ec142c44SVidya Sagar dma-coherent; 2785ec142c44SVidya Sagar 2786ec142c44SVidya Sagar status = "disabled"; 2787ec142c44SVidya Sagar }; 2788ec142c44SVidya Sagar }; 2789ec142c44SVidya Sagar 27907fa30752SThierry Reding sram@40000000 { 279163944891SThierry Reding compatible = "nvidia,tegra234-sysram", "mmio-sram"; 279298094be1SMikko Perttunen reg = <0x0 0x40000000 0x0 0x80000>; 2793*2838cfddSThierry Reding 279463944891SThierry Reding #address-cells = <1>; 279563944891SThierry Reding #size-cells = <1>; 279698094be1SMikko Perttunen ranges = <0x0 0x0 0x40000000 0x80000>; 2797*2838cfddSThierry Reding 279861192a9dSMikko Perttunen no-memory-wc; 279963944891SThierry Reding 280098094be1SMikko Perttunen cpu_bpmp_tx: sram@70000 { 280198094be1SMikko Perttunen reg = <0x70000 0x1000>; 280263944891SThierry Reding label = "cpu-bpmp-tx"; 280363944891SThierry Reding pool; 280463944891SThierry Reding }; 280563944891SThierry Reding 280698094be1SMikko Perttunen cpu_bpmp_rx: sram@71000 { 280798094be1SMikko Perttunen reg = <0x71000 0x1000>; 280863944891SThierry Reding label = "cpu-bpmp-rx"; 280963944891SThierry Reding pool; 281063944891SThierry Reding }; 281163944891SThierry Reding }; 281263944891SThierry Reding 281363944891SThierry Reding bpmp: bpmp { 281463944891SThierry Reding compatible = "nvidia,tegra234-bpmp", "nvidia,tegra186-bpmp"; 281563944891SThierry Reding mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 281663944891SThierry Reding TEGRA_HSP_DB_MASTER_BPMP>; 28177fa30752SThierry Reding shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; 281863944891SThierry Reding #clock-cells = <1>; 281963944891SThierry Reding #reset-cells = <1>; 282063944891SThierry Reding #power-domain-cells = <1>; 28216de481e5SThierry Reding interconnects = <&mc TEGRA234_MEMORY_CLIENT_BPMPR &emc>, 28226de481e5SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_BPMPW &emc>, 28236de481e5SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAR &emc>, 28246de481e5SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAW &emc>; 28256de481e5SThierry Reding interconnect-names = "read", "write", "dma-mem", "dma-write"; 28265710e16aSThierry Reding iommus = <&smmu_niso1 TEGRA234_SID_BPMP>; 282763944891SThierry Reding 282863944891SThierry Reding bpmp_i2c: i2c { 282963944891SThierry Reding compatible = "nvidia,tegra186-bpmp-i2c"; 283063944891SThierry Reding nvidia,bpmp-bus-id = <5>; 283163944891SThierry Reding #address-cells = <1>; 283263944891SThierry Reding #size-cells = <0>; 283363944891SThierry Reding }; 283463944891SThierry Reding }; 283563944891SThierry Reding 283663944891SThierry Reding cpus { 283763944891SThierry Reding #address-cells = <1>; 283863944891SThierry Reding #size-cells = <0>; 283963944891SThierry Reding 2840a12cf5c3SThierry Reding cpu0_0: cpu@0 { 2841a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 284263944891SThierry Reding device_type = "cpu"; 2843a12cf5c3SThierry Reding reg = <0x00000>; 284463944891SThierry Reding 284563944891SThierry Reding enable-method = "psci"; 2846a12cf5c3SThierry Reding 2847a12cf5c3SThierry Reding i-cache-size = <65536>; 2848a12cf5c3SThierry Reding i-cache-line-size = <64>; 2849a12cf5c3SThierry Reding i-cache-sets = <256>; 2850a12cf5c3SThierry Reding d-cache-size = <65536>; 2851a12cf5c3SThierry Reding d-cache-line-size = <64>; 2852a12cf5c3SThierry Reding d-cache-sets = <256>; 2853a12cf5c3SThierry Reding next-level-cache = <&l2c0_0>; 285463944891SThierry Reding }; 2855a12cf5c3SThierry Reding 2856a12cf5c3SThierry Reding cpu0_1: cpu@100 { 2857a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 2858a12cf5c3SThierry Reding device_type = "cpu"; 2859a12cf5c3SThierry Reding reg = <0x00100>; 2860a12cf5c3SThierry Reding 2861a12cf5c3SThierry Reding enable-method = "psci"; 2862a12cf5c3SThierry Reding 2863a12cf5c3SThierry Reding i-cache-size = <65536>; 2864a12cf5c3SThierry Reding i-cache-line-size = <64>; 2865a12cf5c3SThierry Reding i-cache-sets = <256>; 2866a12cf5c3SThierry Reding d-cache-size = <65536>; 2867a12cf5c3SThierry Reding d-cache-line-size = <64>; 2868a12cf5c3SThierry Reding d-cache-sets = <256>; 2869a12cf5c3SThierry Reding next-level-cache = <&l2c0_1>; 2870a12cf5c3SThierry Reding }; 2871a12cf5c3SThierry Reding 2872a12cf5c3SThierry Reding cpu0_2: cpu@200 { 2873a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 2874a12cf5c3SThierry Reding device_type = "cpu"; 2875a12cf5c3SThierry Reding reg = <0x00200>; 2876a12cf5c3SThierry Reding 2877a12cf5c3SThierry Reding enable-method = "psci"; 2878a12cf5c3SThierry Reding 2879a12cf5c3SThierry Reding i-cache-size = <65536>; 2880a12cf5c3SThierry Reding i-cache-line-size = <64>; 2881a12cf5c3SThierry Reding i-cache-sets = <256>; 2882a12cf5c3SThierry Reding d-cache-size = <65536>; 2883a12cf5c3SThierry Reding d-cache-line-size = <64>; 2884a12cf5c3SThierry Reding d-cache-sets = <256>; 2885a12cf5c3SThierry Reding next-level-cache = <&l2c0_2>; 2886a12cf5c3SThierry Reding }; 2887a12cf5c3SThierry Reding 2888a12cf5c3SThierry Reding cpu0_3: cpu@300 { 2889a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 2890a12cf5c3SThierry Reding device_type = "cpu"; 2891a12cf5c3SThierry Reding reg = <0x00300>; 2892a12cf5c3SThierry Reding 2893a12cf5c3SThierry Reding enable-method = "psci"; 2894a12cf5c3SThierry Reding 2895a12cf5c3SThierry Reding i-cache-size = <65536>; 2896a12cf5c3SThierry Reding i-cache-line-size = <64>; 2897a12cf5c3SThierry Reding i-cache-sets = <256>; 2898a12cf5c3SThierry Reding d-cache-size = <65536>; 2899a12cf5c3SThierry Reding d-cache-line-size = <64>; 2900a12cf5c3SThierry Reding d-cache-sets = <256>; 2901a12cf5c3SThierry Reding next-level-cache = <&l2c0_3>; 2902a12cf5c3SThierry Reding }; 2903a12cf5c3SThierry Reding 2904a12cf5c3SThierry Reding cpu1_0: cpu@10000 { 2905a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 2906a12cf5c3SThierry Reding device_type = "cpu"; 2907a12cf5c3SThierry Reding reg = <0x10000>; 2908a12cf5c3SThierry Reding 2909a12cf5c3SThierry Reding enable-method = "psci"; 2910a12cf5c3SThierry Reding 2911a12cf5c3SThierry Reding i-cache-size = <65536>; 2912a12cf5c3SThierry Reding i-cache-line-size = <64>; 2913a12cf5c3SThierry Reding i-cache-sets = <256>; 2914a12cf5c3SThierry Reding d-cache-size = <65536>; 2915a12cf5c3SThierry Reding d-cache-line-size = <64>; 2916a12cf5c3SThierry Reding d-cache-sets = <256>; 2917a12cf5c3SThierry Reding next-level-cache = <&l2c1_0>; 2918a12cf5c3SThierry Reding }; 2919a12cf5c3SThierry Reding 2920a12cf5c3SThierry Reding cpu1_1: cpu@10100 { 2921a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 2922a12cf5c3SThierry Reding device_type = "cpu"; 2923a12cf5c3SThierry Reding reg = <0x10100>; 2924a12cf5c3SThierry Reding 2925a12cf5c3SThierry Reding enable-method = "psci"; 2926a12cf5c3SThierry Reding 2927a12cf5c3SThierry Reding i-cache-size = <65536>; 2928a12cf5c3SThierry Reding i-cache-line-size = <64>; 2929a12cf5c3SThierry Reding i-cache-sets = <256>; 2930a12cf5c3SThierry Reding d-cache-size = <65536>; 2931a12cf5c3SThierry Reding d-cache-line-size = <64>; 2932a12cf5c3SThierry Reding d-cache-sets = <256>; 2933a12cf5c3SThierry Reding next-level-cache = <&l2c1_1>; 2934a12cf5c3SThierry Reding }; 2935a12cf5c3SThierry Reding 2936a12cf5c3SThierry Reding cpu1_2: cpu@10200 { 2937a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 2938a12cf5c3SThierry Reding device_type = "cpu"; 2939a12cf5c3SThierry Reding reg = <0x10200>; 2940a12cf5c3SThierry Reding 2941a12cf5c3SThierry Reding enable-method = "psci"; 2942a12cf5c3SThierry Reding 2943a12cf5c3SThierry Reding i-cache-size = <65536>; 2944a12cf5c3SThierry Reding i-cache-line-size = <64>; 2945a12cf5c3SThierry Reding i-cache-sets = <256>; 2946a12cf5c3SThierry Reding d-cache-size = <65536>; 2947a12cf5c3SThierry Reding d-cache-line-size = <64>; 2948a12cf5c3SThierry Reding d-cache-sets = <256>; 2949a12cf5c3SThierry Reding next-level-cache = <&l2c1_2>; 2950a12cf5c3SThierry Reding }; 2951a12cf5c3SThierry Reding 2952a12cf5c3SThierry Reding cpu1_3: cpu@10300 { 2953a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 2954a12cf5c3SThierry Reding device_type = "cpu"; 2955a12cf5c3SThierry Reding reg = <0x10300>; 2956a12cf5c3SThierry Reding 2957a12cf5c3SThierry Reding enable-method = "psci"; 2958a12cf5c3SThierry Reding 2959a12cf5c3SThierry Reding i-cache-size = <65536>; 2960a12cf5c3SThierry Reding i-cache-line-size = <64>; 2961a12cf5c3SThierry Reding i-cache-sets = <256>; 2962a12cf5c3SThierry Reding d-cache-size = <65536>; 2963a12cf5c3SThierry Reding d-cache-line-size = <64>; 2964a12cf5c3SThierry Reding d-cache-sets = <256>; 2965a12cf5c3SThierry Reding next-level-cache = <&l2c1_3>; 2966a12cf5c3SThierry Reding }; 2967a12cf5c3SThierry Reding 2968a12cf5c3SThierry Reding cpu2_0: cpu@20000 { 2969a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 2970a12cf5c3SThierry Reding device_type = "cpu"; 2971a12cf5c3SThierry Reding reg = <0x20000>; 2972a12cf5c3SThierry Reding 2973a12cf5c3SThierry Reding enable-method = "psci"; 2974a12cf5c3SThierry Reding 2975a12cf5c3SThierry Reding i-cache-size = <65536>; 2976a12cf5c3SThierry Reding i-cache-line-size = <64>; 2977a12cf5c3SThierry Reding i-cache-sets = <256>; 2978a12cf5c3SThierry Reding d-cache-size = <65536>; 2979a12cf5c3SThierry Reding d-cache-line-size = <64>; 2980a12cf5c3SThierry Reding d-cache-sets = <256>; 2981a12cf5c3SThierry Reding next-level-cache = <&l2c2_0>; 2982a12cf5c3SThierry Reding }; 2983a12cf5c3SThierry Reding 2984a12cf5c3SThierry Reding cpu2_1: cpu@20100 { 2985a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 2986a12cf5c3SThierry Reding device_type = "cpu"; 2987a12cf5c3SThierry Reding reg = <0x20100>; 2988a12cf5c3SThierry Reding 2989a12cf5c3SThierry Reding enable-method = "psci"; 2990a12cf5c3SThierry Reding 2991a12cf5c3SThierry Reding i-cache-size = <65536>; 2992a12cf5c3SThierry Reding i-cache-line-size = <64>; 2993a12cf5c3SThierry Reding i-cache-sets = <256>; 2994a12cf5c3SThierry Reding d-cache-size = <65536>; 2995a12cf5c3SThierry Reding d-cache-line-size = <64>; 2996a12cf5c3SThierry Reding d-cache-sets = <256>; 2997a12cf5c3SThierry Reding next-level-cache = <&l2c2_1>; 2998a12cf5c3SThierry Reding }; 2999a12cf5c3SThierry Reding 3000a12cf5c3SThierry Reding cpu2_2: cpu@20200 { 3001a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 3002a12cf5c3SThierry Reding device_type = "cpu"; 3003a12cf5c3SThierry Reding reg = <0x20200>; 3004a12cf5c3SThierry Reding 3005a12cf5c3SThierry Reding enable-method = "psci"; 3006a12cf5c3SThierry Reding 3007a12cf5c3SThierry Reding i-cache-size = <65536>; 3008a12cf5c3SThierry Reding i-cache-line-size = <64>; 3009a12cf5c3SThierry Reding i-cache-sets = <256>; 3010a12cf5c3SThierry Reding d-cache-size = <65536>; 3011a12cf5c3SThierry Reding d-cache-line-size = <64>; 3012a12cf5c3SThierry Reding d-cache-sets = <256>; 3013a12cf5c3SThierry Reding next-level-cache = <&l2c2_2>; 3014a12cf5c3SThierry Reding }; 3015a12cf5c3SThierry Reding 3016a12cf5c3SThierry Reding cpu2_3: cpu@20300 { 3017a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 3018a12cf5c3SThierry Reding device_type = "cpu"; 3019a12cf5c3SThierry Reding reg = <0x20300>; 3020a12cf5c3SThierry Reding 3021a12cf5c3SThierry Reding enable-method = "psci"; 3022a12cf5c3SThierry Reding 3023a12cf5c3SThierry Reding i-cache-size = <65536>; 3024a12cf5c3SThierry Reding i-cache-line-size = <64>; 3025a12cf5c3SThierry Reding i-cache-sets = <256>; 3026a12cf5c3SThierry Reding d-cache-size = <65536>; 3027a12cf5c3SThierry Reding d-cache-line-size = <64>; 3028a12cf5c3SThierry Reding d-cache-sets = <256>; 3029a12cf5c3SThierry Reding next-level-cache = <&l2c2_3>; 3030a12cf5c3SThierry Reding }; 3031a12cf5c3SThierry Reding 3032a12cf5c3SThierry Reding cpu-map { 3033a12cf5c3SThierry Reding cluster0 { 3034a12cf5c3SThierry Reding core0 { 3035a12cf5c3SThierry Reding cpu = <&cpu0_0>; 3036a12cf5c3SThierry Reding }; 3037a12cf5c3SThierry Reding 3038a12cf5c3SThierry Reding core1 { 3039a12cf5c3SThierry Reding cpu = <&cpu0_1>; 3040a12cf5c3SThierry Reding }; 3041a12cf5c3SThierry Reding 3042a12cf5c3SThierry Reding core2 { 3043a12cf5c3SThierry Reding cpu = <&cpu0_2>; 3044a12cf5c3SThierry Reding }; 3045a12cf5c3SThierry Reding 3046a12cf5c3SThierry Reding core3 { 3047a12cf5c3SThierry Reding cpu = <&cpu0_3>; 3048a12cf5c3SThierry Reding }; 3049a12cf5c3SThierry Reding }; 3050a12cf5c3SThierry Reding 3051a12cf5c3SThierry Reding cluster1 { 3052a12cf5c3SThierry Reding core0 { 3053a12cf5c3SThierry Reding cpu = <&cpu1_0>; 3054a12cf5c3SThierry Reding }; 3055a12cf5c3SThierry Reding 3056a12cf5c3SThierry Reding core1 { 3057a12cf5c3SThierry Reding cpu = <&cpu1_1>; 3058a12cf5c3SThierry Reding }; 3059a12cf5c3SThierry Reding 3060a12cf5c3SThierry Reding core2 { 3061a12cf5c3SThierry Reding cpu = <&cpu1_2>; 3062a12cf5c3SThierry Reding }; 3063a12cf5c3SThierry Reding 3064a12cf5c3SThierry Reding core3 { 3065a12cf5c3SThierry Reding cpu = <&cpu1_3>; 3066a12cf5c3SThierry Reding }; 3067a12cf5c3SThierry Reding }; 3068a12cf5c3SThierry Reding 3069a12cf5c3SThierry Reding cluster2 { 3070a12cf5c3SThierry Reding core0 { 3071a12cf5c3SThierry Reding cpu = <&cpu2_0>; 3072a12cf5c3SThierry Reding }; 3073a12cf5c3SThierry Reding 3074a12cf5c3SThierry Reding core1 { 3075a12cf5c3SThierry Reding cpu = <&cpu2_1>; 3076a12cf5c3SThierry Reding }; 3077a12cf5c3SThierry Reding 3078a12cf5c3SThierry Reding core2 { 3079a12cf5c3SThierry Reding cpu = <&cpu2_2>; 3080a12cf5c3SThierry Reding }; 3081a12cf5c3SThierry Reding 3082a12cf5c3SThierry Reding core3 { 3083a12cf5c3SThierry Reding cpu = <&cpu2_3>; 3084a12cf5c3SThierry Reding }; 3085a12cf5c3SThierry Reding }; 3086a12cf5c3SThierry Reding }; 3087a12cf5c3SThierry Reding 3088a12cf5c3SThierry Reding l2c0_0: l2-cache00 { 308927f1568bSPierre Gondois compatible = "cache"; 3090a12cf5c3SThierry Reding cache-size = <262144>; 3091a12cf5c3SThierry Reding cache-line-size = <64>; 3092a12cf5c3SThierry Reding cache-sets = <512>; 3093a12cf5c3SThierry Reding cache-unified; 309427f1568bSPierre Gondois cache-level = <2>; 3095a12cf5c3SThierry Reding next-level-cache = <&l3c0>; 3096a12cf5c3SThierry Reding }; 3097a12cf5c3SThierry Reding 3098a12cf5c3SThierry Reding l2c0_1: l2-cache01 { 309927f1568bSPierre Gondois compatible = "cache"; 3100a12cf5c3SThierry Reding cache-size = <262144>; 3101a12cf5c3SThierry Reding cache-line-size = <64>; 3102a12cf5c3SThierry Reding cache-sets = <512>; 3103a12cf5c3SThierry Reding cache-unified; 310427f1568bSPierre Gondois cache-level = <2>; 3105a12cf5c3SThierry Reding next-level-cache = <&l3c0>; 3106a12cf5c3SThierry Reding }; 3107a12cf5c3SThierry Reding 3108a12cf5c3SThierry Reding l2c0_2: l2-cache02 { 310927f1568bSPierre Gondois compatible = "cache"; 3110a12cf5c3SThierry Reding cache-size = <262144>; 3111a12cf5c3SThierry Reding cache-line-size = <64>; 3112a12cf5c3SThierry Reding cache-sets = <512>; 3113a12cf5c3SThierry Reding cache-unified; 311427f1568bSPierre Gondois cache-level = <2>; 3115a12cf5c3SThierry Reding next-level-cache = <&l3c0>; 3116a12cf5c3SThierry Reding }; 3117a12cf5c3SThierry Reding 3118a12cf5c3SThierry Reding l2c0_3: l2-cache03 { 311927f1568bSPierre Gondois compatible = "cache"; 3120a12cf5c3SThierry Reding cache-size = <262144>; 3121a12cf5c3SThierry Reding cache-line-size = <64>; 3122a12cf5c3SThierry Reding cache-sets = <512>; 3123a12cf5c3SThierry Reding cache-unified; 312427f1568bSPierre Gondois cache-level = <2>; 3125a12cf5c3SThierry Reding next-level-cache = <&l3c0>; 3126a12cf5c3SThierry Reding }; 3127a12cf5c3SThierry Reding 3128a12cf5c3SThierry Reding l2c1_0: l2-cache10 { 312927f1568bSPierre Gondois compatible = "cache"; 3130a12cf5c3SThierry Reding cache-size = <262144>; 3131a12cf5c3SThierry Reding cache-line-size = <64>; 3132a12cf5c3SThierry Reding cache-sets = <512>; 3133a12cf5c3SThierry Reding cache-unified; 313427f1568bSPierre Gondois cache-level = <2>; 3135a12cf5c3SThierry Reding next-level-cache = <&l3c1>; 3136a12cf5c3SThierry Reding }; 3137a12cf5c3SThierry Reding 3138a12cf5c3SThierry Reding l2c1_1: l2-cache11 { 313927f1568bSPierre Gondois compatible = "cache"; 3140a12cf5c3SThierry Reding cache-size = <262144>; 3141a12cf5c3SThierry Reding cache-line-size = <64>; 3142a12cf5c3SThierry Reding cache-sets = <512>; 3143a12cf5c3SThierry Reding cache-unified; 314427f1568bSPierre Gondois cache-level = <2>; 3145a12cf5c3SThierry Reding next-level-cache = <&l3c1>; 3146a12cf5c3SThierry Reding }; 3147a12cf5c3SThierry Reding 3148a12cf5c3SThierry Reding l2c1_2: l2-cache12 { 314927f1568bSPierre Gondois compatible = "cache"; 3150a12cf5c3SThierry Reding cache-size = <262144>; 3151a12cf5c3SThierry Reding cache-line-size = <64>; 3152a12cf5c3SThierry Reding cache-sets = <512>; 3153a12cf5c3SThierry Reding cache-unified; 315427f1568bSPierre Gondois cache-level = <2>; 3155a12cf5c3SThierry Reding next-level-cache = <&l3c1>; 3156a12cf5c3SThierry Reding }; 3157a12cf5c3SThierry Reding 3158a12cf5c3SThierry Reding l2c1_3: l2-cache13 { 315927f1568bSPierre Gondois compatible = "cache"; 3160a12cf5c3SThierry Reding cache-size = <262144>; 3161a12cf5c3SThierry Reding cache-line-size = <64>; 3162a12cf5c3SThierry Reding cache-sets = <512>; 3163a12cf5c3SThierry Reding cache-unified; 316427f1568bSPierre Gondois cache-level = <2>; 3165a12cf5c3SThierry Reding next-level-cache = <&l3c1>; 3166a12cf5c3SThierry Reding }; 3167a12cf5c3SThierry Reding 3168a12cf5c3SThierry Reding l2c2_0: l2-cache20 { 316927f1568bSPierre Gondois compatible = "cache"; 3170a12cf5c3SThierry Reding cache-size = <262144>; 3171a12cf5c3SThierry Reding cache-line-size = <64>; 3172a12cf5c3SThierry Reding cache-sets = <512>; 3173a12cf5c3SThierry Reding cache-unified; 317427f1568bSPierre Gondois cache-level = <2>; 3175a12cf5c3SThierry Reding next-level-cache = <&l3c2>; 3176a12cf5c3SThierry Reding }; 3177a12cf5c3SThierry Reding 3178a12cf5c3SThierry Reding l2c2_1: l2-cache21 { 317927f1568bSPierre Gondois compatible = "cache"; 3180a12cf5c3SThierry Reding cache-size = <262144>; 3181a12cf5c3SThierry Reding cache-line-size = <64>; 3182a12cf5c3SThierry Reding cache-sets = <512>; 3183a12cf5c3SThierry Reding cache-unified; 318427f1568bSPierre Gondois cache-level = <2>; 3185a12cf5c3SThierry Reding next-level-cache = <&l3c2>; 3186a12cf5c3SThierry Reding }; 3187a12cf5c3SThierry Reding 3188a12cf5c3SThierry Reding l2c2_2: l2-cache22 { 318927f1568bSPierre Gondois compatible = "cache"; 3190a12cf5c3SThierry Reding cache-size = <262144>; 3191a12cf5c3SThierry Reding cache-line-size = <64>; 3192a12cf5c3SThierry Reding cache-sets = <512>; 3193a12cf5c3SThierry Reding cache-unified; 319427f1568bSPierre Gondois cache-level = <2>; 3195a12cf5c3SThierry Reding next-level-cache = <&l3c2>; 3196a12cf5c3SThierry Reding }; 3197a12cf5c3SThierry Reding 3198a12cf5c3SThierry Reding l2c2_3: l2-cache23 { 319927f1568bSPierre Gondois compatible = "cache"; 3200a12cf5c3SThierry Reding cache-size = <262144>; 3201a12cf5c3SThierry Reding cache-line-size = <64>; 3202a12cf5c3SThierry Reding cache-sets = <512>; 3203a12cf5c3SThierry Reding cache-unified; 320427f1568bSPierre Gondois cache-level = <2>; 3205a12cf5c3SThierry Reding next-level-cache = <&l3c2>; 3206a12cf5c3SThierry Reding }; 3207a12cf5c3SThierry Reding 3208a12cf5c3SThierry Reding l3c0: l3-cache0 { 320927f1568bSPierre Gondois compatible = "cache"; 321027f1568bSPierre Gondois cache-unified; 3211a12cf5c3SThierry Reding cache-size = <2097152>; 3212a12cf5c3SThierry Reding cache-line-size = <64>; 3213a12cf5c3SThierry Reding cache-sets = <2048>; 321427f1568bSPierre Gondois cache-level = <3>; 3215a12cf5c3SThierry Reding }; 3216a12cf5c3SThierry Reding 3217a12cf5c3SThierry Reding l3c1: l3-cache1 { 321827f1568bSPierre Gondois compatible = "cache"; 321927f1568bSPierre Gondois cache-unified; 3220a12cf5c3SThierry Reding cache-size = <2097152>; 3221a12cf5c3SThierry Reding cache-line-size = <64>; 3222a12cf5c3SThierry Reding cache-sets = <2048>; 322327f1568bSPierre Gondois cache-level = <3>; 3224a12cf5c3SThierry Reding }; 3225a12cf5c3SThierry Reding 3226a12cf5c3SThierry Reding l3c2: l3-cache2 { 322727f1568bSPierre Gondois compatible = "cache"; 322827f1568bSPierre Gondois cache-unified; 3229a12cf5c3SThierry Reding cache-size = <2097152>; 3230a12cf5c3SThierry Reding cache-line-size = <64>; 3231a12cf5c3SThierry Reding cache-sets = <2048>; 323227f1568bSPierre Gondois cache-level = <3>; 3233a12cf5c3SThierry Reding }; 3234a12cf5c3SThierry Reding }; 3235a12cf5c3SThierry Reding 3236a12cf5c3SThierry Reding pmu { 3237a12cf5c3SThierry Reding compatible = "arm,cortex-a78-pmu"; 3238a12cf5c3SThierry Reding interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 3239a12cf5c3SThierry Reding status = "okay"; 324063944891SThierry Reding }; 324163944891SThierry Reding 324263944891SThierry Reding psci { 324363944891SThierry Reding compatible = "arm,psci-1.0"; 324463944891SThierry Reding status = "okay"; 324563944891SThierry Reding method = "smc"; 324663944891SThierry Reding }; 324763944891SThierry Reding 324806ad2ec4SMikko Perttunen tcu: serial { 324906ad2ec4SMikko Perttunen compatible = "nvidia,tegra234-tcu", "nvidia,tegra194-tcu"; 325006ad2ec4SMikko Perttunen mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 325106ad2ec4SMikko Perttunen <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 325206ad2ec4SMikko Perttunen mbox-names = "rx", "tx"; 325306ad2ec4SMikko Perttunen status = "disabled"; 325406ad2ec4SMikko Perttunen }; 325506ad2ec4SMikko Perttunen 325609614acdSSameer Pujar sound { 325709614acdSSameer Pujar status = "disabled"; 325809614acdSSameer Pujar 325909614acdSSameer Pujar clocks = <&bpmp TEGRA234_CLK_PLLA>, 326009614acdSSameer Pujar <&bpmp TEGRA234_CLK_PLLA_OUT0>; 326109614acdSSameer Pujar clock-names = "pll_a", "plla_out0"; 326209614acdSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_PLLA>, 326309614acdSSameer Pujar <&bpmp TEGRA234_CLK_PLLA_OUT0>, 326409614acdSSameer Pujar <&bpmp TEGRA234_CLK_AUD_MCLK>; 326509614acdSSameer Pujar assigned-clock-parents = <0>, 326609614acdSSameer Pujar <&bpmp TEGRA234_CLK_PLLA>, 326709614acdSSameer Pujar <&bpmp TEGRA234_CLK_PLLA_OUT0>; 326809614acdSSameer Pujar }; 326909614acdSSameer Pujar 327063944891SThierry Reding timer { 327163944891SThierry Reding compatible = "arm,armv8-timer"; 327263944891SThierry Reding interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 327363944891SThierry Reding <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 327463944891SThierry Reding <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 327563944891SThierry Reding <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 327663944891SThierry Reding interrupt-parent = <&gic>; 327763944891SThierry Reding always-on; 327863944891SThierry Reding }; 327963944891SThierry Reding}; 3280