163944891SThierry Reding// SPDX-License-Identifier: GPL-2.0 263944891SThierry Reding 363944891SThierry Reding#include <dt-bindings/clock/tegra234-clock.h> 4699349e0SThierry Reding#include <dt-bindings/gpio/tegra234-gpio.h> 563944891SThierry Reding#include <dt-bindings/interrupt-controller/arm-gic.h> 663944891SThierry Reding#include <dt-bindings/mailbox/tegra186-hsp.h> 7eed280dfSThierry Reding#include <dt-bindings/memory/tegra234-mc.h> 8dc94a94dSSameer Pujar#include <dt-bindings/power/tegra234-powergate.h> 963944891SThierry Reding#include <dt-bindings/reset/tegra234-reset.h> 1063944891SThierry Reding 1163944891SThierry Reding/ { 1263944891SThierry Reding compatible = "nvidia,tegra234"; 1363944891SThierry Reding interrupt-parent = <&gic>; 1463944891SThierry Reding #address-cells = <2>; 1563944891SThierry Reding #size-cells = <2>; 1663944891SThierry Reding 1763944891SThierry Reding bus@0 { 1863944891SThierry Reding compatible = "simple-bus"; 1963944891SThierry Reding #address-cells = <1>; 2063944891SThierry Reding #size-cells = <1>; 2163944891SThierry Reding 2263944891SThierry Reding ranges = <0x0 0x0 0x0 0x40000000>; 2363944891SThierry Reding 2460d2016aSAkhil R gpcdma: dma-controller@2600000 { 25f7b93a08SAkhil R compatible = "nvidia,tegra234-gpcdma", 2660d2016aSAkhil R "nvidia,tegra186-gpcdma"; 2760d2016aSAkhil R reg = <0x2600000 0x210000>; 2860d2016aSAkhil R resets = <&bpmp TEGRA234_RESET_GPCDMA>; 2960d2016aSAkhil R reset-names = "gpcdma"; 3060d2016aSAkhil R interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 3160d2016aSAkhil R <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 3260d2016aSAkhil R <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 3360d2016aSAkhil R <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 3460d2016aSAkhil R <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 3560d2016aSAkhil R <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 3660d2016aSAkhil R <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 3760d2016aSAkhil R <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 3860d2016aSAkhil R <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 3960d2016aSAkhil R <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 4060d2016aSAkhil R <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 4160d2016aSAkhil R <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 4260d2016aSAkhil R <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 4360d2016aSAkhil R <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 4460d2016aSAkhil R <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 4560d2016aSAkhil R <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 4660d2016aSAkhil R <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 4760d2016aSAkhil R <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 4860d2016aSAkhil R <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 4960d2016aSAkhil R <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 5060d2016aSAkhil R <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 5160d2016aSAkhil R <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 5260d2016aSAkhil R <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 5360d2016aSAkhil R <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 5460d2016aSAkhil R <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 5560d2016aSAkhil R <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 5660d2016aSAkhil R <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 5760d2016aSAkhil R <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 5860d2016aSAkhil R <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 5960d2016aSAkhil R <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 6060d2016aSAkhil R <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 6160d2016aSAkhil R #dma-cells = <1>; 6260d2016aSAkhil R iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 6360d2016aSAkhil R dma-coherent; 6460d2016aSAkhil R }; 6560d2016aSAkhil R 66dc94a94dSSameer Pujar aconnect@2900000 { 67dc94a94dSSameer Pujar compatible = "nvidia,tegra234-aconnect", 68dc94a94dSSameer Pujar "nvidia,tegra210-aconnect"; 69dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_APE>, 70dc94a94dSSameer Pujar <&bpmp TEGRA234_CLK_APB2APE>; 71dc94a94dSSameer Pujar clock-names = "ape", "apb2ape"; 72dc94a94dSSameer Pujar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_AUD>; 73dc94a94dSSameer Pujar #address-cells = <1>; 74dc94a94dSSameer Pujar #size-cells = <1>; 75dc94a94dSSameer Pujar ranges = <0x02900000 0x02900000 0x200000>; 76dc94a94dSSameer Pujar status = "disabled"; 77dc94a94dSSameer Pujar 78dc94a94dSSameer Pujar tegra_ahub: ahub@2900800 { 79dc94a94dSSameer Pujar compatible = "nvidia,tegra234-ahub"; 80dc94a94dSSameer Pujar reg = <0x02900800 0x800>; 81dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_AHUB>; 82dc94a94dSSameer Pujar clock-names = "ahub"; 83dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_AHUB>; 84dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 85dc94a94dSSameer Pujar #address-cells = <1>; 86dc94a94dSSameer Pujar #size-cells = <1>; 87dc94a94dSSameer Pujar ranges = <0x02900800 0x02900800 0x11800>; 88dc94a94dSSameer Pujar status = "disabled"; 89dc94a94dSSameer Pujar 90dc94a94dSSameer Pujar tegra_i2s1: i2s@2901000 { 91dc94a94dSSameer Pujar compatible = "nvidia,tegra234-i2s", 92dc94a94dSSameer Pujar "nvidia,tegra210-i2s"; 93dc94a94dSSameer Pujar reg = <0x2901000 0x100>; 94dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_I2S1>, 95dc94a94dSSameer Pujar <&bpmp TEGRA234_CLK_I2S1_SYNC_INPUT>; 96dc94a94dSSameer Pujar clock-names = "i2s", "sync_input"; 97dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_I2S1>; 98dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 99dc94a94dSSameer Pujar assigned-clock-rates = <1536000>; 100dc94a94dSSameer Pujar sound-name-prefix = "I2S1"; 101dc94a94dSSameer Pujar status = "disabled"; 102dc94a94dSSameer Pujar }; 103dc94a94dSSameer Pujar 104dc94a94dSSameer Pujar tegra_i2s2: i2s@2901100 { 105dc94a94dSSameer Pujar compatible = "nvidia,tegra234-i2s", 106dc94a94dSSameer Pujar "nvidia,tegra210-i2s"; 107dc94a94dSSameer Pujar reg = <0x2901100 0x100>; 108dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_I2S2>, 109dc94a94dSSameer Pujar <&bpmp TEGRA234_CLK_I2S2_SYNC_INPUT>; 110dc94a94dSSameer Pujar clock-names = "i2s", "sync_input"; 111dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_I2S2>; 112dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 113dc94a94dSSameer Pujar assigned-clock-rates = <1536000>; 114dc94a94dSSameer Pujar sound-name-prefix = "I2S2"; 115dc94a94dSSameer Pujar status = "disabled"; 116dc94a94dSSameer Pujar }; 117dc94a94dSSameer Pujar 118dc94a94dSSameer Pujar tegra_i2s3: i2s@2901200 { 119dc94a94dSSameer Pujar compatible = "nvidia,tegra234-i2s", 120dc94a94dSSameer Pujar "nvidia,tegra210-i2s"; 121dc94a94dSSameer Pujar reg = <0x2901200 0x100>; 122dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_I2S3>, 123dc94a94dSSameer Pujar <&bpmp TEGRA234_CLK_I2S3_SYNC_INPUT>; 124dc94a94dSSameer Pujar clock-names = "i2s", "sync_input"; 125dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_I2S3>; 126dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 127dc94a94dSSameer Pujar assigned-clock-rates = <1536000>; 128dc94a94dSSameer Pujar sound-name-prefix = "I2S3"; 129dc94a94dSSameer Pujar status = "disabled"; 130dc94a94dSSameer Pujar }; 131dc94a94dSSameer Pujar 132dc94a94dSSameer Pujar tegra_i2s4: i2s@2901300 { 133dc94a94dSSameer Pujar compatible = "nvidia,tegra234-i2s", 134dc94a94dSSameer Pujar "nvidia,tegra210-i2s"; 135dc94a94dSSameer Pujar reg = <0x2901300 0x100>; 136dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_I2S4>, 137dc94a94dSSameer Pujar <&bpmp TEGRA234_CLK_I2S4_SYNC_INPUT>; 138dc94a94dSSameer Pujar clock-names = "i2s", "sync_input"; 139dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_I2S4>; 140dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 141dc94a94dSSameer Pujar assigned-clock-rates = <1536000>; 142dc94a94dSSameer Pujar sound-name-prefix = "I2S4"; 143dc94a94dSSameer Pujar status = "disabled"; 144dc94a94dSSameer Pujar }; 145dc94a94dSSameer Pujar 146dc94a94dSSameer Pujar tegra_i2s5: i2s@2901400 { 147dc94a94dSSameer Pujar compatible = "nvidia,tegra234-i2s", 148dc94a94dSSameer Pujar "nvidia,tegra210-i2s"; 149dc94a94dSSameer Pujar reg = <0x2901400 0x100>; 150dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_I2S5>, 151dc94a94dSSameer Pujar <&bpmp TEGRA234_CLK_I2S5_SYNC_INPUT>; 152dc94a94dSSameer Pujar clock-names = "i2s", "sync_input"; 153dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_I2S5>; 154dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 155dc94a94dSSameer Pujar assigned-clock-rates = <1536000>; 156dc94a94dSSameer Pujar sound-name-prefix = "I2S5"; 157dc94a94dSSameer Pujar status = "disabled"; 158dc94a94dSSameer Pujar }; 159dc94a94dSSameer Pujar 160dc94a94dSSameer Pujar tegra_i2s6: i2s@2901500 { 161dc94a94dSSameer Pujar compatible = "nvidia,tegra234-i2s", 162dc94a94dSSameer Pujar "nvidia,tegra210-i2s"; 163dc94a94dSSameer Pujar reg = <0x2901500 0x100>; 164dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_I2S6>, 165dc94a94dSSameer Pujar <&bpmp TEGRA234_CLK_I2S6_SYNC_INPUT>; 166dc94a94dSSameer Pujar clock-names = "i2s", "sync_input"; 167dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_I2S6>; 168dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 169dc94a94dSSameer Pujar assigned-clock-rates = <1536000>; 170dc94a94dSSameer Pujar sound-name-prefix = "I2S6"; 171dc94a94dSSameer Pujar status = "disabled"; 172dc94a94dSSameer Pujar }; 173dc94a94dSSameer Pujar 174dc94a94dSSameer Pujar tegra_sfc1: sfc@2902000 { 175dc94a94dSSameer Pujar compatible = "nvidia,tegra234-sfc", 176dc94a94dSSameer Pujar "nvidia,tegra210-sfc"; 177dc94a94dSSameer Pujar reg = <0x2902000 0x200>; 178dc94a94dSSameer Pujar sound-name-prefix = "SFC1"; 179dc94a94dSSameer Pujar status = "disabled"; 180dc94a94dSSameer Pujar }; 181dc94a94dSSameer Pujar 182dc94a94dSSameer Pujar tegra_sfc2: sfc@2902200 { 183dc94a94dSSameer Pujar compatible = "nvidia,tegra234-sfc", 184dc94a94dSSameer Pujar "nvidia,tegra210-sfc"; 185dc94a94dSSameer Pujar reg = <0x2902200 0x200>; 186dc94a94dSSameer Pujar sound-name-prefix = "SFC2"; 187dc94a94dSSameer Pujar status = "disabled"; 188dc94a94dSSameer Pujar }; 189dc94a94dSSameer Pujar 190dc94a94dSSameer Pujar tegra_sfc3: sfc@2902400 { 191dc94a94dSSameer Pujar compatible = "nvidia,tegra234-sfc", 192dc94a94dSSameer Pujar "nvidia,tegra210-sfc"; 193dc94a94dSSameer Pujar reg = <0x2902400 0x200>; 194dc94a94dSSameer Pujar sound-name-prefix = "SFC3"; 195dc94a94dSSameer Pujar status = "disabled"; 196dc94a94dSSameer Pujar }; 197dc94a94dSSameer Pujar 198dc94a94dSSameer Pujar tegra_sfc4: sfc@2902600 { 199dc94a94dSSameer Pujar compatible = "nvidia,tegra234-sfc", 200dc94a94dSSameer Pujar "nvidia,tegra210-sfc"; 201dc94a94dSSameer Pujar reg = <0x2902600 0x200>; 202dc94a94dSSameer Pujar sound-name-prefix = "SFC4"; 203dc94a94dSSameer Pujar status = "disabled"; 204dc94a94dSSameer Pujar }; 205dc94a94dSSameer Pujar 206dc94a94dSSameer Pujar tegra_amx1: amx@2903000 { 207dc94a94dSSameer Pujar compatible = "nvidia,tegra234-amx", 208dc94a94dSSameer Pujar "nvidia,tegra194-amx"; 209dc94a94dSSameer Pujar reg = <0x2903000 0x100>; 210dc94a94dSSameer Pujar sound-name-prefix = "AMX1"; 211dc94a94dSSameer Pujar status = "disabled"; 212dc94a94dSSameer Pujar }; 213dc94a94dSSameer Pujar 214dc94a94dSSameer Pujar tegra_amx2: amx@2903100 { 215dc94a94dSSameer Pujar compatible = "nvidia,tegra234-amx", 216dc94a94dSSameer Pujar "nvidia,tegra194-amx"; 217dc94a94dSSameer Pujar reg = <0x2903100 0x100>; 218dc94a94dSSameer Pujar sound-name-prefix = "AMX2"; 219dc94a94dSSameer Pujar status = "disabled"; 220dc94a94dSSameer Pujar }; 221dc94a94dSSameer Pujar 222dc94a94dSSameer Pujar tegra_amx3: amx@2903200 { 223dc94a94dSSameer Pujar compatible = "nvidia,tegra234-amx", 224dc94a94dSSameer Pujar "nvidia,tegra194-amx"; 225dc94a94dSSameer Pujar reg = <0x2903200 0x100>; 226dc94a94dSSameer Pujar sound-name-prefix = "AMX3"; 227dc94a94dSSameer Pujar status = "disabled"; 228dc94a94dSSameer Pujar }; 229dc94a94dSSameer Pujar 230dc94a94dSSameer Pujar tegra_amx4: amx@2903300 { 231dc94a94dSSameer Pujar compatible = "nvidia,tegra234-amx", 232dc94a94dSSameer Pujar "nvidia,tegra194-amx"; 233dc94a94dSSameer Pujar reg = <0x2903300 0x100>; 234dc94a94dSSameer Pujar sound-name-prefix = "AMX4"; 235dc94a94dSSameer Pujar status = "disabled"; 236dc94a94dSSameer Pujar }; 237dc94a94dSSameer Pujar 238dc94a94dSSameer Pujar tegra_adx1: adx@2903800 { 239dc94a94dSSameer Pujar compatible = "nvidia,tegra234-adx", 240dc94a94dSSameer Pujar "nvidia,tegra210-adx"; 241dc94a94dSSameer Pujar reg = <0x2903800 0x100>; 242dc94a94dSSameer Pujar sound-name-prefix = "ADX1"; 243dc94a94dSSameer Pujar status = "disabled"; 244dc94a94dSSameer Pujar }; 245dc94a94dSSameer Pujar 246dc94a94dSSameer Pujar tegra_adx2: adx@2903900 { 247dc94a94dSSameer Pujar compatible = "nvidia,tegra234-adx", 248dc94a94dSSameer Pujar "nvidia,tegra210-adx"; 249dc94a94dSSameer Pujar reg = <0x2903900 0x100>; 250dc94a94dSSameer Pujar sound-name-prefix = "ADX2"; 251dc94a94dSSameer Pujar status = "disabled"; 252dc94a94dSSameer Pujar }; 253dc94a94dSSameer Pujar 254dc94a94dSSameer Pujar tegra_adx3: adx@2903a00 { 255dc94a94dSSameer Pujar compatible = "nvidia,tegra234-adx", 256dc94a94dSSameer Pujar "nvidia,tegra210-adx"; 257dc94a94dSSameer Pujar reg = <0x2903a00 0x100>; 258dc94a94dSSameer Pujar sound-name-prefix = "ADX3"; 259dc94a94dSSameer Pujar status = "disabled"; 260dc94a94dSSameer Pujar }; 261dc94a94dSSameer Pujar 262dc94a94dSSameer Pujar tegra_adx4: adx@2903b00 { 263dc94a94dSSameer Pujar compatible = "nvidia,tegra234-adx", 264dc94a94dSSameer Pujar "nvidia,tegra210-adx"; 265dc94a94dSSameer Pujar reg = <0x2903b00 0x100>; 266dc94a94dSSameer Pujar sound-name-prefix = "ADX4"; 267dc94a94dSSameer Pujar status = "disabled"; 268dc94a94dSSameer Pujar }; 269dc94a94dSSameer Pujar 270dc94a94dSSameer Pujar 271dc94a94dSSameer Pujar tegra_dmic1: dmic@2904000 { 272dc94a94dSSameer Pujar compatible = "nvidia,tegra234-dmic", 273dc94a94dSSameer Pujar "nvidia,tegra210-dmic"; 274dc94a94dSSameer Pujar reg = <0x2904000 0x100>; 275dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_DMIC1>; 276dc94a94dSSameer Pujar clock-names = "dmic"; 277dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_DMIC1>; 278dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 279dc94a94dSSameer Pujar assigned-clock-rates = <3072000>; 280dc94a94dSSameer Pujar sound-name-prefix = "DMIC1"; 281dc94a94dSSameer Pujar status = "disabled"; 282dc94a94dSSameer Pujar }; 283dc94a94dSSameer Pujar 284dc94a94dSSameer Pujar tegra_dmic2: dmic@2904100 { 285dc94a94dSSameer Pujar compatible = "nvidia,tegra234-dmic", 286dc94a94dSSameer Pujar "nvidia,tegra210-dmic"; 287dc94a94dSSameer Pujar reg = <0x2904100 0x100>; 288dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_DMIC2>; 289dc94a94dSSameer Pujar clock-names = "dmic"; 290dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_DMIC2>; 291dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 292dc94a94dSSameer Pujar assigned-clock-rates = <3072000>; 293dc94a94dSSameer Pujar sound-name-prefix = "DMIC2"; 294dc94a94dSSameer Pujar status = "disabled"; 295dc94a94dSSameer Pujar }; 296dc94a94dSSameer Pujar 297dc94a94dSSameer Pujar tegra_dmic3: dmic@2904200 { 298dc94a94dSSameer Pujar compatible = "nvidia,tegra234-dmic", 299dc94a94dSSameer Pujar "nvidia,tegra210-dmic"; 300dc94a94dSSameer Pujar reg = <0x2904200 0x100>; 301dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_DMIC3>; 302dc94a94dSSameer Pujar clock-names = "dmic"; 303dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_DMIC3>; 304dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 305dc94a94dSSameer Pujar assigned-clock-rates = <3072000>; 306dc94a94dSSameer Pujar sound-name-prefix = "DMIC3"; 307dc94a94dSSameer Pujar status = "disabled"; 308dc94a94dSSameer Pujar }; 309dc94a94dSSameer Pujar 310dc94a94dSSameer Pujar tegra_dmic4: dmic@2904300 { 311dc94a94dSSameer Pujar compatible = "nvidia,tegra234-dmic", 312dc94a94dSSameer Pujar "nvidia,tegra210-dmic"; 313dc94a94dSSameer Pujar reg = <0x2904300 0x100>; 314dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_DMIC4>; 315dc94a94dSSameer Pujar clock-names = "dmic"; 316dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_DMIC4>; 317dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 318dc94a94dSSameer Pujar assigned-clock-rates = <3072000>; 319dc94a94dSSameer Pujar sound-name-prefix = "DMIC4"; 320dc94a94dSSameer Pujar status = "disabled"; 321dc94a94dSSameer Pujar }; 322dc94a94dSSameer Pujar 323dc94a94dSSameer Pujar tegra_dspk1: dspk@2905000 { 324dc94a94dSSameer Pujar compatible = "nvidia,tegra234-dspk", 325dc94a94dSSameer Pujar "nvidia,tegra186-dspk"; 326dc94a94dSSameer Pujar reg = <0x2905000 0x100>; 327dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_DSPK1>; 328dc94a94dSSameer Pujar clock-names = "dspk"; 329dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_DSPK1>; 330dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 331dc94a94dSSameer Pujar assigned-clock-rates = <12288000>; 332dc94a94dSSameer Pujar sound-name-prefix = "DSPK1"; 333dc94a94dSSameer Pujar status = "disabled"; 334dc94a94dSSameer Pujar }; 335dc94a94dSSameer Pujar 336dc94a94dSSameer Pujar tegra_dspk2: dspk@2905100 { 337dc94a94dSSameer Pujar compatible = "nvidia,tegra234-dspk", 338dc94a94dSSameer Pujar "nvidia,tegra186-dspk"; 339dc94a94dSSameer Pujar reg = <0x2905100 0x100>; 340dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_DSPK2>; 341dc94a94dSSameer Pujar clock-names = "dspk"; 342dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_DSPK2>; 343dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 344dc94a94dSSameer Pujar assigned-clock-rates = <12288000>; 345dc94a94dSSameer Pujar sound-name-prefix = "DSPK2"; 346dc94a94dSSameer Pujar status = "disabled"; 347dc94a94dSSameer Pujar }; 348dc94a94dSSameer Pujar 3494b6a1b7cSSameer Pujar tegra_ope1: processing-engine@2908000 { 3504b6a1b7cSSameer Pujar compatible = "nvidia,tegra234-ope", 3514b6a1b7cSSameer Pujar "nvidia,tegra210-ope"; 3524b6a1b7cSSameer Pujar reg = <0x2908000 0x100>; 3534b6a1b7cSSameer Pujar #address-cells = <1>; 3544b6a1b7cSSameer Pujar #size-cells = <1>; 3554b6a1b7cSSameer Pujar ranges; 3564b6a1b7cSSameer Pujar sound-name-prefix = "OPE1"; 3574b6a1b7cSSameer Pujar status = "disabled"; 3584b6a1b7cSSameer Pujar 3594b6a1b7cSSameer Pujar equalizer@2908100 { 3604b6a1b7cSSameer Pujar compatible = "nvidia,tegra234-peq", 3614b6a1b7cSSameer Pujar "nvidia,tegra210-peq"; 3624b6a1b7cSSameer Pujar reg = <0x2908100 0x100>; 3634b6a1b7cSSameer Pujar }; 3644b6a1b7cSSameer Pujar 3654b6a1b7cSSameer Pujar dynamic-range-compressor@2908200 { 3664b6a1b7cSSameer Pujar compatible = "nvidia,tegra234-mbdrc", 3674b6a1b7cSSameer Pujar "nvidia,tegra210-mbdrc"; 3684b6a1b7cSSameer Pujar reg = <0x2908200 0x200>; 3694b6a1b7cSSameer Pujar }; 3704b6a1b7cSSameer Pujar }; 3714b6a1b7cSSameer Pujar 372dc94a94dSSameer Pujar tegra_mvc1: mvc@290a000 { 373dc94a94dSSameer Pujar compatible = "nvidia,tegra234-mvc", 374dc94a94dSSameer Pujar "nvidia,tegra210-mvc"; 375dc94a94dSSameer Pujar reg = <0x290a000 0x200>; 376dc94a94dSSameer Pujar sound-name-prefix = "MVC1"; 377dc94a94dSSameer Pujar status = "disabled"; 378dc94a94dSSameer Pujar }; 379dc94a94dSSameer Pujar 380dc94a94dSSameer Pujar tegra_mvc2: mvc@290a200 { 381dc94a94dSSameer Pujar compatible = "nvidia,tegra234-mvc", 382dc94a94dSSameer Pujar "nvidia,tegra210-mvc"; 383dc94a94dSSameer Pujar reg = <0x290a200 0x200>; 384dc94a94dSSameer Pujar sound-name-prefix = "MVC2"; 385dc94a94dSSameer Pujar status = "disabled"; 386dc94a94dSSameer Pujar }; 387dc94a94dSSameer Pujar 388dc94a94dSSameer Pujar tegra_amixer: amixer@290bb00 { 389dc94a94dSSameer Pujar compatible = "nvidia,tegra234-amixer", 390dc94a94dSSameer Pujar "nvidia,tegra210-amixer"; 391dc94a94dSSameer Pujar reg = <0x290bb00 0x800>; 392dc94a94dSSameer Pujar sound-name-prefix = "MIXER1"; 393dc94a94dSSameer Pujar status = "disabled"; 394dc94a94dSSameer Pujar }; 395dc94a94dSSameer Pujar 396dc94a94dSSameer Pujar tegra_admaif: admaif@290f000 { 397dc94a94dSSameer Pujar compatible = "nvidia,tegra234-admaif", 398dc94a94dSSameer Pujar "nvidia,tegra186-admaif"; 399dc94a94dSSameer Pujar reg = <0x0290f000 0x1000>; 400dc94a94dSSameer Pujar dmas = <&adma 1>, <&adma 1>, 401dc94a94dSSameer Pujar <&adma 2>, <&adma 2>, 402dc94a94dSSameer Pujar <&adma 3>, <&adma 3>, 403dc94a94dSSameer Pujar <&adma 4>, <&adma 4>, 404dc94a94dSSameer Pujar <&adma 5>, <&adma 5>, 405dc94a94dSSameer Pujar <&adma 6>, <&adma 6>, 406dc94a94dSSameer Pujar <&adma 7>, <&adma 7>, 407dc94a94dSSameer Pujar <&adma 8>, <&adma 8>, 408dc94a94dSSameer Pujar <&adma 9>, <&adma 9>, 409dc94a94dSSameer Pujar <&adma 10>, <&adma 10>, 410dc94a94dSSameer Pujar <&adma 11>, <&adma 11>, 411dc94a94dSSameer Pujar <&adma 12>, <&adma 12>, 412dc94a94dSSameer Pujar <&adma 13>, <&adma 13>, 413dc94a94dSSameer Pujar <&adma 14>, <&adma 14>, 414dc94a94dSSameer Pujar <&adma 15>, <&adma 15>, 415dc94a94dSSameer Pujar <&adma 16>, <&adma 16>, 416dc94a94dSSameer Pujar <&adma 17>, <&adma 17>, 417dc94a94dSSameer Pujar <&adma 18>, <&adma 18>, 418dc94a94dSSameer Pujar <&adma 19>, <&adma 19>, 419dc94a94dSSameer Pujar <&adma 20>, <&adma 20>; 420dc94a94dSSameer Pujar dma-names = "rx1", "tx1", 421dc94a94dSSameer Pujar "rx2", "tx2", 422dc94a94dSSameer Pujar "rx3", "tx3", 423dc94a94dSSameer Pujar "rx4", "tx4", 424dc94a94dSSameer Pujar "rx5", "tx5", 425dc94a94dSSameer Pujar "rx6", "tx6", 426dc94a94dSSameer Pujar "rx7", "tx7", 427dc94a94dSSameer Pujar "rx8", "tx8", 428dc94a94dSSameer Pujar "rx9", "tx9", 429dc94a94dSSameer Pujar "rx10", "tx10", 430dc94a94dSSameer Pujar "rx11", "tx11", 431dc94a94dSSameer Pujar "rx12", "tx12", 432dc94a94dSSameer Pujar "rx13", "tx13", 433dc94a94dSSameer Pujar "rx14", "tx14", 434dc94a94dSSameer Pujar "rx15", "tx15", 435dc94a94dSSameer Pujar "rx16", "tx16", 436dc94a94dSSameer Pujar "rx17", "tx17", 437dc94a94dSSameer Pujar "rx18", "tx18", 438dc94a94dSSameer Pujar "rx19", "tx19", 439dc94a94dSSameer Pujar "rx20", "tx20"; 440dc94a94dSSameer Pujar interconnects = <&mc TEGRA234_MEMORY_CLIENT_APEDMAR &emc>, 441dc94a94dSSameer Pujar <&mc TEGRA234_MEMORY_CLIENT_APEDMAW &emc>; 442dc94a94dSSameer Pujar interconnect-names = "dma-mem", "write"; 443dc94a94dSSameer Pujar iommus = <&smmu_niso0 TEGRA234_SID_APE>; 444dc94a94dSSameer Pujar status = "disabled"; 445dc94a94dSSameer Pujar }; 44647a08153SSameer Pujar 44747a08153SSameer Pujar tegra_asrc: asrc@2910000 { 44847a08153SSameer Pujar compatible = "nvidia,tegra234-asrc", 44947a08153SSameer Pujar "nvidia,tegra186-asrc"; 45047a08153SSameer Pujar reg = <0x2910000 0x2000>; 45147a08153SSameer Pujar sound-name-prefix = "ASRC1"; 45247a08153SSameer Pujar status = "disabled"; 45347a08153SSameer Pujar }; 454dc94a94dSSameer Pujar }; 455dc94a94dSSameer Pujar 456dc94a94dSSameer Pujar adma: dma-controller@2930000 { 457dc94a94dSSameer Pujar compatible = "nvidia,tegra234-adma", 458dc94a94dSSameer Pujar "nvidia,tegra186-adma"; 459dc94a94dSSameer Pujar reg = <0x02930000 0x20000>; 460dc94a94dSSameer Pujar interrupt-parent = <&agic>; 461dc94a94dSSameer Pujar interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 462dc94a94dSSameer Pujar <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 463dc94a94dSSameer Pujar <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 464dc94a94dSSameer Pujar <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 465dc94a94dSSameer Pujar <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 466dc94a94dSSameer Pujar <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 467dc94a94dSSameer Pujar <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 468dc94a94dSSameer Pujar <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 469dc94a94dSSameer Pujar <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 470dc94a94dSSameer Pujar <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 471dc94a94dSSameer Pujar <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 472dc94a94dSSameer Pujar <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 473dc94a94dSSameer Pujar <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 474dc94a94dSSameer Pujar <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 475dc94a94dSSameer Pujar <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 476dc94a94dSSameer Pujar <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 477dc94a94dSSameer Pujar <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 478dc94a94dSSameer Pujar <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 479dc94a94dSSameer Pujar <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 480dc94a94dSSameer Pujar <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 481dc94a94dSSameer Pujar <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 482dc94a94dSSameer Pujar <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 483dc94a94dSSameer Pujar <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 484dc94a94dSSameer Pujar <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 485dc94a94dSSameer Pujar <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 486dc94a94dSSameer Pujar <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 487dc94a94dSSameer Pujar <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 488dc94a94dSSameer Pujar <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 489dc94a94dSSameer Pujar <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 490dc94a94dSSameer Pujar <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 491dc94a94dSSameer Pujar <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 492dc94a94dSSameer Pujar <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 493dc94a94dSSameer Pujar #dma-cells = <1>; 494dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_AHUB>; 495dc94a94dSSameer Pujar clock-names = "d_audio"; 496dc94a94dSSameer Pujar status = "disabled"; 497dc94a94dSSameer Pujar }; 498dc94a94dSSameer Pujar 499dc94a94dSSameer Pujar agic: interrupt-controller@2a40000 { 500dc94a94dSSameer Pujar compatible = "nvidia,tegra234-agic", 501dc94a94dSSameer Pujar "nvidia,tegra210-agic"; 502dc94a94dSSameer Pujar #interrupt-cells = <3>; 503dc94a94dSSameer Pujar interrupt-controller; 504dc94a94dSSameer Pujar reg = <0x02a41000 0x1000>, 505dc94a94dSSameer Pujar <0x02a42000 0x2000>; 506dc94a94dSSameer Pujar interrupts = <GIC_SPI 145 507dc94a94dSSameer Pujar (GIC_CPU_MASK_SIMPLE(4) | 508dc94a94dSSameer Pujar IRQ_TYPE_LEVEL_HIGH)>; 509dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_APE>; 510dc94a94dSSameer Pujar clock-names = "clk"; 511dc94a94dSSameer Pujar status = "disabled"; 512dc94a94dSSameer Pujar }; 513dc94a94dSSameer Pujar }; 514dc94a94dSSameer Pujar 51563944891SThierry Reding misc@100000 { 51663944891SThierry Reding compatible = "nvidia,tegra234-misc"; 51763944891SThierry Reding reg = <0x00100000 0xf000>, 51863944891SThierry Reding <0x0010f000 0x1000>; 51963944891SThierry Reding status = "okay"; 52063944891SThierry Reding }; 52163944891SThierry Reding 52228d860edSKartik timer@2080000 { 52328d860edSKartik compatible = "nvidia,tegra234-timer"; 52428d860edSKartik reg = <0x02080000 0x00121000>; 52528d860edSKartik interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 52628d860edSKartik <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 52728d860edSKartik <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 52828d860edSKartik <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 52928d860edSKartik <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 53028d860edSKartik <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 53128d860edSKartik <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 53228d860edSKartik <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 53328d860edSKartik <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 53428d860edSKartik <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 53528d860edSKartik <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 53628d860edSKartik <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 53728d860edSKartik <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 53828d860edSKartik <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 53928d860edSKartik <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 54028d860edSKartik <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 54128d860edSKartik status = "okay"; 54228d860edSKartik }; 54328d860edSKartik 5444bb39ca2SMikko Perttunen host1x@13e00000 { 5454bb39ca2SMikko Perttunen compatible = "nvidia,tegra234-host1x"; 5464bb39ca2SMikko Perttunen reg = <0x13e00000 0x10000>, 5474bb39ca2SMikko Perttunen <0x13e10000 0x10000>, 5484bb39ca2SMikko Perttunen <0x13e40000 0x10000>; 5494bb39ca2SMikko Perttunen reg-names = "common", "hypervisor", "vm"; 5504bb39ca2SMikko Perttunen interrupts = <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, 5514bb39ca2SMikko Perttunen <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, 5524bb39ca2SMikko Perttunen <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, 5534bb39ca2SMikko Perttunen <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, 5544bb39ca2SMikko Perttunen <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, 5554bb39ca2SMikko Perttunen <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>, 5564bb39ca2SMikko Perttunen <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>, 5574bb39ca2SMikko Perttunen <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>, 5584bb39ca2SMikko Perttunen <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 5594bb39ca2SMikko Perttunen interrupt-names = "syncpt0", "syncpt1", "syncpt2", "syncpt3", "syncpt4", 5604bb39ca2SMikko Perttunen "syncpt5", "syncpt6", "syncpt7", "host1x"; 5614bb39ca2SMikko Perttunen clocks = <&bpmp TEGRA234_CLK_HOST1X>; 5624bb39ca2SMikko Perttunen clock-names = "host1x"; 5634bb39ca2SMikko Perttunen 5644bb39ca2SMikko Perttunen #address-cells = <1>; 5654bb39ca2SMikko Perttunen #size-cells = <1>; 5664bb39ca2SMikko Perttunen 567e25770feSMikko Perttunen ranges = <0x14800000 0x14800000 0x02000000>; 5684bb39ca2SMikko Perttunen interconnects = <&mc TEGRA234_MEMORY_CLIENT_HOST1XDMAR &emc>; 5694bb39ca2SMikko Perttunen interconnect-names = "dma-mem"; 5704bb39ca2SMikko Perttunen iommus = <&smmu_niso1 TEGRA234_SID_HOST1X>; 5714bb39ca2SMikko Perttunen 572b35f5b53SMikko Perttunen /* Context isolation domains */ 573b35f5b53SMikko Perttunen iommu-map = <0 &smmu_niso0 TEGRA234_SID_HOST1X_CTX0 1>, 574b35f5b53SMikko Perttunen <1 &smmu_niso0 TEGRA234_SID_HOST1X_CTX1 1>, 575b35f5b53SMikko Perttunen <2 &smmu_niso0 TEGRA234_SID_HOST1X_CTX2 1>, 576b35f5b53SMikko Perttunen <3 &smmu_niso0 TEGRA234_SID_HOST1X_CTX3 1>, 577b35f5b53SMikko Perttunen <4 &smmu_niso0 TEGRA234_SID_HOST1X_CTX4 1>, 578b35f5b53SMikko Perttunen <5 &smmu_niso0 TEGRA234_SID_HOST1X_CTX5 1>, 579b35f5b53SMikko Perttunen <6 &smmu_niso0 TEGRA234_SID_HOST1X_CTX6 1>, 580b35f5b53SMikko Perttunen <7 &smmu_niso0 TEGRA234_SID_HOST1X_CTX7 1>, 581b35f5b53SMikko Perttunen <8 &smmu_niso1 TEGRA234_SID_HOST1X_CTX0 1>, 582b35f5b53SMikko Perttunen <9 &smmu_niso1 TEGRA234_SID_HOST1X_CTX1 1>, 583b35f5b53SMikko Perttunen <10 &smmu_niso1 TEGRA234_SID_HOST1X_CTX2 1>, 584b35f5b53SMikko Perttunen <11 &smmu_niso1 TEGRA234_SID_HOST1X_CTX3 1>, 585b35f5b53SMikko Perttunen <12 &smmu_niso1 TEGRA234_SID_HOST1X_CTX4 1>, 586b35f5b53SMikko Perttunen <13 &smmu_niso1 TEGRA234_SID_HOST1X_CTX5 1>, 587b35f5b53SMikko Perttunen <14 &smmu_niso1 TEGRA234_SID_HOST1X_CTX6 1>, 588b35f5b53SMikko Perttunen <15 &smmu_niso1 TEGRA234_SID_HOST1X_CTX7 1>; 589b35f5b53SMikko Perttunen 5904bb39ca2SMikko Perttunen vic@15340000 { 5914bb39ca2SMikko Perttunen compatible = "nvidia,tegra234-vic"; 5924bb39ca2SMikko Perttunen reg = <0x15340000 0x00040000>; 5934bb39ca2SMikko Perttunen interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 5944bb39ca2SMikko Perttunen clocks = <&bpmp TEGRA234_CLK_VIC>; 5954bb39ca2SMikko Perttunen clock-names = "vic"; 5964bb39ca2SMikko Perttunen resets = <&bpmp TEGRA234_RESET_VIC>; 5974bb39ca2SMikko Perttunen reset-names = "vic"; 5984bb39ca2SMikko Perttunen 5994bb39ca2SMikko Perttunen power-domains = <&bpmp TEGRA234_POWER_DOMAIN_VIC>; 6004bb39ca2SMikko Perttunen interconnects = <&mc TEGRA234_MEMORY_CLIENT_VICSRD &emc>, 6014bb39ca2SMikko Perttunen <&mc TEGRA234_MEMORY_CLIENT_VICSWR &emc>; 6024bb39ca2SMikko Perttunen interconnect-names = "dma-mem", "write"; 6034bb39ca2SMikko Perttunen iommus = <&smmu_niso1 TEGRA234_SID_VIC>; 6044bb39ca2SMikko Perttunen dma-coherent; 6054bb39ca2SMikko Perttunen }; 60668c31ad0SMikko Perttunen 60768c31ad0SMikko Perttunen nvdec@15480000 { 60868c31ad0SMikko Perttunen compatible = "nvidia,tegra234-nvdec"; 60968c31ad0SMikko Perttunen reg = <0x15480000 0x00040000>; 61068c31ad0SMikko Perttunen clocks = <&bpmp TEGRA234_CLK_NVDEC>, 61168c31ad0SMikko Perttunen <&bpmp TEGRA234_CLK_FUSE>, 61268c31ad0SMikko Perttunen <&bpmp TEGRA234_CLK_TSEC_PKA>; 61368c31ad0SMikko Perttunen clock-names = "nvdec", "fuse", "tsec_pka"; 61468c31ad0SMikko Perttunen resets = <&bpmp TEGRA234_RESET_NVDEC>; 61568c31ad0SMikko Perttunen reset-names = "nvdec"; 61668c31ad0SMikko Perttunen power-domains = <&bpmp TEGRA234_POWER_DOMAIN_NVDEC>; 61768c31ad0SMikko Perttunen interconnects = <&mc TEGRA234_MEMORY_CLIENT_NVDECSRD &emc>, 61868c31ad0SMikko Perttunen <&mc TEGRA234_MEMORY_CLIENT_NVDECSWR &emc>; 61968c31ad0SMikko Perttunen interconnect-names = "dma-mem", "write"; 62068c31ad0SMikko Perttunen iommus = <&smmu_niso1 TEGRA234_SID_NVDEC>; 62168c31ad0SMikko Perttunen dma-coherent; 62268c31ad0SMikko Perttunen 62368c31ad0SMikko Perttunen nvidia,memory-controller = <&mc>; 62468c31ad0SMikko Perttunen 62568c31ad0SMikko Perttunen /* 62668c31ad0SMikko Perttunen * Placeholder values that firmware needs to update with the real 62768c31ad0SMikko Perttunen * offsets parsed from the microcode headers. 62868c31ad0SMikko Perttunen */ 62968c31ad0SMikko Perttunen nvidia,bl-manifest-offset = <0>; 63068c31ad0SMikko Perttunen nvidia,bl-data-offset = <0>; 63168c31ad0SMikko Perttunen nvidia,bl-code-offset = <0>; 63268c31ad0SMikko Perttunen nvidia,os-manifest-offset = <0>; 63368c31ad0SMikko Perttunen nvidia,os-data-offset = <0>; 63468c31ad0SMikko Perttunen nvidia,os-code-offset = <0>; 63568c31ad0SMikko Perttunen 63668c31ad0SMikko Perttunen /* 63768c31ad0SMikko Perttunen * Firmware needs to set this to "okay" once the above values have 63868c31ad0SMikko Perttunen * been updated. 63968c31ad0SMikko Perttunen */ 64068c31ad0SMikko Perttunen status = "disabled"; 64168c31ad0SMikko Perttunen }; 6424bb39ca2SMikko Perttunen }; 6434bb39ca2SMikko Perttunen 644f0e12668SThierry Reding gpio: gpio@2200000 { 645f0e12668SThierry Reding compatible = "nvidia,tegra234-gpio"; 646f0e12668SThierry Reding reg-names = "security", "gpio"; 647f0e12668SThierry Reding reg = <0x02200000 0x10000>, 648f0e12668SThierry Reding <0x02210000 0x10000>; 649f0e12668SThierry Reding interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 650f0e12668SThierry Reding <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 651f0e12668SThierry Reding <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 652f0e12668SThierry Reding <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, 653f0e12668SThierry Reding <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 654f0e12668SThierry Reding <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 655f0e12668SThierry Reding <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 656f0e12668SThierry Reding <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 657f0e12668SThierry Reding <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 658f0e12668SThierry Reding <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 659f0e12668SThierry Reding <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 660f0e12668SThierry Reding <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 661f0e12668SThierry Reding <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 662f0e12668SThierry Reding <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 663f0e12668SThierry Reding <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 664f0e12668SThierry Reding <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 665f0e12668SThierry Reding <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 666f0e12668SThierry Reding <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 667f0e12668SThierry Reding <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 668f0e12668SThierry Reding <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 669f0e12668SThierry Reding <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 670f0e12668SThierry Reding <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 671f0e12668SThierry Reding <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 672f0e12668SThierry Reding <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 673f0e12668SThierry Reding <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 674f0e12668SThierry Reding <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 675f0e12668SThierry Reding <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 676f0e12668SThierry Reding <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 677f0e12668SThierry Reding <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 678f0e12668SThierry Reding <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 679f0e12668SThierry Reding <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 680f0e12668SThierry Reding <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 681f0e12668SThierry Reding <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 682f0e12668SThierry Reding <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 683f0e12668SThierry Reding <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 684f0e12668SThierry Reding <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 685f0e12668SThierry Reding <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 686f0e12668SThierry Reding <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 687f0e12668SThierry Reding <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 688f0e12668SThierry Reding <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 689f0e12668SThierry Reding <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 690f0e12668SThierry Reding <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 691f0e12668SThierry Reding <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 692f0e12668SThierry Reding <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 693f0e12668SThierry Reding <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 694f0e12668SThierry Reding <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 695f0e12668SThierry Reding <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 696f0e12668SThierry Reding <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 697f0e12668SThierry Reding #interrupt-cells = <2>; 698f0e12668SThierry Reding interrupt-controller; 699f0e12668SThierry Reding #gpio-cells = <2>; 700f0e12668SThierry Reding gpio-controller; 701f0e12668SThierry Reding }; 702f0e12668SThierry Reding 703eed280dfSThierry Reding mc: memory-controller@2c00000 { 704eed280dfSThierry Reding compatible = "nvidia,tegra234-mc"; 705000b99e5SAshish Mhetre reg = <0x02c00000 0x10000>, /* MC-SID */ 706000b99e5SAshish Mhetre <0x02c10000 0x10000>, /* MC Broadcast*/ 707000b99e5SAshish Mhetre <0x02c20000 0x10000>, /* MC0 */ 708000b99e5SAshish Mhetre <0x02c30000 0x10000>, /* MC1 */ 709000b99e5SAshish Mhetre <0x02c40000 0x10000>, /* MC2 */ 710000b99e5SAshish Mhetre <0x02c50000 0x10000>, /* MC3 */ 711000b99e5SAshish Mhetre <0x02b80000 0x10000>, /* MC4 */ 712000b99e5SAshish Mhetre <0x02b90000 0x10000>, /* MC5 */ 713000b99e5SAshish Mhetre <0x02ba0000 0x10000>, /* MC6 */ 714000b99e5SAshish Mhetre <0x02bb0000 0x10000>, /* MC7 */ 715000b99e5SAshish Mhetre <0x01700000 0x10000>, /* MC8 */ 716000b99e5SAshish Mhetre <0x01710000 0x10000>, /* MC9 */ 717000b99e5SAshish Mhetre <0x01720000 0x10000>, /* MC10 */ 718000b99e5SAshish Mhetre <0x01730000 0x10000>, /* MC11 */ 719000b99e5SAshish Mhetre <0x01740000 0x10000>, /* MC12 */ 720000b99e5SAshish Mhetre <0x01750000 0x10000>, /* MC13 */ 721000b99e5SAshish Mhetre <0x01760000 0x10000>, /* MC14 */ 722000b99e5SAshish Mhetre <0x01770000 0x10000>; /* MC15 */ 723000b99e5SAshish Mhetre reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3", 724000b99e5SAshish Mhetre "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", 725000b99e5SAshish Mhetre "ch11", "ch12", "ch13", "ch14", "ch15"; 726eed280dfSThierry Reding interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 727eed280dfSThierry Reding #interconnect-cells = <1>; 728eed280dfSThierry Reding status = "okay"; 729eed280dfSThierry Reding 730eed280dfSThierry Reding #address-cells = <2>; 731eed280dfSThierry Reding #size-cells = <2>; 732eed280dfSThierry Reding 733eed280dfSThierry Reding ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>, 734eed280dfSThierry Reding <0x02b80000 0x0 0x02b80000 0x0 0x040000>, 735eed280dfSThierry Reding <0x02c00000 0x0 0x02c00000 0x0 0x100000>; 736eed280dfSThierry Reding 737eed280dfSThierry Reding /* 738eed280dfSThierry Reding * Bit 39 of addresses passing through the memory 739eed280dfSThierry Reding * controller selects the XBAR format used when memory 740eed280dfSThierry Reding * is accessed. This is used to transparently access 741eed280dfSThierry Reding * memory in the XBAR format used by the discrete GPU 742eed280dfSThierry Reding * (bit 39 set) or Tegra (bit 39 clear). 743eed280dfSThierry Reding * 744eed280dfSThierry Reding * As a consequence, the operating system must ensure 745eed280dfSThierry Reding * that bit 39 is never used implicitly, for example 746eed280dfSThierry Reding * via an I/O virtual address mapping of an IOMMU. If 747eed280dfSThierry Reding * devices require access to the XBAR switch, their 748eed280dfSThierry Reding * drivers must set this bit explicitly. 749eed280dfSThierry Reding * 750eed280dfSThierry Reding * Limit the DMA range for memory clients to [38:0]. 751eed280dfSThierry Reding */ 752eed280dfSThierry Reding dma-ranges = <0x0 0x0 0x0 0x80 0x0>; 753eed280dfSThierry Reding 754eed280dfSThierry Reding emc: external-memory-controller@2c60000 { 755eed280dfSThierry Reding compatible = "nvidia,tegra234-emc"; 756eed280dfSThierry Reding reg = <0x0 0x02c60000 0x0 0x90000>, 757eed280dfSThierry Reding <0x0 0x01780000 0x0 0x80000>; 758eed280dfSThierry Reding interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 759eed280dfSThierry Reding clocks = <&bpmp TEGRA234_CLK_EMC>; 760eed280dfSThierry Reding clock-names = "emc"; 761eed280dfSThierry Reding status = "okay"; 762eed280dfSThierry Reding 763eed280dfSThierry Reding #interconnect-cells = <0>; 764eed280dfSThierry Reding 765eed280dfSThierry Reding nvidia,bpmp = <&bpmp>; 766eed280dfSThierry Reding }; 767eed280dfSThierry Reding }; 768eed280dfSThierry Reding 76963944891SThierry Reding uarta: serial@3100000 { 77063944891SThierry Reding compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart"; 77163944891SThierry Reding reg = <0x03100000 0x10000>; 77263944891SThierry Reding interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 77363944891SThierry Reding clocks = <&bpmp TEGRA234_CLK_UARTA>; 77463944891SThierry Reding clock-names = "serial"; 77563944891SThierry Reding resets = <&bpmp TEGRA234_RESET_UARTA>; 77663944891SThierry Reding reset-names = "serial"; 77763944891SThierry Reding status = "disabled"; 77863944891SThierry Reding }; 77963944891SThierry Reding 780156af9deSAkhil R gen1_i2c: i2c@3160000 { 781156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 782156af9deSAkhil R reg = <0x3160000 0x100>; 783156af9deSAkhil R status = "disabled"; 784156af9deSAkhil R interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 785156af9deSAkhil R clock-frequency = <400000>; 786156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C1 787156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 788156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C1>; 789156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 790156af9deSAkhil R clock-names = "div-clk", "parent"; 791156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C1>; 792156af9deSAkhil R reset-names = "i2c"; 7938e442805SAkhil R iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 7948e442805SAkhil R dma-coherent; 7958e442805SAkhil R dmas = <&gpcdma 21>, <&gpcdma 21>; 7968e442805SAkhil R dma-names = "rx", "tx"; 797156af9deSAkhil R }; 798156af9deSAkhil R 799156af9deSAkhil R cam_i2c: i2c@3180000 { 800156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 801156af9deSAkhil R reg = <0x3180000 0x100>; 802156af9deSAkhil R interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 803156af9deSAkhil R status = "disabled"; 804156af9deSAkhil R clock-frequency = <400000>; 805156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C3 806156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 807156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C3>; 808156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 809156af9deSAkhil R clock-names = "div-clk", "parent"; 810156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C3>; 811156af9deSAkhil R reset-names = "i2c"; 8128e442805SAkhil R iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 8138e442805SAkhil R dma-coherent; 8148e442805SAkhil R dmas = <&gpcdma 23>, <&gpcdma 23>; 8158e442805SAkhil R dma-names = "rx", "tx"; 816156af9deSAkhil R }; 817156af9deSAkhil R 818156af9deSAkhil R dp_aux_ch1_i2c: i2c@3190000 { 819156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 820156af9deSAkhil R reg = <0x3190000 0x100>; 821156af9deSAkhil R interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 822156af9deSAkhil R status = "disabled"; 823156af9deSAkhil R clock-frequency = <100000>; 824156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C4 825156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 826156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C4>; 827156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 828156af9deSAkhil R clock-names = "div-clk", "parent"; 829156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C4>; 830156af9deSAkhil R reset-names = "i2c"; 8318e442805SAkhil R iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 8328e442805SAkhil R dma-coherent; 8338e442805SAkhil R dmas = <&gpcdma 26>, <&gpcdma 26>; 8348e442805SAkhil R dma-names = "rx", "tx"; 835156af9deSAkhil R }; 836156af9deSAkhil R 837156af9deSAkhil R dp_aux_ch0_i2c: i2c@31b0000 { 838156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 839156af9deSAkhil R reg = <0x31b0000 0x100>; 840156af9deSAkhil R interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 841156af9deSAkhil R status = "disabled"; 842156af9deSAkhil R clock-frequency = <100000>; 843156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C6 844156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 845156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C6>; 846156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 847156af9deSAkhil R clock-names = "div-clk", "parent"; 848156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C6>; 849156af9deSAkhil R reset-names = "i2c"; 8508e442805SAkhil R iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 8518e442805SAkhil R dma-coherent; 8528e442805SAkhil R dmas = <&gpcdma 30>, <&gpcdma 30>; 8538e442805SAkhil R dma-names = "rx", "tx"; 854156af9deSAkhil R }; 855156af9deSAkhil R 856156af9deSAkhil R dp_aux_ch2_i2c: i2c@31c0000 { 857156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 858156af9deSAkhil R reg = <0x31c0000 0x100>; 859156af9deSAkhil R interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 860156af9deSAkhil R status = "disabled"; 861156af9deSAkhil R clock-frequency = <100000>; 862156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C7 863156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 864156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C7>; 865156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 866156af9deSAkhil R clock-names = "div-clk", "parent"; 867156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C7>; 868156af9deSAkhil R reset-names = "i2c"; 8698e442805SAkhil R iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 8708e442805SAkhil R dma-coherent; 8718e442805SAkhil R dmas = <&gpcdma 27>, <&gpcdma 27>; 8728e442805SAkhil R dma-names = "rx", "tx"; 873156af9deSAkhil R }; 874156af9deSAkhil R 875156af9deSAkhil R dp_aux_ch3_i2c: i2c@31e0000 { 876156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 877156af9deSAkhil R reg = <0x31e0000 0x100>; 878156af9deSAkhil R interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 879156af9deSAkhil R status = "disabled"; 880156af9deSAkhil R clock-frequency = <100000>; 881156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C9 882156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 883156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C9>; 884156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 885156af9deSAkhil R clock-names = "div-clk", "parent"; 886156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C9>; 887156af9deSAkhil R reset-names = "i2c"; 8888e442805SAkhil R iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 8898e442805SAkhil R dma-coherent; 8908e442805SAkhil R dmas = <&gpcdma 31>, <&gpcdma 31>; 8918e442805SAkhil R dma-names = "rx", "tx"; 892156af9deSAkhil R }; 893156af9deSAkhil R 89471f69ffaSAshish Singhal spi@3270000 { 89571f69ffaSAshish Singhal compatible = "nvidia,tegra234-qspi"; 89671f69ffaSAshish Singhal reg = <0x3270000 0x1000>; 89771f69ffaSAshish Singhal interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 89871f69ffaSAshish Singhal #address-cells = <1>; 89971f69ffaSAshish Singhal #size-cells = <0>; 90071f69ffaSAshish Singhal clocks = <&bpmp TEGRA234_CLK_QSPI0_2X_PM>, 90171f69ffaSAshish Singhal <&bpmp TEGRA234_CLK_QSPI0_PM>; 90271f69ffaSAshish Singhal clock-names = "qspi", "qspi_out"; 90371f69ffaSAshish Singhal resets = <&bpmp TEGRA234_RESET_QSPI0>; 90471f69ffaSAshish Singhal reset-names = "qspi"; 90571f69ffaSAshish Singhal status = "disabled"; 90671f69ffaSAshish Singhal }; 90771f69ffaSAshish Singhal 9085e69088dSAkhil R pwm1: pwm@3280000 { 909*2566d28cSJon Hunter compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 9105e69088dSAkhil R reg = <0x3280000 0x10000>; 9115e69088dSAkhil R clocks = <&bpmp TEGRA234_CLK_PWM1>; 9125e69088dSAkhil R clock-names = "pwm"; 9135e69088dSAkhil R resets = <&bpmp TEGRA234_RESET_PWM1>; 9145e69088dSAkhil R reset-names = "pwm"; 9155e69088dSAkhil R status = "disabled"; 9165e69088dSAkhil R #pwm-cells = <2>; 9175e69088dSAkhil R }; 9185e69088dSAkhil R 919*2566d28cSJon Hunter pwm2: pwm@3290000 { 920*2566d28cSJon Hunter compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 921*2566d28cSJon Hunter reg = <0x3290000 0x10000>; 922*2566d28cSJon Hunter clocks = <&bpmp TEGRA234_CLK_PWM2>; 923*2566d28cSJon Hunter clock-names = "pwm"; 924*2566d28cSJon Hunter resets = <&bpmp TEGRA234_RESET_PWM2>; 925*2566d28cSJon Hunter reset-names = "pwm"; 926*2566d28cSJon Hunter status = "disabled"; 927*2566d28cSJon Hunter #pwm-cells = <2>; 928*2566d28cSJon Hunter }; 929*2566d28cSJon Hunter 930*2566d28cSJon Hunter pwm3: pwm@32a0000 { 931*2566d28cSJon Hunter compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 932*2566d28cSJon Hunter reg = <0x32a0000 0x10000>; 933*2566d28cSJon Hunter clocks = <&bpmp TEGRA234_CLK_PWM3>; 934*2566d28cSJon Hunter clock-names = "pwm"; 935*2566d28cSJon Hunter resets = <&bpmp TEGRA234_RESET_PWM3>; 936*2566d28cSJon Hunter reset-names = "pwm"; 937*2566d28cSJon Hunter status = "disabled"; 938*2566d28cSJon Hunter #pwm-cells = <2>; 939*2566d28cSJon Hunter }; 940*2566d28cSJon Hunter 941*2566d28cSJon Hunter pwm5: pwm@32c0000 { 942*2566d28cSJon Hunter compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 943*2566d28cSJon Hunter reg = <0x32c0000 0x10000>; 944*2566d28cSJon Hunter clocks = <&bpmp TEGRA234_CLK_PWM5>; 945*2566d28cSJon Hunter clock-names = "pwm"; 946*2566d28cSJon Hunter resets = <&bpmp TEGRA234_RESET_PWM5>; 947*2566d28cSJon Hunter reset-names = "pwm"; 948*2566d28cSJon Hunter status = "disabled"; 949*2566d28cSJon Hunter #pwm-cells = <2>; 950*2566d28cSJon Hunter }; 951*2566d28cSJon Hunter 952*2566d28cSJon Hunter pwm6: pwm@32d0000 { 953*2566d28cSJon Hunter compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 954*2566d28cSJon Hunter reg = <0x32d0000 0x10000>; 955*2566d28cSJon Hunter clocks = <&bpmp TEGRA234_CLK_PWM6>; 956*2566d28cSJon Hunter clock-names = "pwm"; 957*2566d28cSJon Hunter resets = <&bpmp TEGRA234_RESET_PWM6>; 958*2566d28cSJon Hunter reset-names = "pwm"; 959*2566d28cSJon Hunter status = "disabled"; 960*2566d28cSJon Hunter #pwm-cells = <2>; 961*2566d28cSJon Hunter }; 962*2566d28cSJon Hunter 963*2566d28cSJon Hunter pwm7: pwm@32e0000 { 964*2566d28cSJon Hunter compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 965*2566d28cSJon Hunter reg = <0x32e0000 0x10000>; 966*2566d28cSJon Hunter clocks = <&bpmp TEGRA234_CLK_PWM7>; 967*2566d28cSJon Hunter clock-names = "pwm"; 968*2566d28cSJon Hunter resets = <&bpmp TEGRA234_RESET_PWM7>; 969*2566d28cSJon Hunter reset-names = "pwm"; 970*2566d28cSJon Hunter status = "disabled"; 971*2566d28cSJon Hunter #pwm-cells = <2>; 972*2566d28cSJon Hunter }; 973*2566d28cSJon Hunter 974*2566d28cSJon Hunter pwm8: pwm@32f0000 { 975*2566d28cSJon Hunter compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 976*2566d28cSJon Hunter reg = <0x32f0000 0x10000>; 977*2566d28cSJon Hunter clocks = <&bpmp TEGRA234_CLK_PWM8>; 978*2566d28cSJon Hunter clock-names = "pwm"; 979*2566d28cSJon Hunter resets = <&bpmp TEGRA234_RESET_PWM8>; 980*2566d28cSJon Hunter reset-names = "pwm"; 981*2566d28cSJon Hunter status = "disabled"; 982*2566d28cSJon Hunter #pwm-cells = <2>; 983*2566d28cSJon Hunter }; 984*2566d28cSJon Hunter 98571f69ffaSAshish Singhal spi@3300000 { 98671f69ffaSAshish Singhal compatible = "nvidia,tegra234-qspi"; 98771f69ffaSAshish Singhal reg = <0x3300000 0x1000>; 98871f69ffaSAshish Singhal interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 98971f69ffaSAshish Singhal #address-cells = <1>; 99071f69ffaSAshish Singhal #size-cells = <0>; 99171f69ffaSAshish Singhal clocks = <&bpmp TEGRA234_CLK_QSPI1_2X_PM>, 99271f69ffaSAshish Singhal <&bpmp TEGRA234_CLK_QSPI1_PM>; 99371f69ffaSAshish Singhal clock-names = "qspi", "qspi_out"; 99471f69ffaSAshish Singhal resets = <&bpmp TEGRA234_RESET_QSPI1>; 99571f69ffaSAshish Singhal reset-names = "qspi"; 99671f69ffaSAshish Singhal status = "disabled"; 99771f69ffaSAshish Singhal }; 99871f69ffaSAshish Singhal 99963944891SThierry Reding mmc@3460000 { 100063944891SThierry Reding compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci"; 100163944891SThierry Reding reg = <0x03460000 0x20000>; 100263944891SThierry Reding interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 1003e086d82dSMikko Perttunen clocks = <&bpmp TEGRA234_CLK_SDMMC4>, 1004e086d82dSMikko Perttunen <&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>; 1005e086d82dSMikko Perttunen clock-names = "sdhci", "tmclk"; 1006e086d82dSMikko Perttunen assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC4>, 1007e086d82dSMikko Perttunen <&bpmp TEGRA234_CLK_PLLC4>; 1008e086d82dSMikko Perttunen assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4>; 100963944891SThierry Reding resets = <&bpmp TEGRA234_RESET_SDMMC4>; 101063944891SThierry Reding reset-names = "sdhci"; 10116de481e5SThierry Reding interconnects = <&mc TEGRA234_MEMORY_CLIENT_SDMMCRAB &emc>, 10126de481e5SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_SDMMCWAB &emc>; 10136de481e5SThierry Reding interconnect-names = "dma-mem", "write"; 10145710e16aSThierry Reding iommus = <&smmu_niso1 TEGRA234_SID_SDMMC4>; 1015e086d82dSMikko Perttunen nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 1016e086d82dSMikko Perttunen nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 1017e086d82dSMikko Perttunen nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 1018e086d82dSMikko Perttunen nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; 1019e086d82dSMikko Perttunen nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 1020e086d82dSMikko Perttunen nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>; 1021e086d82dSMikko Perttunen nvidia,default-tap = <0x8>; 1022e086d82dSMikko Perttunen nvidia,default-trim = <0x14>; 1023e086d82dSMikko Perttunen nvidia,dqs-trim = <40>; 1024e086d82dSMikko Perttunen supports-cqe; 102563944891SThierry Reding status = "disabled"; 102663944891SThierry Reding }; 102763944891SThierry Reding 1028621e12a1SMohan Kumar hda@3510000 { 1029621e12a1SMohan Kumar compatible = "nvidia,tegra234-hda", "nvidia,tegra30-hda"; 1030621e12a1SMohan Kumar reg = <0x3510000 0x10000>; 1031621e12a1SMohan Kumar interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 1032621e12a1SMohan Kumar clocks = <&bpmp TEGRA234_CLK_AZA_BIT>, 1033621e12a1SMohan Kumar <&bpmp TEGRA234_CLK_AZA_2XBIT>; 1034621e12a1SMohan Kumar clock-names = "hda", "hda2codec_2x"; 1035621e12a1SMohan Kumar resets = <&bpmp TEGRA234_RESET_HDA>, 1036621e12a1SMohan Kumar <&bpmp TEGRA234_RESET_HDACODEC>; 1037621e12a1SMohan Kumar reset-names = "hda", "hda2codec_2x"; 1038621e12a1SMohan Kumar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_DISP>; 1039621e12a1SMohan Kumar interconnects = <&mc TEGRA234_MEMORY_CLIENT_HDAR &emc>, 1040621e12a1SMohan Kumar <&mc TEGRA234_MEMORY_CLIENT_HDAW &emc>; 1041621e12a1SMohan Kumar interconnect-names = "dma-mem", "write"; 1042af4c2773SMohan Kumar iommus = <&smmu_niso0 TEGRA234_SID_HDA>; 1043621e12a1SMohan Kumar status = "disabled"; 1044621e12a1SMohan Kumar }; 1045621e12a1SMohan Kumar 104663944891SThierry Reding fuse@3810000 { 104763944891SThierry Reding compatible = "nvidia,tegra234-efuse"; 104863944891SThierry Reding reg = <0x03810000 0x10000>; 104963944891SThierry Reding clocks = <&bpmp TEGRA234_CLK_FUSE>; 105063944891SThierry Reding clock-names = "fuse"; 105163944891SThierry Reding }; 105263944891SThierry Reding 105363944891SThierry Reding hsp_top0: hsp@3c00000 { 105463944891SThierry Reding compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; 105563944891SThierry Reding reg = <0x03c00000 0xa0000>; 105663944891SThierry Reding interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 105763944891SThierry Reding <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 105863944891SThierry Reding <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 105963944891SThierry Reding <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 106063944891SThierry Reding <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 106163944891SThierry Reding <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 106263944891SThierry Reding <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 106363944891SThierry Reding <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 106463944891SThierry Reding <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 106563944891SThierry Reding interrupt-names = "doorbell", "shared0", "shared1", "shared2", 106663944891SThierry Reding "shared3", "shared4", "shared5", "shared6", 106763944891SThierry Reding "shared7"; 106863944891SThierry Reding #mbox-cells = <2>; 106963944891SThierry Reding }; 107063944891SThierry Reding 1071610cdf31SThierry Reding ethernet@6800000 { 1072610cdf31SThierry Reding compatible = "nvidia,tegra234-mgbe"; 1073610cdf31SThierry Reding reg = <0x06800000 0x10000>, 1074610cdf31SThierry Reding <0x06810000 0x10000>, 1075610cdf31SThierry Reding <0x068a0000 0x10000>; 1076610cdf31SThierry Reding reg-names = "hypervisor", "mac", "xpcs"; 1077610cdf31SThierry Reding interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>; 1078610cdf31SThierry Reding interrupt-names = "common"; 1079610cdf31SThierry Reding clocks = <&bpmp TEGRA234_CLK_MGBE0_APP>, 1080610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE0_MAC>, 1081610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE0_MAC_DIVIDER>, 1082610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE0_PTP_REF>, 1083610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT_M>, 1084610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT>, 1085610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE0_TX>, 1086610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE0_EEE_PCS>, 1087610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_INPUT>, 1088610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_M>, 1089610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE0_RX_PCS>, 1090610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE0_TX_PCS>; 1091610cdf31SThierry Reding clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", 1092610cdf31SThierry Reding "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", 1093610cdf31SThierry Reding "rx-pcs", "tx-pcs"; 1094610cdf31SThierry Reding resets = <&bpmp TEGRA234_RESET_MGBE0_MAC>, 1095610cdf31SThierry Reding <&bpmp TEGRA234_RESET_MGBE0_PCS>; 1096610cdf31SThierry Reding reset-names = "mac", "pcs"; 1097610cdf31SThierry Reding interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEARD &emc>, 1098610cdf31SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_MGBEAWR &emc>; 1099610cdf31SThierry Reding interconnect-names = "dma-mem", "write"; 1100610cdf31SThierry Reding iommus = <&smmu_niso0 TEGRA234_SID_MGBE>; 1101610cdf31SThierry Reding power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEA>; 1102610cdf31SThierry Reding status = "disabled"; 1103610cdf31SThierry Reding }; 1104610cdf31SThierry Reding 1105610cdf31SThierry Reding ethernet@6900000 { 1106610cdf31SThierry Reding compatible = "nvidia,tegra234-mgbe"; 1107610cdf31SThierry Reding reg = <0x06900000 0x10000>, 1108610cdf31SThierry Reding <0x06910000 0x10000>, 1109610cdf31SThierry Reding <0x069a0000 0x10000>; 1110610cdf31SThierry Reding reg-names = "hypervisor", "mac", "xpcs"; 1111610cdf31SThierry Reding interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>; 1112610cdf31SThierry Reding interrupt-names = "common"; 1113610cdf31SThierry Reding clocks = <&bpmp TEGRA234_CLK_MGBE1_APP>, 1114610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE1_MAC>, 1115610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE1_MAC_DIVIDER>, 1116610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE1_PTP_REF>, 1117610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE1_RX_INPUT_M>, 1118610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE1_RX_INPUT>, 1119610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE1_TX>, 1120610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE1_EEE_PCS>, 1121610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE1_RX_PCS_INPUT>, 1122610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE1_RX_PCS_M>, 1123610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE1_RX_PCS>, 1124610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE1_TX_PCS>; 1125610cdf31SThierry Reding clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", 1126610cdf31SThierry Reding "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", 1127610cdf31SThierry Reding "rx-pcs", "tx-pcs"; 1128610cdf31SThierry Reding resets = <&bpmp TEGRA234_RESET_MGBE1_MAC>, 1129610cdf31SThierry Reding <&bpmp TEGRA234_RESET_MGBE1_PCS>; 1130610cdf31SThierry Reding reset-names = "mac", "pcs"; 1131610cdf31SThierry Reding interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEBRD &emc>, 1132610cdf31SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_MGBEBWR &emc>; 1133610cdf31SThierry Reding interconnect-names = "dma-mem", "write"; 1134610cdf31SThierry Reding iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF1>; 1135610cdf31SThierry Reding power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEB>; 1136610cdf31SThierry Reding status = "disabled"; 1137610cdf31SThierry Reding }; 1138610cdf31SThierry Reding 1139610cdf31SThierry Reding ethernet@6a00000 { 1140610cdf31SThierry Reding compatible = "nvidia,tegra234-mgbe"; 1141610cdf31SThierry Reding reg = <0x06a00000 0x10000>, 1142610cdf31SThierry Reding <0x06a10000 0x10000>, 1143610cdf31SThierry Reding <0x06aa0000 0x10000>; 1144610cdf31SThierry Reding reg-names = "hypervisor", "mac", "xpcs"; 1145610cdf31SThierry Reding interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>; 1146610cdf31SThierry Reding interrupt-names = "common"; 1147610cdf31SThierry Reding clocks = <&bpmp TEGRA234_CLK_MGBE2_APP>, 1148610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE2_MAC>, 1149610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE2_MAC_DIVIDER>, 1150610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE2_PTP_REF>, 1151610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE2_RX_INPUT_M>, 1152610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE2_RX_INPUT>, 1153610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE2_TX>, 1154610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE2_EEE_PCS>, 1155610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE2_RX_PCS_INPUT>, 1156610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE2_RX_PCS_M>, 1157610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE2_RX_PCS>, 1158610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE2_TX_PCS>; 1159610cdf31SThierry Reding clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", 1160610cdf31SThierry Reding "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", 1161610cdf31SThierry Reding "rx-pcs", "tx-pcs"; 1162610cdf31SThierry Reding resets = <&bpmp TEGRA234_RESET_MGBE2_MAC>, 1163610cdf31SThierry Reding <&bpmp TEGRA234_RESET_MGBE2_PCS>; 1164610cdf31SThierry Reding reset-names = "mac", "pcs"; 1165610cdf31SThierry Reding interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBECRD &emc>, 1166610cdf31SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_MGBECWR &emc>; 1167610cdf31SThierry Reding interconnect-names = "dma-mem", "write"; 1168610cdf31SThierry Reding iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF2>; 1169610cdf31SThierry Reding power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEC>; 1170610cdf31SThierry Reding status = "disabled"; 1171610cdf31SThierry Reding }; 1172610cdf31SThierry Reding 1173610cdf31SThierry Reding ethernet@6b00000 { 1174610cdf31SThierry Reding compatible = "nvidia,tegra234-mgbe"; 1175610cdf31SThierry Reding reg = <0x06b00000 0x10000>, 1176610cdf31SThierry Reding <0x06b10000 0x10000>, 1177610cdf31SThierry Reding <0x06ba0000 0x10000>; 1178610cdf31SThierry Reding reg-names = "hypervisor", "mac", "xpcs"; 1179610cdf31SThierry Reding interrupts = <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 1180610cdf31SThierry Reding interrupt-names = "common"; 1181610cdf31SThierry Reding clocks = <&bpmp TEGRA234_CLK_MGBE3_APP>, 1182610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE3_MAC>, 1183610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE3_MAC_DIVIDER>, 1184610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE3_PTP_REF>, 1185610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE3_RX_INPUT_M>, 1186610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE3_RX_INPUT>, 1187610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE3_TX>, 1188610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE3_EEE_PCS>, 1189610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE3_RX_PCS_INPUT>, 1190610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE3_RX_PCS_M>, 1191610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE3_RX_PCS>, 1192610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE3_TX_PCS>; 1193610cdf31SThierry Reding clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", 1194610cdf31SThierry Reding "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", 1195610cdf31SThierry Reding "rx-pcs", "tx-pcs"; 1196610cdf31SThierry Reding resets = <&bpmp TEGRA234_RESET_MGBE3_MAC>, 1197610cdf31SThierry Reding <&bpmp TEGRA234_RESET_MGBE3_PCS>; 1198610cdf31SThierry Reding reset-names = "mac", "pcs"; 1199610cdf31SThierry Reding interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEDRD &emc>, 1200610cdf31SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_MGBEDWR &emc>; 1201610cdf31SThierry Reding interconnect-names = "dma-mem", "write"; 1202610cdf31SThierry Reding iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF3>; 1203610cdf31SThierry Reding power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBED>; 1204610cdf31SThierry Reding status = "disabled"; 1205610cdf31SThierry Reding }; 1206610cdf31SThierry Reding 12075710e16aSThierry Reding smmu_niso1: iommu@8000000 { 12085710e16aSThierry Reding compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; 12095710e16aSThierry Reding reg = <0x8000000 0x1000000>, 12105710e16aSThierry Reding <0x7000000 0x1000000>; 12115710e16aSThierry Reding interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12125710e16aSThierry Reding <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, 12135710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12145710e16aSThierry Reding <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, 12155710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12165710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12175710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12185710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12195710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12205710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12215710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12225710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12235710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12245710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12255710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12265710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12275710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12285710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12295710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12305710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12315710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12325710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12335710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12345710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12355710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12365710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12375710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12385710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12395710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12405710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12415710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12425710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12435710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12445710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12455710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12465710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12475710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12485710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12495710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12505710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12515710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12525710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12535710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12545710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12555710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12565710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12575710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12585710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12595710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12605710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12615710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12625710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12635710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12645710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12655710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12665710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12675710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12685710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12695710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12705710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12715710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12725710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12735710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12745710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12755710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12765710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12775710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12785710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12795710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12805710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12815710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12825710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12835710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12845710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12855710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12865710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12875710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12885710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12895710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12905710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12915710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12925710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12935710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12945710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12955710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12965710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12975710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12985710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 12995710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13005710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13015710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13025710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13035710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13045710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13055710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13065710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13075710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13085710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13095710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13105710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13115710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13125710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13135710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13145710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13155710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13165710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13175710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13185710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13195710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13205710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13215710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13225710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13235710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13245710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13255710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13265710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13275710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13285710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13295710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13305710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13315710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13325710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13335710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13345710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13355710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13365710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13375710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13385710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13395710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 13405710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 13415710e16aSThierry Reding stream-match-mask = <0x7f80>; 13425710e16aSThierry Reding #global-interrupts = <2>; 13435710e16aSThierry Reding #iommu-cells = <1>; 13445710e16aSThierry Reding 13455710e16aSThierry Reding nvidia,memory-controller = <&mc>; 13465710e16aSThierry Reding status = "okay"; 13475710e16aSThierry Reding }; 13485710e16aSThierry Reding 1349302e1540SSumit Gupta sce-fabric@b600000 { 1350302e1540SSumit Gupta compatible = "nvidia,tegra234-sce-fabric"; 1351302e1540SSumit Gupta reg = <0xb600000 0x40000>; 1352302e1540SSumit Gupta interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 1353302e1540SSumit Gupta status = "okay"; 1354302e1540SSumit Gupta }; 1355302e1540SSumit Gupta 1356302e1540SSumit Gupta rce-fabric@be00000 { 1357302e1540SSumit Gupta compatible = "nvidia,tegra234-rce-fabric"; 1358302e1540SSumit Gupta reg = <0xbe00000 0x40000>; 1359302e1540SSumit Gupta interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 1360302e1540SSumit Gupta status = "okay"; 1361302e1540SSumit Gupta }; 1362302e1540SSumit Gupta 1363ec142c44SVidya Sagar p2u_hsio_0: phy@3e00000 { 1364ec142c44SVidya Sagar compatible = "nvidia,tegra234-p2u"; 1365ec142c44SVidya Sagar reg = <0x03e00000 0x10000>; 1366ec142c44SVidya Sagar reg-names = "ctl"; 1367ec142c44SVidya Sagar 1368ec142c44SVidya Sagar #phy-cells = <0>; 1369ec142c44SVidya Sagar }; 1370ec142c44SVidya Sagar 1371ec142c44SVidya Sagar p2u_hsio_1: phy@3e10000 { 1372ec142c44SVidya Sagar compatible = "nvidia,tegra234-p2u"; 1373ec142c44SVidya Sagar reg = <0x03e10000 0x10000>; 1374ec142c44SVidya Sagar reg-names = "ctl"; 1375ec142c44SVidya Sagar 1376ec142c44SVidya Sagar #phy-cells = <0>; 1377ec142c44SVidya Sagar }; 1378ec142c44SVidya Sagar 1379ec142c44SVidya Sagar p2u_hsio_2: phy@3e20000 { 1380ec142c44SVidya Sagar compatible = "nvidia,tegra234-p2u"; 1381ec142c44SVidya Sagar reg = <0x03e20000 0x10000>; 1382ec142c44SVidya Sagar reg-names = "ctl"; 1383ec142c44SVidya Sagar 1384ec142c44SVidya Sagar #phy-cells = <0>; 1385ec142c44SVidya Sagar }; 1386ec142c44SVidya Sagar 1387ec142c44SVidya Sagar p2u_hsio_3: phy@3e30000 { 1388ec142c44SVidya Sagar compatible = "nvidia,tegra234-p2u"; 1389ec142c44SVidya Sagar reg = <0x03e30000 0x10000>; 1390ec142c44SVidya Sagar reg-names = "ctl"; 1391ec142c44SVidya Sagar 1392ec142c44SVidya Sagar #phy-cells = <0>; 1393ec142c44SVidya Sagar }; 1394ec142c44SVidya Sagar 1395ec142c44SVidya Sagar p2u_hsio_4: phy@3e40000 { 1396ec142c44SVidya Sagar compatible = "nvidia,tegra234-p2u"; 1397ec142c44SVidya Sagar reg = <0x03e40000 0x10000>; 1398ec142c44SVidya Sagar reg-names = "ctl"; 1399ec142c44SVidya Sagar 1400ec142c44SVidya Sagar #phy-cells = <0>; 1401ec142c44SVidya Sagar }; 1402ec142c44SVidya Sagar 1403ec142c44SVidya Sagar p2u_hsio_5: phy@3e50000 { 1404ec142c44SVidya Sagar compatible = "nvidia,tegra234-p2u"; 1405ec142c44SVidya Sagar reg = <0x03e50000 0x10000>; 1406ec142c44SVidya Sagar reg-names = "ctl"; 1407ec142c44SVidya Sagar 1408ec142c44SVidya Sagar #phy-cells = <0>; 1409ec142c44SVidya Sagar }; 1410ec142c44SVidya Sagar 1411ec142c44SVidya Sagar p2u_hsio_6: phy@3e60000 { 1412ec142c44SVidya Sagar compatible = "nvidia,tegra234-p2u"; 1413ec142c44SVidya Sagar reg = <0x03e60000 0x10000>; 1414ec142c44SVidya Sagar reg-names = "ctl"; 1415ec142c44SVidya Sagar 1416ec142c44SVidya Sagar #phy-cells = <0>; 1417ec142c44SVidya Sagar }; 1418ec142c44SVidya Sagar 1419ec142c44SVidya Sagar p2u_hsio_7: phy@3e70000 { 1420ec142c44SVidya Sagar compatible = "nvidia,tegra234-p2u"; 1421ec142c44SVidya Sagar reg = <0x03e70000 0x10000>; 1422ec142c44SVidya Sagar reg-names = "ctl"; 1423ec142c44SVidya Sagar 1424ec142c44SVidya Sagar #phy-cells = <0>; 1425ec142c44SVidya Sagar }; 1426ec142c44SVidya Sagar 1427ec142c44SVidya Sagar p2u_nvhs_0: phy@3e90000 { 1428ec142c44SVidya Sagar compatible = "nvidia,tegra234-p2u"; 1429ec142c44SVidya Sagar reg = <0x03e90000 0x10000>; 1430ec142c44SVidya Sagar reg-names = "ctl"; 1431ec142c44SVidya Sagar 1432ec142c44SVidya Sagar #phy-cells = <0>; 1433ec142c44SVidya Sagar }; 1434ec142c44SVidya Sagar 1435ec142c44SVidya Sagar p2u_nvhs_1: phy@3ea0000 { 1436ec142c44SVidya Sagar compatible = "nvidia,tegra234-p2u"; 1437ec142c44SVidya Sagar reg = <0x03ea0000 0x10000>; 1438ec142c44SVidya Sagar reg-names = "ctl"; 1439ec142c44SVidya Sagar 1440ec142c44SVidya Sagar #phy-cells = <0>; 1441ec142c44SVidya Sagar }; 1442ec142c44SVidya Sagar 1443ec142c44SVidya Sagar p2u_nvhs_2: phy@3eb0000 { 1444ec142c44SVidya Sagar compatible = "nvidia,tegra234-p2u"; 1445ec142c44SVidya Sagar reg = <0x03eb0000 0x10000>; 1446ec142c44SVidya Sagar reg-names = "ctl"; 1447ec142c44SVidya Sagar 1448ec142c44SVidya Sagar #phy-cells = <0>; 1449ec142c44SVidya Sagar }; 1450ec142c44SVidya Sagar 1451ec142c44SVidya Sagar p2u_nvhs_3: phy@3ec0000 { 1452ec142c44SVidya Sagar compatible = "nvidia,tegra234-p2u"; 1453ec142c44SVidya Sagar reg = <0x03ec0000 0x10000>; 1454ec142c44SVidya Sagar reg-names = "ctl"; 1455ec142c44SVidya Sagar 1456ec142c44SVidya Sagar #phy-cells = <0>; 1457ec142c44SVidya Sagar }; 1458ec142c44SVidya Sagar 1459ec142c44SVidya Sagar p2u_nvhs_4: phy@3ed0000 { 1460ec142c44SVidya Sagar compatible = "nvidia,tegra234-p2u"; 1461ec142c44SVidya Sagar reg = <0x03ed0000 0x10000>; 1462ec142c44SVidya Sagar reg-names = "ctl"; 1463ec142c44SVidya Sagar 1464ec142c44SVidya Sagar #phy-cells = <0>; 1465ec142c44SVidya Sagar }; 1466ec142c44SVidya Sagar 1467ec142c44SVidya Sagar p2u_nvhs_5: phy@3ee0000 { 1468ec142c44SVidya Sagar compatible = "nvidia,tegra234-p2u"; 1469ec142c44SVidya Sagar reg = <0x03ee0000 0x10000>; 1470ec142c44SVidya Sagar reg-names = "ctl"; 1471ec142c44SVidya Sagar 1472ec142c44SVidya Sagar #phy-cells = <0>; 1473ec142c44SVidya Sagar }; 1474ec142c44SVidya Sagar 1475ec142c44SVidya Sagar p2u_nvhs_6: phy@3ef0000 { 1476ec142c44SVidya Sagar compatible = "nvidia,tegra234-p2u"; 1477ec142c44SVidya Sagar reg = <0x03ef0000 0x10000>; 1478ec142c44SVidya Sagar reg-names = "ctl"; 1479ec142c44SVidya Sagar 1480ec142c44SVidya Sagar #phy-cells = <0>; 1481ec142c44SVidya Sagar }; 1482ec142c44SVidya Sagar 1483ec142c44SVidya Sagar p2u_nvhs_7: phy@3f00000 { 1484ec142c44SVidya Sagar compatible = "nvidia,tegra234-p2u"; 1485ec142c44SVidya Sagar reg = <0x03f00000 0x10000>; 1486ec142c44SVidya Sagar reg-names = "ctl"; 1487ec142c44SVidya Sagar 1488ec142c44SVidya Sagar #phy-cells = <0>; 1489ec142c44SVidya Sagar }; 1490ec142c44SVidya Sagar 1491ec142c44SVidya Sagar p2u_gbe_0: phy@3f20000 { 1492ec142c44SVidya Sagar compatible = "nvidia,tegra234-p2u"; 1493ec142c44SVidya Sagar reg = <0x03f20000 0x10000>; 1494ec142c44SVidya Sagar reg-names = "ctl"; 1495ec142c44SVidya Sagar 1496ec142c44SVidya Sagar #phy-cells = <0>; 1497ec142c44SVidya Sagar }; 1498ec142c44SVidya Sagar 1499ec142c44SVidya Sagar p2u_gbe_1: phy@3f30000 { 1500ec142c44SVidya Sagar compatible = "nvidia,tegra234-p2u"; 1501ec142c44SVidya Sagar reg = <0x03f30000 0x10000>; 1502ec142c44SVidya Sagar reg-names = "ctl"; 1503ec142c44SVidya Sagar 1504ec142c44SVidya Sagar #phy-cells = <0>; 1505ec142c44SVidya Sagar }; 1506ec142c44SVidya Sagar 1507ec142c44SVidya Sagar p2u_gbe_2: phy@3f40000 { 1508ec142c44SVidya Sagar compatible = "nvidia,tegra234-p2u"; 1509ec142c44SVidya Sagar reg = <0x03f40000 0x10000>; 1510ec142c44SVidya Sagar reg-names = "ctl"; 1511ec142c44SVidya Sagar 1512ec142c44SVidya Sagar #phy-cells = <0>; 1513ec142c44SVidya Sagar }; 1514ec142c44SVidya Sagar 1515ec142c44SVidya Sagar p2u_gbe_3: phy@3f50000 { 1516ec142c44SVidya Sagar compatible = "nvidia,tegra234-p2u"; 1517ec142c44SVidya Sagar reg = <0x03f50000 0x10000>; 1518ec142c44SVidya Sagar reg-names = "ctl"; 1519ec142c44SVidya Sagar 1520ec142c44SVidya Sagar #phy-cells = <0>; 1521ec142c44SVidya Sagar }; 1522ec142c44SVidya Sagar 1523ec142c44SVidya Sagar p2u_gbe_4: phy@3f60000 { 1524ec142c44SVidya Sagar compatible = "nvidia,tegra234-p2u"; 1525ec142c44SVidya Sagar reg = <0x03f60000 0x10000>; 1526ec142c44SVidya Sagar reg-names = "ctl"; 1527ec142c44SVidya Sagar 1528ec142c44SVidya Sagar #phy-cells = <0>; 1529ec142c44SVidya Sagar }; 1530ec142c44SVidya Sagar 1531ec142c44SVidya Sagar p2u_gbe_5: phy@3f70000 { 1532ec142c44SVidya Sagar compatible = "nvidia,tegra234-p2u"; 1533ec142c44SVidya Sagar reg = <0x03f70000 0x10000>; 1534ec142c44SVidya Sagar reg-names = "ctl"; 1535ec142c44SVidya Sagar 1536ec142c44SVidya Sagar #phy-cells = <0>; 1537ec142c44SVidya Sagar }; 1538ec142c44SVidya Sagar 1539ec142c44SVidya Sagar p2u_gbe_6: phy@3f80000 { 1540ec142c44SVidya Sagar compatible = "nvidia,tegra234-p2u"; 1541ec142c44SVidya Sagar reg = <0x03f80000 0x10000>; 1542ec142c44SVidya Sagar reg-names = "ctl"; 1543ec142c44SVidya Sagar 1544ec142c44SVidya Sagar #phy-cells = <0>; 1545ec142c44SVidya Sagar }; 1546ec142c44SVidya Sagar 1547ec142c44SVidya Sagar p2u_gbe_7: phy@3f90000 { 1548ec142c44SVidya Sagar compatible = "nvidia,tegra234-p2u"; 1549ec142c44SVidya Sagar reg = <0x03f90000 0x10000>; 1550ec142c44SVidya Sagar reg-names = "ctl"; 1551ec142c44SVidya Sagar 1552ec142c44SVidya Sagar #phy-cells = <0>; 1553ec142c44SVidya Sagar }; 1554ec142c44SVidya Sagar 155563944891SThierry Reding hsp_aon: hsp@c150000 { 155663944891SThierry Reding compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; 155763944891SThierry Reding reg = <0x0c150000 0x90000>; 155863944891SThierry Reding interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 155963944891SThierry Reding <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 156063944891SThierry Reding <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 156163944891SThierry Reding <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 156263944891SThierry Reding /* 156363944891SThierry Reding * Shared interrupt 0 is routed only to AON/SPE, so 156463944891SThierry Reding * we only have 4 shared interrupts for the CCPLEX. 156563944891SThierry Reding */ 156663944891SThierry Reding interrupt-names = "shared1", "shared2", "shared3", "shared4"; 156763944891SThierry Reding #mbox-cells = <2>; 156863944891SThierry Reding }; 156963944891SThierry Reding 1570156af9deSAkhil R gen2_i2c: i2c@c240000 { 1571156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 1572156af9deSAkhil R reg = <0xc240000 0x100>; 1573156af9deSAkhil R interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1574156af9deSAkhil R status = "disabled"; 1575156af9deSAkhil R clock-frequency = <100000>; 1576156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C2 1577156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 1578156af9deSAkhil R clock-names = "div-clk", "parent"; 1579156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C2>; 1580156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 1581156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C2>; 1582156af9deSAkhil R reset-names = "i2c"; 15838e442805SAkhil R iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 15848e442805SAkhil R dma-coherent; 15858e442805SAkhil R dmas = <&gpcdma 22>, <&gpcdma 22>; 15868e442805SAkhil R dma-names = "rx", "tx"; 1587156af9deSAkhil R }; 1588156af9deSAkhil R 1589156af9deSAkhil R gen8_i2c: i2c@c250000 { 1590156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 1591156af9deSAkhil R reg = <0xc250000 0x100>; 1592156af9deSAkhil R interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1593156af9deSAkhil R status = "disabled"; 1594156af9deSAkhil R clock-frequency = <400000>; 1595156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C8 1596156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 1597156af9deSAkhil R clock-names = "div-clk", "parent"; 1598156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C8>; 1599156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 1600156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C8>; 1601156af9deSAkhil R reset-names = "i2c"; 16028e442805SAkhil R iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 16038e442805SAkhil R dma-coherent; 16048e442805SAkhil R dmas = <&gpcdma 0>, <&gpcdma 0>; 16058e442805SAkhil R dma-names = "rx", "tx"; 1606156af9deSAkhil R }; 1607156af9deSAkhil R 160863944891SThierry Reding rtc@c2a0000 { 160963944891SThierry Reding compatible = "nvidia,tegra234-rtc", "nvidia,tegra20-rtc"; 161063944891SThierry Reding reg = <0x0c2a0000 0x10000>; 161163944891SThierry Reding interrupt-parent = <&pmc>; 161263944891SThierry Reding interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 1613e537addeSMikko Perttunen clocks = <&bpmp TEGRA234_CLK_CLK_32K>; 1614e537addeSMikko Perttunen clock-names = "rtc"; 161563944891SThierry Reding status = "disabled"; 161663944891SThierry Reding }; 161763944891SThierry Reding 1618f0e12668SThierry Reding gpio_aon: gpio@c2f0000 { 1619f0e12668SThierry Reding compatible = "nvidia,tegra234-gpio-aon"; 1620f0e12668SThierry Reding reg-names = "security", "gpio"; 1621f0e12668SThierry Reding reg = <0x0c2f0000 0x1000>, 1622f0e12668SThierry Reding <0x0c2f1000 0x1000>; 1623f0e12668SThierry Reding interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1624f0e12668SThierry Reding <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1625f0e12668SThierry Reding <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1626f0e12668SThierry Reding <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 1627f0e12668SThierry Reding #interrupt-cells = <2>; 1628f0e12668SThierry Reding interrupt-controller; 1629f0e12668SThierry Reding #gpio-cells = <2>; 1630f0e12668SThierry Reding gpio-controller; 1631f0e12668SThierry Reding }; 1632f0e12668SThierry Reding 1633*2566d28cSJon Hunter pwm4: pwm@c340000 { 1634*2566d28cSJon Hunter compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 1635*2566d28cSJon Hunter reg = <0xc340000 0x10000>; 1636*2566d28cSJon Hunter clocks = <&bpmp TEGRA234_CLK_PWM4>; 1637*2566d28cSJon Hunter clock-names = "pwm"; 1638*2566d28cSJon Hunter resets = <&bpmp TEGRA234_RESET_PWM4>; 1639*2566d28cSJon Hunter reset-names = "pwm"; 1640*2566d28cSJon Hunter status = "disabled"; 1641*2566d28cSJon Hunter #pwm-cells = <2>; 1642*2566d28cSJon Hunter }; 1643*2566d28cSJon Hunter 164463944891SThierry Reding pmc: pmc@c360000 { 164563944891SThierry Reding compatible = "nvidia,tegra234-pmc"; 164663944891SThierry Reding reg = <0x0c360000 0x10000>, 164763944891SThierry Reding <0x0c370000 0x10000>, 164863944891SThierry Reding <0x0c380000 0x10000>, 164963944891SThierry Reding <0x0c390000 0x10000>, 165063944891SThierry Reding <0x0c3a0000 0x10000>; 165163944891SThierry Reding reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 165263944891SThierry Reding 165363944891SThierry Reding #interrupt-cells = <2>; 165463944891SThierry Reding interrupt-controller; 165563944891SThierry Reding }; 165663944891SThierry Reding 1657302e1540SSumit Gupta aon-fabric@c600000 { 1658302e1540SSumit Gupta compatible = "nvidia,tegra234-aon-fabric"; 1659302e1540SSumit Gupta reg = <0xc600000 0x40000>; 1660302e1540SSumit Gupta interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 1661302e1540SSumit Gupta status = "okay"; 1662302e1540SSumit Gupta }; 1663302e1540SSumit Gupta 1664302e1540SSumit Gupta bpmp-fabric@d600000 { 1665302e1540SSumit Gupta compatible = "nvidia,tegra234-bpmp-fabric"; 1666302e1540SSumit Gupta reg = <0xd600000 0x40000>; 1667302e1540SSumit Gupta interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1668302e1540SSumit Gupta status = "okay"; 1669302e1540SSumit Gupta }; 1670302e1540SSumit Gupta 1671302e1540SSumit Gupta dce-fabric@de00000 { 1672302e1540SSumit Gupta compatible = "nvidia,tegra234-sce-fabric"; 1673302e1540SSumit Gupta reg = <0xde00000 0x40000>; 1674302e1540SSumit Gupta interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>; 1675302e1540SSumit Gupta status = "okay"; 1676302e1540SSumit Gupta }; 1677302e1540SSumit Gupta 167863944891SThierry Reding gic: interrupt-controller@f400000 { 167963944891SThierry Reding compatible = "arm,gic-v3"; 168063944891SThierry Reding reg = <0x0f400000 0x010000>, /* GICD */ 168163944891SThierry Reding <0x0f440000 0x200000>; /* GICR */ 168263944891SThierry Reding interrupt-parent = <&gic>; 168363944891SThierry Reding interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 168463944891SThierry Reding 168563944891SThierry Reding #redistributor-regions = <1>; 168663944891SThierry Reding #interrupt-cells = <3>; 168763944891SThierry Reding interrupt-controller; 168863944891SThierry Reding }; 16895710e16aSThierry Reding 16905710e16aSThierry Reding smmu_iso: iommu@10000000{ 16915710e16aSThierry Reding compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; 16925710e16aSThierry Reding reg = <0x10000000 0x1000000>; 16935710e16aSThierry Reding interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16945710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16955710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16965710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16975710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16985710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 16995710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17005710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17015710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17025710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17035710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17045710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17055710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17065710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17075710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17085710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17095710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17105710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17115710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17125710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17135710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17145710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17155710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17165710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17175710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17185710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17195710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17205710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17215710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17225710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17235710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17245710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17255710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17265710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17275710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17285710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17295710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17305710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17315710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17325710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17335710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17345710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17355710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17365710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17375710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17385710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17395710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17405710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17415710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17425710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17435710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17445710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17455710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17465710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17475710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17485710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17495710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17505710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17515710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17525710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17535710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17545710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17555710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17565710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17575710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17585710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17595710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17605710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17615710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17625710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17635710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17645710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17655710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17665710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17675710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17685710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17695710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17705710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17715710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17725710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17735710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17745710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17755710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17765710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17775710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17785710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17795710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17805710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17815710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17825710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17835710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17845710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17855710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17865710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17875710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17885710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17895710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17905710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17915710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17925710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17935710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17945710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17955710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17965710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17975710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17985710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 17995710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18005710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18015710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18025710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18035710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18045710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18055710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18065710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18075710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18085710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18095710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18105710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18115710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18125710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18135710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18145710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18155710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18165710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18175710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18185710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18195710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18205710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 18215710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 18225710e16aSThierry Reding stream-match-mask = <0x7f80>; 18235710e16aSThierry Reding #global-interrupts = <1>; 18245710e16aSThierry Reding #iommu-cells = <1>; 18255710e16aSThierry Reding 18265710e16aSThierry Reding nvidia,memory-controller = <&mc>; 18275710e16aSThierry Reding status = "okay"; 18285710e16aSThierry Reding }; 18295710e16aSThierry Reding 18305710e16aSThierry Reding smmu_niso0: iommu@12000000 { 18315710e16aSThierry Reding compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; 18325710e16aSThierry Reding reg = <0x12000000 0x1000000>, 18335710e16aSThierry Reding <0x11000000 0x1000000>; 18345710e16aSThierry Reding interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18355710e16aSThierry Reding <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 18365710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18375710e16aSThierry Reding <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 18385710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18395710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18405710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18415710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18425710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18435710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18445710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18455710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18465710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18475710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18485710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18495710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18505710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18515710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18525710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18535710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18545710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18555710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18565710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18575710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18585710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18595710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18605710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18615710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18625710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18635710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18645710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18655710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18665710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18675710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18685710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18695710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18705710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18715710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18725710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18735710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18745710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18755710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18765710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18775710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18785710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18795710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18805710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18815710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18825710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18835710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18845710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18855710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18865710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18875710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18885710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18895710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18905710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18915710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18925710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18935710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18945710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18955710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18965710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18975710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18985710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 18995710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19005710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19015710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19025710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19035710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19045710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19055710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19065710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19075710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19085710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19095710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19105710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19115710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19125710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19135710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19145710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19155710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19165710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19175710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19185710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19195710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19205710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19215710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19225710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19235710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19245710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19255710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19265710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19275710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19285710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19295710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19305710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19315710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19325710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19335710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19345710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19355710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19365710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19375710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19385710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19395710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19405710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19415710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19425710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19435710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19445710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19455710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19465710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19475710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19485710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19495710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19505710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19515710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19525710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19535710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19545710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19555710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19565710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19575710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19585710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19595710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19605710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19615710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19625710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 19635710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 19645710e16aSThierry Reding stream-match-mask = <0x7f80>; 19655710e16aSThierry Reding #global-interrupts = <2>; 19665710e16aSThierry Reding #iommu-cells = <1>; 19675710e16aSThierry Reding 19685710e16aSThierry Reding nvidia,memory-controller = <&mc>; 19695710e16aSThierry Reding status = "okay"; 19705710e16aSThierry Reding }; 1971302e1540SSumit Gupta 1972302e1540SSumit Gupta cbb-fabric@13a00000 { 1973302e1540SSumit Gupta compatible = "nvidia,tegra234-cbb-fabric"; 1974302e1540SSumit Gupta reg = <0x13a00000 0x400000>; 1975302e1540SSumit Gupta interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 1976302e1540SSumit Gupta status = "okay"; 1977302e1540SSumit Gupta }; 197863944891SThierry Reding }; 197963944891SThierry Reding 1980962c400dSSumit Gupta ccplex@e000000 { 1981962c400dSSumit Gupta compatible = "nvidia,tegra234-ccplex-cluster"; 1982962c400dSSumit Gupta reg = <0x0 0x0e000000 0x0 0x5ffff>; 1983962c400dSSumit Gupta nvidia,bpmp = <&bpmp>; 1984962c400dSSumit Gupta status = "okay"; 1985962c400dSSumit Gupta }; 1986962c400dSSumit Gupta 1987ec142c44SVidya Sagar pcie@140a0000 { 1988ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie"; 1989ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CA>; 1990ec142c44SVidya Sagar reg = <0x00 0x140a0000 0x0 0x00020000>, /* appl registers (128K) */ 1991ec142c44SVidya Sagar <0x00 0x2a000000 0x0 0x00040000>, /* configuration space (256K) */ 1992ec142c44SVidya Sagar <0x00 0x2a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1993ec142c44SVidya Sagar <0x00 0x2a080000 0x0 0x00040000>; /* DBI reg space (256K) */ 1994ec142c44SVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 1995ec142c44SVidya Sagar 1996ec142c44SVidya Sagar #address-cells = <3>; 1997ec142c44SVidya Sagar #size-cells = <2>; 1998ec142c44SVidya Sagar device_type = "pci"; 1999ec142c44SVidya Sagar num-lanes = <4>; 2000ec142c44SVidya Sagar num-viewport = <8>; 2001ec142c44SVidya Sagar linux,pci-domain = <8>; 2002ec142c44SVidya Sagar 2003ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX2_C8_CORE>; 2004ec142c44SVidya Sagar clock-names = "core"; 2005ec142c44SVidya Sagar 2006ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX2_CORE_8_APB>, 2007ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX2_CORE_8>; 2008ec142c44SVidya Sagar reset-names = "apb", "core"; 2009ec142c44SVidya Sagar 2010ec142c44SVidya Sagar interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2011ec142c44SVidya Sagar <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2012ec142c44SVidya Sagar interrupt-names = "intr", "msi"; 2013ec142c44SVidya Sagar 2014ec142c44SVidya Sagar #interrupt-cells = <1>; 2015ec142c44SVidya Sagar interrupt-map-mask = <0 0 0 0>; 2016ec142c44SVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 2017ec142c44SVidya Sagar 2018ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 8>; 2019ec142c44SVidya Sagar 2020ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2021ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2022ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2023ec142c44SVidya Sagar 2024ec142c44SVidya Sagar bus-range = <0x0 0xff>; 2025ec142c44SVidya Sagar 2026ec142c44SVidya Sagar ranges = <0x43000000 0x32 0x40000000 0x32 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2027ec142c44SVidya Sagar <0x02000000 0x0 0x40000000 0x35 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2028ec142c44SVidya Sagar <0x01000000 0x0 0x2a100000 0x00 0x2a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2029ec142c44SVidya Sagar 2030ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE8AR &emc>, 2031ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE8AW &emc>; 2032ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2033ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE8 0x1000>; 2034ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2035ec142c44SVidya Sagar dma-coherent; 2036ec142c44SVidya Sagar 2037ec142c44SVidya Sagar status = "disabled"; 2038ec142c44SVidya Sagar }; 2039ec142c44SVidya Sagar 2040ec142c44SVidya Sagar pcie@140c0000 { 2041ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie"; 2042ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CB>; 2043ec142c44SVidya Sagar reg = <0x00 0x140c0000 0x0 0x00020000>, /* appl registers (128K) */ 2044ec142c44SVidya Sagar <0x00 0x2c000000 0x0 0x00040000>, /* configuration space (256K) */ 2045ec142c44SVidya Sagar <0x00 0x2c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2046ec142c44SVidya Sagar <0x00 0x2c080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2047ec142c44SVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 2048ec142c44SVidya Sagar 2049ec142c44SVidya Sagar #address-cells = <3>; 2050ec142c44SVidya Sagar #size-cells = <2>; 2051ec142c44SVidya Sagar device_type = "pci"; 2052ec142c44SVidya Sagar num-lanes = <4>; 2053ec142c44SVidya Sagar num-viewport = <8>; 2054ec142c44SVidya Sagar linux,pci-domain = <9>; 2055ec142c44SVidya Sagar 2056ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX2_C9_CORE>; 2057ec142c44SVidya Sagar clock-names = "core"; 2058ec142c44SVidya Sagar 2059ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX2_CORE_9_APB>, 2060ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX2_CORE_9>; 2061ec142c44SVidya Sagar reset-names = "apb", "core"; 2062ec142c44SVidya Sagar 2063ec142c44SVidya Sagar interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2064ec142c44SVidya Sagar <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2065ec142c44SVidya Sagar interrupt-names = "intr", "msi"; 2066ec142c44SVidya Sagar 2067ec142c44SVidya Sagar #interrupt-cells = <1>; 2068ec142c44SVidya Sagar interrupt-map-mask = <0 0 0 0>; 2069ec142c44SVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2070ec142c44SVidya Sagar 2071ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 9>; 2072ec142c44SVidya Sagar 2073ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2074ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2075ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2076ec142c44SVidya Sagar 2077ec142c44SVidya Sagar bus-range = <0x0 0xff>; 2078ec142c44SVidya Sagar 207924840065SVidya Sagar ranges = <0x43000000 0x35 0x40000000 0x35 0x40000000 0x2 0xc0000000>, /* prefetchable memory (11264 MB) */ 2080ec142c44SVidya Sagar <0x02000000 0x0 0x40000000 0x38 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2081ec142c44SVidya Sagar <0x01000000 0x0 0x2c100000 0x00 0x2c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2082ec142c44SVidya Sagar 2083ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE9AR &emc>, 2084ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE9AW &emc>; 2085ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2086ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE9 0x1000>; 2087ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2088ec142c44SVidya Sagar dma-coherent; 2089ec142c44SVidya Sagar 2090ec142c44SVidya Sagar status = "disabled"; 2091ec142c44SVidya Sagar }; 2092ec142c44SVidya Sagar 2093ec142c44SVidya Sagar pcie@140e0000 { 2094ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie"; 2095ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CC>; 2096ec142c44SVidya Sagar reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K) */ 2097ec142c44SVidya Sagar <0x00 0x2e000000 0x0 0x00040000>, /* configuration space (256K) */ 2098ec142c44SVidya Sagar <0x00 0x2e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2099ec142c44SVidya Sagar <0x00 0x2e080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2100ec142c44SVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 2101ec142c44SVidya Sagar 2102ec142c44SVidya Sagar #address-cells = <3>; 2103ec142c44SVidya Sagar #size-cells = <2>; 2104ec142c44SVidya Sagar device_type = "pci"; 2105ec142c44SVidya Sagar num-lanes = <4>; 2106ec142c44SVidya Sagar num-viewport = <8>; 2107ec142c44SVidya Sagar linux,pci-domain = <10>; 2108ec142c44SVidya Sagar 2109ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX2_C10_CORE>; 2110ec142c44SVidya Sagar clock-names = "core"; 2111ec142c44SVidya Sagar 2112ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX2_CORE_10_APB>, 2113ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX2_CORE_10>; 2114ec142c44SVidya Sagar reset-names = "apb", "core"; 2115ec142c44SVidya Sagar 2116ec142c44SVidya Sagar interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2117ec142c44SVidya Sagar <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2118ec142c44SVidya Sagar interrupt-names = "intr", "msi"; 2119ec142c44SVidya Sagar 2120ec142c44SVidya Sagar #interrupt-cells = <1>; 2121ec142c44SVidya Sagar interrupt-map-mask = <0 0 0 0>; 2122ec142c44SVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 2123ec142c44SVidya Sagar 2124ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 10>; 2125ec142c44SVidya Sagar 2126ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2127ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2128ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2129ec142c44SVidya Sagar 2130ec142c44SVidya Sagar bus-range = <0x0 0xff>; 2131ec142c44SVidya Sagar 2132ec142c44SVidya Sagar ranges = <0x43000000 0x38 0x40000000 0x38 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2133ec142c44SVidya Sagar <0x02000000 0x0 0x40000000 0x3b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2134ec142c44SVidya Sagar <0x01000000 0x0 0x2e100000 0x00 0x2e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2135ec142c44SVidya Sagar 2136ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE10AR &emc>, 2137ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE10AW &emc>; 2138ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2139ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>; 2140ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2141ec142c44SVidya Sagar dma-coherent; 2142ec142c44SVidya Sagar 2143ec142c44SVidya Sagar status = "disabled"; 2144ec142c44SVidya Sagar }; 2145ec142c44SVidya Sagar 2146ec142c44SVidya Sagar pcie@14100000 { 2147ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie"; 2148ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>; 2149ec142c44SVidya Sagar reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */ 2150ec142c44SVidya Sagar <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */ 2151ec142c44SVidya Sagar <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2152ec142c44SVidya Sagar <0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2153ec142c44SVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 2154ec142c44SVidya Sagar 2155ec142c44SVidya Sagar #address-cells = <3>; 2156ec142c44SVidya Sagar #size-cells = <2>; 2157ec142c44SVidya Sagar device_type = "pci"; 2158ec142c44SVidya Sagar num-lanes = <1>; 2159ec142c44SVidya Sagar num-viewport = <8>; 2160ec142c44SVidya Sagar linux,pci-domain = <1>; 2161ec142c44SVidya Sagar 2162ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX0_C1_CORE>; 2163ec142c44SVidya Sagar clock-names = "core"; 2164ec142c44SVidya Sagar 2165ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX0_CORE_1_APB>, 2166ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX0_CORE_1>; 2167ec142c44SVidya Sagar reset-names = "apb", "core"; 2168ec142c44SVidya Sagar 2169ec142c44SVidya Sagar interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2170ec142c44SVidya Sagar <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2171ec142c44SVidya Sagar interrupt-names = "intr", "msi"; 2172ec142c44SVidya Sagar 2173ec142c44SVidya Sagar #interrupt-cells = <1>; 2174ec142c44SVidya Sagar interrupt-map-mask = <0 0 0 0>; 2175ec142c44SVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 2176ec142c44SVidya Sagar 2177ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 1>; 2178ec142c44SVidya Sagar 2179ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2180ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2181ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2182ec142c44SVidya Sagar 2183ec142c44SVidya Sagar bus-range = <0x0 0xff>; 2184ec142c44SVidya Sagar 2185ec142c44SVidya Sagar ranges = <0x43000000 0x20 0x80000000 0x20 0x80000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ 2186ec142c44SVidya Sagar <0x02000000 0x0 0x40000000 0x20 0xa8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2187ec142c44SVidya Sagar <0x01000000 0x0 0x30100000 0x00 0x30100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2188ec142c44SVidya Sagar 2189ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE1R &emc>, 2190ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE1W &emc>; 2191ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2192ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE1 0x1000>; 2193ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2194ec142c44SVidya Sagar dma-coherent; 2195ec142c44SVidya Sagar 2196ec142c44SVidya Sagar status = "disabled"; 2197ec142c44SVidya Sagar }; 2198ec142c44SVidya Sagar 2199ec142c44SVidya Sagar pcie@14120000 { 2200ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie"; 2201ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>; 2202ec142c44SVidya Sagar reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */ 2203ec142c44SVidya Sagar <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */ 2204ec142c44SVidya Sagar <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2205ec142c44SVidya Sagar <0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2206ec142c44SVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 2207ec142c44SVidya Sagar 2208ec142c44SVidya Sagar #address-cells = <3>; 2209ec142c44SVidya Sagar #size-cells = <2>; 2210ec142c44SVidya Sagar device_type = "pci"; 2211ec142c44SVidya Sagar num-lanes = <1>; 2212ec142c44SVidya Sagar num-viewport = <8>; 2213ec142c44SVidya Sagar linux,pci-domain = <2>; 2214ec142c44SVidya Sagar 2215ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX0_C2_CORE>; 2216ec142c44SVidya Sagar clock-names = "core"; 2217ec142c44SVidya Sagar 2218ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX0_CORE_2_APB>, 2219ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX0_CORE_2>; 2220ec142c44SVidya Sagar reset-names = "apb", "core"; 2221ec142c44SVidya Sagar 2222ec142c44SVidya Sagar interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2223ec142c44SVidya Sagar <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2224ec142c44SVidya Sagar interrupt-names = "intr", "msi"; 2225ec142c44SVidya Sagar 2226ec142c44SVidya Sagar #interrupt-cells = <1>; 2227ec142c44SVidya Sagar interrupt-map-mask = <0 0 0 0>; 2228ec142c44SVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 2229ec142c44SVidya Sagar 2230ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 2>; 2231ec142c44SVidya Sagar 2232ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2233ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2234ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2235ec142c44SVidya Sagar 2236ec142c44SVidya Sagar bus-range = <0x0 0xff>; 2237ec142c44SVidya Sagar 2238ec142c44SVidya Sagar ranges = <0x43000000 0x20 0xc0000000 0x20 0xc0000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ 2239ec142c44SVidya Sagar <0x02000000 0x0 0x40000000 0x20 0xe8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2240ec142c44SVidya Sagar <0x01000000 0x0 0x32100000 0x00 0x32100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2241ec142c44SVidya Sagar 2242ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE2AR &emc>, 2243ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE2AW &emc>; 2244ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2245ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE2 0x1000>; 2246ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2247ec142c44SVidya Sagar dma-coherent; 2248ec142c44SVidya Sagar 2249ec142c44SVidya Sagar status = "disabled"; 2250ec142c44SVidya Sagar }; 2251ec142c44SVidya Sagar 2252ec142c44SVidya Sagar pcie@14140000 { 2253ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie"; 2254ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>; 2255ec142c44SVidya Sagar reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */ 2256ec142c44SVidya Sagar <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */ 2257ec142c44SVidya Sagar <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2258ec142c44SVidya Sagar <0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2259ec142c44SVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 2260ec142c44SVidya Sagar 2261ec142c44SVidya Sagar #address-cells = <3>; 2262ec142c44SVidya Sagar #size-cells = <2>; 2263ec142c44SVidya Sagar device_type = "pci"; 2264ec142c44SVidya Sagar num-lanes = <1>; 2265ec142c44SVidya Sagar num-viewport = <8>; 2266ec142c44SVidya Sagar linux,pci-domain = <3>; 2267ec142c44SVidya Sagar 2268ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX0_C3_CORE>; 2269ec142c44SVidya Sagar clock-names = "core"; 2270ec142c44SVidya Sagar 2271ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX0_CORE_3_APB>, 2272ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX0_CORE_3>; 2273ec142c44SVidya Sagar reset-names = "apb", "core"; 2274ec142c44SVidya Sagar 2275ec142c44SVidya Sagar interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2276ec142c44SVidya Sagar <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2277ec142c44SVidya Sagar interrupt-names = "intr", "msi"; 2278ec142c44SVidya Sagar 2279ec142c44SVidya Sagar #interrupt-cells = <1>; 2280ec142c44SVidya Sagar interrupt-map-mask = <0 0 0 0>; 2281ec142c44SVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 2282ec142c44SVidya Sagar 2283ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 3>; 2284ec142c44SVidya Sagar 2285ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2286ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2287ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2288ec142c44SVidya Sagar 2289ec142c44SVidya Sagar bus-range = <0x0 0xff>; 2290ec142c44SVidya Sagar 2291ec142c44SVidya Sagar ranges = <0x43000000 0x21 0x00000000 0x21 0x00000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ 2292ec142c44SVidya Sagar <0x02000000 0x0 0x40000000 0x21 0xe8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2293ec142c44SVidya Sagar <0x01000000 0x0 0x34100000 0x00 0x34100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2294ec142c44SVidya Sagar 2295ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE3R &emc>, 2296ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE3W &emc>; 2297ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2298ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE3 0x1000>; 2299ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2300ec142c44SVidya Sagar dma-coherent; 2301ec142c44SVidya Sagar 2302ec142c44SVidya Sagar status = "disabled"; 2303ec142c44SVidya Sagar }; 2304ec142c44SVidya Sagar 2305ec142c44SVidya Sagar pcie@14160000 { 2306ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie"; 2307ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BB>; 2308ec142c44SVidya Sagar reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2309ec142c44SVidya Sagar <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ 2310ec142c44SVidya Sagar <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2311ec142c44SVidya Sagar <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2312ec142c44SVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 2313ec142c44SVidya Sagar 2314ec142c44SVidya Sagar #address-cells = <3>; 2315ec142c44SVidya Sagar #size-cells = <2>; 2316ec142c44SVidya Sagar device_type = "pci"; 2317ec142c44SVidya Sagar num-lanes = <4>; 2318ec142c44SVidya Sagar num-viewport = <8>; 2319ec142c44SVidya Sagar linux,pci-domain = <4>; 2320ec142c44SVidya Sagar 2321ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX0_C4_CORE>; 2322ec142c44SVidya Sagar clock-names = "core"; 2323ec142c44SVidya Sagar 2324ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX0_CORE_4_APB>, 2325ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX0_CORE_4>; 2326ec142c44SVidya Sagar reset-names = "apb", "core"; 2327ec142c44SVidya Sagar 2328ec142c44SVidya Sagar interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2329ec142c44SVidya Sagar <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2330ec142c44SVidya Sagar interrupt-names = "intr", "msi"; 2331ec142c44SVidya Sagar 2332ec142c44SVidya Sagar #interrupt-cells = <1>; 2333ec142c44SVidya Sagar interrupt-map-mask = <0 0 0 0>; 2334ec142c44SVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 2335ec142c44SVidya Sagar 2336ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 4>; 2337ec142c44SVidya Sagar 2338ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2339ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2340ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2341ec142c44SVidya Sagar 2342ec142c44SVidya Sagar bus-range = <0x0 0xff>; 2343ec142c44SVidya Sagar 2344ec142c44SVidya Sagar ranges = <0x43000000 0x21 0x40000000 0x21 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2345ec142c44SVidya Sagar <0x02000000 0x0 0x40000000 0x24 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2346ec142c44SVidya Sagar <0x01000000 0x0 0x36100000 0x00 0x36100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2347ec142c44SVidya Sagar 2348ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE4R &emc>, 2349ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE4W &emc>; 2350ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2351ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE4 0x1000>; 2352ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2353ec142c44SVidya Sagar dma-coherent; 2354ec142c44SVidya Sagar 2355ec142c44SVidya Sagar status = "disabled"; 2356ec142c44SVidya Sagar }; 2357ec142c44SVidya Sagar 2358ec142c44SVidya Sagar pcie@14180000 { 2359ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie"; 2360ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BA>; 2361ec142c44SVidya Sagar reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2362ec142c44SVidya Sagar <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ 2363ec142c44SVidya Sagar <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2364ec142c44SVidya Sagar <0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2365ec142c44SVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 2366ec142c44SVidya Sagar 2367ec142c44SVidya Sagar #address-cells = <3>; 2368ec142c44SVidya Sagar #size-cells = <2>; 2369ec142c44SVidya Sagar device_type = "pci"; 2370ec142c44SVidya Sagar num-lanes = <4>; 2371ec142c44SVidya Sagar num-viewport = <8>; 2372ec142c44SVidya Sagar linux,pci-domain = <0>; 2373ec142c44SVidya Sagar 2374ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX0_C0_CORE>; 2375ec142c44SVidya Sagar clock-names = "core"; 2376ec142c44SVidya Sagar 2377ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX0_CORE_0_APB>, 2378ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX0_CORE_0>; 2379ec142c44SVidya Sagar reset-names = "apb", "core"; 2380ec142c44SVidya Sagar 2381ec142c44SVidya Sagar interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2382ec142c44SVidya Sagar <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2383ec142c44SVidya Sagar interrupt-names = "intr", "msi"; 2384ec142c44SVidya Sagar 2385ec142c44SVidya Sagar #interrupt-cells = <1>; 2386ec142c44SVidya Sagar interrupt-map-mask = <0 0 0 0>; 2387ec142c44SVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 2388ec142c44SVidya Sagar 2389ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 0>; 2390ec142c44SVidya Sagar 2391ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2392ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2393ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2394ec142c44SVidya Sagar 2395ec142c44SVidya Sagar bus-range = <0x0 0xff>; 2396ec142c44SVidya Sagar 2397ec142c44SVidya Sagar ranges = <0x43000000 0x24 0x40000000 0x24 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2398ec142c44SVidya Sagar <0x02000000 0x0 0x40000000 0x27 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2399ec142c44SVidya Sagar <0x01000000 0x0 0x38100000 0x00 0x38100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2400ec142c44SVidya Sagar 2401ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE0R &emc>, 2402ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE0W &emc>; 2403ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2404ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE0 0x1000>; 2405ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2406ec142c44SVidya Sagar dma-coherent; 2407ec142c44SVidya Sagar 2408ec142c44SVidya Sagar status = "disabled"; 2409ec142c44SVidya Sagar }; 2410ec142c44SVidya Sagar 2411ec142c44SVidya Sagar pcie@141a0000 { 2412ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie"; 2413ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>; 2414ec142c44SVidya Sagar reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2415ec142c44SVidya Sagar <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */ 2416ec142c44SVidya Sagar <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2417ec142c44SVidya Sagar <0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2418ec142c44SVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 2419ec142c44SVidya Sagar 2420ec142c44SVidya Sagar #address-cells = <3>; 2421ec142c44SVidya Sagar #size-cells = <2>; 2422ec142c44SVidya Sagar device_type = "pci"; 2423ec142c44SVidya Sagar num-lanes = <8>; 2424ec142c44SVidya Sagar num-viewport = <8>; 2425ec142c44SVidya Sagar linux,pci-domain = <5>; 2426ec142c44SVidya Sagar 2427ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>; 2428ec142c44SVidya Sagar clock-names = "core"; 2429ec142c44SVidya Sagar 2430ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>, 2431ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX1_CORE_5>; 2432ec142c44SVidya Sagar reset-names = "apb", "core"; 2433ec142c44SVidya Sagar 2434ec142c44SVidya Sagar interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2435ec142c44SVidya Sagar <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2436ec142c44SVidya Sagar interrupt-names = "intr", "msi"; 2437ec142c44SVidya Sagar 2438ec142c44SVidya Sagar #interrupt-cells = <1>; 2439ec142c44SVidya Sagar interrupt-map-mask = <0 0 0 0>; 2440ec142c44SVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 2441ec142c44SVidya Sagar 2442ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 5>; 2443ec142c44SVidya Sagar 2444ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2445ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2446ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2447ec142c44SVidya Sagar 2448ec142c44SVidya Sagar bus-range = <0x0 0xff>; 2449ec142c44SVidya Sagar 245024840065SVidya Sagar ranges = <0x43000000 0x28 0x00000000 0x28 0x00000000 0x3 0x28000000>, /* prefetchable memory (12928 MB) */ 2451ec142c44SVidya Sagar <0x02000000 0x0 0x40000000 0x2b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2452ec142c44SVidya Sagar <0x01000000 0x0 0x3a100000 0x00 0x3a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2453ec142c44SVidya Sagar 2454ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE5R &emc>, 2455ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE5W &emc>; 2456ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2457ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>; 2458ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2459ec142c44SVidya Sagar dma-coherent; 2460ec142c44SVidya Sagar 2461ec142c44SVidya Sagar status = "disabled"; 2462ec142c44SVidya Sagar }; 2463ec142c44SVidya Sagar 2464ec142c44SVidya Sagar pcie@141c0000 { 2465ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie"; 2466ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4A>; 2467ec142c44SVidya Sagar reg = <0x00 0x141c0000 0x0 0x00020000>, /* appl registers (128K) */ 2468ec142c44SVidya Sagar <0x00 0x3c000000 0x0 0x00040000>, /* configuration space (256K) */ 2469ec142c44SVidya Sagar <0x00 0x3c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2470ec142c44SVidya Sagar <0x00 0x3c080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2471ec142c44SVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 2472ec142c44SVidya Sagar 2473ec142c44SVidya Sagar #address-cells = <3>; 2474ec142c44SVidya Sagar #size-cells = <2>; 2475ec142c44SVidya Sagar device_type = "pci"; 2476ec142c44SVidya Sagar num-lanes = <4>; 2477ec142c44SVidya Sagar num-viewport = <8>; 2478ec142c44SVidya Sagar linux,pci-domain = <6>; 2479ec142c44SVidya Sagar 2480ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX1_C6_CORE>; 2481ec142c44SVidya Sagar clock-names = "core"; 2482ec142c44SVidya Sagar 2483ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX1_CORE_6_APB>, 2484ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX1_CORE_6>; 2485ec142c44SVidya Sagar reset-names = "apb", "core"; 2486ec142c44SVidya Sagar 2487ec142c44SVidya Sagar interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2488ec142c44SVidya Sagar <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2489ec142c44SVidya Sagar interrupt-names = "intr", "msi"; 2490ec142c44SVidya Sagar 2491ec142c44SVidya Sagar #interrupt-cells = <1>; 2492ec142c44SVidya Sagar interrupt-map-mask = <0 0 0 0>; 2493ec142c44SVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 2494ec142c44SVidya Sagar 2495ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 6>; 2496ec142c44SVidya Sagar 2497ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2498ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2499ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2500ec142c44SVidya Sagar 2501ec142c44SVidya Sagar bus-range = <0x0 0xff>; 2502ec142c44SVidya Sagar 2503ec142c44SVidya Sagar ranges = <0x43000000 0x2b 0x40000000 0x2b 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2504ec142c44SVidya Sagar <0x02000000 0x0 0x40000000 0x2e 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2505ec142c44SVidya Sagar <0x01000000 0x0 0x3c100000 0x00 0x3c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2506ec142c44SVidya Sagar 2507ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE6AR &emc>, 2508ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE6AW &emc>; 2509ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2510ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>; 2511ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2512ec142c44SVidya Sagar dma-coherent; 2513ec142c44SVidya Sagar 2514ec142c44SVidya Sagar status = "disabled"; 2515ec142c44SVidya Sagar }; 2516ec142c44SVidya Sagar 2517ec142c44SVidya Sagar pcie@141e0000 { 2518ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie"; 2519ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8B>; 2520ec142c44SVidya Sagar reg = <0x00 0x141e0000 0x0 0x00020000>, /* appl registers (128K) */ 2521ec142c44SVidya Sagar <0x00 0x3e000000 0x0 0x00040000>, /* configuration space (256K) */ 2522ec142c44SVidya Sagar <0x00 0x3e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2523ec142c44SVidya Sagar <0x00 0x3e080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2524ec142c44SVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 2525ec142c44SVidya Sagar 2526ec142c44SVidya Sagar #address-cells = <3>; 2527ec142c44SVidya Sagar #size-cells = <2>; 2528ec142c44SVidya Sagar device_type = "pci"; 2529ec142c44SVidya Sagar num-lanes = <8>; 2530ec142c44SVidya Sagar num-viewport = <8>; 2531ec142c44SVidya Sagar linux,pci-domain = <7>; 2532ec142c44SVidya Sagar 2533ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX2_C7_CORE>; 2534ec142c44SVidya Sagar clock-names = "core"; 2535ec142c44SVidya Sagar 2536ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX2_CORE_7_APB>, 2537ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX2_CORE_7>; 2538ec142c44SVidya Sagar reset-names = "apb", "core"; 2539ec142c44SVidya Sagar 2540ec142c44SVidya Sagar interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2541ec142c44SVidya Sagar <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2542ec142c44SVidya Sagar interrupt-names = "intr", "msi"; 2543ec142c44SVidya Sagar 2544ec142c44SVidya Sagar #interrupt-cells = <1>; 2545ec142c44SVidya Sagar interrupt-map-mask = <0 0 0 0>; 2546ec142c44SVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 2547ec142c44SVidya Sagar 2548ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 7>; 2549ec142c44SVidya Sagar 2550ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2551ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2552ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2553ec142c44SVidya Sagar 2554ec142c44SVidya Sagar bus-range = <0x0 0xff>; 2555ec142c44SVidya Sagar 255624840065SVidya Sagar ranges = <0x43000000 0x30 0x00000000 0x30 0x00000000 0x2 0x28000000>, /* prefetchable memory (8832 MB) */ 2557ec142c44SVidya Sagar <0x02000000 0x0 0x40000000 0x32 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2558ec142c44SVidya Sagar <0x01000000 0x0 0x3e100000 0x00 0x3e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2559ec142c44SVidya Sagar 2560ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE7AR &emc>, 2561ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE7AW &emc>; 2562ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2563ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>; 2564ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2565ec142c44SVidya Sagar dma-coherent; 2566ec142c44SVidya Sagar 2567ec142c44SVidya Sagar status = "disabled"; 2568ec142c44SVidya Sagar }; 2569ec142c44SVidya Sagar 2570ec142c44SVidya Sagar pcie-ep@141a0000 { 2571ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie-ep"; 2572ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>; 2573ec142c44SVidya Sagar reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2574ec142c44SVidya Sagar <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2575ec142c44SVidya Sagar <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2576ec142c44SVidya Sagar <0x27 0x40000000 0x4 0x00000000>; /* Address Space (16G) */ 2577ec142c44SVidya Sagar reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2578ec142c44SVidya Sagar 2579ec142c44SVidya Sagar num-lanes = <8>; 2580ec142c44SVidya Sagar 2581ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>; 2582ec142c44SVidya Sagar clock-names = "core"; 2583ec142c44SVidya Sagar 2584ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>, 2585ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX1_CORE_5>; 2586ec142c44SVidya Sagar reset-names = "apb", "core"; 2587ec142c44SVidya Sagar 2588ec142c44SVidya Sagar interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2589ec142c44SVidya Sagar interrupt-names = "intr"; 2590ec142c44SVidya Sagar 2591ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 5>; 2592ec142c44SVidya Sagar 2593ec142c44SVidya Sagar nvidia,enable-ext-refclk; 2594ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2595ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2596ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2597ec142c44SVidya Sagar 2598ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE5R &emc>, 2599ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE5W &emc>; 2600ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2601ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>; 2602ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2603ec142c44SVidya Sagar dma-coherent; 2604ec142c44SVidya Sagar 2605ec142c44SVidya Sagar status = "disabled"; 2606ec142c44SVidya Sagar }; 2607ec142c44SVidya Sagar 2608ec142c44SVidya Sagar pcie-ep@141c0000{ 2609ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie-ep"; 2610ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4A>; 2611ec142c44SVidya Sagar reg = <0x00 0x141c0000 0x0 0x00020000>, /* appl registers (128K) */ 2612ec142c44SVidya Sagar <0x00 0x3c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2613ec142c44SVidya Sagar <0x00 0x3c080000 0x0 0x00040000>, /* DBI space (256K) */ 2614ec142c44SVidya Sagar <0x2b 0x40000000 0x3 0x00000000>; /* Address Space (12G) */ 2615ec142c44SVidya Sagar reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2616ec142c44SVidya Sagar 2617ec142c44SVidya Sagar num-lanes = <4>; 2618ec142c44SVidya Sagar 2619ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX1_C6_CORE>; 2620ec142c44SVidya Sagar clock-names = "core"; 2621ec142c44SVidya Sagar 2622ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX1_CORE_6_APB>, 2623ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX1_CORE_6>; 2624ec142c44SVidya Sagar reset-names = "apb", "core"; 2625ec142c44SVidya Sagar 2626ec142c44SVidya Sagar interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2627ec142c44SVidya Sagar interrupt-names = "intr"; 2628ec142c44SVidya Sagar 2629ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 6>; 2630ec142c44SVidya Sagar 2631ec142c44SVidya Sagar nvidia,enable-ext-refclk; 2632ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2633ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2634ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2635ec142c44SVidya Sagar 2636ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE6AR &emc>, 2637ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE6AW &emc>; 2638ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2639ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>; 2640ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2641ec142c44SVidya Sagar dma-coherent; 2642ec142c44SVidya Sagar 2643ec142c44SVidya Sagar status = "disabled"; 2644ec142c44SVidya Sagar }; 2645ec142c44SVidya Sagar 2646ec142c44SVidya Sagar pcie-ep@141e0000{ 2647ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie-ep"; 2648ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8B>; 2649ec142c44SVidya Sagar reg = <0x00 0x141e0000 0x0 0x00020000>, /* appl registers (128K) */ 2650ec142c44SVidya Sagar <0x00 0x3e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2651ec142c44SVidya Sagar <0x00 0x3e080000 0x0 0x00040000>, /* DBI space (256K) */ 2652ec142c44SVidya Sagar <0x2e 0x40000000 0x4 0x00000000>; /* Address Space (16G) */ 2653ec142c44SVidya Sagar reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2654ec142c44SVidya Sagar 2655ec142c44SVidya Sagar num-lanes = <8>; 2656ec142c44SVidya Sagar 2657ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX2_C7_CORE>; 2658ec142c44SVidya Sagar clock-names = "core"; 2659ec142c44SVidya Sagar 2660ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX2_CORE_7_APB>, 2661ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX2_CORE_7>; 2662ec142c44SVidya Sagar reset-names = "apb", "core"; 2663ec142c44SVidya Sagar 2664ec142c44SVidya Sagar interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2665ec142c44SVidya Sagar interrupt-names = "intr"; 2666ec142c44SVidya Sagar 2667ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 7>; 2668ec142c44SVidya Sagar 2669ec142c44SVidya Sagar nvidia,enable-ext-refclk; 2670ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2671ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2672ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2673ec142c44SVidya Sagar 2674ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE7AR &emc>, 2675ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE7AW &emc>; 2676ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2677ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>; 2678ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2679ec142c44SVidya Sagar dma-coherent; 2680ec142c44SVidya Sagar 2681ec142c44SVidya Sagar status = "disabled"; 2682ec142c44SVidya Sagar }; 2683ec142c44SVidya Sagar 2684ec142c44SVidya Sagar pcie-ep@140e0000{ 2685ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie-ep"; 2686ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CC>; 2687ec142c44SVidya Sagar reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K) */ 2688ec142c44SVidya Sagar <0x00 0x2e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2689ec142c44SVidya Sagar <0x00 0x2e080000 0x0 0x00040000>, /* DBI space (256K) */ 2690ec142c44SVidya Sagar <0x38 0x40000000 0x3 0x00000000>; /* Address Space (12G) */ 2691ec142c44SVidya Sagar reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2692ec142c44SVidya Sagar 2693ec142c44SVidya Sagar num-lanes = <4>; 2694ec142c44SVidya Sagar 2695ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX2_C10_CORE>; 2696ec142c44SVidya Sagar clock-names = "core"; 2697ec142c44SVidya Sagar 2698ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX2_CORE_10_APB>, 2699ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX2_CORE_10>; 2700ec142c44SVidya Sagar reset-names = "apb", "core"; 2701ec142c44SVidya Sagar 2702ec142c44SVidya Sagar interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2703ec142c44SVidya Sagar interrupt-names = "intr"; 2704ec142c44SVidya Sagar 2705ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 10>; 2706ec142c44SVidya Sagar 2707ec142c44SVidya Sagar nvidia,enable-ext-refclk; 2708ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2709ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2710ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2711ec142c44SVidya Sagar 2712ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE10AR &emc>, 2713ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE10AW &emc>; 2714ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2715ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>; 2716ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2717ec142c44SVidya Sagar dma-coherent; 2718ec142c44SVidya Sagar 2719ec142c44SVidya Sagar status = "disabled"; 2720ec142c44SVidya Sagar }; 2721ec142c44SVidya Sagar 27227fa30752SThierry Reding sram@40000000 { 272363944891SThierry Reding compatible = "nvidia,tegra234-sysram", "mmio-sram"; 272498094be1SMikko Perttunen reg = <0x0 0x40000000 0x0 0x80000>; 272563944891SThierry Reding #address-cells = <1>; 272663944891SThierry Reding #size-cells = <1>; 272798094be1SMikko Perttunen ranges = <0x0 0x0 0x40000000 0x80000>; 272861192a9dSMikko Perttunen no-memory-wc; 272963944891SThierry Reding 273098094be1SMikko Perttunen cpu_bpmp_tx: sram@70000 { 273198094be1SMikko Perttunen reg = <0x70000 0x1000>; 273263944891SThierry Reding label = "cpu-bpmp-tx"; 273363944891SThierry Reding pool; 273463944891SThierry Reding }; 273563944891SThierry Reding 273698094be1SMikko Perttunen cpu_bpmp_rx: sram@71000 { 273798094be1SMikko Perttunen reg = <0x71000 0x1000>; 273863944891SThierry Reding label = "cpu-bpmp-rx"; 273963944891SThierry Reding pool; 274063944891SThierry Reding }; 274163944891SThierry Reding }; 274263944891SThierry Reding 274363944891SThierry Reding bpmp: bpmp { 274463944891SThierry Reding compatible = "nvidia,tegra234-bpmp", "nvidia,tegra186-bpmp"; 274563944891SThierry Reding mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 274663944891SThierry Reding TEGRA_HSP_DB_MASTER_BPMP>; 27477fa30752SThierry Reding shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; 274863944891SThierry Reding #clock-cells = <1>; 274963944891SThierry Reding #reset-cells = <1>; 275063944891SThierry Reding #power-domain-cells = <1>; 27516de481e5SThierry Reding interconnects = <&mc TEGRA234_MEMORY_CLIENT_BPMPR &emc>, 27526de481e5SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_BPMPW &emc>, 27536de481e5SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAR &emc>, 27546de481e5SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAW &emc>; 27556de481e5SThierry Reding interconnect-names = "read", "write", "dma-mem", "dma-write"; 27565710e16aSThierry Reding iommus = <&smmu_niso1 TEGRA234_SID_BPMP>; 275763944891SThierry Reding 275863944891SThierry Reding bpmp_i2c: i2c { 275963944891SThierry Reding compatible = "nvidia,tegra186-bpmp-i2c"; 276063944891SThierry Reding nvidia,bpmp-bus-id = <5>; 276163944891SThierry Reding #address-cells = <1>; 276263944891SThierry Reding #size-cells = <0>; 276363944891SThierry Reding }; 276463944891SThierry Reding }; 276563944891SThierry Reding 276663944891SThierry Reding cpus { 276763944891SThierry Reding #address-cells = <1>; 276863944891SThierry Reding #size-cells = <0>; 276963944891SThierry Reding 2770a12cf5c3SThierry Reding cpu0_0: cpu@0 { 2771a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 277263944891SThierry Reding device_type = "cpu"; 2773a12cf5c3SThierry Reding reg = <0x00000>; 277463944891SThierry Reding 277563944891SThierry Reding enable-method = "psci"; 2776a12cf5c3SThierry Reding 2777a12cf5c3SThierry Reding i-cache-size = <65536>; 2778a12cf5c3SThierry Reding i-cache-line-size = <64>; 2779a12cf5c3SThierry Reding i-cache-sets = <256>; 2780a12cf5c3SThierry Reding d-cache-size = <65536>; 2781a12cf5c3SThierry Reding d-cache-line-size = <64>; 2782a12cf5c3SThierry Reding d-cache-sets = <256>; 2783a12cf5c3SThierry Reding next-level-cache = <&l2c0_0>; 278463944891SThierry Reding }; 2785a12cf5c3SThierry Reding 2786a12cf5c3SThierry Reding cpu0_1: cpu@100 { 2787a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 2788a12cf5c3SThierry Reding device_type = "cpu"; 2789a12cf5c3SThierry Reding reg = <0x00100>; 2790a12cf5c3SThierry Reding 2791a12cf5c3SThierry Reding enable-method = "psci"; 2792a12cf5c3SThierry Reding 2793a12cf5c3SThierry Reding i-cache-size = <65536>; 2794a12cf5c3SThierry Reding i-cache-line-size = <64>; 2795a12cf5c3SThierry Reding i-cache-sets = <256>; 2796a12cf5c3SThierry Reding d-cache-size = <65536>; 2797a12cf5c3SThierry Reding d-cache-line-size = <64>; 2798a12cf5c3SThierry Reding d-cache-sets = <256>; 2799a12cf5c3SThierry Reding next-level-cache = <&l2c0_1>; 2800a12cf5c3SThierry Reding }; 2801a12cf5c3SThierry Reding 2802a12cf5c3SThierry Reding cpu0_2: cpu@200 { 2803a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 2804a12cf5c3SThierry Reding device_type = "cpu"; 2805a12cf5c3SThierry Reding reg = <0x00200>; 2806a12cf5c3SThierry Reding 2807a12cf5c3SThierry Reding enable-method = "psci"; 2808a12cf5c3SThierry Reding 2809a12cf5c3SThierry Reding i-cache-size = <65536>; 2810a12cf5c3SThierry Reding i-cache-line-size = <64>; 2811a12cf5c3SThierry Reding i-cache-sets = <256>; 2812a12cf5c3SThierry Reding d-cache-size = <65536>; 2813a12cf5c3SThierry Reding d-cache-line-size = <64>; 2814a12cf5c3SThierry Reding d-cache-sets = <256>; 2815a12cf5c3SThierry Reding next-level-cache = <&l2c0_2>; 2816a12cf5c3SThierry Reding }; 2817a12cf5c3SThierry Reding 2818a12cf5c3SThierry Reding cpu0_3: cpu@300 { 2819a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 2820a12cf5c3SThierry Reding device_type = "cpu"; 2821a12cf5c3SThierry Reding reg = <0x00300>; 2822a12cf5c3SThierry Reding 2823a12cf5c3SThierry Reding enable-method = "psci"; 2824a12cf5c3SThierry Reding 2825a12cf5c3SThierry Reding i-cache-size = <65536>; 2826a12cf5c3SThierry Reding i-cache-line-size = <64>; 2827a12cf5c3SThierry Reding i-cache-sets = <256>; 2828a12cf5c3SThierry Reding d-cache-size = <65536>; 2829a12cf5c3SThierry Reding d-cache-line-size = <64>; 2830a12cf5c3SThierry Reding d-cache-sets = <256>; 2831a12cf5c3SThierry Reding next-level-cache = <&l2c0_3>; 2832a12cf5c3SThierry Reding }; 2833a12cf5c3SThierry Reding 2834a12cf5c3SThierry Reding cpu1_0: cpu@10000 { 2835a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 2836a12cf5c3SThierry Reding device_type = "cpu"; 2837a12cf5c3SThierry Reding reg = <0x10000>; 2838a12cf5c3SThierry Reding 2839a12cf5c3SThierry Reding enable-method = "psci"; 2840a12cf5c3SThierry Reding 2841a12cf5c3SThierry Reding i-cache-size = <65536>; 2842a12cf5c3SThierry Reding i-cache-line-size = <64>; 2843a12cf5c3SThierry Reding i-cache-sets = <256>; 2844a12cf5c3SThierry Reding d-cache-size = <65536>; 2845a12cf5c3SThierry Reding d-cache-line-size = <64>; 2846a12cf5c3SThierry Reding d-cache-sets = <256>; 2847a12cf5c3SThierry Reding next-level-cache = <&l2c1_0>; 2848a12cf5c3SThierry Reding }; 2849a12cf5c3SThierry Reding 2850a12cf5c3SThierry Reding cpu1_1: cpu@10100 { 2851a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 2852a12cf5c3SThierry Reding device_type = "cpu"; 2853a12cf5c3SThierry Reding reg = <0x10100>; 2854a12cf5c3SThierry Reding 2855a12cf5c3SThierry Reding enable-method = "psci"; 2856a12cf5c3SThierry Reding 2857a12cf5c3SThierry Reding i-cache-size = <65536>; 2858a12cf5c3SThierry Reding i-cache-line-size = <64>; 2859a12cf5c3SThierry Reding i-cache-sets = <256>; 2860a12cf5c3SThierry Reding d-cache-size = <65536>; 2861a12cf5c3SThierry Reding d-cache-line-size = <64>; 2862a12cf5c3SThierry Reding d-cache-sets = <256>; 2863a12cf5c3SThierry Reding next-level-cache = <&l2c1_1>; 2864a12cf5c3SThierry Reding }; 2865a12cf5c3SThierry Reding 2866a12cf5c3SThierry Reding cpu1_2: cpu@10200 { 2867a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 2868a12cf5c3SThierry Reding device_type = "cpu"; 2869a12cf5c3SThierry Reding reg = <0x10200>; 2870a12cf5c3SThierry Reding 2871a12cf5c3SThierry Reding enable-method = "psci"; 2872a12cf5c3SThierry Reding 2873a12cf5c3SThierry Reding i-cache-size = <65536>; 2874a12cf5c3SThierry Reding i-cache-line-size = <64>; 2875a12cf5c3SThierry Reding i-cache-sets = <256>; 2876a12cf5c3SThierry Reding d-cache-size = <65536>; 2877a12cf5c3SThierry Reding d-cache-line-size = <64>; 2878a12cf5c3SThierry Reding d-cache-sets = <256>; 2879a12cf5c3SThierry Reding next-level-cache = <&l2c1_2>; 2880a12cf5c3SThierry Reding }; 2881a12cf5c3SThierry Reding 2882a12cf5c3SThierry Reding cpu1_3: cpu@10300 { 2883a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 2884a12cf5c3SThierry Reding device_type = "cpu"; 2885a12cf5c3SThierry Reding reg = <0x10300>; 2886a12cf5c3SThierry Reding 2887a12cf5c3SThierry Reding enable-method = "psci"; 2888a12cf5c3SThierry Reding 2889a12cf5c3SThierry Reding i-cache-size = <65536>; 2890a12cf5c3SThierry Reding i-cache-line-size = <64>; 2891a12cf5c3SThierry Reding i-cache-sets = <256>; 2892a12cf5c3SThierry Reding d-cache-size = <65536>; 2893a12cf5c3SThierry Reding d-cache-line-size = <64>; 2894a12cf5c3SThierry Reding d-cache-sets = <256>; 2895a12cf5c3SThierry Reding next-level-cache = <&l2c1_3>; 2896a12cf5c3SThierry Reding }; 2897a12cf5c3SThierry Reding 2898a12cf5c3SThierry Reding cpu2_0: cpu@20000 { 2899a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 2900a12cf5c3SThierry Reding device_type = "cpu"; 2901a12cf5c3SThierry Reding reg = <0x20000>; 2902a12cf5c3SThierry Reding 2903a12cf5c3SThierry Reding enable-method = "psci"; 2904a12cf5c3SThierry Reding 2905a12cf5c3SThierry Reding i-cache-size = <65536>; 2906a12cf5c3SThierry Reding i-cache-line-size = <64>; 2907a12cf5c3SThierry Reding i-cache-sets = <256>; 2908a12cf5c3SThierry Reding d-cache-size = <65536>; 2909a12cf5c3SThierry Reding d-cache-line-size = <64>; 2910a12cf5c3SThierry Reding d-cache-sets = <256>; 2911a12cf5c3SThierry Reding next-level-cache = <&l2c2_0>; 2912a12cf5c3SThierry Reding }; 2913a12cf5c3SThierry Reding 2914a12cf5c3SThierry Reding cpu2_1: cpu@20100 { 2915a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 2916a12cf5c3SThierry Reding device_type = "cpu"; 2917a12cf5c3SThierry Reding reg = <0x20100>; 2918a12cf5c3SThierry Reding 2919a12cf5c3SThierry Reding enable-method = "psci"; 2920a12cf5c3SThierry Reding 2921a12cf5c3SThierry Reding i-cache-size = <65536>; 2922a12cf5c3SThierry Reding i-cache-line-size = <64>; 2923a12cf5c3SThierry Reding i-cache-sets = <256>; 2924a12cf5c3SThierry Reding d-cache-size = <65536>; 2925a12cf5c3SThierry Reding d-cache-line-size = <64>; 2926a12cf5c3SThierry Reding d-cache-sets = <256>; 2927a12cf5c3SThierry Reding next-level-cache = <&l2c2_1>; 2928a12cf5c3SThierry Reding }; 2929a12cf5c3SThierry Reding 2930a12cf5c3SThierry Reding cpu2_2: cpu@20200 { 2931a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 2932a12cf5c3SThierry Reding device_type = "cpu"; 2933a12cf5c3SThierry Reding reg = <0x20200>; 2934a12cf5c3SThierry Reding 2935a12cf5c3SThierry Reding enable-method = "psci"; 2936a12cf5c3SThierry Reding 2937a12cf5c3SThierry Reding i-cache-size = <65536>; 2938a12cf5c3SThierry Reding i-cache-line-size = <64>; 2939a12cf5c3SThierry Reding i-cache-sets = <256>; 2940a12cf5c3SThierry Reding d-cache-size = <65536>; 2941a12cf5c3SThierry Reding d-cache-line-size = <64>; 2942a12cf5c3SThierry Reding d-cache-sets = <256>; 2943a12cf5c3SThierry Reding next-level-cache = <&l2c2_2>; 2944a12cf5c3SThierry Reding }; 2945a12cf5c3SThierry Reding 2946a12cf5c3SThierry Reding cpu2_3: cpu@20300 { 2947a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 2948a12cf5c3SThierry Reding device_type = "cpu"; 2949a12cf5c3SThierry Reding reg = <0x20300>; 2950a12cf5c3SThierry Reding 2951a12cf5c3SThierry Reding enable-method = "psci"; 2952a12cf5c3SThierry Reding 2953a12cf5c3SThierry Reding i-cache-size = <65536>; 2954a12cf5c3SThierry Reding i-cache-line-size = <64>; 2955a12cf5c3SThierry Reding i-cache-sets = <256>; 2956a12cf5c3SThierry Reding d-cache-size = <65536>; 2957a12cf5c3SThierry Reding d-cache-line-size = <64>; 2958a12cf5c3SThierry Reding d-cache-sets = <256>; 2959a12cf5c3SThierry Reding next-level-cache = <&l2c2_3>; 2960a12cf5c3SThierry Reding }; 2961a12cf5c3SThierry Reding 2962a12cf5c3SThierry Reding cpu-map { 2963a12cf5c3SThierry Reding cluster0 { 2964a12cf5c3SThierry Reding core0 { 2965a12cf5c3SThierry Reding cpu = <&cpu0_0>; 2966a12cf5c3SThierry Reding }; 2967a12cf5c3SThierry Reding 2968a12cf5c3SThierry Reding core1 { 2969a12cf5c3SThierry Reding cpu = <&cpu0_1>; 2970a12cf5c3SThierry Reding }; 2971a12cf5c3SThierry Reding 2972a12cf5c3SThierry Reding core2 { 2973a12cf5c3SThierry Reding cpu = <&cpu0_2>; 2974a12cf5c3SThierry Reding }; 2975a12cf5c3SThierry Reding 2976a12cf5c3SThierry Reding core3 { 2977a12cf5c3SThierry Reding cpu = <&cpu0_3>; 2978a12cf5c3SThierry Reding }; 2979a12cf5c3SThierry Reding }; 2980a12cf5c3SThierry Reding 2981a12cf5c3SThierry Reding cluster1 { 2982a12cf5c3SThierry Reding core0 { 2983a12cf5c3SThierry Reding cpu = <&cpu1_0>; 2984a12cf5c3SThierry Reding }; 2985a12cf5c3SThierry Reding 2986a12cf5c3SThierry Reding core1 { 2987a12cf5c3SThierry Reding cpu = <&cpu1_1>; 2988a12cf5c3SThierry Reding }; 2989a12cf5c3SThierry Reding 2990a12cf5c3SThierry Reding core2 { 2991a12cf5c3SThierry Reding cpu = <&cpu1_2>; 2992a12cf5c3SThierry Reding }; 2993a12cf5c3SThierry Reding 2994a12cf5c3SThierry Reding core3 { 2995a12cf5c3SThierry Reding cpu = <&cpu1_3>; 2996a12cf5c3SThierry Reding }; 2997a12cf5c3SThierry Reding }; 2998a12cf5c3SThierry Reding 2999a12cf5c3SThierry Reding cluster2 { 3000a12cf5c3SThierry Reding core0 { 3001a12cf5c3SThierry Reding cpu = <&cpu2_0>; 3002a12cf5c3SThierry Reding }; 3003a12cf5c3SThierry Reding 3004a12cf5c3SThierry Reding core1 { 3005a12cf5c3SThierry Reding cpu = <&cpu2_1>; 3006a12cf5c3SThierry Reding }; 3007a12cf5c3SThierry Reding 3008a12cf5c3SThierry Reding core2 { 3009a12cf5c3SThierry Reding cpu = <&cpu2_2>; 3010a12cf5c3SThierry Reding }; 3011a12cf5c3SThierry Reding 3012a12cf5c3SThierry Reding core3 { 3013a12cf5c3SThierry Reding cpu = <&cpu2_3>; 3014a12cf5c3SThierry Reding }; 3015a12cf5c3SThierry Reding }; 3016a12cf5c3SThierry Reding }; 3017a12cf5c3SThierry Reding 3018a12cf5c3SThierry Reding l2c0_0: l2-cache00 { 3019a12cf5c3SThierry Reding cache-size = <262144>; 3020a12cf5c3SThierry Reding cache-line-size = <64>; 3021a12cf5c3SThierry Reding cache-sets = <512>; 3022a12cf5c3SThierry Reding cache-unified; 3023a12cf5c3SThierry Reding next-level-cache = <&l3c0>; 3024a12cf5c3SThierry Reding }; 3025a12cf5c3SThierry Reding 3026a12cf5c3SThierry Reding l2c0_1: l2-cache01 { 3027a12cf5c3SThierry Reding cache-size = <262144>; 3028a12cf5c3SThierry Reding cache-line-size = <64>; 3029a12cf5c3SThierry Reding cache-sets = <512>; 3030a12cf5c3SThierry Reding cache-unified; 3031a12cf5c3SThierry Reding next-level-cache = <&l3c0>; 3032a12cf5c3SThierry Reding }; 3033a12cf5c3SThierry Reding 3034a12cf5c3SThierry Reding l2c0_2: l2-cache02 { 3035a12cf5c3SThierry Reding cache-size = <262144>; 3036a12cf5c3SThierry Reding cache-line-size = <64>; 3037a12cf5c3SThierry Reding cache-sets = <512>; 3038a12cf5c3SThierry Reding cache-unified; 3039a12cf5c3SThierry Reding next-level-cache = <&l3c0>; 3040a12cf5c3SThierry Reding }; 3041a12cf5c3SThierry Reding 3042a12cf5c3SThierry Reding l2c0_3: l2-cache03 { 3043a12cf5c3SThierry Reding cache-size = <262144>; 3044a12cf5c3SThierry Reding cache-line-size = <64>; 3045a12cf5c3SThierry Reding cache-sets = <512>; 3046a12cf5c3SThierry Reding cache-unified; 3047a12cf5c3SThierry Reding next-level-cache = <&l3c0>; 3048a12cf5c3SThierry Reding }; 3049a12cf5c3SThierry Reding 3050a12cf5c3SThierry Reding l2c1_0: l2-cache10 { 3051a12cf5c3SThierry Reding cache-size = <262144>; 3052a12cf5c3SThierry Reding cache-line-size = <64>; 3053a12cf5c3SThierry Reding cache-sets = <512>; 3054a12cf5c3SThierry Reding cache-unified; 3055a12cf5c3SThierry Reding next-level-cache = <&l3c1>; 3056a12cf5c3SThierry Reding }; 3057a12cf5c3SThierry Reding 3058a12cf5c3SThierry Reding l2c1_1: l2-cache11 { 3059a12cf5c3SThierry Reding cache-size = <262144>; 3060a12cf5c3SThierry Reding cache-line-size = <64>; 3061a12cf5c3SThierry Reding cache-sets = <512>; 3062a12cf5c3SThierry Reding cache-unified; 3063a12cf5c3SThierry Reding next-level-cache = <&l3c1>; 3064a12cf5c3SThierry Reding }; 3065a12cf5c3SThierry Reding 3066a12cf5c3SThierry Reding l2c1_2: l2-cache12 { 3067a12cf5c3SThierry Reding cache-size = <262144>; 3068a12cf5c3SThierry Reding cache-line-size = <64>; 3069a12cf5c3SThierry Reding cache-sets = <512>; 3070a12cf5c3SThierry Reding cache-unified; 3071a12cf5c3SThierry Reding next-level-cache = <&l3c1>; 3072a12cf5c3SThierry Reding }; 3073a12cf5c3SThierry Reding 3074a12cf5c3SThierry Reding l2c1_3: l2-cache13 { 3075a12cf5c3SThierry Reding cache-size = <262144>; 3076a12cf5c3SThierry Reding cache-line-size = <64>; 3077a12cf5c3SThierry Reding cache-sets = <512>; 3078a12cf5c3SThierry Reding cache-unified; 3079a12cf5c3SThierry Reding next-level-cache = <&l3c1>; 3080a12cf5c3SThierry Reding }; 3081a12cf5c3SThierry Reding 3082a12cf5c3SThierry Reding l2c2_0: l2-cache20 { 3083a12cf5c3SThierry Reding cache-size = <262144>; 3084a12cf5c3SThierry Reding cache-line-size = <64>; 3085a12cf5c3SThierry Reding cache-sets = <512>; 3086a12cf5c3SThierry Reding cache-unified; 3087a12cf5c3SThierry Reding next-level-cache = <&l3c2>; 3088a12cf5c3SThierry Reding }; 3089a12cf5c3SThierry Reding 3090a12cf5c3SThierry Reding l2c2_1: l2-cache21 { 3091a12cf5c3SThierry Reding cache-size = <262144>; 3092a12cf5c3SThierry Reding cache-line-size = <64>; 3093a12cf5c3SThierry Reding cache-sets = <512>; 3094a12cf5c3SThierry Reding cache-unified; 3095a12cf5c3SThierry Reding next-level-cache = <&l3c2>; 3096a12cf5c3SThierry Reding }; 3097a12cf5c3SThierry Reding 3098a12cf5c3SThierry Reding l2c2_2: l2-cache22 { 3099a12cf5c3SThierry Reding cache-size = <262144>; 3100a12cf5c3SThierry Reding cache-line-size = <64>; 3101a12cf5c3SThierry Reding cache-sets = <512>; 3102a12cf5c3SThierry Reding cache-unified; 3103a12cf5c3SThierry Reding next-level-cache = <&l3c2>; 3104a12cf5c3SThierry Reding }; 3105a12cf5c3SThierry Reding 3106a12cf5c3SThierry Reding l2c2_3: l2-cache23 { 3107a12cf5c3SThierry Reding cache-size = <262144>; 3108a12cf5c3SThierry Reding cache-line-size = <64>; 3109a12cf5c3SThierry Reding cache-sets = <512>; 3110a12cf5c3SThierry Reding cache-unified; 3111a12cf5c3SThierry Reding next-level-cache = <&l3c2>; 3112a12cf5c3SThierry Reding }; 3113a12cf5c3SThierry Reding 3114a12cf5c3SThierry Reding l3c0: l3-cache0 { 3115a12cf5c3SThierry Reding cache-size = <2097152>; 3116a12cf5c3SThierry Reding cache-line-size = <64>; 3117a12cf5c3SThierry Reding cache-sets = <2048>; 3118a12cf5c3SThierry Reding }; 3119a12cf5c3SThierry Reding 3120a12cf5c3SThierry Reding l3c1: l3-cache1 { 3121a12cf5c3SThierry Reding cache-size = <2097152>; 3122a12cf5c3SThierry Reding cache-line-size = <64>; 3123a12cf5c3SThierry Reding cache-sets = <2048>; 3124a12cf5c3SThierry Reding }; 3125a12cf5c3SThierry Reding 3126a12cf5c3SThierry Reding l3c2: l3-cache2 { 3127a12cf5c3SThierry Reding cache-size = <2097152>; 3128a12cf5c3SThierry Reding cache-line-size = <64>; 3129a12cf5c3SThierry Reding cache-sets = <2048>; 3130a12cf5c3SThierry Reding }; 3131a12cf5c3SThierry Reding }; 3132a12cf5c3SThierry Reding 3133a12cf5c3SThierry Reding pmu { 3134a12cf5c3SThierry Reding compatible = "arm,cortex-a78-pmu"; 3135a12cf5c3SThierry Reding interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 3136a12cf5c3SThierry Reding status = "okay"; 313763944891SThierry Reding }; 313863944891SThierry Reding 313963944891SThierry Reding psci { 314063944891SThierry Reding compatible = "arm,psci-1.0"; 314163944891SThierry Reding status = "okay"; 314263944891SThierry Reding method = "smc"; 314363944891SThierry Reding }; 314463944891SThierry Reding 314506ad2ec4SMikko Perttunen tcu: serial { 314606ad2ec4SMikko Perttunen compatible = "nvidia,tegra234-tcu", "nvidia,tegra194-tcu"; 314706ad2ec4SMikko Perttunen mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 314806ad2ec4SMikko Perttunen <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 314906ad2ec4SMikko Perttunen mbox-names = "rx", "tx"; 315006ad2ec4SMikko Perttunen status = "disabled"; 315106ad2ec4SMikko Perttunen }; 315206ad2ec4SMikko Perttunen 315309614acdSSameer Pujar sound { 315409614acdSSameer Pujar status = "disabled"; 315509614acdSSameer Pujar 315609614acdSSameer Pujar clocks = <&bpmp TEGRA234_CLK_PLLA>, 315709614acdSSameer Pujar <&bpmp TEGRA234_CLK_PLLA_OUT0>; 315809614acdSSameer Pujar clock-names = "pll_a", "plla_out0"; 315909614acdSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_PLLA>, 316009614acdSSameer Pujar <&bpmp TEGRA234_CLK_PLLA_OUT0>, 316109614acdSSameer Pujar <&bpmp TEGRA234_CLK_AUD_MCLK>; 316209614acdSSameer Pujar assigned-clock-parents = <0>, 316309614acdSSameer Pujar <&bpmp TEGRA234_CLK_PLLA>, 316409614acdSSameer Pujar <&bpmp TEGRA234_CLK_PLLA_OUT0>; 316509614acdSSameer Pujar }; 316609614acdSSameer Pujar 316763944891SThierry Reding timer { 316863944891SThierry Reding compatible = "arm,armv8-timer"; 316963944891SThierry Reding interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 317063944891SThierry Reding <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 317163944891SThierry Reding <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 317263944891SThierry Reding <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 317363944891SThierry Reding interrupt-parent = <&gic>; 317463944891SThierry Reding always-on; 317563944891SThierry Reding }; 317663944891SThierry Reding}; 3177