163944891SThierry Reding// SPDX-License-Identifier: GPL-2.0 263944891SThierry Reding 363944891SThierry Reding#include <dt-bindings/clock/tegra234-clock.h> 463944891SThierry Reding#include <dt-bindings/interrupt-controller/arm-gic.h> 563944891SThierry Reding#include <dt-bindings/mailbox/tegra186-hsp.h> 6eed280dfSThierry Reding#include <dt-bindings/memory/tegra234-mc.h> 763944891SThierry Reding#include <dt-bindings/reset/tegra234-reset.h> 863944891SThierry Reding 963944891SThierry Reding/ { 1063944891SThierry Reding compatible = "nvidia,tegra234"; 1163944891SThierry Reding interrupt-parent = <&gic>; 1263944891SThierry Reding #address-cells = <2>; 1363944891SThierry Reding #size-cells = <2>; 1463944891SThierry Reding 1563944891SThierry Reding bus@0 { 1663944891SThierry Reding compatible = "simple-bus"; 1763944891SThierry Reding #address-cells = <1>; 1863944891SThierry Reding #size-cells = <1>; 1963944891SThierry Reding 2063944891SThierry Reding ranges = <0x0 0x0 0x0 0x40000000>; 2163944891SThierry Reding 2263944891SThierry Reding misc@100000 { 2363944891SThierry Reding compatible = "nvidia,tegra234-misc"; 2463944891SThierry Reding reg = <0x00100000 0xf000>, 2563944891SThierry Reding <0x0010f000 0x1000>; 2663944891SThierry Reding status = "okay"; 2763944891SThierry Reding }; 2863944891SThierry Reding 29f0e12668SThierry Reding gpio: gpio@2200000 { 30f0e12668SThierry Reding compatible = "nvidia,tegra234-gpio"; 31f0e12668SThierry Reding reg-names = "security", "gpio"; 32f0e12668SThierry Reding reg = <0x02200000 0x10000>, 33f0e12668SThierry Reding <0x02210000 0x10000>; 34f0e12668SThierry Reding interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 35f0e12668SThierry Reding <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 36f0e12668SThierry Reding <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 37f0e12668SThierry Reding <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, 38f0e12668SThierry Reding <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 39f0e12668SThierry Reding <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 40f0e12668SThierry Reding <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 41f0e12668SThierry Reding <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 42f0e12668SThierry Reding <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 43f0e12668SThierry Reding <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 44f0e12668SThierry Reding <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 45f0e12668SThierry Reding <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 46f0e12668SThierry Reding <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 47f0e12668SThierry Reding <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 48f0e12668SThierry Reding <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 49f0e12668SThierry Reding <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 50f0e12668SThierry Reding <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 51f0e12668SThierry Reding <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 52f0e12668SThierry Reding <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 53f0e12668SThierry Reding <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 54f0e12668SThierry Reding <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 55f0e12668SThierry Reding <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 56f0e12668SThierry Reding <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 57f0e12668SThierry Reding <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 58f0e12668SThierry Reding <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 59f0e12668SThierry Reding <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 60f0e12668SThierry Reding <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 61f0e12668SThierry Reding <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 62f0e12668SThierry Reding <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 63f0e12668SThierry Reding <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 64f0e12668SThierry Reding <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 65f0e12668SThierry Reding <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 66f0e12668SThierry Reding <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 67f0e12668SThierry Reding <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 68f0e12668SThierry Reding <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 69f0e12668SThierry Reding <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 70f0e12668SThierry Reding <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 71f0e12668SThierry Reding <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 72f0e12668SThierry Reding <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 73f0e12668SThierry Reding <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 74f0e12668SThierry Reding <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 75f0e12668SThierry Reding <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 76f0e12668SThierry Reding <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 77f0e12668SThierry Reding <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 78f0e12668SThierry Reding <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 79f0e12668SThierry Reding <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 80f0e12668SThierry Reding <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 81f0e12668SThierry Reding <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 82f0e12668SThierry Reding #interrupt-cells = <2>; 83f0e12668SThierry Reding interrupt-controller; 84f0e12668SThierry Reding #gpio-cells = <2>; 85f0e12668SThierry Reding gpio-controller; 86f0e12668SThierry Reding }; 87f0e12668SThierry Reding 88eed280dfSThierry Reding mc: memory-controller@2c00000 { 89eed280dfSThierry Reding compatible = "nvidia,tegra234-mc"; 90eed280dfSThierry Reding reg = <0x02c00000 0x100000>, 91eed280dfSThierry Reding <0x02b80000 0x040000>, 92eed280dfSThierry Reding <0x01700000 0x100000>; 93eed280dfSThierry Reding interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 94eed280dfSThierry Reding #interconnect-cells = <1>; 95eed280dfSThierry Reding status = "okay"; 96eed280dfSThierry Reding 97eed280dfSThierry Reding #address-cells = <2>; 98eed280dfSThierry Reding #size-cells = <2>; 99eed280dfSThierry Reding 100eed280dfSThierry Reding ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>, 101eed280dfSThierry Reding <0x02b80000 0x0 0x02b80000 0x0 0x040000>, 102eed280dfSThierry Reding <0x02c00000 0x0 0x02c00000 0x0 0x100000>; 103eed280dfSThierry Reding 104eed280dfSThierry Reding /* 105eed280dfSThierry Reding * Bit 39 of addresses passing through the memory 106eed280dfSThierry Reding * controller selects the XBAR format used when memory 107eed280dfSThierry Reding * is accessed. This is used to transparently access 108eed280dfSThierry Reding * memory in the XBAR format used by the discrete GPU 109eed280dfSThierry Reding * (bit 39 set) or Tegra (bit 39 clear). 110eed280dfSThierry Reding * 111eed280dfSThierry Reding * As a consequence, the operating system must ensure 112eed280dfSThierry Reding * that bit 39 is never used implicitly, for example 113eed280dfSThierry Reding * via an I/O virtual address mapping of an IOMMU. If 114eed280dfSThierry Reding * devices require access to the XBAR switch, their 115eed280dfSThierry Reding * drivers must set this bit explicitly. 116eed280dfSThierry Reding * 117eed280dfSThierry Reding * Limit the DMA range for memory clients to [38:0]. 118eed280dfSThierry Reding */ 119eed280dfSThierry Reding dma-ranges = <0x0 0x0 0x0 0x80 0x0>; 120eed280dfSThierry Reding 121eed280dfSThierry Reding emc: external-memory-controller@2c60000 { 122eed280dfSThierry Reding compatible = "nvidia,tegra234-emc"; 123eed280dfSThierry Reding reg = <0x0 0x02c60000 0x0 0x90000>, 124eed280dfSThierry Reding <0x0 0x01780000 0x0 0x80000>; 125eed280dfSThierry Reding interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 126eed280dfSThierry Reding clocks = <&bpmp TEGRA234_CLK_EMC>; 127eed280dfSThierry Reding clock-names = "emc"; 128eed280dfSThierry Reding status = "okay"; 129eed280dfSThierry Reding 130eed280dfSThierry Reding #interconnect-cells = <0>; 131eed280dfSThierry Reding 132eed280dfSThierry Reding nvidia,bpmp = <&bpmp>; 133eed280dfSThierry Reding }; 134eed280dfSThierry Reding }; 135eed280dfSThierry Reding 13663944891SThierry Reding uarta: serial@3100000 { 13763944891SThierry Reding compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart"; 13863944891SThierry Reding reg = <0x03100000 0x10000>; 13963944891SThierry Reding interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 14063944891SThierry Reding clocks = <&bpmp TEGRA234_CLK_UARTA>; 14163944891SThierry Reding clock-names = "serial"; 14263944891SThierry Reding resets = <&bpmp TEGRA234_RESET_UARTA>; 14363944891SThierry Reding reset-names = "serial"; 14463944891SThierry Reding status = "disabled"; 14563944891SThierry Reding }; 14663944891SThierry Reding 147*156af9deSAkhil R gen1_i2c: i2c@3160000 { 148*156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 149*156af9deSAkhil R reg = <0x3160000 0x100>; 150*156af9deSAkhil R status = "disabled"; 151*156af9deSAkhil R interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 152*156af9deSAkhil R clock-frequency = <400000>; 153*156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C1 154*156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 155*156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C1>; 156*156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 157*156af9deSAkhil R clock-names = "div-clk", "parent"; 158*156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C1>; 159*156af9deSAkhil R reset-names = "i2c"; 160*156af9deSAkhil R }; 161*156af9deSAkhil R 162*156af9deSAkhil R cam_i2c: i2c@3180000 { 163*156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 164*156af9deSAkhil R reg = <0x3180000 0x100>; 165*156af9deSAkhil R interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 166*156af9deSAkhil R status = "disabled"; 167*156af9deSAkhil R clock-frequency = <400000>; 168*156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C3 169*156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 170*156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C3>; 171*156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 172*156af9deSAkhil R clock-names = "div-clk", "parent"; 173*156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C3>; 174*156af9deSAkhil R reset-names = "i2c"; 175*156af9deSAkhil R }; 176*156af9deSAkhil R 177*156af9deSAkhil R dp_aux_ch1_i2c: i2c@3190000 { 178*156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 179*156af9deSAkhil R reg = <0x3190000 0x100>; 180*156af9deSAkhil R interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 181*156af9deSAkhil R status = "disabled"; 182*156af9deSAkhil R clock-frequency = <100000>; 183*156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C4 184*156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 185*156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C4>; 186*156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 187*156af9deSAkhil R clock-names = "div-clk", "parent"; 188*156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C4>; 189*156af9deSAkhil R reset-names = "i2c"; 190*156af9deSAkhil R }; 191*156af9deSAkhil R 192*156af9deSAkhil R dp_aux_ch0_i2c: i2c@31b0000 { 193*156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 194*156af9deSAkhil R reg = <0x31b0000 0x100>; 195*156af9deSAkhil R interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 196*156af9deSAkhil R status = "disabled"; 197*156af9deSAkhil R clock-frequency = <100000>; 198*156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C6 199*156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 200*156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C6>; 201*156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 202*156af9deSAkhil R clock-names = "div-clk", "parent"; 203*156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C6>; 204*156af9deSAkhil R reset-names = "i2c"; 205*156af9deSAkhil R }; 206*156af9deSAkhil R 207*156af9deSAkhil R dp_aux_ch2_i2c: i2c@31c0000 { 208*156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 209*156af9deSAkhil R reg = <0x31c0000 0x100>; 210*156af9deSAkhil R interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 211*156af9deSAkhil R status = "disabled"; 212*156af9deSAkhil R clock-frequency = <100000>; 213*156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C7 214*156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 215*156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C7>; 216*156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 217*156af9deSAkhil R clock-names = "div-clk", "parent"; 218*156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C7>; 219*156af9deSAkhil R reset-names = "i2c"; 220*156af9deSAkhil R }; 221*156af9deSAkhil R 222*156af9deSAkhil R dp_aux_ch3_i2c: i2c@31e0000 { 223*156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 224*156af9deSAkhil R reg = <0x31e0000 0x100>; 225*156af9deSAkhil R interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 226*156af9deSAkhil R status = "disabled"; 227*156af9deSAkhil R clock-frequency = <100000>; 228*156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C9 229*156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 230*156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C9>; 231*156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 232*156af9deSAkhil R clock-names = "div-clk", "parent"; 233*156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C9>; 234*156af9deSAkhil R reset-names = "i2c"; 235*156af9deSAkhil R }; 236*156af9deSAkhil R 23763944891SThierry Reding mmc@3460000 { 23863944891SThierry Reding compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci"; 23963944891SThierry Reding reg = <0x03460000 0x20000>; 24063944891SThierry Reding interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 241e086d82dSMikko Perttunen clocks = <&bpmp TEGRA234_CLK_SDMMC4>, 242e086d82dSMikko Perttunen <&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>; 243e086d82dSMikko Perttunen clock-names = "sdhci", "tmclk"; 244e086d82dSMikko Perttunen assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC4>, 245e086d82dSMikko Perttunen <&bpmp TEGRA234_CLK_PLLC4>; 246e086d82dSMikko Perttunen assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4>; 24763944891SThierry Reding resets = <&bpmp TEGRA234_RESET_SDMMC4>; 24863944891SThierry Reding reset-names = "sdhci"; 2496de481e5SThierry Reding interconnects = <&mc TEGRA234_MEMORY_CLIENT_SDMMCRAB &emc>, 2506de481e5SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_SDMMCWAB &emc>; 2516de481e5SThierry Reding interconnect-names = "dma-mem", "write"; 252e086d82dSMikko Perttunen nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 253e086d82dSMikko Perttunen nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 254e086d82dSMikko Perttunen nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 255e086d82dSMikko Perttunen nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; 256e086d82dSMikko Perttunen nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 257e086d82dSMikko Perttunen nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>; 258e086d82dSMikko Perttunen nvidia,default-tap = <0x8>; 259e086d82dSMikko Perttunen nvidia,default-trim = <0x14>; 260e086d82dSMikko Perttunen nvidia,dqs-trim = <40>; 261e086d82dSMikko Perttunen supports-cqe; 26263944891SThierry Reding status = "disabled"; 26363944891SThierry Reding }; 26463944891SThierry Reding 26563944891SThierry Reding fuse@3810000 { 26663944891SThierry Reding compatible = "nvidia,tegra234-efuse"; 26763944891SThierry Reding reg = <0x03810000 0x10000>; 26863944891SThierry Reding clocks = <&bpmp TEGRA234_CLK_FUSE>; 26963944891SThierry Reding clock-names = "fuse"; 27063944891SThierry Reding }; 27163944891SThierry Reding 27263944891SThierry Reding hsp_top0: hsp@3c00000 { 27363944891SThierry Reding compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; 27463944891SThierry Reding reg = <0x03c00000 0xa0000>; 27563944891SThierry Reding interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 27663944891SThierry Reding <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 27763944891SThierry Reding <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 27863944891SThierry Reding <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 27963944891SThierry Reding <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 28063944891SThierry Reding <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 28163944891SThierry Reding <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 28263944891SThierry Reding <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 28363944891SThierry Reding <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 28463944891SThierry Reding interrupt-names = "doorbell", "shared0", "shared1", "shared2", 28563944891SThierry Reding "shared3", "shared4", "shared5", "shared6", 28663944891SThierry Reding "shared7"; 28763944891SThierry Reding #mbox-cells = <2>; 28863944891SThierry Reding }; 28963944891SThierry Reding 29063944891SThierry Reding hsp_aon: hsp@c150000 { 29163944891SThierry Reding compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; 29263944891SThierry Reding reg = <0x0c150000 0x90000>; 29363944891SThierry Reding interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 29463944891SThierry Reding <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 29563944891SThierry Reding <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 29663944891SThierry Reding <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 29763944891SThierry Reding /* 29863944891SThierry Reding * Shared interrupt 0 is routed only to AON/SPE, so 29963944891SThierry Reding * we only have 4 shared interrupts for the CCPLEX. 30063944891SThierry Reding */ 30163944891SThierry Reding interrupt-names = "shared1", "shared2", "shared3", "shared4"; 30263944891SThierry Reding #mbox-cells = <2>; 30363944891SThierry Reding }; 30463944891SThierry Reding 305*156af9deSAkhil R gen2_i2c: i2c@c240000 { 306*156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 307*156af9deSAkhil R reg = <0xc240000 0x100>; 308*156af9deSAkhil R interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 309*156af9deSAkhil R status = "disabled"; 310*156af9deSAkhil R clock-frequency = <100000>; 311*156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C2 312*156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 313*156af9deSAkhil R clock-names = "div-clk", "parent"; 314*156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C2>; 315*156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 316*156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C2>; 317*156af9deSAkhil R reset-names = "i2c"; 318*156af9deSAkhil R }; 319*156af9deSAkhil R 320*156af9deSAkhil R gen8_i2c: i2c@c250000 { 321*156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 322*156af9deSAkhil R reg = <0xc250000 0x100>; 323*156af9deSAkhil R nvidia,hw-instance-id = <0x7>; 324*156af9deSAkhil R interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 325*156af9deSAkhil R status = "disabled"; 326*156af9deSAkhil R clock-frequency = <400000>; 327*156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C8 328*156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 329*156af9deSAkhil R clock-names = "div-clk", "parent"; 330*156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C8>; 331*156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 332*156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C8>; 333*156af9deSAkhil R reset-names = "i2c"; 334*156af9deSAkhil R }; 335*156af9deSAkhil R 33663944891SThierry Reding rtc@c2a0000 { 33763944891SThierry Reding compatible = "nvidia,tegra234-rtc", "nvidia,tegra20-rtc"; 33863944891SThierry Reding reg = <0x0c2a0000 0x10000>; 33963944891SThierry Reding interrupt-parent = <&pmc>; 34063944891SThierry Reding interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 341e537addeSMikko Perttunen clocks = <&bpmp TEGRA234_CLK_CLK_32K>; 342e537addeSMikko Perttunen clock-names = "rtc"; 34363944891SThierry Reding status = "disabled"; 34463944891SThierry Reding }; 34563944891SThierry Reding 346f0e12668SThierry Reding gpio_aon: gpio@c2f0000 { 347f0e12668SThierry Reding compatible = "nvidia,tegra234-gpio-aon"; 348f0e12668SThierry Reding reg-names = "security", "gpio"; 349f0e12668SThierry Reding reg = <0x0c2f0000 0x1000>, 350f0e12668SThierry Reding <0x0c2f1000 0x1000>; 351f0e12668SThierry Reding interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 352f0e12668SThierry Reding <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 353f0e12668SThierry Reding <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 354f0e12668SThierry Reding <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 355f0e12668SThierry Reding #interrupt-cells = <2>; 356f0e12668SThierry Reding interrupt-controller; 357f0e12668SThierry Reding #gpio-cells = <2>; 358f0e12668SThierry Reding gpio-controller; 359f0e12668SThierry Reding }; 360f0e12668SThierry Reding 36163944891SThierry Reding pmc: pmc@c360000 { 36263944891SThierry Reding compatible = "nvidia,tegra234-pmc"; 36363944891SThierry Reding reg = <0x0c360000 0x10000>, 36463944891SThierry Reding <0x0c370000 0x10000>, 36563944891SThierry Reding <0x0c380000 0x10000>, 36663944891SThierry Reding <0x0c390000 0x10000>, 36763944891SThierry Reding <0x0c3a0000 0x10000>; 36863944891SThierry Reding reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 36963944891SThierry Reding 37063944891SThierry Reding #interrupt-cells = <2>; 37163944891SThierry Reding interrupt-controller; 37263944891SThierry Reding }; 37363944891SThierry Reding 37463944891SThierry Reding gic: interrupt-controller@f400000 { 37563944891SThierry Reding compatible = "arm,gic-v3"; 37663944891SThierry Reding reg = <0x0f400000 0x010000>, /* GICD */ 37763944891SThierry Reding <0x0f440000 0x200000>; /* GICR */ 37863944891SThierry Reding interrupt-parent = <&gic>; 37963944891SThierry Reding interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 38063944891SThierry Reding 38163944891SThierry Reding #redistributor-regions = <1>; 38263944891SThierry Reding #interrupt-cells = <3>; 38363944891SThierry Reding interrupt-controller; 38463944891SThierry Reding }; 38563944891SThierry Reding }; 38663944891SThierry Reding 3877fa30752SThierry Reding sram@40000000 { 38863944891SThierry Reding compatible = "nvidia,tegra234-sysram", "mmio-sram"; 38998094be1SMikko Perttunen reg = <0x0 0x40000000 0x0 0x80000>; 39063944891SThierry Reding #address-cells = <1>; 39163944891SThierry Reding #size-cells = <1>; 39298094be1SMikko Perttunen ranges = <0x0 0x0 0x40000000 0x80000>; 39363944891SThierry Reding 39498094be1SMikko Perttunen cpu_bpmp_tx: sram@70000 { 39598094be1SMikko Perttunen reg = <0x70000 0x1000>; 39663944891SThierry Reding label = "cpu-bpmp-tx"; 39763944891SThierry Reding pool; 39863944891SThierry Reding }; 39963944891SThierry Reding 40098094be1SMikko Perttunen cpu_bpmp_rx: sram@71000 { 40198094be1SMikko Perttunen reg = <0x71000 0x1000>; 40263944891SThierry Reding label = "cpu-bpmp-rx"; 40363944891SThierry Reding pool; 40463944891SThierry Reding }; 40563944891SThierry Reding }; 40663944891SThierry Reding 40763944891SThierry Reding bpmp: bpmp { 40863944891SThierry Reding compatible = "nvidia,tegra234-bpmp", "nvidia,tegra186-bpmp"; 40963944891SThierry Reding mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 41063944891SThierry Reding TEGRA_HSP_DB_MASTER_BPMP>; 4117fa30752SThierry Reding shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; 41263944891SThierry Reding #clock-cells = <1>; 41363944891SThierry Reding #reset-cells = <1>; 41463944891SThierry Reding #power-domain-cells = <1>; 4156de481e5SThierry Reding interconnects = <&mc TEGRA234_MEMORY_CLIENT_BPMPR &emc>, 4166de481e5SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_BPMPW &emc>, 4176de481e5SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAR &emc>, 4186de481e5SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAW &emc>; 4196de481e5SThierry Reding interconnect-names = "read", "write", "dma-mem", "dma-write"; 42063944891SThierry Reding 42163944891SThierry Reding bpmp_i2c: i2c { 42263944891SThierry Reding compatible = "nvidia,tegra186-bpmp-i2c"; 42363944891SThierry Reding nvidia,bpmp-bus-id = <5>; 42463944891SThierry Reding #address-cells = <1>; 42563944891SThierry Reding #size-cells = <0>; 42663944891SThierry Reding }; 42763944891SThierry Reding }; 42863944891SThierry Reding 42963944891SThierry Reding cpus { 43063944891SThierry Reding #address-cells = <1>; 43163944891SThierry Reding #size-cells = <0>; 43263944891SThierry Reding 433a12cf5c3SThierry Reding cpu0_0: cpu@0 { 434a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 43563944891SThierry Reding device_type = "cpu"; 436a12cf5c3SThierry Reding reg = <0x00000>; 43763944891SThierry Reding 43863944891SThierry Reding enable-method = "psci"; 439a12cf5c3SThierry Reding 440a12cf5c3SThierry Reding i-cache-size = <65536>; 441a12cf5c3SThierry Reding i-cache-line-size = <64>; 442a12cf5c3SThierry Reding i-cache-sets = <256>; 443a12cf5c3SThierry Reding d-cache-size = <65536>; 444a12cf5c3SThierry Reding d-cache-line-size = <64>; 445a12cf5c3SThierry Reding d-cache-sets = <256>; 446a12cf5c3SThierry Reding next-level-cache = <&l2c0_0>; 44763944891SThierry Reding }; 448a12cf5c3SThierry Reding 449a12cf5c3SThierry Reding cpu0_1: cpu@100 { 450a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 451a12cf5c3SThierry Reding device_type = "cpu"; 452a12cf5c3SThierry Reding reg = <0x00100>; 453a12cf5c3SThierry Reding 454a12cf5c3SThierry Reding enable-method = "psci"; 455a12cf5c3SThierry Reding 456a12cf5c3SThierry Reding i-cache-size = <65536>; 457a12cf5c3SThierry Reding i-cache-line-size = <64>; 458a12cf5c3SThierry Reding i-cache-sets = <256>; 459a12cf5c3SThierry Reding d-cache-size = <65536>; 460a12cf5c3SThierry Reding d-cache-line-size = <64>; 461a12cf5c3SThierry Reding d-cache-sets = <256>; 462a12cf5c3SThierry Reding next-level-cache = <&l2c0_1>; 463a12cf5c3SThierry Reding }; 464a12cf5c3SThierry Reding 465a12cf5c3SThierry Reding cpu0_2: cpu@200 { 466a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 467a12cf5c3SThierry Reding device_type = "cpu"; 468a12cf5c3SThierry Reding reg = <0x00200>; 469a12cf5c3SThierry Reding 470a12cf5c3SThierry Reding enable-method = "psci"; 471a12cf5c3SThierry Reding 472a12cf5c3SThierry Reding i-cache-size = <65536>; 473a12cf5c3SThierry Reding i-cache-line-size = <64>; 474a12cf5c3SThierry Reding i-cache-sets = <256>; 475a12cf5c3SThierry Reding d-cache-size = <65536>; 476a12cf5c3SThierry Reding d-cache-line-size = <64>; 477a12cf5c3SThierry Reding d-cache-sets = <256>; 478a12cf5c3SThierry Reding next-level-cache = <&l2c0_2>; 479a12cf5c3SThierry Reding }; 480a12cf5c3SThierry Reding 481a12cf5c3SThierry Reding cpu0_3: cpu@300 { 482a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 483a12cf5c3SThierry Reding device_type = "cpu"; 484a12cf5c3SThierry Reding reg = <0x00300>; 485a12cf5c3SThierry Reding 486a12cf5c3SThierry Reding enable-method = "psci"; 487a12cf5c3SThierry Reding 488a12cf5c3SThierry Reding i-cache-size = <65536>; 489a12cf5c3SThierry Reding i-cache-line-size = <64>; 490a12cf5c3SThierry Reding i-cache-sets = <256>; 491a12cf5c3SThierry Reding d-cache-size = <65536>; 492a12cf5c3SThierry Reding d-cache-line-size = <64>; 493a12cf5c3SThierry Reding d-cache-sets = <256>; 494a12cf5c3SThierry Reding next-level-cache = <&l2c0_3>; 495a12cf5c3SThierry Reding }; 496a12cf5c3SThierry Reding 497a12cf5c3SThierry Reding cpu1_0: cpu@10000 { 498a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 499a12cf5c3SThierry Reding device_type = "cpu"; 500a12cf5c3SThierry Reding reg = <0x10000>; 501a12cf5c3SThierry Reding 502a12cf5c3SThierry Reding enable-method = "psci"; 503a12cf5c3SThierry Reding 504a12cf5c3SThierry Reding i-cache-size = <65536>; 505a12cf5c3SThierry Reding i-cache-line-size = <64>; 506a12cf5c3SThierry Reding i-cache-sets = <256>; 507a12cf5c3SThierry Reding d-cache-size = <65536>; 508a12cf5c3SThierry Reding d-cache-line-size = <64>; 509a12cf5c3SThierry Reding d-cache-sets = <256>; 510a12cf5c3SThierry Reding next-level-cache = <&l2c1_0>; 511a12cf5c3SThierry Reding }; 512a12cf5c3SThierry Reding 513a12cf5c3SThierry Reding cpu1_1: cpu@10100 { 514a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 515a12cf5c3SThierry Reding device_type = "cpu"; 516a12cf5c3SThierry Reding reg = <0x10100>; 517a12cf5c3SThierry Reding 518a12cf5c3SThierry Reding enable-method = "psci"; 519a12cf5c3SThierry Reding 520a12cf5c3SThierry Reding i-cache-size = <65536>; 521a12cf5c3SThierry Reding i-cache-line-size = <64>; 522a12cf5c3SThierry Reding i-cache-sets = <256>; 523a12cf5c3SThierry Reding d-cache-size = <65536>; 524a12cf5c3SThierry Reding d-cache-line-size = <64>; 525a12cf5c3SThierry Reding d-cache-sets = <256>; 526a12cf5c3SThierry Reding next-level-cache = <&l2c1_1>; 527a12cf5c3SThierry Reding }; 528a12cf5c3SThierry Reding 529a12cf5c3SThierry Reding cpu1_2: cpu@10200 { 530a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 531a12cf5c3SThierry Reding device_type = "cpu"; 532a12cf5c3SThierry Reding reg = <0x10200>; 533a12cf5c3SThierry Reding 534a12cf5c3SThierry Reding enable-method = "psci"; 535a12cf5c3SThierry Reding 536a12cf5c3SThierry Reding i-cache-size = <65536>; 537a12cf5c3SThierry Reding i-cache-line-size = <64>; 538a12cf5c3SThierry Reding i-cache-sets = <256>; 539a12cf5c3SThierry Reding d-cache-size = <65536>; 540a12cf5c3SThierry Reding d-cache-line-size = <64>; 541a12cf5c3SThierry Reding d-cache-sets = <256>; 542a12cf5c3SThierry Reding next-level-cache = <&l2c1_2>; 543a12cf5c3SThierry Reding }; 544a12cf5c3SThierry Reding 545a12cf5c3SThierry Reding cpu1_3: cpu@10300 { 546a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 547a12cf5c3SThierry Reding device_type = "cpu"; 548a12cf5c3SThierry Reding reg = <0x10300>; 549a12cf5c3SThierry Reding 550a12cf5c3SThierry Reding enable-method = "psci"; 551a12cf5c3SThierry Reding 552a12cf5c3SThierry Reding i-cache-size = <65536>; 553a12cf5c3SThierry Reding i-cache-line-size = <64>; 554a12cf5c3SThierry Reding i-cache-sets = <256>; 555a12cf5c3SThierry Reding d-cache-size = <65536>; 556a12cf5c3SThierry Reding d-cache-line-size = <64>; 557a12cf5c3SThierry Reding d-cache-sets = <256>; 558a12cf5c3SThierry Reding next-level-cache = <&l2c1_3>; 559a12cf5c3SThierry Reding }; 560a12cf5c3SThierry Reding 561a12cf5c3SThierry Reding cpu2_0: cpu@20000 { 562a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 563a12cf5c3SThierry Reding device_type = "cpu"; 564a12cf5c3SThierry Reding reg = <0x20000>; 565a12cf5c3SThierry Reding 566a12cf5c3SThierry Reding enable-method = "psci"; 567a12cf5c3SThierry Reding 568a12cf5c3SThierry Reding i-cache-size = <65536>; 569a12cf5c3SThierry Reding i-cache-line-size = <64>; 570a12cf5c3SThierry Reding i-cache-sets = <256>; 571a12cf5c3SThierry Reding d-cache-size = <65536>; 572a12cf5c3SThierry Reding d-cache-line-size = <64>; 573a12cf5c3SThierry Reding d-cache-sets = <256>; 574a12cf5c3SThierry Reding next-level-cache = <&l2c2_0>; 575a12cf5c3SThierry Reding }; 576a12cf5c3SThierry Reding 577a12cf5c3SThierry Reding cpu2_1: cpu@20100 { 578a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 579a12cf5c3SThierry Reding device_type = "cpu"; 580a12cf5c3SThierry Reding reg = <0x20100>; 581a12cf5c3SThierry Reding 582a12cf5c3SThierry Reding enable-method = "psci"; 583a12cf5c3SThierry Reding 584a12cf5c3SThierry Reding i-cache-size = <65536>; 585a12cf5c3SThierry Reding i-cache-line-size = <64>; 586a12cf5c3SThierry Reding i-cache-sets = <256>; 587a12cf5c3SThierry Reding d-cache-size = <65536>; 588a12cf5c3SThierry Reding d-cache-line-size = <64>; 589a12cf5c3SThierry Reding d-cache-sets = <256>; 590a12cf5c3SThierry Reding next-level-cache = <&l2c2_1>; 591a12cf5c3SThierry Reding }; 592a12cf5c3SThierry Reding 593a12cf5c3SThierry Reding cpu2_2: cpu@20200 { 594a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 595a12cf5c3SThierry Reding device_type = "cpu"; 596a12cf5c3SThierry Reding reg = <0x20200>; 597a12cf5c3SThierry Reding 598a12cf5c3SThierry Reding enable-method = "psci"; 599a12cf5c3SThierry Reding 600a12cf5c3SThierry Reding i-cache-size = <65536>; 601a12cf5c3SThierry Reding i-cache-line-size = <64>; 602a12cf5c3SThierry Reding i-cache-sets = <256>; 603a12cf5c3SThierry Reding d-cache-size = <65536>; 604a12cf5c3SThierry Reding d-cache-line-size = <64>; 605a12cf5c3SThierry Reding d-cache-sets = <256>; 606a12cf5c3SThierry Reding next-level-cache = <&l2c2_2>; 607a12cf5c3SThierry Reding }; 608a12cf5c3SThierry Reding 609a12cf5c3SThierry Reding cpu2_3: cpu@20300 { 610a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 611a12cf5c3SThierry Reding device_type = "cpu"; 612a12cf5c3SThierry Reding reg = <0x20300>; 613a12cf5c3SThierry Reding 614a12cf5c3SThierry Reding enable-method = "psci"; 615a12cf5c3SThierry Reding 616a12cf5c3SThierry Reding i-cache-size = <65536>; 617a12cf5c3SThierry Reding i-cache-line-size = <64>; 618a12cf5c3SThierry Reding i-cache-sets = <256>; 619a12cf5c3SThierry Reding d-cache-size = <65536>; 620a12cf5c3SThierry Reding d-cache-line-size = <64>; 621a12cf5c3SThierry Reding d-cache-sets = <256>; 622a12cf5c3SThierry Reding next-level-cache = <&l2c2_3>; 623a12cf5c3SThierry Reding }; 624a12cf5c3SThierry Reding 625a12cf5c3SThierry Reding cpu-map { 626a12cf5c3SThierry Reding cluster0 { 627a12cf5c3SThierry Reding core0 { 628a12cf5c3SThierry Reding cpu = <&cpu0_0>; 629a12cf5c3SThierry Reding }; 630a12cf5c3SThierry Reding 631a12cf5c3SThierry Reding core1 { 632a12cf5c3SThierry Reding cpu = <&cpu0_1>; 633a12cf5c3SThierry Reding }; 634a12cf5c3SThierry Reding 635a12cf5c3SThierry Reding core2 { 636a12cf5c3SThierry Reding cpu = <&cpu0_2>; 637a12cf5c3SThierry Reding }; 638a12cf5c3SThierry Reding 639a12cf5c3SThierry Reding core3 { 640a12cf5c3SThierry Reding cpu = <&cpu0_3>; 641a12cf5c3SThierry Reding }; 642a12cf5c3SThierry Reding }; 643a12cf5c3SThierry Reding 644a12cf5c3SThierry Reding cluster1 { 645a12cf5c3SThierry Reding core0 { 646a12cf5c3SThierry Reding cpu = <&cpu1_0>; 647a12cf5c3SThierry Reding }; 648a12cf5c3SThierry Reding 649a12cf5c3SThierry Reding core1 { 650a12cf5c3SThierry Reding cpu = <&cpu1_1>; 651a12cf5c3SThierry Reding }; 652a12cf5c3SThierry Reding 653a12cf5c3SThierry Reding core2 { 654a12cf5c3SThierry Reding cpu = <&cpu1_2>; 655a12cf5c3SThierry Reding }; 656a12cf5c3SThierry Reding 657a12cf5c3SThierry Reding core3 { 658a12cf5c3SThierry Reding cpu = <&cpu1_3>; 659a12cf5c3SThierry Reding }; 660a12cf5c3SThierry Reding }; 661a12cf5c3SThierry Reding 662a12cf5c3SThierry Reding cluster2 { 663a12cf5c3SThierry Reding core0 { 664a12cf5c3SThierry Reding cpu = <&cpu2_0>; 665a12cf5c3SThierry Reding }; 666a12cf5c3SThierry Reding 667a12cf5c3SThierry Reding core1 { 668a12cf5c3SThierry Reding cpu = <&cpu2_1>; 669a12cf5c3SThierry Reding }; 670a12cf5c3SThierry Reding 671a12cf5c3SThierry Reding core2 { 672a12cf5c3SThierry Reding cpu = <&cpu2_2>; 673a12cf5c3SThierry Reding }; 674a12cf5c3SThierry Reding 675a12cf5c3SThierry Reding core3 { 676a12cf5c3SThierry Reding cpu = <&cpu2_3>; 677a12cf5c3SThierry Reding }; 678a12cf5c3SThierry Reding }; 679a12cf5c3SThierry Reding }; 680a12cf5c3SThierry Reding 681a12cf5c3SThierry Reding l2c0_0: l2-cache00 { 682a12cf5c3SThierry Reding cache-size = <262144>; 683a12cf5c3SThierry Reding cache-line-size = <64>; 684a12cf5c3SThierry Reding cache-sets = <512>; 685a12cf5c3SThierry Reding cache-unified; 686a12cf5c3SThierry Reding next-level-cache = <&l3c0>; 687a12cf5c3SThierry Reding }; 688a12cf5c3SThierry Reding 689a12cf5c3SThierry Reding l2c0_1: l2-cache01 { 690a12cf5c3SThierry Reding cache-size = <262144>; 691a12cf5c3SThierry Reding cache-line-size = <64>; 692a12cf5c3SThierry Reding cache-sets = <512>; 693a12cf5c3SThierry Reding cache-unified; 694a12cf5c3SThierry Reding next-level-cache = <&l3c0>; 695a12cf5c3SThierry Reding }; 696a12cf5c3SThierry Reding 697a12cf5c3SThierry Reding l2c0_2: l2-cache02 { 698a12cf5c3SThierry Reding cache-size = <262144>; 699a12cf5c3SThierry Reding cache-line-size = <64>; 700a12cf5c3SThierry Reding cache-sets = <512>; 701a12cf5c3SThierry Reding cache-unified; 702a12cf5c3SThierry Reding next-level-cache = <&l3c0>; 703a12cf5c3SThierry Reding }; 704a12cf5c3SThierry Reding 705a12cf5c3SThierry Reding l2c0_3: l2-cache03 { 706a12cf5c3SThierry Reding cache-size = <262144>; 707a12cf5c3SThierry Reding cache-line-size = <64>; 708a12cf5c3SThierry Reding cache-sets = <512>; 709a12cf5c3SThierry Reding cache-unified; 710a12cf5c3SThierry Reding next-level-cache = <&l3c0>; 711a12cf5c3SThierry Reding }; 712a12cf5c3SThierry Reding 713a12cf5c3SThierry Reding l2c1_0: l2-cache10 { 714a12cf5c3SThierry Reding cache-size = <262144>; 715a12cf5c3SThierry Reding cache-line-size = <64>; 716a12cf5c3SThierry Reding cache-sets = <512>; 717a12cf5c3SThierry Reding cache-unified; 718a12cf5c3SThierry Reding next-level-cache = <&l3c1>; 719a12cf5c3SThierry Reding }; 720a12cf5c3SThierry Reding 721a12cf5c3SThierry Reding l2c1_1: l2-cache11 { 722a12cf5c3SThierry Reding cache-size = <262144>; 723a12cf5c3SThierry Reding cache-line-size = <64>; 724a12cf5c3SThierry Reding cache-sets = <512>; 725a12cf5c3SThierry Reding cache-unified; 726a12cf5c3SThierry Reding next-level-cache = <&l3c1>; 727a12cf5c3SThierry Reding }; 728a12cf5c3SThierry Reding 729a12cf5c3SThierry Reding l2c1_2: l2-cache12 { 730a12cf5c3SThierry Reding cache-size = <262144>; 731a12cf5c3SThierry Reding cache-line-size = <64>; 732a12cf5c3SThierry Reding cache-sets = <512>; 733a12cf5c3SThierry Reding cache-unified; 734a12cf5c3SThierry Reding next-level-cache = <&l3c1>; 735a12cf5c3SThierry Reding }; 736a12cf5c3SThierry Reding 737a12cf5c3SThierry Reding l2c1_3: l2-cache13 { 738a12cf5c3SThierry Reding cache-size = <262144>; 739a12cf5c3SThierry Reding cache-line-size = <64>; 740a12cf5c3SThierry Reding cache-sets = <512>; 741a12cf5c3SThierry Reding cache-unified; 742a12cf5c3SThierry Reding next-level-cache = <&l3c1>; 743a12cf5c3SThierry Reding }; 744a12cf5c3SThierry Reding 745a12cf5c3SThierry Reding l2c2_0: l2-cache20 { 746a12cf5c3SThierry Reding cache-size = <262144>; 747a12cf5c3SThierry Reding cache-line-size = <64>; 748a12cf5c3SThierry Reding cache-sets = <512>; 749a12cf5c3SThierry Reding cache-unified; 750a12cf5c3SThierry Reding next-level-cache = <&l3c2>; 751a12cf5c3SThierry Reding }; 752a12cf5c3SThierry Reding 753a12cf5c3SThierry Reding l2c2_1: l2-cache21 { 754a12cf5c3SThierry Reding cache-size = <262144>; 755a12cf5c3SThierry Reding cache-line-size = <64>; 756a12cf5c3SThierry Reding cache-sets = <512>; 757a12cf5c3SThierry Reding cache-unified; 758a12cf5c3SThierry Reding next-level-cache = <&l3c2>; 759a12cf5c3SThierry Reding }; 760a12cf5c3SThierry Reding 761a12cf5c3SThierry Reding l2c2_2: l2-cache22 { 762a12cf5c3SThierry Reding cache-size = <262144>; 763a12cf5c3SThierry Reding cache-line-size = <64>; 764a12cf5c3SThierry Reding cache-sets = <512>; 765a12cf5c3SThierry Reding cache-unified; 766a12cf5c3SThierry Reding next-level-cache = <&l3c2>; 767a12cf5c3SThierry Reding }; 768a12cf5c3SThierry Reding 769a12cf5c3SThierry Reding l2c2_3: l2-cache23 { 770a12cf5c3SThierry Reding cache-size = <262144>; 771a12cf5c3SThierry Reding cache-line-size = <64>; 772a12cf5c3SThierry Reding cache-sets = <512>; 773a12cf5c3SThierry Reding cache-unified; 774a12cf5c3SThierry Reding next-level-cache = <&l3c2>; 775a12cf5c3SThierry Reding }; 776a12cf5c3SThierry Reding 777a12cf5c3SThierry Reding l3c0: l3-cache0 { 778a12cf5c3SThierry Reding cache-size = <2097152>; 779a12cf5c3SThierry Reding cache-line-size = <64>; 780a12cf5c3SThierry Reding cache-sets = <2048>; 781a12cf5c3SThierry Reding }; 782a12cf5c3SThierry Reding 783a12cf5c3SThierry Reding l3c1: l3-cache1 { 784a12cf5c3SThierry Reding cache-size = <2097152>; 785a12cf5c3SThierry Reding cache-line-size = <64>; 786a12cf5c3SThierry Reding cache-sets = <2048>; 787a12cf5c3SThierry Reding }; 788a12cf5c3SThierry Reding 789a12cf5c3SThierry Reding l3c2: l3-cache2 { 790a12cf5c3SThierry Reding cache-size = <2097152>; 791a12cf5c3SThierry Reding cache-line-size = <64>; 792a12cf5c3SThierry Reding cache-sets = <2048>; 793a12cf5c3SThierry Reding }; 794a12cf5c3SThierry Reding }; 795a12cf5c3SThierry Reding 796a12cf5c3SThierry Reding pmu { 797a12cf5c3SThierry Reding compatible = "arm,cortex-a78-pmu"; 798a12cf5c3SThierry Reding interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 799a12cf5c3SThierry Reding status = "okay"; 80063944891SThierry Reding }; 80163944891SThierry Reding 80263944891SThierry Reding psci { 80363944891SThierry Reding compatible = "arm,psci-1.0"; 80463944891SThierry Reding status = "okay"; 80563944891SThierry Reding method = "smc"; 80663944891SThierry Reding }; 80763944891SThierry Reding 80806ad2ec4SMikko Perttunen tcu: serial { 80906ad2ec4SMikko Perttunen compatible = "nvidia,tegra234-tcu", "nvidia,tegra194-tcu"; 81006ad2ec4SMikko Perttunen mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 81106ad2ec4SMikko Perttunen <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 81206ad2ec4SMikko Perttunen mbox-names = "rx", "tx"; 81306ad2ec4SMikko Perttunen status = "disabled"; 81406ad2ec4SMikko Perttunen }; 81506ad2ec4SMikko Perttunen 81663944891SThierry Reding timer { 81763944891SThierry Reding compatible = "arm,armv8-timer"; 81863944891SThierry Reding interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 81963944891SThierry Reding <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 82063944891SThierry Reding <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 82163944891SThierry Reding <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 82263944891SThierry Reding interrupt-parent = <&gic>; 82363944891SThierry Reding always-on; 82463944891SThierry Reding }; 82563944891SThierry Reding}; 826