163944891SThierry Reding// SPDX-License-Identifier: GPL-2.0 263944891SThierry Reding 363944891SThierry Reding#include <dt-bindings/clock/tegra234-clock.h> 4699349e0SThierry Reding#include <dt-bindings/gpio/tegra234-gpio.h> 563944891SThierry Reding#include <dt-bindings/interrupt-controller/arm-gic.h> 663944891SThierry Reding#include <dt-bindings/mailbox/tegra186-hsp.h> 7eed280dfSThierry Reding#include <dt-bindings/memory/tegra234-mc.h> 8c71e1897SThierry Reding#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 9dc94a94dSSameer Pujar#include <dt-bindings/power/tegra234-powergate.h> 1063944891SThierry Reding#include <dt-bindings/reset/tegra234-reset.h> 1109d99078SThierry Reding#include <dt-bindings/thermal/tegra234-bpmp-thermal.h> 1263944891SThierry Reding 1363944891SThierry Reding/ { 1463944891SThierry Reding compatible = "nvidia,tegra234"; 1563944891SThierry Reding interrupt-parent = <&gic>; 1663944891SThierry Reding #address-cells = <2>; 1763944891SThierry Reding #size-cells = <2>; 1863944891SThierry Reding 1963944891SThierry Reding bus@0 { 2063944891SThierry Reding compatible = "simple-bus"; 2163944891SThierry Reding 222838cfddSThierry Reding #address-cells = <2>; 232838cfddSThierry Reding #size-cells = <2>; 244bb54c2cSThierry Reding ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; 2563944891SThierry Reding 2679ed18d9SThierry Reding misc@100000 { 2779ed18d9SThierry Reding compatible = "nvidia,tegra234-misc"; 2879ed18d9SThierry Reding reg = <0x0 0x00100000 0x0 0xf000>, 2979ed18d9SThierry Reding <0x0 0x0010f000 0x0 0x1000>; 3079ed18d9SThierry Reding status = "okay"; 3179ed18d9SThierry Reding }; 3279ed18d9SThierry Reding 3379ed18d9SThierry Reding timer@2080000 { 3479ed18d9SThierry Reding compatible = "nvidia,tegra234-timer"; 3579ed18d9SThierry Reding reg = <0x0 0x02080000 0x0 0x00121000>; 3679ed18d9SThierry Reding interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 3779ed18d9SThierry Reding <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 3879ed18d9SThierry Reding <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 3979ed18d9SThierry Reding <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 4079ed18d9SThierry Reding <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 4179ed18d9SThierry Reding <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 4279ed18d9SThierry Reding <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 4379ed18d9SThierry Reding <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 4479ed18d9SThierry Reding <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 4579ed18d9SThierry Reding <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 46*5b24c396SThierry Reding <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 47*5b24c396SThierry Reding <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 48*5b24c396SThierry Reding <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 49*5b24c396SThierry Reding <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 50*5b24c396SThierry Reding <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 51*5b24c396SThierry Reding <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>; 5279ed18d9SThierry Reding status = "okay"; 5379ed18d9SThierry Reding }; 5479ed18d9SThierry Reding 5579ed18d9SThierry Reding gpio: gpio@2200000 { 5679ed18d9SThierry Reding compatible = "nvidia,tegra234-gpio"; 5779ed18d9SThierry Reding reg-names = "security", "gpio"; 5879ed18d9SThierry Reding reg = <0x0 0x02200000 0x0 0x10000>, 5979ed18d9SThierry Reding <0x0 0x02210000 0x0 0x10000>; 6079ed18d9SThierry Reding interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 6179ed18d9SThierry Reding <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 6279ed18d9SThierry Reding <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 6379ed18d9SThierry Reding <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, 6479ed18d9SThierry Reding <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 6579ed18d9SThierry Reding <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 6679ed18d9SThierry Reding <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 6779ed18d9SThierry Reding <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 6879ed18d9SThierry Reding <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 6979ed18d9SThierry Reding <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 7079ed18d9SThierry Reding <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 7179ed18d9SThierry Reding <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 7279ed18d9SThierry Reding <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 7379ed18d9SThierry Reding <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 7479ed18d9SThierry Reding <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 7579ed18d9SThierry Reding <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 7679ed18d9SThierry Reding <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 7779ed18d9SThierry Reding <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 7879ed18d9SThierry Reding <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 7979ed18d9SThierry Reding <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 8079ed18d9SThierry Reding <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 8179ed18d9SThierry Reding <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 8279ed18d9SThierry Reding <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 8379ed18d9SThierry Reding <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 8479ed18d9SThierry Reding <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 8579ed18d9SThierry Reding <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 8679ed18d9SThierry Reding <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 8779ed18d9SThierry Reding <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 8879ed18d9SThierry Reding <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 8979ed18d9SThierry Reding <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 9079ed18d9SThierry Reding <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 9179ed18d9SThierry Reding <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 9279ed18d9SThierry Reding <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 9379ed18d9SThierry Reding <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 9479ed18d9SThierry Reding <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 9579ed18d9SThierry Reding <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 9679ed18d9SThierry Reding <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 9779ed18d9SThierry Reding <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 9879ed18d9SThierry Reding <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 9979ed18d9SThierry Reding <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 10079ed18d9SThierry Reding <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 10179ed18d9SThierry Reding <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 10279ed18d9SThierry Reding <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 10379ed18d9SThierry Reding <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 10479ed18d9SThierry Reding <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 10579ed18d9SThierry Reding <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 10679ed18d9SThierry Reding <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 10779ed18d9SThierry Reding <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 10879ed18d9SThierry Reding #interrupt-cells = <2>; 10979ed18d9SThierry Reding interrupt-controller; 11079ed18d9SThierry Reding #gpio-cells = <2>; 11179ed18d9SThierry Reding gpio-controller; 112282fde00SPrathamesh Shete gpio-ranges = <&pinmux 0 0 164>; 113282fde00SPrathamesh Shete }; 114282fde00SPrathamesh Shete 115282fde00SPrathamesh Shete pinmux: pinmux@2430000 { 116282fde00SPrathamesh Shete compatible = "nvidia,tegra234-pinmux"; 117282fde00SPrathamesh Shete reg = <0x0 0x2430000 0x0 0x19100>; 11879ed18d9SThierry Reding }; 11979ed18d9SThierry Reding 12060d2016aSAkhil R gpcdma: dma-controller@2600000 { 121f7b93a08SAkhil R compatible = "nvidia,tegra234-gpcdma", 12260d2016aSAkhil R "nvidia,tegra186-gpcdma"; 1232838cfddSThierry Reding reg = <0x0 0x2600000 0x0 0x210000>; 12460d2016aSAkhil R resets = <&bpmp TEGRA234_RESET_GPCDMA>; 12560d2016aSAkhil R reset-names = "gpcdma"; 126dd0be827SAkhil R interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 127dd0be827SAkhil R <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 12860d2016aSAkhil R <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 12960d2016aSAkhil R <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 13060d2016aSAkhil R <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 13160d2016aSAkhil R <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 13260d2016aSAkhil R <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 13360d2016aSAkhil R <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 13460d2016aSAkhil R <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 13560d2016aSAkhil R <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 13660d2016aSAkhil R <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 13760d2016aSAkhil R <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 13860d2016aSAkhil R <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 13960d2016aSAkhil R <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 14060d2016aSAkhil R <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 14160d2016aSAkhil R <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 14260d2016aSAkhil R <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 14360d2016aSAkhil R <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 14460d2016aSAkhil R <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 14560d2016aSAkhil R <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 14660d2016aSAkhil R <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 14760d2016aSAkhil R <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 14860d2016aSAkhil R <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 14960d2016aSAkhil R <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 15060d2016aSAkhil R <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 15160d2016aSAkhil R <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 15260d2016aSAkhil R <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 15360d2016aSAkhil R <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 15460d2016aSAkhil R <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 15560d2016aSAkhil R <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 15660d2016aSAkhil R <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 15760d2016aSAkhil R <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 15860d2016aSAkhil R #dma-cells = <1>; 15960d2016aSAkhil R iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 160dd0be827SAkhil R dma-channel-mask = <0xfffffffe>; 16160d2016aSAkhil R dma-coherent; 16260d2016aSAkhil R }; 16360d2016aSAkhil R 164dc94a94dSSameer Pujar aconnect@2900000 { 165dc94a94dSSameer Pujar compatible = "nvidia,tegra234-aconnect", 166dc94a94dSSameer Pujar "nvidia,tegra210-aconnect"; 167dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_APE>, 168dc94a94dSSameer Pujar <&bpmp TEGRA234_CLK_APB2APE>; 169dc94a94dSSameer Pujar clock-names = "ape", "apb2ape"; 170dc94a94dSSameer Pujar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_AUD>; 171dc94a94dSSameer Pujar status = "disabled"; 172dc94a94dSSameer Pujar 1732838cfddSThierry Reding #address-cells = <2>; 1742838cfddSThierry Reding #size-cells = <2>; 1752838cfddSThierry Reding ranges = <0x0 0x02900000 0x0 0x02900000 0x0 0x200000>; 1762838cfddSThierry Reding 177dc94a94dSSameer Pujar tegra_ahub: ahub@2900800 { 178dc94a94dSSameer Pujar compatible = "nvidia,tegra234-ahub"; 1792838cfddSThierry Reding reg = <0x0 0x02900800 0x0 0x800>; 180dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_AHUB>; 181dc94a94dSSameer Pujar clock-names = "ahub"; 182dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_AHUB>; 183e483fe34SSheetal assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 184e483fe34SSheetal assigned-clock-rates = <81600000>; 185dc94a94dSSameer Pujar status = "disabled"; 186dc94a94dSSameer Pujar 1872838cfddSThierry Reding #address-cells = <2>; 1882838cfddSThierry Reding #size-cells = <2>; 1892838cfddSThierry Reding ranges = <0x0 0x02900800 0x0 0x02900800 0x0 0x11800>; 1902838cfddSThierry Reding 191dc94a94dSSameer Pujar tegra_i2s1: i2s@2901000 { 192dc94a94dSSameer Pujar compatible = "nvidia,tegra234-i2s", 193dc94a94dSSameer Pujar "nvidia,tegra210-i2s"; 1942838cfddSThierry Reding reg = <0x0 0x2901000 0x0 0x100>; 195dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_I2S1>, 196dc94a94dSSameer Pujar <&bpmp TEGRA234_CLK_I2S1_SYNC_INPUT>; 197dc94a94dSSameer Pujar clock-names = "i2s", "sync_input"; 198dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_I2S1>; 199dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 200dc94a94dSSameer Pujar assigned-clock-rates = <1536000>; 201dc94a94dSSameer Pujar sound-name-prefix = "I2S1"; 202dc94a94dSSameer Pujar status = "disabled"; 203dc94a94dSSameer Pujar }; 204dc94a94dSSameer Pujar 205dc94a94dSSameer Pujar tegra_i2s2: i2s@2901100 { 206dc94a94dSSameer Pujar compatible = "nvidia,tegra234-i2s", 207dc94a94dSSameer Pujar "nvidia,tegra210-i2s"; 2082838cfddSThierry Reding reg = <0x0 0x2901100 0x0 0x100>; 209dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_I2S2>, 210dc94a94dSSameer Pujar <&bpmp TEGRA234_CLK_I2S2_SYNC_INPUT>; 211dc94a94dSSameer Pujar clock-names = "i2s", "sync_input"; 212dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_I2S2>; 213dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 214dc94a94dSSameer Pujar assigned-clock-rates = <1536000>; 215dc94a94dSSameer Pujar sound-name-prefix = "I2S2"; 216dc94a94dSSameer Pujar status = "disabled"; 217dc94a94dSSameer Pujar }; 218dc94a94dSSameer Pujar 219dc94a94dSSameer Pujar tegra_i2s3: i2s@2901200 { 220dc94a94dSSameer Pujar compatible = "nvidia,tegra234-i2s", 221dc94a94dSSameer Pujar "nvidia,tegra210-i2s"; 2222838cfddSThierry Reding reg = <0x0 0x2901200 0x0 0x100>; 223dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_I2S3>, 224dc94a94dSSameer Pujar <&bpmp TEGRA234_CLK_I2S3_SYNC_INPUT>; 225dc94a94dSSameer Pujar clock-names = "i2s", "sync_input"; 226dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_I2S3>; 227dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 228dc94a94dSSameer Pujar assigned-clock-rates = <1536000>; 229dc94a94dSSameer Pujar sound-name-prefix = "I2S3"; 230dc94a94dSSameer Pujar status = "disabled"; 231dc94a94dSSameer Pujar }; 232dc94a94dSSameer Pujar 233dc94a94dSSameer Pujar tegra_i2s4: i2s@2901300 { 234dc94a94dSSameer Pujar compatible = "nvidia,tegra234-i2s", 235dc94a94dSSameer Pujar "nvidia,tegra210-i2s"; 2362838cfddSThierry Reding reg = <0x0 0x2901300 0x0 0x100>; 237dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_I2S4>, 238dc94a94dSSameer Pujar <&bpmp TEGRA234_CLK_I2S4_SYNC_INPUT>; 239dc94a94dSSameer Pujar clock-names = "i2s", "sync_input"; 240dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_I2S4>; 241dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 242dc94a94dSSameer Pujar assigned-clock-rates = <1536000>; 243dc94a94dSSameer Pujar sound-name-prefix = "I2S4"; 244dc94a94dSSameer Pujar status = "disabled"; 245dc94a94dSSameer Pujar }; 246dc94a94dSSameer Pujar 247dc94a94dSSameer Pujar tegra_i2s5: i2s@2901400 { 248dc94a94dSSameer Pujar compatible = "nvidia,tegra234-i2s", 249dc94a94dSSameer Pujar "nvidia,tegra210-i2s"; 2502838cfddSThierry Reding reg = <0x0 0x2901400 0x0 0x100>; 251dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_I2S5>, 252dc94a94dSSameer Pujar <&bpmp TEGRA234_CLK_I2S5_SYNC_INPUT>; 253dc94a94dSSameer Pujar clock-names = "i2s", "sync_input"; 254dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_I2S5>; 255dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 256dc94a94dSSameer Pujar assigned-clock-rates = <1536000>; 257dc94a94dSSameer Pujar sound-name-prefix = "I2S5"; 258dc94a94dSSameer Pujar status = "disabled"; 259dc94a94dSSameer Pujar }; 260dc94a94dSSameer Pujar 261dc94a94dSSameer Pujar tegra_i2s6: i2s@2901500 { 262dc94a94dSSameer Pujar compatible = "nvidia,tegra234-i2s", 263dc94a94dSSameer Pujar "nvidia,tegra210-i2s"; 2642838cfddSThierry Reding reg = <0x0 0x2901500 0x0 0x100>; 265dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_I2S6>, 266dc94a94dSSameer Pujar <&bpmp TEGRA234_CLK_I2S6_SYNC_INPUT>; 267dc94a94dSSameer Pujar clock-names = "i2s", "sync_input"; 268dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_I2S6>; 269dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 270dc94a94dSSameer Pujar assigned-clock-rates = <1536000>; 271dc94a94dSSameer Pujar sound-name-prefix = "I2S6"; 272dc94a94dSSameer Pujar status = "disabled"; 273dc94a94dSSameer Pujar }; 274dc94a94dSSameer Pujar 275dc94a94dSSameer Pujar tegra_sfc1: sfc@2902000 { 276dc94a94dSSameer Pujar compatible = "nvidia,tegra234-sfc", 277dc94a94dSSameer Pujar "nvidia,tegra210-sfc"; 2782838cfddSThierry Reding reg = <0x0 0x2902000 0x0 0x200>; 279dc94a94dSSameer Pujar sound-name-prefix = "SFC1"; 280dc94a94dSSameer Pujar status = "disabled"; 281dc94a94dSSameer Pujar }; 282dc94a94dSSameer Pujar 283dc94a94dSSameer Pujar tegra_sfc2: sfc@2902200 { 284dc94a94dSSameer Pujar compatible = "nvidia,tegra234-sfc", 285dc94a94dSSameer Pujar "nvidia,tegra210-sfc"; 2862838cfddSThierry Reding reg = <0x0 0x2902200 0x0 0x200>; 287dc94a94dSSameer Pujar sound-name-prefix = "SFC2"; 288dc94a94dSSameer Pujar status = "disabled"; 289dc94a94dSSameer Pujar }; 290dc94a94dSSameer Pujar 291dc94a94dSSameer Pujar tegra_sfc3: sfc@2902400 { 292dc94a94dSSameer Pujar compatible = "nvidia,tegra234-sfc", 293dc94a94dSSameer Pujar "nvidia,tegra210-sfc"; 2942838cfddSThierry Reding reg = <0x0 0x2902400 0x0 0x200>; 295dc94a94dSSameer Pujar sound-name-prefix = "SFC3"; 296dc94a94dSSameer Pujar status = "disabled"; 297dc94a94dSSameer Pujar }; 298dc94a94dSSameer Pujar 299dc94a94dSSameer Pujar tegra_sfc4: sfc@2902600 { 300dc94a94dSSameer Pujar compatible = "nvidia,tegra234-sfc", 301dc94a94dSSameer Pujar "nvidia,tegra210-sfc"; 3022838cfddSThierry Reding reg = <0x0 0x2902600 0x0 0x200>; 303dc94a94dSSameer Pujar sound-name-prefix = "SFC4"; 304dc94a94dSSameer Pujar status = "disabled"; 305dc94a94dSSameer Pujar }; 306dc94a94dSSameer Pujar 307dc94a94dSSameer Pujar tegra_amx1: amx@2903000 { 308dc94a94dSSameer Pujar compatible = "nvidia,tegra234-amx", 309dc94a94dSSameer Pujar "nvidia,tegra194-amx"; 3102838cfddSThierry Reding reg = <0x0 0x2903000 0x0 0x100>; 311dc94a94dSSameer Pujar sound-name-prefix = "AMX1"; 312dc94a94dSSameer Pujar status = "disabled"; 313dc94a94dSSameer Pujar }; 314dc94a94dSSameer Pujar 315dc94a94dSSameer Pujar tegra_amx2: amx@2903100 { 316dc94a94dSSameer Pujar compatible = "nvidia,tegra234-amx", 317dc94a94dSSameer Pujar "nvidia,tegra194-amx"; 3182838cfddSThierry Reding reg = <0x0 0x2903100 0x0 0x100>; 319dc94a94dSSameer Pujar sound-name-prefix = "AMX2"; 320dc94a94dSSameer Pujar status = "disabled"; 321dc94a94dSSameer Pujar }; 322dc94a94dSSameer Pujar 323dc94a94dSSameer Pujar tegra_amx3: amx@2903200 { 324dc94a94dSSameer Pujar compatible = "nvidia,tegra234-amx", 325dc94a94dSSameer Pujar "nvidia,tegra194-amx"; 3262838cfddSThierry Reding reg = <0x0 0x2903200 0x0 0x100>; 327dc94a94dSSameer Pujar sound-name-prefix = "AMX3"; 328dc94a94dSSameer Pujar status = "disabled"; 329dc94a94dSSameer Pujar }; 330dc94a94dSSameer Pujar 331dc94a94dSSameer Pujar tegra_amx4: amx@2903300 { 332dc94a94dSSameer Pujar compatible = "nvidia,tegra234-amx", 333dc94a94dSSameer Pujar "nvidia,tegra194-amx"; 3342838cfddSThierry Reding reg = <0x0 0x2903300 0x0 0x100>; 335dc94a94dSSameer Pujar sound-name-prefix = "AMX4"; 336dc94a94dSSameer Pujar status = "disabled"; 337dc94a94dSSameer Pujar }; 338dc94a94dSSameer Pujar 339dc94a94dSSameer Pujar tegra_adx1: adx@2903800 { 340dc94a94dSSameer Pujar compatible = "nvidia,tegra234-adx", 341dc94a94dSSameer Pujar "nvidia,tegra210-adx"; 3422838cfddSThierry Reding reg = <0x0 0x2903800 0x0 0x100>; 343dc94a94dSSameer Pujar sound-name-prefix = "ADX1"; 344dc94a94dSSameer Pujar status = "disabled"; 345dc94a94dSSameer Pujar }; 346dc94a94dSSameer Pujar 347dc94a94dSSameer Pujar tegra_adx2: adx@2903900 { 348dc94a94dSSameer Pujar compatible = "nvidia,tegra234-adx", 349dc94a94dSSameer Pujar "nvidia,tegra210-adx"; 3502838cfddSThierry Reding reg = <0x0 0x2903900 0x0 0x100>; 351dc94a94dSSameer Pujar sound-name-prefix = "ADX2"; 352dc94a94dSSameer Pujar status = "disabled"; 353dc94a94dSSameer Pujar }; 354dc94a94dSSameer Pujar 355dc94a94dSSameer Pujar tegra_adx3: adx@2903a00 { 356dc94a94dSSameer Pujar compatible = "nvidia,tegra234-adx", 357dc94a94dSSameer Pujar "nvidia,tegra210-adx"; 3582838cfddSThierry Reding reg = <0x0 0x2903a00 0x0 0x100>; 359dc94a94dSSameer Pujar sound-name-prefix = "ADX3"; 360dc94a94dSSameer Pujar status = "disabled"; 361dc94a94dSSameer Pujar }; 362dc94a94dSSameer Pujar 363dc94a94dSSameer Pujar tegra_adx4: adx@2903b00 { 364dc94a94dSSameer Pujar compatible = "nvidia,tegra234-adx", 365dc94a94dSSameer Pujar "nvidia,tegra210-adx"; 3662838cfddSThierry Reding reg = <0x0 0x2903b00 0x0 0x100>; 367dc94a94dSSameer Pujar sound-name-prefix = "ADX4"; 368dc94a94dSSameer Pujar status = "disabled"; 369dc94a94dSSameer Pujar }; 370dc94a94dSSameer Pujar 371dc94a94dSSameer Pujar 372dc94a94dSSameer Pujar tegra_dmic1: dmic@2904000 { 373dc94a94dSSameer Pujar compatible = "nvidia,tegra234-dmic", 374dc94a94dSSameer Pujar "nvidia,tegra210-dmic"; 3752838cfddSThierry Reding reg = <0x0 0x2904000 0x0 0x100>; 376dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_DMIC1>; 377dc94a94dSSameer Pujar clock-names = "dmic"; 378dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_DMIC1>; 379dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 380dc94a94dSSameer Pujar assigned-clock-rates = <3072000>; 381dc94a94dSSameer Pujar sound-name-prefix = "DMIC1"; 382dc94a94dSSameer Pujar status = "disabled"; 383dc94a94dSSameer Pujar }; 384dc94a94dSSameer Pujar 385dc94a94dSSameer Pujar tegra_dmic2: dmic@2904100 { 386dc94a94dSSameer Pujar compatible = "nvidia,tegra234-dmic", 387dc94a94dSSameer Pujar "nvidia,tegra210-dmic"; 3882838cfddSThierry Reding reg = <0x0 0x2904100 0x0 0x100>; 389dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_DMIC2>; 390dc94a94dSSameer Pujar clock-names = "dmic"; 391dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_DMIC2>; 392dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 393dc94a94dSSameer Pujar assigned-clock-rates = <3072000>; 394dc94a94dSSameer Pujar sound-name-prefix = "DMIC2"; 395dc94a94dSSameer Pujar status = "disabled"; 396dc94a94dSSameer Pujar }; 397dc94a94dSSameer Pujar 398dc94a94dSSameer Pujar tegra_dmic3: dmic@2904200 { 399dc94a94dSSameer Pujar compatible = "nvidia,tegra234-dmic", 400dc94a94dSSameer Pujar "nvidia,tegra210-dmic"; 4012838cfddSThierry Reding reg = <0x0 0x2904200 0x0 0x100>; 402dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_DMIC3>; 403dc94a94dSSameer Pujar clock-names = "dmic"; 404dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_DMIC3>; 405dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 406dc94a94dSSameer Pujar assigned-clock-rates = <3072000>; 407dc94a94dSSameer Pujar sound-name-prefix = "DMIC3"; 408dc94a94dSSameer Pujar status = "disabled"; 409dc94a94dSSameer Pujar }; 410dc94a94dSSameer Pujar 411dc94a94dSSameer Pujar tegra_dmic4: dmic@2904300 { 412dc94a94dSSameer Pujar compatible = "nvidia,tegra234-dmic", 413dc94a94dSSameer Pujar "nvidia,tegra210-dmic"; 4142838cfddSThierry Reding reg = <0x0 0x2904300 0x0 0x100>; 415dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_DMIC4>; 416dc94a94dSSameer Pujar clock-names = "dmic"; 417dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_DMIC4>; 418dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 419dc94a94dSSameer Pujar assigned-clock-rates = <3072000>; 420dc94a94dSSameer Pujar sound-name-prefix = "DMIC4"; 421dc94a94dSSameer Pujar status = "disabled"; 422dc94a94dSSameer Pujar }; 423dc94a94dSSameer Pujar 424dc94a94dSSameer Pujar tegra_dspk1: dspk@2905000 { 425dc94a94dSSameer Pujar compatible = "nvidia,tegra234-dspk", 426dc94a94dSSameer Pujar "nvidia,tegra186-dspk"; 4272838cfddSThierry Reding reg = <0x0 0x2905000 0x0 0x100>; 428dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_DSPK1>; 429dc94a94dSSameer Pujar clock-names = "dspk"; 430dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_DSPK1>; 431dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 432dc94a94dSSameer Pujar assigned-clock-rates = <12288000>; 433dc94a94dSSameer Pujar sound-name-prefix = "DSPK1"; 434dc94a94dSSameer Pujar status = "disabled"; 435dc94a94dSSameer Pujar }; 436dc94a94dSSameer Pujar 437dc94a94dSSameer Pujar tegra_dspk2: dspk@2905100 { 438dc94a94dSSameer Pujar compatible = "nvidia,tegra234-dspk", 439dc94a94dSSameer Pujar "nvidia,tegra186-dspk"; 4402838cfddSThierry Reding reg = <0x0 0x2905100 0x0 0x100>; 441dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_DSPK2>; 442dc94a94dSSameer Pujar clock-names = "dspk"; 443dc94a94dSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_DSPK2>; 444dc94a94dSSameer Pujar assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 445dc94a94dSSameer Pujar assigned-clock-rates = <12288000>; 446dc94a94dSSameer Pujar sound-name-prefix = "DSPK2"; 447dc94a94dSSameer Pujar status = "disabled"; 448dc94a94dSSameer Pujar }; 449dc94a94dSSameer Pujar 4504b6a1b7cSSameer Pujar tegra_ope1: processing-engine@2908000 { 4514b6a1b7cSSameer Pujar compatible = "nvidia,tegra234-ope", 4524b6a1b7cSSameer Pujar "nvidia,tegra210-ope"; 4532838cfddSThierry Reding reg = <0x0 0x2908000 0x0 0x100>; 4544b6a1b7cSSameer Pujar sound-name-prefix = "OPE1"; 4554b6a1b7cSSameer Pujar status = "disabled"; 4564b6a1b7cSSameer Pujar 4572838cfddSThierry Reding #address-cells = <2>; 4582838cfddSThierry Reding #size-cells = <2>; 4592838cfddSThierry Reding ranges; 4602838cfddSThierry Reding 4614b6a1b7cSSameer Pujar equalizer@2908100 { 4624b6a1b7cSSameer Pujar compatible = "nvidia,tegra234-peq", 4634b6a1b7cSSameer Pujar "nvidia,tegra210-peq"; 4642838cfddSThierry Reding reg = <0x0 0x2908100 0x0 0x100>; 4654b6a1b7cSSameer Pujar }; 4664b6a1b7cSSameer Pujar 4674b6a1b7cSSameer Pujar dynamic-range-compressor@2908200 { 4684b6a1b7cSSameer Pujar compatible = "nvidia,tegra234-mbdrc", 4694b6a1b7cSSameer Pujar "nvidia,tegra210-mbdrc"; 4702838cfddSThierry Reding reg = <0x0 0x2908200 0x0 0x200>; 4714b6a1b7cSSameer Pujar }; 4724b6a1b7cSSameer Pujar }; 4734b6a1b7cSSameer Pujar 474dc94a94dSSameer Pujar tegra_mvc1: mvc@290a000 { 475dc94a94dSSameer Pujar compatible = "nvidia,tegra234-mvc", 476dc94a94dSSameer Pujar "nvidia,tegra210-mvc"; 4772838cfddSThierry Reding reg = <0x0 0x290a000 0x0 0x200>; 478dc94a94dSSameer Pujar sound-name-prefix = "MVC1"; 479dc94a94dSSameer Pujar status = "disabled"; 480dc94a94dSSameer Pujar }; 481dc94a94dSSameer Pujar 482dc94a94dSSameer Pujar tegra_mvc2: mvc@290a200 { 483dc94a94dSSameer Pujar compatible = "nvidia,tegra234-mvc", 484dc94a94dSSameer Pujar "nvidia,tegra210-mvc"; 4852838cfddSThierry Reding reg = <0x0 0x290a200 0x0 0x200>; 486dc94a94dSSameer Pujar sound-name-prefix = "MVC2"; 487dc94a94dSSameer Pujar status = "disabled"; 488dc94a94dSSameer Pujar }; 489dc94a94dSSameer Pujar 490dc94a94dSSameer Pujar tegra_amixer: amixer@290bb00 { 491dc94a94dSSameer Pujar compatible = "nvidia,tegra234-amixer", 492dc94a94dSSameer Pujar "nvidia,tegra210-amixer"; 4932838cfddSThierry Reding reg = <0x0 0x290bb00 0x0 0x800>; 494dc94a94dSSameer Pujar sound-name-prefix = "MIXER1"; 495dc94a94dSSameer Pujar status = "disabled"; 496dc94a94dSSameer Pujar }; 497dc94a94dSSameer Pujar 498dc94a94dSSameer Pujar tegra_admaif: admaif@290f000 { 499dc94a94dSSameer Pujar compatible = "nvidia,tegra234-admaif", 500dc94a94dSSameer Pujar "nvidia,tegra186-admaif"; 5012838cfddSThierry Reding reg = <0x0 0x0290f000 0x0 0x1000>; 502dc94a94dSSameer Pujar dmas = <&adma 1>, <&adma 1>, 503dc94a94dSSameer Pujar <&adma 2>, <&adma 2>, 504dc94a94dSSameer Pujar <&adma 3>, <&adma 3>, 505dc94a94dSSameer Pujar <&adma 4>, <&adma 4>, 506dc94a94dSSameer Pujar <&adma 5>, <&adma 5>, 507dc94a94dSSameer Pujar <&adma 6>, <&adma 6>, 508dc94a94dSSameer Pujar <&adma 7>, <&adma 7>, 509dc94a94dSSameer Pujar <&adma 8>, <&adma 8>, 510dc94a94dSSameer Pujar <&adma 9>, <&adma 9>, 511dc94a94dSSameer Pujar <&adma 10>, <&adma 10>, 512dc94a94dSSameer Pujar <&adma 11>, <&adma 11>, 513dc94a94dSSameer Pujar <&adma 12>, <&adma 12>, 514dc94a94dSSameer Pujar <&adma 13>, <&adma 13>, 515dc94a94dSSameer Pujar <&adma 14>, <&adma 14>, 516dc94a94dSSameer Pujar <&adma 15>, <&adma 15>, 517dc94a94dSSameer Pujar <&adma 16>, <&adma 16>, 518dc94a94dSSameer Pujar <&adma 17>, <&adma 17>, 519dc94a94dSSameer Pujar <&adma 18>, <&adma 18>, 520dc94a94dSSameer Pujar <&adma 19>, <&adma 19>, 521dc94a94dSSameer Pujar <&adma 20>, <&adma 20>; 522dc94a94dSSameer Pujar dma-names = "rx1", "tx1", 523dc94a94dSSameer Pujar "rx2", "tx2", 524dc94a94dSSameer Pujar "rx3", "tx3", 525dc94a94dSSameer Pujar "rx4", "tx4", 526dc94a94dSSameer Pujar "rx5", "tx5", 527dc94a94dSSameer Pujar "rx6", "tx6", 528dc94a94dSSameer Pujar "rx7", "tx7", 529dc94a94dSSameer Pujar "rx8", "tx8", 530dc94a94dSSameer Pujar "rx9", "tx9", 531dc94a94dSSameer Pujar "rx10", "tx10", 532dc94a94dSSameer Pujar "rx11", "tx11", 533dc94a94dSSameer Pujar "rx12", "tx12", 534dc94a94dSSameer Pujar "rx13", "tx13", 535dc94a94dSSameer Pujar "rx14", "tx14", 536dc94a94dSSameer Pujar "rx15", "tx15", 537dc94a94dSSameer Pujar "rx16", "tx16", 538dc94a94dSSameer Pujar "rx17", "tx17", 539dc94a94dSSameer Pujar "rx18", "tx18", 540dc94a94dSSameer Pujar "rx19", "tx19", 541dc94a94dSSameer Pujar "rx20", "tx20"; 542dc94a94dSSameer Pujar interconnects = <&mc TEGRA234_MEMORY_CLIENT_APEDMAR &emc>, 543dc94a94dSSameer Pujar <&mc TEGRA234_MEMORY_CLIENT_APEDMAW &emc>; 544dc94a94dSSameer Pujar interconnect-names = "dma-mem", "write"; 545dc94a94dSSameer Pujar iommus = <&smmu_niso0 TEGRA234_SID_APE>; 546dc94a94dSSameer Pujar status = "disabled"; 547dc94a94dSSameer Pujar }; 54847a08153SSameer Pujar 54947a08153SSameer Pujar tegra_asrc: asrc@2910000 { 55047a08153SSameer Pujar compatible = "nvidia,tegra234-asrc", 55147a08153SSameer Pujar "nvidia,tegra186-asrc"; 5522838cfddSThierry Reding reg = <0x0 0x2910000 0x0 0x2000>; 55347a08153SSameer Pujar sound-name-prefix = "ASRC1"; 55447a08153SSameer Pujar status = "disabled"; 55547a08153SSameer Pujar }; 556dc94a94dSSameer Pujar }; 557dc94a94dSSameer Pujar 558dc94a94dSSameer Pujar adma: dma-controller@2930000 { 559dc94a94dSSameer Pujar compatible = "nvidia,tegra234-adma", 560dc94a94dSSameer Pujar "nvidia,tegra186-adma"; 5612838cfddSThierry Reding reg = <0x0 0x02930000 0x0 0x20000>; 562dc94a94dSSameer Pujar interrupt-parent = <&agic>; 563dc94a94dSSameer Pujar interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 564dc94a94dSSameer Pujar <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 565dc94a94dSSameer Pujar <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 566dc94a94dSSameer Pujar <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 567dc94a94dSSameer Pujar <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 568dc94a94dSSameer Pujar <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 569dc94a94dSSameer Pujar <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 570dc94a94dSSameer Pujar <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 571dc94a94dSSameer Pujar <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 572dc94a94dSSameer Pujar <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 573dc94a94dSSameer Pujar <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 574dc94a94dSSameer Pujar <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 575dc94a94dSSameer Pujar <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 576dc94a94dSSameer Pujar <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 577dc94a94dSSameer Pujar <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 578dc94a94dSSameer Pujar <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 579dc94a94dSSameer Pujar <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 580dc94a94dSSameer Pujar <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 581dc94a94dSSameer Pujar <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 582dc94a94dSSameer Pujar <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 583dc94a94dSSameer Pujar <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 584dc94a94dSSameer Pujar <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 585dc94a94dSSameer Pujar <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 586dc94a94dSSameer Pujar <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 587dc94a94dSSameer Pujar <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 588dc94a94dSSameer Pujar <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 589dc94a94dSSameer Pujar <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 590dc94a94dSSameer Pujar <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 591dc94a94dSSameer Pujar <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 592dc94a94dSSameer Pujar <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 593dc94a94dSSameer Pujar <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 594dc94a94dSSameer Pujar <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 595dc94a94dSSameer Pujar #dma-cells = <1>; 596dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_AHUB>; 597dc94a94dSSameer Pujar clock-names = "d_audio"; 598dc94a94dSSameer Pujar status = "disabled"; 599dc94a94dSSameer Pujar }; 600dc94a94dSSameer Pujar 601dc94a94dSSameer Pujar agic: interrupt-controller@2a40000 { 602dc94a94dSSameer Pujar compatible = "nvidia,tegra234-agic", 603dc94a94dSSameer Pujar "nvidia,tegra210-agic"; 604dc94a94dSSameer Pujar #interrupt-cells = <3>; 605dc94a94dSSameer Pujar interrupt-controller; 6062838cfddSThierry Reding reg = <0x0 0x02a41000 0x0 0x1000>, 6072838cfddSThierry Reding <0x0 0x02a42000 0x0 0x2000>; 608dc94a94dSSameer Pujar interrupts = <GIC_SPI 145 609dc94a94dSSameer Pujar (GIC_CPU_MASK_SIMPLE(4) | 610dc94a94dSSameer Pujar IRQ_TYPE_LEVEL_HIGH)>; 611dc94a94dSSameer Pujar clocks = <&bpmp TEGRA234_CLK_APE>; 612dc94a94dSSameer Pujar clock-names = "clk"; 613dc94a94dSSameer Pujar status = "disabled"; 614dc94a94dSSameer Pujar }; 615dc94a94dSSameer Pujar }; 616dc94a94dSSameer Pujar 617eed280dfSThierry Reding mc: memory-controller@2c00000 { 618eed280dfSThierry Reding compatible = "nvidia,tegra234-mc"; 6192838cfddSThierry Reding reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */ 6202838cfddSThierry Reding <0x0 0x02c10000 0x0 0x10000>, /* MC Broadcast*/ 6212838cfddSThierry Reding <0x0 0x02c20000 0x0 0x10000>, /* MC0 */ 6222838cfddSThierry Reding <0x0 0x02c30000 0x0 0x10000>, /* MC1 */ 6232838cfddSThierry Reding <0x0 0x02c40000 0x0 0x10000>, /* MC2 */ 6242838cfddSThierry Reding <0x0 0x02c50000 0x0 0x10000>, /* MC3 */ 6252838cfddSThierry Reding <0x0 0x02b80000 0x0 0x10000>, /* MC4 */ 6262838cfddSThierry Reding <0x0 0x02b90000 0x0 0x10000>, /* MC5 */ 6272838cfddSThierry Reding <0x0 0x02ba0000 0x0 0x10000>, /* MC6 */ 6282838cfddSThierry Reding <0x0 0x02bb0000 0x0 0x10000>, /* MC7 */ 6292838cfddSThierry Reding <0x0 0x01700000 0x0 0x10000>, /* MC8 */ 6302838cfddSThierry Reding <0x0 0x01710000 0x0 0x10000>, /* MC9 */ 6312838cfddSThierry Reding <0x0 0x01720000 0x0 0x10000>, /* MC10 */ 6322838cfddSThierry Reding <0x0 0x01730000 0x0 0x10000>, /* MC11 */ 6332838cfddSThierry Reding <0x0 0x01740000 0x0 0x10000>, /* MC12 */ 6342838cfddSThierry Reding <0x0 0x01750000 0x0 0x10000>, /* MC13 */ 6352838cfddSThierry Reding <0x0 0x01760000 0x0 0x10000>, /* MC14 */ 6362838cfddSThierry Reding <0x0 0x01770000 0x0 0x10000>; /* MC15 */ 637000b99e5SAshish Mhetre reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3", 638000b99e5SAshish Mhetre "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", 639000b99e5SAshish Mhetre "ch11", "ch12", "ch13", "ch14", "ch15"; 640eed280dfSThierry Reding interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 641eed280dfSThierry Reding #interconnect-cells = <1>; 642eed280dfSThierry Reding status = "okay"; 643eed280dfSThierry Reding 644eed280dfSThierry Reding #address-cells = <2>; 645eed280dfSThierry Reding #size-cells = <2>; 6462838cfddSThierry Reding ranges = <0x0 0x01700000 0x0 0x01700000 0x0 0x100000>, 6472838cfddSThierry Reding <0x0 0x02b80000 0x0 0x02b80000 0x0 0x040000>, 6482838cfddSThierry Reding <0x0 0x02c00000 0x0 0x02c00000 0x0 0x100000>; 649eed280dfSThierry Reding 650eed280dfSThierry Reding /* 651eed280dfSThierry Reding * Bit 39 of addresses passing through the memory 652eed280dfSThierry Reding * controller selects the XBAR format used when memory 653eed280dfSThierry Reding * is accessed. This is used to transparently access 654eed280dfSThierry Reding * memory in the XBAR format used by the discrete GPU 655eed280dfSThierry Reding * (bit 39 set) or Tegra (bit 39 clear). 656eed280dfSThierry Reding * 657eed280dfSThierry Reding * As a consequence, the operating system must ensure 658eed280dfSThierry Reding * that bit 39 is never used implicitly, for example 659eed280dfSThierry Reding * via an I/O virtual address mapping of an IOMMU. If 660eed280dfSThierry Reding * devices require access to the XBAR switch, their 661eed280dfSThierry Reding * drivers must set this bit explicitly. 662eed280dfSThierry Reding * 663eed280dfSThierry Reding * Limit the DMA range for memory clients to [38:0]. 664eed280dfSThierry Reding */ 6652838cfddSThierry Reding dma-ranges = <0x0 0x0 0x0 0x0 0x80 0x0>; 666eed280dfSThierry Reding 667eed280dfSThierry Reding emc: external-memory-controller@2c60000 { 668eed280dfSThierry Reding compatible = "nvidia,tegra234-emc"; 669eed280dfSThierry Reding reg = <0x0 0x02c60000 0x0 0x90000>, 670eed280dfSThierry Reding <0x0 0x01780000 0x0 0x80000>; 671eed280dfSThierry Reding interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 672eed280dfSThierry Reding clocks = <&bpmp TEGRA234_CLK_EMC>; 673eed280dfSThierry Reding clock-names = "emc"; 674eed280dfSThierry Reding status = "okay"; 675eed280dfSThierry Reding 676eed280dfSThierry Reding #interconnect-cells = <0>; 677eed280dfSThierry Reding 678eed280dfSThierry Reding nvidia,bpmp = <&bpmp>; 679eed280dfSThierry Reding }; 680eed280dfSThierry Reding }; 681eed280dfSThierry Reding 68263944891SThierry Reding uarta: serial@3100000 { 68363944891SThierry Reding compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart"; 6842838cfddSThierry Reding reg = <0x0 0x03100000 0x0 0x10000>; 68563944891SThierry Reding interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 68663944891SThierry Reding clocks = <&bpmp TEGRA234_CLK_UARTA>; 68763944891SThierry Reding resets = <&bpmp TEGRA234_RESET_UARTA>; 68863944891SThierry Reding status = "disabled"; 68963944891SThierry Reding }; 69063944891SThierry Reding 691940acdacSGautham Srinivasan uarte: serial@3140000 { 692940acdacSGautham Srinivasan compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart"; 693940acdacSGautham Srinivasan reg = <0x0 0x03140000 0x0 0x10000>; 694940acdacSGautham Srinivasan interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 695940acdacSGautham Srinivasan clocks = <&bpmp TEGRA234_CLK_UARTE>; 696940acdacSGautham Srinivasan resets = <&bpmp TEGRA234_RESET_UARTE>; 697940acdacSGautham Srinivasan status = "disabled"; 698940acdacSGautham Srinivasan }; 699940acdacSGautham Srinivasan 700156af9deSAkhil R gen1_i2c: i2c@3160000 { 701156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 7022838cfddSThierry Reding reg = <0x0 0x3160000 0x0 0x100>; 703156af9deSAkhil R status = "disabled"; 704156af9deSAkhil R interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 705260e8d42SJon Hunter #address-cells = <1>; 706260e8d42SJon Hunter #size-cells = <0>; 707156af9deSAkhil R clock-frequency = <400000>; 708156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C1 709156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 710156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C1>; 711156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 712156af9deSAkhil R clock-names = "div-clk", "parent"; 713156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C1>; 714156af9deSAkhil R reset-names = "i2c"; 7158e442805SAkhil R dmas = <&gpcdma 21>, <&gpcdma 21>; 7168e442805SAkhil R dma-names = "rx", "tx"; 717156af9deSAkhil R }; 718156af9deSAkhil R 719156af9deSAkhil R cam_i2c: i2c@3180000 { 720156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 7212838cfddSThierry Reding reg = <0x0 0x3180000 0x0 0x100>; 722156af9deSAkhil R interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 723260e8d42SJon Hunter #address-cells = <1>; 724260e8d42SJon Hunter #size-cells = <0>; 725156af9deSAkhil R status = "disabled"; 726156af9deSAkhil R clock-frequency = <400000>; 727156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C3 728156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 729156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C3>; 730156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 731156af9deSAkhil R clock-names = "div-clk", "parent"; 732156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C3>; 733156af9deSAkhil R reset-names = "i2c"; 7348e442805SAkhil R dmas = <&gpcdma 23>, <&gpcdma 23>; 7358e442805SAkhil R dma-names = "rx", "tx"; 736156af9deSAkhil R }; 737156af9deSAkhil R 738156af9deSAkhil R dp_aux_ch1_i2c: i2c@3190000 { 739156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 7402838cfddSThierry Reding reg = <0x0 0x3190000 0x0 0x100>; 741156af9deSAkhil R interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 742260e8d42SJon Hunter #address-cells = <1>; 743260e8d42SJon Hunter #size-cells = <0>; 744156af9deSAkhil R status = "disabled"; 745156af9deSAkhil R clock-frequency = <100000>; 746156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C4 747156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 748156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C4>; 749156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 750156af9deSAkhil R clock-names = "div-clk", "parent"; 751156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C4>; 752156af9deSAkhil R reset-names = "i2c"; 7538e442805SAkhil R dmas = <&gpcdma 26>, <&gpcdma 26>; 7548e442805SAkhil R dma-names = "rx", "tx"; 755156af9deSAkhil R }; 756156af9deSAkhil R 757156af9deSAkhil R dp_aux_ch0_i2c: i2c@31b0000 { 758156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 7592838cfddSThierry Reding reg = <0x0 0x31b0000 0x0 0x100>; 760156af9deSAkhil R interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 761260e8d42SJon Hunter #address-cells = <1>; 762260e8d42SJon Hunter #size-cells = <0>; 763156af9deSAkhil R status = "disabled"; 764156af9deSAkhil R clock-frequency = <100000>; 765156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C6 766156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 767156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C6>; 768156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 769156af9deSAkhil R clock-names = "div-clk", "parent"; 770156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C6>; 771156af9deSAkhil R reset-names = "i2c"; 7728e442805SAkhil R dmas = <&gpcdma 30>, <&gpcdma 30>; 7738e442805SAkhil R dma-names = "rx", "tx"; 774156af9deSAkhil R }; 775156af9deSAkhil R 776156af9deSAkhil R dp_aux_ch2_i2c: i2c@31c0000 { 777156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 7782838cfddSThierry Reding reg = <0x0 0x31c0000 0x0 0x100>; 779156af9deSAkhil R interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 780260e8d42SJon Hunter #address-cells = <1>; 781260e8d42SJon Hunter #size-cells = <0>; 782156af9deSAkhil R status = "disabled"; 783156af9deSAkhil R clock-frequency = <100000>; 784156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C7 785156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 786156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C7>; 787156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 788156af9deSAkhil R clock-names = "div-clk", "parent"; 789156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C7>; 790156af9deSAkhil R reset-names = "i2c"; 7918e442805SAkhil R dmas = <&gpcdma 27>, <&gpcdma 27>; 7928e442805SAkhil R dma-names = "rx", "tx"; 793156af9deSAkhil R }; 794156af9deSAkhil R 7951bbba854SJon Hunter uarti: serial@31d0000 { 7961bbba854SJon Hunter compatible = "arm,sbsa-uart"; 7972838cfddSThierry Reding reg = <0x0 0x31d0000 0x0 0x10000>; 7981bbba854SJon Hunter interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; 7991bbba854SJon Hunter status = "disabled"; 8001bbba854SJon Hunter }; 8011bbba854SJon Hunter 802156af9deSAkhil R dp_aux_ch3_i2c: i2c@31e0000 { 803156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 8042838cfddSThierry Reding reg = <0x0 0x31e0000 0x0 0x100>; 805156af9deSAkhil R interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 806260e8d42SJon Hunter #address-cells = <1>; 807260e8d42SJon Hunter #size-cells = <0>; 808156af9deSAkhil R status = "disabled"; 809156af9deSAkhil R clock-frequency = <100000>; 810156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C9 811156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 812156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C9>; 813156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 814156af9deSAkhil R clock-names = "div-clk", "parent"; 815156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C9>; 816156af9deSAkhil R reset-names = "i2c"; 8178e442805SAkhil R dmas = <&gpcdma 31>, <&gpcdma 31>; 8188e442805SAkhil R dma-names = "rx", "tx"; 819156af9deSAkhil R }; 820156af9deSAkhil R 821bb9667d8SGautham Srinivasan spi@3210000 { 822bb9667d8SGautham Srinivasan compatible = "nvidia,tegra210-spi"; 823bb9667d8SGautham Srinivasan reg = <0x0 0x03210000 0x0 0x1000>; 824bb9667d8SGautham Srinivasan interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 825bb9667d8SGautham Srinivasan #address-cells = <1>; 826bb9667d8SGautham Srinivasan #size-cells = <0>; 827bb9667d8SGautham Srinivasan clocks = <&bpmp TEGRA234_CLK_SPI1>; 828bb9667d8SGautham Srinivasan assigned-clocks = <&bpmp TEGRA234_CLK_SPI1>; 829bb9667d8SGautham Srinivasan assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 830bb9667d8SGautham Srinivasan clock-names = "spi"; 831bb9667d8SGautham Srinivasan iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 832bb9667d8SGautham Srinivasan resets = <&bpmp TEGRA234_RESET_SPI1>; 833bb9667d8SGautham Srinivasan reset-names = "spi"; 834bb9667d8SGautham Srinivasan dmas = <&gpcdma 15>, <&gpcdma 15>; 835bb9667d8SGautham Srinivasan dma-names = "rx", "tx"; 836bb9667d8SGautham Srinivasan dma-coherent; 837bb9667d8SGautham Srinivasan status = "disabled"; 838bb9667d8SGautham Srinivasan }; 839bb9667d8SGautham Srinivasan 840bb9667d8SGautham Srinivasan spi@3230000 { 841bb9667d8SGautham Srinivasan compatible = "nvidia,tegra210-spi"; 842bb9667d8SGautham Srinivasan reg = <0x0 0x03230000 0x0 0x1000>; 843bb9667d8SGautham Srinivasan interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 844bb9667d8SGautham Srinivasan #address-cells = <1>; 845bb9667d8SGautham Srinivasan #size-cells = <0>; 846bb9667d8SGautham Srinivasan clocks = <&bpmp TEGRA234_CLK_SPI3>; 847bb9667d8SGautham Srinivasan clock-names = "spi"; 848bb9667d8SGautham Srinivasan iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 849bb9667d8SGautham Srinivasan assigned-clocks = <&bpmp TEGRA234_CLK_SPI3>; 850bb9667d8SGautham Srinivasan assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 851bb9667d8SGautham Srinivasan resets = <&bpmp TEGRA234_RESET_SPI3>; 852bb9667d8SGautham Srinivasan reset-names = "spi"; 853bb9667d8SGautham Srinivasan dmas = <&gpcdma 17>, <&gpcdma 17>; 854bb9667d8SGautham Srinivasan dma-names = "rx", "tx"; 855bb9667d8SGautham Srinivasan dma-coherent; 856bb9667d8SGautham Srinivasan status = "disabled"; 857bb9667d8SGautham Srinivasan }; 858bb9667d8SGautham Srinivasan 85971f69ffaSAshish Singhal spi@3270000 { 86071f69ffaSAshish Singhal compatible = "nvidia,tegra234-qspi"; 8612838cfddSThierry Reding reg = <0x0 0x3270000 0x0 0x1000>; 86271f69ffaSAshish Singhal interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 86371f69ffaSAshish Singhal #address-cells = <1>; 86471f69ffaSAshish Singhal #size-cells = <0>; 86571f69ffaSAshish Singhal clocks = <&bpmp TEGRA234_CLK_QSPI0_2X_PM>, 86671f69ffaSAshish Singhal <&bpmp TEGRA234_CLK_QSPI0_PM>; 86771f69ffaSAshish Singhal clock-names = "qspi", "qspi_out"; 86871f69ffaSAshish Singhal resets = <&bpmp TEGRA234_RESET_QSPI0>; 86971f69ffaSAshish Singhal status = "disabled"; 87071f69ffaSAshish Singhal }; 87171f69ffaSAshish Singhal 8725e69088dSAkhil R pwm1: pwm@3280000 { 8732566d28cSJon Hunter compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 8742838cfddSThierry Reding reg = <0x0 0x3280000 0x0 0x10000>; 8755e69088dSAkhil R clocks = <&bpmp TEGRA234_CLK_PWM1>; 8765e69088dSAkhil R resets = <&bpmp TEGRA234_RESET_PWM1>; 8775e69088dSAkhil R reset-names = "pwm"; 8785e69088dSAkhil R status = "disabled"; 8795e69088dSAkhil R #pwm-cells = <2>; 8805e69088dSAkhil R }; 8815e69088dSAkhil R 8822566d28cSJon Hunter pwm2: pwm@3290000 { 8832566d28cSJon Hunter compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 8842838cfddSThierry Reding reg = <0x0 0x3290000 0x0 0x10000>; 8852566d28cSJon Hunter clocks = <&bpmp TEGRA234_CLK_PWM2>; 8862566d28cSJon Hunter resets = <&bpmp TEGRA234_RESET_PWM2>; 8872566d28cSJon Hunter reset-names = "pwm"; 8882566d28cSJon Hunter status = "disabled"; 8892566d28cSJon Hunter #pwm-cells = <2>; 8902566d28cSJon Hunter }; 8912566d28cSJon Hunter 8922566d28cSJon Hunter pwm3: pwm@32a0000 { 8932566d28cSJon Hunter compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 8942838cfddSThierry Reding reg = <0x0 0x32a0000 0x0 0x10000>; 8952566d28cSJon Hunter clocks = <&bpmp TEGRA234_CLK_PWM3>; 8962566d28cSJon Hunter resets = <&bpmp TEGRA234_RESET_PWM3>; 8972566d28cSJon Hunter reset-names = "pwm"; 8982566d28cSJon Hunter status = "disabled"; 8992566d28cSJon Hunter #pwm-cells = <2>; 9002566d28cSJon Hunter }; 9012566d28cSJon Hunter 9022566d28cSJon Hunter pwm5: pwm@32c0000 { 9032566d28cSJon Hunter compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 9042838cfddSThierry Reding reg = <0x0 0x32c0000 0x0 0x10000>; 9052566d28cSJon Hunter clocks = <&bpmp TEGRA234_CLK_PWM5>; 9062566d28cSJon Hunter resets = <&bpmp TEGRA234_RESET_PWM5>; 9072566d28cSJon Hunter reset-names = "pwm"; 9082566d28cSJon Hunter status = "disabled"; 9092566d28cSJon Hunter #pwm-cells = <2>; 9102566d28cSJon Hunter }; 9112566d28cSJon Hunter 9122566d28cSJon Hunter pwm6: pwm@32d0000 { 9132566d28cSJon Hunter compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 9142838cfddSThierry Reding reg = <0x0 0x32d0000 0x0 0x10000>; 9152566d28cSJon Hunter clocks = <&bpmp TEGRA234_CLK_PWM6>; 9162566d28cSJon Hunter resets = <&bpmp TEGRA234_RESET_PWM6>; 9172566d28cSJon Hunter reset-names = "pwm"; 9182566d28cSJon Hunter status = "disabled"; 9192566d28cSJon Hunter #pwm-cells = <2>; 9202566d28cSJon Hunter }; 9212566d28cSJon Hunter 9222566d28cSJon Hunter pwm7: pwm@32e0000 { 9232566d28cSJon Hunter compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 9242838cfddSThierry Reding reg = <0x0 0x32e0000 0x0 0x10000>; 9252566d28cSJon Hunter clocks = <&bpmp TEGRA234_CLK_PWM7>; 9262566d28cSJon Hunter resets = <&bpmp TEGRA234_RESET_PWM7>; 9272566d28cSJon Hunter reset-names = "pwm"; 9282566d28cSJon Hunter status = "disabled"; 9292566d28cSJon Hunter #pwm-cells = <2>; 9302566d28cSJon Hunter }; 9312566d28cSJon Hunter 9322566d28cSJon Hunter pwm8: pwm@32f0000 { 9332566d28cSJon Hunter compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 9342838cfddSThierry Reding reg = <0x0 0x32f0000 0x0 0x10000>; 9352566d28cSJon Hunter clocks = <&bpmp TEGRA234_CLK_PWM8>; 9362566d28cSJon Hunter resets = <&bpmp TEGRA234_RESET_PWM8>; 9372566d28cSJon Hunter reset-names = "pwm"; 9382566d28cSJon Hunter status = "disabled"; 9392566d28cSJon Hunter #pwm-cells = <2>; 9402566d28cSJon Hunter }; 9412566d28cSJon Hunter 94271f69ffaSAshish Singhal spi@3300000 { 94371f69ffaSAshish Singhal compatible = "nvidia,tegra234-qspi"; 9442838cfddSThierry Reding reg = <0x0 0x3300000 0x0 0x1000>; 94571f69ffaSAshish Singhal interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 94671f69ffaSAshish Singhal #address-cells = <1>; 94771f69ffaSAshish Singhal #size-cells = <0>; 94871f69ffaSAshish Singhal clocks = <&bpmp TEGRA234_CLK_QSPI1_2X_PM>, 94971f69ffaSAshish Singhal <&bpmp TEGRA234_CLK_QSPI1_PM>; 95071f69ffaSAshish Singhal clock-names = "qspi", "qspi_out"; 95171f69ffaSAshish Singhal resets = <&bpmp TEGRA234_RESET_QSPI1>; 95271f69ffaSAshish Singhal status = "disabled"; 95371f69ffaSAshish Singhal }; 95471f69ffaSAshish Singhal 955d71b893aSPrathamesh Shete mmc@3400000 { 956132b552cSThierry Reding compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci"; 9572838cfddSThierry Reding reg = <0x0 0x03400000 0x0 0x20000>; 958d71b893aSPrathamesh Shete interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 959d71b893aSPrathamesh Shete clocks = <&bpmp TEGRA234_CLK_SDMMC1>, 960d71b893aSPrathamesh Shete <&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>; 961d71b893aSPrathamesh Shete clock-names = "sdhci", "tmclk"; 962d71b893aSPrathamesh Shete assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC1>, 963d71b893aSPrathamesh Shete <&bpmp TEGRA234_CLK_PLLC4_MUXED>; 964d71b893aSPrathamesh Shete assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4_MUXED>, 965d71b893aSPrathamesh Shete <&bpmp TEGRA234_CLK_PLLC4_VCO_DIV2>; 966d71b893aSPrathamesh Shete resets = <&bpmp TEGRA234_RESET_SDMMC1>; 967d71b893aSPrathamesh Shete reset-names = "sdhci"; 968d71b893aSPrathamesh Shete interconnects = <&mc TEGRA234_MEMORY_CLIENT_SDMMCRA &emc>, 969d71b893aSPrathamesh Shete <&mc TEGRA234_MEMORY_CLIENT_SDMMCWA &emc>; 970d71b893aSPrathamesh Shete interconnect-names = "dma-mem", "write"; 971d71b893aSPrathamesh Shete iommus = <&smmu_niso1 TEGRA234_SID_SDMMC1A>; 972d71b893aSPrathamesh Shete pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 973d71b893aSPrathamesh Shete pinctrl-0 = <&sdmmc1_3v3>; 974d71b893aSPrathamesh Shete pinctrl-1 = <&sdmmc1_1v8>; 975d71b893aSPrathamesh Shete nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 976d71b893aSPrathamesh Shete nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x07>; 977d71b893aSPrathamesh Shete nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 978d71b893aSPrathamesh Shete nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 979d71b893aSPrathamesh Shete nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 980d71b893aSPrathamesh Shete nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 981d71b893aSPrathamesh Shete nvidia,default-tap = <14>; 982d71b893aSPrathamesh Shete nvidia,default-trim = <0x8>; 983d71b893aSPrathamesh Shete sd-uhs-sdr25; 984d71b893aSPrathamesh Shete sd-uhs-sdr50; 985d71b893aSPrathamesh Shete sd-uhs-ddr50; 986d71b893aSPrathamesh Shete sd-uhs-sdr104; 987d71b893aSPrathamesh Shete status = "disabled"; 988d71b893aSPrathamesh Shete }; 989d71b893aSPrathamesh Shete 99063944891SThierry Reding mmc@3460000 { 99163944891SThierry Reding compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci"; 9922838cfddSThierry Reding reg = <0x0 0x03460000 0x0 0x20000>; 99363944891SThierry Reding interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 994e086d82dSMikko Perttunen clocks = <&bpmp TEGRA234_CLK_SDMMC4>, 995e086d82dSMikko Perttunen <&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>; 996e086d82dSMikko Perttunen clock-names = "sdhci", "tmclk"; 997e086d82dSMikko Perttunen assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC4>, 998e086d82dSMikko Perttunen <&bpmp TEGRA234_CLK_PLLC4>; 999e086d82dSMikko Perttunen assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4>; 100063944891SThierry Reding resets = <&bpmp TEGRA234_RESET_SDMMC4>; 100163944891SThierry Reding reset-names = "sdhci"; 10026de481e5SThierry Reding interconnects = <&mc TEGRA234_MEMORY_CLIENT_SDMMCRAB &emc>, 10036de481e5SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_SDMMCWAB &emc>; 10046de481e5SThierry Reding interconnect-names = "dma-mem", "write"; 10055710e16aSThierry Reding iommus = <&smmu_niso1 TEGRA234_SID_SDMMC4>; 1006e086d82dSMikko Perttunen nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 1007e086d82dSMikko Perttunen nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 1008e086d82dSMikko Perttunen nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 1009e086d82dSMikko Perttunen nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; 1010e086d82dSMikko Perttunen nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 1011e086d82dSMikko Perttunen nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>; 1012e086d82dSMikko Perttunen nvidia,default-tap = <0x8>; 1013e086d82dSMikko Perttunen nvidia,default-trim = <0x14>; 1014e086d82dSMikko Perttunen nvidia,dqs-trim = <40>; 1015e086d82dSMikko Perttunen supports-cqe; 101663944891SThierry Reding status = "disabled"; 101763944891SThierry Reding }; 101863944891SThierry Reding 1019621e12a1SMohan Kumar hda@3510000 { 1020b2fbcbe1SThierry Reding compatible = "nvidia,tegra234-hda"; 10212838cfddSThierry Reding reg = <0x0 0x3510000 0x0 0x10000>; 1022621e12a1SMohan Kumar interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 1023621e12a1SMohan Kumar clocks = <&bpmp TEGRA234_CLK_AZA_BIT>, 1024621e12a1SMohan Kumar <&bpmp TEGRA234_CLK_AZA_2XBIT>; 1025621e12a1SMohan Kumar clock-names = "hda", "hda2codec_2x"; 1026621e12a1SMohan Kumar resets = <&bpmp TEGRA234_RESET_HDA>, 1027621e12a1SMohan Kumar <&bpmp TEGRA234_RESET_HDACODEC>; 1028621e12a1SMohan Kumar reset-names = "hda", "hda2codec_2x"; 1029621e12a1SMohan Kumar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_DISP>; 1030621e12a1SMohan Kumar interconnects = <&mc TEGRA234_MEMORY_CLIENT_HDAR &emc>, 1031621e12a1SMohan Kumar <&mc TEGRA234_MEMORY_CLIENT_HDAW &emc>; 1032621e12a1SMohan Kumar interconnect-names = "dma-mem", "write"; 1033af4c2773SMohan Kumar iommus = <&smmu_niso0 TEGRA234_SID_HDA>; 1034621e12a1SMohan Kumar status = "disabled"; 1035621e12a1SMohan Kumar }; 1036621e12a1SMohan Kumar 10376e505dd6SWayne Chang xusb_padctl: padctl@3520000 { 10386e505dd6SWayne Chang compatible = "nvidia,tegra234-xusb-padctl"; 10396e505dd6SWayne Chang reg = <0x0 0x03520000 0x0 0x20000>, 10406e505dd6SWayne Chang <0x0 0x03540000 0x0 0x10000>; 10416e505dd6SWayne Chang reg-names = "padctl", "ao"; 10426e505dd6SWayne Chang interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 10436e505dd6SWayne Chang 10446e505dd6SWayne Chang resets = <&bpmp TEGRA234_RESET_XUSB_PADCTL>; 10456e505dd6SWayne Chang reset-names = "padctl"; 10466e505dd6SWayne Chang 10476e505dd6SWayne Chang status = "disabled"; 10486e505dd6SWayne Chang 10496e505dd6SWayne Chang pads { 10506e505dd6SWayne Chang usb2 { 10516e505dd6SWayne Chang clocks = <&bpmp TEGRA234_CLK_USB2_TRK>; 10526e505dd6SWayne Chang clock-names = "trk"; 10536e505dd6SWayne Chang 10546e505dd6SWayne Chang lanes { 10556e505dd6SWayne Chang usb2-0 { 10566e505dd6SWayne Chang nvidia,function = "xusb"; 10576e505dd6SWayne Chang status = "disabled"; 10586e505dd6SWayne Chang #phy-cells = <0>; 10596e505dd6SWayne Chang }; 10606e505dd6SWayne Chang 10616e505dd6SWayne Chang usb2-1 { 10626e505dd6SWayne Chang nvidia,function = "xusb"; 10636e505dd6SWayne Chang status = "disabled"; 10646e505dd6SWayne Chang #phy-cells = <0>; 10656e505dd6SWayne Chang }; 10666e505dd6SWayne Chang 10676e505dd6SWayne Chang usb2-2 { 10686e505dd6SWayne Chang nvidia,function = "xusb"; 10696e505dd6SWayne Chang status = "disabled"; 10706e505dd6SWayne Chang #phy-cells = <0>; 10716e505dd6SWayne Chang }; 10726e505dd6SWayne Chang 10736e505dd6SWayne Chang usb2-3 { 10746e505dd6SWayne Chang nvidia,function = "xusb"; 10756e505dd6SWayne Chang status = "disabled"; 10766e505dd6SWayne Chang #phy-cells = <0>; 10776e505dd6SWayne Chang }; 10786e505dd6SWayne Chang }; 10796e505dd6SWayne Chang }; 10806e505dd6SWayne Chang 10816e505dd6SWayne Chang usb3 { 10826e505dd6SWayne Chang lanes { 10836e505dd6SWayne Chang usb3-0 { 10846e505dd6SWayne Chang nvidia,function = "xusb"; 10856e505dd6SWayne Chang status = "disabled"; 10866e505dd6SWayne Chang #phy-cells = <0>; 10876e505dd6SWayne Chang }; 10886e505dd6SWayne Chang 10896e505dd6SWayne Chang usb3-1 { 10906e505dd6SWayne Chang nvidia,function = "xusb"; 10916e505dd6SWayne Chang status = "disabled"; 10926e505dd6SWayne Chang #phy-cells = <0>; 10936e505dd6SWayne Chang }; 10946e505dd6SWayne Chang 10956e505dd6SWayne Chang usb3-2 { 10966e505dd6SWayne Chang nvidia,function = "xusb"; 10976e505dd6SWayne Chang status = "disabled"; 10986e505dd6SWayne Chang #phy-cells = <0>; 10996e505dd6SWayne Chang }; 11006e505dd6SWayne Chang 11016e505dd6SWayne Chang usb3-3 { 11026e505dd6SWayne Chang nvidia,function = "xusb"; 11036e505dd6SWayne Chang status = "disabled"; 11046e505dd6SWayne Chang #phy-cells = <0>; 11056e505dd6SWayne Chang }; 11066e505dd6SWayne Chang }; 11076e505dd6SWayne Chang }; 11086e505dd6SWayne Chang }; 11096e505dd6SWayne Chang 11106e505dd6SWayne Chang ports { 11116e505dd6SWayne Chang usb2-0 { 11126e505dd6SWayne Chang status = "disabled"; 11136e505dd6SWayne Chang }; 11146e505dd6SWayne Chang 11156e505dd6SWayne Chang usb2-1 { 11166e505dd6SWayne Chang status = "disabled"; 11176e505dd6SWayne Chang }; 11186e505dd6SWayne Chang 11196e505dd6SWayne Chang usb2-2 { 11206e505dd6SWayne Chang status = "disabled"; 11216e505dd6SWayne Chang }; 11226e505dd6SWayne Chang 11236e505dd6SWayne Chang usb2-3 { 11246e505dd6SWayne Chang status = "disabled"; 11256e505dd6SWayne Chang }; 11266e505dd6SWayne Chang 11276e505dd6SWayne Chang usb3-0 { 11286e505dd6SWayne Chang status = "disabled"; 11296e505dd6SWayne Chang }; 11306e505dd6SWayne Chang 11316e505dd6SWayne Chang usb3-1 { 11326e505dd6SWayne Chang status = "disabled"; 11336e505dd6SWayne Chang }; 11346e505dd6SWayne Chang 11356e505dd6SWayne Chang usb3-2 { 11366e505dd6SWayne Chang status = "disabled"; 11376e505dd6SWayne Chang }; 11386e505dd6SWayne Chang 11396e505dd6SWayne Chang usb3-3 { 11406e505dd6SWayne Chang status = "disabled"; 11416e505dd6SWayne Chang }; 11426e505dd6SWayne Chang }; 11436e505dd6SWayne Chang }; 11446e505dd6SWayne Chang 1145320e0a70SJon Hunter usb@3550000 { 1146320e0a70SJon Hunter compatible = "nvidia,tegra234-xudc"; 1147320e0a70SJon Hunter reg = <0x0 0x03550000 0x0 0x8000>, 1148320e0a70SJon Hunter <0x0 0x03558000 0x0 0x8000>; 1149320e0a70SJon Hunter reg-names = "base", "fpci"; 1150320e0a70SJon Hunter interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1151320e0a70SJon Hunter clocks = <&bpmp TEGRA234_CLK_XUSB_CORE_DEV>, 1152320e0a70SJon Hunter <&bpmp TEGRA234_CLK_XUSB_CORE_SS>, 1153320e0a70SJon Hunter <&bpmp TEGRA234_CLK_XUSB_SS>, 1154320e0a70SJon Hunter <&bpmp TEGRA234_CLK_XUSB_FS>; 1155320e0a70SJon Hunter clock-names = "dev", "ss", "ss_src", "fs_src"; 1156320e0a70SJon Hunter interconnects = <&mc TEGRA234_MEMORY_CLIENT_XUSB_DEVR &emc>, 1157320e0a70SJon Hunter <&mc TEGRA234_MEMORY_CLIENT_XUSB_DEVW &emc>; 1158320e0a70SJon Hunter interconnect-names = "dma-mem", "write"; 1159320e0a70SJon Hunter iommus = <&smmu_niso1 TEGRA234_SID_XUSB_DEV>; 1160320e0a70SJon Hunter power-domains = <&bpmp TEGRA234_POWER_DOMAIN_XUSBB>, 1161320e0a70SJon Hunter <&bpmp TEGRA234_POWER_DOMAIN_XUSBA>; 1162320e0a70SJon Hunter power-domain-names = "dev", "ss"; 1163320e0a70SJon Hunter nvidia,xusb-padctl = <&xusb_padctl>; 1164320e0a70SJon Hunter dma-coherent; 1165320e0a70SJon Hunter status = "disabled"; 1166320e0a70SJon Hunter }; 1167320e0a70SJon Hunter 11686e505dd6SWayne Chang usb@3610000 { 11696e505dd6SWayne Chang compatible = "nvidia,tegra234-xusb"; 11706e505dd6SWayne Chang reg = <0x0 0x03610000 0x0 0x40000>, 11716e505dd6SWayne Chang <0x0 0x03600000 0x0 0x10000>, 11726e505dd6SWayne Chang <0x0 0x03650000 0x0 0x10000>; 11736e505dd6SWayne Chang reg-names = "hcd", "fpci", "bar2"; 11746e505dd6SWayne Chang 11756e505dd6SWayne Chang interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 11766e505dd6SWayne Chang <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 11776e505dd6SWayne Chang 11786e505dd6SWayne Chang clocks = <&bpmp TEGRA234_CLK_XUSB_CORE_HOST>, 11796e505dd6SWayne Chang <&bpmp TEGRA234_CLK_XUSB_FALCON>, 11806e505dd6SWayne Chang <&bpmp TEGRA234_CLK_XUSB_CORE_SS>, 11816e505dd6SWayne Chang <&bpmp TEGRA234_CLK_XUSB_SS>, 11826e505dd6SWayne Chang <&bpmp TEGRA234_CLK_CLK_M>, 11836e505dd6SWayne Chang <&bpmp TEGRA234_CLK_XUSB_FS>, 11846e505dd6SWayne Chang <&bpmp TEGRA234_CLK_UTMIP_PLL>, 11856e505dd6SWayne Chang <&bpmp TEGRA234_CLK_CLK_M>, 11866e505dd6SWayne Chang <&bpmp TEGRA234_CLK_PLLE>; 11876e505dd6SWayne Chang clock-names = "xusb_host", "xusb_falcon_src", 11886e505dd6SWayne Chang "xusb_ss", "xusb_ss_src", "xusb_hs_src", 11896e505dd6SWayne Chang "xusb_fs_src", "pll_u_480m", "clk_m", 11906e505dd6SWayne Chang "pll_e"; 11916e505dd6SWayne Chang interconnects = <&mc TEGRA234_MEMORY_CLIENT_XUSB_HOSTR &emc>, 11926e505dd6SWayne Chang <&mc TEGRA234_MEMORY_CLIENT_XUSB_HOSTW &emc>; 11936e505dd6SWayne Chang interconnect-names = "dma-mem", "write"; 11946e505dd6SWayne Chang iommus = <&smmu_niso1 TEGRA234_SID_XUSB_HOST>; 11956e505dd6SWayne Chang 11966e505dd6SWayne Chang power-domains = <&bpmp TEGRA234_POWER_DOMAIN_XUSBC>, 11976e505dd6SWayne Chang <&bpmp TEGRA234_POWER_DOMAIN_XUSBA>; 11986e505dd6SWayne Chang power-domain-names = "xusb_host", "xusb_ss"; 11996e505dd6SWayne Chang 12006e505dd6SWayne Chang nvidia,xusb-padctl = <&xusb_padctl>; 12016e505dd6SWayne Chang dma-coherent; 12026e505dd6SWayne Chang status = "disabled"; 12036e505dd6SWayne Chang }; 12046e505dd6SWayne Chang 120563944891SThierry Reding fuse@3810000 { 120663944891SThierry Reding compatible = "nvidia,tegra234-efuse"; 12072838cfddSThierry Reding reg = <0x0 0x03810000 0x0 0x10000>; 120863944891SThierry Reding clocks = <&bpmp TEGRA234_CLK_FUSE>; 120963944891SThierry Reding clock-names = "fuse"; 121063944891SThierry Reding }; 121163944891SThierry Reding 121229662d62SDipen Patel hte_lic: hardware-timestamp@3aa0000 { 121329662d62SDipen Patel compatible = "nvidia,tegra234-gte-lic"; 121429662d62SDipen Patel reg = <0x0 0x3aa0000 0x0 0x10000>; 121529662d62SDipen Patel interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 121629662d62SDipen Patel nvidia,int-threshold = <1>; 121729662d62SDipen Patel #timestamp-cells = <1>; 121829662d62SDipen Patel }; 121929662d62SDipen Patel 122063944891SThierry Reding hsp_top0: hsp@3c00000 { 122163944891SThierry Reding compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; 12222838cfddSThierry Reding reg = <0x0 0x03c00000 0x0 0xa0000>; 122363944891SThierry Reding interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 122463944891SThierry Reding <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 122563944891SThierry Reding <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 122663944891SThierry Reding <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 122763944891SThierry Reding <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 122863944891SThierry Reding <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 122963944891SThierry Reding <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 123063944891SThierry Reding <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 123163944891SThierry Reding <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 123263944891SThierry Reding interrupt-names = "doorbell", "shared0", "shared1", "shared2", 123363944891SThierry Reding "shared3", "shared4", "shared5", "shared6", 123463944891SThierry Reding "shared7"; 123563944891SThierry Reding #mbox-cells = <2>; 123663944891SThierry Reding }; 123763944891SThierry Reding 123878159542SThierry Reding p2u_hsio_0: phy@3e00000 { 123978159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 12402838cfddSThierry Reding reg = <0x0 0x03e00000 0x0 0x10000>; 124178159542SThierry Reding reg-names = "ctl"; 124278159542SThierry Reding 124378159542SThierry Reding #phy-cells = <0>; 124478159542SThierry Reding }; 124578159542SThierry Reding 124678159542SThierry Reding p2u_hsio_1: phy@3e10000 { 124778159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 12482838cfddSThierry Reding reg = <0x0 0x03e10000 0x0 0x10000>; 124978159542SThierry Reding reg-names = "ctl"; 125078159542SThierry Reding 125178159542SThierry Reding #phy-cells = <0>; 125278159542SThierry Reding }; 125378159542SThierry Reding 125478159542SThierry Reding p2u_hsio_2: phy@3e20000 { 125578159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 12562838cfddSThierry Reding reg = <0x0 0x03e20000 0x0 0x10000>; 125778159542SThierry Reding reg-names = "ctl"; 125878159542SThierry Reding 125978159542SThierry Reding #phy-cells = <0>; 126078159542SThierry Reding }; 126178159542SThierry Reding 126278159542SThierry Reding p2u_hsio_3: phy@3e30000 { 126378159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 12642838cfddSThierry Reding reg = <0x0 0x03e30000 0x0 0x10000>; 126578159542SThierry Reding reg-names = "ctl"; 126678159542SThierry Reding 126778159542SThierry Reding #phy-cells = <0>; 126878159542SThierry Reding }; 126978159542SThierry Reding 127078159542SThierry Reding p2u_hsio_4: phy@3e40000 { 127178159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 12722838cfddSThierry Reding reg = <0x0 0x03e40000 0x0 0x10000>; 127378159542SThierry Reding reg-names = "ctl"; 127478159542SThierry Reding 127578159542SThierry Reding #phy-cells = <0>; 127678159542SThierry Reding }; 127778159542SThierry Reding 127878159542SThierry Reding p2u_hsio_5: phy@3e50000 { 127978159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 12802838cfddSThierry Reding reg = <0x0 0x03e50000 0x0 0x10000>; 128178159542SThierry Reding reg-names = "ctl"; 128278159542SThierry Reding 128378159542SThierry Reding #phy-cells = <0>; 128478159542SThierry Reding }; 128578159542SThierry Reding 128678159542SThierry Reding p2u_hsio_6: phy@3e60000 { 128778159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 12882838cfddSThierry Reding reg = <0x0 0x03e60000 0x0 0x10000>; 128978159542SThierry Reding reg-names = "ctl"; 129078159542SThierry Reding 129178159542SThierry Reding #phy-cells = <0>; 129278159542SThierry Reding }; 129378159542SThierry Reding 129478159542SThierry Reding p2u_hsio_7: phy@3e70000 { 129578159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 12962838cfddSThierry Reding reg = <0x0 0x03e70000 0x0 0x10000>; 129778159542SThierry Reding reg-names = "ctl"; 129878159542SThierry Reding 129978159542SThierry Reding #phy-cells = <0>; 130078159542SThierry Reding }; 130178159542SThierry Reding 130278159542SThierry Reding p2u_nvhs_0: phy@3e90000 { 130378159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 13042838cfddSThierry Reding reg = <0x0 0x03e90000 0x0 0x10000>; 130578159542SThierry Reding reg-names = "ctl"; 130678159542SThierry Reding 130778159542SThierry Reding #phy-cells = <0>; 130878159542SThierry Reding }; 130978159542SThierry Reding 131078159542SThierry Reding p2u_nvhs_1: phy@3ea0000 { 131178159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 13122838cfddSThierry Reding reg = <0x0 0x03ea0000 0x0 0x10000>; 131378159542SThierry Reding reg-names = "ctl"; 131478159542SThierry Reding 131578159542SThierry Reding #phy-cells = <0>; 131678159542SThierry Reding }; 131778159542SThierry Reding 131878159542SThierry Reding p2u_nvhs_2: phy@3eb0000 { 131978159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 13202838cfddSThierry Reding reg = <0x0 0x03eb0000 0x0 0x10000>; 132178159542SThierry Reding reg-names = "ctl"; 132278159542SThierry Reding 132378159542SThierry Reding #phy-cells = <0>; 132478159542SThierry Reding }; 132578159542SThierry Reding 132678159542SThierry Reding p2u_nvhs_3: phy@3ec0000 { 132778159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 13282838cfddSThierry Reding reg = <0x0 0x03ec0000 0x0 0x10000>; 132978159542SThierry Reding reg-names = "ctl"; 133078159542SThierry Reding 133178159542SThierry Reding #phy-cells = <0>; 133278159542SThierry Reding }; 133378159542SThierry Reding 133478159542SThierry Reding p2u_nvhs_4: phy@3ed0000 { 133578159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 13362838cfddSThierry Reding reg = <0x0 0x03ed0000 0x0 0x10000>; 133778159542SThierry Reding reg-names = "ctl"; 133878159542SThierry Reding 133978159542SThierry Reding #phy-cells = <0>; 134078159542SThierry Reding }; 134178159542SThierry Reding 134278159542SThierry Reding p2u_nvhs_5: phy@3ee0000 { 134378159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 13442838cfddSThierry Reding reg = <0x0 0x03ee0000 0x0 0x10000>; 134578159542SThierry Reding reg-names = "ctl"; 134678159542SThierry Reding 134778159542SThierry Reding #phy-cells = <0>; 134878159542SThierry Reding }; 134978159542SThierry Reding 135078159542SThierry Reding p2u_nvhs_6: phy@3ef0000 { 135178159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 13522838cfddSThierry Reding reg = <0x0 0x03ef0000 0x0 0x10000>; 135378159542SThierry Reding reg-names = "ctl"; 135478159542SThierry Reding 135578159542SThierry Reding #phy-cells = <0>; 135678159542SThierry Reding }; 135778159542SThierry Reding 135878159542SThierry Reding p2u_nvhs_7: phy@3f00000 { 135978159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 13602838cfddSThierry Reding reg = <0x0 0x03f00000 0x0 0x10000>; 136178159542SThierry Reding reg-names = "ctl"; 136278159542SThierry Reding 136378159542SThierry Reding #phy-cells = <0>; 136478159542SThierry Reding }; 136578159542SThierry Reding 136678159542SThierry Reding p2u_gbe_0: phy@3f20000 { 136778159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 13682838cfddSThierry Reding reg = <0x0 0x03f20000 0x0 0x10000>; 136978159542SThierry Reding reg-names = "ctl"; 137078159542SThierry Reding 137178159542SThierry Reding #phy-cells = <0>; 137278159542SThierry Reding }; 137378159542SThierry Reding 137478159542SThierry Reding p2u_gbe_1: phy@3f30000 { 137578159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 13762838cfddSThierry Reding reg = <0x0 0x03f30000 0x0 0x10000>; 137778159542SThierry Reding reg-names = "ctl"; 137878159542SThierry Reding 137978159542SThierry Reding #phy-cells = <0>; 138078159542SThierry Reding }; 138178159542SThierry Reding 138278159542SThierry Reding p2u_gbe_2: phy@3f40000 { 138378159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 13842838cfddSThierry Reding reg = <0x0 0x03f40000 0x0 0x10000>; 138578159542SThierry Reding reg-names = "ctl"; 138678159542SThierry Reding 138778159542SThierry Reding #phy-cells = <0>; 138878159542SThierry Reding }; 138978159542SThierry Reding 139078159542SThierry Reding p2u_gbe_3: phy@3f50000 { 139178159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 13922838cfddSThierry Reding reg = <0x0 0x03f50000 0x0 0x10000>; 139378159542SThierry Reding reg-names = "ctl"; 139478159542SThierry Reding 139578159542SThierry Reding #phy-cells = <0>; 139678159542SThierry Reding }; 139778159542SThierry Reding 139878159542SThierry Reding p2u_gbe_4: phy@3f60000 { 139978159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 14002838cfddSThierry Reding reg = <0x0 0x03f60000 0x0 0x10000>; 140178159542SThierry Reding reg-names = "ctl"; 140278159542SThierry Reding 140378159542SThierry Reding #phy-cells = <0>; 140478159542SThierry Reding }; 140578159542SThierry Reding 140678159542SThierry Reding p2u_gbe_5: phy@3f70000 { 140778159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 14082838cfddSThierry Reding reg = <0x0 0x03f70000 0x0 0x10000>; 140978159542SThierry Reding reg-names = "ctl"; 141078159542SThierry Reding 141178159542SThierry Reding #phy-cells = <0>; 141278159542SThierry Reding }; 141378159542SThierry Reding 141478159542SThierry Reding p2u_gbe_6: phy@3f80000 { 141578159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 14162838cfddSThierry Reding reg = <0x0 0x03f80000 0x0 0x10000>; 141778159542SThierry Reding reg-names = "ctl"; 141878159542SThierry Reding 141978159542SThierry Reding #phy-cells = <0>; 142078159542SThierry Reding }; 142178159542SThierry Reding 142278159542SThierry Reding p2u_gbe_7: phy@3f90000 { 142378159542SThierry Reding compatible = "nvidia,tegra234-p2u"; 14242838cfddSThierry Reding reg = <0x0 0x03f90000 0x0 0x10000>; 142578159542SThierry Reding reg-names = "ctl"; 142678159542SThierry Reding 142778159542SThierry Reding #phy-cells = <0>; 142878159542SThierry Reding }; 142978159542SThierry Reding 1430610cdf31SThierry Reding ethernet@6800000 { 1431610cdf31SThierry Reding compatible = "nvidia,tegra234-mgbe"; 14322838cfddSThierry Reding reg = <0x0 0x06800000 0x0 0x10000>, 14332838cfddSThierry Reding <0x0 0x06810000 0x0 0x10000>, 14342838cfddSThierry Reding <0x0 0x068a0000 0x0 0x10000>; 1435610cdf31SThierry Reding reg-names = "hypervisor", "mac", "xpcs"; 1436610cdf31SThierry Reding interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>; 1437610cdf31SThierry Reding interrupt-names = "common"; 1438610cdf31SThierry Reding clocks = <&bpmp TEGRA234_CLK_MGBE0_APP>, 1439610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE0_MAC>, 1440610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE0_MAC_DIVIDER>, 1441610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE0_PTP_REF>, 1442610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT_M>, 1443610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT>, 1444610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE0_TX>, 1445610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE0_EEE_PCS>, 1446610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_INPUT>, 1447610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_M>, 1448610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE0_RX_PCS>, 1449610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE0_TX_PCS>; 1450610cdf31SThierry Reding clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", 1451610cdf31SThierry Reding "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", 1452610cdf31SThierry Reding "rx-pcs", "tx-pcs"; 1453610cdf31SThierry Reding resets = <&bpmp TEGRA234_RESET_MGBE0_MAC>, 1454610cdf31SThierry Reding <&bpmp TEGRA234_RESET_MGBE0_PCS>; 1455610cdf31SThierry Reding reset-names = "mac", "pcs"; 1456610cdf31SThierry Reding interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEARD &emc>, 1457610cdf31SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_MGBEAWR &emc>; 1458610cdf31SThierry Reding interconnect-names = "dma-mem", "write"; 1459610cdf31SThierry Reding iommus = <&smmu_niso0 TEGRA234_SID_MGBE>; 1460610cdf31SThierry Reding power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEA>; 1461610cdf31SThierry Reding status = "disabled"; 1462610cdf31SThierry Reding }; 1463610cdf31SThierry Reding 1464610cdf31SThierry Reding ethernet@6900000 { 1465610cdf31SThierry Reding compatible = "nvidia,tegra234-mgbe"; 14662838cfddSThierry Reding reg = <0x0 0x06900000 0x0 0x10000>, 14672838cfddSThierry Reding <0x0 0x06910000 0x0 0x10000>, 14682838cfddSThierry Reding <0x0 0x069a0000 0x0 0x10000>; 1469610cdf31SThierry Reding reg-names = "hypervisor", "mac", "xpcs"; 1470610cdf31SThierry Reding interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>; 1471610cdf31SThierry Reding interrupt-names = "common"; 1472610cdf31SThierry Reding clocks = <&bpmp TEGRA234_CLK_MGBE1_APP>, 1473610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE1_MAC>, 1474610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE1_MAC_DIVIDER>, 1475610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE1_PTP_REF>, 1476610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE1_RX_INPUT_M>, 1477610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE1_RX_INPUT>, 1478610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE1_TX>, 1479610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE1_EEE_PCS>, 1480610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE1_RX_PCS_INPUT>, 1481610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE1_RX_PCS_M>, 1482610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE1_RX_PCS>, 1483610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE1_TX_PCS>; 1484610cdf31SThierry Reding clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", 1485610cdf31SThierry Reding "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", 1486610cdf31SThierry Reding "rx-pcs", "tx-pcs"; 1487610cdf31SThierry Reding resets = <&bpmp TEGRA234_RESET_MGBE1_MAC>, 1488610cdf31SThierry Reding <&bpmp TEGRA234_RESET_MGBE1_PCS>; 1489610cdf31SThierry Reding reset-names = "mac", "pcs"; 1490610cdf31SThierry Reding interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEBRD &emc>, 1491610cdf31SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_MGBEBWR &emc>; 1492610cdf31SThierry Reding interconnect-names = "dma-mem", "write"; 1493610cdf31SThierry Reding iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF1>; 1494610cdf31SThierry Reding power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEB>; 1495610cdf31SThierry Reding status = "disabled"; 1496610cdf31SThierry Reding }; 1497610cdf31SThierry Reding 1498610cdf31SThierry Reding ethernet@6a00000 { 1499610cdf31SThierry Reding compatible = "nvidia,tegra234-mgbe"; 15002838cfddSThierry Reding reg = <0x0 0x06a00000 0x0 0x10000>, 15012838cfddSThierry Reding <0x0 0x06a10000 0x0 0x10000>, 15022838cfddSThierry Reding <0x0 0x06aa0000 0x0 0x10000>; 1503610cdf31SThierry Reding reg-names = "hypervisor", "mac", "xpcs"; 1504610cdf31SThierry Reding interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>; 1505610cdf31SThierry Reding interrupt-names = "common"; 1506610cdf31SThierry Reding clocks = <&bpmp TEGRA234_CLK_MGBE2_APP>, 1507610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE2_MAC>, 1508610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE2_MAC_DIVIDER>, 1509610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE2_PTP_REF>, 1510610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE2_RX_INPUT_M>, 1511610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE2_RX_INPUT>, 1512610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE2_TX>, 1513610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE2_EEE_PCS>, 1514610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE2_RX_PCS_INPUT>, 1515610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE2_RX_PCS_M>, 1516610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE2_RX_PCS>, 1517610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE2_TX_PCS>; 1518610cdf31SThierry Reding clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", 1519610cdf31SThierry Reding "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", 1520610cdf31SThierry Reding "rx-pcs", "tx-pcs"; 1521610cdf31SThierry Reding resets = <&bpmp TEGRA234_RESET_MGBE2_MAC>, 1522610cdf31SThierry Reding <&bpmp TEGRA234_RESET_MGBE2_PCS>; 1523610cdf31SThierry Reding reset-names = "mac", "pcs"; 1524610cdf31SThierry Reding interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBECRD &emc>, 1525610cdf31SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_MGBECWR &emc>; 1526610cdf31SThierry Reding interconnect-names = "dma-mem", "write"; 1527610cdf31SThierry Reding iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF2>; 1528610cdf31SThierry Reding power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEC>; 1529610cdf31SThierry Reding status = "disabled"; 1530610cdf31SThierry Reding }; 1531610cdf31SThierry Reding 1532610cdf31SThierry Reding ethernet@6b00000 { 1533610cdf31SThierry Reding compatible = "nvidia,tegra234-mgbe"; 15342838cfddSThierry Reding reg = <0x0 0x06b00000 0x0 0x10000>, 15352838cfddSThierry Reding <0x0 0x06b10000 0x0 0x10000>, 15362838cfddSThierry Reding <0x0 0x06ba0000 0x0 0x10000>; 1537610cdf31SThierry Reding reg-names = "hypervisor", "mac", "xpcs"; 1538610cdf31SThierry Reding interrupts = <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 1539610cdf31SThierry Reding interrupt-names = "common"; 1540610cdf31SThierry Reding clocks = <&bpmp TEGRA234_CLK_MGBE3_APP>, 1541610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE3_MAC>, 1542610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE3_MAC_DIVIDER>, 1543610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE3_PTP_REF>, 1544610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE3_RX_INPUT_M>, 1545610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE3_RX_INPUT>, 1546610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE3_TX>, 1547610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE3_EEE_PCS>, 1548610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE3_RX_PCS_INPUT>, 1549610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE3_RX_PCS_M>, 1550610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE3_RX_PCS>, 1551610cdf31SThierry Reding <&bpmp TEGRA234_CLK_MGBE3_TX_PCS>; 1552610cdf31SThierry Reding clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", 1553610cdf31SThierry Reding "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", 1554610cdf31SThierry Reding "rx-pcs", "tx-pcs"; 1555610cdf31SThierry Reding resets = <&bpmp TEGRA234_RESET_MGBE3_MAC>, 1556610cdf31SThierry Reding <&bpmp TEGRA234_RESET_MGBE3_PCS>; 1557610cdf31SThierry Reding reset-names = "mac", "pcs"; 1558610cdf31SThierry Reding interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEDRD &emc>, 1559610cdf31SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_MGBEDWR &emc>; 1560610cdf31SThierry Reding interconnect-names = "dma-mem", "write"; 1561610cdf31SThierry Reding iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF3>; 1562610cdf31SThierry Reding power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBED>; 1563610cdf31SThierry Reding status = "disabled"; 1564610cdf31SThierry Reding }; 1565610cdf31SThierry Reding 15665710e16aSThierry Reding smmu_niso1: iommu@8000000 { 15675710e16aSThierry Reding compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; 15682838cfddSThierry Reding reg = <0x0 0x8000000 0x0 0x1000000>, 15692838cfddSThierry Reding <0x0 0x7000000 0x0 0x1000000>; 15705710e16aSThierry Reding interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15715710e16aSThierry Reding <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, 15725710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15735710e16aSThierry Reding <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, 15745710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15755710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15765710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15775710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15785710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15795710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15805710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15815710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15825710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15835710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15845710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15855710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15865710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15875710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15885710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15895710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15905710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15915710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15925710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15935710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15945710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15955710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15965710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15975710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15985710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 15995710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16005710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16015710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16025710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16035710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16045710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16055710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16065710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16075710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16085710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16095710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16105710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16115710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16125710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16135710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16145710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16155710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16165710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16175710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16185710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16195710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16205710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16215710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16225710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16235710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16245710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16255710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16265710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16275710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16285710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16295710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16305710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16315710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16325710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16335710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16345710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16355710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16365710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16375710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16385710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16395710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16405710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16415710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16425710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16435710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16445710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16455710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16465710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16475710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16485710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16495710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16505710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16515710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16525710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16535710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16545710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16555710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16565710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16575710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16585710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16595710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16605710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16615710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16625710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16635710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16645710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16655710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16665710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16675710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16685710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16695710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16705710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16715710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16725710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16735710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16745710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16755710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16765710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16775710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16785710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16795710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16805710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16815710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16825710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16835710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16845710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16855710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16865710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16875710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16885710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16895710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16905710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16915710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16925710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16935710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16945710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16955710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16965710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16975710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16985710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 16995710e16aSThierry Reding <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 17005710e16aSThierry Reding stream-match-mask = <0x7f80>; 17015710e16aSThierry Reding #global-interrupts = <2>; 17025710e16aSThierry Reding #iommu-cells = <1>; 17035710e16aSThierry Reding 17045710e16aSThierry Reding nvidia,memory-controller = <&mc>; 17055710e16aSThierry Reding status = "okay"; 17065710e16aSThierry Reding }; 17075710e16aSThierry Reding 1708302e1540SSumit Gupta sce-fabric@b600000 { 1709302e1540SSumit Gupta compatible = "nvidia,tegra234-sce-fabric"; 17102838cfddSThierry Reding reg = <0x0 0xb600000 0x0 0x40000>; 1711302e1540SSumit Gupta interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 1712302e1540SSumit Gupta status = "okay"; 1713302e1540SSumit Gupta }; 1714302e1540SSumit Gupta 1715302e1540SSumit Gupta rce-fabric@be00000 { 1716302e1540SSumit Gupta compatible = "nvidia,tegra234-rce-fabric"; 17172838cfddSThierry Reding reg = <0x0 0xbe00000 0x0 0x40000>; 1718302e1540SSumit Gupta interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 1719302e1540SSumit Gupta status = "okay"; 1720302e1540SSumit Gupta }; 1721302e1540SSumit Gupta 172263944891SThierry Reding hsp_aon: hsp@c150000 { 172363944891SThierry Reding compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; 17242838cfddSThierry Reding reg = <0x0 0x0c150000 0x0 0x90000>; 172563944891SThierry Reding interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 172663944891SThierry Reding <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 172763944891SThierry Reding <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 172863944891SThierry Reding <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 172963944891SThierry Reding /* 173063944891SThierry Reding * Shared interrupt 0 is routed only to AON/SPE, so 173163944891SThierry Reding * we only have 4 shared interrupts for the CCPLEX. 173263944891SThierry Reding */ 173363944891SThierry Reding interrupt-names = "shared1", "shared2", "shared3", "shared4"; 173463944891SThierry Reding #mbox-cells = <2>; 173563944891SThierry Reding }; 173663944891SThierry Reding 173729662d62SDipen Patel hte_aon: hardware-timestamp@c1e0000 { 173829662d62SDipen Patel compatible = "nvidia,tegra234-gte-aon"; 173929662d62SDipen Patel reg = <0x0 0xc1e0000 0x0 0x10000>; 174029662d62SDipen Patel interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 174129662d62SDipen Patel nvidia,int-threshold = <1>; 174229662d62SDipen Patel nvidia,gpio-controller = <&gpio_aon>; 174329662d62SDipen Patel #timestamp-cells = <1>; 174429662d62SDipen Patel }; 174529662d62SDipen Patel 1746156af9deSAkhil R gen2_i2c: i2c@c240000 { 1747156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 17482838cfddSThierry Reding reg = <0x0 0xc240000 0x0 0x100>; 1749156af9deSAkhil R interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1750260e8d42SJon Hunter #address-cells = <1>; 1751260e8d42SJon Hunter #size-cells = <0>; 1752156af9deSAkhil R status = "disabled"; 1753156af9deSAkhil R clock-frequency = <100000>; 1754156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C2 1755156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 1756156af9deSAkhil R clock-names = "div-clk", "parent"; 1757156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C2>; 1758156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 1759156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C2>; 1760156af9deSAkhil R reset-names = "i2c"; 17618e442805SAkhil R dmas = <&gpcdma 22>, <&gpcdma 22>; 17628e442805SAkhil R dma-names = "rx", "tx"; 1763156af9deSAkhil R }; 1764156af9deSAkhil R 1765156af9deSAkhil R gen8_i2c: i2c@c250000 { 1766156af9deSAkhil R compatible = "nvidia,tegra194-i2c"; 17672838cfddSThierry Reding reg = <0x0 0xc250000 0x0 0x100>; 1768156af9deSAkhil R interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1769260e8d42SJon Hunter #address-cells = <1>; 1770260e8d42SJon Hunter #size-cells = <0>; 1771156af9deSAkhil R status = "disabled"; 1772156af9deSAkhil R clock-frequency = <400000>; 1773156af9deSAkhil R clocks = <&bpmp TEGRA234_CLK_I2C8 1774156af9deSAkhil R &bpmp TEGRA234_CLK_PLLP_OUT0>; 1775156af9deSAkhil R clock-names = "div-clk", "parent"; 1776156af9deSAkhil R assigned-clocks = <&bpmp TEGRA234_CLK_I2C8>; 1777156af9deSAkhil R assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 1778156af9deSAkhil R resets = <&bpmp TEGRA234_RESET_I2C8>; 1779156af9deSAkhil R reset-names = "i2c"; 17808e442805SAkhil R dmas = <&gpcdma 0>, <&gpcdma 0>; 17818e442805SAkhil R dma-names = "rx", "tx"; 1782156af9deSAkhil R }; 1783156af9deSAkhil R 1784bb9667d8SGautham Srinivasan spi@c260000 { 1785bb9667d8SGautham Srinivasan compatible = "nvidia,tegra210-spi"; 1786bb9667d8SGautham Srinivasan reg = <0x0 0x0c260000 0x0 0x1000>; 1787bb9667d8SGautham Srinivasan interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1788bb9667d8SGautham Srinivasan #address-cells = <1>; 1789bb9667d8SGautham Srinivasan #size-cells = <0>; 1790bb9667d8SGautham Srinivasan clocks = <&bpmp TEGRA234_CLK_SPI2>; 1791bb9667d8SGautham Srinivasan clock-names = "spi"; 1792bb9667d8SGautham Srinivasan iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 1793bb9667d8SGautham Srinivasan assigned-clocks = <&bpmp TEGRA234_CLK_SPI2>; 1794bb9667d8SGautham Srinivasan assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 1795bb9667d8SGautham Srinivasan resets = <&bpmp TEGRA234_RESET_SPI2>; 1796bb9667d8SGautham Srinivasan reset-names = "spi"; 1797bb9667d8SGautham Srinivasan dmas = <&gpcdma 19>, <&gpcdma 19>; 1798bb9667d8SGautham Srinivasan dma-names = "rx", "tx"; 1799bb9667d8SGautham Srinivasan dma-coherent; 1800bb9667d8SGautham Srinivasan status = "disabled"; 1801bb9667d8SGautham Srinivasan }; 1802bb9667d8SGautham Srinivasan 180363944891SThierry Reding rtc@c2a0000 { 180463944891SThierry Reding compatible = "nvidia,tegra234-rtc", "nvidia,tegra20-rtc"; 18052838cfddSThierry Reding reg = <0x0 0x0c2a0000 0x0 0x10000>; 180663944891SThierry Reding interrupt-parent = <&pmc>; 180763944891SThierry Reding interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 1808e537addeSMikko Perttunen clocks = <&bpmp TEGRA234_CLK_CLK_32K>; 1809e537addeSMikko Perttunen clock-names = "rtc"; 181063944891SThierry Reding status = "disabled"; 181163944891SThierry Reding }; 181263944891SThierry Reding 1813f0e12668SThierry Reding gpio_aon: gpio@c2f0000 { 1814f0e12668SThierry Reding compatible = "nvidia,tegra234-gpio-aon"; 1815f0e12668SThierry Reding reg-names = "security", "gpio"; 18162838cfddSThierry Reding reg = <0x0 0x0c2f0000 0x0 0x1000>, 18172838cfddSThierry Reding <0x0 0x0c2f1000 0x0 0x1000>; 1818f0e12668SThierry Reding interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1819f0e12668SThierry Reding <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1820f0e12668SThierry Reding <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1821f0e12668SThierry Reding <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 1822f0e12668SThierry Reding #interrupt-cells = <2>; 1823f0e12668SThierry Reding interrupt-controller; 1824f0e12668SThierry Reding #gpio-cells = <2>; 1825f0e12668SThierry Reding gpio-controller; 1826282fde00SPrathamesh Shete gpio-ranges = <&pinmux_aon 0 0 32>; 1827282fde00SPrathamesh Shete }; 1828282fde00SPrathamesh Shete 1829282fde00SPrathamesh Shete pinmux_aon: pinmux@c300000 { 1830282fde00SPrathamesh Shete compatible = "nvidia,tegra234-pinmux-aon"; 1831282fde00SPrathamesh Shete reg = <0x0 0xc300000 0x0 0x4000>; 1832f0e12668SThierry Reding }; 1833f0e12668SThierry Reding 18342566d28cSJon Hunter pwm4: pwm@c340000 { 18352566d28cSJon Hunter compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 18362838cfddSThierry Reding reg = <0x0 0xc340000 0x0 0x10000>; 18372566d28cSJon Hunter clocks = <&bpmp TEGRA234_CLK_PWM4>; 18382566d28cSJon Hunter resets = <&bpmp TEGRA234_RESET_PWM4>; 18392566d28cSJon Hunter reset-names = "pwm"; 18402566d28cSJon Hunter status = "disabled"; 18412566d28cSJon Hunter #pwm-cells = <2>; 18422566d28cSJon Hunter }; 18432566d28cSJon Hunter 184463944891SThierry Reding pmc: pmc@c360000 { 184563944891SThierry Reding compatible = "nvidia,tegra234-pmc"; 18462838cfddSThierry Reding reg = <0x0 0x0c360000 0x0 0x10000>, 18472838cfddSThierry Reding <0x0 0x0c370000 0x0 0x10000>, 18482838cfddSThierry Reding <0x0 0x0c380000 0x0 0x10000>, 18492838cfddSThierry Reding <0x0 0x0c390000 0x0 0x10000>, 18502838cfddSThierry Reding <0x0 0x0c3a0000 0x0 0x10000>; 185163944891SThierry Reding reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 185263944891SThierry Reding 185363944891SThierry Reding #interrupt-cells = <2>; 185463944891SThierry Reding interrupt-controller; 1855d71b893aSPrathamesh Shete 1856d71b893aSPrathamesh Shete sdmmc1_1v8: sdmmc1-1v8 { 1857d71b893aSPrathamesh Shete pins = "sdmmc1-hv"; 1858d71b893aSPrathamesh Shete power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1859d71b893aSPrathamesh Shete }; 1860d71b893aSPrathamesh Shete 186179ed18d9SThierry Reding sdmmc1_3v3: sdmmc1-3v3 { 186279ed18d9SThierry Reding pins = "sdmmc1-hv"; 1863d71b893aSPrathamesh Shete power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1864d71b893aSPrathamesh Shete }; 1865d71b893aSPrathamesh Shete 1866d71b893aSPrathamesh Shete sdmmc3_1v8: sdmmc3-1v8 { 1867d71b893aSPrathamesh Shete pins = "sdmmc3-hv"; 1868d71b893aSPrathamesh Shete power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1869d71b893aSPrathamesh Shete }; 187079ed18d9SThierry Reding 187179ed18d9SThierry Reding sdmmc3_3v3: sdmmc3-3v3 { 187279ed18d9SThierry Reding pins = "sdmmc3-hv"; 187379ed18d9SThierry Reding power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 187479ed18d9SThierry Reding }; 187563944891SThierry Reding }; 187663944891SThierry Reding 1877302e1540SSumit Gupta aon-fabric@c600000 { 1878302e1540SSumit Gupta compatible = "nvidia,tegra234-aon-fabric"; 18792838cfddSThierry Reding reg = <0x0 0xc600000 0x0 0x40000>; 1880302e1540SSumit Gupta interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 1881302e1540SSumit Gupta status = "okay"; 1882302e1540SSumit Gupta }; 1883302e1540SSumit Gupta 1884302e1540SSumit Gupta bpmp-fabric@d600000 { 1885302e1540SSumit Gupta compatible = "nvidia,tegra234-bpmp-fabric"; 18862838cfddSThierry Reding reg = <0x0 0xd600000 0x0 0x40000>; 1887302e1540SSumit Gupta interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1888302e1540SSumit Gupta status = "okay"; 1889302e1540SSumit Gupta }; 1890302e1540SSumit Gupta 1891302e1540SSumit Gupta dce-fabric@de00000 { 1892302e1540SSumit Gupta compatible = "nvidia,tegra234-sce-fabric"; 18932838cfddSThierry Reding reg = <0x0 0xde00000 0x0 0x40000>; 1894302e1540SSumit Gupta interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>; 1895302e1540SSumit Gupta status = "okay"; 1896302e1540SSumit Gupta }; 1897302e1540SSumit Gupta 18982838cfddSThierry Reding ccplex@e000000 { 18992838cfddSThierry Reding compatible = "nvidia,tegra234-ccplex-cluster"; 19002838cfddSThierry Reding reg = <0x0 0x0e000000 0x0 0x5ffff>; 19012838cfddSThierry Reding nvidia,bpmp = <&bpmp>; 19022838cfddSThierry Reding status = "okay"; 19032838cfddSThierry Reding }; 19042838cfddSThierry Reding 190563944891SThierry Reding gic: interrupt-controller@f400000 { 190663944891SThierry Reding compatible = "arm,gic-v3"; 19072838cfddSThierry Reding reg = <0x0 0x0f400000 0x0 0x010000>, /* GICD */ 19082838cfddSThierry Reding <0x0 0x0f440000 0x0 0x200000>; /* GICR */ 190963944891SThierry Reding interrupt-parent = <&gic>; 191063944891SThierry Reding interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 191163944891SThierry Reding 191263944891SThierry Reding #redistributor-regions = <1>; 191363944891SThierry Reding #interrupt-cells = <3>; 191463944891SThierry Reding interrupt-controller; 191563944891SThierry Reding }; 19165710e16aSThierry Reding 19175710e16aSThierry Reding smmu_iso: iommu@10000000 { 19185710e16aSThierry Reding compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; 19192838cfddSThierry Reding reg = <0x0 0x10000000 0x0 0x1000000>; 19205710e16aSThierry Reding interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19215710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19225710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19235710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19245710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19255710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19265710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19275710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19285710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19295710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19305710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19315710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19325710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19335710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19345710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19355710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19365710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19375710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19385710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19395710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19405710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19415710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19425710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19435710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19445710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19455710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19465710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19475710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19485710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19495710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19505710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19515710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19525710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19535710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19545710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19555710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19565710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19575710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19585710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19595710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19605710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19615710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19625710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19635710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19645710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19655710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19665710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19675710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19685710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19695710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19705710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19715710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19725710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19735710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19745710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19755710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19765710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19775710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19785710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19795710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19805710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19815710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19825710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19835710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19845710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19855710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19865710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19875710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19885710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19895710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19905710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19915710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19925710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19935710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19945710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19955710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19965710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19975710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19985710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 19995710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 20005710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 20015710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 20025710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 20035710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 20045710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 20055710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 20065710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 20075710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 20085710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 20095710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 20105710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 20115710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 20125710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 20135710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 20145710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 20155710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 20165710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 20175710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 20185710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 20195710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 20205710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 20215710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 20225710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 20235710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 20245710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 20255710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 20265710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 20275710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 20285710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 20295710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 20305710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 20315710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 20325710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 20335710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 20345710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 20355710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 20365710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 20375710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 20385710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 20395710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 20405710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 20415710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 20425710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 20435710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 20445710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 20455710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 20465710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 20475710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 20485710e16aSThierry Reding <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 20495710e16aSThierry Reding stream-match-mask = <0x7f80>; 20505710e16aSThierry Reding #global-interrupts = <1>; 20515710e16aSThierry Reding #iommu-cells = <1>; 20525710e16aSThierry Reding 20535710e16aSThierry Reding nvidia,memory-controller = <&mc>; 20545710e16aSThierry Reding status = "okay"; 20555710e16aSThierry Reding }; 20565710e16aSThierry Reding 20575710e16aSThierry Reding smmu_niso0: iommu@12000000 { 20585710e16aSThierry Reding compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; 20592838cfddSThierry Reding reg = <0x0 0x12000000 0x0 0x1000000>, 20602838cfddSThierry Reding <0x0 0x11000000 0x0 0x1000000>; 20615710e16aSThierry Reding interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20625710e16aSThierry Reding <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 20635710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20645710e16aSThierry Reding <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 20655710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20665710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20675710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20685710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20695710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20705710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20715710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20725710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20735710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20745710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20755710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20765710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20775710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20785710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20795710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20805710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20815710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20825710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20835710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20845710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20855710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20865710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20875710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20885710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20895710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20905710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20915710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20925710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20935710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20945710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20955710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20965710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20975710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20985710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 20995710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21005710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21015710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21025710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21035710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21045710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21055710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21065710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21075710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21085710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21095710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21105710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21115710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21125710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21135710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21145710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21155710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21165710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21175710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21185710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21195710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21205710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21215710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21225710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21235710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21245710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21255710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21265710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21275710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21285710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21295710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21305710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21315710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21325710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21335710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21345710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21355710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21365710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21375710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21385710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21395710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21405710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21415710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21425710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21435710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21445710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21455710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21465710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21475710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21485710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21495710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21505710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21515710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21525710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21535710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21545710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21555710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21565710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21575710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21585710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21595710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21605710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21615710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21625710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21635710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21645710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21655710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21665710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21675710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21685710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21695710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21705710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21715710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21725710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21735710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21745710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21755710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21765710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21775710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21785710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21795710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21805710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21815710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21825710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21835710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21845710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21855710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21865710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21875710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21885710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21895710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 21905710e16aSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 21915710e16aSThierry Reding stream-match-mask = <0x7f80>; 21925710e16aSThierry Reding #global-interrupts = <2>; 21935710e16aSThierry Reding #iommu-cells = <1>; 21945710e16aSThierry Reding 21955710e16aSThierry Reding nvidia,memory-controller = <&mc>; 21965710e16aSThierry Reding status = "okay"; 21975710e16aSThierry Reding }; 2198302e1540SSumit Gupta 2199302e1540SSumit Gupta cbb-fabric@13a00000 { 2200302e1540SSumit Gupta compatible = "nvidia,tegra234-cbb-fabric"; 22012838cfddSThierry Reding reg = <0x0 0x13a00000 0x0 0x400000>; 2202302e1540SSumit Gupta interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 2203302e1540SSumit Gupta status = "okay"; 2204302e1540SSumit Gupta }; 2205962c400dSSumit Gupta 220679ed18d9SThierry Reding host1x@13e00000 { 220779ed18d9SThierry Reding compatible = "nvidia,tegra234-host1x"; 220879ed18d9SThierry Reding reg = <0x0 0x13e00000 0x0 0x10000>, 220979ed18d9SThierry Reding <0x0 0x13e10000 0x0 0x10000>, 221079ed18d9SThierry Reding <0x0 0x13e40000 0x0 0x10000>; 221179ed18d9SThierry Reding reg-names = "common", "hypervisor", "vm"; 221279ed18d9SThierry Reding interrupts = <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, 221379ed18d9SThierry Reding <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, 221479ed18d9SThierry Reding <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, 221579ed18d9SThierry Reding <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, 221679ed18d9SThierry Reding <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, 221779ed18d9SThierry Reding <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>, 221879ed18d9SThierry Reding <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>, 221979ed18d9SThierry Reding <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>, 222079ed18d9SThierry Reding <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 222179ed18d9SThierry Reding interrupt-names = "syncpt0", "syncpt1", "syncpt2", "syncpt3", "syncpt4", 222279ed18d9SThierry Reding "syncpt5", "syncpt6", "syncpt7", "host1x"; 222379ed18d9SThierry Reding clocks = <&bpmp TEGRA234_CLK_HOST1X>; 222479ed18d9SThierry Reding clock-names = "host1x"; 222579ed18d9SThierry Reding 222679ed18d9SThierry Reding #address-cells = <2>; 222779ed18d9SThierry Reding #size-cells = <2>; 222879ed18d9SThierry Reding ranges = <0x0 0x14800000 0x0 0x14800000 0x0 0x02000000>; 222979ed18d9SThierry Reding 223079ed18d9SThierry Reding interconnects = <&mc TEGRA234_MEMORY_CLIENT_HOST1XDMAR &emc>; 223179ed18d9SThierry Reding interconnect-names = "dma-mem"; 223279ed18d9SThierry Reding iommus = <&smmu_niso1 TEGRA234_SID_HOST1X>; 2233361238cdSMikko Perttunen dma-coherent; 223479ed18d9SThierry Reding 223579ed18d9SThierry Reding /* Context isolation domains */ 223679ed18d9SThierry Reding iommu-map = <0 &smmu_niso0 TEGRA234_SID_HOST1X_CTX0 1>, 223779ed18d9SThierry Reding <1 &smmu_niso0 TEGRA234_SID_HOST1X_CTX1 1>, 223879ed18d9SThierry Reding <2 &smmu_niso0 TEGRA234_SID_HOST1X_CTX2 1>, 223979ed18d9SThierry Reding <3 &smmu_niso0 TEGRA234_SID_HOST1X_CTX3 1>, 224079ed18d9SThierry Reding <4 &smmu_niso0 TEGRA234_SID_HOST1X_CTX4 1>, 224179ed18d9SThierry Reding <5 &smmu_niso0 TEGRA234_SID_HOST1X_CTX5 1>, 224279ed18d9SThierry Reding <6 &smmu_niso0 TEGRA234_SID_HOST1X_CTX6 1>, 224379ed18d9SThierry Reding <7 &smmu_niso0 TEGRA234_SID_HOST1X_CTX7 1>, 224479ed18d9SThierry Reding <8 &smmu_niso1 TEGRA234_SID_HOST1X_CTX0 1>, 224579ed18d9SThierry Reding <9 &smmu_niso1 TEGRA234_SID_HOST1X_CTX1 1>, 224679ed18d9SThierry Reding <10 &smmu_niso1 TEGRA234_SID_HOST1X_CTX2 1>, 224779ed18d9SThierry Reding <11 &smmu_niso1 TEGRA234_SID_HOST1X_CTX3 1>, 224879ed18d9SThierry Reding <12 &smmu_niso1 TEGRA234_SID_HOST1X_CTX4 1>, 224979ed18d9SThierry Reding <13 &smmu_niso1 TEGRA234_SID_HOST1X_CTX5 1>, 225079ed18d9SThierry Reding <14 &smmu_niso1 TEGRA234_SID_HOST1X_CTX6 1>, 225179ed18d9SThierry Reding <15 &smmu_niso1 TEGRA234_SID_HOST1X_CTX7 1>; 225279ed18d9SThierry Reding 225379ed18d9SThierry Reding vic@15340000 { 225479ed18d9SThierry Reding compatible = "nvidia,tegra234-vic"; 225579ed18d9SThierry Reding reg = <0x0 0x15340000 0x0 0x00040000>; 225679ed18d9SThierry Reding interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 225779ed18d9SThierry Reding clocks = <&bpmp TEGRA234_CLK_VIC>; 225879ed18d9SThierry Reding clock-names = "vic"; 225979ed18d9SThierry Reding resets = <&bpmp TEGRA234_RESET_VIC>; 226079ed18d9SThierry Reding reset-names = "vic"; 226179ed18d9SThierry Reding 226279ed18d9SThierry Reding power-domains = <&bpmp TEGRA234_POWER_DOMAIN_VIC>; 226379ed18d9SThierry Reding interconnects = <&mc TEGRA234_MEMORY_CLIENT_VICSRD &emc>, 226479ed18d9SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_VICSWR &emc>; 226579ed18d9SThierry Reding interconnect-names = "dma-mem", "write"; 226679ed18d9SThierry Reding iommus = <&smmu_niso1 TEGRA234_SID_VIC>; 226779ed18d9SThierry Reding dma-coherent; 226879ed18d9SThierry Reding }; 226979ed18d9SThierry Reding 227079ed18d9SThierry Reding nvdec@15480000 { 227179ed18d9SThierry Reding compatible = "nvidia,tegra234-nvdec"; 227279ed18d9SThierry Reding reg = <0x0 0x15480000 0x0 0x00040000>; 227379ed18d9SThierry Reding clocks = <&bpmp TEGRA234_CLK_NVDEC>, 227479ed18d9SThierry Reding <&bpmp TEGRA234_CLK_FUSE>, 227579ed18d9SThierry Reding <&bpmp TEGRA234_CLK_TSEC_PKA>; 227679ed18d9SThierry Reding clock-names = "nvdec", "fuse", "tsec_pka"; 227779ed18d9SThierry Reding resets = <&bpmp TEGRA234_RESET_NVDEC>; 227879ed18d9SThierry Reding reset-names = "nvdec"; 227979ed18d9SThierry Reding power-domains = <&bpmp TEGRA234_POWER_DOMAIN_NVDEC>; 228079ed18d9SThierry Reding interconnects = <&mc TEGRA234_MEMORY_CLIENT_NVDECSRD &emc>, 228179ed18d9SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_NVDECSWR &emc>; 228279ed18d9SThierry Reding interconnect-names = "dma-mem", "write"; 228379ed18d9SThierry Reding iommus = <&smmu_niso1 TEGRA234_SID_NVDEC>; 228479ed18d9SThierry Reding dma-coherent; 228579ed18d9SThierry Reding 228679ed18d9SThierry Reding nvidia,memory-controller = <&mc>; 228779ed18d9SThierry Reding 228879ed18d9SThierry Reding /* 228979ed18d9SThierry Reding * Placeholder values that firmware needs to update with the real 229079ed18d9SThierry Reding * offsets parsed from the microcode headers. 229179ed18d9SThierry Reding */ 229279ed18d9SThierry Reding nvidia,bl-manifest-offset = <0>; 229379ed18d9SThierry Reding nvidia,bl-data-offset = <0>; 229479ed18d9SThierry Reding nvidia,bl-code-offset = <0>; 229579ed18d9SThierry Reding nvidia,os-manifest-offset = <0>; 229679ed18d9SThierry Reding nvidia,os-data-offset = <0>; 229779ed18d9SThierry Reding nvidia,os-code-offset = <0>; 229879ed18d9SThierry Reding 229979ed18d9SThierry Reding /* 230079ed18d9SThierry Reding * Firmware needs to set this to "okay" once the above values have 230179ed18d9SThierry Reding * been updated. 230279ed18d9SThierry Reding */ 230379ed18d9SThierry Reding status = "disabled"; 230479ed18d9SThierry Reding }; 230579ed18d9SThierry Reding }; 230679ed18d9SThierry Reding 2307ec142c44SVidya Sagar pcie@140a0000 { 2308ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie"; 2309ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CA>; 2310ec142c44SVidya Sagar reg = <0x00 0x140a0000 0x0 0x00020000>, /* appl registers (128K) */ 2311ec142c44SVidya Sagar <0x00 0x2a000000 0x0 0x00040000>, /* configuration space (256K) */ 2312ec142c44SVidya Sagar <0x00 0x2a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2313794b834dSVidya Sagar <0x00 0x2a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2314794b834dSVidya Sagar <0x35 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2315794b834dSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2316ec142c44SVidya Sagar 2317ec142c44SVidya Sagar #address-cells = <3>; 2318ec142c44SVidya Sagar #size-cells = <2>; 2319ec142c44SVidya Sagar device_type = "pci"; 2320ec142c44SVidya Sagar num-lanes = <4>; 2321ec142c44SVidya Sagar num-viewport = <8>; 2322ec142c44SVidya Sagar linux,pci-domain = <8>; 2323ec142c44SVidya Sagar 2324ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX2_C8_CORE>; 2325ec142c44SVidya Sagar clock-names = "core"; 2326ec142c44SVidya Sagar 2327ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX2_CORE_8_APB>, 2328ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX2_CORE_8>; 2329ec142c44SVidya Sagar reset-names = "apb", "core"; 2330ec142c44SVidya Sagar 2331ec142c44SVidya Sagar interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2332ec142c44SVidya Sagar <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2333ec142c44SVidya Sagar interrupt-names = "intr", "msi"; 2334ec142c44SVidya Sagar 2335ec142c44SVidya Sagar #interrupt-cells = <1>; 2336ec142c44SVidya Sagar interrupt-map-mask = <0 0 0 0>; 2337ec142c44SVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 2338ec142c44SVidya Sagar 2339ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 8>; 2340ec142c44SVidya Sagar 2341ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2342ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2343ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2344ec142c44SVidya Sagar 2345ec142c44SVidya Sagar bus-range = <0x0 0xff>; 2346ec142c44SVidya Sagar 2347ec142c44SVidya Sagar ranges = <0x43000000 0x32 0x40000000 0x32 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2348ec142c44SVidya Sagar <0x02000000 0x0 0x40000000 0x35 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2349ec142c44SVidya Sagar <0x01000000 0x0 0x2a100000 0x00 0x2a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2350ec142c44SVidya Sagar 2351ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE8AR &emc>, 2352ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE8AW &emc>; 2353ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2354ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE8 0x1000>; 2355ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2356ec142c44SVidya Sagar dma-coherent; 2357ec142c44SVidya Sagar 2358ec142c44SVidya Sagar status = "disabled"; 2359ec142c44SVidya Sagar }; 2360ec142c44SVidya Sagar 2361ec142c44SVidya Sagar pcie@140c0000 { 2362ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie"; 2363ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CB>; 2364ec142c44SVidya Sagar reg = <0x00 0x140c0000 0x0 0x00020000>, /* appl registers (128K) */ 2365ec142c44SVidya Sagar <0x00 0x2c000000 0x0 0x00040000>, /* configuration space (256K) */ 2366ec142c44SVidya Sagar <0x00 0x2c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2367794b834dSVidya Sagar <0x00 0x2c080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2368794b834dSVidya Sagar <0x38 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2369794b834dSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2370ec142c44SVidya Sagar 2371ec142c44SVidya Sagar #address-cells = <3>; 2372ec142c44SVidya Sagar #size-cells = <2>; 2373ec142c44SVidya Sagar device_type = "pci"; 2374ec142c44SVidya Sagar num-lanes = <4>; 2375ec142c44SVidya Sagar num-viewport = <8>; 2376ec142c44SVidya Sagar linux,pci-domain = <9>; 2377ec142c44SVidya Sagar 2378ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX2_C9_CORE>; 2379ec142c44SVidya Sagar clock-names = "core"; 2380ec142c44SVidya Sagar 2381ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX2_CORE_9_APB>, 2382ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX2_CORE_9>; 2383ec142c44SVidya Sagar reset-names = "apb", "core"; 2384ec142c44SVidya Sagar 2385ec142c44SVidya Sagar interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2386ec142c44SVidya Sagar <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2387ec142c44SVidya Sagar interrupt-names = "intr", "msi"; 2388ec142c44SVidya Sagar 2389ec142c44SVidya Sagar #interrupt-cells = <1>; 2390ec142c44SVidya Sagar interrupt-map-mask = <0 0 0 0>; 2391ec142c44SVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2392ec142c44SVidya Sagar 2393ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 9>; 2394ec142c44SVidya Sagar 2395ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2396ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2397ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2398ec142c44SVidya Sagar 2399ec142c44SVidya Sagar bus-range = <0x0 0xff>; 2400ec142c44SVidya Sagar 240124840065SVidya Sagar ranges = <0x43000000 0x35 0x40000000 0x35 0x40000000 0x2 0xc0000000>, /* prefetchable memory (11264 MB) */ 2402ec142c44SVidya Sagar <0x02000000 0x0 0x40000000 0x38 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2403ec142c44SVidya Sagar <0x01000000 0x0 0x2c100000 0x00 0x2c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2404ec142c44SVidya Sagar 2405ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE9AR &emc>, 2406ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE9AW &emc>; 2407ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2408ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE9 0x1000>; 2409ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2410ec142c44SVidya Sagar dma-coherent; 2411ec142c44SVidya Sagar 2412ec142c44SVidya Sagar status = "disabled"; 2413ec142c44SVidya Sagar }; 2414ec142c44SVidya Sagar 2415ec142c44SVidya Sagar pcie@140e0000 { 2416ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie"; 2417ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CC>; 2418ec142c44SVidya Sagar reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K) */ 2419ec142c44SVidya Sagar <0x00 0x2e000000 0x0 0x00040000>, /* configuration space (256K) */ 2420ec142c44SVidya Sagar <0x00 0x2e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2421794b834dSVidya Sagar <0x00 0x2e080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2422794b834dSVidya Sagar <0x3b 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2423794b834dSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2424ec142c44SVidya Sagar 2425ec142c44SVidya Sagar #address-cells = <3>; 2426ec142c44SVidya Sagar #size-cells = <2>; 2427ec142c44SVidya Sagar device_type = "pci"; 2428ec142c44SVidya Sagar num-lanes = <4>; 2429ec142c44SVidya Sagar num-viewport = <8>; 2430ec142c44SVidya Sagar linux,pci-domain = <10>; 2431ec142c44SVidya Sagar 2432ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX2_C10_CORE>; 2433ec142c44SVidya Sagar clock-names = "core"; 2434ec142c44SVidya Sagar 2435ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX2_CORE_10_APB>, 2436ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX2_CORE_10>; 2437ec142c44SVidya Sagar reset-names = "apb", "core"; 2438ec142c44SVidya Sagar 2439ec142c44SVidya Sagar interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2440ec142c44SVidya Sagar <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2441ec142c44SVidya Sagar interrupt-names = "intr", "msi"; 2442ec142c44SVidya Sagar 2443ec142c44SVidya Sagar #interrupt-cells = <1>; 2444ec142c44SVidya Sagar interrupt-map-mask = <0 0 0 0>; 2445ec142c44SVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 2446ec142c44SVidya Sagar 2447ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 10>; 2448ec142c44SVidya Sagar 2449ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2450ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2451ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2452ec142c44SVidya Sagar 2453ec142c44SVidya Sagar bus-range = <0x0 0xff>; 2454ec142c44SVidya Sagar 2455ec142c44SVidya Sagar ranges = <0x43000000 0x38 0x40000000 0x38 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2456ec142c44SVidya Sagar <0x02000000 0x0 0x40000000 0x3b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2457ec142c44SVidya Sagar <0x01000000 0x0 0x2e100000 0x00 0x2e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2458ec142c44SVidya Sagar 2459ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE10AR &emc>, 2460ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE10AW &emc>; 2461ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2462ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>; 2463ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2464ec142c44SVidya Sagar dma-coherent; 2465ec142c44SVidya Sagar 2466ec142c44SVidya Sagar status = "disabled"; 2467ec142c44SVidya Sagar }; 2468ec142c44SVidya Sagar 24692838cfddSThierry Reding pcie-ep@140e0000 { 24702838cfddSThierry Reding compatible = "nvidia,tegra234-pcie-ep"; 24712838cfddSThierry Reding power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CC>; 24722838cfddSThierry Reding reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K) */ 24732838cfddSThierry Reding <0x00 0x2e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 24742838cfddSThierry Reding <0x00 0x2e080000 0x0 0x00040000>, /* DBI space (256K) */ 24752838cfddSThierry Reding <0x38 0x40000000 0x3 0x00000000>; /* Address Space (12G) */ 24762838cfddSThierry Reding reg-names = "appl", "atu_dma", "dbi", "addr_space"; 24772838cfddSThierry Reding 24782838cfddSThierry Reding num-lanes = <4>; 24792838cfddSThierry Reding 24802838cfddSThierry Reding clocks = <&bpmp TEGRA234_CLK_PEX2_C10_CORE>; 24812838cfddSThierry Reding clock-names = "core"; 24822838cfddSThierry Reding 24832838cfddSThierry Reding resets = <&bpmp TEGRA234_RESET_PEX2_CORE_10_APB>, 24842838cfddSThierry Reding <&bpmp TEGRA234_RESET_PEX2_CORE_10>; 24852838cfddSThierry Reding reset-names = "apb", "core"; 24862838cfddSThierry Reding 24872838cfddSThierry Reding interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 24882838cfddSThierry Reding interrupt-names = "intr"; 24892838cfddSThierry Reding 24902838cfddSThierry Reding nvidia,bpmp = <&bpmp 10>; 24912838cfddSThierry Reding 24922838cfddSThierry Reding nvidia,enable-ext-refclk; 24932838cfddSThierry Reding nvidia,aspm-cmrt-us = <60>; 24942838cfddSThierry Reding nvidia,aspm-pwr-on-t-us = <20>; 24952838cfddSThierry Reding nvidia,aspm-l0s-entrance-latency-us = <3>; 24962838cfddSThierry Reding 24972838cfddSThierry Reding interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE10AR &emc>, 24982838cfddSThierry Reding <&mc TEGRA234_MEMORY_CLIENT_PCIE10AW &emc>; 24992838cfddSThierry Reding interconnect-names = "dma-mem", "write"; 25002838cfddSThierry Reding iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>; 25012838cfddSThierry Reding iommu-map-mask = <0x0>; 25022838cfddSThierry Reding dma-coherent; 25032838cfddSThierry Reding 25042838cfddSThierry Reding status = "disabled"; 25052838cfddSThierry Reding }; 25062838cfddSThierry Reding 2507ec142c44SVidya Sagar pcie@14100000 { 2508ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie"; 2509ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>; 2510ec142c44SVidya Sagar reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */ 2511ec142c44SVidya Sagar <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */ 2512ec142c44SVidya Sagar <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2513794b834dSVidya Sagar <0x00 0x30080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2514794b834dSVidya Sagar <0x20 0xb0000000 0x0 0x10000000>; /* ECAM (256MB) */ 2515794b834dSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2516ec142c44SVidya Sagar 2517ec142c44SVidya Sagar #address-cells = <3>; 2518ec142c44SVidya Sagar #size-cells = <2>; 2519ec142c44SVidya Sagar device_type = "pci"; 2520ec142c44SVidya Sagar num-lanes = <1>; 2521ec142c44SVidya Sagar num-viewport = <8>; 2522ec142c44SVidya Sagar linux,pci-domain = <1>; 2523ec142c44SVidya Sagar 2524ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX0_C1_CORE>; 2525ec142c44SVidya Sagar clock-names = "core"; 2526ec142c44SVidya Sagar 2527ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX0_CORE_1_APB>, 2528ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX0_CORE_1>; 2529ec142c44SVidya Sagar reset-names = "apb", "core"; 2530ec142c44SVidya Sagar 2531ec142c44SVidya Sagar interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2532ec142c44SVidya Sagar <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2533ec142c44SVidya Sagar interrupt-names = "intr", "msi"; 2534ec142c44SVidya Sagar 2535ec142c44SVidya Sagar #interrupt-cells = <1>; 2536ec142c44SVidya Sagar interrupt-map-mask = <0 0 0 0>; 2537ec142c44SVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 2538ec142c44SVidya Sagar 2539ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 1>; 2540ec142c44SVidya Sagar 2541ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2542ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2543ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2544ec142c44SVidya Sagar 2545ec142c44SVidya Sagar bus-range = <0x0 0xff>; 2546ec142c44SVidya Sagar 2547ec142c44SVidya Sagar ranges = <0x43000000 0x20 0x80000000 0x20 0x80000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ 2548ec142c44SVidya Sagar <0x02000000 0x0 0x40000000 0x20 0xa8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2549ec142c44SVidya Sagar <0x01000000 0x0 0x30100000 0x00 0x30100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2550ec142c44SVidya Sagar 2551ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE1R &emc>, 2552ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE1W &emc>; 2553ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2554ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE1 0x1000>; 2555ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2556ec142c44SVidya Sagar dma-coherent; 2557ec142c44SVidya Sagar 2558ec142c44SVidya Sagar status = "disabled"; 2559ec142c44SVidya Sagar }; 2560ec142c44SVidya Sagar 2561ec142c44SVidya Sagar pcie@14120000 { 2562ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie"; 2563ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>; 2564ec142c44SVidya Sagar reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */ 2565ec142c44SVidya Sagar <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */ 2566ec142c44SVidya Sagar <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2567794b834dSVidya Sagar <0x00 0x32080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2568794b834dSVidya Sagar <0x20 0xf0000000 0x0 0x10000000>; /* ECAM (256MB) */ 2569794b834dSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2570ec142c44SVidya Sagar 2571ec142c44SVidya Sagar #address-cells = <3>; 2572ec142c44SVidya Sagar #size-cells = <2>; 2573ec142c44SVidya Sagar device_type = "pci"; 2574ec142c44SVidya Sagar num-lanes = <1>; 2575ec142c44SVidya Sagar num-viewport = <8>; 2576ec142c44SVidya Sagar linux,pci-domain = <2>; 2577ec142c44SVidya Sagar 2578ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX0_C2_CORE>; 2579ec142c44SVidya Sagar clock-names = "core"; 2580ec142c44SVidya Sagar 2581ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX0_CORE_2_APB>, 2582ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX0_CORE_2>; 2583ec142c44SVidya Sagar reset-names = "apb", "core"; 2584ec142c44SVidya Sagar 2585ec142c44SVidya Sagar interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2586ec142c44SVidya Sagar <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2587ec142c44SVidya Sagar interrupt-names = "intr", "msi"; 2588ec142c44SVidya Sagar 2589ec142c44SVidya Sagar #interrupt-cells = <1>; 2590ec142c44SVidya Sagar interrupt-map-mask = <0 0 0 0>; 2591ec142c44SVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 2592ec142c44SVidya Sagar 2593ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 2>; 2594ec142c44SVidya Sagar 2595ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2596ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2597ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2598ec142c44SVidya Sagar 2599ec142c44SVidya Sagar bus-range = <0x0 0xff>; 2600ec142c44SVidya Sagar 2601ec142c44SVidya Sagar ranges = <0x43000000 0x20 0xc0000000 0x20 0xc0000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ 2602ec142c44SVidya Sagar <0x02000000 0x0 0x40000000 0x20 0xe8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2603ec142c44SVidya Sagar <0x01000000 0x0 0x32100000 0x00 0x32100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2604ec142c44SVidya Sagar 2605ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE2AR &emc>, 2606ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE2AW &emc>; 2607ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2608ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE2 0x1000>; 2609ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2610ec142c44SVidya Sagar dma-coherent; 2611ec142c44SVidya Sagar 2612ec142c44SVidya Sagar status = "disabled"; 2613ec142c44SVidya Sagar }; 2614ec142c44SVidya Sagar 2615ec142c44SVidya Sagar pcie@14140000 { 2616ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie"; 2617ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>; 2618ec142c44SVidya Sagar reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */ 2619ec142c44SVidya Sagar <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */ 2620ec142c44SVidya Sagar <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2621794b834dSVidya Sagar <0x00 0x34080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2622794b834dSVidya Sagar <0x21 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2623794b834dSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2624ec142c44SVidya Sagar 2625ec142c44SVidya Sagar #address-cells = <3>; 2626ec142c44SVidya Sagar #size-cells = <2>; 2627ec142c44SVidya Sagar device_type = "pci"; 2628ec142c44SVidya Sagar num-lanes = <1>; 2629ec142c44SVidya Sagar num-viewport = <8>; 2630ec142c44SVidya Sagar linux,pci-domain = <3>; 2631ec142c44SVidya Sagar 2632ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX0_C3_CORE>; 2633ec142c44SVidya Sagar clock-names = "core"; 2634ec142c44SVidya Sagar 2635ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX0_CORE_3_APB>, 2636ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX0_CORE_3>; 2637ec142c44SVidya Sagar reset-names = "apb", "core"; 2638ec142c44SVidya Sagar 2639ec142c44SVidya Sagar interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2640ec142c44SVidya Sagar <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2641ec142c44SVidya Sagar interrupt-names = "intr", "msi"; 2642ec142c44SVidya Sagar 2643ec142c44SVidya Sagar #interrupt-cells = <1>; 2644ec142c44SVidya Sagar interrupt-map-mask = <0 0 0 0>; 2645ec142c44SVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 2646ec142c44SVidya Sagar 2647ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 3>; 2648ec142c44SVidya Sagar 2649ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2650ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2651ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2652ec142c44SVidya Sagar 2653ec142c44SVidya Sagar bus-range = <0x0 0xff>; 2654ec142c44SVidya Sagar 2655ec142c44SVidya Sagar ranges = <0x43000000 0x21 0x00000000 0x21 0x00000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ 265647a2f35dSVidya Sagar <0x02000000 0x0 0x40000000 0x21 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2657ec142c44SVidya Sagar <0x01000000 0x0 0x34100000 0x00 0x34100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2658ec142c44SVidya Sagar 2659ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE3R &emc>, 2660ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE3W &emc>; 2661ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2662ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE3 0x1000>; 2663ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2664ec142c44SVidya Sagar dma-coherent; 2665ec142c44SVidya Sagar 2666ec142c44SVidya Sagar status = "disabled"; 2667ec142c44SVidya Sagar }; 2668ec142c44SVidya Sagar 2669ec142c44SVidya Sagar pcie@14160000 { 2670ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie"; 2671ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BB>; 2672ec142c44SVidya Sagar reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2673ec142c44SVidya Sagar <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ 2674ec142c44SVidya Sagar <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2675794b834dSVidya Sagar <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2676794b834dSVidya Sagar <0x24 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2677794b834dSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2678ec142c44SVidya Sagar 2679ec142c44SVidya Sagar #address-cells = <3>; 2680ec142c44SVidya Sagar #size-cells = <2>; 2681ec142c44SVidya Sagar device_type = "pci"; 2682ec142c44SVidya Sagar num-lanes = <4>; 2683ec142c44SVidya Sagar num-viewport = <8>; 2684ec142c44SVidya Sagar linux,pci-domain = <4>; 2685ec142c44SVidya Sagar 2686ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX0_C4_CORE>; 2687ec142c44SVidya Sagar clock-names = "core"; 2688ec142c44SVidya Sagar 2689ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX0_CORE_4_APB>, 2690ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX0_CORE_4>; 2691ec142c44SVidya Sagar reset-names = "apb", "core"; 2692ec142c44SVidya Sagar 2693ec142c44SVidya Sagar interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2694ec142c44SVidya Sagar <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2695ec142c44SVidya Sagar interrupt-names = "intr", "msi"; 2696ec142c44SVidya Sagar 2697ec142c44SVidya Sagar #interrupt-cells = <1>; 2698ec142c44SVidya Sagar interrupt-map-mask = <0 0 0 0>; 2699ec142c44SVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 2700ec142c44SVidya Sagar 2701ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 4>; 2702ec142c44SVidya Sagar 2703ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2704ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2705ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2706ec142c44SVidya Sagar 2707ec142c44SVidya Sagar bus-range = <0x0 0xff>; 2708ec142c44SVidya Sagar 2709ec142c44SVidya Sagar ranges = <0x43000000 0x21 0x40000000 0x21 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2710ec142c44SVidya Sagar <0x02000000 0x0 0x40000000 0x24 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2711ec142c44SVidya Sagar <0x01000000 0x0 0x36100000 0x00 0x36100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2712ec142c44SVidya Sagar 2713ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE4R &emc>, 2714ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE4W &emc>; 2715ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2716ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE4 0x1000>; 2717ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2718ec142c44SVidya Sagar dma-coherent; 2719ec142c44SVidya Sagar 2720ec142c44SVidya Sagar status = "disabled"; 2721ec142c44SVidya Sagar }; 2722ec142c44SVidya Sagar 2723ec142c44SVidya Sagar pcie@14180000 { 2724ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie"; 2725ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BA>; 2726ec142c44SVidya Sagar reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2727ec142c44SVidya Sagar <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ 2728ec142c44SVidya Sagar <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2729794b834dSVidya Sagar <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2730794b834dSVidya Sagar <0x27 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2731794b834dSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2732ec142c44SVidya Sagar 2733ec142c44SVidya Sagar #address-cells = <3>; 2734ec142c44SVidya Sagar #size-cells = <2>; 2735ec142c44SVidya Sagar device_type = "pci"; 2736ec142c44SVidya Sagar num-lanes = <4>; 2737ec142c44SVidya Sagar num-viewport = <8>; 2738ec142c44SVidya Sagar linux,pci-domain = <0>; 2739ec142c44SVidya Sagar 2740ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX0_C0_CORE>; 2741ec142c44SVidya Sagar clock-names = "core"; 2742ec142c44SVidya Sagar 2743ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX0_CORE_0_APB>, 2744ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX0_CORE_0>; 2745ec142c44SVidya Sagar reset-names = "apb", "core"; 2746ec142c44SVidya Sagar 2747ec142c44SVidya Sagar interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2748ec142c44SVidya Sagar <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2749ec142c44SVidya Sagar interrupt-names = "intr", "msi"; 2750ec142c44SVidya Sagar 2751ec142c44SVidya Sagar #interrupt-cells = <1>; 2752ec142c44SVidya Sagar interrupt-map-mask = <0 0 0 0>; 2753ec142c44SVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 2754ec142c44SVidya Sagar 2755ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 0>; 2756ec142c44SVidya Sagar 2757ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2758ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2759ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2760ec142c44SVidya Sagar 2761ec142c44SVidya Sagar bus-range = <0x0 0xff>; 2762ec142c44SVidya Sagar 2763ec142c44SVidya Sagar ranges = <0x43000000 0x24 0x40000000 0x24 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2764ec142c44SVidya Sagar <0x02000000 0x0 0x40000000 0x27 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2765ec142c44SVidya Sagar <0x01000000 0x0 0x38100000 0x00 0x38100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2766ec142c44SVidya Sagar 2767ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE0R &emc>, 2768ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE0W &emc>; 2769ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2770ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE0 0x1000>; 2771ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2772ec142c44SVidya Sagar dma-coherent; 2773ec142c44SVidya Sagar 2774ec142c44SVidya Sagar status = "disabled"; 2775ec142c44SVidya Sagar }; 2776ec142c44SVidya Sagar 2777ec142c44SVidya Sagar pcie@141a0000 { 2778ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie"; 2779ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>; 2780ec142c44SVidya Sagar reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2781ec142c44SVidya Sagar <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */ 2782ec142c44SVidya Sagar <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2783794b834dSVidya Sagar <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2784794b834dSVidya Sagar <0x2b 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2785794b834dSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2786ec142c44SVidya Sagar 2787ec142c44SVidya Sagar #address-cells = <3>; 2788ec142c44SVidya Sagar #size-cells = <2>; 2789ec142c44SVidya Sagar device_type = "pci"; 2790ec142c44SVidya Sagar num-lanes = <8>; 2791ec142c44SVidya Sagar num-viewport = <8>; 2792ec142c44SVidya Sagar linux,pci-domain = <5>; 2793ec142c44SVidya Sagar 2794ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>; 2795ec142c44SVidya Sagar clock-names = "core"; 2796ec142c44SVidya Sagar 2797ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>, 2798ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX1_CORE_5>; 2799ec142c44SVidya Sagar reset-names = "apb", "core"; 2800ec142c44SVidya Sagar 2801ec142c44SVidya Sagar interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2802ec142c44SVidya Sagar <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2803ec142c44SVidya Sagar interrupt-names = "intr", "msi"; 2804ec142c44SVidya Sagar 2805ec142c44SVidya Sagar #interrupt-cells = <1>; 2806ec142c44SVidya Sagar interrupt-map-mask = <0 0 0 0>; 2807ec142c44SVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 2808ec142c44SVidya Sagar 2809ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 5>; 2810ec142c44SVidya Sagar 2811ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2812ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2813ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2814ec142c44SVidya Sagar 2815ec142c44SVidya Sagar bus-range = <0x0 0xff>; 2816ec142c44SVidya Sagar 281724840065SVidya Sagar ranges = <0x43000000 0x28 0x00000000 0x28 0x00000000 0x3 0x28000000>, /* prefetchable memory (12928 MB) */ 2818ec142c44SVidya Sagar <0x02000000 0x0 0x40000000 0x2b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2819ec142c44SVidya Sagar <0x01000000 0x0 0x3a100000 0x00 0x3a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2820ec142c44SVidya Sagar 2821ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE5R &emc>, 2822ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE5W &emc>; 2823ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2824ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>; 2825ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2826ec142c44SVidya Sagar dma-coherent; 2827ec142c44SVidya Sagar 2828ec142c44SVidya Sagar status = "disabled"; 2829ec142c44SVidya Sagar }; 2830ec142c44SVidya Sagar 28312838cfddSThierry Reding pcie-ep@141a0000 { 28322838cfddSThierry Reding compatible = "nvidia,tegra234-pcie-ep"; 28332838cfddSThierry Reding power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>; 28342838cfddSThierry Reding reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 28352838cfddSThierry Reding <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 28362838cfddSThierry Reding <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 28372838cfddSThierry Reding <0x27 0x40000000 0x4 0x00000000>; /* Address Space (16G) */ 28382838cfddSThierry Reding reg-names = "appl", "atu_dma", "dbi", "addr_space"; 28392838cfddSThierry Reding 28402838cfddSThierry Reding num-lanes = <8>; 28412838cfddSThierry Reding 28422838cfddSThierry Reding clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>; 28432838cfddSThierry Reding clock-names = "core"; 28442838cfddSThierry Reding 28452838cfddSThierry Reding resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>, 28462838cfddSThierry Reding <&bpmp TEGRA234_RESET_PEX1_CORE_5>; 28472838cfddSThierry Reding reset-names = "apb", "core"; 28482838cfddSThierry Reding 28492838cfddSThierry Reding interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 28502838cfddSThierry Reding interrupt-names = "intr"; 28512838cfddSThierry Reding 28522838cfddSThierry Reding nvidia,bpmp = <&bpmp 5>; 28532838cfddSThierry Reding 28542838cfddSThierry Reding nvidia,enable-ext-refclk; 28552838cfddSThierry Reding nvidia,aspm-cmrt-us = <60>; 28562838cfddSThierry Reding nvidia,aspm-pwr-on-t-us = <20>; 28572838cfddSThierry Reding nvidia,aspm-l0s-entrance-latency-us = <3>; 28582838cfddSThierry Reding 28592838cfddSThierry Reding interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE5R &emc>, 28602838cfddSThierry Reding <&mc TEGRA234_MEMORY_CLIENT_PCIE5W &emc>; 28612838cfddSThierry Reding interconnect-names = "dma-mem", "write"; 28622838cfddSThierry Reding iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>; 28632838cfddSThierry Reding iommu-map-mask = <0x0>; 28642838cfddSThierry Reding dma-coherent; 28652838cfddSThierry Reding 28662838cfddSThierry Reding status = "disabled"; 28672838cfddSThierry Reding }; 28682838cfddSThierry Reding 2869ec142c44SVidya Sagar pcie@141c0000 { 2870ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie"; 2871ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4A>; 2872ec142c44SVidya Sagar reg = <0x00 0x141c0000 0x0 0x00020000>, /* appl registers (128K) */ 2873ec142c44SVidya Sagar <0x00 0x3c000000 0x0 0x00040000>, /* configuration space (256K) */ 2874ec142c44SVidya Sagar <0x00 0x3c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2875794b834dSVidya Sagar <0x00 0x3c080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2876794b834dSVidya Sagar <0x2e 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2877794b834dSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2878ec142c44SVidya Sagar 2879ec142c44SVidya Sagar #address-cells = <3>; 2880ec142c44SVidya Sagar #size-cells = <2>; 2881ec142c44SVidya Sagar device_type = "pci"; 2882ec142c44SVidya Sagar num-lanes = <4>; 2883ec142c44SVidya Sagar num-viewport = <8>; 2884ec142c44SVidya Sagar linux,pci-domain = <6>; 2885ec142c44SVidya Sagar 2886ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX1_C6_CORE>; 2887ec142c44SVidya Sagar clock-names = "core"; 2888ec142c44SVidya Sagar 2889ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX1_CORE_6_APB>, 2890ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX1_CORE_6>; 2891ec142c44SVidya Sagar reset-names = "apb", "core"; 2892ec142c44SVidya Sagar 2893ec142c44SVidya Sagar interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2894ec142c44SVidya Sagar <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2895ec142c44SVidya Sagar interrupt-names = "intr", "msi"; 2896ec142c44SVidya Sagar 2897ec142c44SVidya Sagar #interrupt-cells = <1>; 2898ec142c44SVidya Sagar interrupt-map-mask = <0 0 0 0>; 2899ec142c44SVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 2900ec142c44SVidya Sagar 2901ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 6>; 2902ec142c44SVidya Sagar 2903ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2904ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2905ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2906ec142c44SVidya Sagar 2907ec142c44SVidya Sagar bus-range = <0x0 0xff>; 2908ec142c44SVidya Sagar 2909ec142c44SVidya Sagar ranges = <0x43000000 0x2b 0x40000000 0x2b 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2910ec142c44SVidya Sagar <0x02000000 0x0 0x40000000 0x2e 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2911ec142c44SVidya Sagar <0x01000000 0x0 0x3c100000 0x00 0x3c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2912ec142c44SVidya Sagar 2913ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE6AR &emc>, 2914ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE6AW &emc>; 2915ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 2916ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>; 2917ec142c44SVidya Sagar iommu-map-mask = <0x0>; 2918ec142c44SVidya Sagar dma-coherent; 2919ec142c44SVidya Sagar 2920ec142c44SVidya Sagar status = "disabled"; 2921ec142c44SVidya Sagar }; 2922ec142c44SVidya Sagar 29232838cfddSThierry Reding pcie-ep@141c0000 { 29242838cfddSThierry Reding compatible = "nvidia,tegra234-pcie-ep"; 29252838cfddSThierry Reding power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4A>; 29262838cfddSThierry Reding reg = <0x00 0x141c0000 0x0 0x00020000>, /* appl registers (128K) */ 29272838cfddSThierry Reding <0x00 0x3c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 29282838cfddSThierry Reding <0x00 0x3c080000 0x0 0x00040000>, /* DBI space (256K) */ 29292838cfddSThierry Reding <0x2b 0x40000000 0x3 0x00000000>; /* Address Space (12G) */ 29302838cfddSThierry Reding reg-names = "appl", "atu_dma", "dbi", "addr_space"; 29312838cfddSThierry Reding 29322838cfddSThierry Reding num-lanes = <4>; 29332838cfddSThierry Reding 29342838cfddSThierry Reding clocks = <&bpmp TEGRA234_CLK_PEX1_C6_CORE>; 29352838cfddSThierry Reding clock-names = "core"; 29362838cfddSThierry Reding 29372838cfddSThierry Reding resets = <&bpmp TEGRA234_RESET_PEX1_CORE_6_APB>, 29382838cfddSThierry Reding <&bpmp TEGRA234_RESET_PEX1_CORE_6>; 29392838cfddSThierry Reding reset-names = "apb", "core"; 29402838cfddSThierry Reding 29412838cfddSThierry Reding interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 29422838cfddSThierry Reding interrupt-names = "intr"; 29432838cfddSThierry Reding 29442838cfddSThierry Reding nvidia,bpmp = <&bpmp 6>; 29452838cfddSThierry Reding 29462838cfddSThierry Reding nvidia,enable-ext-refclk; 29472838cfddSThierry Reding nvidia,aspm-cmrt-us = <60>; 29482838cfddSThierry Reding nvidia,aspm-pwr-on-t-us = <20>; 29492838cfddSThierry Reding nvidia,aspm-l0s-entrance-latency-us = <3>; 29502838cfddSThierry Reding 29512838cfddSThierry Reding interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE6AR &emc>, 29522838cfddSThierry Reding <&mc TEGRA234_MEMORY_CLIENT_PCIE6AW &emc>; 29532838cfddSThierry Reding interconnect-names = "dma-mem", "write"; 29542838cfddSThierry Reding iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>; 29552838cfddSThierry Reding iommu-map-mask = <0x0>; 29562838cfddSThierry Reding dma-coherent; 29572838cfddSThierry Reding 29582838cfddSThierry Reding status = "disabled"; 29592838cfddSThierry Reding }; 29602838cfddSThierry Reding 2961ec142c44SVidya Sagar pcie@141e0000 { 2962ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie"; 2963ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8B>; 2964ec142c44SVidya Sagar reg = <0x00 0x141e0000 0x0 0x00020000>, /* appl registers (128K) */ 2965ec142c44SVidya Sagar <0x00 0x3e000000 0x0 0x00040000>, /* configuration space (256K) */ 2966ec142c44SVidya Sagar <0x00 0x3e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2967794b834dSVidya Sagar <0x00 0x3e080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2968794b834dSVidya Sagar <0x32 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2969794b834dSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2970ec142c44SVidya Sagar 2971ec142c44SVidya Sagar #address-cells = <3>; 2972ec142c44SVidya Sagar #size-cells = <2>; 2973ec142c44SVidya Sagar device_type = "pci"; 2974ec142c44SVidya Sagar num-lanes = <8>; 2975ec142c44SVidya Sagar num-viewport = <8>; 2976ec142c44SVidya Sagar linux,pci-domain = <7>; 2977ec142c44SVidya Sagar 2978ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX2_C7_CORE>; 2979ec142c44SVidya Sagar clock-names = "core"; 2980ec142c44SVidya Sagar 2981ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX2_CORE_7_APB>, 2982ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX2_CORE_7>; 2983ec142c44SVidya Sagar reset-names = "apb", "core"; 2984ec142c44SVidya Sagar 2985ec142c44SVidya Sagar interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2986ec142c44SVidya Sagar <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2987ec142c44SVidya Sagar interrupt-names = "intr", "msi"; 2988ec142c44SVidya Sagar 2989ec142c44SVidya Sagar #interrupt-cells = <1>; 2990ec142c44SVidya Sagar interrupt-map-mask = <0 0 0 0>; 2991ec142c44SVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 2992ec142c44SVidya Sagar 2993ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 7>; 2994ec142c44SVidya Sagar 2995ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 2996ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 2997ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2998ec142c44SVidya Sagar 2999ec142c44SVidya Sagar bus-range = <0x0 0xff>; 3000ec142c44SVidya Sagar 300124840065SVidya Sagar ranges = <0x43000000 0x30 0x00000000 0x30 0x00000000 0x2 0x28000000>, /* prefetchable memory (8832 MB) */ 3002ec142c44SVidya Sagar <0x02000000 0x0 0x40000000 0x32 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 3003ec142c44SVidya Sagar <0x01000000 0x0 0x3e100000 0x00 0x3e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 3004ec142c44SVidya Sagar 3005ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE7AR &emc>, 3006ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE7AW &emc>; 3007ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 3008ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>; 3009ec142c44SVidya Sagar iommu-map-mask = <0x0>; 3010ec142c44SVidya Sagar dma-coherent; 3011ec142c44SVidya Sagar 3012ec142c44SVidya Sagar status = "disabled"; 3013ec142c44SVidya Sagar }; 3014ec142c44SVidya Sagar 3015ec142c44SVidya Sagar pcie-ep@141e0000 { 3016ec142c44SVidya Sagar compatible = "nvidia,tegra234-pcie-ep"; 3017ec142c44SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8B>; 3018ec142c44SVidya Sagar reg = <0x00 0x141e0000 0x0 0x00020000>, /* appl registers (128K) */ 3019ec142c44SVidya Sagar <0x00 0x3e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 3020ec142c44SVidya Sagar <0x00 0x3e080000 0x0 0x00040000>, /* DBI space (256K) */ 3021ec142c44SVidya Sagar <0x2e 0x40000000 0x4 0x00000000>; /* Address Space (16G) */ 3022ec142c44SVidya Sagar reg-names = "appl", "atu_dma", "dbi", "addr_space"; 3023ec142c44SVidya Sagar 3024ec142c44SVidya Sagar num-lanes = <8>; 3025ec142c44SVidya Sagar 3026ec142c44SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX2_C7_CORE>; 3027ec142c44SVidya Sagar clock-names = "core"; 3028ec142c44SVidya Sagar 3029ec142c44SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX2_CORE_7_APB>, 3030ec142c44SVidya Sagar <&bpmp TEGRA234_RESET_PEX2_CORE_7>; 3031ec142c44SVidya Sagar reset-names = "apb", "core"; 3032ec142c44SVidya Sagar 3033ec142c44SVidya Sagar interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 3034ec142c44SVidya Sagar interrupt-names = "intr"; 3035ec142c44SVidya Sagar 3036ec142c44SVidya Sagar nvidia,bpmp = <&bpmp 7>; 3037ec142c44SVidya Sagar 3038ec142c44SVidya Sagar nvidia,enable-ext-refclk; 3039ec142c44SVidya Sagar nvidia,aspm-cmrt-us = <60>; 3040ec142c44SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 3041ec142c44SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 3042ec142c44SVidya Sagar 3043ec142c44SVidya Sagar interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE7AR &emc>, 3044ec142c44SVidya Sagar <&mc TEGRA234_MEMORY_CLIENT_PCIE7AW &emc>; 3045ec142c44SVidya Sagar interconnect-names = "dma-mem", "write"; 3046ec142c44SVidya Sagar iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>; 3047ec142c44SVidya Sagar iommu-map-mask = <0x0>; 3048ec142c44SVidya Sagar dma-coherent; 3049ec142c44SVidya Sagar 3050ec142c44SVidya Sagar status = "disabled"; 3051ec142c44SVidya Sagar }; 3052ec142c44SVidya Sagar }; 3053ec142c44SVidya Sagar 30547fa30752SThierry Reding sram@40000000 { 305563944891SThierry Reding compatible = "nvidia,tegra234-sysram", "mmio-sram"; 305698094be1SMikko Perttunen reg = <0x0 0x40000000 0x0 0x80000>; 30572838cfddSThierry Reding 305863944891SThierry Reding #address-cells = <1>; 305963944891SThierry Reding #size-cells = <1>; 306098094be1SMikko Perttunen ranges = <0x0 0x0 0x40000000 0x80000>; 30612838cfddSThierry Reding 306261192a9dSMikko Perttunen no-memory-wc; 306363944891SThierry Reding 306498094be1SMikko Perttunen cpu_bpmp_tx: sram@70000 { 306598094be1SMikko Perttunen reg = <0x70000 0x1000>; 306663944891SThierry Reding label = "cpu-bpmp-tx"; 306763944891SThierry Reding pool; 306863944891SThierry Reding }; 306963944891SThierry Reding 307098094be1SMikko Perttunen cpu_bpmp_rx: sram@71000 { 307198094be1SMikko Perttunen reg = <0x71000 0x1000>; 307263944891SThierry Reding label = "cpu-bpmp-rx"; 307363944891SThierry Reding pool; 307463944891SThierry Reding }; 307563944891SThierry Reding }; 307663944891SThierry Reding 307763944891SThierry Reding bpmp: bpmp { 307863944891SThierry Reding compatible = "nvidia,tegra234-bpmp", "nvidia,tegra186-bpmp"; 307963944891SThierry Reding mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 308063944891SThierry Reding TEGRA_HSP_DB_MASTER_BPMP>; 30817fa30752SThierry Reding shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; 308263944891SThierry Reding #clock-cells = <1>; 308363944891SThierry Reding #reset-cells = <1>; 308463944891SThierry Reding #power-domain-cells = <1>; 30856de481e5SThierry Reding interconnects = <&mc TEGRA234_MEMORY_CLIENT_BPMPR &emc>, 30866de481e5SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_BPMPW &emc>, 30876de481e5SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAR &emc>, 30886de481e5SThierry Reding <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAW &emc>; 30896de481e5SThierry Reding interconnect-names = "read", "write", "dma-mem", "dma-write"; 30905710e16aSThierry Reding iommus = <&smmu_niso1 TEGRA234_SID_BPMP>; 309163944891SThierry Reding 309263944891SThierry Reding bpmp_i2c: i2c { 309363944891SThierry Reding compatible = "nvidia,tegra186-bpmp-i2c"; 309463944891SThierry Reding nvidia,bpmp-bus-id = <5>; 309563944891SThierry Reding #address-cells = <1>; 309663944891SThierry Reding #size-cells = <0>; 309763944891SThierry Reding }; 309809d99078SThierry Reding 309909d99078SThierry Reding bpmp_thermal: thermal { 310009d99078SThierry Reding compatible = "nvidia,tegra186-bpmp-thermal"; 310109d99078SThierry Reding #thermal-sensor-cells = <1>; 310209d99078SThierry Reding }; 310363944891SThierry Reding }; 310463944891SThierry Reding 310563944891SThierry Reding cpus { 310663944891SThierry Reding #address-cells = <1>; 310763944891SThierry Reding #size-cells = <0>; 310863944891SThierry Reding 3109a12cf5c3SThierry Reding cpu0_0: cpu@0 { 3110a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 311163944891SThierry Reding device_type = "cpu"; 3112a12cf5c3SThierry Reding reg = <0x00000>; 311363944891SThierry Reding 311463944891SThierry Reding enable-method = "psci"; 3115a12cf5c3SThierry Reding 31161582e1d1SSumit Gupta operating-points-v2 = <&cl0_opp_tbl>; 31171582e1d1SSumit Gupta interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER0 &emc>; 31181582e1d1SSumit Gupta 3119a12cf5c3SThierry Reding i-cache-size = <65536>; 3120a12cf5c3SThierry Reding i-cache-line-size = <64>; 3121a12cf5c3SThierry Reding i-cache-sets = <256>; 3122a12cf5c3SThierry Reding d-cache-size = <65536>; 3123a12cf5c3SThierry Reding d-cache-line-size = <64>; 3124a12cf5c3SThierry Reding d-cache-sets = <256>; 3125a12cf5c3SThierry Reding next-level-cache = <&l2c0_0>; 312663944891SThierry Reding }; 3127a12cf5c3SThierry Reding 3128a12cf5c3SThierry Reding cpu0_1: cpu@100 { 3129a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 3130a12cf5c3SThierry Reding device_type = "cpu"; 3131a12cf5c3SThierry Reding reg = <0x00100>; 3132a12cf5c3SThierry Reding 3133a12cf5c3SThierry Reding enable-method = "psci"; 3134a12cf5c3SThierry Reding 31351582e1d1SSumit Gupta operating-points-v2 = <&cl0_opp_tbl>; 31361582e1d1SSumit Gupta interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER0 &emc>; 31371582e1d1SSumit Gupta 3138a12cf5c3SThierry Reding i-cache-size = <65536>; 3139a12cf5c3SThierry Reding i-cache-line-size = <64>; 3140a12cf5c3SThierry Reding i-cache-sets = <256>; 3141a12cf5c3SThierry Reding d-cache-size = <65536>; 3142a12cf5c3SThierry Reding d-cache-line-size = <64>; 3143a12cf5c3SThierry Reding d-cache-sets = <256>; 3144a12cf5c3SThierry Reding next-level-cache = <&l2c0_1>; 3145a12cf5c3SThierry Reding }; 3146a12cf5c3SThierry Reding 3147a12cf5c3SThierry Reding cpu0_2: cpu@200 { 3148a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 3149a12cf5c3SThierry Reding device_type = "cpu"; 3150a12cf5c3SThierry Reding reg = <0x00200>; 3151a12cf5c3SThierry Reding 3152a12cf5c3SThierry Reding enable-method = "psci"; 3153a12cf5c3SThierry Reding 31541582e1d1SSumit Gupta operating-points-v2 = <&cl0_opp_tbl>; 31551582e1d1SSumit Gupta interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER0 &emc>; 31561582e1d1SSumit Gupta 3157a12cf5c3SThierry Reding i-cache-size = <65536>; 3158a12cf5c3SThierry Reding i-cache-line-size = <64>; 3159a12cf5c3SThierry Reding i-cache-sets = <256>; 3160a12cf5c3SThierry Reding d-cache-size = <65536>; 3161a12cf5c3SThierry Reding d-cache-line-size = <64>; 3162a12cf5c3SThierry Reding d-cache-sets = <256>; 3163a12cf5c3SThierry Reding next-level-cache = <&l2c0_2>; 3164a12cf5c3SThierry Reding }; 3165a12cf5c3SThierry Reding 3166a12cf5c3SThierry Reding cpu0_3: cpu@300 { 3167a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 3168a12cf5c3SThierry Reding device_type = "cpu"; 3169a12cf5c3SThierry Reding reg = <0x00300>; 3170a12cf5c3SThierry Reding 3171a12cf5c3SThierry Reding enable-method = "psci"; 3172a12cf5c3SThierry Reding 31731582e1d1SSumit Gupta operating-points-v2 = <&cl0_opp_tbl>; 31741582e1d1SSumit Gupta interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER0 &emc>; 31751582e1d1SSumit Gupta 3176a12cf5c3SThierry Reding i-cache-size = <65536>; 3177a12cf5c3SThierry Reding i-cache-line-size = <64>; 3178a12cf5c3SThierry Reding i-cache-sets = <256>; 3179a12cf5c3SThierry Reding d-cache-size = <65536>; 3180a12cf5c3SThierry Reding d-cache-line-size = <64>; 3181a12cf5c3SThierry Reding d-cache-sets = <256>; 3182a12cf5c3SThierry Reding next-level-cache = <&l2c0_3>; 3183a12cf5c3SThierry Reding }; 3184a12cf5c3SThierry Reding 3185a12cf5c3SThierry Reding cpu1_0: cpu@10000 { 3186a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 3187a12cf5c3SThierry Reding device_type = "cpu"; 3188a12cf5c3SThierry Reding reg = <0x10000>; 3189a12cf5c3SThierry Reding 3190a12cf5c3SThierry Reding enable-method = "psci"; 3191a12cf5c3SThierry Reding 31921582e1d1SSumit Gupta operating-points-v2 = <&cl1_opp_tbl>; 31931582e1d1SSumit Gupta interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER1 &emc>; 31941582e1d1SSumit Gupta 3195a12cf5c3SThierry Reding i-cache-size = <65536>; 3196a12cf5c3SThierry Reding i-cache-line-size = <64>; 3197a12cf5c3SThierry Reding i-cache-sets = <256>; 3198a12cf5c3SThierry Reding d-cache-size = <65536>; 3199a12cf5c3SThierry Reding d-cache-line-size = <64>; 3200a12cf5c3SThierry Reding d-cache-sets = <256>; 3201a12cf5c3SThierry Reding next-level-cache = <&l2c1_0>; 3202a12cf5c3SThierry Reding }; 3203a12cf5c3SThierry Reding 3204a12cf5c3SThierry Reding cpu1_1: cpu@10100 { 3205a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 3206a12cf5c3SThierry Reding device_type = "cpu"; 3207a12cf5c3SThierry Reding reg = <0x10100>; 3208a12cf5c3SThierry Reding 3209a12cf5c3SThierry Reding enable-method = "psci"; 3210a12cf5c3SThierry Reding 32111582e1d1SSumit Gupta operating-points-v2 = <&cl1_opp_tbl>; 32121582e1d1SSumit Gupta interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER1 &emc>; 32131582e1d1SSumit Gupta 3214a12cf5c3SThierry Reding i-cache-size = <65536>; 3215a12cf5c3SThierry Reding i-cache-line-size = <64>; 3216a12cf5c3SThierry Reding i-cache-sets = <256>; 3217a12cf5c3SThierry Reding d-cache-size = <65536>; 3218a12cf5c3SThierry Reding d-cache-line-size = <64>; 3219a12cf5c3SThierry Reding d-cache-sets = <256>; 3220a12cf5c3SThierry Reding next-level-cache = <&l2c1_1>; 3221a12cf5c3SThierry Reding }; 3222a12cf5c3SThierry Reding 3223a12cf5c3SThierry Reding cpu1_2: cpu@10200 { 3224a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 3225a12cf5c3SThierry Reding device_type = "cpu"; 3226a12cf5c3SThierry Reding reg = <0x10200>; 3227a12cf5c3SThierry Reding 3228a12cf5c3SThierry Reding enable-method = "psci"; 3229a12cf5c3SThierry Reding 32301582e1d1SSumit Gupta operating-points-v2 = <&cl1_opp_tbl>; 32311582e1d1SSumit Gupta interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER1 &emc>; 32321582e1d1SSumit Gupta 3233a12cf5c3SThierry Reding i-cache-size = <65536>; 3234a12cf5c3SThierry Reding i-cache-line-size = <64>; 3235a12cf5c3SThierry Reding i-cache-sets = <256>; 3236a12cf5c3SThierry Reding d-cache-size = <65536>; 3237a12cf5c3SThierry Reding d-cache-line-size = <64>; 3238a12cf5c3SThierry Reding d-cache-sets = <256>; 3239a12cf5c3SThierry Reding next-level-cache = <&l2c1_2>; 3240a12cf5c3SThierry Reding }; 3241a12cf5c3SThierry Reding 3242a12cf5c3SThierry Reding cpu1_3: cpu@10300 { 3243a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 3244a12cf5c3SThierry Reding device_type = "cpu"; 3245a12cf5c3SThierry Reding reg = <0x10300>; 3246a12cf5c3SThierry Reding 3247a12cf5c3SThierry Reding enable-method = "psci"; 3248a12cf5c3SThierry Reding 32491582e1d1SSumit Gupta operating-points-v2 = <&cl1_opp_tbl>; 32501582e1d1SSumit Gupta interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER1 &emc>; 32511582e1d1SSumit Gupta 3252a12cf5c3SThierry Reding i-cache-size = <65536>; 3253a12cf5c3SThierry Reding i-cache-line-size = <64>; 3254a12cf5c3SThierry Reding i-cache-sets = <256>; 3255a12cf5c3SThierry Reding d-cache-size = <65536>; 3256a12cf5c3SThierry Reding d-cache-line-size = <64>; 3257a12cf5c3SThierry Reding d-cache-sets = <256>; 3258a12cf5c3SThierry Reding next-level-cache = <&l2c1_3>; 3259a12cf5c3SThierry Reding }; 3260a12cf5c3SThierry Reding 3261a12cf5c3SThierry Reding cpu2_0: cpu@20000 { 3262a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 3263a12cf5c3SThierry Reding device_type = "cpu"; 3264a12cf5c3SThierry Reding reg = <0x20000>; 3265a12cf5c3SThierry Reding 3266a12cf5c3SThierry Reding enable-method = "psci"; 3267a12cf5c3SThierry Reding 32681582e1d1SSumit Gupta operating-points-v2 = <&cl2_opp_tbl>; 32691582e1d1SSumit Gupta interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER2 &emc>; 32701582e1d1SSumit Gupta 3271a12cf5c3SThierry Reding i-cache-size = <65536>; 3272a12cf5c3SThierry Reding i-cache-line-size = <64>; 3273a12cf5c3SThierry Reding i-cache-sets = <256>; 3274a12cf5c3SThierry Reding d-cache-size = <65536>; 3275a12cf5c3SThierry Reding d-cache-line-size = <64>; 3276a12cf5c3SThierry Reding d-cache-sets = <256>; 3277a12cf5c3SThierry Reding next-level-cache = <&l2c2_0>; 3278a12cf5c3SThierry Reding }; 3279a12cf5c3SThierry Reding 3280a12cf5c3SThierry Reding cpu2_1: cpu@20100 { 3281a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 3282a12cf5c3SThierry Reding device_type = "cpu"; 3283a12cf5c3SThierry Reding reg = <0x20100>; 3284a12cf5c3SThierry Reding 3285a12cf5c3SThierry Reding enable-method = "psci"; 3286a12cf5c3SThierry Reding 32871582e1d1SSumit Gupta operating-points-v2 = <&cl2_opp_tbl>; 32881582e1d1SSumit Gupta interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER2 &emc>; 32891582e1d1SSumit Gupta 3290a12cf5c3SThierry Reding i-cache-size = <65536>; 3291a12cf5c3SThierry Reding i-cache-line-size = <64>; 3292a12cf5c3SThierry Reding i-cache-sets = <256>; 3293a12cf5c3SThierry Reding d-cache-size = <65536>; 3294a12cf5c3SThierry Reding d-cache-line-size = <64>; 3295a12cf5c3SThierry Reding d-cache-sets = <256>; 3296a12cf5c3SThierry Reding next-level-cache = <&l2c2_1>; 3297a12cf5c3SThierry Reding }; 3298a12cf5c3SThierry Reding 3299a12cf5c3SThierry Reding cpu2_2: cpu@20200 { 3300a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 3301a12cf5c3SThierry Reding device_type = "cpu"; 3302a12cf5c3SThierry Reding reg = <0x20200>; 3303a12cf5c3SThierry Reding 3304a12cf5c3SThierry Reding enable-method = "psci"; 3305a12cf5c3SThierry Reding 33061582e1d1SSumit Gupta operating-points-v2 = <&cl2_opp_tbl>; 33071582e1d1SSumit Gupta interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER2 &emc>; 33081582e1d1SSumit Gupta 3309a12cf5c3SThierry Reding i-cache-size = <65536>; 3310a12cf5c3SThierry Reding i-cache-line-size = <64>; 3311a12cf5c3SThierry Reding i-cache-sets = <256>; 3312a12cf5c3SThierry Reding d-cache-size = <65536>; 3313a12cf5c3SThierry Reding d-cache-line-size = <64>; 3314a12cf5c3SThierry Reding d-cache-sets = <256>; 3315a12cf5c3SThierry Reding next-level-cache = <&l2c2_2>; 3316a12cf5c3SThierry Reding }; 3317a12cf5c3SThierry Reding 3318a12cf5c3SThierry Reding cpu2_3: cpu@20300 { 3319a12cf5c3SThierry Reding compatible = "arm,cortex-a78"; 3320a12cf5c3SThierry Reding device_type = "cpu"; 3321a12cf5c3SThierry Reding reg = <0x20300>; 3322a12cf5c3SThierry Reding 3323a12cf5c3SThierry Reding enable-method = "psci"; 3324a12cf5c3SThierry Reding 33251582e1d1SSumit Gupta operating-points-v2 = <&cl2_opp_tbl>; 33261582e1d1SSumit Gupta interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER2 &emc>; 33271582e1d1SSumit Gupta 3328a12cf5c3SThierry Reding i-cache-size = <65536>; 3329a12cf5c3SThierry Reding i-cache-line-size = <64>; 3330a12cf5c3SThierry Reding i-cache-sets = <256>; 3331a12cf5c3SThierry Reding d-cache-size = <65536>; 3332a12cf5c3SThierry Reding d-cache-line-size = <64>; 3333a12cf5c3SThierry Reding d-cache-sets = <256>; 3334a12cf5c3SThierry Reding next-level-cache = <&l2c2_3>; 3335a12cf5c3SThierry Reding }; 3336a12cf5c3SThierry Reding 3337a12cf5c3SThierry Reding cpu-map { 3338a12cf5c3SThierry Reding cluster0 { 3339a12cf5c3SThierry Reding core0 { 3340a12cf5c3SThierry Reding cpu = <&cpu0_0>; 3341a12cf5c3SThierry Reding }; 3342a12cf5c3SThierry Reding 3343a12cf5c3SThierry Reding core1 { 3344a12cf5c3SThierry Reding cpu = <&cpu0_1>; 3345a12cf5c3SThierry Reding }; 3346a12cf5c3SThierry Reding 3347a12cf5c3SThierry Reding core2 { 3348a12cf5c3SThierry Reding cpu = <&cpu0_2>; 3349a12cf5c3SThierry Reding }; 3350a12cf5c3SThierry Reding 3351a12cf5c3SThierry Reding core3 { 3352a12cf5c3SThierry Reding cpu = <&cpu0_3>; 3353a12cf5c3SThierry Reding }; 3354a12cf5c3SThierry Reding }; 3355a12cf5c3SThierry Reding 3356a12cf5c3SThierry Reding cluster1 { 3357a12cf5c3SThierry Reding core0 { 3358a12cf5c3SThierry Reding cpu = <&cpu1_0>; 3359a12cf5c3SThierry Reding }; 3360a12cf5c3SThierry Reding 3361a12cf5c3SThierry Reding core1 { 3362a12cf5c3SThierry Reding cpu = <&cpu1_1>; 3363a12cf5c3SThierry Reding }; 3364a12cf5c3SThierry Reding 3365a12cf5c3SThierry Reding core2 { 3366a12cf5c3SThierry Reding cpu = <&cpu1_2>; 3367a12cf5c3SThierry Reding }; 3368a12cf5c3SThierry Reding 3369a12cf5c3SThierry Reding core3 { 3370a12cf5c3SThierry Reding cpu = <&cpu1_3>; 3371a12cf5c3SThierry Reding }; 3372a12cf5c3SThierry Reding }; 3373a12cf5c3SThierry Reding 3374a12cf5c3SThierry Reding cluster2 { 3375a12cf5c3SThierry Reding core0 { 3376a12cf5c3SThierry Reding cpu = <&cpu2_0>; 3377a12cf5c3SThierry Reding }; 3378a12cf5c3SThierry Reding 3379a12cf5c3SThierry Reding core1 { 3380a12cf5c3SThierry Reding cpu = <&cpu2_1>; 3381a12cf5c3SThierry Reding }; 3382a12cf5c3SThierry Reding 3383a12cf5c3SThierry Reding core2 { 3384a12cf5c3SThierry Reding cpu = <&cpu2_2>; 3385a12cf5c3SThierry Reding }; 3386a12cf5c3SThierry Reding 3387a12cf5c3SThierry Reding core3 { 3388a12cf5c3SThierry Reding cpu = <&cpu2_3>; 3389a12cf5c3SThierry Reding }; 3390a12cf5c3SThierry Reding }; 3391a12cf5c3SThierry Reding }; 3392a12cf5c3SThierry Reding 3393a12cf5c3SThierry Reding l2c0_0: l2-cache00 { 339427f1568bSPierre Gondois compatible = "cache"; 3395a12cf5c3SThierry Reding cache-size = <262144>; 3396a12cf5c3SThierry Reding cache-line-size = <64>; 3397a12cf5c3SThierry Reding cache-sets = <512>; 3398a12cf5c3SThierry Reding cache-unified; 339927f1568bSPierre Gondois cache-level = <2>; 3400a12cf5c3SThierry Reding next-level-cache = <&l3c0>; 3401a12cf5c3SThierry Reding }; 3402a12cf5c3SThierry Reding 3403a12cf5c3SThierry Reding l2c0_1: l2-cache01 { 340427f1568bSPierre Gondois compatible = "cache"; 3405a12cf5c3SThierry Reding cache-size = <262144>; 3406a12cf5c3SThierry Reding cache-line-size = <64>; 3407a12cf5c3SThierry Reding cache-sets = <512>; 3408a12cf5c3SThierry Reding cache-unified; 340927f1568bSPierre Gondois cache-level = <2>; 3410a12cf5c3SThierry Reding next-level-cache = <&l3c0>; 3411a12cf5c3SThierry Reding }; 3412a12cf5c3SThierry Reding 3413a12cf5c3SThierry Reding l2c0_2: l2-cache02 { 341427f1568bSPierre Gondois compatible = "cache"; 3415a12cf5c3SThierry Reding cache-size = <262144>; 3416a12cf5c3SThierry Reding cache-line-size = <64>; 3417a12cf5c3SThierry Reding cache-sets = <512>; 3418a12cf5c3SThierry Reding cache-unified; 341927f1568bSPierre Gondois cache-level = <2>; 3420a12cf5c3SThierry Reding next-level-cache = <&l3c0>; 3421a12cf5c3SThierry Reding }; 3422a12cf5c3SThierry Reding 3423a12cf5c3SThierry Reding l2c0_3: l2-cache03 { 342427f1568bSPierre Gondois compatible = "cache"; 3425a12cf5c3SThierry Reding cache-size = <262144>; 3426a12cf5c3SThierry Reding cache-line-size = <64>; 3427a12cf5c3SThierry Reding cache-sets = <512>; 3428a12cf5c3SThierry Reding cache-unified; 342927f1568bSPierre Gondois cache-level = <2>; 3430a12cf5c3SThierry Reding next-level-cache = <&l3c0>; 3431a12cf5c3SThierry Reding }; 3432a12cf5c3SThierry Reding 3433a12cf5c3SThierry Reding l2c1_0: l2-cache10 { 343427f1568bSPierre Gondois compatible = "cache"; 3435a12cf5c3SThierry Reding cache-size = <262144>; 3436a12cf5c3SThierry Reding cache-line-size = <64>; 3437a12cf5c3SThierry Reding cache-sets = <512>; 3438a12cf5c3SThierry Reding cache-unified; 343927f1568bSPierre Gondois cache-level = <2>; 3440a12cf5c3SThierry Reding next-level-cache = <&l3c1>; 3441a12cf5c3SThierry Reding }; 3442a12cf5c3SThierry Reding 3443a12cf5c3SThierry Reding l2c1_1: l2-cache11 { 344427f1568bSPierre Gondois compatible = "cache"; 3445a12cf5c3SThierry Reding cache-size = <262144>; 3446a12cf5c3SThierry Reding cache-line-size = <64>; 3447a12cf5c3SThierry Reding cache-sets = <512>; 3448a12cf5c3SThierry Reding cache-unified; 344927f1568bSPierre Gondois cache-level = <2>; 3450a12cf5c3SThierry Reding next-level-cache = <&l3c1>; 3451a12cf5c3SThierry Reding }; 3452a12cf5c3SThierry Reding 3453a12cf5c3SThierry Reding l2c1_2: l2-cache12 { 345427f1568bSPierre Gondois compatible = "cache"; 3455a12cf5c3SThierry Reding cache-size = <262144>; 3456a12cf5c3SThierry Reding cache-line-size = <64>; 3457a12cf5c3SThierry Reding cache-sets = <512>; 3458a12cf5c3SThierry Reding cache-unified; 345927f1568bSPierre Gondois cache-level = <2>; 3460a12cf5c3SThierry Reding next-level-cache = <&l3c1>; 3461a12cf5c3SThierry Reding }; 3462a12cf5c3SThierry Reding 3463a12cf5c3SThierry Reding l2c1_3: l2-cache13 { 346427f1568bSPierre Gondois compatible = "cache"; 3465a12cf5c3SThierry Reding cache-size = <262144>; 3466a12cf5c3SThierry Reding cache-line-size = <64>; 3467a12cf5c3SThierry Reding cache-sets = <512>; 3468a12cf5c3SThierry Reding cache-unified; 346927f1568bSPierre Gondois cache-level = <2>; 3470a12cf5c3SThierry Reding next-level-cache = <&l3c1>; 3471a12cf5c3SThierry Reding }; 3472a12cf5c3SThierry Reding 3473a12cf5c3SThierry Reding l2c2_0: l2-cache20 { 347427f1568bSPierre Gondois compatible = "cache"; 3475a12cf5c3SThierry Reding cache-size = <262144>; 3476a12cf5c3SThierry Reding cache-line-size = <64>; 3477a12cf5c3SThierry Reding cache-sets = <512>; 3478a12cf5c3SThierry Reding cache-unified; 347927f1568bSPierre Gondois cache-level = <2>; 3480a12cf5c3SThierry Reding next-level-cache = <&l3c2>; 3481a12cf5c3SThierry Reding }; 3482a12cf5c3SThierry Reding 3483a12cf5c3SThierry Reding l2c2_1: l2-cache21 { 348427f1568bSPierre Gondois compatible = "cache"; 3485a12cf5c3SThierry Reding cache-size = <262144>; 3486a12cf5c3SThierry Reding cache-line-size = <64>; 3487a12cf5c3SThierry Reding cache-sets = <512>; 3488a12cf5c3SThierry Reding cache-unified; 348927f1568bSPierre Gondois cache-level = <2>; 3490a12cf5c3SThierry Reding next-level-cache = <&l3c2>; 3491a12cf5c3SThierry Reding }; 3492a12cf5c3SThierry Reding 3493a12cf5c3SThierry Reding l2c2_2: l2-cache22 { 349427f1568bSPierre Gondois compatible = "cache"; 3495a12cf5c3SThierry Reding cache-size = <262144>; 3496a12cf5c3SThierry Reding cache-line-size = <64>; 3497a12cf5c3SThierry Reding cache-sets = <512>; 3498a12cf5c3SThierry Reding cache-unified; 349927f1568bSPierre Gondois cache-level = <2>; 3500a12cf5c3SThierry Reding next-level-cache = <&l3c2>; 3501a12cf5c3SThierry Reding }; 3502a12cf5c3SThierry Reding 3503a12cf5c3SThierry Reding l2c2_3: l2-cache23 { 350427f1568bSPierre Gondois compatible = "cache"; 3505a12cf5c3SThierry Reding cache-size = <262144>; 3506a12cf5c3SThierry Reding cache-line-size = <64>; 3507a12cf5c3SThierry Reding cache-sets = <512>; 3508a12cf5c3SThierry Reding cache-unified; 350927f1568bSPierre Gondois cache-level = <2>; 3510a12cf5c3SThierry Reding next-level-cache = <&l3c2>; 3511a12cf5c3SThierry Reding }; 3512a12cf5c3SThierry Reding 3513a12cf5c3SThierry Reding l3c0: l3-cache0 { 351427f1568bSPierre Gondois compatible = "cache"; 351527f1568bSPierre Gondois cache-unified; 3516a12cf5c3SThierry Reding cache-size = <2097152>; 3517a12cf5c3SThierry Reding cache-line-size = <64>; 3518a12cf5c3SThierry Reding cache-sets = <2048>; 351927f1568bSPierre Gondois cache-level = <3>; 3520a12cf5c3SThierry Reding }; 3521a12cf5c3SThierry Reding 3522a12cf5c3SThierry Reding l3c1: l3-cache1 { 352327f1568bSPierre Gondois compatible = "cache"; 352427f1568bSPierre Gondois cache-unified; 3525a12cf5c3SThierry Reding cache-size = <2097152>; 3526a12cf5c3SThierry Reding cache-line-size = <64>; 3527a12cf5c3SThierry Reding cache-sets = <2048>; 352827f1568bSPierre Gondois cache-level = <3>; 3529a12cf5c3SThierry Reding }; 3530a12cf5c3SThierry Reding 3531a12cf5c3SThierry Reding l3c2: l3-cache2 { 353227f1568bSPierre Gondois compatible = "cache"; 353327f1568bSPierre Gondois cache-unified; 3534a12cf5c3SThierry Reding cache-size = <2097152>; 3535a12cf5c3SThierry Reding cache-line-size = <64>; 3536a12cf5c3SThierry Reding cache-sets = <2048>; 353727f1568bSPierre Gondois cache-level = <3>; 3538a12cf5c3SThierry Reding }; 3539a12cf5c3SThierry Reding }; 3540a12cf5c3SThierry Reding 35418e0ae0fbSJon Hunter dsu-pmu0 { 35428e0ae0fbSJon Hunter compatible = "arm,dsu-pmu"; 35438e0ae0fbSJon Hunter interrupts = <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>; 35448e0ae0fbSJon Hunter cpus = <&cpu0_0>, <&cpu0_1>, <&cpu0_2>, <&cpu0_3>; 35458e0ae0fbSJon Hunter }; 35468e0ae0fbSJon Hunter 35478e0ae0fbSJon Hunter dsu-pmu1 { 35488e0ae0fbSJon Hunter compatible = "arm,dsu-pmu"; 35498e0ae0fbSJon Hunter interrupts = <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>; 35508e0ae0fbSJon Hunter cpus = <&cpu1_0>, <&cpu1_1>, <&cpu1_2>, <&cpu1_3>; 35518e0ae0fbSJon Hunter }; 35528e0ae0fbSJon Hunter 35538e0ae0fbSJon Hunter dsu-pmu2 { 35548e0ae0fbSJon Hunter compatible = "arm,dsu-pmu"; 35558e0ae0fbSJon Hunter interrupts = <GIC_SPI 549 IRQ_TYPE_LEVEL_HIGH>; 35568e0ae0fbSJon Hunter cpus = <&cpu2_0>, <&cpu2_1>, <&cpu2_2>, <&cpu2_3>; 35578e0ae0fbSJon Hunter }; 35588e0ae0fbSJon Hunter 3559a12cf5c3SThierry Reding pmu { 3560a12cf5c3SThierry Reding compatible = "arm,cortex-a78-pmu"; 3561a12cf5c3SThierry Reding interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 3562a12cf5c3SThierry Reding status = "okay"; 356363944891SThierry Reding }; 356463944891SThierry Reding 356563944891SThierry Reding psci { 356663944891SThierry Reding compatible = "arm,psci-1.0"; 356763944891SThierry Reding status = "okay"; 356863944891SThierry Reding method = "smc"; 356963944891SThierry Reding }; 357063944891SThierry Reding 357106ad2ec4SMikko Perttunen tcu: serial { 357206ad2ec4SMikko Perttunen compatible = "nvidia,tegra234-tcu", "nvidia,tegra194-tcu"; 357306ad2ec4SMikko Perttunen mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 357406ad2ec4SMikko Perttunen <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 357506ad2ec4SMikko Perttunen mbox-names = "rx", "tx"; 357606ad2ec4SMikko Perttunen status = "disabled"; 357706ad2ec4SMikko Perttunen }; 357806ad2ec4SMikko Perttunen 357909614acdSSameer Pujar sound { 358009614acdSSameer Pujar status = "disabled"; 358109614acdSSameer Pujar 358209614acdSSameer Pujar clocks = <&bpmp TEGRA234_CLK_PLLA>, 358309614acdSSameer Pujar <&bpmp TEGRA234_CLK_PLLA_OUT0>; 358409614acdSSameer Pujar clock-names = "pll_a", "plla_out0"; 358509614acdSSameer Pujar assigned-clocks = <&bpmp TEGRA234_CLK_PLLA>, 358609614acdSSameer Pujar <&bpmp TEGRA234_CLK_PLLA_OUT0>, 358709614acdSSameer Pujar <&bpmp TEGRA234_CLK_AUD_MCLK>; 358809614acdSSameer Pujar assigned-clock-parents = <0>, 358909614acdSSameer Pujar <&bpmp TEGRA234_CLK_PLLA>, 359009614acdSSameer Pujar <&bpmp TEGRA234_CLK_PLLA_OUT0>; 359109614acdSSameer Pujar }; 359209614acdSSameer Pujar 359309d99078SThierry Reding thermal-zones { 359409d99078SThierry Reding cpu-thermal { 359509d99078SThierry Reding thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_CPU>; 359609d99078SThierry Reding status = "disabled"; 359709d99078SThierry Reding }; 359809d99078SThierry Reding 359909d99078SThierry Reding gpu-thermal { 360009d99078SThierry Reding thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_GPU>; 360109d99078SThierry Reding status = "disabled"; 360209d99078SThierry Reding }; 360309d99078SThierry Reding 360409d99078SThierry Reding cv0-thermal { 360509d99078SThierry Reding thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_CV0>; 360609d99078SThierry Reding status = "disabled"; 360709d99078SThierry Reding }; 360809d99078SThierry Reding 360909d99078SThierry Reding cv1-thermal { 361009d99078SThierry Reding thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_CV1>; 361109d99078SThierry Reding status = "disabled"; 361209d99078SThierry Reding }; 361309d99078SThierry Reding 361409d99078SThierry Reding cv2-thermal { 361509d99078SThierry Reding thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_CV2>; 361609d99078SThierry Reding status = "disabled"; 361709d99078SThierry Reding }; 361809d99078SThierry Reding 361909d99078SThierry Reding soc0-thermal { 362009d99078SThierry Reding thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_SOC0>; 362109d99078SThierry Reding status = "disabled"; 362209d99078SThierry Reding }; 362309d99078SThierry Reding 362409d99078SThierry Reding soc1-thermal { 362509d99078SThierry Reding thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_SOC1>; 362609d99078SThierry Reding status = "disabled"; 362709d99078SThierry Reding }; 362809d99078SThierry Reding 362909d99078SThierry Reding soc2-thermal { 363009d99078SThierry Reding thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_SOC2>; 363109d99078SThierry Reding status = "disabled"; 363209d99078SThierry Reding }; 363309d99078SThierry Reding 363409d99078SThierry Reding tj-thermal { 363509d99078SThierry Reding thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_TJ_MAX>; 363609d99078SThierry Reding status = "disabled"; 363709d99078SThierry Reding }; 363809d99078SThierry Reding }; 363909d99078SThierry Reding 364063944891SThierry Reding timer { 364163944891SThierry Reding compatible = "arm,armv8-timer"; 364263944891SThierry Reding interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 364363944891SThierry Reding <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 364463944891SThierry Reding <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 364563944891SThierry Reding <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 364663944891SThierry Reding interrupt-parent = <&gic>; 364763944891SThierry Reding always-on; 364863944891SThierry Reding }; 36491582e1d1SSumit Gupta 36501582e1d1SSumit Gupta cl0_opp_tbl: opp-table-cluster0 { 36511582e1d1SSumit Gupta compatible = "operating-points-v2"; 36521582e1d1SSumit Gupta opp-shared; 36531582e1d1SSumit Gupta 36541582e1d1SSumit Gupta cl0_ch1_opp1: opp-115200000 { 36551582e1d1SSumit Gupta opp-hz = /bits/ 64 <115200000>; 36561582e1d1SSumit Gupta opp-peak-kBps = <816000>; 36571582e1d1SSumit Gupta }; 36581582e1d1SSumit Gupta 365920515700SSumit Gupta cl0_ch1_opp2: opp-192000000 { 366020515700SSumit Gupta opp-hz = /bits/ 64 <192000000>; 366120515700SSumit Gupta opp-peak-kBps = <816000>; 366220515700SSumit Gupta }; 366320515700SSumit Gupta 366420515700SSumit Gupta cl0_ch1_opp3: opp-268800000 { 36651582e1d1SSumit Gupta opp-hz = /bits/ 64 <268800000>; 36661582e1d1SSumit Gupta opp-peak-kBps = <816000>; 36671582e1d1SSumit Gupta }; 36681582e1d1SSumit Gupta 366920515700SSumit Gupta cl0_ch1_opp4: opp-345600000 { 367020515700SSumit Gupta opp-hz = /bits/ 64 <345600000>; 367120515700SSumit Gupta opp-peak-kBps = <816000>; 367220515700SSumit Gupta }; 367320515700SSumit Gupta 367420515700SSumit Gupta cl0_ch1_opp5: opp-422400000 { 36751582e1d1SSumit Gupta opp-hz = /bits/ 64 <422400000>; 36761582e1d1SSumit Gupta opp-peak-kBps = <816000>; 36771582e1d1SSumit Gupta }; 36781582e1d1SSumit Gupta 367920515700SSumit Gupta cl0_ch1_opp6: opp-499200000 { 368020515700SSumit Gupta opp-hz = /bits/ 64 <499200000>; 368120515700SSumit Gupta opp-peak-kBps = <816000>; 368220515700SSumit Gupta }; 368320515700SSumit Gupta 368420515700SSumit Gupta cl0_ch1_opp7: opp-576000000 { 36851582e1d1SSumit Gupta opp-hz = /bits/ 64 <576000000>; 36861582e1d1SSumit Gupta opp-peak-kBps = <816000>; 36871582e1d1SSumit Gupta }; 36881582e1d1SSumit Gupta 368920515700SSumit Gupta cl0_ch1_opp8: opp-652800000 { 369020515700SSumit Gupta opp-hz = /bits/ 64 <652800000>; 369120515700SSumit Gupta opp-peak-kBps = <816000>; 369220515700SSumit Gupta }; 369320515700SSumit Gupta 369420515700SSumit Gupta cl0_ch1_opp9: opp-729600000 { 36951582e1d1SSumit Gupta opp-hz = /bits/ 64 <729600000>; 36961582e1d1SSumit Gupta opp-peak-kBps = <816000>; 36971582e1d1SSumit Gupta }; 36981582e1d1SSumit Gupta 369920515700SSumit Gupta cl0_ch1_opp10: opp-806400000 { 370020515700SSumit Gupta opp-hz = /bits/ 64 <806400000>; 370120515700SSumit Gupta opp-peak-kBps = <816000>; 370220515700SSumit Gupta }; 370320515700SSumit Gupta 370420515700SSumit Gupta cl0_ch1_opp11: opp-883200000 { 37051582e1d1SSumit Gupta opp-hz = /bits/ 64 <883200000>; 37061582e1d1SSumit Gupta opp-peak-kBps = <816000>; 37071582e1d1SSumit Gupta }; 37081582e1d1SSumit Gupta 370920515700SSumit Gupta cl0_ch1_opp12: opp-960000000 { 371020515700SSumit Gupta opp-hz = /bits/ 64 <960000000>; 371120515700SSumit Gupta opp-peak-kBps = <816000>; 371220515700SSumit Gupta }; 371320515700SSumit Gupta 371420515700SSumit Gupta cl0_ch1_opp13: opp-1036800000 { 37151582e1d1SSumit Gupta opp-hz = /bits/ 64 <1036800000>; 37161582e1d1SSumit Gupta opp-peak-kBps = <816000>; 37171582e1d1SSumit Gupta }; 37181582e1d1SSumit Gupta 371920515700SSumit Gupta cl0_ch1_opp14: opp-1113600000 { 372020515700SSumit Gupta opp-hz = /bits/ 64 <1113600000>; 372120515700SSumit Gupta opp-peak-kBps = <1632000>; 37221582e1d1SSumit Gupta }; 37231582e1d1SSumit Gupta 372420515700SSumit Gupta cl0_ch1_opp15: opp-1190400000 { 372520515700SSumit Gupta opp-hz = /bits/ 64 <1190400000>; 372620515700SSumit Gupta opp-peak-kBps = <1632000>; 372720515700SSumit Gupta }; 372820515700SSumit Gupta 372920515700SSumit Gupta cl0_ch1_opp16: opp-1267200000 { 373020515700SSumit Gupta opp-hz = /bits/ 64 <1267200000>; 373120515700SSumit Gupta opp-peak-kBps = <1632000>; 373220515700SSumit Gupta }; 373320515700SSumit Gupta 373420515700SSumit Gupta cl0_ch1_opp17: opp-1344000000 { 37351582e1d1SSumit Gupta opp-hz = /bits/ 64 <1344000000>; 37361582e1d1SSumit Gupta opp-peak-kBps = <1632000>; 37371582e1d1SSumit Gupta }; 37381582e1d1SSumit Gupta 373920515700SSumit Gupta cl0_ch1_opp18: opp-1420800000 { 374020515700SSumit Gupta opp-hz = /bits/ 64 <1420800000>; 37411582e1d1SSumit Gupta opp-peak-kBps = <1632000>; 37421582e1d1SSumit Gupta }; 37431582e1d1SSumit Gupta 374420515700SSumit Gupta cl0_ch1_opp19: opp-1497600000 { 374520515700SSumit Gupta opp-hz = /bits/ 64 <1497600000>; 374620515700SSumit Gupta opp-peak-kBps = <3200000>; 374720515700SSumit Gupta }; 374820515700SSumit Gupta 374920515700SSumit Gupta cl0_ch1_opp20: opp-1574400000 { 375020515700SSumit Gupta opp-hz = /bits/ 64 <1574400000>; 375120515700SSumit Gupta opp-peak-kBps = <3200000>; 375220515700SSumit Gupta }; 375320515700SSumit Gupta 375420515700SSumit Gupta cl0_ch1_opp21: opp-1651200000 { 37551582e1d1SSumit Gupta opp-hz = /bits/ 64 <1651200000>; 375620515700SSumit Gupta opp-peak-kBps = <3200000>; 37571582e1d1SSumit Gupta }; 37581582e1d1SSumit Gupta 375920515700SSumit Gupta cl0_ch1_opp22: opp-1728000000 { 376020515700SSumit Gupta opp-hz = /bits/ 64 <1728000000>; 376120515700SSumit Gupta opp-peak-kBps = <3200000>; 376220515700SSumit Gupta }; 376320515700SSumit Gupta 376420515700SSumit Gupta cl0_ch1_opp23: opp-1804800000 { 37651582e1d1SSumit Gupta opp-hz = /bits/ 64 <1804800000>; 376620515700SSumit Gupta opp-peak-kBps = <3200000>; 37671582e1d1SSumit Gupta }; 37681582e1d1SSumit Gupta 376920515700SSumit Gupta cl0_ch1_opp24: opp-1881600000 { 377020515700SSumit Gupta opp-hz = /bits/ 64 <1881600000>; 377120515700SSumit Gupta opp-peak-kBps = <3200000>; 377220515700SSumit Gupta }; 377320515700SSumit Gupta 377420515700SSumit Gupta cl0_ch1_opp25: opp-1958400000 { 37751582e1d1SSumit Gupta opp-hz = /bits/ 64 <1958400000>; 37761582e1d1SSumit Gupta opp-peak-kBps = <3200000>; 37771582e1d1SSumit Gupta }; 37781582e1d1SSumit Gupta 377920515700SSumit Gupta cl0_ch1_opp26: opp-2035200000 { 378020515700SSumit Gupta opp-hz = /bits/ 64 <2035200000>; 378120515700SSumit Gupta opp-peak-kBps = <3200000>; 378220515700SSumit Gupta }; 378320515700SSumit Gupta 378420515700SSumit Gupta cl0_ch1_opp27: opp-2112000000 { 37851582e1d1SSumit Gupta opp-hz = /bits/ 64 <2112000000>; 37861582e1d1SSumit Gupta opp-peak-kBps = <6400000>; 37871582e1d1SSumit Gupta }; 37881582e1d1SSumit Gupta 378920515700SSumit Gupta cl0_ch1_opp28: opp-2188800000 { 379020515700SSumit Gupta opp-hz = /bits/ 64 <2188800000>; 379120515700SSumit Gupta opp-peak-kBps = <6400000>; 379220515700SSumit Gupta }; 379320515700SSumit Gupta 379420515700SSumit Gupta cl0_ch1_opp29: opp-2201600000 { 37951582e1d1SSumit Gupta opp-hz = /bits/ 64 <2201600000>; 37961582e1d1SSumit Gupta opp-peak-kBps = <6400000>; 37971582e1d1SSumit Gupta }; 37981582e1d1SSumit Gupta }; 37991582e1d1SSumit Gupta 38001582e1d1SSumit Gupta cl1_opp_tbl: opp-table-cluster1 { 38011582e1d1SSumit Gupta compatible = "operating-points-v2"; 38021582e1d1SSumit Gupta opp-shared; 38031582e1d1SSumit Gupta 38041582e1d1SSumit Gupta cl1_ch1_opp1: opp-115200000 { 38051582e1d1SSumit Gupta opp-hz = /bits/ 64 <115200000>; 38061582e1d1SSumit Gupta opp-peak-kBps = <816000>; 38071582e1d1SSumit Gupta }; 38081582e1d1SSumit Gupta 380920515700SSumit Gupta cl1_ch1_opp2: opp-192000000 { 381020515700SSumit Gupta opp-hz = /bits/ 64 <192000000>; 381120515700SSumit Gupta opp-peak-kBps = <816000>; 381220515700SSumit Gupta }; 381320515700SSumit Gupta 381420515700SSumit Gupta cl1_ch1_opp3: opp-268800000 { 38151582e1d1SSumit Gupta opp-hz = /bits/ 64 <268800000>; 38161582e1d1SSumit Gupta opp-peak-kBps = <816000>; 38171582e1d1SSumit Gupta }; 38181582e1d1SSumit Gupta 381920515700SSumit Gupta cl1_ch1_opp4: opp-345600000 { 382020515700SSumit Gupta opp-hz = /bits/ 64 <345600000>; 382120515700SSumit Gupta opp-peak-kBps = <816000>; 382220515700SSumit Gupta }; 382320515700SSumit Gupta 382420515700SSumit Gupta cl1_ch1_opp5: opp-422400000 { 38251582e1d1SSumit Gupta opp-hz = /bits/ 64 <422400000>; 38261582e1d1SSumit Gupta opp-peak-kBps = <816000>; 38271582e1d1SSumit Gupta }; 38281582e1d1SSumit Gupta 382920515700SSumit Gupta cl1_ch1_opp6: opp-499200000 { 383020515700SSumit Gupta opp-hz = /bits/ 64 <499200000>; 383120515700SSumit Gupta opp-peak-kBps = <816000>; 383220515700SSumit Gupta }; 383320515700SSumit Gupta 383420515700SSumit Gupta cl1_ch1_opp7: opp-576000000 { 38351582e1d1SSumit Gupta opp-hz = /bits/ 64 <576000000>; 38361582e1d1SSumit Gupta opp-peak-kBps = <816000>; 38371582e1d1SSumit Gupta }; 38381582e1d1SSumit Gupta 383920515700SSumit Gupta cl1_ch1_opp8: opp-652800000 { 384020515700SSumit Gupta opp-hz = /bits/ 64 <652800000>; 384120515700SSumit Gupta opp-peak-kBps = <816000>; 384220515700SSumit Gupta }; 384320515700SSumit Gupta 384420515700SSumit Gupta cl1_ch1_opp9: opp-729600000 { 38451582e1d1SSumit Gupta opp-hz = /bits/ 64 <729600000>; 38461582e1d1SSumit Gupta opp-peak-kBps = <816000>; 38471582e1d1SSumit Gupta }; 38481582e1d1SSumit Gupta 384920515700SSumit Gupta cl1_ch1_opp10: opp-806400000 { 385020515700SSumit Gupta opp-hz = /bits/ 64 <806400000>; 385120515700SSumit Gupta opp-peak-kBps = <816000>; 385220515700SSumit Gupta }; 385320515700SSumit Gupta 385420515700SSumit Gupta cl1_ch1_opp11: opp-883200000 { 38551582e1d1SSumit Gupta opp-hz = /bits/ 64 <883200000>; 38561582e1d1SSumit Gupta opp-peak-kBps = <816000>; 38571582e1d1SSumit Gupta }; 38581582e1d1SSumit Gupta 385920515700SSumit Gupta cl1_ch1_opp12: opp-960000000 { 386020515700SSumit Gupta opp-hz = /bits/ 64 <960000000>; 386120515700SSumit Gupta opp-peak-kBps = <816000>; 386220515700SSumit Gupta }; 386320515700SSumit Gupta 386420515700SSumit Gupta cl1_ch1_opp13: opp-1036800000 { 38651582e1d1SSumit Gupta opp-hz = /bits/ 64 <1036800000>; 38661582e1d1SSumit Gupta opp-peak-kBps = <816000>; 38671582e1d1SSumit Gupta }; 38681582e1d1SSumit Gupta 386920515700SSumit Gupta cl1_ch1_opp14: opp-1113600000 { 387020515700SSumit Gupta opp-hz = /bits/ 64 <1113600000>; 387120515700SSumit Gupta opp-peak-kBps = <1632000>; 38721582e1d1SSumit Gupta }; 38731582e1d1SSumit Gupta 387420515700SSumit Gupta cl1_ch1_opp15: opp-1190400000 { 387520515700SSumit Gupta opp-hz = /bits/ 64 <1190400000>; 387620515700SSumit Gupta opp-peak-kBps = <1632000>; 387720515700SSumit Gupta }; 387820515700SSumit Gupta 387920515700SSumit Gupta cl1_ch1_opp16: opp-1267200000 { 388020515700SSumit Gupta opp-hz = /bits/ 64 <1267200000>; 388120515700SSumit Gupta opp-peak-kBps = <1632000>; 388220515700SSumit Gupta }; 388320515700SSumit Gupta 388420515700SSumit Gupta cl1_ch1_opp17: opp-1344000000 { 38851582e1d1SSumit Gupta opp-hz = /bits/ 64 <1344000000>; 38861582e1d1SSumit Gupta opp-peak-kBps = <1632000>; 38871582e1d1SSumit Gupta }; 38881582e1d1SSumit Gupta 388920515700SSumit Gupta cl1_ch1_opp18: opp-1420800000 { 389020515700SSumit Gupta opp-hz = /bits/ 64 <1420800000>; 38911582e1d1SSumit Gupta opp-peak-kBps = <1632000>; 38921582e1d1SSumit Gupta }; 38931582e1d1SSumit Gupta 389420515700SSumit Gupta cl1_ch1_opp19: opp-1497600000 { 389520515700SSumit Gupta opp-hz = /bits/ 64 <1497600000>; 389620515700SSumit Gupta opp-peak-kBps = <3200000>; 389720515700SSumit Gupta }; 389820515700SSumit Gupta 389920515700SSumit Gupta cl1_ch1_opp20: opp-1574400000 { 390020515700SSumit Gupta opp-hz = /bits/ 64 <1574400000>; 390120515700SSumit Gupta opp-peak-kBps = <3200000>; 390220515700SSumit Gupta }; 390320515700SSumit Gupta 390420515700SSumit Gupta cl1_ch1_opp21: opp-1651200000 { 39051582e1d1SSumit Gupta opp-hz = /bits/ 64 <1651200000>; 390620515700SSumit Gupta opp-peak-kBps = <3200000>; 39071582e1d1SSumit Gupta }; 39081582e1d1SSumit Gupta 390920515700SSumit Gupta cl1_ch1_opp22: opp-1728000000 { 391020515700SSumit Gupta opp-hz = /bits/ 64 <1728000000>; 391120515700SSumit Gupta opp-peak-kBps = <3200000>; 391220515700SSumit Gupta }; 391320515700SSumit Gupta 391420515700SSumit Gupta cl1_ch1_opp23: opp-1804800000 { 39151582e1d1SSumit Gupta opp-hz = /bits/ 64 <1804800000>; 391620515700SSumit Gupta opp-peak-kBps = <3200000>; 39171582e1d1SSumit Gupta }; 39181582e1d1SSumit Gupta 391920515700SSumit Gupta cl1_ch1_opp24: opp-1881600000 { 392020515700SSumit Gupta opp-hz = /bits/ 64 <1881600000>; 392120515700SSumit Gupta opp-peak-kBps = <3200000>; 392220515700SSumit Gupta }; 392320515700SSumit Gupta 392420515700SSumit Gupta cl1_ch1_opp25: opp-1958400000 { 39251582e1d1SSumit Gupta opp-hz = /bits/ 64 <1958400000>; 39261582e1d1SSumit Gupta opp-peak-kBps = <3200000>; 39271582e1d1SSumit Gupta }; 39281582e1d1SSumit Gupta 392920515700SSumit Gupta cl1_ch1_opp26: opp-2035200000 { 393020515700SSumit Gupta opp-hz = /bits/ 64 <2035200000>; 393120515700SSumit Gupta opp-peak-kBps = <3200000>; 393220515700SSumit Gupta }; 393320515700SSumit Gupta 393420515700SSumit Gupta cl1_ch1_opp27: opp-2112000000 { 39351582e1d1SSumit Gupta opp-hz = /bits/ 64 <2112000000>; 39361582e1d1SSumit Gupta opp-peak-kBps = <6400000>; 39371582e1d1SSumit Gupta }; 39381582e1d1SSumit Gupta 393920515700SSumit Gupta cl1_ch1_opp28: opp-2188800000 { 394020515700SSumit Gupta opp-hz = /bits/ 64 <2188800000>; 394120515700SSumit Gupta opp-peak-kBps = <6400000>; 394220515700SSumit Gupta }; 394320515700SSumit Gupta 394420515700SSumit Gupta cl1_ch1_opp29: opp-2201600000 { 39451582e1d1SSumit Gupta opp-hz = /bits/ 64 <2201600000>; 39461582e1d1SSumit Gupta opp-peak-kBps = <6400000>; 39471582e1d1SSumit Gupta }; 39481582e1d1SSumit Gupta }; 39491582e1d1SSumit Gupta 39501582e1d1SSumit Gupta cl2_opp_tbl: opp-table-cluster2 { 39511582e1d1SSumit Gupta compatible = "operating-points-v2"; 39521582e1d1SSumit Gupta opp-shared; 39531582e1d1SSumit Gupta 39541582e1d1SSumit Gupta cl2_ch1_opp1: opp-115200000 { 39551582e1d1SSumit Gupta opp-hz = /bits/ 64 <115200000>; 39561582e1d1SSumit Gupta opp-peak-kBps = <816000>; 39571582e1d1SSumit Gupta }; 39581582e1d1SSumit Gupta 395920515700SSumit Gupta cl2_ch1_opp2: opp-192000000 { 396020515700SSumit Gupta opp-hz = /bits/ 64 <192000000>; 396120515700SSumit Gupta opp-peak-kBps = <816000>; 396220515700SSumit Gupta }; 396320515700SSumit Gupta 396420515700SSumit Gupta cl2_ch1_opp3: opp-268800000 { 39651582e1d1SSumit Gupta opp-hz = /bits/ 64 <268800000>; 39661582e1d1SSumit Gupta opp-peak-kBps = <816000>; 39671582e1d1SSumit Gupta }; 39681582e1d1SSumit Gupta 396920515700SSumit Gupta cl2_ch1_opp4: opp-345600000 { 397020515700SSumit Gupta opp-hz = /bits/ 64 <345600000>; 397120515700SSumit Gupta opp-peak-kBps = <816000>; 397220515700SSumit Gupta }; 397320515700SSumit Gupta 397420515700SSumit Gupta cl2_ch1_opp5: opp-422400000 { 39751582e1d1SSumit Gupta opp-hz = /bits/ 64 <422400000>; 39761582e1d1SSumit Gupta opp-peak-kBps = <816000>; 39771582e1d1SSumit Gupta }; 39781582e1d1SSumit Gupta 397920515700SSumit Gupta cl2_ch1_opp6: opp-499200000 { 398020515700SSumit Gupta opp-hz = /bits/ 64 <499200000>; 398120515700SSumit Gupta opp-peak-kBps = <816000>; 398220515700SSumit Gupta }; 398320515700SSumit Gupta 398420515700SSumit Gupta cl2_ch1_opp7: opp-576000000 { 39851582e1d1SSumit Gupta opp-hz = /bits/ 64 <576000000>; 39861582e1d1SSumit Gupta opp-peak-kBps = <816000>; 39871582e1d1SSumit Gupta }; 39881582e1d1SSumit Gupta 398920515700SSumit Gupta cl2_ch1_opp8: opp-652800000 { 399020515700SSumit Gupta opp-hz = /bits/ 64 <652800000>; 399120515700SSumit Gupta opp-peak-kBps = <816000>; 399220515700SSumit Gupta }; 399320515700SSumit Gupta 399420515700SSumit Gupta cl2_ch1_opp9: opp-729600000 { 39951582e1d1SSumit Gupta opp-hz = /bits/ 64 <729600000>; 39961582e1d1SSumit Gupta opp-peak-kBps = <816000>; 39971582e1d1SSumit Gupta }; 39981582e1d1SSumit Gupta 399920515700SSumit Gupta cl2_ch1_opp10: opp-806400000 { 400020515700SSumit Gupta opp-hz = /bits/ 64 <806400000>; 400120515700SSumit Gupta opp-peak-kBps = <816000>; 400220515700SSumit Gupta }; 400320515700SSumit Gupta 400420515700SSumit Gupta cl2_ch1_opp11: opp-883200000 { 40051582e1d1SSumit Gupta opp-hz = /bits/ 64 <883200000>; 40061582e1d1SSumit Gupta opp-peak-kBps = <816000>; 40071582e1d1SSumit Gupta }; 40081582e1d1SSumit Gupta 400920515700SSumit Gupta cl2_ch1_opp12: opp-960000000 { 401020515700SSumit Gupta opp-hz = /bits/ 64 <960000000>; 401120515700SSumit Gupta opp-peak-kBps = <816000>; 401220515700SSumit Gupta }; 401320515700SSumit Gupta 401420515700SSumit Gupta cl2_ch1_opp13: opp-1036800000 { 40151582e1d1SSumit Gupta opp-hz = /bits/ 64 <1036800000>; 40161582e1d1SSumit Gupta opp-peak-kBps = <816000>; 40171582e1d1SSumit Gupta }; 40181582e1d1SSumit Gupta 401920515700SSumit Gupta cl2_ch1_opp14: opp-1113600000 { 402020515700SSumit Gupta opp-hz = /bits/ 64 <1113600000>; 402120515700SSumit Gupta opp-peak-kBps = <1632000>; 40221582e1d1SSumit Gupta }; 40231582e1d1SSumit Gupta 402420515700SSumit Gupta cl2_ch1_opp15: opp-1190400000 { 402520515700SSumit Gupta opp-hz = /bits/ 64 <1190400000>; 402620515700SSumit Gupta opp-peak-kBps = <1632000>; 402720515700SSumit Gupta }; 402820515700SSumit Gupta 402920515700SSumit Gupta cl2_ch1_opp16: opp-1267200000 { 403020515700SSumit Gupta opp-hz = /bits/ 64 <1267200000>; 403120515700SSumit Gupta opp-peak-kBps = <1632000>; 403220515700SSumit Gupta }; 403320515700SSumit Gupta 403420515700SSumit Gupta cl2_ch1_opp17: opp-1344000000 { 40351582e1d1SSumit Gupta opp-hz = /bits/ 64 <1344000000>; 40361582e1d1SSumit Gupta opp-peak-kBps = <1632000>; 40371582e1d1SSumit Gupta }; 40381582e1d1SSumit Gupta 403920515700SSumit Gupta cl2_ch1_opp18: opp-1420800000 { 404020515700SSumit Gupta opp-hz = /bits/ 64 <1420800000>; 40411582e1d1SSumit Gupta opp-peak-kBps = <1632000>; 40421582e1d1SSumit Gupta }; 40431582e1d1SSumit Gupta 404420515700SSumit Gupta cl2_ch1_opp19: opp-1497600000 { 404520515700SSumit Gupta opp-hz = /bits/ 64 <1497600000>; 404620515700SSumit Gupta opp-peak-kBps = <3200000>; 404720515700SSumit Gupta }; 404820515700SSumit Gupta 404920515700SSumit Gupta cl2_ch1_opp20: opp-1574400000 { 405020515700SSumit Gupta opp-hz = /bits/ 64 <1574400000>; 405120515700SSumit Gupta opp-peak-kBps = <3200000>; 405220515700SSumit Gupta }; 405320515700SSumit Gupta 405420515700SSumit Gupta cl2_ch1_opp21: opp-1651200000 { 40551582e1d1SSumit Gupta opp-hz = /bits/ 64 <1651200000>; 405620515700SSumit Gupta opp-peak-kBps = <3200000>; 40571582e1d1SSumit Gupta }; 40581582e1d1SSumit Gupta 405920515700SSumit Gupta cl2_ch1_opp22: opp-1728000000 { 406020515700SSumit Gupta opp-hz = /bits/ 64 <1728000000>; 406120515700SSumit Gupta opp-peak-kBps = <3200000>; 406220515700SSumit Gupta }; 406320515700SSumit Gupta 406420515700SSumit Gupta cl2_ch1_opp23: opp-1804800000 { 40651582e1d1SSumit Gupta opp-hz = /bits/ 64 <1804800000>; 406620515700SSumit Gupta opp-peak-kBps = <3200000>; 40671582e1d1SSumit Gupta }; 40681582e1d1SSumit Gupta 406920515700SSumit Gupta cl2_ch1_opp24: opp-1881600000 { 407020515700SSumit Gupta opp-hz = /bits/ 64 <1881600000>; 407120515700SSumit Gupta opp-peak-kBps = <3200000>; 407220515700SSumit Gupta }; 407320515700SSumit Gupta 407420515700SSumit Gupta cl2_ch1_opp25: opp-1958400000 { 40751582e1d1SSumit Gupta opp-hz = /bits/ 64 <1958400000>; 40761582e1d1SSumit Gupta opp-peak-kBps = <3200000>; 40771582e1d1SSumit Gupta }; 40781582e1d1SSumit Gupta 407920515700SSumit Gupta cl2_ch1_opp26: opp-2035200000 { 408020515700SSumit Gupta opp-hz = /bits/ 64 <2035200000>; 408120515700SSumit Gupta opp-peak-kBps = <3200000>; 408220515700SSumit Gupta }; 408320515700SSumit Gupta 408420515700SSumit Gupta cl2_ch1_opp27: opp-2112000000 { 40851582e1d1SSumit Gupta opp-hz = /bits/ 64 <2112000000>; 40861582e1d1SSumit Gupta opp-peak-kBps = <6400000>; 40871582e1d1SSumit Gupta }; 40881582e1d1SSumit Gupta 408920515700SSumit Gupta cl2_ch1_opp28: opp-2188800000 { 409020515700SSumit Gupta opp-hz = /bits/ 64 <2188800000>; 409120515700SSumit Gupta opp-peak-kBps = <6400000>; 409220515700SSumit Gupta }; 409320515700SSumit Gupta 409420515700SSumit Gupta cl2_ch1_opp29: opp-2201600000 { 40951582e1d1SSumit Gupta opp-hz = /bits/ 64 <2201600000>; 40961582e1d1SSumit Gupta opp-peak-kBps = <6400000>; 40971582e1d1SSumit Gupta }; 40981582e1d1SSumit Gupta }; 409963944891SThierry Reding}; 4100