1#include <dt-bindings/clock/tegra210-car.h> 2#include <dt-bindings/gpio/tegra-gpio.h> 3#include <dt-bindings/memory/tegra210-mc.h> 4#include <dt-bindings/pinctrl/pinctrl-tegra.h> 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6#include <dt-bindings/thermal/tegra124-soctherm.h> 7 8/ { 9 compatible = "nvidia,tegra210"; 10 interrupt-parent = <&lic>; 11 #address-cells = <2>; 12 #size-cells = <2>; 13 14 host1x@50000000 { 15 compatible = "nvidia,tegra210-host1x", "simple-bus"; 16 reg = <0x0 0x50000000 0x0 0x00034000>; 17 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 18 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ 19 clocks = <&tegra_car TEGRA210_CLK_HOST1X>; 20 clock-names = "host1x"; 21 resets = <&tegra_car 28>; 22 reset-names = "host1x"; 23 24 #address-cells = <2>; 25 #size-cells = <2>; 26 27 ranges = <0x0 0x54000000 0x0 0x54000000 0x0 0x01000000>; 28 29 dpaux1: dpaux@54040000 { 30 compatible = "nvidia,tegra210-dpaux"; 31 reg = <0x0 0x54040000 0x0 0x00040000>; 32 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 33 clocks = <&tegra_car TEGRA210_CLK_DPAUX1>, 34 <&tegra_car TEGRA210_CLK_PLL_DP>; 35 clock-names = "dpaux", "parent"; 36 resets = <&tegra_car 207>; 37 reset-names = "dpaux"; 38 status = "disabled"; 39 40 state_dpaux1_aux: pinmux-aux { 41 groups = "dpaux-io"; 42 function = "aux"; 43 }; 44 45 state_dpaux1_i2c: pinmux-i2c { 46 groups = "dpaux-io"; 47 function = "i2c"; 48 }; 49 50 state_dpaux1_off: pinmux-off { 51 groups = "dpaux-io"; 52 function = "off"; 53 }; 54 55 i2c-bus { 56 #address-cells = <1>; 57 #size-cells = <0>; 58 }; 59 }; 60 61 vi@54080000 { 62 compatible = "nvidia,tegra210-vi"; 63 reg = <0x0 0x54080000 0x0 0x00040000>; 64 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 65 status = "disabled"; 66 }; 67 68 tsec@54100000 { 69 compatible = "nvidia,tegra210-tsec"; 70 reg = <0x0 0x54100000 0x0 0x00040000>; 71 }; 72 73 dc@54200000 { 74 compatible = "nvidia,tegra210-dc"; 75 reg = <0x0 0x54200000 0x0 0x00040000>; 76 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 77 clocks = <&tegra_car TEGRA210_CLK_DISP1>, 78 <&tegra_car TEGRA210_CLK_PLL_P>; 79 clock-names = "dc", "parent"; 80 resets = <&tegra_car 27>; 81 reset-names = "dc"; 82 83 iommus = <&mc TEGRA_SWGROUP_DC>; 84 85 nvidia,head = <0>; 86 }; 87 88 dc@54240000 { 89 compatible = "nvidia,tegra210-dc"; 90 reg = <0x0 0x54240000 0x0 0x00040000>; 91 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 92 clocks = <&tegra_car TEGRA210_CLK_DISP2>, 93 <&tegra_car TEGRA210_CLK_PLL_P>; 94 clock-names = "dc", "parent"; 95 resets = <&tegra_car 26>; 96 reset-names = "dc"; 97 98 iommus = <&mc TEGRA_SWGROUP_DCB>; 99 100 nvidia,head = <1>; 101 }; 102 103 dsi@54300000 { 104 compatible = "nvidia,tegra210-dsi"; 105 reg = <0x0 0x54300000 0x0 0x00040000>; 106 clocks = <&tegra_car TEGRA210_CLK_DSIA>, 107 <&tegra_car TEGRA210_CLK_DSIALP>, 108 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; 109 clock-names = "dsi", "lp", "parent"; 110 resets = <&tegra_car 48>; 111 reset-names = "dsi"; 112 nvidia,mipi-calibrate = <&mipi 0x0c0>; /* DSIA & DSIB pads */ 113 114 status = "disabled"; 115 116 #address-cells = <1>; 117 #size-cells = <0>; 118 }; 119 120 vic@54340000 { 121 compatible = "nvidia,tegra210-vic"; 122 reg = <0x0 0x54340000 0x0 0x00040000>; 123 status = "disabled"; 124 }; 125 126 nvjpg@54380000 { 127 compatible = "nvidia,tegra210-nvjpg"; 128 reg = <0x0 0x54380000 0x0 0x00040000>; 129 status = "disabled"; 130 }; 131 132 dsi@54400000 { 133 compatible = "nvidia,tegra210-dsi"; 134 reg = <0x0 0x54400000 0x0 0x00040000>; 135 clocks = <&tegra_car TEGRA210_CLK_DSIB>, 136 <&tegra_car TEGRA210_CLK_DSIBLP>, 137 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; 138 clock-names = "dsi", "lp", "parent"; 139 resets = <&tegra_car 82>; 140 reset-names = "dsi"; 141 nvidia,mipi-calibrate = <&mipi 0x300>; /* DSIC & DSID pads */ 142 143 status = "disabled"; 144 145 #address-cells = <1>; 146 #size-cells = <0>; 147 }; 148 149 nvdec@54480000 { 150 compatible = "nvidia,tegra210-nvdec"; 151 reg = <0x0 0x54480000 0x0 0x00040000>; 152 status = "disabled"; 153 }; 154 155 nvenc@544c0000 { 156 compatible = "nvidia,tegra210-nvenc"; 157 reg = <0x0 0x544c0000 0x0 0x00040000>; 158 status = "disabled"; 159 }; 160 161 tsec@54500000 { 162 compatible = "nvidia,tegra210-tsec"; 163 reg = <0x0 0x54500000 0x0 0x00040000>; 164 status = "disabled"; 165 }; 166 167 sor@54540000 { 168 compatible = "nvidia,tegra210-sor"; 169 reg = <0x0 0x54540000 0x0 0x00040000>; 170 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 171 clocks = <&tegra_car TEGRA210_CLK_SOR0>, 172 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>, 173 <&tegra_car TEGRA210_CLK_PLL_DP>, 174 <&tegra_car TEGRA210_CLK_SOR_SAFE>; 175 clock-names = "sor", "parent", "dp", "safe"; 176 resets = <&tegra_car 182>; 177 reset-names = "sor"; 178 pinctrl-0 = <&state_dpaux_aux>; 179 pinctrl-1 = <&state_dpaux_i2c>; 180 pinctrl-2 = <&state_dpaux_off>; 181 pinctrl-names = "aux", "i2c", "off"; 182 status = "disabled"; 183 }; 184 185 sor@54580000 { 186 compatible = "nvidia,tegra210-sor1"; 187 reg = <0x0 0x54580000 0x0 0x00040000>; 188 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 189 clocks = <&tegra_car TEGRA210_CLK_SOR1>, 190 <&tegra_car TEGRA210_CLK_SOR1_SRC>, 191 <&tegra_car TEGRA210_CLK_PLL_D2_OUT0>, 192 <&tegra_car TEGRA210_CLK_PLL_DP>, 193 <&tegra_car TEGRA210_CLK_SOR_SAFE>; 194 clock-names = "sor", "source", "parent", "dp", "safe"; 195 resets = <&tegra_car 183>; 196 reset-names = "sor"; 197 pinctrl-0 = <&state_dpaux1_aux>; 198 pinctrl-1 = <&state_dpaux1_i2c>; 199 pinctrl-2 = <&state_dpaux1_off>; 200 pinctrl-names = "aux", "i2c", "off"; 201 status = "disabled"; 202 }; 203 204 dpaux: dpaux@545c0000 { 205 compatible = "nvidia,tegra124-dpaux"; 206 reg = <0x0 0x545c0000 0x0 0x00040000>; 207 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 208 clocks = <&tegra_car TEGRA210_CLK_DPAUX>, 209 <&tegra_car TEGRA210_CLK_PLL_DP>; 210 clock-names = "dpaux", "parent"; 211 resets = <&tegra_car 181>; 212 reset-names = "dpaux"; 213 status = "disabled"; 214 215 state_dpaux_aux: pinmux-aux { 216 groups = "dpaux-io"; 217 function = "aux"; 218 }; 219 220 state_dpaux_i2c: pinmux-i2c { 221 groups = "dpaux-io"; 222 function = "i2c"; 223 }; 224 225 state_dpaux_off: pinmux-off { 226 groups = "dpaux-io"; 227 function = "off"; 228 }; 229 230 i2c-bus { 231 #address-cells = <1>; 232 #size-cells = <0>; 233 }; 234 }; 235 236 isp@54600000 { 237 compatible = "nvidia,tegra210-isp"; 238 reg = <0x0 0x54600000 0x0 0x00040000>; 239 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 240 status = "disabled"; 241 }; 242 243 isp@54680000 { 244 compatible = "nvidia,tegra210-isp"; 245 reg = <0x0 0x54680000 0x0 0x00040000>; 246 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 247 status = "disabled"; 248 }; 249 250 i2c@546c0000 { 251 compatible = "nvidia,tegra210-i2c-vi"; 252 reg = <0x0 0x546c0000 0x0 0x00040000>; 253 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 254 status = "disabled"; 255 }; 256 }; 257 258 gic: interrupt-controller@50041000 { 259 compatible = "arm,gic-400"; 260 #interrupt-cells = <3>; 261 interrupt-controller; 262 reg = <0x0 0x50041000 0x0 0x1000>, 263 <0x0 0x50042000 0x0 0x2000>, 264 <0x0 0x50044000 0x0 0x2000>, 265 <0x0 0x50046000 0x0 0x2000>; 266 interrupts = <GIC_PPI 9 267 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 268 interrupt-parent = <&gic>; 269 }; 270 271 gpu@57000000 { 272 compatible = "nvidia,gm20b"; 273 reg = <0x0 0x57000000 0x0 0x01000000>, 274 <0x0 0x58000000 0x0 0x01000000>; 275 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 276 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 277 interrupt-names = "stall", "nonstall"; 278 clocks = <&tegra_car TEGRA210_CLK_GPU>, 279 <&tegra_car TEGRA210_CLK_PLL_P_OUT5>, 280 <&tegra_car TEGRA210_CLK_PLL_G_REF>; 281 clock-names = "gpu", "pwr", "ref"; 282 resets = <&tegra_car 184>; 283 reset-names = "gpu"; 284 285 iommus = <&mc TEGRA_SWGROUP_GPU>; 286 287 status = "disabled"; 288 }; 289 290 lic: interrupt-controller@60004000 { 291 compatible = "nvidia,tegra210-ictlr"; 292 reg = <0x0 0x60004000 0x0 0x40>, /* primary controller */ 293 <0x0 0x60004100 0x0 0x40>, /* secondary controller */ 294 <0x0 0x60004200 0x0 0x40>, /* tertiary controller */ 295 <0x0 0x60004300 0x0 0x40>, /* quaternary controller */ 296 <0x0 0x60004400 0x0 0x40>, /* quinary controller */ 297 <0x0 0x60004500 0x0 0x40>; /* senary controller */ 298 interrupt-controller; 299 #interrupt-cells = <3>; 300 interrupt-parent = <&gic>; 301 }; 302 303 timer@60005000 { 304 compatible = "nvidia,tegra210-timer", "nvidia,tegra20-timer"; 305 reg = <0x0 0x60005000 0x0 0x400>; 306 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 307 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 308 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 309 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 310 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 311 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 312 clocks = <&tegra_car TEGRA210_CLK_TIMER>; 313 clock-names = "timer"; 314 }; 315 316 tegra_car: clock@60006000 { 317 compatible = "nvidia,tegra210-car"; 318 reg = <0x0 0x60006000 0x0 0x1000>; 319 #clock-cells = <1>; 320 #reset-cells = <1>; 321 }; 322 323 flow-controller@60007000 { 324 compatible = "nvidia,tegra210-flowctrl"; 325 reg = <0x0 0x60007000 0x0 0x1000>; 326 }; 327 328 gpio: gpio@6000d000 { 329 compatible = "nvidia,tegra210-gpio", "nvidia,tegra124-gpio", "nvidia,tegra30-gpio"; 330 reg = <0x0 0x6000d000 0x0 0x1000>; 331 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 332 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 333 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 334 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 335 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 336 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 337 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 338 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 339 #gpio-cells = <2>; 340 gpio-controller; 341 #interrupt-cells = <2>; 342 interrupt-controller; 343 }; 344 345 apbdma: dma@60020000 { 346 compatible = "nvidia,tegra210-apbdma", "nvidia,tegra148-apbdma"; 347 reg = <0x0 0x60020000 0x0 0x1400>; 348 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 349 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 350 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 351 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 352 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 353 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 354 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 355 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 356 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 357 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 358 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 359 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 360 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 361 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 362 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 363 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 364 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 365 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 366 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 367 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 368 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 369 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 370 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 371 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 372 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 373 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 374 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 375 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 376 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 377 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 378 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 379 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 380 clocks = <&tegra_car TEGRA210_CLK_APBDMA>; 381 clock-names = "dma"; 382 resets = <&tegra_car 34>; 383 reset-names = "dma"; 384 #dma-cells = <1>; 385 }; 386 387 apbmisc@70000800 { 388 compatible = "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc"; 389 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */ 390 <0x0 0x7000e864 0x0 0x04>; /* Strapping options */ 391 }; 392 393 pinmux: pinmux@700008d4 { 394 compatible = "nvidia,tegra210-pinmux"; 395 reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */ 396 <0x0 0x70003000 0x0 0x294>; /* Mux registers */ 397 }; 398 399 /* 400 * There are two serial driver i.e. 8250 based simple serial 401 * driver and APB DMA based serial driver for higher baudrate 402 * and performance. To enable the 8250 based driver, the compatible 403 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable 404 * the APB DMA based serial driver, the compatible is 405 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". 406 */ 407 uarta: serial@70006000 { 408 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 409 reg = <0x0 0x70006000 0x0 0x40>; 410 reg-shift = <2>; 411 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 412 clocks = <&tegra_car TEGRA210_CLK_UARTA>; 413 clock-names = "serial"; 414 resets = <&tegra_car 6>; 415 reset-names = "serial"; 416 dmas = <&apbdma 8>, <&apbdma 8>; 417 dma-names = "rx", "tx"; 418 status = "disabled"; 419 }; 420 421 uartb: serial@70006040 { 422 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 423 reg = <0x0 0x70006040 0x0 0x40>; 424 reg-shift = <2>; 425 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 426 clocks = <&tegra_car TEGRA210_CLK_UARTB>; 427 clock-names = "serial"; 428 resets = <&tegra_car 7>; 429 reset-names = "serial"; 430 dmas = <&apbdma 9>, <&apbdma 9>; 431 dma-names = "rx", "tx"; 432 status = "disabled"; 433 }; 434 435 uartc: serial@70006200 { 436 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 437 reg = <0x0 0x70006200 0x0 0x40>; 438 reg-shift = <2>; 439 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 440 clocks = <&tegra_car TEGRA210_CLK_UARTC>; 441 clock-names = "serial"; 442 resets = <&tegra_car 55>; 443 reset-names = "serial"; 444 dmas = <&apbdma 10>, <&apbdma 10>; 445 dma-names = "rx", "tx"; 446 status = "disabled"; 447 }; 448 449 uartd: serial@70006300 { 450 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 451 reg = <0x0 0x70006300 0x0 0x40>; 452 reg-shift = <2>; 453 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 454 clocks = <&tegra_car TEGRA210_CLK_UARTD>; 455 clock-names = "serial"; 456 resets = <&tegra_car 65>; 457 reset-names = "serial"; 458 dmas = <&apbdma 19>, <&apbdma 19>; 459 dma-names = "rx", "tx"; 460 status = "disabled"; 461 }; 462 463 pwm: pwm@7000a000 { 464 compatible = "nvidia,tegra210-pwm", "nvidia,tegra20-pwm"; 465 reg = <0x0 0x7000a000 0x0 0x100>; 466 #pwm-cells = <2>; 467 clocks = <&tegra_car TEGRA210_CLK_PWM>; 468 clock-names = "pwm"; 469 resets = <&tegra_car 17>; 470 reset-names = "pwm"; 471 status = "disabled"; 472 }; 473 474 i2c@7000c000 { 475 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 476 reg = <0x0 0x7000c000 0x0 0x100>; 477 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 478 #address-cells = <1>; 479 #size-cells = <0>; 480 clocks = <&tegra_car TEGRA210_CLK_I2C1>; 481 clock-names = "div-clk"; 482 resets = <&tegra_car 12>; 483 reset-names = "i2c"; 484 dmas = <&apbdma 21>, <&apbdma 21>; 485 dma-names = "rx", "tx"; 486 status = "disabled"; 487 }; 488 489 i2c@7000c400 { 490 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 491 reg = <0x0 0x7000c400 0x0 0x100>; 492 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 493 #address-cells = <1>; 494 #size-cells = <0>; 495 clocks = <&tegra_car TEGRA210_CLK_I2C2>; 496 clock-names = "div-clk"; 497 resets = <&tegra_car 54>; 498 reset-names = "i2c"; 499 dmas = <&apbdma 22>, <&apbdma 22>; 500 dma-names = "rx", "tx"; 501 status = "disabled"; 502 }; 503 504 i2c@7000c500 { 505 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 506 reg = <0x0 0x7000c500 0x0 0x100>; 507 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 508 #address-cells = <1>; 509 #size-cells = <0>; 510 clocks = <&tegra_car TEGRA210_CLK_I2C3>; 511 clock-names = "div-clk"; 512 resets = <&tegra_car 67>; 513 reset-names = "i2c"; 514 dmas = <&apbdma 23>, <&apbdma 23>; 515 dma-names = "rx", "tx"; 516 status = "disabled"; 517 }; 518 519 i2c@7000c700 { 520 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 521 reg = <0x0 0x7000c700 0x0 0x100>; 522 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 523 #address-cells = <1>; 524 #size-cells = <0>; 525 clocks = <&tegra_car TEGRA210_CLK_I2C4>; 526 clock-names = "div-clk"; 527 resets = <&tegra_car 103>; 528 reset-names = "i2c"; 529 dmas = <&apbdma 26>, <&apbdma 26>; 530 dma-names = "rx", "tx"; 531 pinctrl-0 = <&state_dpaux1_i2c>; 532 pinctrl-1 = <&state_dpaux1_off>; 533 pinctrl-names = "default", "idle"; 534 status = "disabled"; 535 }; 536 537 i2c@7000d000 { 538 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 539 reg = <0x0 0x7000d000 0x0 0x100>; 540 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 541 #address-cells = <1>; 542 #size-cells = <0>; 543 clocks = <&tegra_car TEGRA210_CLK_I2C5>; 544 clock-names = "div-clk"; 545 resets = <&tegra_car 47>; 546 reset-names = "i2c"; 547 dmas = <&apbdma 24>, <&apbdma 24>; 548 dma-names = "rx", "tx"; 549 status = "disabled"; 550 }; 551 552 i2c@7000d100 { 553 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 554 reg = <0x0 0x7000d100 0x0 0x100>; 555 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 556 #address-cells = <1>; 557 #size-cells = <0>; 558 clocks = <&tegra_car TEGRA210_CLK_I2C6>; 559 clock-names = "div-clk"; 560 resets = <&tegra_car 166>; 561 reset-names = "i2c"; 562 dmas = <&apbdma 30>, <&apbdma 30>; 563 dma-names = "rx", "tx"; 564 pinctrl-0 = <&state_dpaux_i2c>; 565 pinctrl-1 = <&state_dpaux_off>; 566 pinctrl-names = "default", "idle"; 567 status = "disabled"; 568 }; 569 570 spi@7000d400 { 571 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 572 reg = <0x0 0x7000d400 0x0 0x200>; 573 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 574 #address-cells = <1>; 575 #size-cells = <0>; 576 clocks = <&tegra_car TEGRA210_CLK_SBC1>; 577 clock-names = "spi"; 578 resets = <&tegra_car 41>; 579 reset-names = "spi"; 580 dmas = <&apbdma 15>, <&apbdma 15>; 581 dma-names = "rx", "tx"; 582 status = "disabled"; 583 }; 584 585 spi@7000d600 { 586 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 587 reg = <0x0 0x7000d600 0x0 0x200>; 588 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 589 #address-cells = <1>; 590 #size-cells = <0>; 591 clocks = <&tegra_car TEGRA210_CLK_SBC2>; 592 clock-names = "spi"; 593 resets = <&tegra_car 44>; 594 reset-names = "spi"; 595 dmas = <&apbdma 16>, <&apbdma 16>; 596 dma-names = "rx", "tx"; 597 status = "disabled"; 598 }; 599 600 spi@7000d800 { 601 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 602 reg = <0x0 0x7000d800 0x0 0x200>; 603 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 604 #address-cells = <1>; 605 #size-cells = <0>; 606 clocks = <&tegra_car TEGRA210_CLK_SBC3>; 607 clock-names = "spi"; 608 resets = <&tegra_car 46>; 609 reset-names = "spi"; 610 dmas = <&apbdma 17>, <&apbdma 17>; 611 dma-names = "rx", "tx"; 612 status = "disabled"; 613 }; 614 615 spi@7000da00 { 616 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 617 reg = <0x0 0x7000da00 0x0 0x200>; 618 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 619 #address-cells = <1>; 620 #size-cells = <0>; 621 clocks = <&tegra_car TEGRA210_CLK_SBC4>; 622 clock-names = "spi"; 623 resets = <&tegra_car 68>; 624 reset-names = "spi"; 625 dmas = <&apbdma 18>, <&apbdma 18>; 626 dma-names = "rx", "tx"; 627 status = "disabled"; 628 }; 629 630 rtc@7000e000 { 631 compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc"; 632 reg = <0x0 0x7000e000 0x0 0x100>; 633 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 634 clocks = <&tegra_car TEGRA210_CLK_RTC>; 635 clock-names = "rtc"; 636 }; 637 638 pmc: pmc@7000e400 { 639 compatible = "nvidia,tegra210-pmc"; 640 reg = <0x0 0x7000e400 0x0 0x400>; 641 clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; 642 clock-names = "pclk", "clk32k_in"; 643 644 powergates { 645 pd_audio: aud { 646 clocks = <&tegra_car TEGRA210_CLK_APE>, 647 <&tegra_car TEGRA210_CLK_APB2APE>; 648 resets = <&tegra_car 198>; 649 #power-domain-cells = <0>; 650 }; 651 652 pd_xusbss: xusba { 653 clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>; 654 clock-names = "xusb-ss"; 655 resets = <&tegra_car TEGRA210_CLK_XUSB_SS>; 656 reset-names = "xusb-ss"; 657 #power-domain-cells = <0>; 658 }; 659 660 pd_xusbdev: xusbb { 661 clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>; 662 clock-names = "xusb-dev"; 663 resets = <&tegra_car 95>; 664 reset-names = "xusb-dev"; 665 #power-domain-cells = <0>; 666 }; 667 668 pd_xusbhost: xusbc { 669 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>; 670 clock-names = "xusb-host"; 671 resets = <&tegra_car TEGRA210_CLK_XUSB_HOST>; 672 reset-names = "xusb-host"; 673 #power-domain-cells = <0>; 674 }; 675 }; 676 }; 677 678 fuse@7000f800 { 679 compatible = "nvidia,tegra210-efuse"; 680 reg = <0x0 0x7000f800 0x0 0x400>; 681 clocks = <&tegra_car TEGRA210_CLK_FUSE>; 682 clock-names = "fuse"; 683 resets = <&tegra_car 39>; 684 reset-names = "fuse"; 685 }; 686 687 mc: memory-controller@70019000 { 688 compatible = "nvidia,tegra210-mc"; 689 reg = <0x0 0x70019000 0x0 0x1000>; 690 clocks = <&tegra_car TEGRA210_CLK_MC>; 691 clock-names = "mc"; 692 693 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 694 695 #iommu-cells = <1>; 696 }; 697 698 hda@70030000 { 699 compatible = "nvidia,tegra210-hda", "nvidia,tegra30-hda"; 700 reg = <0x0 0x70030000 0x0 0x10000>; 701 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 702 clocks = <&tegra_car TEGRA210_CLK_HDA>, 703 <&tegra_car TEGRA210_CLK_HDA2HDMI>, 704 <&tegra_car TEGRA210_CLK_HDA2CODEC_2X>; 705 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 706 resets = <&tegra_car 125>, /* hda */ 707 <&tegra_car 128>, /* hda2hdmi */ 708 <&tegra_car 111>; /* hda2codec_2x */ 709 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 710 status = "disabled"; 711 }; 712 713 usb@70090000 { 714 compatible = "nvidia,tegra210-xusb"; 715 reg = <0x0 0x70090000 0x0 0x8000>, 716 <0x0 0x70098000 0x0 0x1000>, 717 <0x0 0x70099000 0x0 0x1000>; 718 reg-names = "hcd", "fpci", "ipfs"; 719 720 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 721 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 722 723 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>, 724 <&tegra_car TEGRA210_CLK_XUSB_HOST_SRC>, 725 <&tegra_car TEGRA210_CLK_XUSB_FALCON_SRC>, 726 <&tegra_car TEGRA210_CLK_XUSB_SS>, 727 <&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>, 728 <&tegra_car TEGRA210_CLK_XUSB_SS_SRC>, 729 <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>, 730 <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>, 731 <&tegra_car TEGRA210_CLK_PLL_U_480M>, 732 <&tegra_car TEGRA210_CLK_CLK_M>, 733 <&tegra_car TEGRA210_CLK_PLL_E>; 734 clock-names = "xusb_host", "xusb_host_src", 735 "xusb_falcon_src", "xusb_ss", 736 "xusb_ss_div2", "xusb_ss_src", 737 "xusb_hs_src", "xusb_fs_src", 738 "pll_u_480m", "clk_m", "pll_e"; 739 resets = <&tegra_car 89>, <&tegra_car 156>, 740 <&tegra_car 143>; 741 reset-names = "xusb_host", "xusb_ss", "xusb_src"; 742 743 nvidia,xusb-padctl = <&padctl>; 744 745 status = "disabled"; 746 }; 747 748 padctl: padctl@7009f000 { 749 compatible = "nvidia,tegra210-xusb-padctl"; 750 reg = <0x0 0x7009f000 0x0 0x1000>; 751 resets = <&tegra_car 142>; 752 reset-names = "padctl"; 753 754 status = "disabled"; 755 756 pads { 757 usb2 { 758 clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>; 759 clock-names = "trk"; 760 status = "disabled"; 761 762 lanes { 763 usb2-0 { 764 status = "disabled"; 765 #phy-cells = <0>; 766 }; 767 768 usb2-1 { 769 status = "disabled"; 770 #phy-cells = <0>; 771 }; 772 773 usb2-2 { 774 status = "disabled"; 775 #phy-cells = <0>; 776 }; 777 778 usb2-3 { 779 status = "disabled"; 780 #phy-cells = <0>; 781 }; 782 }; 783 }; 784 785 hsic { 786 clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>; 787 clock-names = "trk"; 788 status = "disabled"; 789 790 lanes { 791 hsic-0 { 792 status = "disabled"; 793 #phy-cells = <0>; 794 }; 795 796 hsic-1 { 797 status = "disabled"; 798 #phy-cells = <0>; 799 }; 800 }; 801 }; 802 803 pcie { 804 clocks = <&tegra_car TEGRA210_CLK_PLL_E>; 805 clock-names = "pll"; 806 resets = <&tegra_car 205>; 807 reset-names = "phy"; 808 status = "disabled"; 809 810 lanes { 811 pcie-0 { 812 status = "disabled"; 813 #phy-cells = <0>; 814 }; 815 816 pcie-1 { 817 status = "disabled"; 818 #phy-cells = <0>; 819 }; 820 821 pcie-2 { 822 status = "disabled"; 823 #phy-cells = <0>; 824 }; 825 826 pcie-3 { 827 status = "disabled"; 828 #phy-cells = <0>; 829 }; 830 831 pcie-4 { 832 status = "disabled"; 833 #phy-cells = <0>; 834 }; 835 836 pcie-5 { 837 status = "disabled"; 838 #phy-cells = <0>; 839 }; 840 841 pcie-6 { 842 status = "disabled"; 843 #phy-cells = <0>; 844 }; 845 }; 846 }; 847 848 sata { 849 clocks = <&tegra_car TEGRA210_CLK_PLL_E>; 850 clock-names = "pll"; 851 resets = <&tegra_car 204>; 852 reset-names = "phy"; 853 status = "disabled"; 854 855 lanes { 856 sata-0 { 857 status = "disabled"; 858 #phy-cells = <0>; 859 }; 860 }; 861 }; 862 }; 863 864 ports { 865 usb2-0 { 866 status = "disabled"; 867 }; 868 869 usb2-1 { 870 status = "disabled"; 871 }; 872 873 usb2-2 { 874 status = "disabled"; 875 }; 876 877 usb2-3 { 878 status = "disabled"; 879 }; 880 881 hsic-0 { 882 status = "disabled"; 883 }; 884 885 usb3-0 { 886 status = "disabled"; 887 }; 888 889 usb3-1 { 890 status = "disabled"; 891 }; 892 893 usb3-2 { 894 status = "disabled"; 895 }; 896 897 usb3-3 { 898 status = "disabled"; 899 }; 900 }; 901 }; 902 903 sdhci@700b0000 { 904 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; 905 reg = <0x0 0x700b0000 0x0 0x200>; 906 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 907 clocks = <&tegra_car TEGRA210_CLK_SDMMC1>; 908 clock-names = "sdhci"; 909 resets = <&tegra_car 14>; 910 reset-names = "sdhci"; 911 status = "disabled"; 912 }; 913 914 sdhci@700b0200 { 915 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; 916 reg = <0x0 0x700b0200 0x0 0x200>; 917 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 918 clocks = <&tegra_car TEGRA210_CLK_SDMMC2>; 919 clock-names = "sdhci"; 920 resets = <&tegra_car 9>; 921 reset-names = "sdhci"; 922 status = "disabled"; 923 }; 924 925 sdhci@700b0400 { 926 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; 927 reg = <0x0 0x700b0400 0x0 0x200>; 928 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 929 clocks = <&tegra_car TEGRA210_CLK_SDMMC3>; 930 clock-names = "sdhci"; 931 resets = <&tegra_car 69>; 932 reset-names = "sdhci"; 933 status = "disabled"; 934 }; 935 936 sdhci@700b0600 { 937 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; 938 reg = <0x0 0x700b0600 0x0 0x200>; 939 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 940 clocks = <&tegra_car TEGRA210_CLK_SDMMC4>; 941 clock-names = "sdhci"; 942 resets = <&tegra_car 15>; 943 reset-names = "sdhci"; 944 status = "disabled"; 945 }; 946 947 mipi: mipi@700e3000 { 948 compatible = "nvidia,tegra210-mipi"; 949 reg = <0x0 0x700e3000 0x0 0x100>; 950 clocks = <&tegra_car TEGRA210_CLK_MIPI_CAL>; 951 clock-names = "mipi-cal"; 952 #nvidia,mipi-calibrate-cells = <1>; 953 }; 954 955 aconnect@702c0000 { 956 compatible = "nvidia,tegra210-aconnect"; 957 clocks = <&tegra_car TEGRA210_CLK_APE>, 958 <&tegra_car TEGRA210_CLK_APB2APE>; 959 clock-names = "ape", "apb2ape"; 960 power-domains = <&pd_audio>; 961 #address-cells = <1>; 962 #size-cells = <1>; 963 ranges = <0x702c0000 0x0 0x702c0000 0x00040000>; 964 status = "disabled"; 965 }; 966 967 spi@70410000 { 968 compatible = "nvidia,tegra210-qspi"; 969 reg = <0x0 0x70410000 0x0 0x1000>; 970 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 971 #address-cells = <1>; 972 #size-cells = <0>; 973 clocks = <&tegra_car TEGRA210_CLK_QSPI>; 974 clock-names = "qspi"; 975 resets = <&tegra_car 211>; 976 reset-names = "qspi"; 977 dmas = <&apbdma 5>, <&apbdma 5>; 978 dma-names = "rx", "tx"; 979 status = "disabled"; 980 }; 981 982 usb@7d000000 { 983 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 984 reg = <0x0 0x7d000000 0x0 0x4000>; 985 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 986 phy_type = "utmi"; 987 clocks = <&tegra_car TEGRA210_CLK_USBD>; 988 clock-names = "usb"; 989 resets = <&tegra_car 22>; 990 reset-names = "usb"; 991 nvidia,phy = <&phy1>; 992 status = "disabled"; 993 }; 994 995 phy1: usb-phy@7d000000 { 996 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; 997 reg = <0x0 0x7d000000 0x0 0x4000>, 998 <0x0 0x7d000000 0x0 0x4000>; 999 phy_type = "utmi"; 1000 clocks = <&tegra_car TEGRA210_CLK_USBD>, 1001 <&tegra_car TEGRA210_CLK_PLL_U>, 1002 <&tegra_car TEGRA210_CLK_USBD>; 1003 clock-names = "reg", "pll_u", "utmi-pads"; 1004 resets = <&tegra_car 22>, <&tegra_car 22>; 1005 reset-names = "usb", "utmi-pads"; 1006 nvidia,hssync-start-delay = <0>; 1007 nvidia,idle-wait-delay = <17>; 1008 nvidia,elastic-limit = <16>; 1009 nvidia,term-range-adj = <6>; 1010 nvidia,xcvr-setup = <9>; 1011 nvidia,xcvr-lsfslew = <0>; 1012 nvidia,xcvr-lsrslew = <3>; 1013 nvidia,hssquelch-level = <2>; 1014 nvidia,hsdiscon-level = <5>; 1015 nvidia,xcvr-hsslew = <12>; 1016 nvidia,has-utmi-pad-registers; 1017 status = "disabled"; 1018 }; 1019 1020 usb@7d004000 { 1021 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 1022 reg = <0x0 0x7d004000 0x0 0x4000>; 1023 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1024 phy_type = "utmi"; 1025 clocks = <&tegra_car TEGRA210_CLK_USB2>; 1026 clock-names = "usb"; 1027 resets = <&tegra_car 58>; 1028 reset-names = "usb"; 1029 nvidia,phy = <&phy2>; 1030 status = "disabled"; 1031 }; 1032 1033 phy2: usb-phy@7d004000 { 1034 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; 1035 reg = <0x0 0x7d004000 0x0 0x4000>, 1036 <0x0 0x7d000000 0x0 0x4000>; 1037 phy_type = "utmi"; 1038 clocks = <&tegra_car TEGRA210_CLK_USB2>, 1039 <&tegra_car TEGRA210_CLK_PLL_U>, 1040 <&tegra_car TEGRA210_CLK_USBD>; 1041 clock-names = "reg", "pll_u", "utmi-pads"; 1042 resets = <&tegra_car 58>, <&tegra_car 22>; 1043 reset-names = "usb", "utmi-pads"; 1044 nvidia,hssync-start-delay = <0>; 1045 nvidia,idle-wait-delay = <17>; 1046 nvidia,elastic-limit = <16>; 1047 nvidia,term-range-adj = <6>; 1048 nvidia,xcvr-setup = <9>; 1049 nvidia,xcvr-lsfslew = <0>; 1050 nvidia,xcvr-lsrslew = <3>; 1051 nvidia,hssquelch-level = <2>; 1052 nvidia,hsdiscon-level = <5>; 1053 nvidia,xcvr-hsslew = <12>; 1054 status = "disabled"; 1055 }; 1056 1057 cpus { 1058 #address-cells = <1>; 1059 #size-cells = <0>; 1060 1061 cpu@0 { 1062 device_type = "cpu"; 1063 compatible = "arm,cortex-a57"; 1064 reg = <0>; 1065 }; 1066 1067 cpu@1 { 1068 device_type = "cpu"; 1069 compatible = "arm,cortex-a57"; 1070 reg = <1>; 1071 }; 1072 1073 cpu@2 { 1074 device_type = "cpu"; 1075 compatible = "arm,cortex-a57"; 1076 reg = <2>; 1077 }; 1078 1079 cpu@3 { 1080 device_type = "cpu"; 1081 compatible = "arm,cortex-a57"; 1082 reg = <3>; 1083 }; 1084 }; 1085 1086 timer { 1087 compatible = "arm,armv8-timer"; 1088 interrupts = <GIC_PPI 13 1089 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1090 <GIC_PPI 14 1091 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1092 <GIC_PPI 11 1093 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1094 <GIC_PPI 10 1095 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1096 interrupt-parent = <&gic>; 1097 }; 1098 1099 soctherm: thermal-sensor@700e2000 { 1100 compatible = "nvidia,tegra210-soctherm"; 1101 reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */ 1102 0x0 0x60006000 0x0 0x400>; /* CAR reg_base */ 1103 reg-names = "soctherm-reg", "car-reg"; 1104 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 1105 clocks = <&tegra_car TEGRA210_CLK_TSENSOR>, 1106 <&tegra_car TEGRA210_CLK_SOC_THERM>; 1107 clock-names = "tsensor", "soctherm"; 1108 resets = <&tegra_car 78>; 1109 reset-names = "soctherm"; 1110 #thermal-sensor-cells = <1>; 1111 1112 throttle-cfgs { 1113 throttle_heavy: heavy { 1114 nvidia,priority = <100>; 1115 nvidia,cpu-throt-percent = <85>; 1116 1117 #cooling-cells = <2>; 1118 }; 1119 }; 1120 }; 1121 1122 thermal-zones { 1123 cpu { 1124 polling-delay-passive = <1000>; 1125 polling-delay = <0>; 1126 1127 thermal-sensors = 1128 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; 1129 1130 trips { 1131 cpu-shutdown-trip { 1132 temperature = <102500>; 1133 hysteresis = <0>; 1134 type = "critical"; 1135 }; 1136 1137 cpu_throttle_trip: throttle-trip { 1138 temperature = <98500>; 1139 hysteresis = <1000>; 1140 type = "hot"; 1141 }; 1142 }; 1143 1144 cooling-maps { 1145 map0 { 1146 trip = <&cpu_throttle_trip>; 1147 cooling-device = <&throttle_heavy 1 1>; 1148 }; 1149 }; 1150 }; 1151 mem { 1152 polling-delay-passive = <0>; 1153 polling-delay = <0>; 1154 1155 thermal-sensors = 1156 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>; 1157 1158 trips { 1159 mem-shutdown-trip { 1160 temperature = <103000>; 1161 hysteresis = <0>; 1162 type = "critical"; 1163 }; 1164 }; 1165 1166 cooling-maps { 1167 /* 1168 * There are currently no cooling maps, 1169 * because there are no cooling devices. 1170 */ 1171 }; 1172 }; 1173 gpu { 1174 polling-delay-passive = <1000>; 1175 polling-delay = <0>; 1176 1177 thermal-sensors = 1178 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>; 1179 1180 trips { 1181 gpu-shutdown-trip { 1182 temperature = <103000>; 1183 hysteresis = <0>; 1184 type = "critical"; 1185 }; 1186 1187 gpu_throttle_trip: throttle-trip { 1188 temperature = <100000>; 1189 hysteresis = <1000>; 1190 type = "hot"; 1191 }; 1192 }; 1193 1194 cooling-maps { 1195 map0 { 1196 trip = <&gpu_throttle_trip>; 1197 cooling-device = <&throttle_heavy 1 1>; 1198 }; 1199 }; 1200 }; 1201 pllx { 1202 polling-delay-passive = <0>; 1203 polling-delay = <0>; 1204 1205 thermal-sensors = 1206 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>; 1207 1208 trips { 1209 pllx-shutdown-trip { 1210 temperature = <103000>; 1211 hysteresis = <0>; 1212 type = "critical"; 1213 }; 1214 }; 1215 1216 cooling-maps { 1217 /* 1218 * There are currently no cooling maps, 1219 * because there are no cooling devices. 1220 */ 1221 }; 1222 }; 1223 }; 1224}; 1225