1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra210-car.h> 3#include <dt-bindings/gpio/tegra-gpio.h> 4#include <dt-bindings/memory/tegra210-mc.h> 5#include <dt-bindings/pinctrl/pinctrl-tegra.h> 6#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 7#include <dt-bindings/reset/tegra210-car.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/thermal/tegra124-soctherm.h> 10#include <dt-bindings/soc/tegra-pmc.h> 11 12/ { 13 compatible = "nvidia,tegra210"; 14 interrupt-parent = <&lic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 pcie@1003000 { 19 compatible = "nvidia,tegra210-pcie"; 20 device_type = "pci"; 21 reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */ 22 <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */ 23 <0x0 0x02000000 0x0 0x10000000>; /* configuration space */ 24 reg-names = "pads", "afi", "cs"; 25 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 26 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 27 interrupt-names = "intr", "msi"; 28 29 #interrupt-cells = <1>; 30 interrupt-map-mask = <0 0 0 0>; 31 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 32 33 bus-range = <0x00 0xff>; 34 #address-cells = <3>; 35 #size-cells = <2>; 36 37 ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */ 38 <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */ 39 <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */ 40 <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */ 41 <0x42000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ 42 43 clocks = <&tegra_car TEGRA210_CLK_PCIE>, 44 <&tegra_car TEGRA210_CLK_AFI>, 45 <&tegra_car TEGRA210_CLK_PLL_E>, 46 <&tegra_car TEGRA210_CLK_CML0>; 47 clock-names = "pex", "afi", "pll_e", "cml"; 48 resets = <&tegra_car 70>, 49 <&tegra_car 72>, 50 <&tegra_car 74>; 51 reset-names = "pex", "afi", "pcie_x"; 52 53 pinctrl-names = "default", "idle"; 54 pinctrl-0 = <&pex_dpd_disable>; 55 pinctrl-1 = <&pex_dpd_enable>; 56 57 status = "disabled"; 58 59 pci@1,0 { 60 device_type = "pci"; 61 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>; 62 reg = <0x000800 0 0 0 0>; 63 bus-range = <0x00 0xff>; 64 status = "disabled"; 65 66 #address-cells = <3>; 67 #size-cells = <2>; 68 ranges; 69 70 nvidia,num-lanes = <4>; 71 }; 72 73 pci@2,0 { 74 device_type = "pci"; 75 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>; 76 reg = <0x001000 0 0 0 0>; 77 bus-range = <0x00 0xff>; 78 status = "disabled"; 79 80 #address-cells = <3>; 81 #size-cells = <2>; 82 ranges; 83 84 nvidia,num-lanes = <1>; 85 }; 86 }; 87 88 host1x@50000000 { 89 compatible = "nvidia,tegra210-host1x"; 90 reg = <0x0 0x50000000 0x0 0x00034000>; 91 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 92 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ 93 interrupt-names = "syncpt", "host1x"; 94 clocks = <&tegra_car TEGRA210_CLK_HOST1X>; 95 clock-names = "host1x"; 96 resets = <&tegra_car 28>; 97 reset-names = "host1x"; 98 99 #address-cells = <2>; 100 #size-cells = <2>; 101 102 ranges = <0x0 0x54000000 0x0 0x54000000 0x0 0x01000000>; 103 104 iommus = <&mc TEGRA_SWGROUP_HC>; 105 106 dpaux1: dpaux@54040000 { 107 compatible = "nvidia,tegra210-dpaux"; 108 reg = <0x0 0x54040000 0x0 0x00040000>; 109 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 110 clocks = <&tegra_car TEGRA210_CLK_DPAUX1>, 111 <&tegra_car TEGRA210_CLK_PLL_DP>; 112 clock-names = "dpaux", "parent"; 113 resets = <&tegra_car 207>; 114 reset-names = "dpaux"; 115 power-domains = <&pd_sor>; 116 status = "disabled"; 117 118 state_dpaux1_aux: pinmux-aux { 119 groups = "dpaux-io"; 120 function = "aux"; 121 }; 122 123 state_dpaux1_i2c: pinmux-i2c { 124 groups = "dpaux-io"; 125 function = "i2c"; 126 }; 127 128 state_dpaux1_off: pinmux-off { 129 groups = "dpaux-io"; 130 function = "off"; 131 }; 132 133 i2c-bus { 134 #address-cells = <1>; 135 #size-cells = <0>; 136 }; 137 }; 138 139 vi@54080000 { 140 compatible = "nvidia,tegra210-vi"; 141 reg = <0x0 0x54080000 0x0 0x700>; 142 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 143 status = "disabled"; 144 assigned-clocks = <&tegra_car TEGRA210_CLK_VI>; 145 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 146 147 clocks = <&tegra_car TEGRA210_CLK_VI>; 148 power-domains = <&pd_venc>; 149 150 #address-cells = <1>; 151 #size-cells = <1>; 152 153 ranges = <0x0 0x0 0x54080000 0x2000>; 154 155 csi@838 { 156 compatible = "nvidia,tegra210-csi"; 157 reg = <0x838 0x1300>; 158 status = "disabled"; 159 assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>, 160 <&tegra_car TEGRA210_CLK_CILCD>, 161 <&tegra_car TEGRA210_CLK_CILE>, 162 <&tegra_car TEGRA210_CLK_CSI_TPG>; 163 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>, 164 <&tegra_car TEGRA210_CLK_PLL_P>, 165 <&tegra_car TEGRA210_CLK_PLL_P>; 166 assigned-clock-rates = <102000000>, 167 <102000000>, 168 <102000000>, 169 <972000000>; 170 171 clocks = <&tegra_car TEGRA210_CLK_CSI>, 172 <&tegra_car TEGRA210_CLK_CILAB>, 173 <&tegra_car TEGRA210_CLK_CILCD>, 174 <&tegra_car TEGRA210_CLK_CILE>, 175 <&tegra_car TEGRA210_CLK_CSI_TPG>; 176 clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg"; 177 power-domains = <&pd_sor>; 178 }; 179 }; 180 181 tsec@54100000 { 182 compatible = "nvidia,tegra210-tsec"; 183 reg = <0x0 0x54100000 0x0 0x00040000>; 184 }; 185 186 dc@54200000 { 187 compatible = "nvidia,tegra210-dc"; 188 reg = <0x0 0x54200000 0x0 0x00040000>; 189 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 190 clocks = <&tegra_car TEGRA210_CLK_DISP1>; 191 clock-names = "dc"; 192 resets = <&tegra_car 27>; 193 reset-names = "dc"; 194 195 iommus = <&mc TEGRA_SWGROUP_DC>; 196 197 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 198 nvidia,head = <0>; 199 }; 200 201 dc@54240000 { 202 compatible = "nvidia,tegra210-dc"; 203 reg = <0x0 0x54240000 0x0 0x00040000>; 204 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 205 clocks = <&tegra_car TEGRA210_CLK_DISP2>; 206 clock-names = "dc"; 207 resets = <&tegra_car 26>; 208 reset-names = "dc"; 209 210 iommus = <&mc TEGRA_SWGROUP_DCB>; 211 212 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 213 nvidia,head = <1>; 214 }; 215 216 dsia: dsi@54300000 { 217 compatible = "nvidia,tegra210-dsi"; 218 reg = <0x0 0x54300000 0x0 0x00040000>; 219 clocks = <&tegra_car TEGRA210_CLK_DSIA>, 220 <&tegra_car TEGRA210_CLK_DSIALP>, 221 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; 222 clock-names = "dsi", "lp", "parent"; 223 resets = <&tegra_car 48>; 224 reset-names = "dsi"; 225 power-domains = <&pd_sor>; 226 nvidia,mipi-calibrate = <&mipi 0x0c0>; /* DSIA & DSIB pads */ 227 228 status = "disabled"; 229 230 #address-cells = <1>; 231 #size-cells = <0>; 232 }; 233 234 vic@54340000 { 235 compatible = "nvidia,tegra210-vic"; 236 reg = <0x0 0x54340000 0x0 0x00040000>; 237 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 238 clocks = <&tegra_car TEGRA210_CLK_VIC03>; 239 clock-names = "vic"; 240 resets = <&tegra_car 178>; 241 reset-names = "vic"; 242 243 iommus = <&mc TEGRA_SWGROUP_VIC>; 244 power-domains = <&pd_vic>; 245 }; 246 247 nvjpg@54380000 { 248 compatible = "nvidia,tegra210-nvjpg"; 249 reg = <0x0 0x54380000 0x0 0x00040000>; 250 status = "disabled"; 251 }; 252 253 dsib: dsi@54400000 { 254 compatible = "nvidia,tegra210-dsi"; 255 reg = <0x0 0x54400000 0x0 0x00040000>; 256 clocks = <&tegra_car TEGRA210_CLK_DSIB>, 257 <&tegra_car TEGRA210_CLK_DSIBLP>, 258 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; 259 clock-names = "dsi", "lp", "parent"; 260 resets = <&tegra_car 82>; 261 reset-names = "dsi"; 262 power-domains = <&pd_sor>; 263 nvidia,mipi-calibrate = <&mipi 0x300>; /* DSIC & DSID pads */ 264 265 status = "disabled"; 266 267 #address-cells = <1>; 268 #size-cells = <0>; 269 }; 270 271 nvdec@54480000 { 272 compatible = "nvidia,tegra210-nvdec"; 273 reg = <0x0 0x54480000 0x0 0x00040000>; 274 status = "disabled"; 275 }; 276 277 nvenc@544c0000 { 278 compatible = "nvidia,tegra210-nvenc"; 279 reg = <0x0 0x544c0000 0x0 0x00040000>; 280 status = "disabled"; 281 }; 282 283 tsec@54500000 { 284 compatible = "nvidia,tegra210-tsec"; 285 reg = <0x0 0x54500000 0x0 0x00040000>; 286 status = "disabled"; 287 }; 288 289 sor0: sor@54540000 { 290 compatible = "nvidia,tegra210-sor"; 291 reg = <0x0 0x54540000 0x0 0x00040000>; 292 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 293 clocks = <&tegra_car TEGRA210_CLK_SOR0>, 294 <&tegra_car TEGRA210_CLK_SOR0_OUT>, 295 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>, 296 <&tegra_car TEGRA210_CLK_PLL_DP>, 297 <&tegra_car TEGRA210_CLK_SOR_SAFE>; 298 clock-names = "sor", "out", "parent", "dp", "safe"; 299 resets = <&tegra_car 182>; 300 reset-names = "sor"; 301 pinctrl-0 = <&state_dpaux_aux>; 302 pinctrl-1 = <&state_dpaux_i2c>; 303 pinctrl-2 = <&state_dpaux_off>; 304 pinctrl-names = "aux", "i2c", "off"; 305 power-domains = <&pd_sor>; 306 status = "disabled"; 307 }; 308 309 sor1: sor@54580000 { 310 compatible = "nvidia,tegra210-sor1"; 311 reg = <0x0 0x54580000 0x0 0x00040000>; 312 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 313 clocks = <&tegra_car TEGRA210_CLK_SOR1>, 314 <&tegra_car TEGRA210_CLK_SOR1_OUT>, 315 <&tegra_car TEGRA210_CLK_PLL_D2_OUT0>, 316 <&tegra_car TEGRA210_CLK_PLL_DP>, 317 <&tegra_car TEGRA210_CLK_SOR_SAFE>; 318 clock-names = "sor", "out", "parent", "dp", "safe"; 319 resets = <&tegra_car 183>; 320 reset-names = "sor"; 321 pinctrl-0 = <&state_dpaux1_aux>; 322 pinctrl-1 = <&state_dpaux1_i2c>; 323 pinctrl-2 = <&state_dpaux1_off>; 324 pinctrl-names = "aux", "i2c", "off"; 325 power-domains = <&pd_sor>; 326 status = "disabled"; 327 }; 328 329 dpaux: dpaux@545c0000 { 330 compatible = "nvidia,tegra210-dpaux"; 331 reg = <0x0 0x545c0000 0x0 0x00040000>; 332 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 333 clocks = <&tegra_car TEGRA210_CLK_DPAUX>, 334 <&tegra_car TEGRA210_CLK_PLL_DP>; 335 clock-names = "dpaux", "parent"; 336 resets = <&tegra_car 181>; 337 reset-names = "dpaux"; 338 power-domains = <&pd_sor>; 339 status = "disabled"; 340 341 state_dpaux_aux: pinmux-aux { 342 groups = "dpaux-io"; 343 function = "aux"; 344 }; 345 346 state_dpaux_i2c: pinmux-i2c { 347 groups = "dpaux-io"; 348 function = "i2c"; 349 }; 350 351 state_dpaux_off: pinmux-off { 352 groups = "dpaux-io"; 353 function = "off"; 354 }; 355 356 i2c-bus { 357 #address-cells = <1>; 358 #size-cells = <0>; 359 }; 360 }; 361 362 isp@54600000 { 363 compatible = "nvidia,tegra210-isp"; 364 reg = <0x0 0x54600000 0x0 0x00040000>; 365 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 366 clocks = <&tegra_car TEGRA210_CLK_ISPA>; 367 resets = <&tegra_car 23>; 368 reset-names = "isp"; 369 status = "disabled"; 370 }; 371 372 isp@54680000 { 373 compatible = "nvidia,tegra210-isp"; 374 reg = <0x0 0x54680000 0x0 0x00040000>; 375 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 376 clocks = <&tegra_car TEGRA210_CLK_ISPB>; 377 resets = <&tegra_car 3>; 378 reset-names = "isp"; 379 status = "disabled"; 380 }; 381 382 i2c@546c0000 { 383 compatible = "nvidia,tegra210-i2c-vi"; 384 reg = <0x0 0x546c0000 0x0 0x00040000>; 385 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 386 clocks = <&tegra_car TEGRA210_CLK_VI_I2C>, 387 <&tegra_car TEGRA210_CLK_I2CSLOW>; 388 clock-names = "div-clk", "slow"; 389 resets = <&tegra_car 208>; 390 reset-names = "i2c"; 391 power-domains = <&pd_venc>; 392 status = "disabled"; 393 394 #address-cells = <1>; 395 #size-cells = <0>; 396 }; 397 }; 398 399 gic: interrupt-controller@50041000 { 400 compatible = "arm,gic-400"; 401 #interrupt-cells = <3>; 402 interrupt-controller; 403 reg = <0x0 0x50041000 0x0 0x1000>, 404 <0x0 0x50042000 0x0 0x2000>, 405 <0x0 0x50044000 0x0 0x2000>, 406 <0x0 0x50046000 0x0 0x2000>; 407 interrupts = <GIC_PPI 9 408 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 409 interrupt-parent = <&gic>; 410 }; 411 412 gpu@57000000 { 413 compatible = "nvidia,gm20b"; 414 reg = <0x0 0x57000000 0x0 0x01000000>, 415 <0x0 0x58000000 0x0 0x01000000>; 416 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 417 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 418 interrupt-names = "stall", "nonstall"; 419 clocks = <&tegra_car TEGRA210_CLK_GPU>, 420 <&tegra_car TEGRA210_CLK_PLL_P_OUT5>, 421 <&tegra_car TEGRA210_CLK_PLL_G_REF>; 422 clock-names = "gpu", "pwr", "ref"; 423 resets = <&tegra_car 184>; 424 reset-names = "gpu"; 425 426 iommus = <&mc TEGRA_SWGROUP_GPU>; 427 428 status = "disabled"; 429 }; 430 431 lic: interrupt-controller@60004000 { 432 compatible = "nvidia,tegra210-ictlr"; 433 reg = <0x0 0x60004000 0x0 0x40>, /* primary controller */ 434 <0x0 0x60004100 0x0 0x40>, /* secondary controller */ 435 <0x0 0x60004200 0x0 0x40>, /* tertiary controller */ 436 <0x0 0x60004300 0x0 0x40>, /* quaternary controller */ 437 <0x0 0x60004400 0x0 0x40>, /* quinary controller */ 438 <0x0 0x60004500 0x0 0x40>; /* senary controller */ 439 interrupt-controller; 440 #interrupt-cells = <3>; 441 interrupt-parent = <&gic>; 442 }; 443 444 timer@60005000 { 445 compatible = "nvidia,tegra210-timer"; 446 reg = <0x0 0x60005000 0x0 0x400>; 447 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 448 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 449 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 450 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 451 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 452 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 453 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 454 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 455 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 456 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 457 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 458 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 459 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, 460 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 461 clocks = <&tegra_car TEGRA210_CLK_TIMER>; 462 clock-names = "timer"; 463 }; 464 465 tegra_car: clock@60006000 { 466 compatible = "nvidia,tegra210-car"; 467 reg = <0x0 0x60006000 0x0 0x1000>; 468 #clock-cells = <1>; 469 #reset-cells = <1>; 470 }; 471 472 flow-controller@60007000 { 473 compatible = "nvidia,tegra210-flowctrl"; 474 reg = <0x0 0x60007000 0x0 0x1000>; 475 }; 476 477 gpio: gpio@6000d000 { 478 compatible = "nvidia,tegra210-gpio", "nvidia,tegra30-gpio"; 479 reg = <0x0 0x6000d000 0x0 0x1000>; 480 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 481 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 482 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 483 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 484 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 485 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 486 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 487 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 488 #gpio-cells = <2>; 489 gpio-controller; 490 #interrupt-cells = <2>; 491 interrupt-controller; 492 }; 493 494 apbdma: dma@60020000 { 495 compatible = "nvidia,tegra210-apbdma", "nvidia,tegra148-apbdma"; 496 reg = <0x0 0x60020000 0x0 0x1400>; 497 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 498 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 499 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 500 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 501 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 502 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 503 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 504 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 505 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 506 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 507 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 508 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 509 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 510 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 511 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 512 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 513 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 514 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 515 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 516 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 517 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 518 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 519 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 520 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 521 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 522 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 523 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 524 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 525 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 526 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 527 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 528 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 529 clocks = <&tegra_car TEGRA210_CLK_APBDMA>; 530 clock-names = "dma"; 531 resets = <&tegra_car 34>; 532 reset-names = "dma"; 533 #dma-cells = <1>; 534 }; 535 536 apbmisc@70000800 { 537 compatible = "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc"; 538 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */ 539 <0x0 0x70000008 0x0 0x04>; /* Strapping options */ 540 }; 541 542 pinmux: pinmux@700008d4 { 543 compatible = "nvidia,tegra210-pinmux"; 544 reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */ 545 <0x0 0x70003000 0x0 0x294>; /* Mux registers */ 546 sdmmc1_3v3_drv: sdmmc1-3v3-drv { 547 sdmmc1 { 548 nvidia,pins = "drive_sdmmc1"; 549 nvidia,pull-down-strength = <0x8>; 550 nvidia,pull-up-strength = <0x8>; 551 }; 552 }; 553 sdmmc1_1v8_drv: sdmmc1-1v8-drv { 554 sdmmc1 { 555 nvidia,pins = "drive_sdmmc1"; 556 nvidia,pull-down-strength = <0x4>; 557 nvidia,pull-up-strength = <0x3>; 558 }; 559 }; 560 sdmmc2_1v8_drv: sdmmc2-1v8-drv { 561 sdmmc2 { 562 nvidia,pins = "drive_sdmmc2"; 563 nvidia,pull-down-strength = <0x10>; 564 nvidia,pull-up-strength = <0x10>; 565 }; 566 }; 567 sdmmc3_3v3_drv: sdmmc3-3v3-drv { 568 sdmmc3 { 569 nvidia,pins = "drive_sdmmc3"; 570 nvidia,pull-down-strength = <0x8>; 571 nvidia,pull-up-strength = <0x8>; 572 }; 573 }; 574 sdmmc3_1v8_drv: sdmmc3-1v8-drv { 575 sdmmc3 { 576 nvidia,pins = "drive_sdmmc3"; 577 nvidia,pull-down-strength = <0x4>; 578 nvidia,pull-up-strength = <0x3>; 579 }; 580 }; 581 sdmmc4_1v8_drv: sdmmc4-1v8-drv { 582 sdmmc4 { 583 nvidia,pins = "drive_sdmmc4"; 584 nvidia,pull-down-strength = <0x10>; 585 nvidia,pull-up-strength = <0x10>; 586 }; 587 }; 588 }; 589 590 /* 591 * There are two serial driver i.e. 8250 based simple serial 592 * driver and APB DMA based serial driver for higher baudrate 593 * and performance. To enable the 8250 based driver, the compatible 594 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable 595 * the APB DMA based serial driver, the compatible is 596 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". 597 */ 598 uarta: serial@70006000 { 599 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 600 reg = <0x0 0x70006000 0x0 0x40>; 601 reg-shift = <2>; 602 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 603 clocks = <&tegra_car TEGRA210_CLK_UARTA>; 604 clock-names = "serial"; 605 resets = <&tegra_car 6>; 606 reset-names = "serial"; 607 dmas = <&apbdma 8>, <&apbdma 8>; 608 dma-names = "rx", "tx"; 609 status = "disabled"; 610 }; 611 612 uartb: serial@70006040 { 613 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 614 reg = <0x0 0x70006040 0x0 0x40>; 615 reg-shift = <2>; 616 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 617 clocks = <&tegra_car TEGRA210_CLK_UARTB>; 618 clock-names = "serial"; 619 resets = <&tegra_car 7>; 620 reset-names = "serial"; 621 dmas = <&apbdma 9>, <&apbdma 9>; 622 dma-names = "rx", "tx"; 623 status = "disabled"; 624 }; 625 626 uartc: serial@70006200 { 627 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 628 reg = <0x0 0x70006200 0x0 0x40>; 629 reg-shift = <2>; 630 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 631 clocks = <&tegra_car TEGRA210_CLK_UARTC>; 632 clock-names = "serial"; 633 resets = <&tegra_car 55>; 634 reset-names = "serial"; 635 dmas = <&apbdma 10>, <&apbdma 10>; 636 dma-names = "rx", "tx"; 637 status = "disabled"; 638 }; 639 640 uartd: serial@70006300 { 641 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 642 reg = <0x0 0x70006300 0x0 0x40>; 643 reg-shift = <2>; 644 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 645 clocks = <&tegra_car TEGRA210_CLK_UARTD>; 646 clock-names = "serial"; 647 resets = <&tegra_car 65>; 648 reset-names = "serial"; 649 dmas = <&apbdma 19>, <&apbdma 19>; 650 dma-names = "rx", "tx"; 651 status = "disabled"; 652 }; 653 654 pwm: pwm@7000a000 { 655 compatible = "nvidia,tegra210-pwm", "nvidia,tegra20-pwm"; 656 reg = <0x0 0x7000a000 0x0 0x100>; 657 #pwm-cells = <2>; 658 clocks = <&tegra_car TEGRA210_CLK_PWM>; 659 clock-names = "pwm"; 660 resets = <&tegra_car 17>; 661 reset-names = "pwm"; 662 status = "disabled"; 663 }; 664 665 i2c@7000c000 { 666 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 667 reg = <0x0 0x7000c000 0x0 0x100>; 668 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 669 #address-cells = <1>; 670 #size-cells = <0>; 671 clocks = <&tegra_car TEGRA210_CLK_I2C1>; 672 clock-names = "div-clk"; 673 resets = <&tegra_car 12>; 674 reset-names = "i2c"; 675 dmas = <&apbdma 21>, <&apbdma 21>; 676 dma-names = "rx", "tx"; 677 status = "disabled"; 678 }; 679 680 i2c@7000c400 { 681 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 682 reg = <0x0 0x7000c400 0x0 0x100>; 683 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 684 #address-cells = <1>; 685 #size-cells = <0>; 686 clocks = <&tegra_car TEGRA210_CLK_I2C2>; 687 clock-names = "div-clk"; 688 resets = <&tegra_car 54>; 689 reset-names = "i2c"; 690 dmas = <&apbdma 22>, <&apbdma 22>; 691 dma-names = "rx", "tx"; 692 status = "disabled"; 693 }; 694 695 i2c@7000c500 { 696 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 697 reg = <0x0 0x7000c500 0x0 0x100>; 698 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 699 #address-cells = <1>; 700 #size-cells = <0>; 701 clocks = <&tegra_car TEGRA210_CLK_I2C3>; 702 clock-names = "div-clk"; 703 resets = <&tegra_car 67>; 704 reset-names = "i2c"; 705 dmas = <&apbdma 23>, <&apbdma 23>; 706 dma-names = "rx", "tx"; 707 status = "disabled"; 708 }; 709 710 i2c@7000c700 { 711 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 712 reg = <0x0 0x7000c700 0x0 0x100>; 713 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 714 #address-cells = <1>; 715 #size-cells = <0>; 716 clocks = <&tegra_car TEGRA210_CLK_I2C4>; 717 clock-names = "div-clk"; 718 resets = <&tegra_car 103>; 719 reset-names = "i2c"; 720 dmas = <&apbdma 26>, <&apbdma 26>; 721 dma-names = "rx", "tx"; 722 pinctrl-0 = <&state_dpaux1_i2c>; 723 pinctrl-1 = <&state_dpaux1_off>; 724 pinctrl-names = "default", "idle"; 725 status = "disabled"; 726 }; 727 728 i2c@7000d000 { 729 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 730 reg = <0x0 0x7000d000 0x0 0x100>; 731 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 732 #address-cells = <1>; 733 #size-cells = <0>; 734 clocks = <&tegra_car TEGRA210_CLK_I2C5>; 735 clock-names = "div-clk"; 736 resets = <&tegra_car 47>; 737 reset-names = "i2c"; 738 dmas = <&apbdma 24>, <&apbdma 24>; 739 dma-names = "rx", "tx"; 740 status = "disabled"; 741 }; 742 743 i2c@7000d100 { 744 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 745 reg = <0x0 0x7000d100 0x0 0x100>; 746 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 747 #address-cells = <1>; 748 #size-cells = <0>; 749 clocks = <&tegra_car TEGRA210_CLK_I2C6>; 750 clock-names = "div-clk"; 751 resets = <&tegra_car 166>; 752 reset-names = "i2c"; 753 dmas = <&apbdma 30>, <&apbdma 30>; 754 dma-names = "rx", "tx"; 755 pinctrl-0 = <&state_dpaux_i2c>; 756 pinctrl-1 = <&state_dpaux_off>; 757 pinctrl-names = "default", "idle"; 758 status = "disabled"; 759 }; 760 761 spi@7000d400 { 762 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 763 reg = <0x0 0x7000d400 0x0 0x200>; 764 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 765 #address-cells = <1>; 766 #size-cells = <0>; 767 clocks = <&tegra_car TEGRA210_CLK_SBC1>; 768 clock-names = "spi"; 769 resets = <&tegra_car 41>; 770 reset-names = "spi"; 771 dmas = <&apbdma 15>, <&apbdma 15>; 772 dma-names = "rx", "tx"; 773 status = "disabled"; 774 }; 775 776 spi@7000d600 { 777 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 778 reg = <0x0 0x7000d600 0x0 0x200>; 779 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 780 #address-cells = <1>; 781 #size-cells = <0>; 782 clocks = <&tegra_car TEGRA210_CLK_SBC2>; 783 clock-names = "spi"; 784 resets = <&tegra_car 44>; 785 reset-names = "spi"; 786 dmas = <&apbdma 16>, <&apbdma 16>; 787 dma-names = "rx", "tx"; 788 status = "disabled"; 789 }; 790 791 spi@7000d800 { 792 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 793 reg = <0x0 0x7000d800 0x0 0x200>; 794 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 795 #address-cells = <1>; 796 #size-cells = <0>; 797 clocks = <&tegra_car TEGRA210_CLK_SBC3>; 798 clock-names = "spi"; 799 resets = <&tegra_car 46>; 800 reset-names = "spi"; 801 dmas = <&apbdma 17>, <&apbdma 17>; 802 dma-names = "rx", "tx"; 803 status = "disabled"; 804 }; 805 806 spi@7000da00 { 807 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 808 reg = <0x0 0x7000da00 0x0 0x200>; 809 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 810 #address-cells = <1>; 811 #size-cells = <0>; 812 clocks = <&tegra_car TEGRA210_CLK_SBC4>; 813 clock-names = "spi"; 814 resets = <&tegra_car 68>; 815 reset-names = "spi"; 816 dmas = <&apbdma 18>, <&apbdma 18>; 817 dma-names = "rx", "tx"; 818 status = "disabled"; 819 }; 820 821 rtc@7000e000 { 822 compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc"; 823 reg = <0x0 0x7000e000 0x0 0x100>; 824 interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; 825 interrupt-parent = <&tegra_pmc>; 826 clocks = <&tegra_car TEGRA210_CLK_RTC>; 827 clock-names = "rtc"; 828 }; 829 830 tegra_pmc: pmc@7000e400 { 831 compatible = "nvidia,tegra210-pmc"; 832 reg = <0x0 0x7000e400 0x0 0x400>; 833 clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; 834 clock-names = "pclk", "clk32k_in"; 835 #clock-cells = <1>; 836 #interrupt-cells = <2>; 837 interrupt-controller; 838 839 powergates { 840 pd_audio: aud { 841 clocks = <&tegra_car TEGRA210_CLK_APE>, 842 <&tegra_car TEGRA210_CLK_APB2APE>; 843 resets = <&tegra_car 198>; 844 #power-domain-cells = <0>; 845 }; 846 847 pd_sor: sor { 848 clocks = <&tegra_car TEGRA210_CLK_SOR0>, 849 <&tegra_car TEGRA210_CLK_SOR1>, 850 <&tegra_car TEGRA210_CLK_CILAB>, 851 <&tegra_car TEGRA210_CLK_CILCD>, 852 <&tegra_car TEGRA210_CLK_CILE>, 853 <&tegra_car TEGRA210_CLK_DSIA>, 854 <&tegra_car TEGRA210_CLK_DSIB>, 855 <&tegra_car TEGRA210_CLK_DPAUX>, 856 <&tegra_car TEGRA210_CLK_DPAUX1>, 857 <&tegra_car TEGRA210_CLK_MIPI_CAL>; 858 resets = <&tegra_car TEGRA210_CLK_SOR0>, 859 <&tegra_car TEGRA210_CLK_SOR1>, 860 <&tegra_car TEGRA210_CLK_DSIA>, 861 <&tegra_car TEGRA210_CLK_DSIB>, 862 <&tegra_car TEGRA210_CLK_DPAUX>, 863 <&tegra_car TEGRA210_CLK_DPAUX1>, 864 <&tegra_car TEGRA210_CLK_MIPI_CAL>; 865 #power-domain-cells = <0>; 866 }; 867 868 pd_xusbss: xusba { 869 clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>; 870 resets = <&tegra_car TEGRA210_CLK_XUSB_SS>; 871 #power-domain-cells = <0>; 872 }; 873 874 pd_xusbdev: xusbb { 875 clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>; 876 resets = <&tegra_car 95>; 877 #power-domain-cells = <0>; 878 }; 879 880 pd_xusbhost: xusbc { 881 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>; 882 resets = <&tegra_car TEGRA210_CLK_XUSB_HOST>; 883 #power-domain-cells = <0>; 884 }; 885 886 pd_vic: vic { 887 clocks = <&tegra_car TEGRA210_CLK_VIC03>; 888 clock-names = "vic"; 889 resets = <&tegra_car 178>; 890 reset-names = "vic"; 891 #power-domain-cells = <0>; 892 }; 893 894 pd_venc: venc { 895 clocks = <&tegra_car TEGRA210_CLK_VI>, 896 <&tegra_car TEGRA210_CLK_CSI>; 897 resets = <&mc TEGRA210_MC_RESET_VI>, 898 <&tegra_car 20>, 899 <&tegra_car 52>; 900 #power-domain-cells = <0>; 901 }; 902 }; 903 904 sdmmc1_3v3: sdmmc1-3v3 { 905 pins = "sdmmc1"; 906 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 907 }; 908 909 sdmmc1_1v8: sdmmc1-1v8 { 910 pins = "sdmmc1"; 911 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 912 }; 913 914 sdmmc3_3v3: sdmmc3-3v3 { 915 pins = "sdmmc3"; 916 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 917 }; 918 919 sdmmc3_1v8: sdmmc3-1v8 { 920 pins = "sdmmc3"; 921 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 922 }; 923 924 pex_dpd_disable: pex_en { 925 pex-dpd-disable { 926 pins = "pex-bias", "pex-clk1", "pex-clk2"; 927 low-power-disable; 928 }; 929 }; 930 931 pex_dpd_enable: pex_dis { 932 pex-dpd-enable { 933 pins = "pex-bias", "pex-clk1", "pex-clk2"; 934 low-power-enable; 935 }; 936 }; 937 }; 938 939 fuse@7000f800 { 940 compatible = "nvidia,tegra210-efuse"; 941 reg = <0x0 0x7000f800 0x0 0x400>; 942 clocks = <&tegra_car TEGRA210_CLK_FUSE>; 943 clock-names = "fuse"; 944 resets = <&tegra_car 39>; 945 reset-names = "fuse"; 946 }; 947 948 mc: memory-controller@70019000 { 949 compatible = "nvidia,tegra210-mc"; 950 reg = <0x0 0x70019000 0x0 0x1000>; 951 clocks = <&tegra_car TEGRA210_CLK_MC>; 952 clock-names = "mc"; 953 954 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 955 956 #iommu-cells = <1>; 957 #reset-cells = <1>; 958 }; 959 960 emc: external-memory-controller@7001b000 { 961 compatible = "nvidia,tegra210-emc"; 962 reg = <0x0 0x7001b000 0x0 0x1000>, 963 <0x0 0x7001e000 0x0 0x1000>, 964 <0x0 0x7001f000 0x0 0x1000>; 965 clocks = <&tegra_car TEGRA210_CLK_EMC>; 966 clock-names = "emc"; 967 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 968 nvidia,memory-controller = <&mc>; 969 #cooling-cells = <2>; 970 }; 971 972 sata@70020000 { 973 compatible = "nvidia,tegra210-ahci"; 974 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */ 975 <0x0 0x70020000 0x0 0x7000>, /* SATA */ 976 <0x0 0x70001100 0x0 0x1000>; /* SATA AUX */ 977 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 978 clocks = <&tegra_car TEGRA210_CLK_SATA>, 979 <&tegra_car TEGRA210_CLK_SATA_OOB>; 980 clock-names = "sata", "sata-oob"; 981 resets = <&tegra_car 124>, 982 <&tegra_car 129>, 983 <&tegra_car 123>; 984 reset-names = "sata", "sata-cold", "sata-oob"; 985 status = "disabled"; 986 }; 987 988 hda@70030000 { 989 compatible = "nvidia,tegra210-hda", "nvidia,tegra30-hda"; 990 reg = <0x0 0x70030000 0x0 0x10000>; 991 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 992 clocks = <&tegra_car TEGRA210_CLK_HDA>, 993 <&tegra_car TEGRA210_CLK_HDA2HDMI>, 994 <&tegra_car TEGRA210_CLK_HDA2CODEC_2X>; 995 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 996 resets = <&tegra_car 125>, /* hda */ 997 <&tegra_car 128>, /* hda2hdmi */ 998 <&tegra_car 111>; /* hda2codec_2x */ 999 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 1000 power-domains = <&pd_sor>; 1001 status = "disabled"; 1002 }; 1003 1004 usb@70090000 { 1005 compatible = "nvidia,tegra210-xusb"; 1006 reg = <0x0 0x70090000 0x0 0x8000>, 1007 <0x0 0x70098000 0x0 0x1000>, 1008 <0x0 0x70099000 0x0 0x1000>; 1009 reg-names = "hcd", "fpci", "ipfs"; 1010 1011 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 1012 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 1013 1014 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>, 1015 <&tegra_car TEGRA210_CLK_XUSB_HOST_SRC>, 1016 <&tegra_car TEGRA210_CLK_XUSB_FALCON_SRC>, 1017 <&tegra_car TEGRA210_CLK_XUSB_SS>, 1018 <&tegra_car TEGRA210_CLK_XUSB_SS_SRC>, 1019 <&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>, 1020 <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>, 1021 <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>, 1022 <&tegra_car TEGRA210_CLK_PLL_U_480M>, 1023 <&tegra_car TEGRA210_CLK_CLK_M>, 1024 <&tegra_car TEGRA210_CLK_PLL_E>; 1025 clock-names = "xusb_host", "xusb_host_src", 1026 "xusb_falcon_src", "xusb_ss", 1027 "xusb_ss_src", "xusb_ss_div2", 1028 "xusb_hs_src", "xusb_fs_src", 1029 "pll_u_480m", "clk_m", "pll_e"; 1030 resets = <&tegra_car 89>, <&tegra_car 156>, 1031 <&tegra_car 143>; 1032 reset-names = "xusb_host", "xusb_ss", "xusb_src"; 1033 power-domains = <&pd_xusbhost>, <&pd_xusbss>; 1034 power-domain-names = "xusb_host", "xusb_ss"; 1035 1036 nvidia,xusb-padctl = <&padctl>; 1037 1038 status = "disabled"; 1039 }; 1040 1041 padctl: padctl@7009f000 { 1042 compatible = "nvidia,tegra210-xusb-padctl"; 1043 reg = <0x0 0x7009f000 0x0 0x1000>; 1044 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 1045 resets = <&tegra_car 142>; 1046 reset-names = "padctl"; 1047 nvidia,pmc = <&tegra_pmc>; 1048 1049 status = "disabled"; 1050 1051 pads { 1052 usb2 { 1053 clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>; 1054 clock-names = "trk"; 1055 status = "disabled"; 1056 1057 lanes { 1058 usb2-0 { 1059 status = "disabled"; 1060 #phy-cells = <0>; 1061 }; 1062 1063 usb2-1 { 1064 status = "disabled"; 1065 #phy-cells = <0>; 1066 }; 1067 1068 usb2-2 { 1069 status = "disabled"; 1070 #phy-cells = <0>; 1071 }; 1072 1073 usb2-3 { 1074 status = "disabled"; 1075 #phy-cells = <0>; 1076 }; 1077 }; 1078 }; 1079 1080 hsic { 1081 clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>; 1082 clock-names = "trk"; 1083 status = "disabled"; 1084 1085 lanes { 1086 hsic-0 { 1087 status = "disabled"; 1088 #phy-cells = <0>; 1089 }; 1090 1091 hsic-1 { 1092 status = "disabled"; 1093 #phy-cells = <0>; 1094 }; 1095 }; 1096 }; 1097 1098 pcie { 1099 clocks = <&tegra_car TEGRA210_CLK_PLL_E>; 1100 clock-names = "pll"; 1101 resets = <&tegra_car 205>; 1102 reset-names = "phy"; 1103 status = "disabled"; 1104 1105 lanes { 1106 pcie-0 { 1107 status = "disabled"; 1108 #phy-cells = <0>; 1109 }; 1110 1111 pcie-1 { 1112 status = "disabled"; 1113 #phy-cells = <0>; 1114 }; 1115 1116 pcie-2 { 1117 status = "disabled"; 1118 #phy-cells = <0>; 1119 }; 1120 1121 pcie-3 { 1122 status = "disabled"; 1123 #phy-cells = <0>; 1124 }; 1125 1126 pcie-4 { 1127 status = "disabled"; 1128 #phy-cells = <0>; 1129 }; 1130 1131 pcie-5 { 1132 status = "disabled"; 1133 #phy-cells = <0>; 1134 }; 1135 1136 pcie-6 { 1137 status = "disabled"; 1138 #phy-cells = <0>; 1139 }; 1140 }; 1141 }; 1142 1143 sata { 1144 clocks = <&tegra_car TEGRA210_CLK_PLL_E>; 1145 clock-names = "pll"; 1146 resets = <&tegra_car 204>; 1147 reset-names = "phy"; 1148 status = "disabled"; 1149 1150 lanes { 1151 sata-0 { 1152 status = "disabled"; 1153 #phy-cells = <0>; 1154 }; 1155 }; 1156 }; 1157 }; 1158 1159 ports { 1160 usb2-0 { 1161 status = "disabled"; 1162 }; 1163 1164 usb2-1 { 1165 status = "disabled"; 1166 }; 1167 1168 usb2-2 { 1169 status = "disabled"; 1170 }; 1171 1172 usb2-3 { 1173 status = "disabled"; 1174 }; 1175 1176 hsic-0 { 1177 status = "disabled"; 1178 }; 1179 1180 usb3-0 { 1181 status = "disabled"; 1182 }; 1183 1184 usb3-1 { 1185 status = "disabled"; 1186 }; 1187 1188 usb3-2 { 1189 status = "disabled"; 1190 }; 1191 1192 usb3-3 { 1193 status = "disabled"; 1194 }; 1195 }; 1196 }; 1197 1198 mmc@700b0000 { 1199 compatible = "nvidia,tegra210-sdhci"; 1200 reg = <0x0 0x700b0000 0x0 0x200>; 1201 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1202 clocks = <&tegra_car TEGRA210_CLK_SDMMC1>, 1203 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>; 1204 clock-names = "sdhci", "tmclk"; 1205 resets = <&tegra_car 14>; 1206 reset-names = "sdhci"; 1207 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8", 1208 "sdmmc-3v3-drv", "sdmmc-1v8-drv"; 1209 pinctrl-0 = <&sdmmc1_3v3>; 1210 pinctrl-1 = <&sdmmc1_1v8>; 1211 pinctrl-2 = <&sdmmc1_3v3_drv>; 1212 pinctrl-3 = <&sdmmc1_1v8_drv>; 1213 nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>; 1214 nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>; 1215 nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>; 1216 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>; 1217 nvidia,default-tap = <0x2>; 1218 nvidia,default-trim = <0x4>; 1219 assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>, 1220 <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>, 1221 <&tegra_car TEGRA210_CLK_PLL_C4>; 1222 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 1223 assigned-clock-rates = <200000000>, <1000000000>, <1000000000>; 1224 status = "disabled"; 1225 }; 1226 1227 mmc@700b0200 { 1228 compatible = "nvidia,tegra210-sdhci"; 1229 reg = <0x0 0x700b0200 0x0 0x200>; 1230 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 1231 clocks = <&tegra_car TEGRA210_CLK_SDMMC2>, 1232 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>; 1233 clock-names = "sdhci", "tmclk"; 1234 resets = <&tegra_car 9>; 1235 reset-names = "sdhci"; 1236 pinctrl-names = "sdmmc-1v8-drv"; 1237 pinctrl-0 = <&sdmmc2_1v8_drv>; 1238 nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>; 1239 nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>; 1240 nvidia,default-tap = <0x8>; 1241 nvidia,default-trim = <0x0>; 1242 status = "disabled"; 1243 }; 1244 1245 mmc@700b0400 { 1246 compatible = "nvidia,tegra210-sdhci"; 1247 reg = <0x0 0x700b0400 0x0 0x200>; 1248 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 1249 clocks = <&tegra_car TEGRA210_CLK_SDMMC3>, 1250 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>; 1251 clock-names = "sdhci", "tmclk"; 1252 resets = <&tegra_car 69>; 1253 reset-names = "sdhci"; 1254 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8", 1255 "sdmmc-3v3-drv", "sdmmc-1v8-drv"; 1256 pinctrl-0 = <&sdmmc3_3v3>; 1257 pinctrl-1 = <&sdmmc3_1v8>; 1258 pinctrl-2 = <&sdmmc3_3v3_drv>; 1259 pinctrl-3 = <&sdmmc3_1v8_drv>; 1260 nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>; 1261 nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>; 1262 nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>; 1263 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>; 1264 nvidia,default-tap = <0x3>; 1265 nvidia,default-trim = <0x3>; 1266 status = "disabled"; 1267 }; 1268 1269 mmc@700b0600 { 1270 compatible = "nvidia,tegra210-sdhci"; 1271 reg = <0x0 0x700b0600 0x0 0x200>; 1272 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1273 clocks = <&tegra_car TEGRA210_CLK_SDMMC4>, 1274 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>; 1275 clock-names = "sdhci", "tmclk"; 1276 resets = <&tegra_car 15>; 1277 reset-names = "sdhci"; 1278 pinctrl-names = "sdmmc-3v3-drv", "sdmmc-1v8-drv"; 1279 pinctrl-0 = <&sdmmc4_1v8_drv>; 1280 pinctrl-1 = <&sdmmc4_1v8_drv>; 1281 nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>; 1282 nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>; 1283 nvidia,default-tap = <0x8>; 1284 nvidia,default-trim = <0x0>; 1285 assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>, 1286 <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 1287 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 1288 nvidia,dqs-trim = <40>; 1289 mmc-hs400-1_8v; 1290 status = "disabled"; 1291 }; 1292 1293 usb@700d0000 { 1294 compatible = "nvidia,tegra210-xudc"; 1295 reg = <0x0 0x700d0000 0x0 0x8000>, 1296 <0x0 0x700d8000 0x0 0x1000>, 1297 <0x0 0x700d9000 0x0 0x1000>; 1298 reg-names = "base", "fpci", "ipfs"; 1299 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1300 clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>, 1301 <&tegra_car TEGRA210_CLK_XUSB_SS>, 1302 <&tegra_car TEGRA210_CLK_XUSB_SSP_SRC>, 1303 <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>, 1304 <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>; 1305 clock-names = "dev", "ss", "ss_src", "fs_src", "hs_src"; 1306 power-domains = <&pd_xusbdev>, <&pd_xusbss>; 1307 power-domain-names = "dev", "ss"; 1308 nvidia,xusb-padctl = <&padctl>; 1309 status = "disabled"; 1310 }; 1311 1312 soctherm: thermal-sensor@700e2000 { 1313 compatible = "nvidia,tegra210-soctherm"; 1314 reg = <0x0 0x700e2000 0x0 0x600>, /* SOC_THERM reg_base */ 1315 <0x0 0x60006000 0x0 0x400>; /* CAR reg_base */ 1316 reg-names = "soctherm-reg", "car-reg"; 1317 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 1318 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 1319 interrupt-names = "thermal", "edp"; 1320 clocks = <&tegra_car TEGRA210_CLK_TSENSOR>, 1321 <&tegra_car TEGRA210_CLK_SOC_THERM>; 1322 clock-names = "tsensor", "soctherm"; 1323 resets = <&tegra_car 78>; 1324 reset-names = "soctherm"; 1325 #thermal-sensor-cells = <1>; 1326 1327 throttle-cfgs { 1328 throttle_heavy: heavy { 1329 nvidia,priority = <100>; 1330 nvidia,cpu-throt-percent = <85>; 1331 nvidia,gpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_HIGH>; 1332 1333 #cooling-cells = <2>; 1334 }; 1335 }; 1336 }; 1337 1338 mipi: mipi@700e3000 { 1339 compatible = "nvidia,tegra210-mipi"; 1340 reg = <0x0 0x700e3000 0x0 0x100>; 1341 clocks = <&tegra_car TEGRA210_CLK_MIPI_CAL>; 1342 clock-names = "mipi-cal"; 1343 power-domains = <&pd_sor>; 1344 #nvidia,mipi-calibrate-cells = <1>; 1345 }; 1346 1347 dfll: clock@70110000 { 1348 compatible = "nvidia,tegra210-dfll"; 1349 reg = <0 0x70110000 0 0x100>, /* DFLL control */ 1350 <0 0x70110000 0 0x100>, /* I2C output control */ 1351 <0 0x70110100 0 0x100>, /* Integrated I2C controller */ 1352 <0 0x70110200 0 0x100>; /* Look-up table RAM */ 1353 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 1354 clocks = <&tegra_car TEGRA210_CLK_DFLL_SOC>, 1355 <&tegra_car TEGRA210_CLK_DFLL_REF>, 1356 <&tegra_car TEGRA210_CLK_I2C5>; 1357 clock-names = "soc", "ref", "i2c"; 1358 resets = <&tegra_car TEGRA210_RST_DFLL_DVCO>, 1359 <&tegra_car 155>; 1360 reset-names = "dvco", "dfll"; 1361 #clock-cells = <0>; 1362 clock-output-names = "dfllCPU_out"; 1363 status = "disabled"; 1364 }; 1365 1366 aconnect@702c0000 { 1367 compatible = "nvidia,tegra210-aconnect"; 1368 clocks = <&tegra_car TEGRA210_CLK_APE>, 1369 <&tegra_car TEGRA210_CLK_APB2APE>; 1370 clock-names = "ape", "apb2ape"; 1371 power-domains = <&pd_audio>; 1372 #address-cells = <1>; 1373 #size-cells = <1>; 1374 ranges = <0x702c0000 0x0 0x702c0000 0x00040000>; 1375 status = "disabled"; 1376 1377 adma: dma-controller@702e2000 { 1378 compatible = "nvidia,tegra210-adma"; 1379 reg = <0x702e2000 0x2000>; 1380 interrupt-parent = <&agic>; 1381 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 1382 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 1383 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 1384 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 1385 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 1386 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 1387 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 1388 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 1389 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 1390 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 1391 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 1392 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 1393 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 1394 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 1395 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 1396 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 1397 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 1398 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 1399 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 1400 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 1401 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 1402 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1403 #dma-cells = <1>; 1404 clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>; 1405 clock-names = "d_audio"; 1406 status = "disabled"; 1407 }; 1408 1409 agic: interrupt-controller@702f9000 { 1410 compatible = "nvidia,tegra210-agic"; 1411 #interrupt-cells = <3>; 1412 interrupt-controller; 1413 reg = <0x702f9000 0x1000>, 1414 <0x702fa000 0x2000>; 1415 interrupts = <GIC_SPI 102 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1416 clocks = <&tegra_car TEGRA210_CLK_APE>; 1417 clock-names = "clk"; 1418 status = "disabled"; 1419 }; 1420 1421 tegra_ahub: ahub@702d0800 { 1422 compatible = "nvidia,tegra210-ahub"; 1423 reg = <0x702d0800 0x800>; 1424 clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>; 1425 clock-names = "ahub"; 1426 assigned-clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>; 1427 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1428 #address-cells = <1>; 1429 #size-cells = <1>; 1430 ranges = <0x702d0000 0x702d0000 0x0000e400>; 1431 status = "disabled"; 1432 1433 tegra_admaif: admaif@702d0000 { 1434 compatible = "nvidia,tegra210-admaif"; 1435 reg = <0x702d0000 0x800>; 1436 dmas = <&adma 1>, <&adma 1>, 1437 <&adma 2>, <&adma 2>, 1438 <&adma 3>, <&adma 3>, 1439 <&adma 4>, <&adma 4>, 1440 <&adma 5>, <&adma 5>, 1441 <&adma 6>, <&adma 6>, 1442 <&adma 7>, <&adma 7>, 1443 <&adma 8>, <&adma 8>, 1444 <&adma 9>, <&adma 9>, 1445 <&adma 10>, <&adma 10>; 1446 dma-names = "rx1", "tx1", 1447 "rx2", "tx2", 1448 "rx3", "tx3", 1449 "rx4", "tx4", 1450 "rx5", "tx5", 1451 "rx6", "tx6", 1452 "rx7", "tx7", 1453 "rx8", "tx8", 1454 "rx9", "tx9", 1455 "rx10", "tx10"; 1456 status = "disabled"; 1457 1458 ports { 1459 #address-cells = <1>; 1460 #size-cells = <0>; 1461 1462 admaif1_port: port@0 { 1463 reg = <0>; 1464 1465 admaif1_ep: endpoint { 1466 remote-endpoint = <&xbar_admaif1_ep>; 1467 }; 1468 }; 1469 1470 admaif2_port: port@1 { 1471 reg = <1>; 1472 1473 admaif2_ep: endpoint { 1474 remote-endpoint = <&xbar_admaif2_ep>; 1475 }; 1476 }; 1477 1478 admaif3_port: port@2 { 1479 reg = <2>; 1480 1481 admaif3_ep: endpoint { 1482 remote-endpoint = <&xbar_admaif3_ep>; 1483 }; 1484 }; 1485 1486 admaif4_port: port@3 { 1487 reg = <3>; 1488 1489 admaif4_ep: endpoint { 1490 remote-endpoint = <&xbar_admaif4_ep>; 1491 }; 1492 }; 1493 1494 admaif5_port: port@4 { 1495 reg = <4>; 1496 1497 admaif5_ep: endpoint { 1498 remote-endpoint = <&xbar_admaif5_ep>; 1499 }; 1500 }; 1501 1502 admaif6_port: port@5 { 1503 reg = <5>; 1504 1505 admaif6_ep: endpoint { 1506 remote-endpoint = <&xbar_admaif6_ep>; 1507 }; 1508 }; 1509 1510 admaif7_port: port@6 { 1511 reg = <6>; 1512 1513 admaif7_ep: endpoint { 1514 remote-endpoint = <&xbar_admaif7_ep>; 1515 }; 1516 }; 1517 1518 admaif8_port: port@7 { 1519 reg = <7>; 1520 1521 admaif8_ep: endpoint { 1522 remote-endpoint = <&xbar_admaif8_ep>; 1523 }; 1524 }; 1525 1526 admaif9_port: port@8 { 1527 reg = <8>; 1528 1529 admaif9_ep: endpoint { 1530 remote-endpoint = <&xbar_admaif9_ep>; 1531 }; 1532 }; 1533 1534 admaif10_port: port@9 { 1535 reg = <9>; 1536 1537 admaif10_ep: endpoint { 1538 remote-endpoint = <&xbar_admaif10_ep>; 1539 }; 1540 }; 1541 }; 1542 }; 1543 1544 tegra_i2s1: i2s@702d1000 { 1545 compatible = "nvidia,tegra210-i2s"; 1546 reg = <0x702d1000 0x100>; 1547 clocks = <&tegra_car TEGRA210_CLK_I2S0>, 1548 <&tegra_car TEGRA210_CLK_I2S0_SYNC>; 1549 clock-names = "i2s", "sync_input"; 1550 assigned-clocks = <&tegra_car TEGRA210_CLK_I2S0>; 1551 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1552 assigned-clock-rates = <1536000>; 1553 sound-name-prefix = "I2S1"; 1554 status = "disabled"; 1555 }; 1556 1557 tegra_i2s2: i2s@702d1100 { 1558 compatible = "nvidia,tegra210-i2s"; 1559 reg = <0x702d1100 0x100>; 1560 clocks = <&tegra_car TEGRA210_CLK_I2S1>, 1561 <&tegra_car TEGRA210_CLK_I2S1_SYNC>; 1562 clock-names = "i2s", "sync_input"; 1563 assigned-clocks = <&tegra_car TEGRA210_CLK_I2S1>; 1564 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1565 assigned-clock-rates = <1536000>; 1566 sound-name-prefix = "I2S2"; 1567 status = "disabled"; 1568 }; 1569 1570 tegra_i2s3: i2s@702d1200 { 1571 compatible = "nvidia,tegra210-i2s"; 1572 reg = <0x702d1200 0x100>; 1573 clocks = <&tegra_car TEGRA210_CLK_I2S2>, 1574 <&tegra_car TEGRA210_CLK_I2S2_SYNC>; 1575 clock-names = "i2s", "sync_input"; 1576 assigned-clocks = <&tegra_car TEGRA210_CLK_I2S2>; 1577 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1578 assigned-clock-rates = <1536000>; 1579 sound-name-prefix = "I2S3"; 1580 status = "disabled"; 1581 }; 1582 1583 tegra_i2s4: i2s@702d1300 { 1584 compatible = "nvidia,tegra210-i2s"; 1585 reg = <0x702d1300 0x100>; 1586 clocks = <&tegra_car TEGRA210_CLK_I2S3>, 1587 <&tegra_car TEGRA210_CLK_I2S3_SYNC>; 1588 clock-names = "i2s", "sync_input"; 1589 assigned-clocks = <&tegra_car TEGRA210_CLK_I2S3>; 1590 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1591 assigned-clock-rates = <1536000>; 1592 sound-name-prefix = "I2S4"; 1593 status = "disabled"; 1594 }; 1595 1596 tegra_i2s5: i2s@702d1400 { 1597 compatible = "nvidia,tegra210-i2s"; 1598 reg = <0x702d1400 0x100>; 1599 clocks = <&tegra_car TEGRA210_CLK_I2S4>, 1600 <&tegra_car TEGRA210_CLK_I2S4_SYNC>; 1601 clock-names = "i2s", "sync_input"; 1602 assigned-clocks = <&tegra_car TEGRA210_CLK_I2S4>; 1603 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1604 assigned-clock-rates = <1536000>; 1605 sound-name-prefix = "I2S5"; 1606 status = "disabled"; 1607 }; 1608 1609 tegra_dmic1: dmic@702d4000 { 1610 compatible = "nvidia,tegra210-dmic"; 1611 reg = <0x702d4000 0x100>; 1612 clocks = <&tegra_car TEGRA210_CLK_DMIC1>; 1613 clock-names = "dmic"; 1614 assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC1>; 1615 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1616 assigned-clock-rates = <3072000>; 1617 sound-name-prefix = "DMIC1"; 1618 status = "disabled"; 1619 }; 1620 1621 tegra_dmic2: dmic@702d4100 { 1622 compatible = "nvidia,tegra210-dmic"; 1623 reg = <0x702d4100 0x100>; 1624 clocks = <&tegra_car TEGRA210_CLK_DMIC2>; 1625 clock-names = "dmic"; 1626 assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC2>; 1627 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1628 assigned-clock-rates = <3072000>; 1629 sound-name-prefix = "DMIC2"; 1630 status = "disabled"; 1631 }; 1632 1633 tegra_dmic3: dmic@702d4200 { 1634 compatible = "nvidia,tegra210-dmic"; 1635 reg = <0x702d4200 0x100>; 1636 clocks = <&tegra_car TEGRA210_CLK_DMIC3>; 1637 clock-names = "dmic"; 1638 assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC3>; 1639 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1640 assigned-clock-rates = <3072000>; 1641 sound-name-prefix = "DMIC3"; 1642 status = "disabled"; 1643 }; 1644 1645 ports { 1646 #address-cells = <1>; 1647 #size-cells = <0>; 1648 1649 port@0 { 1650 reg = <0x0>; 1651 1652 xbar_admaif1_ep: endpoint { 1653 remote-endpoint = <&admaif1_ep>; 1654 }; 1655 }; 1656 1657 port@1 { 1658 reg = <0x1>; 1659 1660 xbar_admaif2_ep: endpoint { 1661 remote-endpoint = <&admaif2_ep>; 1662 }; 1663 }; 1664 1665 port@2 { 1666 reg = <0x2>; 1667 1668 xbar_admaif3_ep: endpoint { 1669 remote-endpoint = <&admaif3_ep>; 1670 }; 1671 }; 1672 1673 port@3 { 1674 reg = <0x3>; 1675 1676 xbar_admaif4_ep: endpoint { 1677 remote-endpoint = <&admaif4_ep>; 1678 }; 1679 }; 1680 1681 port@4 { 1682 reg = <0x4>; 1683 xbar_admaif5_ep: endpoint { 1684 remote-endpoint = <&admaif5_ep>; 1685 }; 1686 }; 1687 port@5 { 1688 reg = <0x5>; 1689 1690 xbar_admaif6_ep: endpoint { 1691 remote-endpoint = <&admaif6_ep>; 1692 }; 1693 }; 1694 1695 port@6 { 1696 reg = <0x6>; 1697 1698 xbar_admaif7_ep: endpoint { 1699 remote-endpoint = <&admaif7_ep>; 1700 }; 1701 }; 1702 1703 port@7 { 1704 reg = <0x7>; 1705 1706 xbar_admaif8_ep: endpoint { 1707 remote-endpoint = <&admaif8_ep>; 1708 }; 1709 }; 1710 1711 port@8 { 1712 reg = <0x8>; 1713 1714 xbar_admaif9_ep: endpoint { 1715 remote-endpoint = <&admaif9_ep>; 1716 }; 1717 }; 1718 1719 port@9 { 1720 reg = <0x9>; 1721 1722 xbar_admaif10_ep: endpoint { 1723 remote-endpoint = <&admaif10_ep>; 1724 }; 1725 }; 1726 }; 1727 }; 1728 }; 1729 1730 spi@70410000 { 1731 compatible = "nvidia,tegra210-qspi"; 1732 reg = <0x0 0x70410000 0x0 0x1000>; 1733 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1734 #address-cells = <1>; 1735 #size-cells = <0>; 1736 clocks = <&tegra_car TEGRA210_CLK_QSPI>, 1737 <&tegra_car TEGRA210_CLK_QSPI_PM>; 1738 clock-names = "qspi", "qspi_out"; 1739 resets = <&tegra_car 211>; 1740 reset-names = "qspi"; 1741 dmas = <&apbdma 5>, <&apbdma 5>; 1742 dma-names = "rx", "tx"; 1743 status = "disabled"; 1744 }; 1745 1746 usb@7d000000 { 1747 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 1748 reg = <0x0 0x7d000000 0x0 0x4000>; 1749 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1750 phy_type = "utmi"; 1751 clocks = <&tegra_car TEGRA210_CLK_USBD>; 1752 clock-names = "usb"; 1753 resets = <&tegra_car 22>; 1754 reset-names = "usb"; 1755 nvidia,phy = <&phy1>; 1756 status = "disabled"; 1757 }; 1758 1759 phy1: usb-phy@7d000000 { 1760 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; 1761 reg = <0x0 0x7d000000 0x0 0x4000>, 1762 <0x0 0x7d000000 0x0 0x4000>; 1763 phy_type = "utmi"; 1764 clocks = <&tegra_car TEGRA210_CLK_USBD>, 1765 <&tegra_car TEGRA210_CLK_PLL_U>, 1766 <&tegra_car TEGRA210_CLK_USBD>; 1767 clock-names = "reg", "pll_u", "utmi-pads"; 1768 resets = <&tegra_car 22>, <&tegra_car 22>; 1769 reset-names = "usb", "utmi-pads"; 1770 nvidia,hssync-start-delay = <0>; 1771 nvidia,idle-wait-delay = <17>; 1772 nvidia,elastic-limit = <16>; 1773 nvidia,term-range-adj = <6>; 1774 nvidia,xcvr-setup = <9>; 1775 nvidia,xcvr-lsfslew = <0>; 1776 nvidia,xcvr-lsrslew = <3>; 1777 nvidia,hssquelch-level = <2>; 1778 nvidia,hsdiscon-level = <5>; 1779 nvidia,xcvr-hsslew = <12>; 1780 nvidia,has-utmi-pad-registers; 1781 status = "disabled"; 1782 }; 1783 1784 usb@7d004000 { 1785 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 1786 reg = <0x0 0x7d004000 0x0 0x4000>; 1787 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1788 phy_type = "utmi"; 1789 clocks = <&tegra_car TEGRA210_CLK_USB2>; 1790 clock-names = "usb"; 1791 resets = <&tegra_car 58>; 1792 reset-names = "usb"; 1793 nvidia,phy = <&phy2>; 1794 status = "disabled"; 1795 }; 1796 1797 phy2: usb-phy@7d004000 { 1798 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; 1799 reg = <0x0 0x7d004000 0x0 0x4000>, 1800 <0x0 0x7d000000 0x0 0x4000>; 1801 phy_type = "utmi"; 1802 clocks = <&tegra_car TEGRA210_CLK_USB2>, 1803 <&tegra_car TEGRA210_CLK_PLL_U>, 1804 <&tegra_car TEGRA210_CLK_USBD>; 1805 clock-names = "reg", "pll_u", "utmi-pads"; 1806 resets = <&tegra_car 58>, <&tegra_car 22>; 1807 reset-names = "usb", "utmi-pads"; 1808 nvidia,hssync-start-delay = <0>; 1809 nvidia,idle-wait-delay = <17>; 1810 nvidia,elastic-limit = <16>; 1811 nvidia,term-range-adj = <6>; 1812 nvidia,xcvr-setup = <9>; 1813 nvidia,xcvr-lsfslew = <0>; 1814 nvidia,xcvr-lsrslew = <3>; 1815 nvidia,hssquelch-level = <2>; 1816 nvidia,hsdiscon-level = <5>; 1817 nvidia,xcvr-hsslew = <12>; 1818 status = "disabled"; 1819 }; 1820 1821 cpus { 1822 #address-cells = <1>; 1823 #size-cells = <0>; 1824 1825 cpu@0 { 1826 device_type = "cpu"; 1827 compatible = "arm,cortex-a57"; 1828 reg = <0>; 1829 clocks = <&tegra_car TEGRA210_CLK_CCLK_G>, 1830 <&tegra_car TEGRA210_CLK_PLL_X>, 1831 <&tegra_car TEGRA210_CLK_PLL_P_OUT4>, 1832 <&dfll>; 1833 clock-names = "cpu_g", "pll_x", "pll_p", "dfll"; 1834 clock-latency = <300000>; 1835 cpu-idle-states = <&CPU_SLEEP>; 1836 next-level-cache = <&L2>; 1837 }; 1838 1839 cpu@1 { 1840 device_type = "cpu"; 1841 compatible = "arm,cortex-a57"; 1842 reg = <1>; 1843 cpu-idle-states = <&CPU_SLEEP>; 1844 next-level-cache = <&L2>; 1845 }; 1846 1847 cpu@2 { 1848 device_type = "cpu"; 1849 compatible = "arm,cortex-a57"; 1850 reg = <2>; 1851 cpu-idle-states = <&CPU_SLEEP>; 1852 next-level-cache = <&L2>; 1853 }; 1854 1855 cpu@3 { 1856 device_type = "cpu"; 1857 compatible = "arm,cortex-a57"; 1858 reg = <3>; 1859 cpu-idle-states = <&CPU_SLEEP>; 1860 next-level-cache = <&L2>; 1861 }; 1862 1863 idle-states { 1864 entry-method = "psci"; 1865 1866 CPU_SLEEP: cpu-sleep { 1867 compatible = "arm,idle-state"; 1868 arm,psci-suspend-param = <0x40000007>; 1869 entry-latency-us = <100>; 1870 exit-latency-us = <30>; 1871 min-residency-us = <1000>; 1872 wakeup-latency-us = <130>; 1873 idle-state-name = "cpu-sleep"; 1874 status = "disabled"; 1875 }; 1876 }; 1877 1878 L2: l2-cache { 1879 compatible = "cache"; 1880 }; 1881 }; 1882 1883 pmu { 1884 compatible = "arm,armv8-pmuv3"; 1885 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1886 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1887 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1888 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 1889 interrupt-affinity = <&{/cpus/cpu@0} &{/cpus/cpu@1} 1890 &{/cpus/cpu@2} &{/cpus/cpu@3}>; 1891 }; 1892 1893 sound { 1894 status = "disabled"; 1895 1896 clocks = <&tegra_car TEGRA210_CLK_PLL_A>, 1897 <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1898 clock-names = "pll_a", "plla_out0"; 1899 1900 assigned-clocks = <&tegra_car TEGRA210_CLK_PLL_A>, 1901 <&tegra_car TEGRA210_CLK_PLL_A_OUT0>, 1902 <&tegra_car TEGRA210_CLK_EXTERN1>; 1903 assigned-clock-parents = <0>, <0>, <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1904 assigned-clock-rates = <368640000>, <49152000>, <12288000>; 1905 }; 1906 1907 thermal-zones { 1908 cpu { 1909 polling-delay-passive = <1000>; 1910 polling-delay = <0>; 1911 1912 thermal-sensors = 1913 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; 1914 1915 trips { 1916 cpu-shutdown-trip { 1917 temperature = <102500>; 1918 hysteresis = <0>; 1919 type = "critical"; 1920 }; 1921 1922 cpu_throttle_trip: throttle-trip { 1923 temperature = <98500>; 1924 hysteresis = <1000>; 1925 type = "hot"; 1926 }; 1927 }; 1928 1929 cooling-maps { 1930 map0 { 1931 trip = <&cpu_throttle_trip>; 1932 cooling-device = <&throttle_heavy 1 1>; 1933 }; 1934 }; 1935 }; 1936 1937 mem { 1938 polling-delay-passive = <0>; 1939 polling-delay = <0>; 1940 1941 thermal-sensors = 1942 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>; 1943 1944 trips { 1945 dram_nominal: mem-nominal-trip { 1946 temperature = <50000>; 1947 hysteresis = <1000>; 1948 type = "passive"; 1949 }; 1950 1951 dram_throttle: mem-throttle-trip { 1952 temperature = <70000>; 1953 hysteresis = <1000>; 1954 type = "active"; 1955 }; 1956 1957 mem-hot-trip { 1958 temperature = <100000>; 1959 hysteresis = <1000>; 1960 type = "hot"; 1961 }; 1962 1963 mem-shutdown-trip { 1964 temperature = <103000>; 1965 hysteresis = <0>; 1966 type = "critical"; 1967 }; 1968 }; 1969 1970 cooling-maps { 1971 dram-passive { 1972 cooling-device = <&emc 0 0>; 1973 trip = <&dram_nominal>; 1974 }; 1975 1976 dram-active { 1977 cooling-device = <&emc 1 1>; 1978 trip = <&dram_throttle>; 1979 }; 1980 }; 1981 }; 1982 1983 gpu { 1984 polling-delay-passive = <1000>; 1985 polling-delay = <0>; 1986 1987 thermal-sensors = 1988 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>; 1989 1990 trips { 1991 gpu-shutdown-trip { 1992 temperature = <103000>; 1993 hysteresis = <0>; 1994 type = "critical"; 1995 }; 1996 1997 gpu_throttle_trip: throttle-trip { 1998 temperature = <100000>; 1999 hysteresis = <1000>; 2000 type = "hot"; 2001 }; 2002 }; 2003 2004 cooling-maps { 2005 map0 { 2006 trip = <&gpu_throttle_trip>; 2007 cooling-device = <&throttle_heavy 1 1>; 2008 }; 2009 }; 2010 }; 2011 2012 pllx { 2013 polling-delay-passive = <0>; 2014 polling-delay = <0>; 2015 2016 thermal-sensors = 2017 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>; 2018 2019 trips { 2020 pllx-shutdown-trip { 2021 temperature = <103000>; 2022 hysteresis = <0>; 2023 type = "critical"; 2024 }; 2025 2026 pllx-throttle-trip { 2027 temperature = <100000>; 2028 hysteresis = <1000>; 2029 type = "hot"; 2030 }; 2031 }; 2032 2033 cooling-maps { 2034 /* 2035 * There are currently no cooling maps, 2036 * because there are no cooling devices. 2037 */ 2038 }; 2039 }; 2040 }; 2041 2042 timer { 2043 compatible = "arm,armv8-timer"; 2044 interrupts = <GIC_PPI 13 2045 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2046 <GIC_PPI 14 2047 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2048 <GIC_PPI 11 2049 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2050 <GIC_PPI 10 2051 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 2052 interrupt-parent = <&gic>; 2053 arm,no-tick-in-suspend; 2054 }; 2055}; 2056