1#include <dt-bindings/clock/tegra210-car.h> 2#include <dt-bindings/gpio/tegra-gpio.h> 3#include <dt-bindings/memory/tegra210-mc.h> 4#include <dt-bindings/pinctrl/pinctrl-tegra.h> 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6 7/ { 8 compatible = "nvidia,tegra210"; 9 interrupt-parent = <&lic>; 10 #address-cells = <2>; 11 #size-cells = <2>; 12 13 host1x@50000000 { 14 compatible = "nvidia,tegra210-host1x", "simple-bus"; 15 reg = <0x0 0x50000000 0x0 0x00034000>; 16 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 17 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ 18 clocks = <&tegra_car TEGRA210_CLK_HOST1X>; 19 clock-names = "host1x"; 20 resets = <&tegra_car 28>; 21 reset-names = "host1x"; 22 23 #address-cells = <2>; 24 #size-cells = <2>; 25 26 ranges = <0x0 0x54000000 0x0 0x54000000 0x0 0x01000000>; 27 28 dpaux1: dpaux@54040000 { 29 compatible = "nvidia,tegra210-dpaux"; 30 reg = <0x0 0x54040000 0x0 0x00040000>; 31 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 32 clocks = <&tegra_car TEGRA210_CLK_DPAUX1>, 33 <&tegra_car TEGRA210_CLK_PLL_DP>; 34 clock-names = "dpaux", "parent"; 35 resets = <&tegra_car 207>; 36 reset-names = "dpaux"; 37 power-domains = <&pd_sor>; 38 status = "disabled"; 39 40 state_dpaux1_aux: pinmux-aux { 41 groups = "dpaux-io"; 42 function = "aux"; 43 }; 44 45 state_dpaux1_i2c: pinmux-i2c { 46 groups = "dpaux-io"; 47 function = "i2c"; 48 }; 49 50 state_dpaux1_off: pinmux-off { 51 groups = "dpaux-io"; 52 function = "off"; 53 }; 54 55 i2c-bus { 56 #address-cells = <1>; 57 #size-cells = <0>; 58 }; 59 }; 60 61 vi@54080000 { 62 compatible = "nvidia,tegra210-vi"; 63 reg = <0x0 0x54080000 0x0 0x00040000>; 64 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 65 status = "disabled"; 66 }; 67 68 tsec@54100000 { 69 compatible = "nvidia,tegra210-tsec"; 70 reg = <0x0 0x54100000 0x0 0x00040000>; 71 }; 72 73 dc@54200000 { 74 compatible = "nvidia,tegra210-dc"; 75 reg = <0x0 0x54200000 0x0 0x00040000>; 76 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 77 clocks = <&tegra_car TEGRA210_CLK_DISP1>, 78 <&tegra_car TEGRA210_CLK_PLL_P>; 79 clock-names = "dc", "parent"; 80 resets = <&tegra_car 27>; 81 reset-names = "dc"; 82 83 iommus = <&mc TEGRA_SWGROUP_DC>; 84 85 nvidia,head = <0>; 86 }; 87 88 dc@54240000 { 89 compatible = "nvidia,tegra210-dc"; 90 reg = <0x0 0x54240000 0x0 0x00040000>; 91 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 92 clocks = <&tegra_car TEGRA210_CLK_DISP2>, 93 <&tegra_car TEGRA210_CLK_PLL_P>; 94 clock-names = "dc", "parent"; 95 resets = <&tegra_car 26>; 96 reset-names = "dc"; 97 98 iommus = <&mc TEGRA_SWGROUP_DCB>; 99 100 nvidia,head = <1>; 101 }; 102 103 dsi@54300000 { 104 compatible = "nvidia,tegra210-dsi"; 105 reg = <0x0 0x54300000 0x0 0x00040000>; 106 clocks = <&tegra_car TEGRA210_CLK_DSIA>, 107 <&tegra_car TEGRA210_CLK_DSIALP>, 108 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; 109 clock-names = "dsi", "lp", "parent"; 110 resets = <&tegra_car 48>; 111 reset-names = "dsi"; 112 power-domains = <&pd_sor>; 113 nvidia,mipi-calibrate = <&mipi 0x0c0>; /* DSIA & DSIB pads */ 114 115 status = "disabled"; 116 117 #address-cells = <1>; 118 #size-cells = <0>; 119 }; 120 121 vic@54340000 { 122 compatible = "nvidia,tegra210-vic"; 123 reg = <0x0 0x54340000 0x0 0x00040000>; 124 status = "disabled"; 125 }; 126 127 nvjpg@54380000 { 128 compatible = "nvidia,tegra210-nvjpg"; 129 reg = <0x0 0x54380000 0x0 0x00040000>; 130 status = "disabled"; 131 }; 132 133 dsi@54400000 { 134 compatible = "nvidia,tegra210-dsi"; 135 reg = <0x0 0x54400000 0x0 0x00040000>; 136 clocks = <&tegra_car TEGRA210_CLK_DSIB>, 137 <&tegra_car TEGRA210_CLK_DSIBLP>, 138 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; 139 clock-names = "dsi", "lp", "parent"; 140 resets = <&tegra_car 82>; 141 reset-names = "dsi"; 142 power-domains = <&pd_sor>; 143 nvidia,mipi-calibrate = <&mipi 0x300>; /* DSIC & DSID pads */ 144 145 status = "disabled"; 146 147 #address-cells = <1>; 148 #size-cells = <0>; 149 }; 150 151 nvdec@54480000 { 152 compatible = "nvidia,tegra210-nvdec"; 153 reg = <0x0 0x54480000 0x0 0x00040000>; 154 status = "disabled"; 155 }; 156 157 nvenc@544c0000 { 158 compatible = "nvidia,tegra210-nvenc"; 159 reg = <0x0 0x544c0000 0x0 0x00040000>; 160 status = "disabled"; 161 }; 162 163 tsec@54500000 { 164 compatible = "nvidia,tegra210-tsec"; 165 reg = <0x0 0x54500000 0x0 0x00040000>; 166 status = "disabled"; 167 }; 168 169 sor@54540000 { 170 compatible = "nvidia,tegra210-sor"; 171 reg = <0x0 0x54540000 0x0 0x00040000>; 172 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 173 clocks = <&tegra_car TEGRA210_CLK_SOR0>, 174 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>, 175 <&tegra_car TEGRA210_CLK_PLL_DP>, 176 <&tegra_car TEGRA210_CLK_SOR_SAFE>; 177 clock-names = "sor", "parent", "dp", "safe"; 178 resets = <&tegra_car 182>; 179 reset-names = "sor"; 180 pinctrl-0 = <&state_dpaux_aux>; 181 pinctrl-1 = <&state_dpaux_i2c>; 182 pinctrl-2 = <&state_dpaux_off>; 183 pinctrl-names = "aux", "i2c", "off"; 184 power-domains = <&pd_sor>; 185 status = "disabled"; 186 }; 187 188 sor@54580000 { 189 compatible = "nvidia,tegra210-sor1"; 190 reg = <0x0 0x54580000 0x0 0x00040000>; 191 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 192 clocks = <&tegra_car TEGRA210_CLK_SOR1>, 193 <&tegra_car TEGRA210_CLK_SOR1_SRC>, 194 <&tegra_car TEGRA210_CLK_PLL_D2_OUT0>, 195 <&tegra_car TEGRA210_CLK_PLL_DP>, 196 <&tegra_car TEGRA210_CLK_SOR_SAFE>; 197 clock-names = "sor", "source", "parent", "dp", "safe"; 198 resets = <&tegra_car 183>; 199 reset-names = "sor"; 200 pinctrl-0 = <&state_dpaux1_aux>; 201 pinctrl-1 = <&state_dpaux1_i2c>; 202 pinctrl-2 = <&state_dpaux1_off>; 203 pinctrl-names = "aux", "i2c", "off"; 204 power-domains = <&pd_sor>; 205 status = "disabled"; 206 }; 207 208 dpaux: dpaux@545c0000 { 209 compatible = "nvidia,tegra124-dpaux"; 210 reg = <0x0 0x545c0000 0x0 0x00040000>; 211 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 212 clocks = <&tegra_car TEGRA210_CLK_DPAUX>, 213 <&tegra_car TEGRA210_CLK_PLL_DP>; 214 clock-names = "dpaux", "parent"; 215 resets = <&tegra_car 181>; 216 reset-names = "dpaux"; 217 power-domains = <&pd_sor>; 218 status = "disabled"; 219 220 state_dpaux_aux: pinmux-aux { 221 groups = "dpaux-io"; 222 function = "aux"; 223 }; 224 225 state_dpaux_i2c: pinmux-i2c { 226 groups = "dpaux-io"; 227 function = "i2c"; 228 }; 229 230 state_dpaux_off: pinmux-off { 231 groups = "dpaux-io"; 232 function = "off"; 233 }; 234 235 i2c-bus { 236 #address-cells = <1>; 237 #size-cells = <0>; 238 }; 239 }; 240 241 isp@54600000 { 242 compatible = "nvidia,tegra210-isp"; 243 reg = <0x0 0x54600000 0x0 0x00040000>; 244 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 245 status = "disabled"; 246 }; 247 248 isp@54680000 { 249 compatible = "nvidia,tegra210-isp"; 250 reg = <0x0 0x54680000 0x0 0x00040000>; 251 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 252 status = "disabled"; 253 }; 254 255 i2c@546c0000 { 256 compatible = "nvidia,tegra210-i2c-vi"; 257 reg = <0x0 0x546c0000 0x0 0x00040000>; 258 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 259 status = "disabled"; 260 }; 261 }; 262 263 gic: interrupt-controller@50041000 { 264 compatible = "arm,gic-400"; 265 #interrupt-cells = <3>; 266 interrupt-controller; 267 reg = <0x0 0x50041000 0x0 0x1000>, 268 <0x0 0x50042000 0x0 0x2000>, 269 <0x0 0x50044000 0x0 0x2000>, 270 <0x0 0x50046000 0x0 0x2000>; 271 interrupts = <GIC_PPI 9 272 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 273 interrupt-parent = <&gic>; 274 }; 275 276 gpu@57000000 { 277 compatible = "nvidia,gm20b"; 278 reg = <0x0 0x57000000 0x0 0x01000000>, 279 <0x0 0x58000000 0x0 0x01000000>; 280 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 281 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 282 interrupt-names = "stall", "nonstall"; 283 clocks = <&tegra_car TEGRA210_CLK_GPU>, 284 <&tegra_car TEGRA210_CLK_PLL_P_OUT5>, 285 <&tegra_car TEGRA210_CLK_PLL_G_REF>; 286 clock-names = "gpu", "pwr", "ref"; 287 resets = <&tegra_car 184>; 288 reset-names = "gpu"; 289 290 iommus = <&mc TEGRA_SWGROUP_GPU>; 291 292 status = "disabled"; 293 }; 294 295 lic: interrupt-controller@60004000 { 296 compatible = "nvidia,tegra210-ictlr"; 297 reg = <0x0 0x60004000 0x0 0x40>, /* primary controller */ 298 <0x0 0x60004100 0x0 0x40>, /* secondary controller */ 299 <0x0 0x60004200 0x0 0x40>, /* tertiary controller */ 300 <0x0 0x60004300 0x0 0x40>, /* quaternary controller */ 301 <0x0 0x60004400 0x0 0x40>, /* quinary controller */ 302 <0x0 0x60004500 0x0 0x40>; /* senary controller */ 303 interrupt-controller; 304 #interrupt-cells = <3>; 305 interrupt-parent = <&gic>; 306 }; 307 308 timer@60005000 { 309 compatible = "nvidia,tegra210-timer", "nvidia,tegra20-timer"; 310 reg = <0x0 0x60005000 0x0 0x400>; 311 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 312 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 313 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 314 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 315 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 316 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 317 clocks = <&tegra_car TEGRA210_CLK_TIMER>; 318 clock-names = "timer"; 319 }; 320 321 tegra_car: clock@60006000 { 322 compatible = "nvidia,tegra210-car"; 323 reg = <0x0 0x60006000 0x0 0x1000>; 324 #clock-cells = <1>; 325 #reset-cells = <1>; 326 }; 327 328 flow-controller@60007000 { 329 compatible = "nvidia,tegra210-flowctrl"; 330 reg = <0x0 0x60007000 0x0 0x1000>; 331 }; 332 333 gpio: gpio@6000d000 { 334 compatible = "nvidia,tegra210-gpio", "nvidia,tegra30-gpio"; 335 reg = <0x0 0x6000d000 0x0 0x1000>; 336 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 337 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 338 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 339 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 340 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 341 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 342 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 343 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 344 #gpio-cells = <2>; 345 gpio-controller; 346 #interrupt-cells = <2>; 347 interrupt-controller; 348 }; 349 350 apbdma: dma@60020000 { 351 compatible = "nvidia,tegra210-apbdma", "nvidia,tegra148-apbdma"; 352 reg = <0x0 0x60020000 0x0 0x1400>; 353 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 354 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 355 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 356 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 357 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 358 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 359 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 360 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 361 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 362 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 363 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 364 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 365 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 366 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 367 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 368 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 369 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 370 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 371 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 372 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 373 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 374 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 375 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 376 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 377 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 378 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 379 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 380 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 381 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 382 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 383 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 384 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 385 clocks = <&tegra_car TEGRA210_CLK_APBDMA>; 386 clock-names = "dma"; 387 resets = <&tegra_car 34>; 388 reset-names = "dma"; 389 #dma-cells = <1>; 390 }; 391 392 apbmisc@70000800 { 393 compatible = "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc"; 394 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */ 395 <0x0 0x7000e864 0x0 0x04>; /* Strapping options */ 396 }; 397 398 pinmux: pinmux@700008d4 { 399 compatible = "nvidia,tegra210-pinmux"; 400 reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */ 401 <0x0 0x70003000 0x0 0x294>; /* Mux registers */ 402 }; 403 404 /* 405 * There are two serial driver i.e. 8250 based simple serial 406 * driver and APB DMA based serial driver for higher baudrate 407 * and performance. To enable the 8250 based driver, the compatible 408 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable 409 * the APB DMA based serial driver, the compatible is 410 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". 411 */ 412 uarta: serial@70006000 { 413 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 414 reg = <0x0 0x70006000 0x0 0x40>; 415 reg-shift = <2>; 416 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 417 clocks = <&tegra_car TEGRA210_CLK_UARTA>; 418 clock-names = "serial"; 419 resets = <&tegra_car 6>; 420 reset-names = "serial"; 421 dmas = <&apbdma 8>, <&apbdma 8>; 422 dma-names = "rx", "tx"; 423 status = "disabled"; 424 }; 425 426 uartb: serial@70006040 { 427 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 428 reg = <0x0 0x70006040 0x0 0x40>; 429 reg-shift = <2>; 430 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 431 clocks = <&tegra_car TEGRA210_CLK_UARTB>; 432 clock-names = "serial"; 433 resets = <&tegra_car 7>; 434 reset-names = "serial"; 435 dmas = <&apbdma 9>, <&apbdma 9>; 436 dma-names = "rx", "tx"; 437 status = "disabled"; 438 }; 439 440 uartc: serial@70006200 { 441 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 442 reg = <0x0 0x70006200 0x0 0x40>; 443 reg-shift = <2>; 444 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 445 clocks = <&tegra_car TEGRA210_CLK_UARTC>; 446 clock-names = "serial"; 447 resets = <&tegra_car 55>; 448 reset-names = "serial"; 449 dmas = <&apbdma 10>, <&apbdma 10>; 450 dma-names = "rx", "tx"; 451 status = "disabled"; 452 }; 453 454 uartd: serial@70006300 { 455 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 456 reg = <0x0 0x70006300 0x0 0x40>; 457 reg-shift = <2>; 458 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 459 clocks = <&tegra_car TEGRA210_CLK_UARTD>; 460 clock-names = "serial"; 461 resets = <&tegra_car 65>; 462 reset-names = "serial"; 463 dmas = <&apbdma 19>, <&apbdma 19>; 464 dma-names = "rx", "tx"; 465 status = "disabled"; 466 }; 467 468 pwm: pwm@7000a000 { 469 compatible = "nvidia,tegra210-pwm", "nvidia,tegra20-pwm"; 470 reg = <0x0 0x7000a000 0x0 0x100>; 471 #pwm-cells = <2>; 472 clocks = <&tegra_car TEGRA210_CLK_PWM>; 473 clock-names = "pwm"; 474 resets = <&tegra_car 17>; 475 reset-names = "pwm"; 476 status = "disabled"; 477 }; 478 479 i2c@7000c000 { 480 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 481 reg = <0x0 0x7000c000 0x0 0x100>; 482 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 483 #address-cells = <1>; 484 #size-cells = <0>; 485 clocks = <&tegra_car TEGRA210_CLK_I2C1>; 486 clock-names = "div-clk"; 487 resets = <&tegra_car 12>; 488 reset-names = "i2c"; 489 dmas = <&apbdma 21>, <&apbdma 21>; 490 dma-names = "rx", "tx"; 491 status = "disabled"; 492 }; 493 494 i2c@7000c400 { 495 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 496 reg = <0x0 0x7000c400 0x0 0x100>; 497 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 498 #address-cells = <1>; 499 #size-cells = <0>; 500 clocks = <&tegra_car TEGRA210_CLK_I2C2>; 501 clock-names = "div-clk"; 502 resets = <&tegra_car 54>; 503 reset-names = "i2c"; 504 dmas = <&apbdma 22>, <&apbdma 22>; 505 dma-names = "rx", "tx"; 506 status = "disabled"; 507 }; 508 509 i2c@7000c500 { 510 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 511 reg = <0x0 0x7000c500 0x0 0x100>; 512 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 513 #address-cells = <1>; 514 #size-cells = <0>; 515 clocks = <&tegra_car TEGRA210_CLK_I2C3>; 516 clock-names = "div-clk"; 517 resets = <&tegra_car 67>; 518 reset-names = "i2c"; 519 dmas = <&apbdma 23>, <&apbdma 23>; 520 dma-names = "rx", "tx"; 521 status = "disabled"; 522 }; 523 524 i2c@7000c700 { 525 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 526 reg = <0x0 0x7000c700 0x0 0x100>; 527 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 528 #address-cells = <1>; 529 #size-cells = <0>; 530 clocks = <&tegra_car TEGRA210_CLK_I2C4>; 531 clock-names = "div-clk"; 532 resets = <&tegra_car 103>; 533 reset-names = "i2c"; 534 dmas = <&apbdma 26>, <&apbdma 26>; 535 dma-names = "rx", "tx"; 536 pinctrl-0 = <&state_dpaux1_i2c>; 537 pinctrl-1 = <&state_dpaux1_off>; 538 pinctrl-names = "default", "idle"; 539 status = "disabled"; 540 }; 541 542 i2c@7000d000 { 543 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 544 reg = <0x0 0x7000d000 0x0 0x100>; 545 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 546 #address-cells = <1>; 547 #size-cells = <0>; 548 clocks = <&tegra_car TEGRA210_CLK_I2C5>; 549 clock-names = "div-clk"; 550 resets = <&tegra_car 47>; 551 reset-names = "i2c"; 552 dmas = <&apbdma 24>, <&apbdma 24>; 553 dma-names = "rx", "tx"; 554 status = "disabled"; 555 }; 556 557 i2c@7000d100 { 558 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 559 reg = <0x0 0x7000d100 0x0 0x100>; 560 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 561 #address-cells = <1>; 562 #size-cells = <0>; 563 clocks = <&tegra_car TEGRA210_CLK_I2C6>; 564 clock-names = "div-clk"; 565 resets = <&tegra_car 166>; 566 reset-names = "i2c"; 567 dmas = <&apbdma 30>, <&apbdma 30>; 568 dma-names = "rx", "tx"; 569 pinctrl-0 = <&state_dpaux_i2c>; 570 pinctrl-1 = <&state_dpaux_off>; 571 pinctrl-names = "default", "idle"; 572 status = "disabled"; 573 }; 574 575 spi@7000d400 { 576 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 577 reg = <0x0 0x7000d400 0x0 0x200>; 578 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 579 #address-cells = <1>; 580 #size-cells = <0>; 581 clocks = <&tegra_car TEGRA210_CLK_SBC1>; 582 clock-names = "spi"; 583 resets = <&tegra_car 41>; 584 reset-names = "spi"; 585 dmas = <&apbdma 15>, <&apbdma 15>; 586 dma-names = "rx", "tx"; 587 status = "disabled"; 588 }; 589 590 spi@7000d600 { 591 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 592 reg = <0x0 0x7000d600 0x0 0x200>; 593 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 594 #address-cells = <1>; 595 #size-cells = <0>; 596 clocks = <&tegra_car TEGRA210_CLK_SBC2>; 597 clock-names = "spi"; 598 resets = <&tegra_car 44>; 599 reset-names = "spi"; 600 dmas = <&apbdma 16>, <&apbdma 16>; 601 dma-names = "rx", "tx"; 602 status = "disabled"; 603 }; 604 605 spi@7000d800 { 606 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 607 reg = <0x0 0x7000d800 0x0 0x200>; 608 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 609 #address-cells = <1>; 610 #size-cells = <0>; 611 clocks = <&tegra_car TEGRA210_CLK_SBC3>; 612 clock-names = "spi"; 613 resets = <&tegra_car 46>; 614 reset-names = "spi"; 615 dmas = <&apbdma 17>, <&apbdma 17>; 616 dma-names = "rx", "tx"; 617 status = "disabled"; 618 }; 619 620 spi@7000da00 { 621 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 622 reg = <0x0 0x7000da00 0x0 0x200>; 623 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 624 #address-cells = <1>; 625 #size-cells = <0>; 626 clocks = <&tegra_car TEGRA210_CLK_SBC4>; 627 clock-names = "spi"; 628 resets = <&tegra_car 68>; 629 reset-names = "spi"; 630 dmas = <&apbdma 18>, <&apbdma 18>; 631 dma-names = "rx", "tx"; 632 status = "disabled"; 633 }; 634 635 rtc@7000e000 { 636 compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc"; 637 reg = <0x0 0x7000e000 0x0 0x100>; 638 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 639 clocks = <&tegra_car TEGRA210_CLK_RTC>; 640 clock-names = "rtc"; 641 }; 642 643 pmc: pmc@7000e400 { 644 compatible = "nvidia,tegra210-pmc"; 645 reg = <0x0 0x7000e400 0x0 0x400>; 646 clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; 647 clock-names = "pclk", "clk32k_in"; 648 649 powergates { 650 pd_audio: aud { 651 clocks = <&tegra_car TEGRA210_CLK_APE>, 652 <&tegra_car TEGRA210_CLK_APB2APE>; 653 resets = <&tegra_car 198>; 654 #power-domain-cells = <0>; 655 }; 656 657 pd_sor: sor { 658 clocks = <&tegra_car TEGRA210_CLK_SOR0>, 659 <&tegra_car TEGRA210_CLK_SOR1>, 660 <&tegra_car TEGRA210_CLK_CSI>, 661 <&tegra_car TEGRA210_CLK_DSIA>, 662 <&tegra_car TEGRA210_CLK_DSIB>, 663 <&tegra_car TEGRA210_CLK_DPAUX>, 664 <&tegra_car TEGRA210_CLK_DPAUX1>, 665 <&tegra_car TEGRA210_CLK_MIPI_CAL>; 666 resets = <&tegra_car TEGRA210_CLK_SOR0>, 667 <&tegra_car TEGRA210_CLK_SOR1>, 668 <&tegra_car TEGRA210_CLK_CSI>, 669 <&tegra_car TEGRA210_CLK_DSIA>, 670 <&tegra_car TEGRA210_CLK_DSIB>, 671 <&tegra_car TEGRA210_CLK_DPAUX>, 672 <&tegra_car TEGRA210_CLK_DPAUX1>, 673 <&tegra_car TEGRA210_CLK_MIPI_CAL>; 674 #power-domain-cells = <0>; 675 }; 676 677 pd_xusbss: xusba { 678 clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>; 679 resets = <&tegra_car TEGRA210_CLK_XUSB_SS>; 680 #power-domain-cells = <0>; 681 }; 682 683 pd_xusbdev: xusbb { 684 clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>; 685 resets = <&tegra_car 95>; 686 #power-domain-cells = <0>; 687 }; 688 689 pd_xusbhost: xusbc { 690 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>; 691 resets = <&tegra_car TEGRA210_CLK_XUSB_HOST>; 692 #power-domain-cells = <0>; 693 }; 694 }; 695 }; 696 697 fuse@7000f800 { 698 compatible = "nvidia,tegra210-efuse"; 699 reg = <0x0 0x7000f800 0x0 0x400>; 700 clocks = <&tegra_car TEGRA210_CLK_FUSE>; 701 clock-names = "fuse"; 702 resets = <&tegra_car 39>; 703 reset-names = "fuse"; 704 }; 705 706 mc: memory-controller@70019000 { 707 compatible = "nvidia,tegra210-mc"; 708 reg = <0x0 0x70019000 0x0 0x1000>; 709 clocks = <&tegra_car TEGRA210_CLK_MC>; 710 clock-names = "mc"; 711 712 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 713 714 #iommu-cells = <1>; 715 }; 716 717 hda@70030000 { 718 compatible = "nvidia,tegra210-hda", "nvidia,tegra30-hda"; 719 reg = <0x0 0x70030000 0x0 0x10000>; 720 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 721 clocks = <&tegra_car TEGRA210_CLK_HDA>, 722 <&tegra_car TEGRA210_CLK_HDA2HDMI>, 723 <&tegra_car TEGRA210_CLK_HDA2CODEC_2X>; 724 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 725 resets = <&tegra_car 125>, /* hda */ 726 <&tegra_car 128>, /* hda2hdmi */ 727 <&tegra_car 111>; /* hda2codec_2x */ 728 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 729 status = "disabled"; 730 }; 731 732 usb@70090000 { 733 compatible = "nvidia,tegra210-xusb"; 734 reg = <0x0 0x70090000 0x0 0x8000>, 735 <0x0 0x70098000 0x0 0x1000>, 736 <0x0 0x70099000 0x0 0x1000>; 737 reg-names = "hcd", "fpci", "ipfs"; 738 739 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 740 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 741 742 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>, 743 <&tegra_car TEGRA210_CLK_XUSB_HOST_SRC>, 744 <&tegra_car TEGRA210_CLK_XUSB_FALCON_SRC>, 745 <&tegra_car TEGRA210_CLK_XUSB_SS>, 746 <&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>, 747 <&tegra_car TEGRA210_CLK_XUSB_SS_SRC>, 748 <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>, 749 <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>, 750 <&tegra_car TEGRA210_CLK_PLL_U_480M>, 751 <&tegra_car TEGRA210_CLK_CLK_M>, 752 <&tegra_car TEGRA210_CLK_PLL_E>; 753 clock-names = "xusb_host", "xusb_host_src", 754 "xusb_falcon_src", "xusb_ss", 755 "xusb_ss_div2", "xusb_ss_src", 756 "xusb_hs_src", "xusb_fs_src", 757 "pll_u_480m", "clk_m", "pll_e"; 758 resets = <&tegra_car 89>, <&tegra_car 156>, 759 <&tegra_car 143>; 760 reset-names = "xusb_host", "xusb_ss", "xusb_src"; 761 762 nvidia,xusb-padctl = <&padctl>; 763 764 status = "disabled"; 765 }; 766 767 padctl: padctl@7009f000 { 768 compatible = "nvidia,tegra210-xusb-padctl"; 769 reg = <0x0 0x7009f000 0x0 0x1000>; 770 resets = <&tegra_car 142>; 771 reset-names = "padctl"; 772 773 status = "disabled"; 774 775 pads { 776 usb2 { 777 clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>; 778 clock-names = "trk"; 779 status = "disabled"; 780 781 lanes { 782 usb2-0 { 783 status = "disabled"; 784 #phy-cells = <0>; 785 }; 786 787 usb2-1 { 788 status = "disabled"; 789 #phy-cells = <0>; 790 }; 791 792 usb2-2 { 793 status = "disabled"; 794 #phy-cells = <0>; 795 }; 796 797 usb2-3 { 798 status = "disabled"; 799 #phy-cells = <0>; 800 }; 801 }; 802 }; 803 804 hsic { 805 clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>; 806 clock-names = "trk"; 807 status = "disabled"; 808 809 lanes { 810 hsic-0 { 811 status = "disabled"; 812 #phy-cells = <0>; 813 }; 814 815 hsic-1 { 816 status = "disabled"; 817 #phy-cells = <0>; 818 }; 819 }; 820 }; 821 822 pcie { 823 clocks = <&tegra_car TEGRA210_CLK_PLL_E>; 824 clock-names = "pll"; 825 resets = <&tegra_car 205>; 826 reset-names = "phy"; 827 status = "disabled"; 828 829 lanes { 830 pcie-0 { 831 status = "disabled"; 832 #phy-cells = <0>; 833 }; 834 835 pcie-1 { 836 status = "disabled"; 837 #phy-cells = <0>; 838 }; 839 840 pcie-2 { 841 status = "disabled"; 842 #phy-cells = <0>; 843 }; 844 845 pcie-3 { 846 status = "disabled"; 847 #phy-cells = <0>; 848 }; 849 850 pcie-4 { 851 status = "disabled"; 852 #phy-cells = <0>; 853 }; 854 855 pcie-5 { 856 status = "disabled"; 857 #phy-cells = <0>; 858 }; 859 860 pcie-6 { 861 status = "disabled"; 862 #phy-cells = <0>; 863 }; 864 }; 865 }; 866 867 sata { 868 clocks = <&tegra_car TEGRA210_CLK_PLL_E>; 869 clock-names = "pll"; 870 resets = <&tegra_car 204>; 871 reset-names = "phy"; 872 status = "disabled"; 873 874 lanes { 875 sata-0 { 876 status = "disabled"; 877 #phy-cells = <0>; 878 }; 879 }; 880 }; 881 }; 882 883 ports { 884 usb2-0 { 885 status = "disabled"; 886 }; 887 888 usb2-1 { 889 status = "disabled"; 890 }; 891 892 usb2-2 { 893 status = "disabled"; 894 }; 895 896 usb2-3 { 897 status = "disabled"; 898 }; 899 900 hsic-0 { 901 status = "disabled"; 902 }; 903 904 usb3-0 { 905 status = "disabled"; 906 }; 907 908 usb3-1 { 909 status = "disabled"; 910 }; 911 912 usb3-2 { 913 status = "disabled"; 914 }; 915 916 usb3-3 { 917 status = "disabled"; 918 }; 919 }; 920 }; 921 922 sdhci@700b0000 { 923 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; 924 reg = <0x0 0x700b0000 0x0 0x200>; 925 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 926 clocks = <&tegra_car TEGRA210_CLK_SDMMC1>; 927 clock-names = "sdhci"; 928 resets = <&tegra_car 14>; 929 reset-names = "sdhci"; 930 status = "disabled"; 931 }; 932 933 sdhci@700b0200 { 934 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; 935 reg = <0x0 0x700b0200 0x0 0x200>; 936 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 937 clocks = <&tegra_car TEGRA210_CLK_SDMMC2>; 938 clock-names = "sdhci"; 939 resets = <&tegra_car 9>; 940 reset-names = "sdhci"; 941 status = "disabled"; 942 }; 943 944 sdhci@700b0400 { 945 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; 946 reg = <0x0 0x700b0400 0x0 0x200>; 947 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 948 clocks = <&tegra_car TEGRA210_CLK_SDMMC3>; 949 clock-names = "sdhci"; 950 resets = <&tegra_car 69>; 951 reset-names = "sdhci"; 952 status = "disabled"; 953 }; 954 955 sdhci@700b0600 { 956 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; 957 reg = <0x0 0x700b0600 0x0 0x200>; 958 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 959 clocks = <&tegra_car TEGRA210_CLK_SDMMC4>; 960 clock-names = "sdhci"; 961 resets = <&tegra_car 15>; 962 reset-names = "sdhci"; 963 status = "disabled"; 964 }; 965 966 mipi: mipi@700e3000 { 967 compatible = "nvidia,tegra210-mipi"; 968 reg = <0x0 0x700e3000 0x0 0x100>; 969 clocks = <&tegra_car TEGRA210_CLK_MIPI_CAL>; 970 clock-names = "mipi-cal"; 971 power-domains = <&pd_sor>; 972 #nvidia,mipi-calibrate-cells = <1>; 973 }; 974 975 aconnect@702c0000 { 976 compatible = "nvidia,tegra210-aconnect"; 977 clocks = <&tegra_car TEGRA210_CLK_APE>, 978 <&tegra_car TEGRA210_CLK_APB2APE>; 979 clock-names = "ape", "apb2ape"; 980 power-domains = <&pd_audio>; 981 #address-cells = <1>; 982 #size-cells = <1>; 983 ranges = <0x702c0000 0x0 0x702c0000 0x00040000>; 984 status = "disabled"; 985 986 adma: dma@702e2000 { 987 compatible = "nvidia,tegra210-adma"; 988 reg = <0x702e2000 0x2000>; 989 interrupt-parent = <&agic>; 990 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 991 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 992 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 993 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 994 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 995 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 996 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 997 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 998 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 999 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 1000 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 1001 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 1002 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 1003 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 1004 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 1005 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 1006 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 1007 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 1008 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 1009 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 1010 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 1011 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1012 #dma-cells = <1>; 1013 clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>; 1014 clock-names = "d_audio"; 1015 status = "disabled"; 1016 }; 1017 1018 agic: agic@702f9000 { 1019 compatible = "nvidia,tegra210-agic"; 1020 #interrupt-cells = <3>; 1021 interrupt-controller; 1022 reg = <0x702f9000 0x2000>, 1023 <0x702fa000 0x2000>; 1024 interrupts = <GIC_SPI 102 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1025 clocks = <&tegra_car TEGRA210_CLK_APE>; 1026 clock-names = "clk"; 1027 status = "disabled"; 1028 }; 1029 }; 1030 1031 spi@70410000 { 1032 compatible = "nvidia,tegra210-qspi"; 1033 reg = <0x0 0x70410000 0x0 0x1000>; 1034 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1035 #address-cells = <1>; 1036 #size-cells = <0>; 1037 clocks = <&tegra_car TEGRA210_CLK_QSPI>; 1038 clock-names = "qspi"; 1039 resets = <&tegra_car 211>; 1040 reset-names = "qspi"; 1041 dmas = <&apbdma 5>, <&apbdma 5>; 1042 dma-names = "rx", "tx"; 1043 status = "disabled"; 1044 }; 1045 1046 usb@7d000000 { 1047 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 1048 reg = <0x0 0x7d000000 0x0 0x4000>; 1049 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1050 phy_type = "utmi"; 1051 clocks = <&tegra_car TEGRA210_CLK_USBD>; 1052 clock-names = "usb"; 1053 resets = <&tegra_car 22>; 1054 reset-names = "usb"; 1055 nvidia,phy = <&phy1>; 1056 status = "disabled"; 1057 }; 1058 1059 phy1: usb-phy@7d000000 { 1060 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; 1061 reg = <0x0 0x7d000000 0x0 0x4000>, 1062 <0x0 0x7d000000 0x0 0x4000>; 1063 phy_type = "utmi"; 1064 clocks = <&tegra_car TEGRA210_CLK_USBD>, 1065 <&tegra_car TEGRA210_CLK_PLL_U>, 1066 <&tegra_car TEGRA210_CLK_USBD>; 1067 clock-names = "reg", "pll_u", "utmi-pads"; 1068 resets = <&tegra_car 22>, <&tegra_car 22>; 1069 reset-names = "usb", "utmi-pads"; 1070 nvidia,hssync-start-delay = <0>; 1071 nvidia,idle-wait-delay = <17>; 1072 nvidia,elastic-limit = <16>; 1073 nvidia,term-range-adj = <6>; 1074 nvidia,xcvr-setup = <9>; 1075 nvidia,xcvr-lsfslew = <0>; 1076 nvidia,xcvr-lsrslew = <3>; 1077 nvidia,hssquelch-level = <2>; 1078 nvidia,hsdiscon-level = <5>; 1079 nvidia,xcvr-hsslew = <12>; 1080 nvidia,has-utmi-pad-registers; 1081 status = "disabled"; 1082 }; 1083 1084 usb@7d004000 { 1085 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 1086 reg = <0x0 0x7d004000 0x0 0x4000>; 1087 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1088 phy_type = "utmi"; 1089 clocks = <&tegra_car TEGRA210_CLK_USB2>; 1090 clock-names = "usb"; 1091 resets = <&tegra_car 58>; 1092 reset-names = "usb"; 1093 nvidia,phy = <&phy2>; 1094 status = "disabled"; 1095 }; 1096 1097 phy2: usb-phy@7d004000 { 1098 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; 1099 reg = <0x0 0x7d004000 0x0 0x4000>, 1100 <0x0 0x7d000000 0x0 0x4000>; 1101 phy_type = "utmi"; 1102 clocks = <&tegra_car TEGRA210_CLK_USB2>, 1103 <&tegra_car TEGRA210_CLK_PLL_U>, 1104 <&tegra_car TEGRA210_CLK_USBD>; 1105 clock-names = "reg", "pll_u", "utmi-pads"; 1106 resets = <&tegra_car 58>, <&tegra_car 22>; 1107 reset-names = "usb", "utmi-pads"; 1108 nvidia,hssync-start-delay = <0>; 1109 nvidia,idle-wait-delay = <17>; 1110 nvidia,elastic-limit = <16>; 1111 nvidia,term-range-adj = <6>; 1112 nvidia,xcvr-setup = <9>; 1113 nvidia,xcvr-lsfslew = <0>; 1114 nvidia,xcvr-lsrslew = <3>; 1115 nvidia,hssquelch-level = <2>; 1116 nvidia,hsdiscon-level = <5>; 1117 nvidia,xcvr-hsslew = <12>; 1118 status = "disabled"; 1119 }; 1120 1121 cpus { 1122 #address-cells = <1>; 1123 #size-cells = <0>; 1124 1125 cpu@0 { 1126 device_type = "cpu"; 1127 compatible = "arm,cortex-a57"; 1128 reg = <0>; 1129 }; 1130 1131 cpu@1 { 1132 device_type = "cpu"; 1133 compatible = "arm,cortex-a57"; 1134 reg = <1>; 1135 }; 1136 1137 cpu@2 { 1138 device_type = "cpu"; 1139 compatible = "arm,cortex-a57"; 1140 reg = <2>; 1141 }; 1142 1143 cpu@3 { 1144 device_type = "cpu"; 1145 compatible = "arm,cortex-a57"; 1146 reg = <3>; 1147 }; 1148 }; 1149 1150 timer { 1151 compatible = "arm,armv8-timer"; 1152 interrupts = <GIC_PPI 13 1153 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1154 <GIC_PPI 14 1155 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1156 <GIC_PPI 11 1157 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1158 <GIC_PPI 10 1159 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1160 interrupt-parent = <&gic>; 1161 }; 1162}; 1163