1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra210-car.h> 3#include <dt-bindings/gpio/tegra-gpio.h> 4#include <dt-bindings/memory/tegra210-mc.h> 5#include <dt-bindings/pinctrl/pinctrl-tegra.h> 6#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 7#include <dt-bindings/reset/tegra210-car.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/thermal/tegra124-soctherm.h> 10#include <dt-bindings/soc/tegra-pmc.h> 11 12/ { 13 compatible = "nvidia,tegra210"; 14 interrupt-parent = <&lic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 pcie@1003000 { 19 compatible = "nvidia,tegra210-pcie"; 20 device_type = "pci"; 21 reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */ 22 <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */ 23 <0x0 0x02000000 0x0 0x10000000>; /* configuration space */ 24 reg-names = "pads", "afi", "cs"; 25 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 26 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 27 interrupt-names = "intr", "msi"; 28 29 #interrupt-cells = <1>; 30 interrupt-map-mask = <0 0 0 0>; 31 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 32 33 bus-range = <0x00 0xff>; 34 #address-cells = <3>; 35 #size-cells = <2>; 36 37 ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */ 38 <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */ 39 <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */ 40 <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */ 41 <0x42000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ 42 43 clocks = <&tegra_car TEGRA210_CLK_PCIE>, 44 <&tegra_car TEGRA210_CLK_AFI>, 45 <&tegra_car TEGRA210_CLK_PLL_E>, 46 <&tegra_car TEGRA210_CLK_CML0>; 47 clock-names = "pex", "afi", "pll_e", "cml"; 48 resets = <&tegra_car 70>, 49 <&tegra_car 72>, 50 <&tegra_car 74>; 51 reset-names = "pex", "afi", "pcie_x"; 52 53 pinctrl-names = "default", "idle"; 54 pinctrl-0 = <&pex_dpd_disable>; 55 pinctrl-1 = <&pex_dpd_enable>; 56 57 status = "disabled"; 58 59 pci@1,0 { 60 device_type = "pci"; 61 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>; 62 reg = <0x000800 0 0 0 0>; 63 bus-range = <0x00 0xff>; 64 status = "disabled"; 65 66 #address-cells = <3>; 67 #size-cells = <2>; 68 ranges; 69 70 nvidia,num-lanes = <4>; 71 }; 72 73 pci@2,0 { 74 device_type = "pci"; 75 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>; 76 reg = <0x001000 0 0 0 0>; 77 bus-range = <0x00 0xff>; 78 status = "disabled"; 79 80 #address-cells = <3>; 81 #size-cells = <2>; 82 ranges; 83 84 nvidia,num-lanes = <1>; 85 }; 86 }; 87 88 host1x@50000000 { 89 compatible = "nvidia,tegra210-host1x"; 90 reg = <0x0 0x50000000 0x0 0x00034000>; 91 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 92 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ 93 interrupt-names = "syncpt", "host1x"; 94 clocks = <&tegra_car TEGRA210_CLK_HOST1X>; 95 clock-names = "host1x"; 96 resets = <&tegra_car 28>, <&mc TEGRA210_MC_RESET_HC>; 97 reset-names = "host1x", "mc"; 98 99 #address-cells = <2>; 100 #size-cells = <2>; 101 102 ranges = <0x0 0x54000000 0x0 0x54000000 0x0 0x01000000>; 103 104 iommus = <&mc TEGRA_SWGROUP_HC>; 105 106 dpaux1: dpaux@54040000 { 107 compatible = "nvidia,tegra210-dpaux"; 108 reg = <0x0 0x54040000 0x0 0x00040000>; 109 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 110 clocks = <&tegra_car TEGRA210_CLK_DPAUX1>, 111 <&tegra_car TEGRA210_CLK_PLL_DP>; 112 clock-names = "dpaux", "parent"; 113 resets = <&tegra_car 207>; 114 reset-names = "dpaux"; 115 power-domains = <&pd_sor>; 116 status = "disabled"; 117 118 state_dpaux1_aux: pinmux-aux { 119 groups = "dpaux-io"; 120 function = "aux"; 121 }; 122 123 state_dpaux1_i2c: pinmux-i2c { 124 groups = "dpaux-io"; 125 function = "i2c"; 126 }; 127 128 state_dpaux1_off: pinmux-off { 129 groups = "dpaux-io"; 130 function = "off"; 131 }; 132 133 i2c-bus { 134 #address-cells = <1>; 135 #size-cells = <0>; 136 }; 137 }; 138 139 vi@54080000 { 140 compatible = "nvidia,tegra210-vi"; 141 reg = <0x0 0x54080000 0x0 0x700>; 142 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 143 status = "disabled"; 144 assigned-clocks = <&tegra_car TEGRA210_CLK_VI>; 145 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 146 147 clocks = <&tegra_car TEGRA210_CLK_VI>; 148 power-domains = <&pd_venc>; 149 150 #address-cells = <1>; 151 #size-cells = <1>; 152 153 ranges = <0x0 0x0 0x54080000 0x2000>; 154 155 csi@838 { 156 compatible = "nvidia,tegra210-csi"; 157 reg = <0x838 0x1300>; 158 status = "disabled"; 159 assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>, 160 <&tegra_car TEGRA210_CLK_CILCD>, 161 <&tegra_car TEGRA210_CLK_CILE>, 162 <&tegra_car TEGRA210_CLK_CSI_TPG>; 163 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>, 164 <&tegra_car TEGRA210_CLK_PLL_P>, 165 <&tegra_car TEGRA210_CLK_PLL_P>; 166 assigned-clock-rates = <102000000>, 167 <102000000>, 168 <102000000>, 169 <972000000>; 170 171 clocks = <&tegra_car TEGRA210_CLK_CSI>, 172 <&tegra_car TEGRA210_CLK_CILAB>, 173 <&tegra_car TEGRA210_CLK_CILCD>, 174 <&tegra_car TEGRA210_CLK_CILE>, 175 <&tegra_car TEGRA210_CLK_CSI_TPG>; 176 clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg"; 177 power-domains = <&pd_sor>; 178 }; 179 }; 180 181 tsec@54100000 { 182 compatible = "nvidia,tegra210-tsec"; 183 reg = <0x0 0x54100000 0x0 0x00040000>; 184 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 185 clocks = <&tegra_car TEGRA210_CLK_TSEC>; 186 clock-names = "tsec"; 187 resets = <&tegra_car 83>; 188 reset-names = "tsec"; 189 status = "disabled"; 190 }; 191 192 dc@54200000 { 193 compatible = "nvidia,tegra210-dc"; 194 reg = <0x0 0x54200000 0x0 0x00040000>; 195 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 196 clocks = <&tegra_car TEGRA210_CLK_DISP1>; 197 clock-names = "dc"; 198 resets = <&tegra_car 27>; 199 reset-names = "dc"; 200 201 iommus = <&mc TEGRA_SWGROUP_DC>; 202 203 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 204 nvidia,head = <0>; 205 }; 206 207 dc@54240000 { 208 compatible = "nvidia,tegra210-dc"; 209 reg = <0x0 0x54240000 0x0 0x00040000>; 210 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 211 clocks = <&tegra_car TEGRA210_CLK_DISP2>; 212 clock-names = "dc"; 213 resets = <&tegra_car 26>; 214 reset-names = "dc"; 215 216 iommus = <&mc TEGRA_SWGROUP_DCB>; 217 218 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 219 nvidia,head = <1>; 220 }; 221 222 dsia: dsi@54300000 { 223 compatible = "nvidia,tegra210-dsi"; 224 reg = <0x0 0x54300000 0x0 0x00040000>; 225 clocks = <&tegra_car TEGRA210_CLK_DSIA>, 226 <&tegra_car TEGRA210_CLK_DSIALP>, 227 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; 228 clock-names = "dsi", "lp", "parent"; 229 resets = <&tegra_car 48>; 230 reset-names = "dsi"; 231 power-domains = <&pd_sor>; 232 nvidia,mipi-calibrate = <&mipi 0x0c0>; /* DSIA & DSIB pads */ 233 234 status = "disabled"; 235 236 #address-cells = <1>; 237 #size-cells = <0>; 238 }; 239 240 vic@54340000 { 241 compatible = "nvidia,tegra210-vic"; 242 reg = <0x0 0x54340000 0x0 0x00040000>; 243 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 244 clocks = <&tegra_car TEGRA210_CLK_VIC03>; 245 clock-names = "vic"; 246 resets = <&tegra_car 178>; 247 reset-names = "vic"; 248 249 iommus = <&mc TEGRA_SWGROUP_VIC>; 250 power-domains = <&pd_vic>; 251 }; 252 253 nvjpg@54380000 { 254 compatible = "nvidia,tegra210-nvjpg"; 255 reg = <0x0 0x54380000 0x0 0x00040000>; 256 status = "disabled"; 257 }; 258 259 dsib: dsi@54400000 { 260 compatible = "nvidia,tegra210-dsi"; 261 reg = <0x0 0x54400000 0x0 0x00040000>; 262 clocks = <&tegra_car TEGRA210_CLK_DSIB>, 263 <&tegra_car TEGRA210_CLK_DSIBLP>, 264 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; 265 clock-names = "dsi", "lp", "parent"; 266 resets = <&tegra_car 82>; 267 reset-names = "dsi"; 268 power-domains = <&pd_sor>; 269 nvidia,mipi-calibrate = <&mipi 0x300>; /* DSIC & DSID pads */ 270 271 status = "disabled"; 272 273 #address-cells = <1>; 274 #size-cells = <0>; 275 }; 276 277 nvdec@54480000 { 278 compatible = "nvidia,tegra210-nvdec"; 279 reg = <0x0 0x54480000 0x0 0x00040000>; 280 status = "disabled"; 281 }; 282 283 nvenc@544c0000 { 284 compatible = "nvidia,tegra210-nvenc"; 285 reg = <0x0 0x544c0000 0x0 0x00040000>; 286 status = "disabled"; 287 }; 288 289 tsec@54500000 { 290 compatible = "nvidia,tegra210-tsec"; 291 reg = <0x0 0x54500000 0x0 0x00040000>; 292 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 293 clocks = <&tegra_car TEGRA210_CLK_TSECB>; 294 clock-names = "tsec"; 295 resets = <&tegra_car 206>; 296 reset-names = "tsec"; 297 status = "disabled"; 298 }; 299 300 sor0: sor@54540000 { 301 compatible = "nvidia,tegra210-sor"; 302 reg = <0x0 0x54540000 0x0 0x00040000>; 303 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 304 clocks = <&tegra_car TEGRA210_CLK_SOR0>, 305 <&tegra_car TEGRA210_CLK_SOR0_OUT>, 306 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>, 307 <&tegra_car TEGRA210_CLK_PLL_DP>, 308 <&tegra_car TEGRA210_CLK_SOR_SAFE>; 309 clock-names = "sor", "out", "parent", "dp", "safe"; 310 resets = <&tegra_car 182>; 311 reset-names = "sor"; 312 pinctrl-0 = <&state_dpaux_aux>; 313 pinctrl-1 = <&state_dpaux_i2c>; 314 pinctrl-2 = <&state_dpaux_off>; 315 pinctrl-names = "aux", "i2c", "off"; 316 power-domains = <&pd_sor>; 317 status = "disabled"; 318 }; 319 320 sor1: sor@54580000 { 321 compatible = "nvidia,tegra210-sor1"; 322 reg = <0x0 0x54580000 0x0 0x00040000>; 323 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 324 clocks = <&tegra_car TEGRA210_CLK_SOR1>, 325 <&tegra_car TEGRA210_CLK_SOR1_OUT>, 326 <&tegra_car TEGRA210_CLK_PLL_D2_OUT0>, 327 <&tegra_car TEGRA210_CLK_PLL_DP>, 328 <&tegra_car TEGRA210_CLK_SOR_SAFE>; 329 clock-names = "sor", "out", "parent", "dp", "safe"; 330 resets = <&tegra_car 183>; 331 reset-names = "sor"; 332 pinctrl-0 = <&state_dpaux1_aux>; 333 pinctrl-1 = <&state_dpaux1_i2c>; 334 pinctrl-2 = <&state_dpaux1_off>; 335 pinctrl-names = "aux", "i2c", "off"; 336 power-domains = <&pd_sor>; 337 status = "disabled"; 338 }; 339 340 dpaux: dpaux@545c0000 { 341 compatible = "nvidia,tegra210-dpaux"; 342 reg = <0x0 0x545c0000 0x0 0x00040000>; 343 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 344 clocks = <&tegra_car TEGRA210_CLK_DPAUX>, 345 <&tegra_car TEGRA210_CLK_PLL_DP>; 346 clock-names = "dpaux", "parent"; 347 resets = <&tegra_car 181>; 348 reset-names = "dpaux"; 349 power-domains = <&pd_sor>; 350 status = "disabled"; 351 352 state_dpaux_aux: pinmux-aux { 353 groups = "dpaux-io"; 354 function = "aux"; 355 }; 356 357 state_dpaux_i2c: pinmux-i2c { 358 groups = "dpaux-io"; 359 function = "i2c"; 360 }; 361 362 state_dpaux_off: pinmux-off { 363 groups = "dpaux-io"; 364 function = "off"; 365 }; 366 367 i2c-bus { 368 #address-cells = <1>; 369 #size-cells = <0>; 370 }; 371 }; 372 373 isp@54600000 { 374 compatible = "nvidia,tegra210-isp"; 375 reg = <0x0 0x54600000 0x0 0x00040000>; 376 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 377 clocks = <&tegra_car TEGRA210_CLK_ISPA>; 378 resets = <&tegra_car 23>; 379 reset-names = "isp"; 380 status = "disabled"; 381 }; 382 383 isp@54680000 { 384 compatible = "nvidia,tegra210-isp"; 385 reg = <0x0 0x54680000 0x0 0x00040000>; 386 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 387 clocks = <&tegra_car TEGRA210_CLK_ISPB>; 388 resets = <&tegra_car 3>; 389 reset-names = "isp"; 390 status = "disabled"; 391 }; 392 393 i2c@546c0000 { 394 compatible = "nvidia,tegra210-i2c-vi"; 395 reg = <0x0 0x546c0000 0x0 0x00040000>; 396 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 397 clocks = <&tegra_car TEGRA210_CLK_VI_I2C>, 398 <&tegra_car TEGRA210_CLK_I2CSLOW>; 399 clock-names = "div-clk", "slow"; 400 resets = <&tegra_car 208>; 401 reset-names = "i2c"; 402 power-domains = <&pd_venc>; 403 status = "disabled"; 404 405 #address-cells = <1>; 406 #size-cells = <0>; 407 }; 408 }; 409 410 gic: interrupt-controller@50041000 { 411 compatible = "arm,gic-400"; 412 #interrupt-cells = <3>; 413 interrupt-controller; 414 reg = <0x0 0x50041000 0x0 0x1000>, 415 <0x0 0x50042000 0x0 0x2000>, 416 <0x0 0x50044000 0x0 0x2000>, 417 <0x0 0x50046000 0x0 0x2000>; 418 interrupts = <GIC_PPI 9 419 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 420 interrupt-parent = <&gic>; 421 }; 422 423 gpu@57000000 { 424 compatible = "nvidia,gm20b"; 425 reg = <0x0 0x57000000 0x0 0x01000000>, 426 <0x0 0x58000000 0x0 0x01000000>; 427 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 428 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 429 interrupt-names = "stall", "nonstall"; 430 clocks = <&tegra_car TEGRA210_CLK_GPU>, 431 <&tegra_car TEGRA210_CLK_PLL_P_OUT5>, 432 <&tegra_car TEGRA210_CLK_PLL_G_REF>; 433 clock-names = "gpu", "pwr", "ref"; 434 resets = <&tegra_car 184>; 435 reset-names = "gpu"; 436 437 iommus = <&mc TEGRA_SWGROUP_GPU>; 438 439 status = "disabled"; 440 }; 441 442 lic: interrupt-controller@60004000 { 443 compatible = "nvidia,tegra210-ictlr"; 444 reg = <0x0 0x60004000 0x0 0x40>, /* primary controller */ 445 <0x0 0x60004100 0x0 0x40>, /* secondary controller */ 446 <0x0 0x60004200 0x0 0x40>, /* tertiary controller */ 447 <0x0 0x60004300 0x0 0x40>, /* quaternary controller */ 448 <0x0 0x60004400 0x0 0x40>, /* quinary controller */ 449 <0x0 0x60004500 0x0 0x40>; /* senary controller */ 450 interrupt-controller; 451 #interrupt-cells = <3>; 452 interrupt-parent = <&gic>; 453 }; 454 455 timer@60005000 { 456 compatible = "nvidia,tegra210-timer"; 457 reg = <0x0 0x60005000 0x0 0x400>; 458 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 459 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 460 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 461 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 462 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 463 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 464 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 465 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 466 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 467 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 468 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 469 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 470 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, 471 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 472 clocks = <&tegra_car TEGRA210_CLK_TIMER>; 473 clock-names = "timer"; 474 }; 475 476 tegra_car: clock@60006000 { 477 compatible = "nvidia,tegra210-car"; 478 reg = <0x0 0x60006000 0x0 0x1000>; 479 #clock-cells = <1>; 480 #reset-cells = <1>; 481 }; 482 483 flow-controller@60007000 { 484 compatible = "nvidia,tegra210-flowctrl"; 485 reg = <0x0 0x60007000 0x0 0x1000>; 486 }; 487 488 gpio: gpio@6000d000 { 489 compatible = "nvidia,tegra210-gpio", "nvidia,tegra30-gpio"; 490 reg = <0x0 0x6000d000 0x0 0x1000>; 491 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 492 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 493 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 494 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 495 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 496 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 497 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 498 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 499 #gpio-cells = <2>; 500 gpio-controller; 501 #interrupt-cells = <2>; 502 interrupt-controller; 503 }; 504 505 apbdma: dma@60020000 { 506 compatible = "nvidia,tegra210-apbdma", "nvidia,tegra148-apbdma"; 507 reg = <0x0 0x60020000 0x0 0x1400>; 508 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 509 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 510 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 511 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 512 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 513 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 514 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 515 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 516 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 517 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 518 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 519 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 520 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 521 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 522 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 523 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 524 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 525 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 526 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 527 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 528 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 529 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 530 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 531 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 532 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 533 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 534 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 535 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 536 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 537 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 538 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 539 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 540 clocks = <&tegra_car TEGRA210_CLK_APBDMA>; 541 clock-names = "dma"; 542 resets = <&tegra_car 34>; 543 reset-names = "dma"; 544 #dma-cells = <1>; 545 }; 546 547 apbmisc@70000800 { 548 compatible = "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc"; 549 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */ 550 <0x0 0x70000008 0x0 0x04>; /* Strapping options */ 551 }; 552 553 pinmux: pinmux@700008d4 { 554 compatible = "nvidia,tegra210-pinmux"; 555 reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */ 556 <0x0 0x70003000 0x0 0x294>; /* Mux registers */ 557 sdmmc1_3v3_drv: sdmmc1-3v3-drv { 558 sdmmc1 { 559 nvidia,pins = "drive_sdmmc1"; 560 nvidia,pull-down-strength = <0x8>; 561 nvidia,pull-up-strength = <0x8>; 562 }; 563 }; 564 sdmmc1_1v8_drv: sdmmc1-1v8-drv { 565 sdmmc1 { 566 nvidia,pins = "drive_sdmmc1"; 567 nvidia,pull-down-strength = <0x4>; 568 nvidia,pull-up-strength = <0x3>; 569 }; 570 }; 571 sdmmc2_1v8_drv: sdmmc2-1v8-drv { 572 sdmmc2 { 573 nvidia,pins = "drive_sdmmc2"; 574 nvidia,pull-down-strength = <0x10>; 575 nvidia,pull-up-strength = <0x10>; 576 }; 577 }; 578 sdmmc3_3v3_drv: sdmmc3-3v3-drv { 579 sdmmc3 { 580 nvidia,pins = "drive_sdmmc3"; 581 nvidia,pull-down-strength = <0x8>; 582 nvidia,pull-up-strength = <0x8>; 583 }; 584 }; 585 sdmmc3_1v8_drv: sdmmc3-1v8-drv { 586 sdmmc3 { 587 nvidia,pins = "drive_sdmmc3"; 588 nvidia,pull-down-strength = <0x4>; 589 nvidia,pull-up-strength = <0x3>; 590 }; 591 }; 592 sdmmc4_1v8_drv: sdmmc4-1v8-drv { 593 sdmmc4 { 594 nvidia,pins = "drive_sdmmc4"; 595 nvidia,pull-down-strength = <0x10>; 596 nvidia,pull-up-strength = <0x10>; 597 }; 598 }; 599 }; 600 601 /* 602 * There are two serial driver i.e. 8250 based simple serial 603 * driver and APB DMA based serial driver for higher baudrate 604 * and performance. To enable the 8250 based driver, the compatible 605 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable 606 * the APB DMA based serial driver, the compatible is 607 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". 608 */ 609 uarta: serial@70006000 { 610 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 611 reg = <0x0 0x70006000 0x0 0x40>; 612 reg-shift = <2>; 613 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 614 clocks = <&tegra_car TEGRA210_CLK_UARTA>; 615 clock-names = "serial"; 616 resets = <&tegra_car 6>; 617 reset-names = "serial"; 618 dmas = <&apbdma 8>, <&apbdma 8>; 619 dma-names = "rx", "tx"; 620 status = "disabled"; 621 }; 622 623 uartb: serial@70006040 { 624 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 625 reg = <0x0 0x70006040 0x0 0x40>; 626 reg-shift = <2>; 627 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 628 clocks = <&tegra_car TEGRA210_CLK_UARTB>; 629 clock-names = "serial"; 630 resets = <&tegra_car 7>; 631 reset-names = "serial"; 632 dmas = <&apbdma 9>, <&apbdma 9>; 633 dma-names = "rx", "tx"; 634 status = "disabled"; 635 }; 636 637 uartc: serial@70006200 { 638 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 639 reg = <0x0 0x70006200 0x0 0x40>; 640 reg-shift = <2>; 641 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 642 clocks = <&tegra_car TEGRA210_CLK_UARTC>; 643 clock-names = "serial"; 644 resets = <&tegra_car 55>; 645 reset-names = "serial"; 646 dmas = <&apbdma 10>, <&apbdma 10>; 647 dma-names = "rx", "tx"; 648 status = "disabled"; 649 }; 650 651 uartd: serial@70006300 { 652 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 653 reg = <0x0 0x70006300 0x0 0x40>; 654 reg-shift = <2>; 655 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 656 clocks = <&tegra_car TEGRA210_CLK_UARTD>; 657 clock-names = "serial"; 658 resets = <&tegra_car 65>; 659 reset-names = "serial"; 660 dmas = <&apbdma 19>, <&apbdma 19>; 661 dma-names = "rx", "tx"; 662 status = "disabled"; 663 }; 664 665 pwm: pwm@7000a000 { 666 compatible = "nvidia,tegra210-pwm", "nvidia,tegra20-pwm"; 667 reg = <0x0 0x7000a000 0x0 0x100>; 668 #pwm-cells = <2>; 669 clocks = <&tegra_car TEGRA210_CLK_PWM>; 670 resets = <&tegra_car 17>; 671 reset-names = "pwm"; 672 status = "disabled"; 673 }; 674 675 i2c@7000c000 { 676 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 677 reg = <0x0 0x7000c000 0x0 0x100>; 678 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 679 #address-cells = <1>; 680 #size-cells = <0>; 681 clocks = <&tegra_car TEGRA210_CLK_I2C1>; 682 clock-names = "div-clk"; 683 resets = <&tegra_car 12>; 684 reset-names = "i2c"; 685 dmas = <&apbdma 21>, <&apbdma 21>; 686 dma-names = "rx", "tx"; 687 status = "disabled"; 688 }; 689 690 i2c@7000c400 { 691 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 692 reg = <0x0 0x7000c400 0x0 0x100>; 693 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 694 #address-cells = <1>; 695 #size-cells = <0>; 696 clocks = <&tegra_car TEGRA210_CLK_I2C2>; 697 clock-names = "div-clk"; 698 resets = <&tegra_car 54>; 699 reset-names = "i2c"; 700 dmas = <&apbdma 22>, <&apbdma 22>; 701 dma-names = "rx", "tx"; 702 status = "disabled"; 703 }; 704 705 i2c@7000c500 { 706 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 707 reg = <0x0 0x7000c500 0x0 0x100>; 708 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 709 #address-cells = <1>; 710 #size-cells = <0>; 711 clocks = <&tegra_car TEGRA210_CLK_I2C3>; 712 clock-names = "div-clk"; 713 resets = <&tegra_car 67>; 714 reset-names = "i2c"; 715 dmas = <&apbdma 23>, <&apbdma 23>; 716 dma-names = "rx", "tx"; 717 status = "disabled"; 718 }; 719 720 i2c@7000c700 { 721 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 722 reg = <0x0 0x7000c700 0x0 0x100>; 723 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 724 #address-cells = <1>; 725 #size-cells = <0>; 726 clocks = <&tegra_car TEGRA210_CLK_I2C4>; 727 clock-names = "div-clk"; 728 resets = <&tegra_car 103>; 729 reset-names = "i2c"; 730 dmas = <&apbdma 26>, <&apbdma 26>; 731 dma-names = "rx", "tx"; 732 pinctrl-0 = <&state_dpaux1_i2c>; 733 pinctrl-1 = <&state_dpaux1_off>; 734 pinctrl-names = "default", "idle"; 735 status = "disabled"; 736 }; 737 738 i2c@7000d000 { 739 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 740 reg = <0x0 0x7000d000 0x0 0x100>; 741 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 742 #address-cells = <1>; 743 #size-cells = <0>; 744 clocks = <&tegra_car TEGRA210_CLK_I2C5>; 745 clock-names = "div-clk"; 746 resets = <&tegra_car 47>; 747 reset-names = "i2c"; 748 dmas = <&apbdma 24>, <&apbdma 24>; 749 dma-names = "rx", "tx"; 750 status = "disabled"; 751 }; 752 753 i2c@7000d100 { 754 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 755 reg = <0x0 0x7000d100 0x0 0x100>; 756 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 757 #address-cells = <1>; 758 #size-cells = <0>; 759 clocks = <&tegra_car TEGRA210_CLK_I2C6>; 760 clock-names = "div-clk"; 761 resets = <&tegra_car 166>; 762 reset-names = "i2c"; 763 dmas = <&apbdma 30>, <&apbdma 30>; 764 dma-names = "rx", "tx"; 765 pinctrl-0 = <&state_dpaux_i2c>; 766 pinctrl-1 = <&state_dpaux_off>; 767 pinctrl-names = "default", "idle"; 768 status = "disabled"; 769 }; 770 771 spi@7000d400 { 772 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 773 reg = <0x0 0x7000d400 0x0 0x200>; 774 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 775 #address-cells = <1>; 776 #size-cells = <0>; 777 clocks = <&tegra_car TEGRA210_CLK_SBC1>; 778 clock-names = "spi"; 779 resets = <&tegra_car 41>; 780 reset-names = "spi"; 781 dmas = <&apbdma 15>, <&apbdma 15>; 782 dma-names = "rx", "tx"; 783 status = "disabled"; 784 }; 785 786 spi@7000d600 { 787 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 788 reg = <0x0 0x7000d600 0x0 0x200>; 789 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 790 #address-cells = <1>; 791 #size-cells = <0>; 792 clocks = <&tegra_car TEGRA210_CLK_SBC2>; 793 clock-names = "spi"; 794 resets = <&tegra_car 44>; 795 reset-names = "spi"; 796 dmas = <&apbdma 16>, <&apbdma 16>; 797 dma-names = "rx", "tx"; 798 status = "disabled"; 799 }; 800 801 spi@7000d800 { 802 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 803 reg = <0x0 0x7000d800 0x0 0x200>; 804 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 805 #address-cells = <1>; 806 #size-cells = <0>; 807 clocks = <&tegra_car TEGRA210_CLK_SBC3>; 808 clock-names = "spi"; 809 resets = <&tegra_car 46>; 810 reset-names = "spi"; 811 dmas = <&apbdma 17>, <&apbdma 17>; 812 dma-names = "rx", "tx"; 813 status = "disabled"; 814 }; 815 816 spi@7000da00 { 817 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 818 reg = <0x0 0x7000da00 0x0 0x200>; 819 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 820 #address-cells = <1>; 821 #size-cells = <0>; 822 clocks = <&tegra_car TEGRA210_CLK_SBC4>; 823 clock-names = "spi"; 824 resets = <&tegra_car 68>; 825 reset-names = "spi"; 826 dmas = <&apbdma 18>, <&apbdma 18>; 827 dma-names = "rx", "tx"; 828 status = "disabled"; 829 }; 830 831 rtc@7000e000 { 832 compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc"; 833 reg = <0x0 0x7000e000 0x0 0x100>; 834 interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; 835 interrupt-parent = <&tegra_pmc>; 836 clocks = <&tegra_car TEGRA210_CLK_RTC>; 837 clock-names = "rtc"; 838 }; 839 840 tegra_pmc: pmc@7000e400 { 841 compatible = "nvidia,tegra210-pmc"; 842 reg = <0x0 0x7000e400 0x0 0x400>; 843 clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; 844 clock-names = "pclk", "clk32k_in"; 845 #clock-cells = <1>; 846 #interrupt-cells = <2>; 847 interrupt-controller; 848 849 powergates { 850 pd_audio: aud { 851 clocks = <&tegra_car TEGRA210_CLK_APE>, 852 <&tegra_car TEGRA210_CLK_APB2APE>; 853 resets = <&tegra_car 198>; 854 #power-domain-cells = <0>; 855 }; 856 857 pd_sor: sor { 858 clocks = <&tegra_car TEGRA210_CLK_SOR0>, 859 <&tegra_car TEGRA210_CLK_SOR1>, 860 <&tegra_car TEGRA210_CLK_CILAB>, 861 <&tegra_car TEGRA210_CLK_CILCD>, 862 <&tegra_car TEGRA210_CLK_CILE>, 863 <&tegra_car TEGRA210_CLK_DSIA>, 864 <&tegra_car TEGRA210_CLK_DSIB>, 865 <&tegra_car TEGRA210_CLK_DPAUX>, 866 <&tegra_car TEGRA210_CLK_DPAUX1>, 867 <&tegra_car TEGRA210_CLK_MIPI_CAL>; 868 resets = <&tegra_car TEGRA210_CLK_SOR0>, 869 <&tegra_car TEGRA210_CLK_SOR1>, 870 <&tegra_car TEGRA210_CLK_DSIA>, 871 <&tegra_car TEGRA210_CLK_DSIB>, 872 <&tegra_car TEGRA210_CLK_DPAUX>, 873 <&tegra_car TEGRA210_CLK_DPAUX1>, 874 <&tegra_car TEGRA210_CLK_MIPI_CAL>; 875 #power-domain-cells = <0>; 876 }; 877 878 pd_xusbss: xusba { 879 clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>; 880 resets = <&tegra_car TEGRA210_CLK_XUSB_SS>; 881 #power-domain-cells = <0>; 882 }; 883 884 pd_xusbdev: xusbb { 885 clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>; 886 resets = <&tegra_car 95>; 887 #power-domain-cells = <0>; 888 }; 889 890 pd_xusbhost: xusbc { 891 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>; 892 resets = <&tegra_car TEGRA210_CLK_XUSB_HOST>; 893 #power-domain-cells = <0>; 894 }; 895 896 pd_vic: vic { 897 clocks = <&tegra_car TEGRA210_CLK_VIC03>; 898 clock-names = "vic"; 899 resets = <&tegra_car 178>; 900 reset-names = "vic"; 901 #power-domain-cells = <0>; 902 }; 903 904 pd_venc: venc { 905 clocks = <&tegra_car TEGRA210_CLK_VI>, 906 <&tegra_car TEGRA210_CLK_CSI>; 907 resets = <&mc TEGRA210_MC_RESET_VI>, 908 <&tegra_car 20>, 909 <&tegra_car 52>; 910 #power-domain-cells = <0>; 911 }; 912 }; 913 914 pinmux { 915 sdmmc1_3v3: sdmmc1-3v3 { 916 pins = "sdmmc1"; 917 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 918 }; 919 920 sdmmc1_1v8: sdmmc1-1v8 { 921 pins = "sdmmc1"; 922 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 923 }; 924 925 sdmmc3_3v3: sdmmc3-3v3 { 926 pins = "sdmmc3"; 927 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 928 }; 929 930 sdmmc3_1v8: sdmmc3-1v8 { 931 pins = "sdmmc3"; 932 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 933 }; 934 935 pex_dpd_disable: pex-dpd-disable { 936 pins = "pex-bias", "pex-clk1", "pex-clk2"; 937 low-power-disable; 938 }; 939 940 pex_dpd_enable: pex-dpd-enable { 941 pins = "pex-bias", "pex-clk1", "pex-clk2"; 942 low-power-enable; 943 }; 944 }; 945 }; 946 947 fuse@7000f800 { 948 compatible = "nvidia,tegra210-efuse"; 949 reg = <0x0 0x7000f800 0x0 0x400>; 950 clocks = <&tegra_car TEGRA210_CLK_FUSE>; 951 clock-names = "fuse"; 952 resets = <&tegra_car 39>; 953 reset-names = "fuse"; 954 }; 955 956 mc: memory-controller@70019000 { 957 compatible = "nvidia,tegra210-mc"; 958 reg = <0x0 0x70019000 0x0 0x1000>; 959 clocks = <&tegra_car TEGRA210_CLK_MC>; 960 clock-names = "mc"; 961 962 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 963 964 #iommu-cells = <1>; 965 #reset-cells = <1>; 966 }; 967 968 emc: external-memory-controller@7001b000 { 969 compatible = "nvidia,tegra210-emc"; 970 reg = <0x0 0x7001b000 0x0 0x1000>, 971 <0x0 0x7001e000 0x0 0x1000>, 972 <0x0 0x7001f000 0x0 0x1000>; 973 clocks = <&tegra_car TEGRA210_CLK_EMC>; 974 clock-names = "emc"; 975 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 976 nvidia,memory-controller = <&mc>; 977 #cooling-cells = <2>; 978 }; 979 980 sata@70020000 { 981 compatible = "nvidia,tegra210-ahci"; 982 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */ 983 <0x0 0x70020000 0x0 0x7000>, /* SATA */ 984 <0x0 0x70001100 0x0 0x1000>; /* SATA AUX */ 985 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 986 clocks = <&tegra_car TEGRA210_CLK_SATA>, 987 <&tegra_car TEGRA210_CLK_SATA_OOB>; 988 clock-names = "sata", "sata-oob"; 989 resets = <&tegra_car 124>, 990 <&tegra_car 129>, 991 <&tegra_car 123>; 992 reset-names = "sata", "sata-cold", "sata-oob"; 993 status = "disabled"; 994 }; 995 996 hda@70030000 { 997 compatible = "nvidia,tegra210-hda", "nvidia,tegra30-hda"; 998 reg = <0x0 0x70030000 0x0 0x10000>; 999 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 1000 clocks = <&tegra_car TEGRA210_CLK_HDA>, 1001 <&tegra_car TEGRA210_CLK_HDA2HDMI>, 1002 <&tegra_car TEGRA210_CLK_HDA2CODEC_2X>; 1003 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 1004 resets = <&tegra_car 125>, /* hda */ 1005 <&tegra_car 128>, /* hda2hdmi */ 1006 <&tegra_car 111>; /* hda2codec_2x */ 1007 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 1008 power-domains = <&pd_sor>; 1009 status = "disabled"; 1010 }; 1011 1012 usb@70090000 { 1013 compatible = "nvidia,tegra210-xusb"; 1014 reg = <0x0 0x70090000 0x0 0x8000>, 1015 <0x0 0x70098000 0x0 0x1000>, 1016 <0x0 0x70099000 0x0 0x1000>; 1017 reg-names = "hcd", "fpci", "ipfs"; 1018 1019 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 1020 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 1021 1022 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>, 1023 <&tegra_car TEGRA210_CLK_XUSB_HOST_SRC>, 1024 <&tegra_car TEGRA210_CLK_XUSB_FALCON_SRC>, 1025 <&tegra_car TEGRA210_CLK_XUSB_SS>, 1026 <&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>, 1027 <&tegra_car TEGRA210_CLK_XUSB_SS_SRC>, 1028 <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>, 1029 <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>, 1030 <&tegra_car TEGRA210_CLK_PLL_U_480M>, 1031 <&tegra_car TEGRA210_CLK_CLK_M>, 1032 <&tegra_car TEGRA210_CLK_PLL_E>; 1033 clock-names = "xusb_host", "xusb_host_src", 1034 "xusb_falcon_src", "xusb_ss", 1035 "xusb_ss_div2", "xusb_ss_src", 1036 "xusb_hs_src", "xusb_fs_src", 1037 "pll_u_480m", "clk_m", "pll_e"; 1038 resets = <&tegra_car 89>, <&tegra_car 156>, 1039 <&tegra_car 143>; 1040 reset-names = "xusb_host", "xusb_ss", "xusb_src"; 1041 power-domains = <&pd_xusbhost>, <&pd_xusbss>; 1042 power-domain-names = "xusb_host", "xusb_ss"; 1043 1044 nvidia,xusb-padctl = <&padctl>; 1045 1046 status = "disabled"; 1047 }; 1048 1049 padctl: padctl@7009f000 { 1050 compatible = "nvidia,tegra210-xusb-padctl"; 1051 reg = <0x0 0x7009f000 0x0 0x1000>; 1052 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 1053 resets = <&tegra_car 142>; 1054 reset-names = "padctl"; 1055 nvidia,pmc = <&tegra_pmc>; 1056 1057 status = "disabled"; 1058 1059 pads { 1060 usb2 { 1061 clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>; 1062 clock-names = "trk"; 1063 status = "disabled"; 1064 1065 lanes { 1066 usb2-0 { 1067 status = "disabled"; 1068 #phy-cells = <0>; 1069 }; 1070 1071 usb2-1 { 1072 status = "disabled"; 1073 #phy-cells = <0>; 1074 }; 1075 1076 usb2-2 { 1077 status = "disabled"; 1078 #phy-cells = <0>; 1079 }; 1080 1081 usb2-3 { 1082 status = "disabled"; 1083 #phy-cells = <0>; 1084 }; 1085 }; 1086 }; 1087 1088 hsic { 1089 clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>; 1090 clock-names = "trk"; 1091 status = "disabled"; 1092 1093 lanes { 1094 hsic-0 { 1095 status = "disabled"; 1096 #phy-cells = <0>; 1097 }; 1098 1099 hsic-1 { 1100 status = "disabled"; 1101 #phy-cells = <0>; 1102 }; 1103 }; 1104 }; 1105 1106 pcie { 1107 clocks = <&tegra_car TEGRA210_CLK_PLL_E>; 1108 clock-names = "pll"; 1109 resets = <&tegra_car 205>; 1110 reset-names = "phy"; 1111 status = "disabled"; 1112 1113 lanes { 1114 pcie-0 { 1115 status = "disabled"; 1116 #phy-cells = <0>; 1117 }; 1118 1119 pcie-1 { 1120 status = "disabled"; 1121 #phy-cells = <0>; 1122 }; 1123 1124 pcie-2 { 1125 status = "disabled"; 1126 #phy-cells = <0>; 1127 }; 1128 1129 pcie-3 { 1130 status = "disabled"; 1131 #phy-cells = <0>; 1132 }; 1133 1134 pcie-4 { 1135 status = "disabled"; 1136 #phy-cells = <0>; 1137 }; 1138 1139 pcie-5 { 1140 status = "disabled"; 1141 #phy-cells = <0>; 1142 }; 1143 1144 pcie-6 { 1145 status = "disabled"; 1146 #phy-cells = <0>; 1147 }; 1148 }; 1149 }; 1150 1151 sata { 1152 clocks = <&tegra_car TEGRA210_CLK_PLL_E>; 1153 clock-names = "pll"; 1154 resets = <&tegra_car 204>; 1155 reset-names = "phy"; 1156 status = "disabled"; 1157 1158 lanes { 1159 sata-0 { 1160 status = "disabled"; 1161 #phy-cells = <0>; 1162 }; 1163 }; 1164 }; 1165 }; 1166 1167 ports { 1168 usb2-0 { 1169 status = "disabled"; 1170 }; 1171 1172 usb2-1 { 1173 status = "disabled"; 1174 }; 1175 1176 usb2-2 { 1177 status = "disabled"; 1178 }; 1179 1180 usb2-3 { 1181 status = "disabled"; 1182 }; 1183 1184 hsic-0 { 1185 status = "disabled"; 1186 }; 1187 1188 usb3-0 { 1189 status = "disabled"; 1190 }; 1191 1192 usb3-1 { 1193 status = "disabled"; 1194 }; 1195 1196 usb3-2 { 1197 status = "disabled"; 1198 }; 1199 1200 usb3-3 { 1201 status = "disabled"; 1202 }; 1203 }; 1204 }; 1205 1206 mmc@700b0000 { 1207 compatible = "nvidia,tegra210-sdhci"; 1208 reg = <0x0 0x700b0000 0x0 0x200>; 1209 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1210 clocks = <&tegra_car TEGRA210_CLK_SDMMC1>, 1211 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>; 1212 clock-names = "sdhci", "tmclk"; 1213 resets = <&tegra_car 14>; 1214 reset-names = "sdhci"; 1215 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8", 1216 "sdmmc-3v3-drv", "sdmmc-1v8-drv"; 1217 pinctrl-0 = <&sdmmc1_3v3>; 1218 pinctrl-1 = <&sdmmc1_1v8>; 1219 pinctrl-2 = <&sdmmc1_3v3_drv>; 1220 pinctrl-3 = <&sdmmc1_1v8_drv>; 1221 nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>; 1222 nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>; 1223 nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>; 1224 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>; 1225 nvidia,default-tap = <0x2>; 1226 nvidia,default-trim = <0x4>; 1227 assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>, 1228 <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>, 1229 <&tegra_car TEGRA210_CLK_PLL_C4>; 1230 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 1231 assigned-clock-rates = <200000000>, <1000000000>, <1000000000>; 1232 status = "disabled"; 1233 }; 1234 1235 mmc@700b0200 { 1236 compatible = "nvidia,tegra210-sdhci"; 1237 reg = <0x0 0x700b0200 0x0 0x200>; 1238 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 1239 clocks = <&tegra_car TEGRA210_CLK_SDMMC2>, 1240 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>; 1241 clock-names = "sdhci", "tmclk"; 1242 resets = <&tegra_car 9>; 1243 reset-names = "sdhci"; 1244 pinctrl-names = "sdmmc-1v8-drv"; 1245 pinctrl-0 = <&sdmmc2_1v8_drv>; 1246 nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>; 1247 nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>; 1248 nvidia,default-tap = <0x8>; 1249 nvidia,default-trim = <0x0>; 1250 status = "disabled"; 1251 }; 1252 1253 mmc@700b0400 { 1254 compatible = "nvidia,tegra210-sdhci"; 1255 reg = <0x0 0x700b0400 0x0 0x200>; 1256 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 1257 clocks = <&tegra_car TEGRA210_CLK_SDMMC3>, 1258 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>; 1259 clock-names = "sdhci", "tmclk"; 1260 resets = <&tegra_car 69>; 1261 reset-names = "sdhci"; 1262 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8", 1263 "sdmmc-3v3-drv", "sdmmc-1v8-drv"; 1264 pinctrl-0 = <&sdmmc3_3v3>; 1265 pinctrl-1 = <&sdmmc3_1v8>; 1266 pinctrl-2 = <&sdmmc3_3v3_drv>; 1267 pinctrl-3 = <&sdmmc3_1v8_drv>; 1268 nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>; 1269 nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>; 1270 nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>; 1271 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>; 1272 nvidia,default-tap = <0x3>; 1273 nvidia,default-trim = <0x3>; 1274 status = "disabled"; 1275 }; 1276 1277 mmc@700b0600 { 1278 compatible = "nvidia,tegra210-sdhci"; 1279 reg = <0x0 0x700b0600 0x0 0x200>; 1280 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1281 clocks = <&tegra_car TEGRA210_CLK_SDMMC4>, 1282 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>; 1283 clock-names = "sdhci", "tmclk"; 1284 resets = <&tegra_car 15>; 1285 reset-names = "sdhci"; 1286 pinctrl-names = "sdmmc-3v3-drv", "sdmmc-1v8-drv"; 1287 pinctrl-0 = <&sdmmc4_1v8_drv>; 1288 pinctrl-1 = <&sdmmc4_1v8_drv>; 1289 nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>; 1290 nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>; 1291 nvidia,default-tap = <0x8>; 1292 nvidia,default-trim = <0x0>; 1293 assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>, 1294 <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 1295 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 1296 nvidia,dqs-trim = <40>; 1297 mmc-hs400-1_8v; 1298 status = "disabled"; 1299 }; 1300 1301 usb@700d0000 { 1302 compatible = "nvidia,tegra210-xudc"; 1303 reg = <0x0 0x700d0000 0x0 0x8000>, 1304 <0x0 0x700d8000 0x0 0x1000>, 1305 <0x0 0x700d9000 0x0 0x1000>; 1306 reg-names = "base", "fpci", "ipfs"; 1307 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1308 clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>, 1309 <&tegra_car TEGRA210_CLK_XUSB_SS>, 1310 <&tegra_car TEGRA210_CLK_XUSB_SSP_SRC>, 1311 <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>, 1312 <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>; 1313 clock-names = "dev", "ss", "ss_src", "fs_src", "hs_src"; 1314 power-domains = <&pd_xusbdev>, <&pd_xusbss>; 1315 power-domain-names = "dev", "ss"; 1316 nvidia,xusb-padctl = <&padctl>; 1317 status = "disabled"; 1318 }; 1319 1320 soctherm: thermal-sensor@700e2000 { 1321 compatible = "nvidia,tegra210-soctherm"; 1322 reg = <0x0 0x700e2000 0x0 0x600>, /* SOC_THERM reg_base */ 1323 <0x0 0x60006000 0x0 0x400>; /* CAR reg_base */ 1324 reg-names = "soctherm-reg", "car-reg"; 1325 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 1326 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 1327 interrupt-names = "thermal", "edp"; 1328 clocks = <&tegra_car TEGRA210_CLK_TSENSOR>, 1329 <&tegra_car TEGRA210_CLK_SOC_THERM>; 1330 clock-names = "tsensor", "soctherm"; 1331 resets = <&tegra_car 78>; 1332 reset-names = "soctherm"; 1333 #thermal-sensor-cells = <1>; 1334 1335 throttle-cfgs { 1336 throttle_heavy: heavy { 1337 nvidia,priority = <100>; 1338 nvidia,cpu-throt-percent = <85>; 1339 nvidia,gpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_HIGH>; 1340 1341 #cooling-cells = <2>; 1342 }; 1343 }; 1344 }; 1345 1346 mipi: mipi@700e3000 { 1347 compatible = "nvidia,tegra210-mipi"; 1348 reg = <0x0 0x700e3000 0x0 0x100>; 1349 clocks = <&tegra_car TEGRA210_CLK_MIPI_CAL>; 1350 clock-names = "mipi-cal"; 1351 power-domains = <&pd_sor>; 1352 #nvidia,mipi-calibrate-cells = <1>; 1353 }; 1354 1355 dfll: clock@70110000 { 1356 compatible = "nvidia,tegra210-dfll"; 1357 reg = <0 0x70110000 0 0x100>, /* DFLL control */ 1358 <0 0x70110000 0 0x100>, /* I2C output control */ 1359 <0 0x70110100 0 0x100>, /* Integrated I2C controller */ 1360 <0 0x70110200 0 0x100>; /* Look-up table RAM */ 1361 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 1362 clocks = <&tegra_car TEGRA210_CLK_DFLL_SOC>, 1363 <&tegra_car TEGRA210_CLK_DFLL_REF>, 1364 <&tegra_car TEGRA210_CLK_I2C5>; 1365 clock-names = "soc", "ref", "i2c"; 1366 resets = <&tegra_car TEGRA210_RST_DFLL_DVCO>, 1367 <&tegra_car 155>; 1368 reset-names = "dvco", "dfll"; 1369 #clock-cells = <0>; 1370 clock-output-names = "dfllCPU_out"; 1371 status = "disabled"; 1372 }; 1373 1374 aconnect@702c0000 { 1375 compatible = "nvidia,tegra210-aconnect"; 1376 clocks = <&tegra_car TEGRA210_CLK_APE>, 1377 <&tegra_car TEGRA210_CLK_APB2APE>; 1378 clock-names = "ape", "apb2ape"; 1379 power-domains = <&pd_audio>; 1380 #address-cells = <1>; 1381 #size-cells = <1>; 1382 ranges = <0x702c0000 0x0 0x702c0000 0x00040000>; 1383 status = "disabled"; 1384 1385 adma: dma-controller@702e2000 { 1386 compatible = "nvidia,tegra210-adma"; 1387 reg = <0x702e2000 0x2000>; 1388 interrupt-parent = <&agic>; 1389 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 1390 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 1391 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 1392 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 1393 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 1394 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 1395 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 1396 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 1397 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 1398 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 1399 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 1400 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 1401 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 1402 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 1403 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 1404 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 1405 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 1406 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 1407 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 1408 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 1409 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 1410 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1411 #dma-cells = <1>; 1412 clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>; 1413 clock-names = "d_audio"; 1414 status = "disabled"; 1415 }; 1416 1417 agic: interrupt-controller@702f9000 { 1418 compatible = "nvidia,tegra210-agic"; 1419 #interrupt-cells = <3>; 1420 interrupt-controller; 1421 reg = <0x702f9000 0x1000>, 1422 <0x702fa000 0x2000>; 1423 interrupts = <GIC_SPI 102 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1424 clocks = <&tegra_car TEGRA210_CLK_APE>; 1425 clock-names = "clk"; 1426 status = "disabled"; 1427 }; 1428 1429 tegra_ahub: ahub@702d0800 { 1430 compatible = "nvidia,tegra210-ahub"; 1431 reg = <0x702d0800 0x800>; 1432 clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>; 1433 clock-names = "ahub"; 1434 assigned-clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>; 1435 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1436 #address-cells = <1>; 1437 #size-cells = <1>; 1438 ranges = <0x702d0000 0x702d0000 0x0000e400>; 1439 status = "disabled"; 1440 1441 tegra_admaif: admaif@702d0000 { 1442 compatible = "nvidia,tegra210-admaif"; 1443 reg = <0x702d0000 0x800>; 1444 dmas = <&adma 1>, <&adma 1>, 1445 <&adma 2>, <&adma 2>, 1446 <&adma 3>, <&adma 3>, 1447 <&adma 4>, <&adma 4>, 1448 <&adma 5>, <&adma 5>, 1449 <&adma 6>, <&adma 6>, 1450 <&adma 7>, <&adma 7>, 1451 <&adma 8>, <&adma 8>, 1452 <&adma 9>, <&adma 9>, 1453 <&adma 10>, <&adma 10>; 1454 dma-names = "rx1", "tx1", 1455 "rx2", "tx2", 1456 "rx3", "tx3", 1457 "rx4", "tx4", 1458 "rx5", "tx5", 1459 "rx6", "tx6", 1460 "rx7", "tx7", 1461 "rx8", "tx8", 1462 "rx9", "tx9", 1463 "rx10", "tx10"; 1464 status = "disabled"; 1465 1466 ports { 1467 #address-cells = <1>; 1468 #size-cells = <0>; 1469 1470 admaif1_port: port@0 { 1471 reg = <0>; 1472 1473 admaif1_ep: endpoint { 1474 remote-endpoint = <&xbar_admaif1_ep>; 1475 }; 1476 }; 1477 1478 admaif2_port: port@1 { 1479 reg = <1>; 1480 1481 admaif2_ep: endpoint { 1482 remote-endpoint = <&xbar_admaif2_ep>; 1483 }; 1484 }; 1485 1486 admaif3_port: port@2 { 1487 reg = <2>; 1488 1489 admaif3_ep: endpoint { 1490 remote-endpoint = <&xbar_admaif3_ep>; 1491 }; 1492 }; 1493 1494 admaif4_port: port@3 { 1495 reg = <3>; 1496 1497 admaif4_ep: endpoint { 1498 remote-endpoint = <&xbar_admaif4_ep>; 1499 }; 1500 }; 1501 1502 admaif5_port: port@4 { 1503 reg = <4>; 1504 1505 admaif5_ep: endpoint { 1506 remote-endpoint = <&xbar_admaif5_ep>; 1507 }; 1508 }; 1509 1510 admaif6_port: port@5 { 1511 reg = <5>; 1512 1513 admaif6_ep: endpoint { 1514 remote-endpoint = <&xbar_admaif6_ep>; 1515 }; 1516 }; 1517 1518 admaif7_port: port@6 { 1519 reg = <6>; 1520 1521 admaif7_ep: endpoint { 1522 remote-endpoint = <&xbar_admaif7_ep>; 1523 }; 1524 }; 1525 1526 admaif8_port: port@7 { 1527 reg = <7>; 1528 1529 admaif8_ep: endpoint { 1530 remote-endpoint = <&xbar_admaif8_ep>; 1531 }; 1532 }; 1533 1534 admaif9_port: port@8 { 1535 reg = <8>; 1536 1537 admaif9_ep: endpoint { 1538 remote-endpoint = <&xbar_admaif9_ep>; 1539 }; 1540 }; 1541 1542 admaif10_port: port@9 { 1543 reg = <9>; 1544 1545 admaif10_ep: endpoint { 1546 remote-endpoint = <&xbar_admaif10_ep>; 1547 }; 1548 }; 1549 }; 1550 }; 1551 1552 tegra_i2s1: i2s@702d1000 { 1553 compatible = "nvidia,tegra210-i2s"; 1554 reg = <0x702d1000 0x100>; 1555 clocks = <&tegra_car TEGRA210_CLK_I2S0>, 1556 <&tegra_car TEGRA210_CLK_I2S0_SYNC>; 1557 clock-names = "i2s", "sync_input"; 1558 assigned-clocks = <&tegra_car TEGRA210_CLK_I2S0>; 1559 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1560 assigned-clock-rates = <1536000>; 1561 sound-name-prefix = "I2S1"; 1562 status = "disabled"; 1563 }; 1564 1565 tegra_i2s2: i2s@702d1100 { 1566 compatible = "nvidia,tegra210-i2s"; 1567 reg = <0x702d1100 0x100>; 1568 clocks = <&tegra_car TEGRA210_CLK_I2S1>, 1569 <&tegra_car TEGRA210_CLK_I2S1_SYNC>; 1570 clock-names = "i2s", "sync_input"; 1571 assigned-clocks = <&tegra_car TEGRA210_CLK_I2S1>; 1572 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1573 assigned-clock-rates = <1536000>; 1574 sound-name-prefix = "I2S2"; 1575 status = "disabled"; 1576 }; 1577 1578 tegra_i2s3: i2s@702d1200 { 1579 compatible = "nvidia,tegra210-i2s"; 1580 reg = <0x702d1200 0x100>; 1581 clocks = <&tegra_car TEGRA210_CLK_I2S2>, 1582 <&tegra_car TEGRA210_CLK_I2S2_SYNC>; 1583 clock-names = "i2s", "sync_input"; 1584 assigned-clocks = <&tegra_car TEGRA210_CLK_I2S2>; 1585 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1586 assigned-clock-rates = <1536000>; 1587 sound-name-prefix = "I2S3"; 1588 status = "disabled"; 1589 }; 1590 1591 tegra_i2s4: i2s@702d1300 { 1592 compatible = "nvidia,tegra210-i2s"; 1593 reg = <0x702d1300 0x100>; 1594 clocks = <&tegra_car TEGRA210_CLK_I2S3>, 1595 <&tegra_car TEGRA210_CLK_I2S3_SYNC>; 1596 clock-names = "i2s", "sync_input"; 1597 assigned-clocks = <&tegra_car TEGRA210_CLK_I2S3>; 1598 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1599 assigned-clock-rates = <1536000>; 1600 sound-name-prefix = "I2S4"; 1601 status = "disabled"; 1602 }; 1603 1604 tegra_i2s5: i2s@702d1400 { 1605 compatible = "nvidia,tegra210-i2s"; 1606 reg = <0x702d1400 0x100>; 1607 clocks = <&tegra_car TEGRA210_CLK_I2S4>, 1608 <&tegra_car TEGRA210_CLK_I2S4_SYNC>; 1609 clock-names = "i2s", "sync_input"; 1610 assigned-clocks = <&tegra_car TEGRA210_CLK_I2S4>; 1611 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1612 assigned-clock-rates = <1536000>; 1613 sound-name-prefix = "I2S5"; 1614 status = "disabled"; 1615 }; 1616 1617 tegra_dmic1: dmic@702d4000 { 1618 compatible = "nvidia,tegra210-dmic"; 1619 reg = <0x702d4000 0x100>; 1620 clocks = <&tegra_car TEGRA210_CLK_DMIC1>; 1621 clock-names = "dmic"; 1622 assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC1>; 1623 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1624 assigned-clock-rates = <3072000>; 1625 sound-name-prefix = "DMIC1"; 1626 status = "disabled"; 1627 }; 1628 1629 tegra_dmic2: dmic@702d4100 { 1630 compatible = "nvidia,tegra210-dmic"; 1631 reg = <0x702d4100 0x100>; 1632 clocks = <&tegra_car TEGRA210_CLK_DMIC2>; 1633 clock-names = "dmic"; 1634 assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC2>; 1635 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1636 assigned-clock-rates = <3072000>; 1637 sound-name-prefix = "DMIC2"; 1638 status = "disabled"; 1639 }; 1640 1641 tegra_dmic3: dmic@702d4200 { 1642 compatible = "nvidia,tegra210-dmic"; 1643 reg = <0x702d4200 0x100>; 1644 clocks = <&tegra_car TEGRA210_CLK_DMIC3>; 1645 clock-names = "dmic"; 1646 assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC3>; 1647 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1648 assigned-clock-rates = <3072000>; 1649 sound-name-prefix = "DMIC3"; 1650 status = "disabled"; 1651 }; 1652 1653 tegra_sfc1: sfc@702d2000 { 1654 compatible = "nvidia,tegra210-sfc"; 1655 reg = <0x702d2000 0x200>; 1656 sound-name-prefix = "SFC1"; 1657 status = "disabled"; 1658 }; 1659 1660 tegra_sfc2: sfc@702d2200 { 1661 compatible = "nvidia,tegra210-sfc"; 1662 reg = <0x702d2200 0x200>; 1663 sound-name-prefix = "SFC2"; 1664 status = "disabled"; 1665 }; 1666 1667 tegra_sfc3: sfc@702d2400 { 1668 compatible = "nvidia,tegra210-sfc"; 1669 reg = <0x702d2400 0x200>; 1670 sound-name-prefix = "SFC3"; 1671 status = "disabled"; 1672 }; 1673 1674 tegra_sfc4: sfc@702d2600 { 1675 compatible = "nvidia,tegra210-sfc"; 1676 reg = <0x702d2600 0x200>; 1677 sound-name-prefix = "SFC4"; 1678 status = "disabled"; 1679 }; 1680 1681 tegra_mvc1: mvc@702da000 { 1682 compatible = "nvidia,tegra210-mvc"; 1683 reg = <0x702da000 0x200>; 1684 sound-name-prefix = "MVC1"; 1685 status = "disabled"; 1686 }; 1687 1688 tegra_mvc2: mvc@702da200 { 1689 compatible = "nvidia,tegra210-mvc"; 1690 reg = <0x702da200 0x200>; 1691 sound-name-prefix = "MVC2"; 1692 status = "disabled"; 1693 }; 1694 1695 tegra_amx1: amx@702d3000 { 1696 compatible = "nvidia,tegra210-amx"; 1697 reg = <0x702d3000 0x100>; 1698 sound-name-prefix = "AMX1"; 1699 status = "disabled"; 1700 }; 1701 1702 tegra_amx2: amx@702d3100 { 1703 compatible = "nvidia,tegra210-amx"; 1704 reg = <0x702d3100 0x100>; 1705 sound-name-prefix = "AMX2"; 1706 status = "disabled"; 1707 }; 1708 1709 tegra_adx1: adx@702d3800 { 1710 compatible = "nvidia,tegra210-adx"; 1711 reg = <0x702d3800 0x100>; 1712 sound-name-prefix = "ADX1"; 1713 status = "disabled"; 1714 }; 1715 1716 tegra_adx2: adx@702d3900 { 1717 compatible = "nvidia,tegra210-adx"; 1718 reg = <0x702d3900 0x100>; 1719 sound-name-prefix = "ADX2"; 1720 status = "disabled"; 1721 }; 1722 1723 tegra_ope1: processing-engine@702d8000 { 1724 compatible = "nvidia,tegra210-ope"; 1725 reg = <0x702d8000 0x100>; 1726 #address-cells = <1>; 1727 #size-cells = <1>; 1728 ranges; 1729 sound-name-prefix = "OPE1"; 1730 status = "disabled"; 1731 1732 equalizer@702d8100 { 1733 compatible = "nvidia,tegra210-peq"; 1734 reg = <0x702d8100 0x100>; 1735 }; 1736 1737 dynamic-range-compressor@702d8200 { 1738 compatible = "nvidia,tegra210-mbdrc"; 1739 reg = <0x702d8200 0x200>; 1740 }; 1741 }; 1742 1743 tegra_ope2: processing-engine@702d8400 { 1744 compatible = "nvidia,tegra210-ope"; 1745 reg = <0x702d8400 0x100>; 1746 #address-cells = <1>; 1747 #size-cells = <1>; 1748 ranges; 1749 sound-name-prefix = "OPE2"; 1750 status = "disabled"; 1751 1752 equalizer@702d8500 { 1753 compatible = "nvidia,tegra210-peq"; 1754 reg = <0x702d8500 0x100>; 1755 }; 1756 1757 dynamic-range-compressor@702d8600 { 1758 compatible = "nvidia,tegra210-mbdrc"; 1759 reg = <0x702d8600 0x200>; 1760 }; 1761 }; 1762 1763 tegra_amixer: amixer@702dbb00 { 1764 compatible = "nvidia,tegra210-amixer"; 1765 reg = <0x702dbb00 0x800>; 1766 sound-name-prefix = "MIXER1"; 1767 status = "disabled"; 1768 }; 1769 1770 ports { 1771 #address-cells = <1>; 1772 #size-cells = <0>; 1773 1774 port@0 { 1775 reg = <0x0>; 1776 1777 xbar_admaif1_ep: endpoint { 1778 remote-endpoint = <&admaif1_ep>; 1779 }; 1780 }; 1781 1782 port@1 { 1783 reg = <0x1>; 1784 1785 xbar_admaif2_ep: endpoint { 1786 remote-endpoint = <&admaif2_ep>; 1787 }; 1788 }; 1789 1790 port@2 { 1791 reg = <0x2>; 1792 1793 xbar_admaif3_ep: endpoint { 1794 remote-endpoint = <&admaif3_ep>; 1795 }; 1796 }; 1797 1798 port@3 { 1799 reg = <0x3>; 1800 1801 xbar_admaif4_ep: endpoint { 1802 remote-endpoint = <&admaif4_ep>; 1803 }; 1804 }; 1805 1806 port@4 { 1807 reg = <0x4>; 1808 xbar_admaif5_ep: endpoint { 1809 remote-endpoint = <&admaif5_ep>; 1810 }; 1811 }; 1812 port@5 { 1813 reg = <0x5>; 1814 1815 xbar_admaif6_ep: endpoint { 1816 remote-endpoint = <&admaif6_ep>; 1817 }; 1818 }; 1819 1820 port@6 { 1821 reg = <0x6>; 1822 1823 xbar_admaif7_ep: endpoint { 1824 remote-endpoint = <&admaif7_ep>; 1825 }; 1826 }; 1827 1828 port@7 { 1829 reg = <0x7>; 1830 1831 xbar_admaif8_ep: endpoint { 1832 remote-endpoint = <&admaif8_ep>; 1833 }; 1834 }; 1835 1836 port@8 { 1837 reg = <0x8>; 1838 1839 xbar_admaif9_ep: endpoint { 1840 remote-endpoint = <&admaif9_ep>; 1841 }; 1842 }; 1843 1844 port@9 { 1845 reg = <0x9>; 1846 1847 xbar_admaif10_ep: endpoint { 1848 remote-endpoint = <&admaif10_ep>; 1849 }; 1850 }; 1851 }; 1852 }; 1853 }; 1854 1855 spi@70410000 { 1856 compatible = "nvidia,tegra210-qspi"; 1857 reg = <0x0 0x70410000 0x0 0x1000>; 1858 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1859 #address-cells = <1>; 1860 #size-cells = <0>; 1861 clocks = <&tegra_car TEGRA210_CLK_QSPI>, 1862 <&tegra_car TEGRA210_CLK_QSPI_PM>; 1863 clock-names = "qspi", "qspi_out"; 1864 resets = <&tegra_car 211>; 1865 reset-names = "qspi"; 1866 dmas = <&apbdma 5>, <&apbdma 5>; 1867 dma-names = "rx", "tx"; 1868 status = "disabled"; 1869 }; 1870 1871 usb@7d000000 { 1872 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci"; 1873 reg = <0x0 0x7d000000 0x0 0x4000>; 1874 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1875 phy_type = "utmi"; 1876 clocks = <&tegra_car TEGRA210_CLK_USBD>; 1877 clock-names = "usb"; 1878 resets = <&tegra_car 22>; 1879 reset-names = "usb"; 1880 nvidia,phy = <&phy1>; 1881 status = "disabled"; 1882 }; 1883 1884 phy1: usb-phy@7d000000 { 1885 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; 1886 reg = <0x0 0x7d000000 0x0 0x4000>, 1887 <0x0 0x7d000000 0x0 0x4000>; 1888 phy_type = "utmi"; 1889 clocks = <&tegra_car TEGRA210_CLK_USBD>, 1890 <&tegra_car TEGRA210_CLK_PLL_U>, 1891 <&tegra_car TEGRA210_CLK_USBD>; 1892 clock-names = "reg", "pll_u", "utmi-pads"; 1893 resets = <&tegra_car 22>, <&tegra_car 22>; 1894 reset-names = "usb", "utmi-pads"; 1895 nvidia,hssync-start-delay = <0>; 1896 nvidia,idle-wait-delay = <17>; 1897 nvidia,elastic-limit = <16>; 1898 nvidia,term-range-adj = <6>; 1899 nvidia,xcvr-setup = <9>; 1900 nvidia,xcvr-lsfslew = <0>; 1901 nvidia,xcvr-lsrslew = <3>; 1902 nvidia,hssquelch-level = <2>; 1903 nvidia,hsdiscon-level = <5>; 1904 nvidia,xcvr-hsslew = <12>; 1905 nvidia,has-utmi-pad-registers; 1906 status = "disabled"; 1907 }; 1908 1909 usb@7d004000 { 1910 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci"; 1911 reg = <0x0 0x7d004000 0x0 0x4000>; 1912 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1913 phy_type = "utmi"; 1914 clocks = <&tegra_car TEGRA210_CLK_USB2>; 1915 clock-names = "usb"; 1916 resets = <&tegra_car 58>; 1917 reset-names = "usb"; 1918 nvidia,phy = <&phy2>; 1919 status = "disabled"; 1920 }; 1921 1922 phy2: usb-phy@7d004000 { 1923 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; 1924 reg = <0x0 0x7d004000 0x0 0x4000>, 1925 <0x0 0x7d000000 0x0 0x4000>; 1926 phy_type = "utmi"; 1927 clocks = <&tegra_car TEGRA210_CLK_USB2>, 1928 <&tegra_car TEGRA210_CLK_PLL_U>, 1929 <&tegra_car TEGRA210_CLK_USBD>; 1930 clock-names = "reg", "pll_u", "utmi-pads"; 1931 resets = <&tegra_car 58>, <&tegra_car 22>; 1932 reset-names = "usb", "utmi-pads"; 1933 nvidia,hssync-start-delay = <0>; 1934 nvidia,idle-wait-delay = <17>; 1935 nvidia,elastic-limit = <16>; 1936 nvidia,term-range-adj = <6>; 1937 nvidia,xcvr-setup = <9>; 1938 nvidia,xcvr-lsfslew = <0>; 1939 nvidia,xcvr-lsrslew = <3>; 1940 nvidia,hssquelch-level = <2>; 1941 nvidia,hsdiscon-level = <5>; 1942 nvidia,xcvr-hsslew = <12>; 1943 status = "disabled"; 1944 }; 1945 1946 cpus { 1947 #address-cells = <1>; 1948 #size-cells = <0>; 1949 1950 cpu@0 { 1951 device_type = "cpu"; 1952 compatible = "arm,cortex-a57"; 1953 reg = <0>; 1954 clocks = <&tegra_car TEGRA210_CLK_CCLK_G>, 1955 <&tegra_car TEGRA210_CLK_PLL_X>, 1956 <&tegra_car TEGRA210_CLK_PLL_P_OUT4>, 1957 <&dfll>; 1958 clock-names = "cpu_g", "pll_x", "pll_p", "dfll"; 1959 clock-latency = <300000>; 1960 cpu-idle-states = <&CPU_SLEEP>; 1961 next-level-cache = <&L2>; 1962 }; 1963 1964 cpu@1 { 1965 device_type = "cpu"; 1966 compatible = "arm,cortex-a57"; 1967 reg = <1>; 1968 cpu-idle-states = <&CPU_SLEEP>; 1969 next-level-cache = <&L2>; 1970 }; 1971 1972 cpu@2 { 1973 device_type = "cpu"; 1974 compatible = "arm,cortex-a57"; 1975 reg = <2>; 1976 cpu-idle-states = <&CPU_SLEEP>; 1977 next-level-cache = <&L2>; 1978 }; 1979 1980 cpu@3 { 1981 device_type = "cpu"; 1982 compatible = "arm,cortex-a57"; 1983 reg = <3>; 1984 cpu-idle-states = <&CPU_SLEEP>; 1985 next-level-cache = <&L2>; 1986 }; 1987 1988 idle-states { 1989 entry-method = "psci"; 1990 1991 CPU_SLEEP: cpu-sleep { 1992 compatible = "arm,idle-state"; 1993 arm,psci-suspend-param = <0x40000007>; 1994 entry-latency-us = <100>; 1995 exit-latency-us = <30>; 1996 min-residency-us = <1000>; 1997 wakeup-latency-us = <130>; 1998 idle-state-name = "cpu-sleep"; 1999 status = "disabled"; 2000 }; 2001 }; 2002 2003 L2: l2-cache { 2004 compatible = "cache"; 2005 cache-level = <2>; 2006 }; 2007 }; 2008 2009 pmu { 2010 compatible = "arm,armv8-pmuv3"; 2011 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 2012 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 2013 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 2014 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 2015 interrupt-affinity = <&{/cpus/cpu@0} &{/cpus/cpu@1} 2016 &{/cpus/cpu@2} &{/cpus/cpu@3}>; 2017 }; 2018 2019 sound { 2020 status = "disabled"; 2021 2022 clocks = <&tegra_car TEGRA210_CLK_PLL_A>, 2023 <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 2024 clock-names = "pll_a", "plla_out0"; 2025 2026 assigned-clocks = <&tegra_car TEGRA210_CLK_PLL_A>, 2027 <&tegra_car TEGRA210_CLK_PLL_A_OUT0>, 2028 <&tegra_car TEGRA210_CLK_EXTERN1>; 2029 assigned-clock-parents = <0>, <0>, <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 2030 assigned-clock-rates = <368640000>, <49152000>, <12288000>; 2031 }; 2032 2033 thermal-zones { 2034 cpu-thermal { 2035 polling-delay-passive = <1000>; 2036 polling-delay = <0>; 2037 2038 thermal-sensors = 2039 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; 2040 2041 trips { 2042 cpu-shutdown-trip { 2043 temperature = <102500>; 2044 hysteresis = <0>; 2045 type = "critical"; 2046 }; 2047 2048 cpu_throttle_trip: throttle-trip { 2049 temperature = <98500>; 2050 hysteresis = <1000>; 2051 type = "hot"; 2052 }; 2053 }; 2054 2055 cooling-maps { 2056 map0 { 2057 trip = <&cpu_throttle_trip>; 2058 cooling-device = <&throttle_heavy 1 1>; 2059 }; 2060 }; 2061 }; 2062 2063 mem-thermal { 2064 polling-delay-passive = <0>; 2065 polling-delay = <0>; 2066 2067 thermal-sensors = 2068 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>; 2069 2070 trips { 2071 dram_nominal: mem-nominal-trip { 2072 temperature = <50000>; 2073 hysteresis = <1000>; 2074 type = "passive"; 2075 }; 2076 2077 dram_throttle: mem-throttle-trip { 2078 temperature = <70000>; 2079 hysteresis = <1000>; 2080 type = "active"; 2081 }; 2082 2083 mem-hot-trip { 2084 temperature = <100000>; 2085 hysteresis = <1000>; 2086 type = "hot"; 2087 }; 2088 2089 mem-shutdown-trip { 2090 temperature = <103000>; 2091 hysteresis = <0>; 2092 type = "critical"; 2093 }; 2094 }; 2095 2096 cooling-maps { 2097 dram-passive { 2098 cooling-device = <&emc 0 0>; 2099 trip = <&dram_nominal>; 2100 }; 2101 2102 dram-active { 2103 cooling-device = <&emc 1 1>; 2104 trip = <&dram_throttle>; 2105 }; 2106 }; 2107 }; 2108 2109 gpu-thermal { 2110 polling-delay-passive = <1000>; 2111 polling-delay = <0>; 2112 2113 thermal-sensors = 2114 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>; 2115 2116 trips { 2117 gpu-shutdown-trip { 2118 temperature = <103000>; 2119 hysteresis = <0>; 2120 type = "critical"; 2121 }; 2122 2123 gpu_throttle_trip: throttle-trip { 2124 temperature = <100000>; 2125 hysteresis = <1000>; 2126 type = "hot"; 2127 }; 2128 }; 2129 2130 cooling-maps { 2131 map0 { 2132 trip = <&gpu_throttle_trip>; 2133 cooling-device = <&throttle_heavy 1 1>; 2134 }; 2135 }; 2136 }; 2137 2138 pllx-thermal { 2139 polling-delay-passive = <0>; 2140 polling-delay = <0>; 2141 2142 thermal-sensors = 2143 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>; 2144 2145 trips { 2146 pllx-shutdown-trip { 2147 temperature = <103000>; 2148 hysteresis = <0>; 2149 type = "critical"; 2150 }; 2151 2152 pllx-throttle-trip { 2153 temperature = <100000>; 2154 hysteresis = <1000>; 2155 type = "hot"; 2156 }; 2157 }; 2158 2159 cooling-maps { 2160 /* 2161 * There are currently no cooling maps, 2162 * because there are no cooling devices. 2163 */ 2164 }; 2165 }; 2166 }; 2167 2168 timer { 2169 compatible = "arm,armv8-timer"; 2170 interrupts = <GIC_PPI 13 2171 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2172 <GIC_PPI 14 2173 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2174 <GIC_PPI 11 2175 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2176 <GIC_PPI 10 2177 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 2178 interrupt-parent = <&gic>; 2179 arm,no-tick-in-suspend; 2180 }; 2181}; 2182