1#include <dt-bindings/clock/tegra210-car.h> 2#include <dt-bindings/gpio/tegra-gpio.h> 3#include <dt-bindings/memory/tegra210-mc.h> 4#include <dt-bindings/pinctrl/pinctrl-tegra.h> 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6 7/ { 8 compatible = "nvidia,tegra210"; 9 interrupt-parent = <&lic>; 10 #address-cells = <2>; 11 #size-cells = <2>; 12 13 host1x@50000000 { 14 compatible = "nvidia,tegra210-host1x", "simple-bus"; 15 reg = <0x0 0x50000000 0x0 0x00034000>; 16 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 17 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ 18 clocks = <&tegra_car TEGRA210_CLK_HOST1X>; 19 clock-names = "host1x"; 20 resets = <&tegra_car 28>; 21 reset-names = "host1x"; 22 23 #address-cells = <2>; 24 #size-cells = <2>; 25 26 ranges = <0x0 0x54000000 0x0 0x54000000 0x0 0x01000000>; 27 28 dpaux1: dpaux@54040000 { 29 compatible = "nvidia,tegra210-dpaux"; 30 reg = <0x0 0x54040000 0x0 0x00040000>; 31 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 32 clocks = <&tegra_car TEGRA210_CLK_DPAUX1>, 33 <&tegra_car TEGRA210_CLK_PLL_DP>; 34 clock-names = "dpaux", "parent"; 35 resets = <&tegra_car 207>; 36 reset-names = "dpaux"; 37 status = "disabled"; 38 39 state_dpaux1_aux: pinmux-aux { 40 groups = "dpaux-io"; 41 function = "aux"; 42 }; 43 44 state_dpaux1_i2c: pinmux-i2c { 45 groups = "dpaux-io"; 46 function = "i2c"; 47 }; 48 49 state_dpaux1_off: pinmux-off { 50 groups = "dpaux-io"; 51 function = "off"; 52 }; 53 54 i2c-bus { 55 #address-cells = <1>; 56 #size-cells = <0>; 57 }; 58 }; 59 60 vi@54080000 { 61 compatible = "nvidia,tegra210-vi"; 62 reg = <0x0 0x54080000 0x0 0x00040000>; 63 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 64 status = "disabled"; 65 }; 66 67 tsec@54100000 { 68 compatible = "nvidia,tegra210-tsec"; 69 reg = <0x0 0x54100000 0x0 0x00040000>; 70 }; 71 72 dc@54200000 { 73 compatible = "nvidia,tegra210-dc"; 74 reg = <0x0 0x54200000 0x0 0x00040000>; 75 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 76 clocks = <&tegra_car TEGRA210_CLK_DISP1>, 77 <&tegra_car TEGRA210_CLK_PLL_P>; 78 clock-names = "dc", "parent"; 79 resets = <&tegra_car 27>; 80 reset-names = "dc"; 81 82 iommus = <&mc TEGRA_SWGROUP_DC>; 83 84 nvidia,head = <0>; 85 }; 86 87 dc@54240000 { 88 compatible = "nvidia,tegra210-dc"; 89 reg = <0x0 0x54240000 0x0 0x00040000>; 90 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 91 clocks = <&tegra_car TEGRA210_CLK_DISP2>, 92 <&tegra_car TEGRA210_CLK_PLL_P>; 93 clock-names = "dc", "parent"; 94 resets = <&tegra_car 26>; 95 reset-names = "dc"; 96 97 iommus = <&mc TEGRA_SWGROUP_DCB>; 98 99 nvidia,head = <1>; 100 }; 101 102 dsi@54300000 { 103 compatible = "nvidia,tegra210-dsi"; 104 reg = <0x0 0x54300000 0x0 0x00040000>; 105 clocks = <&tegra_car TEGRA210_CLK_DSIA>, 106 <&tegra_car TEGRA210_CLK_DSIALP>, 107 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; 108 clock-names = "dsi", "lp", "parent"; 109 resets = <&tegra_car 48>; 110 reset-names = "dsi"; 111 nvidia,mipi-calibrate = <&mipi 0x0c0>; /* DSIA & DSIB pads */ 112 113 status = "disabled"; 114 115 #address-cells = <1>; 116 #size-cells = <0>; 117 }; 118 119 vic@54340000 { 120 compatible = "nvidia,tegra210-vic"; 121 reg = <0x0 0x54340000 0x0 0x00040000>; 122 status = "disabled"; 123 }; 124 125 nvjpg@54380000 { 126 compatible = "nvidia,tegra210-nvjpg"; 127 reg = <0x0 0x54380000 0x0 0x00040000>; 128 status = "disabled"; 129 }; 130 131 dsi@54400000 { 132 compatible = "nvidia,tegra210-dsi"; 133 reg = <0x0 0x54400000 0x0 0x00040000>; 134 clocks = <&tegra_car TEGRA210_CLK_DSIB>, 135 <&tegra_car TEGRA210_CLK_DSIBLP>, 136 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; 137 clock-names = "dsi", "lp", "parent"; 138 resets = <&tegra_car 82>; 139 reset-names = "dsi"; 140 nvidia,mipi-calibrate = <&mipi 0x300>; /* DSIC & DSID pads */ 141 142 status = "disabled"; 143 144 #address-cells = <1>; 145 #size-cells = <0>; 146 }; 147 148 nvdec@54480000 { 149 compatible = "nvidia,tegra210-nvdec"; 150 reg = <0x0 0x54480000 0x0 0x00040000>; 151 status = "disabled"; 152 }; 153 154 nvenc@544c0000 { 155 compatible = "nvidia,tegra210-nvenc"; 156 reg = <0x0 0x544c0000 0x0 0x00040000>; 157 status = "disabled"; 158 }; 159 160 tsec@54500000 { 161 compatible = "nvidia,tegra210-tsec"; 162 reg = <0x0 0x54500000 0x0 0x00040000>; 163 status = "disabled"; 164 }; 165 166 sor@54540000 { 167 compatible = "nvidia,tegra210-sor"; 168 reg = <0x0 0x54540000 0x0 0x00040000>; 169 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 170 clocks = <&tegra_car TEGRA210_CLK_SOR0>, 171 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>, 172 <&tegra_car TEGRA210_CLK_PLL_DP>, 173 <&tegra_car TEGRA210_CLK_SOR_SAFE>; 174 clock-names = "sor", "parent", "dp", "safe"; 175 resets = <&tegra_car 182>; 176 reset-names = "sor"; 177 pinctrl-0 = <&state_dpaux_aux>; 178 pinctrl-1 = <&state_dpaux_i2c>; 179 pinctrl-2 = <&state_dpaux_off>; 180 pinctrl-names = "aux", "i2c", "off"; 181 status = "disabled"; 182 }; 183 184 sor@54580000 { 185 compatible = "nvidia,tegra210-sor1"; 186 reg = <0x0 0x54580000 0x0 0x00040000>; 187 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 188 clocks = <&tegra_car TEGRA210_CLK_SOR1>, 189 <&tegra_car TEGRA210_CLK_PLL_D2_OUT0>, 190 <&tegra_car TEGRA210_CLK_PLL_DP>, 191 <&tegra_car TEGRA210_CLK_SOR_SAFE>; 192 clock-names = "sor", "parent", "dp", "safe"; 193 resets = <&tegra_car 183>; 194 reset-names = "sor"; 195 pinctrl-0 = <&state_dpaux1_aux>; 196 pinctrl-1 = <&state_dpaux1_i2c>; 197 pinctrl-2 = <&state_dpaux1_off>; 198 pinctrl-names = "aux", "i2c", "off"; 199 status = "disabled"; 200 }; 201 202 dpaux: dpaux@545c0000 { 203 compatible = "nvidia,tegra124-dpaux"; 204 reg = <0x0 0x545c0000 0x0 0x00040000>; 205 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 206 clocks = <&tegra_car TEGRA210_CLK_DPAUX>, 207 <&tegra_car TEGRA210_CLK_PLL_DP>; 208 clock-names = "dpaux", "parent"; 209 resets = <&tegra_car 181>; 210 reset-names = "dpaux"; 211 status = "disabled"; 212 213 state_dpaux_aux: pinmux-aux { 214 groups = "dpaux-io"; 215 function = "aux"; 216 }; 217 218 state_dpaux_i2c: pinmux-i2c { 219 groups = "dpaux-io"; 220 function = "i2c"; 221 }; 222 223 state_dpaux_off: pinmux-off { 224 groups = "dpaux-io"; 225 function = "off"; 226 }; 227 228 i2c-bus { 229 #address-cells = <1>; 230 #size-cells = <0>; 231 }; 232 }; 233 234 isp@54600000 { 235 compatible = "nvidia,tegra210-isp"; 236 reg = <0x0 0x54600000 0x0 0x00040000>; 237 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 238 status = "disabled"; 239 }; 240 241 isp@54680000 { 242 compatible = "nvidia,tegra210-isp"; 243 reg = <0x0 0x54680000 0x0 0x00040000>; 244 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 245 status = "disabled"; 246 }; 247 248 i2c@546c0000 { 249 compatible = "nvidia,tegra210-i2c-vi"; 250 reg = <0x0 0x546c0000 0x0 0x00040000>; 251 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 252 status = "disabled"; 253 }; 254 }; 255 256 gic: interrupt-controller@50041000 { 257 compatible = "arm,gic-400"; 258 #interrupt-cells = <3>; 259 interrupt-controller; 260 reg = <0x0 0x50041000 0x0 0x1000>, 261 <0x0 0x50042000 0x0 0x2000>, 262 <0x0 0x50044000 0x0 0x2000>, 263 <0x0 0x50046000 0x0 0x2000>; 264 interrupts = <GIC_PPI 9 265 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 266 interrupt-parent = <&gic>; 267 }; 268 269 gpu@57000000 { 270 compatible = "nvidia,gm20b"; 271 reg = <0x0 0x57000000 0x0 0x01000000>, 272 <0x0 0x58000000 0x0 0x01000000>; 273 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 274 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 275 interrupt-names = "stall", "nonstall"; 276 clocks = <&tegra_car TEGRA210_CLK_GPU>, 277 <&tegra_car TEGRA210_CLK_PLL_P_OUT5>, 278 <&tegra_car TEGRA210_CLK_PLL_G_REF>; 279 clock-names = "gpu", "pwr", "ref"; 280 resets = <&tegra_car 184>; 281 reset-names = "gpu"; 282 283 iommus = <&mc TEGRA_SWGROUP_GPU>; 284 285 status = "disabled"; 286 }; 287 288 lic: interrupt-controller@60004000 { 289 compatible = "nvidia,tegra210-ictlr"; 290 reg = <0x0 0x60004000 0x0 0x40>, /* primary controller */ 291 <0x0 0x60004100 0x0 0x40>, /* secondary controller */ 292 <0x0 0x60004200 0x0 0x40>, /* tertiary controller */ 293 <0x0 0x60004300 0x0 0x40>, /* quaternary controller */ 294 <0x0 0x60004400 0x0 0x40>, /* quinary controller */ 295 <0x0 0x60004500 0x0 0x40>; /* senary controller */ 296 interrupt-controller; 297 #interrupt-cells = <3>; 298 interrupt-parent = <&gic>; 299 }; 300 301 timer@60005000 { 302 compatible = "nvidia,tegra210-timer", "nvidia,tegra20-timer"; 303 reg = <0x0 0x60005000 0x0 0x400>; 304 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 305 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 306 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 307 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 308 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 309 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 310 clocks = <&tegra_car TEGRA210_CLK_TIMER>; 311 clock-names = "timer"; 312 }; 313 314 tegra_car: clock@60006000 { 315 compatible = "nvidia,tegra210-car"; 316 reg = <0x0 0x60006000 0x0 0x1000>; 317 #clock-cells = <1>; 318 #reset-cells = <1>; 319 }; 320 321 flow-controller@60007000 { 322 compatible = "nvidia,tegra210-flowctrl"; 323 reg = <0x0 0x60007000 0x0 0x1000>; 324 }; 325 326 gpio: gpio@6000d000 { 327 compatible = "nvidia,tegra210-gpio", "nvidia,tegra124-gpio", "nvidia,tegra30-gpio"; 328 reg = <0x0 0x6000d000 0x0 0x1000>; 329 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 330 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 331 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 332 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 333 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 334 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 335 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 336 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 337 #gpio-cells = <2>; 338 gpio-controller; 339 #interrupt-cells = <2>; 340 interrupt-controller; 341 }; 342 343 apbdma: dma@60020000 { 344 compatible = "nvidia,tegra210-apbdma", "nvidia,tegra148-apbdma"; 345 reg = <0x0 0x60020000 0x0 0x1400>; 346 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 347 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 348 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 349 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 350 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 351 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 352 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 353 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 354 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 355 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 356 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 357 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 358 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 359 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 360 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 361 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 362 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 363 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 364 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 365 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 366 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 367 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 368 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 369 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 370 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 371 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 372 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 373 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 374 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 375 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 376 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 377 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 378 clocks = <&tegra_car TEGRA210_CLK_APBDMA>; 379 clock-names = "dma"; 380 resets = <&tegra_car 34>; 381 reset-names = "dma"; 382 #dma-cells = <1>; 383 }; 384 385 apbmisc@70000800 { 386 compatible = "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc"; 387 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */ 388 <0x0 0x7000e864 0x0 0x04>; /* Strapping options */ 389 }; 390 391 pinmux: pinmux@700008d4 { 392 compatible = "nvidia,tegra210-pinmux"; 393 reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */ 394 <0x0 0x70003000 0x0 0x294>; /* Mux registers */ 395 }; 396 397 /* 398 * There are two serial driver i.e. 8250 based simple serial 399 * driver and APB DMA based serial driver for higher baudrate 400 * and performance. To enable the 8250 based driver, the compatible 401 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable 402 * the APB DMA based serial driver, the compatible is 403 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". 404 */ 405 uarta: serial@70006000 { 406 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 407 reg = <0x0 0x70006000 0x0 0x40>; 408 reg-shift = <2>; 409 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 410 clocks = <&tegra_car TEGRA210_CLK_UARTA>; 411 clock-names = "serial"; 412 resets = <&tegra_car 6>; 413 reset-names = "serial"; 414 dmas = <&apbdma 8>, <&apbdma 8>; 415 dma-names = "rx", "tx"; 416 status = "disabled"; 417 }; 418 419 uartb: serial@70006040 { 420 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 421 reg = <0x0 0x70006040 0x0 0x40>; 422 reg-shift = <2>; 423 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 424 clocks = <&tegra_car TEGRA210_CLK_UARTB>; 425 clock-names = "serial"; 426 resets = <&tegra_car 7>; 427 reset-names = "serial"; 428 dmas = <&apbdma 9>, <&apbdma 9>; 429 dma-names = "rx", "tx"; 430 status = "disabled"; 431 }; 432 433 uartc: serial@70006200 { 434 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 435 reg = <0x0 0x70006200 0x0 0x40>; 436 reg-shift = <2>; 437 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 438 clocks = <&tegra_car TEGRA210_CLK_UARTC>; 439 clock-names = "serial"; 440 resets = <&tegra_car 55>; 441 reset-names = "serial"; 442 dmas = <&apbdma 10>, <&apbdma 10>; 443 dma-names = "rx", "tx"; 444 status = "disabled"; 445 }; 446 447 uartd: serial@70006300 { 448 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 449 reg = <0x0 0x70006300 0x0 0x40>; 450 reg-shift = <2>; 451 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 452 clocks = <&tegra_car TEGRA210_CLK_UARTD>; 453 clock-names = "serial"; 454 resets = <&tegra_car 65>; 455 reset-names = "serial"; 456 dmas = <&apbdma 19>, <&apbdma 19>; 457 dma-names = "rx", "tx"; 458 status = "disabled"; 459 }; 460 461 pwm: pwm@7000a000 { 462 compatible = "nvidia,tegra210-pwm", "nvidia,tegra20-pwm"; 463 reg = <0x0 0x7000a000 0x0 0x100>; 464 #pwm-cells = <2>; 465 clocks = <&tegra_car TEGRA210_CLK_PWM>; 466 clock-names = "pwm"; 467 resets = <&tegra_car 17>; 468 reset-names = "pwm"; 469 status = "disabled"; 470 }; 471 472 i2c@7000c000 { 473 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 474 reg = <0x0 0x7000c000 0x0 0x100>; 475 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 476 #address-cells = <1>; 477 #size-cells = <0>; 478 clocks = <&tegra_car TEGRA210_CLK_I2C1>; 479 clock-names = "div-clk"; 480 resets = <&tegra_car 12>; 481 reset-names = "i2c"; 482 dmas = <&apbdma 21>, <&apbdma 21>; 483 dma-names = "rx", "tx"; 484 status = "disabled"; 485 }; 486 487 i2c@7000c400 { 488 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 489 reg = <0x0 0x7000c400 0x0 0x100>; 490 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 491 #address-cells = <1>; 492 #size-cells = <0>; 493 clocks = <&tegra_car TEGRA210_CLK_I2C2>; 494 clock-names = "div-clk"; 495 resets = <&tegra_car 54>; 496 reset-names = "i2c"; 497 dmas = <&apbdma 22>, <&apbdma 22>; 498 dma-names = "rx", "tx"; 499 status = "disabled"; 500 }; 501 502 i2c@7000c500 { 503 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 504 reg = <0x0 0x7000c500 0x0 0x100>; 505 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 506 #address-cells = <1>; 507 #size-cells = <0>; 508 clocks = <&tegra_car TEGRA210_CLK_I2C3>; 509 clock-names = "div-clk"; 510 resets = <&tegra_car 67>; 511 reset-names = "i2c"; 512 dmas = <&apbdma 23>, <&apbdma 23>; 513 dma-names = "rx", "tx"; 514 status = "disabled"; 515 }; 516 517 i2c@7000c700 { 518 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 519 reg = <0x0 0x7000c700 0x0 0x100>; 520 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 521 #address-cells = <1>; 522 #size-cells = <0>; 523 clocks = <&tegra_car TEGRA210_CLK_I2C4>; 524 clock-names = "div-clk"; 525 resets = <&tegra_car 103>; 526 reset-names = "i2c"; 527 dmas = <&apbdma 26>, <&apbdma 26>; 528 dma-names = "rx", "tx"; 529 pinctrl-0 = <&state_dpaux1_i2c>; 530 pinctrl-1 = <&state_dpaux1_off>; 531 pinctrl-names = "default", "idle"; 532 status = "disabled"; 533 }; 534 535 i2c@7000d000 { 536 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 537 reg = <0x0 0x7000d000 0x0 0x100>; 538 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 539 #address-cells = <1>; 540 #size-cells = <0>; 541 clocks = <&tegra_car TEGRA210_CLK_I2C5>; 542 clock-names = "div-clk"; 543 resets = <&tegra_car 47>; 544 reset-names = "i2c"; 545 dmas = <&apbdma 24>, <&apbdma 24>; 546 dma-names = "rx", "tx"; 547 status = "disabled"; 548 }; 549 550 i2c@7000d100 { 551 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 552 reg = <0x0 0x7000d100 0x0 0x100>; 553 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 554 #address-cells = <1>; 555 #size-cells = <0>; 556 clocks = <&tegra_car TEGRA210_CLK_I2C6>; 557 clock-names = "div-clk"; 558 resets = <&tegra_car 166>; 559 reset-names = "i2c"; 560 dmas = <&apbdma 30>, <&apbdma 30>; 561 dma-names = "rx", "tx"; 562 pinctrl-0 = <&state_dpaux_i2c>; 563 pinctrl-1 = <&state_dpaux_off>; 564 pinctrl-names = "default", "idle"; 565 status = "disabled"; 566 }; 567 568 spi@7000d400 { 569 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 570 reg = <0x0 0x7000d400 0x0 0x200>; 571 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 572 #address-cells = <1>; 573 #size-cells = <0>; 574 clocks = <&tegra_car TEGRA210_CLK_SBC1>; 575 clock-names = "spi"; 576 resets = <&tegra_car 41>; 577 reset-names = "spi"; 578 dmas = <&apbdma 15>, <&apbdma 15>; 579 dma-names = "rx", "tx"; 580 status = "disabled"; 581 }; 582 583 spi@7000d600 { 584 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 585 reg = <0x0 0x7000d600 0x0 0x200>; 586 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 587 #address-cells = <1>; 588 #size-cells = <0>; 589 clocks = <&tegra_car TEGRA210_CLK_SBC2>; 590 clock-names = "spi"; 591 resets = <&tegra_car 44>; 592 reset-names = "spi"; 593 dmas = <&apbdma 16>, <&apbdma 16>; 594 dma-names = "rx", "tx"; 595 status = "disabled"; 596 }; 597 598 spi@7000d800 { 599 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 600 reg = <0x0 0x7000d800 0x0 0x200>; 601 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 602 #address-cells = <1>; 603 #size-cells = <0>; 604 clocks = <&tegra_car TEGRA210_CLK_SBC3>; 605 clock-names = "spi"; 606 resets = <&tegra_car 46>; 607 reset-names = "spi"; 608 dmas = <&apbdma 17>, <&apbdma 17>; 609 dma-names = "rx", "tx"; 610 status = "disabled"; 611 }; 612 613 spi@7000da00 { 614 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 615 reg = <0x0 0x7000da00 0x0 0x200>; 616 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 617 #address-cells = <1>; 618 #size-cells = <0>; 619 clocks = <&tegra_car TEGRA210_CLK_SBC4>; 620 clock-names = "spi"; 621 resets = <&tegra_car 68>; 622 reset-names = "spi"; 623 dmas = <&apbdma 18>, <&apbdma 18>; 624 dma-names = "rx", "tx"; 625 status = "disabled"; 626 }; 627 628 rtc@7000e000 { 629 compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc"; 630 reg = <0x0 0x7000e000 0x0 0x100>; 631 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 632 clocks = <&tegra_car TEGRA210_CLK_RTC>; 633 clock-names = "rtc"; 634 }; 635 636 pmc: pmc@7000e400 { 637 compatible = "nvidia,tegra210-pmc"; 638 reg = <0x0 0x7000e400 0x0 0x400>; 639 clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; 640 clock-names = "pclk", "clk32k_in"; 641 642 powergates { 643 pd_audio: aud { 644 clocks = <&tegra_car TEGRA210_CLK_APE>, 645 <&tegra_car TEGRA210_CLK_APB2APE>; 646 resets = <&tegra_car 198>; 647 #power-domain-cells = <0>; 648 }; 649 }; 650 }; 651 652 fuse@7000f800 { 653 compatible = "nvidia,tegra210-efuse"; 654 reg = <0x0 0x7000f800 0x0 0x400>; 655 clocks = <&tegra_car TEGRA210_CLK_FUSE>; 656 clock-names = "fuse"; 657 resets = <&tegra_car 39>; 658 reset-names = "fuse"; 659 }; 660 661 mc: memory-controller@70019000 { 662 compatible = "nvidia,tegra210-mc"; 663 reg = <0x0 0x70019000 0x0 0x1000>; 664 clocks = <&tegra_car TEGRA210_CLK_MC>; 665 clock-names = "mc"; 666 667 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 668 669 #iommu-cells = <1>; 670 }; 671 672 hda@70030000 { 673 compatible = "nvidia,tegra210-hda", "nvidia,tegra30-hda"; 674 reg = <0x0 0x70030000 0x0 0x10000>; 675 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 676 clocks = <&tegra_car TEGRA210_CLK_HDA>, 677 <&tegra_car TEGRA210_CLK_HDA2HDMI>, 678 <&tegra_car TEGRA210_CLK_HDA2CODEC_2X>; 679 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 680 resets = <&tegra_car 125>, /* hda */ 681 <&tegra_car 128>, /* hda2hdmi */ 682 <&tegra_car 111>; /* hda2codec_2x */ 683 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 684 status = "disabled"; 685 }; 686 687 usb@70090000 { 688 compatible = "nvidia,tegra210-xusb"; 689 reg = <0x0 0x70090000 0x0 0x8000>, 690 <0x0 0x70098000 0x0 0x1000>, 691 <0x0 0x70099000 0x0 0x1000>; 692 reg-names = "hcd", "fpci", "ipfs"; 693 694 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 695 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 696 697 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>, 698 <&tegra_car TEGRA210_CLK_XUSB_HOST_SRC>, 699 <&tegra_car TEGRA210_CLK_XUSB_FALCON_SRC>, 700 <&tegra_car TEGRA210_CLK_XUSB_SS>, 701 <&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>, 702 <&tegra_car TEGRA210_CLK_XUSB_SS_SRC>, 703 <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>, 704 <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>, 705 <&tegra_car TEGRA210_CLK_PLL_U_480M>, 706 <&tegra_car TEGRA210_CLK_CLK_M>, 707 <&tegra_car TEGRA210_CLK_PLL_E>; 708 clock-names = "xusb_host", "xusb_host_src", 709 "xusb_falcon_src", "xusb_ss", 710 "xusb_ss_div2", "xusb_ss_src", 711 "xusb_hs_src", "xusb_fs_src", 712 "pll_u_480m", "clk_m", "pll_e"; 713 resets = <&tegra_car 89>, <&tegra_car 156>, 714 <&tegra_car 143>; 715 reset-names = "xusb_host", "xusb_ss", "xusb_src"; 716 717 nvidia,xusb-padctl = <&padctl>; 718 719 status = "disabled"; 720 }; 721 722 padctl: padctl@7009f000 { 723 compatible = "nvidia,tegra210-xusb-padctl"; 724 reg = <0x0 0x7009f000 0x0 0x1000>; 725 resets = <&tegra_car 142>; 726 reset-names = "padctl"; 727 728 status = "disabled"; 729 730 pads { 731 usb2 { 732 clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>; 733 clock-names = "trk"; 734 status = "disabled"; 735 736 lanes { 737 usb2-0 { 738 status = "disabled"; 739 #phy-cells = <0>; 740 }; 741 742 usb2-1 { 743 status = "disabled"; 744 #phy-cells = <0>; 745 }; 746 747 usb2-2 { 748 status = "disabled"; 749 #phy-cells = <0>; 750 }; 751 752 usb2-3 { 753 status = "disabled"; 754 #phy-cells = <0>; 755 }; 756 }; 757 }; 758 759 hsic { 760 clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>; 761 clock-names = "trk"; 762 status = "disabled"; 763 764 lanes { 765 hsic-0 { 766 status = "disabled"; 767 #phy-cells = <0>; 768 }; 769 770 hsic-1 { 771 status = "disabled"; 772 #phy-cells = <0>; 773 }; 774 }; 775 }; 776 777 pcie { 778 clocks = <&tegra_car TEGRA210_CLK_PLL_E>; 779 clock-names = "pll"; 780 resets = <&tegra_car 205>; 781 reset-names = "phy"; 782 status = "disabled"; 783 784 lanes { 785 pcie-0 { 786 status = "disabled"; 787 #phy-cells = <0>; 788 }; 789 790 pcie-1 { 791 status = "disabled"; 792 #phy-cells = <0>; 793 }; 794 795 pcie-2 { 796 status = "disabled"; 797 #phy-cells = <0>; 798 }; 799 800 pcie-3 { 801 status = "disabled"; 802 #phy-cells = <0>; 803 }; 804 805 pcie-4 { 806 status = "disabled"; 807 #phy-cells = <0>; 808 }; 809 810 pcie-5 { 811 status = "disabled"; 812 #phy-cells = <0>; 813 }; 814 815 pcie-6 { 816 status = "disabled"; 817 #phy-cells = <0>; 818 }; 819 }; 820 }; 821 822 sata { 823 clocks = <&tegra_car TEGRA210_CLK_PLL_E>; 824 clock-names = "pll"; 825 resets = <&tegra_car 204>; 826 reset-names = "phy"; 827 status = "disabled"; 828 829 lanes { 830 sata-0 { 831 status = "disabled"; 832 #phy-cells = <0>; 833 }; 834 }; 835 }; 836 }; 837 838 ports { 839 usb2-0 { 840 status = "disabled"; 841 }; 842 843 usb2-1 { 844 status = "disabled"; 845 }; 846 847 usb2-2 { 848 status = "disabled"; 849 }; 850 851 usb2-3 { 852 status = "disabled"; 853 }; 854 855 hsic-0 { 856 status = "disabled"; 857 }; 858 859 usb3-0 { 860 status = "disabled"; 861 }; 862 863 usb3-1 { 864 status = "disabled"; 865 }; 866 867 usb3-2 { 868 status = "disabled"; 869 }; 870 871 usb3-3 { 872 status = "disabled"; 873 }; 874 }; 875 }; 876 877 sdhci@700b0000 { 878 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; 879 reg = <0x0 0x700b0000 0x0 0x200>; 880 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 881 clocks = <&tegra_car TEGRA210_CLK_SDMMC1>; 882 clock-names = "sdhci"; 883 resets = <&tegra_car 14>; 884 reset-names = "sdhci"; 885 status = "disabled"; 886 }; 887 888 sdhci@700b0200 { 889 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; 890 reg = <0x0 0x700b0200 0x0 0x200>; 891 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 892 clocks = <&tegra_car TEGRA210_CLK_SDMMC2>; 893 clock-names = "sdhci"; 894 resets = <&tegra_car 9>; 895 reset-names = "sdhci"; 896 status = "disabled"; 897 }; 898 899 sdhci@700b0400 { 900 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; 901 reg = <0x0 0x700b0400 0x0 0x200>; 902 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 903 clocks = <&tegra_car TEGRA210_CLK_SDMMC3>; 904 clock-names = "sdhci"; 905 resets = <&tegra_car 69>; 906 reset-names = "sdhci"; 907 status = "disabled"; 908 }; 909 910 sdhci@700b0600 { 911 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; 912 reg = <0x0 0x700b0600 0x0 0x200>; 913 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 914 clocks = <&tegra_car TEGRA210_CLK_SDMMC4>; 915 clock-names = "sdhci"; 916 resets = <&tegra_car 15>; 917 reset-names = "sdhci"; 918 status = "disabled"; 919 }; 920 921 mipi: mipi@700e3000 { 922 compatible = "nvidia,tegra210-mipi"; 923 reg = <0x0 0x700e3000 0x0 0x100>; 924 clocks = <&tegra_car TEGRA210_CLK_MIPI_CAL>; 925 clock-names = "mipi-cal"; 926 #nvidia,mipi-calibrate-cells = <1>; 927 }; 928 929 aconnect@702c0000 { 930 compatible = "nvidia,tegra210-aconnect"; 931 clocks = <&tegra_car TEGRA210_CLK_APE>, 932 <&tegra_car TEGRA210_CLK_APB2APE>; 933 clock-names = "ape", "apb2ape"; 934 power-domains = <&pd_audio>; 935 #address-cells = <1>; 936 #size-cells = <1>; 937 ranges = <0x702c0000 0x0 0x702c0000 0x00040000>; 938 status = "disabled"; 939 }; 940 941 spi@70410000 { 942 compatible = "nvidia,tegra210-qspi"; 943 reg = <0x0 0x70410000 0x0 0x1000>; 944 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 945 #address-cells = <1>; 946 #size-cells = <0>; 947 clocks = <&tegra_car TEGRA210_CLK_QSPI>; 948 clock-names = "qspi"; 949 resets = <&tegra_car 211>; 950 reset-names = "qspi"; 951 dmas = <&apbdma 5>, <&apbdma 5>; 952 dma-names = "rx", "tx"; 953 status = "disabled"; 954 }; 955 956 usb@7d000000 { 957 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 958 reg = <0x0 0x7d000000 0x0 0x4000>; 959 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 960 phy_type = "utmi"; 961 clocks = <&tegra_car TEGRA210_CLK_USBD>; 962 clock-names = "usb"; 963 resets = <&tegra_car 22>; 964 reset-names = "usb"; 965 nvidia,phy = <&phy1>; 966 status = "disabled"; 967 }; 968 969 phy1: usb-phy@7d000000 { 970 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; 971 reg = <0x0 0x7d000000 0x0 0x4000>, 972 <0x0 0x7d000000 0x0 0x4000>; 973 phy_type = "utmi"; 974 clocks = <&tegra_car TEGRA210_CLK_USBD>, 975 <&tegra_car TEGRA210_CLK_PLL_U>, 976 <&tegra_car TEGRA210_CLK_USBD>; 977 clock-names = "reg", "pll_u", "utmi-pads"; 978 resets = <&tegra_car 22>, <&tegra_car 22>; 979 reset-names = "usb", "utmi-pads"; 980 nvidia,hssync-start-delay = <0>; 981 nvidia,idle-wait-delay = <17>; 982 nvidia,elastic-limit = <16>; 983 nvidia,term-range-adj = <6>; 984 nvidia,xcvr-setup = <9>; 985 nvidia,xcvr-lsfslew = <0>; 986 nvidia,xcvr-lsrslew = <3>; 987 nvidia,hssquelch-level = <2>; 988 nvidia,hsdiscon-level = <5>; 989 nvidia,xcvr-hsslew = <12>; 990 nvidia,has-utmi-pad-registers; 991 status = "disabled"; 992 }; 993 994 usb@7d004000 { 995 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 996 reg = <0x0 0x7d004000 0x0 0x4000>; 997 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 998 phy_type = "utmi"; 999 clocks = <&tegra_car TEGRA210_CLK_USB2>; 1000 clock-names = "usb"; 1001 resets = <&tegra_car 58>; 1002 reset-names = "usb"; 1003 nvidia,phy = <&phy2>; 1004 status = "disabled"; 1005 }; 1006 1007 phy2: usb-phy@7d004000 { 1008 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; 1009 reg = <0x0 0x7d004000 0x0 0x4000>, 1010 <0x0 0x7d000000 0x0 0x4000>; 1011 phy_type = "utmi"; 1012 clocks = <&tegra_car TEGRA210_CLK_USB2>, 1013 <&tegra_car TEGRA210_CLK_PLL_U>, 1014 <&tegra_car TEGRA210_CLK_USBD>; 1015 clock-names = "reg", "pll_u", "utmi-pads"; 1016 resets = <&tegra_car 58>, <&tegra_car 22>; 1017 reset-names = "usb", "utmi-pads"; 1018 nvidia,hssync-start-delay = <0>; 1019 nvidia,idle-wait-delay = <17>; 1020 nvidia,elastic-limit = <16>; 1021 nvidia,term-range-adj = <6>; 1022 nvidia,xcvr-setup = <9>; 1023 nvidia,xcvr-lsfslew = <0>; 1024 nvidia,xcvr-lsrslew = <3>; 1025 nvidia,hssquelch-level = <2>; 1026 nvidia,hsdiscon-level = <5>; 1027 nvidia,xcvr-hsslew = <12>; 1028 status = "disabled"; 1029 }; 1030 1031 cpus { 1032 #address-cells = <1>; 1033 #size-cells = <0>; 1034 1035 cpu@0 { 1036 device_type = "cpu"; 1037 compatible = "arm,cortex-a57"; 1038 reg = <0>; 1039 }; 1040 1041 cpu@1 { 1042 device_type = "cpu"; 1043 compatible = "arm,cortex-a57"; 1044 reg = <1>; 1045 }; 1046 1047 cpu@2 { 1048 device_type = "cpu"; 1049 compatible = "arm,cortex-a57"; 1050 reg = <2>; 1051 }; 1052 1053 cpu@3 { 1054 device_type = "cpu"; 1055 compatible = "arm,cortex-a57"; 1056 reg = <3>; 1057 }; 1058 }; 1059 1060 timer { 1061 compatible = "arm,armv8-timer"; 1062 interrupts = <GIC_PPI 13 1063 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1064 <GIC_PPI 14 1065 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1066 <GIC_PPI 11 1067 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1068 <GIC_PPI 10 1069 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1070 interrupt-parent = <&gic>; 1071 }; 1072}; 1073