1#include <dt-bindings/clock/tegra210-car.h> 2#include <dt-bindings/gpio/tegra-gpio.h> 3#include <dt-bindings/memory/tegra210-mc.h> 4#include <dt-bindings/pinctrl/pinctrl-tegra.h> 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6#include <dt-bindings/thermal/tegra124-soctherm.h> 7 8/ { 9 compatible = "nvidia,tegra210"; 10 interrupt-parent = <&lic>; 11 #address-cells = <2>; 12 #size-cells = <2>; 13 14 pcie@1003000 { 15 compatible = "nvidia,tegra210-pcie"; 16 device_type = "pci"; 17 reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */ 18 0x0 0x01003800 0x0 0x00000800 /* AFI registers */ 19 0x0 0x02000000 0x0 0x10000000>; /* configuration space */ 20 reg-names = "pads", "afi", "cs"; 21 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 22 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 23 interrupt-names = "intr", "msi"; 24 25 #interrupt-cells = <1>; 26 interrupt-map-mask = <0 0 0 0>; 27 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 28 29 bus-range = <0x00 0xff>; 30 #address-cells = <3>; 31 #size-cells = <2>; 32 33 ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */ 34 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */ 35 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */ 36 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */ 37 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ 38 39 clocks = <&tegra_car TEGRA210_CLK_PCIE>, 40 <&tegra_car TEGRA210_CLK_AFI>, 41 <&tegra_car TEGRA210_CLK_PLL_E>, 42 <&tegra_car TEGRA210_CLK_CML0>; 43 clock-names = "pex", "afi", "pll_e", "cml"; 44 resets = <&tegra_car 70>, 45 <&tegra_car 72>, 46 <&tegra_car 74>; 47 reset-names = "pex", "afi", "pcie_x"; 48 status = "disabled"; 49 50 pci@1,0 { 51 device_type = "pci"; 52 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>; 53 reg = <0x000800 0 0 0 0>; 54 bus-range = <0x00 0xff>; 55 status = "disabled"; 56 57 #address-cells = <3>; 58 #size-cells = <2>; 59 ranges; 60 61 nvidia,num-lanes = <4>; 62 }; 63 64 pci@2,0 { 65 device_type = "pci"; 66 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>; 67 reg = <0x001000 0 0 0 0>; 68 bus-range = <0x00 0xff>; 69 status = "disabled"; 70 71 #address-cells = <3>; 72 #size-cells = <2>; 73 ranges; 74 75 nvidia,num-lanes = <1>; 76 }; 77 }; 78 79 host1x@50000000 { 80 compatible = "nvidia,tegra210-host1x", "simple-bus"; 81 reg = <0x0 0x50000000 0x0 0x00034000>; 82 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 83 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ 84 clocks = <&tegra_car TEGRA210_CLK_HOST1X>; 85 clock-names = "host1x"; 86 resets = <&tegra_car 28>; 87 reset-names = "host1x"; 88 89 #address-cells = <2>; 90 #size-cells = <2>; 91 92 ranges = <0x0 0x54000000 0x0 0x54000000 0x0 0x01000000>; 93 94 iommus = <&mc TEGRA_SWGROUP_HC>; 95 96 dpaux1: dpaux@54040000 { 97 compatible = "nvidia,tegra210-dpaux"; 98 reg = <0x0 0x54040000 0x0 0x00040000>; 99 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 100 clocks = <&tegra_car TEGRA210_CLK_DPAUX1>, 101 <&tegra_car TEGRA210_CLK_PLL_DP>; 102 clock-names = "dpaux", "parent"; 103 resets = <&tegra_car 207>; 104 reset-names = "dpaux"; 105 power-domains = <&pd_sor>; 106 status = "disabled"; 107 108 state_dpaux1_aux: pinmux-aux { 109 groups = "dpaux-io"; 110 function = "aux"; 111 }; 112 113 state_dpaux1_i2c: pinmux-i2c { 114 groups = "dpaux-io"; 115 function = "i2c"; 116 }; 117 118 state_dpaux1_off: pinmux-off { 119 groups = "dpaux-io"; 120 function = "off"; 121 }; 122 123 i2c-bus { 124 #address-cells = <1>; 125 #size-cells = <0>; 126 }; 127 }; 128 129 vi@54080000 { 130 compatible = "nvidia,tegra210-vi"; 131 reg = <0x0 0x54080000 0x0 0x00040000>; 132 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 133 status = "disabled"; 134 }; 135 136 tsec@54100000 { 137 compatible = "nvidia,tegra210-tsec"; 138 reg = <0x0 0x54100000 0x0 0x00040000>; 139 }; 140 141 dc@54200000 { 142 compatible = "nvidia,tegra210-dc"; 143 reg = <0x0 0x54200000 0x0 0x00040000>; 144 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 145 clocks = <&tegra_car TEGRA210_CLK_DISP1>, 146 <&tegra_car TEGRA210_CLK_PLL_P>; 147 clock-names = "dc", "parent"; 148 resets = <&tegra_car 27>; 149 reset-names = "dc"; 150 151 iommus = <&mc TEGRA_SWGROUP_DC>; 152 153 nvidia,head = <0>; 154 }; 155 156 dc@54240000 { 157 compatible = "nvidia,tegra210-dc"; 158 reg = <0x0 0x54240000 0x0 0x00040000>; 159 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 160 clocks = <&tegra_car TEGRA210_CLK_DISP2>, 161 <&tegra_car TEGRA210_CLK_PLL_P>; 162 clock-names = "dc", "parent"; 163 resets = <&tegra_car 26>; 164 reset-names = "dc"; 165 166 iommus = <&mc TEGRA_SWGROUP_DCB>; 167 168 nvidia,head = <1>; 169 }; 170 171 dsi@54300000 { 172 compatible = "nvidia,tegra210-dsi"; 173 reg = <0x0 0x54300000 0x0 0x00040000>; 174 clocks = <&tegra_car TEGRA210_CLK_DSIA>, 175 <&tegra_car TEGRA210_CLK_DSIALP>, 176 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; 177 clock-names = "dsi", "lp", "parent"; 178 resets = <&tegra_car 48>; 179 reset-names = "dsi"; 180 power-domains = <&pd_sor>; 181 nvidia,mipi-calibrate = <&mipi 0x0c0>; /* DSIA & DSIB pads */ 182 183 status = "disabled"; 184 185 #address-cells = <1>; 186 #size-cells = <0>; 187 }; 188 189 vic@54340000 { 190 compatible = "nvidia,tegra210-vic"; 191 reg = <0x0 0x54340000 0x0 0x00040000>; 192 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 193 clocks = <&tegra_car TEGRA210_CLK_VIC03>; 194 clock-names = "vic"; 195 resets = <&tegra_car 178>; 196 reset-names = "vic"; 197 198 iommus = <&mc TEGRA_SWGROUP_VIC>; 199 power-domains = <&pd_vic>; 200 }; 201 202 nvjpg@54380000 { 203 compatible = "nvidia,tegra210-nvjpg"; 204 reg = <0x0 0x54380000 0x0 0x00040000>; 205 status = "disabled"; 206 }; 207 208 dsi@54400000 { 209 compatible = "nvidia,tegra210-dsi"; 210 reg = <0x0 0x54400000 0x0 0x00040000>; 211 clocks = <&tegra_car TEGRA210_CLK_DSIB>, 212 <&tegra_car TEGRA210_CLK_DSIBLP>, 213 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; 214 clock-names = "dsi", "lp", "parent"; 215 resets = <&tegra_car 82>; 216 reset-names = "dsi"; 217 power-domains = <&pd_sor>; 218 nvidia,mipi-calibrate = <&mipi 0x300>; /* DSIC & DSID pads */ 219 220 status = "disabled"; 221 222 #address-cells = <1>; 223 #size-cells = <0>; 224 }; 225 226 nvdec@54480000 { 227 compatible = "nvidia,tegra210-nvdec"; 228 reg = <0x0 0x54480000 0x0 0x00040000>; 229 status = "disabled"; 230 }; 231 232 nvenc@544c0000 { 233 compatible = "nvidia,tegra210-nvenc"; 234 reg = <0x0 0x544c0000 0x0 0x00040000>; 235 status = "disabled"; 236 }; 237 238 tsec@54500000 { 239 compatible = "nvidia,tegra210-tsec"; 240 reg = <0x0 0x54500000 0x0 0x00040000>; 241 status = "disabled"; 242 }; 243 244 sor@54540000 { 245 compatible = "nvidia,tegra210-sor"; 246 reg = <0x0 0x54540000 0x0 0x00040000>; 247 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 248 clocks = <&tegra_car TEGRA210_CLK_SOR0>, 249 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>, 250 <&tegra_car TEGRA210_CLK_PLL_DP>, 251 <&tegra_car TEGRA210_CLK_SOR_SAFE>; 252 clock-names = "sor", "parent", "dp", "safe"; 253 resets = <&tegra_car 182>; 254 reset-names = "sor"; 255 pinctrl-0 = <&state_dpaux_aux>; 256 pinctrl-1 = <&state_dpaux_i2c>; 257 pinctrl-2 = <&state_dpaux_off>; 258 pinctrl-names = "aux", "i2c", "off"; 259 power-domains = <&pd_sor>; 260 status = "disabled"; 261 }; 262 263 sor@54580000 { 264 compatible = "nvidia,tegra210-sor1"; 265 reg = <0x0 0x54580000 0x0 0x00040000>; 266 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 267 clocks = <&tegra_car TEGRA210_CLK_SOR1>, 268 <&tegra_car TEGRA210_CLK_SOR1_SRC>, 269 <&tegra_car TEGRA210_CLK_PLL_D2_OUT0>, 270 <&tegra_car TEGRA210_CLK_PLL_DP>, 271 <&tegra_car TEGRA210_CLK_SOR_SAFE>; 272 clock-names = "sor", "source", "parent", "dp", "safe"; 273 resets = <&tegra_car 183>; 274 reset-names = "sor"; 275 pinctrl-0 = <&state_dpaux1_aux>; 276 pinctrl-1 = <&state_dpaux1_i2c>; 277 pinctrl-2 = <&state_dpaux1_off>; 278 pinctrl-names = "aux", "i2c", "off"; 279 power-domains = <&pd_sor>; 280 status = "disabled"; 281 }; 282 283 dpaux: dpaux@545c0000 { 284 compatible = "nvidia,tegra124-dpaux"; 285 reg = <0x0 0x545c0000 0x0 0x00040000>; 286 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 287 clocks = <&tegra_car TEGRA210_CLK_DPAUX>, 288 <&tegra_car TEGRA210_CLK_PLL_DP>; 289 clock-names = "dpaux", "parent"; 290 resets = <&tegra_car 181>; 291 reset-names = "dpaux"; 292 power-domains = <&pd_sor>; 293 status = "disabled"; 294 295 state_dpaux_aux: pinmux-aux { 296 groups = "dpaux-io"; 297 function = "aux"; 298 }; 299 300 state_dpaux_i2c: pinmux-i2c { 301 groups = "dpaux-io"; 302 function = "i2c"; 303 }; 304 305 state_dpaux_off: pinmux-off { 306 groups = "dpaux-io"; 307 function = "off"; 308 }; 309 310 i2c-bus { 311 #address-cells = <1>; 312 #size-cells = <0>; 313 }; 314 }; 315 316 isp@54600000 { 317 compatible = "nvidia,tegra210-isp"; 318 reg = <0x0 0x54600000 0x0 0x00040000>; 319 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 320 status = "disabled"; 321 }; 322 323 isp@54680000 { 324 compatible = "nvidia,tegra210-isp"; 325 reg = <0x0 0x54680000 0x0 0x00040000>; 326 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 327 status = "disabled"; 328 }; 329 330 i2c@546c0000 { 331 compatible = "nvidia,tegra210-i2c-vi"; 332 reg = <0x0 0x546c0000 0x0 0x00040000>; 333 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 334 status = "disabled"; 335 }; 336 }; 337 338 gic: interrupt-controller@50041000 { 339 compatible = "arm,gic-400"; 340 #interrupt-cells = <3>; 341 interrupt-controller; 342 reg = <0x0 0x50041000 0x0 0x1000>, 343 <0x0 0x50042000 0x0 0x2000>, 344 <0x0 0x50044000 0x0 0x2000>, 345 <0x0 0x50046000 0x0 0x2000>; 346 interrupts = <GIC_PPI 9 347 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 348 interrupt-parent = <&gic>; 349 }; 350 351 gpu@57000000 { 352 compatible = "nvidia,gm20b"; 353 reg = <0x0 0x57000000 0x0 0x01000000>, 354 <0x0 0x58000000 0x0 0x01000000>; 355 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 356 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 357 interrupt-names = "stall", "nonstall"; 358 clocks = <&tegra_car TEGRA210_CLK_GPU>, 359 <&tegra_car TEGRA210_CLK_PLL_P_OUT5>, 360 <&tegra_car TEGRA210_CLK_PLL_G_REF>; 361 clock-names = "gpu", "pwr", "ref"; 362 resets = <&tegra_car 184>; 363 reset-names = "gpu"; 364 365 iommus = <&mc TEGRA_SWGROUP_GPU>; 366 367 status = "disabled"; 368 }; 369 370 lic: interrupt-controller@60004000 { 371 compatible = "nvidia,tegra210-ictlr"; 372 reg = <0x0 0x60004000 0x0 0x40>, /* primary controller */ 373 <0x0 0x60004100 0x0 0x40>, /* secondary controller */ 374 <0x0 0x60004200 0x0 0x40>, /* tertiary controller */ 375 <0x0 0x60004300 0x0 0x40>, /* quaternary controller */ 376 <0x0 0x60004400 0x0 0x40>, /* quinary controller */ 377 <0x0 0x60004500 0x0 0x40>; /* senary controller */ 378 interrupt-controller; 379 #interrupt-cells = <3>; 380 interrupt-parent = <&gic>; 381 }; 382 383 timer@60005000 { 384 compatible = "nvidia,tegra210-timer", "nvidia,tegra20-timer"; 385 reg = <0x0 0x60005000 0x0 0x400>; 386 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 387 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 388 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 389 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 390 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 391 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 392 clocks = <&tegra_car TEGRA210_CLK_TIMER>; 393 clock-names = "timer"; 394 }; 395 396 tegra_car: clock@60006000 { 397 compatible = "nvidia,tegra210-car"; 398 reg = <0x0 0x60006000 0x0 0x1000>; 399 #clock-cells = <1>; 400 #reset-cells = <1>; 401 }; 402 403 flow-controller@60007000 { 404 compatible = "nvidia,tegra210-flowctrl"; 405 reg = <0x0 0x60007000 0x0 0x1000>; 406 }; 407 408 gpio: gpio@6000d000 { 409 compatible = "nvidia,tegra210-gpio", "nvidia,tegra30-gpio"; 410 reg = <0x0 0x6000d000 0x0 0x1000>; 411 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 412 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 413 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 414 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 415 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 416 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 417 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 418 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 419 #gpio-cells = <2>; 420 gpio-controller; 421 #interrupt-cells = <2>; 422 interrupt-controller; 423 }; 424 425 apbdma: dma@60020000 { 426 compatible = "nvidia,tegra210-apbdma", "nvidia,tegra148-apbdma"; 427 reg = <0x0 0x60020000 0x0 0x1400>; 428 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 429 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 430 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 431 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 432 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 433 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 434 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 435 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 436 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 437 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 438 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 439 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 440 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 441 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 442 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 443 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 444 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 445 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 446 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 447 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 448 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 449 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 450 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 451 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 452 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 453 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 454 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 455 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 456 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 457 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 458 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 459 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 460 clocks = <&tegra_car TEGRA210_CLK_APBDMA>; 461 clock-names = "dma"; 462 resets = <&tegra_car 34>; 463 reset-names = "dma"; 464 #dma-cells = <1>; 465 }; 466 467 apbmisc@70000800 { 468 compatible = "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc"; 469 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */ 470 <0x0 0x7000e864 0x0 0x04>; /* Strapping options */ 471 }; 472 473 pinmux: pinmux@700008d4 { 474 compatible = "nvidia,tegra210-pinmux"; 475 reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */ 476 <0x0 0x70003000 0x0 0x294>; /* Mux registers */ 477 }; 478 479 /* 480 * There are two serial driver i.e. 8250 based simple serial 481 * driver and APB DMA based serial driver for higher baudrate 482 * and performance. To enable the 8250 based driver, the compatible 483 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable 484 * the APB DMA based serial driver, the compatible is 485 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". 486 */ 487 uarta: serial@70006000 { 488 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 489 reg = <0x0 0x70006000 0x0 0x40>; 490 reg-shift = <2>; 491 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 492 clocks = <&tegra_car TEGRA210_CLK_UARTA>; 493 clock-names = "serial"; 494 resets = <&tegra_car 6>; 495 reset-names = "serial"; 496 dmas = <&apbdma 8>, <&apbdma 8>; 497 dma-names = "rx", "tx"; 498 status = "disabled"; 499 }; 500 501 uartb: serial@70006040 { 502 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 503 reg = <0x0 0x70006040 0x0 0x40>; 504 reg-shift = <2>; 505 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 506 clocks = <&tegra_car TEGRA210_CLK_UARTB>; 507 clock-names = "serial"; 508 resets = <&tegra_car 7>; 509 reset-names = "serial"; 510 dmas = <&apbdma 9>, <&apbdma 9>; 511 dma-names = "rx", "tx"; 512 status = "disabled"; 513 }; 514 515 uartc: serial@70006200 { 516 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 517 reg = <0x0 0x70006200 0x0 0x40>; 518 reg-shift = <2>; 519 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 520 clocks = <&tegra_car TEGRA210_CLK_UARTC>; 521 clock-names = "serial"; 522 resets = <&tegra_car 55>; 523 reset-names = "serial"; 524 dmas = <&apbdma 10>, <&apbdma 10>; 525 dma-names = "rx", "tx"; 526 status = "disabled"; 527 }; 528 529 uartd: serial@70006300 { 530 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 531 reg = <0x0 0x70006300 0x0 0x40>; 532 reg-shift = <2>; 533 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 534 clocks = <&tegra_car TEGRA210_CLK_UARTD>; 535 clock-names = "serial"; 536 resets = <&tegra_car 65>; 537 reset-names = "serial"; 538 dmas = <&apbdma 19>, <&apbdma 19>; 539 dma-names = "rx", "tx"; 540 status = "disabled"; 541 }; 542 543 pwm: pwm@7000a000 { 544 compatible = "nvidia,tegra210-pwm", "nvidia,tegra20-pwm"; 545 reg = <0x0 0x7000a000 0x0 0x100>; 546 #pwm-cells = <2>; 547 clocks = <&tegra_car TEGRA210_CLK_PWM>; 548 clock-names = "pwm"; 549 resets = <&tegra_car 17>; 550 reset-names = "pwm"; 551 status = "disabled"; 552 }; 553 554 i2c@7000c000 { 555 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 556 reg = <0x0 0x7000c000 0x0 0x100>; 557 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 558 #address-cells = <1>; 559 #size-cells = <0>; 560 clocks = <&tegra_car TEGRA210_CLK_I2C1>; 561 clock-names = "div-clk"; 562 resets = <&tegra_car 12>; 563 reset-names = "i2c"; 564 dmas = <&apbdma 21>, <&apbdma 21>; 565 dma-names = "rx", "tx"; 566 status = "disabled"; 567 }; 568 569 i2c@7000c400 { 570 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 571 reg = <0x0 0x7000c400 0x0 0x100>; 572 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 573 #address-cells = <1>; 574 #size-cells = <0>; 575 clocks = <&tegra_car TEGRA210_CLK_I2C2>; 576 clock-names = "div-clk"; 577 resets = <&tegra_car 54>; 578 reset-names = "i2c"; 579 dmas = <&apbdma 22>, <&apbdma 22>; 580 dma-names = "rx", "tx"; 581 status = "disabled"; 582 }; 583 584 i2c@7000c500 { 585 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 586 reg = <0x0 0x7000c500 0x0 0x100>; 587 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 588 #address-cells = <1>; 589 #size-cells = <0>; 590 clocks = <&tegra_car TEGRA210_CLK_I2C3>; 591 clock-names = "div-clk"; 592 resets = <&tegra_car 67>; 593 reset-names = "i2c"; 594 dmas = <&apbdma 23>, <&apbdma 23>; 595 dma-names = "rx", "tx"; 596 status = "disabled"; 597 }; 598 599 i2c@7000c700 { 600 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 601 reg = <0x0 0x7000c700 0x0 0x100>; 602 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 603 #address-cells = <1>; 604 #size-cells = <0>; 605 clocks = <&tegra_car TEGRA210_CLK_I2C4>; 606 clock-names = "div-clk"; 607 resets = <&tegra_car 103>; 608 reset-names = "i2c"; 609 dmas = <&apbdma 26>, <&apbdma 26>; 610 dma-names = "rx", "tx"; 611 pinctrl-0 = <&state_dpaux1_i2c>; 612 pinctrl-1 = <&state_dpaux1_off>; 613 pinctrl-names = "default", "idle"; 614 status = "disabled"; 615 }; 616 617 i2c@7000d000 { 618 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 619 reg = <0x0 0x7000d000 0x0 0x100>; 620 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 621 #address-cells = <1>; 622 #size-cells = <0>; 623 clocks = <&tegra_car TEGRA210_CLK_I2C5>; 624 clock-names = "div-clk"; 625 resets = <&tegra_car 47>; 626 reset-names = "i2c"; 627 dmas = <&apbdma 24>, <&apbdma 24>; 628 dma-names = "rx", "tx"; 629 status = "disabled"; 630 }; 631 632 i2c@7000d100 { 633 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 634 reg = <0x0 0x7000d100 0x0 0x100>; 635 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 636 #address-cells = <1>; 637 #size-cells = <0>; 638 clocks = <&tegra_car TEGRA210_CLK_I2C6>; 639 clock-names = "div-clk"; 640 resets = <&tegra_car 166>; 641 reset-names = "i2c"; 642 dmas = <&apbdma 30>, <&apbdma 30>; 643 dma-names = "rx", "tx"; 644 pinctrl-0 = <&state_dpaux_i2c>; 645 pinctrl-1 = <&state_dpaux_off>; 646 pinctrl-names = "default", "idle"; 647 status = "disabled"; 648 }; 649 650 spi@7000d400 { 651 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 652 reg = <0x0 0x7000d400 0x0 0x200>; 653 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 654 #address-cells = <1>; 655 #size-cells = <0>; 656 clocks = <&tegra_car TEGRA210_CLK_SBC1>; 657 clock-names = "spi"; 658 resets = <&tegra_car 41>; 659 reset-names = "spi"; 660 dmas = <&apbdma 15>, <&apbdma 15>; 661 dma-names = "rx", "tx"; 662 status = "disabled"; 663 }; 664 665 spi@7000d600 { 666 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 667 reg = <0x0 0x7000d600 0x0 0x200>; 668 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 669 #address-cells = <1>; 670 #size-cells = <0>; 671 clocks = <&tegra_car TEGRA210_CLK_SBC2>; 672 clock-names = "spi"; 673 resets = <&tegra_car 44>; 674 reset-names = "spi"; 675 dmas = <&apbdma 16>, <&apbdma 16>; 676 dma-names = "rx", "tx"; 677 status = "disabled"; 678 }; 679 680 spi@7000d800 { 681 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 682 reg = <0x0 0x7000d800 0x0 0x200>; 683 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 684 #address-cells = <1>; 685 #size-cells = <0>; 686 clocks = <&tegra_car TEGRA210_CLK_SBC3>; 687 clock-names = "spi"; 688 resets = <&tegra_car 46>; 689 reset-names = "spi"; 690 dmas = <&apbdma 17>, <&apbdma 17>; 691 dma-names = "rx", "tx"; 692 status = "disabled"; 693 }; 694 695 spi@7000da00 { 696 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 697 reg = <0x0 0x7000da00 0x0 0x200>; 698 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 699 #address-cells = <1>; 700 #size-cells = <0>; 701 clocks = <&tegra_car TEGRA210_CLK_SBC4>; 702 clock-names = "spi"; 703 resets = <&tegra_car 68>; 704 reset-names = "spi"; 705 dmas = <&apbdma 18>, <&apbdma 18>; 706 dma-names = "rx", "tx"; 707 status = "disabled"; 708 }; 709 710 rtc@7000e000 { 711 compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc"; 712 reg = <0x0 0x7000e000 0x0 0x100>; 713 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 714 clocks = <&tegra_car TEGRA210_CLK_RTC>; 715 clock-names = "rtc"; 716 }; 717 718 pmc: pmc@7000e400 { 719 compatible = "nvidia,tegra210-pmc"; 720 reg = <0x0 0x7000e400 0x0 0x400>; 721 clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; 722 clock-names = "pclk", "clk32k_in"; 723 724 powergates { 725 pd_audio: aud { 726 clocks = <&tegra_car TEGRA210_CLK_APE>, 727 <&tegra_car TEGRA210_CLK_APB2APE>; 728 resets = <&tegra_car 198>; 729 #power-domain-cells = <0>; 730 }; 731 732 pd_sor: sor { 733 clocks = <&tegra_car TEGRA210_CLK_SOR0>, 734 <&tegra_car TEGRA210_CLK_SOR1>, 735 <&tegra_car TEGRA210_CLK_CSI>, 736 <&tegra_car TEGRA210_CLK_DSIA>, 737 <&tegra_car TEGRA210_CLK_DSIB>, 738 <&tegra_car TEGRA210_CLK_DPAUX>, 739 <&tegra_car TEGRA210_CLK_DPAUX1>, 740 <&tegra_car TEGRA210_CLK_MIPI_CAL>; 741 resets = <&tegra_car TEGRA210_CLK_SOR0>, 742 <&tegra_car TEGRA210_CLK_SOR1>, 743 <&tegra_car TEGRA210_CLK_CSI>, 744 <&tegra_car TEGRA210_CLK_DSIA>, 745 <&tegra_car TEGRA210_CLK_DSIB>, 746 <&tegra_car TEGRA210_CLK_DPAUX>, 747 <&tegra_car TEGRA210_CLK_DPAUX1>, 748 <&tegra_car TEGRA210_CLK_MIPI_CAL>; 749 #power-domain-cells = <0>; 750 }; 751 752 pd_xusbss: xusba { 753 clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>; 754 resets = <&tegra_car TEGRA210_CLK_XUSB_SS>; 755 #power-domain-cells = <0>; 756 }; 757 758 pd_xusbdev: xusbb { 759 clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>; 760 resets = <&tegra_car 95>; 761 #power-domain-cells = <0>; 762 }; 763 764 pd_xusbhost: xusbc { 765 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>; 766 resets = <&tegra_car TEGRA210_CLK_XUSB_HOST>; 767 #power-domain-cells = <0>; 768 }; 769 770 pd_vic: vic { 771 clocks = <&tegra_car TEGRA210_CLK_VIC03>; 772 clock-names = "vic"; 773 resets = <&tegra_car 178>; 774 reset-names = "vic"; 775 #power-domain-cells = <0>; 776 }; 777 }; 778 }; 779 780 fuse@7000f800 { 781 compatible = "nvidia,tegra210-efuse"; 782 reg = <0x0 0x7000f800 0x0 0x400>; 783 clocks = <&tegra_car TEGRA210_CLK_FUSE>; 784 clock-names = "fuse"; 785 resets = <&tegra_car 39>; 786 reset-names = "fuse"; 787 }; 788 789 mc: memory-controller@70019000 { 790 compatible = "nvidia,tegra210-mc"; 791 reg = <0x0 0x70019000 0x0 0x1000>; 792 clocks = <&tegra_car TEGRA210_CLK_MC>; 793 clock-names = "mc"; 794 795 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 796 797 #iommu-cells = <1>; 798 }; 799 800 hda@70030000 { 801 compatible = "nvidia,tegra210-hda", "nvidia,tegra30-hda"; 802 reg = <0x0 0x70030000 0x0 0x10000>; 803 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 804 clocks = <&tegra_car TEGRA210_CLK_HDA>, 805 <&tegra_car TEGRA210_CLK_HDA2HDMI>, 806 <&tegra_car TEGRA210_CLK_HDA2CODEC_2X>; 807 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 808 resets = <&tegra_car 125>, /* hda */ 809 <&tegra_car 128>, /* hda2hdmi */ 810 <&tegra_car 111>; /* hda2codec_2x */ 811 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 812 status = "disabled"; 813 }; 814 815 usb@70090000 { 816 compatible = "nvidia,tegra210-xusb"; 817 reg = <0x0 0x70090000 0x0 0x8000>, 818 <0x0 0x70098000 0x0 0x1000>, 819 <0x0 0x70099000 0x0 0x1000>; 820 reg-names = "hcd", "fpci", "ipfs"; 821 822 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 823 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 824 825 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>, 826 <&tegra_car TEGRA210_CLK_XUSB_HOST_SRC>, 827 <&tegra_car TEGRA210_CLK_XUSB_FALCON_SRC>, 828 <&tegra_car TEGRA210_CLK_XUSB_SS>, 829 <&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>, 830 <&tegra_car TEGRA210_CLK_XUSB_SS_SRC>, 831 <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>, 832 <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>, 833 <&tegra_car TEGRA210_CLK_PLL_U_480M>, 834 <&tegra_car TEGRA210_CLK_CLK_M>, 835 <&tegra_car TEGRA210_CLK_PLL_E>; 836 clock-names = "xusb_host", "xusb_host_src", 837 "xusb_falcon_src", "xusb_ss", 838 "xusb_ss_div2", "xusb_ss_src", 839 "xusb_hs_src", "xusb_fs_src", 840 "pll_u_480m", "clk_m", "pll_e"; 841 resets = <&tegra_car 89>, <&tegra_car 156>, 842 <&tegra_car 143>; 843 reset-names = "xusb_host", "xusb_ss", "xusb_src"; 844 845 nvidia,xusb-padctl = <&padctl>; 846 847 status = "disabled"; 848 }; 849 850 padctl: padctl@7009f000 { 851 compatible = "nvidia,tegra210-xusb-padctl"; 852 reg = <0x0 0x7009f000 0x0 0x1000>; 853 resets = <&tegra_car 142>; 854 reset-names = "padctl"; 855 856 status = "disabled"; 857 858 pads { 859 usb2 { 860 clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>; 861 clock-names = "trk"; 862 status = "disabled"; 863 864 lanes { 865 usb2-0 { 866 status = "disabled"; 867 #phy-cells = <0>; 868 }; 869 870 usb2-1 { 871 status = "disabled"; 872 #phy-cells = <0>; 873 }; 874 875 usb2-2 { 876 status = "disabled"; 877 #phy-cells = <0>; 878 }; 879 880 usb2-3 { 881 status = "disabled"; 882 #phy-cells = <0>; 883 }; 884 }; 885 }; 886 887 hsic { 888 clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>; 889 clock-names = "trk"; 890 status = "disabled"; 891 892 lanes { 893 hsic-0 { 894 status = "disabled"; 895 #phy-cells = <0>; 896 }; 897 898 hsic-1 { 899 status = "disabled"; 900 #phy-cells = <0>; 901 }; 902 }; 903 }; 904 905 pcie { 906 clocks = <&tegra_car TEGRA210_CLK_PLL_E>; 907 clock-names = "pll"; 908 resets = <&tegra_car 205>; 909 reset-names = "phy"; 910 status = "disabled"; 911 912 lanes { 913 pcie-0 { 914 status = "disabled"; 915 #phy-cells = <0>; 916 }; 917 918 pcie-1 { 919 status = "disabled"; 920 #phy-cells = <0>; 921 }; 922 923 pcie-2 { 924 status = "disabled"; 925 #phy-cells = <0>; 926 }; 927 928 pcie-3 { 929 status = "disabled"; 930 #phy-cells = <0>; 931 }; 932 933 pcie-4 { 934 status = "disabled"; 935 #phy-cells = <0>; 936 }; 937 938 pcie-5 { 939 status = "disabled"; 940 #phy-cells = <0>; 941 }; 942 943 pcie-6 { 944 status = "disabled"; 945 #phy-cells = <0>; 946 }; 947 }; 948 }; 949 950 sata { 951 clocks = <&tegra_car TEGRA210_CLK_PLL_E>; 952 clock-names = "pll"; 953 resets = <&tegra_car 204>; 954 reset-names = "phy"; 955 status = "disabled"; 956 957 lanes { 958 sata-0 { 959 status = "disabled"; 960 #phy-cells = <0>; 961 }; 962 }; 963 }; 964 }; 965 966 ports { 967 usb2-0 { 968 status = "disabled"; 969 }; 970 971 usb2-1 { 972 status = "disabled"; 973 }; 974 975 usb2-2 { 976 status = "disabled"; 977 }; 978 979 usb2-3 { 980 status = "disabled"; 981 }; 982 983 hsic-0 { 984 status = "disabled"; 985 }; 986 987 usb3-0 { 988 status = "disabled"; 989 }; 990 991 usb3-1 { 992 status = "disabled"; 993 }; 994 995 usb3-2 { 996 status = "disabled"; 997 }; 998 999 usb3-3 { 1000 status = "disabled"; 1001 }; 1002 }; 1003 }; 1004 1005 sdhci@700b0000 { 1006 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; 1007 reg = <0x0 0x700b0000 0x0 0x200>; 1008 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1009 clocks = <&tegra_car TEGRA210_CLK_SDMMC1>; 1010 clock-names = "sdhci"; 1011 resets = <&tegra_car 14>; 1012 reset-names = "sdhci"; 1013 status = "disabled"; 1014 }; 1015 1016 sdhci@700b0200 { 1017 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; 1018 reg = <0x0 0x700b0200 0x0 0x200>; 1019 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 1020 clocks = <&tegra_car TEGRA210_CLK_SDMMC2>; 1021 clock-names = "sdhci"; 1022 resets = <&tegra_car 9>; 1023 reset-names = "sdhci"; 1024 status = "disabled"; 1025 }; 1026 1027 sdhci@700b0400 { 1028 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; 1029 reg = <0x0 0x700b0400 0x0 0x200>; 1030 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 1031 clocks = <&tegra_car TEGRA210_CLK_SDMMC3>; 1032 clock-names = "sdhci"; 1033 resets = <&tegra_car 69>; 1034 reset-names = "sdhci"; 1035 status = "disabled"; 1036 }; 1037 1038 sdhci@700b0600 { 1039 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; 1040 reg = <0x0 0x700b0600 0x0 0x200>; 1041 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1042 clocks = <&tegra_car TEGRA210_CLK_SDMMC4>; 1043 clock-names = "sdhci"; 1044 resets = <&tegra_car 15>; 1045 reset-names = "sdhci"; 1046 status = "disabled"; 1047 }; 1048 1049 mipi: mipi@700e3000 { 1050 compatible = "nvidia,tegra210-mipi"; 1051 reg = <0x0 0x700e3000 0x0 0x100>; 1052 clocks = <&tegra_car TEGRA210_CLK_MIPI_CAL>; 1053 clock-names = "mipi-cal"; 1054 power-domains = <&pd_sor>; 1055 #nvidia,mipi-calibrate-cells = <1>; 1056 }; 1057 1058 aconnect@702c0000 { 1059 compatible = "nvidia,tegra210-aconnect"; 1060 clocks = <&tegra_car TEGRA210_CLK_APE>, 1061 <&tegra_car TEGRA210_CLK_APB2APE>; 1062 clock-names = "ape", "apb2ape"; 1063 power-domains = <&pd_audio>; 1064 #address-cells = <1>; 1065 #size-cells = <1>; 1066 ranges = <0x702c0000 0x0 0x702c0000 0x00040000>; 1067 status = "disabled"; 1068 1069 adma: dma@702e2000 { 1070 compatible = "nvidia,tegra210-adma"; 1071 reg = <0x702e2000 0x2000>; 1072 interrupt-parent = <&agic>; 1073 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 1074 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 1075 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 1076 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 1077 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 1078 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 1079 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 1080 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 1081 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 1082 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 1083 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 1084 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 1085 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 1086 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 1087 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 1088 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 1089 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 1090 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 1091 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 1092 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 1093 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 1094 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1095 #dma-cells = <1>; 1096 clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>; 1097 clock-names = "d_audio"; 1098 status = "disabled"; 1099 }; 1100 1101 agic: agic@702f9000 { 1102 compatible = "nvidia,tegra210-agic"; 1103 #interrupt-cells = <3>; 1104 interrupt-controller; 1105 reg = <0x702f9000 0x2000>, 1106 <0x702fa000 0x2000>; 1107 interrupts = <GIC_SPI 102 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1108 clocks = <&tegra_car TEGRA210_CLK_APE>; 1109 clock-names = "clk"; 1110 status = "disabled"; 1111 }; 1112 }; 1113 1114 spi@70410000 { 1115 compatible = "nvidia,tegra210-qspi"; 1116 reg = <0x0 0x70410000 0x0 0x1000>; 1117 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1118 #address-cells = <1>; 1119 #size-cells = <0>; 1120 clocks = <&tegra_car TEGRA210_CLK_QSPI>; 1121 clock-names = "qspi"; 1122 resets = <&tegra_car 211>; 1123 reset-names = "qspi"; 1124 dmas = <&apbdma 5>, <&apbdma 5>; 1125 dma-names = "rx", "tx"; 1126 status = "disabled"; 1127 }; 1128 1129 usb@7d000000 { 1130 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 1131 reg = <0x0 0x7d000000 0x0 0x4000>; 1132 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1133 phy_type = "utmi"; 1134 clocks = <&tegra_car TEGRA210_CLK_USBD>; 1135 clock-names = "usb"; 1136 resets = <&tegra_car 22>; 1137 reset-names = "usb"; 1138 nvidia,phy = <&phy1>; 1139 status = "disabled"; 1140 }; 1141 1142 phy1: usb-phy@7d000000 { 1143 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; 1144 reg = <0x0 0x7d000000 0x0 0x4000>, 1145 <0x0 0x7d000000 0x0 0x4000>; 1146 phy_type = "utmi"; 1147 clocks = <&tegra_car TEGRA210_CLK_USBD>, 1148 <&tegra_car TEGRA210_CLK_PLL_U>, 1149 <&tegra_car TEGRA210_CLK_USBD>; 1150 clock-names = "reg", "pll_u", "utmi-pads"; 1151 resets = <&tegra_car 22>, <&tegra_car 22>; 1152 reset-names = "usb", "utmi-pads"; 1153 nvidia,hssync-start-delay = <0>; 1154 nvidia,idle-wait-delay = <17>; 1155 nvidia,elastic-limit = <16>; 1156 nvidia,term-range-adj = <6>; 1157 nvidia,xcvr-setup = <9>; 1158 nvidia,xcvr-lsfslew = <0>; 1159 nvidia,xcvr-lsrslew = <3>; 1160 nvidia,hssquelch-level = <2>; 1161 nvidia,hsdiscon-level = <5>; 1162 nvidia,xcvr-hsslew = <12>; 1163 nvidia,has-utmi-pad-registers; 1164 status = "disabled"; 1165 }; 1166 1167 usb@7d004000 { 1168 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 1169 reg = <0x0 0x7d004000 0x0 0x4000>; 1170 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1171 phy_type = "utmi"; 1172 clocks = <&tegra_car TEGRA210_CLK_USB2>; 1173 clock-names = "usb"; 1174 resets = <&tegra_car 58>; 1175 reset-names = "usb"; 1176 nvidia,phy = <&phy2>; 1177 status = "disabled"; 1178 }; 1179 1180 phy2: usb-phy@7d004000 { 1181 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; 1182 reg = <0x0 0x7d004000 0x0 0x4000>, 1183 <0x0 0x7d000000 0x0 0x4000>; 1184 phy_type = "utmi"; 1185 clocks = <&tegra_car TEGRA210_CLK_USB2>, 1186 <&tegra_car TEGRA210_CLK_PLL_U>, 1187 <&tegra_car TEGRA210_CLK_USBD>; 1188 clock-names = "reg", "pll_u", "utmi-pads"; 1189 resets = <&tegra_car 58>, <&tegra_car 22>; 1190 reset-names = "usb", "utmi-pads"; 1191 nvidia,hssync-start-delay = <0>; 1192 nvidia,idle-wait-delay = <17>; 1193 nvidia,elastic-limit = <16>; 1194 nvidia,term-range-adj = <6>; 1195 nvidia,xcvr-setup = <9>; 1196 nvidia,xcvr-lsfslew = <0>; 1197 nvidia,xcvr-lsrslew = <3>; 1198 nvidia,hssquelch-level = <2>; 1199 nvidia,hsdiscon-level = <5>; 1200 nvidia,xcvr-hsslew = <12>; 1201 status = "disabled"; 1202 }; 1203 1204 cpus { 1205 #address-cells = <1>; 1206 #size-cells = <0>; 1207 1208 cpu@0 { 1209 device_type = "cpu"; 1210 compatible = "arm,cortex-a57"; 1211 reg = <0>; 1212 }; 1213 1214 cpu@1 { 1215 device_type = "cpu"; 1216 compatible = "arm,cortex-a57"; 1217 reg = <1>; 1218 }; 1219 1220 cpu@2 { 1221 device_type = "cpu"; 1222 compatible = "arm,cortex-a57"; 1223 reg = <2>; 1224 }; 1225 1226 cpu@3 { 1227 device_type = "cpu"; 1228 compatible = "arm,cortex-a57"; 1229 reg = <3>; 1230 }; 1231 }; 1232 1233 timer { 1234 compatible = "arm,armv8-timer"; 1235 interrupts = <GIC_PPI 13 1236 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1237 <GIC_PPI 14 1238 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1239 <GIC_PPI 11 1240 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1241 <GIC_PPI 10 1242 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1243 interrupt-parent = <&gic>; 1244 }; 1245 1246 soctherm: thermal-sensor@700e2000 { 1247 compatible = "nvidia,tegra210-soctherm"; 1248 reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */ 1249 0x0 0x60006000 0x0 0x400>; /* CAR reg_base */ 1250 reg-names = "soctherm-reg", "car-reg"; 1251 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 1252 clocks = <&tegra_car TEGRA210_CLK_TSENSOR>, 1253 <&tegra_car TEGRA210_CLK_SOC_THERM>; 1254 clock-names = "tsensor", "soctherm"; 1255 resets = <&tegra_car 78>; 1256 reset-names = "soctherm"; 1257 #thermal-sensor-cells = <1>; 1258 1259 throttle-cfgs { 1260 throttle_heavy: heavy { 1261 nvidia,priority = <100>; 1262 nvidia,cpu-throt-percent = <85>; 1263 1264 #cooling-cells = <2>; 1265 }; 1266 }; 1267 }; 1268 1269 thermal-zones { 1270 cpu { 1271 polling-delay-passive = <1000>; 1272 polling-delay = <0>; 1273 1274 thermal-sensors = 1275 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; 1276 1277 trips { 1278 cpu-shutdown-trip { 1279 temperature = <102500>; 1280 hysteresis = <0>; 1281 type = "critical"; 1282 }; 1283 1284 cpu_throttle_trip: throttle-trip { 1285 temperature = <98500>; 1286 hysteresis = <1000>; 1287 type = "hot"; 1288 }; 1289 }; 1290 1291 cooling-maps { 1292 map0 { 1293 trip = <&cpu_throttle_trip>; 1294 cooling-device = <&throttle_heavy 1 1>; 1295 }; 1296 }; 1297 }; 1298 mem { 1299 polling-delay-passive = <0>; 1300 polling-delay = <0>; 1301 1302 thermal-sensors = 1303 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>; 1304 1305 trips { 1306 mem-shutdown-trip { 1307 temperature = <103000>; 1308 hysteresis = <0>; 1309 type = "critical"; 1310 }; 1311 }; 1312 1313 cooling-maps { 1314 /* 1315 * There are currently no cooling maps, 1316 * because there are no cooling devices. 1317 */ 1318 }; 1319 }; 1320 gpu { 1321 polling-delay-passive = <1000>; 1322 polling-delay = <0>; 1323 1324 thermal-sensors = 1325 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>; 1326 1327 trips { 1328 gpu-shutdown-trip { 1329 temperature = <103000>; 1330 hysteresis = <0>; 1331 type = "critical"; 1332 }; 1333 1334 gpu_throttle_trip: throttle-trip { 1335 temperature = <100000>; 1336 hysteresis = <1000>; 1337 type = "hot"; 1338 }; 1339 }; 1340 1341 cooling-maps { 1342 map0 { 1343 trip = <&gpu_throttle_trip>; 1344 cooling-device = <&throttle_heavy 1 1>; 1345 }; 1346 }; 1347 }; 1348 pllx { 1349 polling-delay-passive = <0>; 1350 polling-delay = <0>; 1351 1352 thermal-sensors = 1353 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>; 1354 1355 trips { 1356 pllx-shutdown-trip { 1357 temperature = <103000>; 1358 hysteresis = <0>; 1359 type = "critical"; 1360 }; 1361 }; 1362 1363 cooling-maps { 1364 /* 1365 * There are currently no cooling maps, 1366 * because there are no cooling devices. 1367 */ 1368 }; 1369 }; 1370 }; 1371}; 1372