1// SPDX-License-Identifier: GPL-2.0
2#include <dt-bindings/clock/tegra210-car.h>
3#include <dt-bindings/gpio/tegra-gpio.h>
4#include <dt-bindings/memory/tegra210-mc.h>
5#include <dt-bindings/pinctrl/pinctrl-tegra.h>
6#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
7#include <dt-bindings/reset/tegra210-car.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9#include <dt-bindings/thermal/tegra124-soctherm.h>
10#include <dt-bindings/soc/tegra-pmc.h>
11
12/ {
13	compatible = "nvidia,tegra210";
14	interrupt-parent = <&lic>;
15	#address-cells = <2>;
16	#size-cells = <2>;
17
18	pcie@1003000 {
19		compatible = "nvidia,tegra210-pcie";
20		device_type = "pci";
21		reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */
22		      <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */
23		      <0x0 0x02000000 0x0 0x10000000>; /* configuration space */
24		reg-names = "pads", "afi", "cs";
25		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
26			     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
27		interrupt-names = "intr", "msi";
28
29		#interrupt-cells = <1>;
30		interrupt-map-mask = <0 0 0 0>;
31		interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
32
33		bus-range = <0x00 0xff>;
34		#address-cells = <3>;
35		#size-cells = <2>;
36
37		ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */
38			 <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */
39			 <0x01000000 0 0x0        0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */
40			 <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */
41			 <0x42000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
42
43		clocks = <&tegra_car TEGRA210_CLK_PCIE>,
44			 <&tegra_car TEGRA210_CLK_AFI>,
45			 <&tegra_car TEGRA210_CLK_PLL_E>,
46			 <&tegra_car TEGRA210_CLK_CML0>;
47		clock-names = "pex", "afi", "pll_e", "cml";
48		resets = <&tegra_car 70>,
49			 <&tegra_car 72>,
50			 <&tegra_car 74>;
51		reset-names = "pex", "afi", "pcie_x";
52
53		pinctrl-names = "default", "idle";
54		pinctrl-0 = <&pex_dpd_disable>;
55		pinctrl-1 = <&pex_dpd_enable>;
56
57		status = "disabled";
58
59		pci@1,0 {
60			device_type = "pci";
61			assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
62			reg = <0x000800 0 0 0 0>;
63			bus-range = <0x00 0xff>;
64			status = "disabled";
65
66			#address-cells = <3>;
67			#size-cells = <2>;
68			ranges;
69
70			nvidia,num-lanes = <4>;
71		};
72
73		pci@2,0 {
74			device_type = "pci";
75			assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
76			reg = <0x001000 0 0 0 0>;
77			bus-range = <0x00 0xff>;
78			status = "disabled";
79
80			#address-cells = <3>;
81			#size-cells = <2>;
82			ranges;
83
84			nvidia,num-lanes = <1>;
85		};
86	};
87
88	host1x@50000000 {
89		compatible = "nvidia,tegra210-host1x";
90		reg = <0x0 0x50000000 0x0 0x00034000>;
91		interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
92			     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
93		interrupt-names = "syncpt", "host1x";
94		clocks = <&tegra_car TEGRA210_CLK_HOST1X>;
95		clock-names = "host1x";
96		resets = <&tegra_car 28>;
97		reset-names = "host1x";
98
99		#address-cells = <2>;
100		#size-cells = <2>;
101
102		ranges = <0x0 0x54000000 0x0 0x54000000 0x0 0x01000000>;
103
104		iommus = <&mc TEGRA_SWGROUP_HC>;
105
106		dpaux1: dpaux@54040000 {
107			compatible = "nvidia,tegra210-dpaux";
108			reg = <0x0 0x54040000 0x0 0x00040000>;
109			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
110			clocks = <&tegra_car TEGRA210_CLK_DPAUX1>,
111				 <&tegra_car TEGRA210_CLK_PLL_DP>;
112			clock-names = "dpaux", "parent";
113			resets = <&tegra_car 207>;
114			reset-names = "dpaux";
115			power-domains = <&pd_sor>;
116			status = "disabled";
117
118			state_dpaux1_aux: pinmux-aux {
119				groups = "dpaux-io";
120				function = "aux";
121			};
122
123			state_dpaux1_i2c: pinmux-i2c {
124				groups = "dpaux-io";
125				function = "i2c";
126			};
127
128			state_dpaux1_off: pinmux-off {
129				groups = "dpaux-io";
130				function = "off";
131			};
132
133			i2c-bus {
134				#address-cells = <1>;
135				#size-cells = <0>;
136			};
137		};
138
139		vi@54080000 {
140			compatible = "nvidia,tegra210-vi";
141			reg = <0x0 0x54080000 0x0 0x700>;
142			interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
143			status = "disabled";
144			assigned-clocks = <&tegra_car TEGRA210_CLK_VI>;
145			assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
146
147			clocks = <&tegra_car TEGRA210_CLK_VI>;
148			power-domains = <&pd_venc>;
149
150			#address-cells = <1>;
151			#size-cells = <1>;
152
153			ranges = <0x0 0x0 0x54080000 0x2000>;
154
155			csi@838 {
156				compatible = "nvidia,tegra210-csi";
157				reg = <0x838 0x1300>;
158				status = "disabled";
159				assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>,
160						  <&tegra_car TEGRA210_CLK_CILCD>,
161						  <&tegra_car TEGRA210_CLK_CILE>,
162						  <&tegra_car TEGRA210_CLK_CSI_TPG>;
163				assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>,
164							 <&tegra_car TEGRA210_CLK_PLL_P>,
165							 <&tegra_car TEGRA210_CLK_PLL_P>;
166				assigned-clock-rates = <102000000>,
167						       <102000000>,
168						       <102000000>,
169						       <972000000>;
170
171				clocks = <&tegra_car TEGRA210_CLK_CSI>,
172					 <&tegra_car TEGRA210_CLK_CILAB>,
173					 <&tegra_car TEGRA210_CLK_CILCD>,
174					 <&tegra_car TEGRA210_CLK_CILE>,
175					 <&tegra_car TEGRA210_CLK_CSI_TPG>;
176				clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg";
177				power-domains = <&pd_sor>;
178			};
179		};
180
181		tsec@54100000 {
182			compatible = "nvidia,tegra210-tsec";
183			reg = <0x0 0x54100000 0x0 0x00040000>;
184			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
185			clocks = <&tegra_car TEGRA210_CLK_TSEC>;
186			clock-names = "tsec";
187			resets = <&tegra_car 83>;
188			reset-names = "tsec";
189			status = "disabled";
190		};
191
192		dc@54200000 {
193			compatible = "nvidia,tegra210-dc";
194			reg = <0x0 0x54200000 0x0 0x00040000>;
195			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
196			clocks = <&tegra_car TEGRA210_CLK_DISP1>;
197			clock-names = "dc";
198			resets = <&tegra_car 27>;
199			reset-names = "dc";
200
201			iommus = <&mc TEGRA_SWGROUP_DC>;
202
203			nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
204			nvidia,head = <0>;
205		};
206
207		dc@54240000 {
208			compatible = "nvidia,tegra210-dc";
209			reg = <0x0 0x54240000 0x0 0x00040000>;
210			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
211			clocks = <&tegra_car TEGRA210_CLK_DISP2>;
212			clock-names = "dc";
213			resets = <&tegra_car 26>;
214			reset-names = "dc";
215
216			iommus = <&mc TEGRA_SWGROUP_DCB>;
217
218			nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
219			nvidia,head = <1>;
220		};
221
222		dsia: dsi@54300000 {
223			compatible = "nvidia,tegra210-dsi";
224			reg = <0x0 0x54300000 0x0 0x00040000>;
225			clocks = <&tegra_car TEGRA210_CLK_DSIA>,
226				 <&tegra_car TEGRA210_CLK_DSIALP>,
227				 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>;
228			clock-names = "dsi", "lp", "parent";
229			resets = <&tegra_car 48>;
230			reset-names = "dsi";
231			power-domains = <&pd_sor>;
232			nvidia,mipi-calibrate = <&mipi 0x0c0>; /* DSIA & DSIB pads */
233
234			status = "disabled";
235
236			#address-cells = <1>;
237			#size-cells = <0>;
238		};
239
240		vic@54340000 {
241			compatible = "nvidia,tegra210-vic";
242			reg = <0x0 0x54340000 0x0 0x00040000>;
243			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
244			clocks = <&tegra_car TEGRA210_CLK_VIC03>;
245			clock-names = "vic";
246			resets = <&tegra_car 178>;
247			reset-names = "vic";
248
249			iommus = <&mc TEGRA_SWGROUP_VIC>;
250			power-domains = <&pd_vic>;
251		};
252
253		nvjpg@54380000 {
254			compatible = "nvidia,tegra210-nvjpg";
255			reg = <0x0 0x54380000 0x0 0x00040000>;
256			status = "disabled";
257		};
258
259		dsib: dsi@54400000 {
260			compatible = "nvidia,tegra210-dsi";
261			reg = <0x0 0x54400000 0x0 0x00040000>;
262			clocks = <&tegra_car TEGRA210_CLK_DSIB>,
263				 <&tegra_car TEGRA210_CLK_DSIBLP>,
264				 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>;
265			clock-names = "dsi", "lp", "parent";
266			resets = <&tegra_car 82>;
267			reset-names = "dsi";
268			power-domains = <&pd_sor>;
269			nvidia,mipi-calibrate = <&mipi 0x300>; /* DSIC & DSID pads */
270
271			status = "disabled";
272
273			#address-cells = <1>;
274			#size-cells = <0>;
275		};
276
277		nvdec@54480000 {
278			compatible = "nvidia,tegra210-nvdec";
279			reg = <0x0 0x54480000 0x0 0x00040000>;
280			status = "disabled";
281		};
282
283		nvenc@544c0000 {
284			compatible = "nvidia,tegra210-nvenc";
285			reg = <0x0 0x544c0000 0x0 0x00040000>;
286			status = "disabled";
287		};
288
289		tsec@54500000 {
290			compatible = "nvidia,tegra210-tsec";
291			reg = <0x0 0x54500000 0x0 0x00040000>;
292			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
293			clocks = <&tegra_car TEGRA210_CLK_TSECB>;
294			clock-names = "tsec";
295			resets = <&tegra_car 206>;
296			reset-names = "tsec";
297			status = "disabled";
298		};
299
300		sor0: sor@54540000 {
301			compatible = "nvidia,tegra210-sor";
302			reg = <0x0 0x54540000 0x0 0x00040000>;
303			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
304			clocks = <&tegra_car TEGRA210_CLK_SOR0>,
305				 <&tegra_car TEGRA210_CLK_SOR0_OUT>,
306				 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>,
307				 <&tegra_car TEGRA210_CLK_PLL_DP>,
308				 <&tegra_car TEGRA210_CLK_SOR_SAFE>;
309			clock-names = "sor", "out", "parent", "dp", "safe";
310			resets = <&tegra_car 182>;
311			reset-names = "sor";
312			pinctrl-0 = <&state_dpaux_aux>;
313			pinctrl-1 = <&state_dpaux_i2c>;
314			pinctrl-2 = <&state_dpaux_off>;
315			pinctrl-names = "aux", "i2c", "off";
316			power-domains = <&pd_sor>;
317			status = "disabled";
318		};
319
320		sor1: sor@54580000 {
321			compatible = "nvidia,tegra210-sor1";
322			reg = <0x0 0x54580000 0x0 0x00040000>;
323			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
324			clocks = <&tegra_car TEGRA210_CLK_SOR1>,
325				 <&tegra_car TEGRA210_CLK_SOR1_OUT>,
326				 <&tegra_car TEGRA210_CLK_PLL_D2_OUT0>,
327				 <&tegra_car TEGRA210_CLK_PLL_DP>,
328				 <&tegra_car TEGRA210_CLK_SOR_SAFE>;
329			clock-names = "sor", "out", "parent", "dp", "safe";
330			resets = <&tegra_car 183>;
331			reset-names = "sor";
332			pinctrl-0 = <&state_dpaux1_aux>;
333			pinctrl-1 = <&state_dpaux1_i2c>;
334			pinctrl-2 = <&state_dpaux1_off>;
335			pinctrl-names = "aux", "i2c", "off";
336			power-domains = <&pd_sor>;
337			status = "disabled";
338		};
339
340		dpaux: dpaux@545c0000 {
341			compatible = "nvidia,tegra210-dpaux";
342			reg = <0x0 0x545c0000 0x0 0x00040000>;
343			interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
344			clocks = <&tegra_car TEGRA210_CLK_DPAUX>,
345				 <&tegra_car TEGRA210_CLK_PLL_DP>;
346			clock-names = "dpaux", "parent";
347			resets = <&tegra_car 181>;
348			reset-names = "dpaux";
349			power-domains = <&pd_sor>;
350			status = "disabled";
351
352			state_dpaux_aux: pinmux-aux {
353				groups = "dpaux-io";
354				function = "aux";
355			};
356
357			state_dpaux_i2c: pinmux-i2c {
358				groups = "dpaux-io";
359				function = "i2c";
360			};
361
362			state_dpaux_off: pinmux-off {
363				groups = "dpaux-io";
364				function = "off";
365			};
366
367			i2c-bus {
368				#address-cells = <1>;
369				#size-cells = <0>;
370			};
371		};
372
373		isp@54600000 {
374			compatible = "nvidia,tegra210-isp";
375			reg = <0x0 0x54600000 0x0 0x00040000>;
376			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
377			clocks = <&tegra_car TEGRA210_CLK_ISPA>;
378			resets = <&tegra_car 23>;
379			reset-names = "isp";
380			status = "disabled";
381		};
382
383		isp@54680000 {
384			compatible = "nvidia,tegra210-isp";
385			reg = <0x0 0x54680000 0x0 0x00040000>;
386			interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
387			clocks = <&tegra_car TEGRA210_CLK_ISPB>;
388			resets = <&tegra_car 3>;
389			reset-names = "isp";
390			status = "disabled";
391		};
392
393		i2c@546c0000 {
394			compatible = "nvidia,tegra210-i2c-vi";
395			reg = <0x0 0x546c0000 0x0 0x00040000>;
396			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
397			clocks = <&tegra_car TEGRA210_CLK_VI_I2C>,
398				 <&tegra_car TEGRA210_CLK_I2CSLOW>;
399			clock-names = "div-clk", "slow";
400			resets = <&tegra_car 208>;
401			reset-names = "i2c";
402			power-domains = <&pd_venc>;
403			status = "disabled";
404
405			#address-cells = <1>;
406			#size-cells = <0>;
407		};
408	};
409
410	gic: interrupt-controller@50041000 {
411		compatible = "arm,gic-400";
412		#interrupt-cells = <3>;
413		interrupt-controller;
414		reg = <0x0 0x50041000 0x0 0x1000>,
415		      <0x0 0x50042000 0x0 0x2000>,
416		      <0x0 0x50044000 0x0 0x2000>,
417		      <0x0 0x50046000 0x0 0x2000>;
418		interrupts = <GIC_PPI 9
419			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
420		interrupt-parent = <&gic>;
421	};
422
423	gpu@57000000 {
424		compatible = "nvidia,gm20b";
425		reg = <0x0 0x57000000 0x0 0x01000000>,
426		      <0x0 0x58000000 0x0 0x01000000>;
427		interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
428			     <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
429		interrupt-names = "stall", "nonstall";
430		clocks = <&tegra_car TEGRA210_CLK_GPU>,
431			 <&tegra_car TEGRA210_CLK_PLL_P_OUT5>,
432			 <&tegra_car TEGRA210_CLK_PLL_G_REF>;
433		clock-names = "gpu", "pwr", "ref";
434		resets = <&tegra_car 184>;
435		reset-names = "gpu";
436
437		iommus = <&mc TEGRA_SWGROUP_GPU>;
438
439		status = "disabled";
440	};
441
442	lic: interrupt-controller@60004000 {
443		compatible = "nvidia,tegra210-ictlr";
444		reg = <0x0 0x60004000 0x0 0x40>, /* primary controller */
445		      <0x0 0x60004100 0x0 0x40>, /* secondary controller */
446		      <0x0 0x60004200 0x0 0x40>, /* tertiary controller */
447		      <0x0 0x60004300 0x0 0x40>, /* quaternary controller */
448		      <0x0 0x60004400 0x0 0x40>, /* quinary controller */
449		      <0x0 0x60004500 0x0 0x40>; /* senary controller */
450		interrupt-controller;
451		#interrupt-cells = <3>;
452		interrupt-parent = <&gic>;
453	};
454
455	timer@60005000 {
456		compatible = "nvidia,tegra210-timer";
457		reg = <0x0 0x60005000 0x0 0x400>;
458		interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
459			     <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
460			     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
461			     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
462			     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
463			     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
464			     <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
465			     <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
466			     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
467			     <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
468			     <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
469			     <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
470			     <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
471			     <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
472		clocks = <&tegra_car TEGRA210_CLK_TIMER>;
473		clock-names = "timer";
474	};
475
476	tegra_car: clock@60006000 {
477		compatible = "nvidia,tegra210-car";
478		reg = <0x0 0x60006000 0x0 0x1000>;
479		#clock-cells = <1>;
480		#reset-cells = <1>;
481	};
482
483	flow-controller@60007000 {
484		compatible = "nvidia,tegra210-flowctrl";
485		reg = <0x0 0x60007000 0x0 0x1000>;
486	};
487
488	gpio: gpio@6000d000 {
489		compatible = "nvidia,tegra210-gpio", "nvidia,tegra30-gpio";
490		reg = <0x0 0x6000d000 0x0 0x1000>;
491		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
492			     <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
493			     <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
494			     <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
495			     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
496			     <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
497			     <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
498			     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
499		#gpio-cells = <2>;
500		gpio-controller;
501		#interrupt-cells = <2>;
502		interrupt-controller;
503	};
504
505	apbdma: dma@60020000 {
506		compatible = "nvidia,tegra210-apbdma", "nvidia,tegra148-apbdma";
507		reg = <0x0 0x60020000 0x0 0x1400>;
508		interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
509			     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
510			     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
511			     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
512			     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
513			     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
514			     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
515			     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
516			     <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
517			     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
518			     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
519			     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
520			     <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
521			     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
522			     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
523			     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
524			     <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
525			     <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
526			     <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
527			     <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
528			     <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
529			     <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
530			     <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
531			     <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
532			     <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
533			     <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
534			     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
535			     <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
536			     <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
537			     <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
538			     <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
539			     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
540		clocks = <&tegra_car TEGRA210_CLK_APBDMA>;
541		clock-names = "dma";
542		resets = <&tegra_car 34>;
543		reset-names = "dma";
544		#dma-cells = <1>;
545	};
546
547	apbmisc@70000800 {
548		compatible = "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc";
549		reg = <0x0 0x70000800 0x0 0x64>,   /* Chip revision */
550		      <0x0 0x70000008 0x0 0x04>;   /* Strapping options */
551	};
552
553	pinmux: pinmux@700008d4 {
554		compatible = "nvidia,tegra210-pinmux";
555		reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */
556		      <0x0 0x70003000 0x0 0x294>; /* Mux registers */
557		sdmmc1_3v3_drv: sdmmc1-3v3-drv {
558			sdmmc1 {
559				nvidia,pins = "drive_sdmmc1";
560				nvidia,pull-down-strength = <0x8>;
561				nvidia,pull-up-strength = <0x8>;
562			};
563		};
564		sdmmc1_1v8_drv: sdmmc1-1v8-drv {
565			sdmmc1 {
566				nvidia,pins = "drive_sdmmc1";
567				nvidia,pull-down-strength = <0x4>;
568				nvidia,pull-up-strength = <0x3>;
569			};
570		};
571		sdmmc2_1v8_drv: sdmmc2-1v8-drv {
572			sdmmc2 {
573				nvidia,pins = "drive_sdmmc2";
574				nvidia,pull-down-strength = <0x10>;
575				nvidia,pull-up-strength = <0x10>;
576			};
577		};
578		sdmmc3_3v3_drv: sdmmc3-3v3-drv {
579			sdmmc3 {
580				nvidia,pins = "drive_sdmmc3";
581				nvidia,pull-down-strength = <0x8>;
582				nvidia,pull-up-strength = <0x8>;
583			};
584		};
585		sdmmc3_1v8_drv: sdmmc3-1v8-drv {
586			sdmmc3 {
587				nvidia,pins = "drive_sdmmc3";
588				nvidia,pull-down-strength = <0x4>;
589				nvidia,pull-up-strength = <0x3>;
590			};
591		};
592		sdmmc4_1v8_drv: sdmmc4-1v8-drv {
593			sdmmc4 {
594				nvidia,pins = "drive_sdmmc4";
595				nvidia,pull-down-strength = <0x10>;
596				nvidia,pull-up-strength = <0x10>;
597			};
598		};
599	};
600
601	/*
602	 * There are two serial driver i.e. 8250 based simple serial
603	 * driver and APB DMA based serial driver for higher baudrate
604	 * and performance. To enable the 8250 based driver, the compatible
605	 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
606	 * the APB DMA based serial driver, the compatible is
607	 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
608	 */
609	uarta: serial@70006000 {
610		compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
611		reg = <0x0 0x70006000 0x0 0x40>;
612		reg-shift = <2>;
613		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
614		clocks = <&tegra_car TEGRA210_CLK_UARTA>;
615		clock-names = "serial";
616		resets = <&tegra_car 6>;
617		reset-names = "serial";
618		dmas = <&apbdma 8>, <&apbdma 8>;
619		dma-names = "rx", "tx";
620		status = "disabled";
621	};
622
623	uartb: serial@70006040 {
624		compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
625		reg = <0x0 0x70006040 0x0 0x40>;
626		reg-shift = <2>;
627		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
628		clocks = <&tegra_car TEGRA210_CLK_UARTB>;
629		clock-names = "serial";
630		resets = <&tegra_car 7>;
631		reset-names = "serial";
632		dmas = <&apbdma 9>, <&apbdma 9>;
633		dma-names = "rx", "tx";
634		status = "disabled";
635	};
636
637	uartc: serial@70006200 {
638		compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
639		reg = <0x0 0x70006200 0x0 0x40>;
640		reg-shift = <2>;
641		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
642		clocks = <&tegra_car TEGRA210_CLK_UARTC>;
643		clock-names = "serial";
644		resets = <&tegra_car 55>;
645		reset-names = "serial";
646		dmas = <&apbdma 10>, <&apbdma 10>;
647		dma-names = "rx", "tx";
648		status = "disabled";
649	};
650
651	uartd: serial@70006300 {
652		compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
653		reg = <0x0 0x70006300 0x0 0x40>;
654		reg-shift = <2>;
655		interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
656		clocks = <&tegra_car TEGRA210_CLK_UARTD>;
657		clock-names = "serial";
658		resets = <&tegra_car 65>;
659		reset-names = "serial";
660		dmas = <&apbdma 19>, <&apbdma 19>;
661		dma-names = "rx", "tx";
662		status = "disabled";
663	};
664
665	pwm: pwm@7000a000 {
666		compatible = "nvidia,tegra210-pwm", "nvidia,tegra20-pwm";
667		reg = <0x0 0x7000a000 0x0 0x100>;
668		#pwm-cells = <2>;
669		clocks = <&tegra_car TEGRA210_CLK_PWM>;
670		clock-names = "pwm";
671		resets = <&tegra_car 17>;
672		reset-names = "pwm";
673		status = "disabled";
674	};
675
676	i2c@7000c000 {
677		compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
678		reg = <0x0 0x7000c000 0x0 0x100>;
679		interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
680		#address-cells = <1>;
681		#size-cells = <0>;
682		clocks = <&tegra_car TEGRA210_CLK_I2C1>;
683		clock-names = "div-clk";
684		resets = <&tegra_car 12>;
685		reset-names = "i2c";
686		dmas = <&apbdma 21>, <&apbdma 21>;
687		dma-names = "rx", "tx";
688		status = "disabled";
689	};
690
691	i2c@7000c400 {
692		compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
693		reg = <0x0 0x7000c400 0x0 0x100>;
694		interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
695		#address-cells = <1>;
696		#size-cells = <0>;
697		clocks = <&tegra_car TEGRA210_CLK_I2C2>;
698		clock-names = "div-clk";
699		resets = <&tegra_car 54>;
700		reset-names = "i2c";
701		dmas = <&apbdma 22>, <&apbdma 22>;
702		dma-names = "rx", "tx";
703		status = "disabled";
704	};
705
706	i2c@7000c500 {
707		compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
708		reg = <0x0 0x7000c500 0x0 0x100>;
709		interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
710		#address-cells = <1>;
711		#size-cells = <0>;
712		clocks = <&tegra_car TEGRA210_CLK_I2C3>;
713		clock-names = "div-clk";
714		resets = <&tegra_car 67>;
715		reset-names = "i2c";
716		dmas = <&apbdma 23>, <&apbdma 23>;
717		dma-names = "rx", "tx";
718		status = "disabled";
719	};
720
721	i2c@7000c700 {
722		compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
723		reg = <0x0 0x7000c700 0x0 0x100>;
724		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
725		#address-cells = <1>;
726		#size-cells = <0>;
727		clocks = <&tegra_car TEGRA210_CLK_I2C4>;
728		clock-names = "div-clk";
729		resets = <&tegra_car 103>;
730		reset-names = "i2c";
731		dmas = <&apbdma 26>, <&apbdma 26>;
732		dma-names = "rx", "tx";
733		pinctrl-0 = <&state_dpaux1_i2c>;
734		pinctrl-1 = <&state_dpaux1_off>;
735		pinctrl-names = "default", "idle";
736		status = "disabled";
737	};
738
739	i2c@7000d000 {
740		compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
741		reg = <0x0 0x7000d000 0x0 0x100>;
742		interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
743		#address-cells = <1>;
744		#size-cells = <0>;
745		clocks = <&tegra_car TEGRA210_CLK_I2C5>;
746		clock-names = "div-clk";
747		resets = <&tegra_car 47>;
748		reset-names = "i2c";
749		dmas = <&apbdma 24>, <&apbdma 24>;
750		dma-names = "rx", "tx";
751		status = "disabled";
752	};
753
754	i2c@7000d100 {
755		compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
756		reg = <0x0 0x7000d100 0x0 0x100>;
757		interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
758		#address-cells = <1>;
759		#size-cells = <0>;
760		clocks = <&tegra_car TEGRA210_CLK_I2C6>;
761		clock-names = "div-clk";
762		resets = <&tegra_car 166>;
763		reset-names = "i2c";
764		dmas = <&apbdma 30>, <&apbdma 30>;
765		dma-names = "rx", "tx";
766		pinctrl-0 = <&state_dpaux_i2c>;
767		pinctrl-1 = <&state_dpaux_off>;
768		pinctrl-names = "default", "idle";
769		status = "disabled";
770	};
771
772	spi@7000d400 {
773		compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
774		reg = <0x0 0x7000d400 0x0 0x200>;
775		interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
776		#address-cells = <1>;
777		#size-cells = <0>;
778		clocks = <&tegra_car TEGRA210_CLK_SBC1>;
779		clock-names = "spi";
780		resets = <&tegra_car 41>;
781		reset-names = "spi";
782		dmas = <&apbdma 15>, <&apbdma 15>;
783		dma-names = "rx", "tx";
784		status = "disabled";
785	};
786
787	spi@7000d600 {
788		compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
789		reg = <0x0 0x7000d600 0x0 0x200>;
790		interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
791		#address-cells = <1>;
792		#size-cells = <0>;
793		clocks = <&tegra_car TEGRA210_CLK_SBC2>;
794		clock-names = "spi";
795		resets = <&tegra_car 44>;
796		reset-names = "spi";
797		dmas = <&apbdma 16>, <&apbdma 16>;
798		dma-names = "rx", "tx";
799		status = "disabled";
800	};
801
802	spi@7000d800 {
803		compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
804		reg = <0x0 0x7000d800 0x0 0x200>;
805		interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
806		#address-cells = <1>;
807		#size-cells = <0>;
808		clocks = <&tegra_car TEGRA210_CLK_SBC3>;
809		clock-names = "spi";
810		resets = <&tegra_car 46>;
811		reset-names = "spi";
812		dmas = <&apbdma 17>, <&apbdma 17>;
813		dma-names = "rx", "tx";
814		status = "disabled";
815	};
816
817	spi@7000da00 {
818		compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
819		reg = <0x0 0x7000da00 0x0 0x200>;
820		interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
821		#address-cells = <1>;
822		#size-cells = <0>;
823		clocks = <&tegra_car TEGRA210_CLK_SBC4>;
824		clock-names = "spi";
825		resets = <&tegra_car 68>;
826		reset-names = "spi";
827		dmas = <&apbdma 18>, <&apbdma 18>;
828		dma-names = "rx", "tx";
829		status = "disabled";
830	};
831
832	rtc@7000e000 {
833		compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc";
834		reg = <0x0 0x7000e000 0x0 0x100>;
835		interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
836		interrupt-parent = <&tegra_pmc>;
837		clocks = <&tegra_car TEGRA210_CLK_RTC>;
838		clock-names = "rtc";
839	};
840
841	tegra_pmc: pmc@7000e400 {
842		compatible = "nvidia,tegra210-pmc";
843		reg = <0x0 0x7000e400 0x0 0x400>;
844		clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
845		clock-names = "pclk", "clk32k_in";
846		#clock-cells = <1>;
847		#interrupt-cells = <2>;
848		interrupt-controller;
849
850		powergates {
851			pd_audio: aud {
852				clocks = <&tegra_car TEGRA210_CLK_APE>,
853					 <&tegra_car TEGRA210_CLK_APB2APE>;
854				resets = <&tegra_car 198>;
855				#power-domain-cells = <0>;
856			};
857
858			pd_sor: sor {
859				clocks = <&tegra_car TEGRA210_CLK_SOR0>,
860					 <&tegra_car TEGRA210_CLK_SOR1>,
861					 <&tegra_car TEGRA210_CLK_CILAB>,
862					 <&tegra_car TEGRA210_CLK_CILCD>,
863					 <&tegra_car TEGRA210_CLK_CILE>,
864					 <&tegra_car TEGRA210_CLK_DSIA>,
865					 <&tegra_car TEGRA210_CLK_DSIB>,
866					 <&tegra_car TEGRA210_CLK_DPAUX>,
867					 <&tegra_car TEGRA210_CLK_DPAUX1>,
868					 <&tegra_car TEGRA210_CLK_MIPI_CAL>;
869				resets = <&tegra_car TEGRA210_CLK_SOR0>,
870					 <&tegra_car TEGRA210_CLK_SOR1>,
871					 <&tegra_car TEGRA210_CLK_DSIA>,
872					 <&tegra_car TEGRA210_CLK_DSIB>,
873					 <&tegra_car TEGRA210_CLK_DPAUX>,
874					 <&tegra_car TEGRA210_CLK_DPAUX1>,
875					 <&tegra_car TEGRA210_CLK_MIPI_CAL>;
876				#power-domain-cells = <0>;
877			};
878
879			pd_xusbss: xusba {
880				clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>;
881				resets = <&tegra_car TEGRA210_CLK_XUSB_SS>;
882				#power-domain-cells = <0>;
883			};
884
885			pd_xusbdev: xusbb {
886				clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>;
887				resets = <&tegra_car 95>;
888				#power-domain-cells = <0>;
889			};
890
891			pd_xusbhost: xusbc {
892				clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>;
893				resets = <&tegra_car TEGRA210_CLK_XUSB_HOST>;
894				#power-domain-cells = <0>;
895			};
896
897			pd_vic: vic {
898				clocks = <&tegra_car TEGRA210_CLK_VIC03>;
899				clock-names = "vic";
900				resets = <&tegra_car 178>;
901				reset-names = "vic";
902				#power-domain-cells = <0>;
903			};
904
905			pd_venc: venc {
906				clocks = <&tegra_car TEGRA210_CLK_VI>,
907					 <&tegra_car TEGRA210_CLK_CSI>;
908				resets = <&mc TEGRA210_MC_RESET_VI>,
909					 <&tegra_car 20>,
910					 <&tegra_car 52>;
911				#power-domain-cells = <0>;
912			};
913		};
914
915		sdmmc1_3v3: sdmmc1-3v3 {
916			pins = "sdmmc1";
917			power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
918		};
919
920		sdmmc1_1v8: sdmmc1-1v8 {
921			pins = "sdmmc1";
922			power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
923		};
924
925		sdmmc3_3v3: sdmmc3-3v3 {
926			pins = "sdmmc3";
927			power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
928		};
929
930		sdmmc3_1v8: sdmmc3-1v8 {
931			pins = "sdmmc3";
932			power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
933		};
934
935		pex_dpd_disable: pex_en {
936			pex-dpd-disable {
937				pins = "pex-bias", "pex-clk1", "pex-clk2";
938				low-power-disable;
939			};
940		};
941
942		pex_dpd_enable: pex_dis {
943			pex-dpd-enable {
944				pins = "pex-bias", "pex-clk1", "pex-clk2";
945				low-power-enable;
946			};
947		};
948	};
949
950	fuse@7000f800 {
951		compatible = "nvidia,tegra210-efuse";
952		reg = <0x0 0x7000f800 0x0 0x400>;
953		clocks = <&tegra_car TEGRA210_CLK_FUSE>;
954		clock-names = "fuse";
955		resets = <&tegra_car 39>;
956		reset-names = "fuse";
957	};
958
959	mc: memory-controller@70019000 {
960		compatible = "nvidia,tegra210-mc";
961		reg = <0x0 0x70019000 0x0 0x1000>;
962		clocks = <&tegra_car TEGRA210_CLK_MC>;
963		clock-names = "mc";
964
965		interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
966
967		#iommu-cells = <1>;
968		#reset-cells = <1>;
969	};
970
971	emc: external-memory-controller@7001b000 {
972		compatible = "nvidia,tegra210-emc";
973		reg = <0x0 0x7001b000 0x0 0x1000>,
974		      <0x0 0x7001e000 0x0 0x1000>,
975		      <0x0 0x7001f000 0x0 0x1000>;
976		clocks = <&tegra_car TEGRA210_CLK_EMC>;
977		clock-names = "emc";
978		interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
979		nvidia,memory-controller = <&mc>;
980		#cooling-cells = <2>;
981	};
982
983	sata@70020000 {
984		compatible = "nvidia,tegra210-ahci";
985		reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
986		      <0x0 0x70020000 0x0 0x7000>, /* SATA */
987		      <0x0 0x70001100 0x0 0x1000>; /* SATA AUX */
988		interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
989		clocks = <&tegra_car TEGRA210_CLK_SATA>,
990			 <&tegra_car TEGRA210_CLK_SATA_OOB>;
991		clock-names = "sata", "sata-oob";
992		resets = <&tegra_car 124>,
993			 <&tegra_car 129>,
994			 <&tegra_car 123>;
995		reset-names = "sata", "sata-cold", "sata-oob";
996		status = "disabled";
997	};
998
999	hda@70030000 {
1000		compatible = "nvidia,tegra210-hda", "nvidia,tegra30-hda";
1001		reg = <0x0 0x70030000 0x0 0x10000>;
1002		interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1003		clocks = <&tegra_car TEGRA210_CLK_HDA>,
1004		         <&tegra_car TEGRA210_CLK_HDA2HDMI>,
1005			 <&tegra_car TEGRA210_CLK_HDA2CODEC_2X>;
1006		clock-names = "hda", "hda2hdmi", "hda2codec_2x";
1007		resets = <&tegra_car 125>, /* hda */
1008			 <&tegra_car 128>, /* hda2hdmi */
1009			 <&tegra_car 111>; /* hda2codec_2x */
1010		reset-names = "hda", "hda2hdmi", "hda2codec_2x";
1011		power-domains = <&pd_sor>;
1012		status = "disabled";
1013	};
1014
1015	usb@70090000 {
1016		compatible = "nvidia,tegra210-xusb";
1017		reg = <0x0 0x70090000 0x0 0x8000>,
1018		      <0x0 0x70098000 0x0 0x1000>,
1019		      <0x0 0x70099000 0x0 0x1000>;
1020		reg-names = "hcd", "fpci", "ipfs";
1021
1022		interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
1023			     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1024
1025		clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>,
1026			 <&tegra_car TEGRA210_CLK_XUSB_HOST_SRC>,
1027			 <&tegra_car TEGRA210_CLK_XUSB_FALCON_SRC>,
1028			 <&tegra_car TEGRA210_CLK_XUSB_SS>,
1029			 <&tegra_car TEGRA210_CLK_XUSB_SS_SRC>,
1030			 <&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>,
1031			 <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>,
1032			 <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>,
1033			 <&tegra_car TEGRA210_CLK_PLL_U_480M>,
1034			 <&tegra_car TEGRA210_CLK_CLK_M>,
1035			 <&tegra_car TEGRA210_CLK_PLL_E>;
1036		clock-names = "xusb_host", "xusb_host_src",
1037			      "xusb_falcon_src", "xusb_ss",
1038			      "xusb_ss_src", "xusb_ss_div2",
1039			      "xusb_hs_src", "xusb_fs_src",
1040			      "pll_u_480m", "clk_m", "pll_e";
1041		resets = <&tegra_car 89>, <&tegra_car 156>,
1042			 <&tegra_car 143>;
1043		reset-names = "xusb_host", "xusb_ss", "xusb_src";
1044		power-domains = <&pd_xusbhost>, <&pd_xusbss>;
1045		power-domain-names = "xusb_host", "xusb_ss";
1046
1047		nvidia,xusb-padctl = <&padctl>;
1048
1049		status = "disabled";
1050	};
1051
1052	padctl: padctl@7009f000 {
1053		compatible = "nvidia,tegra210-xusb-padctl";
1054		reg = <0x0 0x7009f000 0x0 0x1000>;
1055		interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1056		resets = <&tegra_car 142>;
1057		reset-names = "padctl";
1058		nvidia,pmc =  <&tegra_pmc>;
1059
1060		status = "disabled";
1061
1062		pads {
1063			usb2 {
1064				clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>;
1065				clock-names = "trk";
1066				status = "disabled";
1067
1068				lanes {
1069					usb2-0 {
1070						status = "disabled";
1071						#phy-cells = <0>;
1072					};
1073
1074					usb2-1 {
1075						status = "disabled";
1076						#phy-cells = <0>;
1077					};
1078
1079					usb2-2 {
1080						status = "disabled";
1081						#phy-cells = <0>;
1082					};
1083
1084					usb2-3 {
1085						status = "disabled";
1086						#phy-cells = <0>;
1087					};
1088				};
1089			};
1090
1091			hsic {
1092				clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>;
1093				clock-names = "trk";
1094				status = "disabled";
1095
1096				lanes {
1097					hsic-0 {
1098						status = "disabled";
1099						#phy-cells = <0>;
1100					};
1101
1102					hsic-1 {
1103						status = "disabled";
1104						#phy-cells = <0>;
1105					};
1106				};
1107			};
1108
1109			pcie {
1110				clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
1111				clock-names = "pll";
1112				resets = <&tegra_car 205>;
1113				reset-names = "phy";
1114				status = "disabled";
1115
1116				lanes {
1117					pcie-0 {
1118						status = "disabled";
1119						#phy-cells = <0>;
1120					};
1121
1122					pcie-1 {
1123						status = "disabled";
1124						#phy-cells = <0>;
1125					};
1126
1127					pcie-2 {
1128						status = "disabled";
1129						#phy-cells = <0>;
1130					};
1131
1132					pcie-3 {
1133						status = "disabled";
1134						#phy-cells = <0>;
1135					};
1136
1137					pcie-4 {
1138						status = "disabled";
1139						#phy-cells = <0>;
1140					};
1141
1142					pcie-5 {
1143						status = "disabled";
1144						#phy-cells = <0>;
1145					};
1146
1147					pcie-6 {
1148						status = "disabled";
1149						#phy-cells = <0>;
1150					};
1151				};
1152			};
1153
1154			sata {
1155				clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
1156				clock-names = "pll";
1157				resets = <&tegra_car 204>;
1158				reset-names = "phy";
1159				status = "disabled";
1160
1161				lanes {
1162					sata-0 {
1163						status = "disabled";
1164						#phy-cells = <0>;
1165					};
1166				};
1167			};
1168		};
1169
1170		ports {
1171			usb2-0 {
1172				status = "disabled";
1173			};
1174
1175			usb2-1 {
1176				status = "disabled";
1177			};
1178
1179			usb2-2 {
1180				status = "disabled";
1181			};
1182
1183			usb2-3 {
1184				status = "disabled";
1185			};
1186
1187			hsic-0 {
1188				status = "disabled";
1189			};
1190
1191			usb3-0 {
1192				status = "disabled";
1193			};
1194
1195			usb3-1 {
1196				status = "disabled";
1197			};
1198
1199			usb3-2 {
1200				status = "disabled";
1201			};
1202
1203			usb3-3 {
1204				status = "disabled";
1205			};
1206		};
1207	};
1208
1209	mmc@700b0000 {
1210		compatible = "nvidia,tegra210-sdhci";
1211		reg = <0x0 0x700b0000 0x0 0x200>;
1212		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1213		clocks = <&tegra_car TEGRA210_CLK_SDMMC1>,
1214			 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>;
1215		clock-names = "sdhci", "tmclk";
1216		resets = <&tegra_car 14>;
1217		reset-names = "sdhci";
1218		pinctrl-names = "sdmmc-3v3", "sdmmc-1v8",
1219				"sdmmc-3v3-drv", "sdmmc-1v8-drv";
1220		pinctrl-0 = <&sdmmc1_3v3>;
1221		pinctrl-1 = <&sdmmc1_1v8>;
1222		pinctrl-2 = <&sdmmc1_3v3_drv>;
1223		pinctrl-3 = <&sdmmc1_1v8_drv>;
1224		nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;
1225		nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;
1226		nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;
1227		nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>;
1228		nvidia,default-tap = <0x2>;
1229		nvidia,default-trim = <0x4>;
1230		assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>,
1231				  <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>,
1232				  <&tegra_car TEGRA210_CLK_PLL_C4>;
1233		assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
1234		assigned-clock-rates = <200000000>, <1000000000>, <1000000000>;
1235		status = "disabled";
1236	};
1237
1238	mmc@700b0200 {
1239		compatible = "nvidia,tegra210-sdhci";
1240		reg = <0x0 0x700b0200 0x0 0x200>;
1241		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1242		clocks = <&tegra_car TEGRA210_CLK_SDMMC2>,
1243			 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>;
1244		clock-names = "sdhci", "tmclk";
1245		resets = <&tegra_car 9>;
1246		reset-names = "sdhci";
1247		pinctrl-names = "sdmmc-1v8-drv";
1248		pinctrl-0 = <&sdmmc2_1v8_drv>;
1249		nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>;
1250		nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>;
1251		nvidia,default-tap = <0x8>;
1252		nvidia,default-trim = <0x0>;
1253		status = "disabled";
1254	};
1255
1256	mmc@700b0400 {
1257		compatible = "nvidia,tegra210-sdhci";
1258		reg = <0x0 0x700b0400 0x0 0x200>;
1259		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1260		clocks = <&tegra_car TEGRA210_CLK_SDMMC3>,
1261			 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>;
1262		clock-names = "sdhci", "tmclk";
1263		resets = <&tegra_car 69>;
1264		reset-names = "sdhci";
1265		pinctrl-names = "sdmmc-3v3", "sdmmc-1v8",
1266				"sdmmc-3v3-drv", "sdmmc-1v8-drv";
1267		pinctrl-0 = <&sdmmc3_3v3>;
1268		pinctrl-1 = <&sdmmc3_1v8>;
1269		pinctrl-2 = <&sdmmc3_3v3_drv>;
1270		pinctrl-3 = <&sdmmc3_1v8_drv>;
1271		nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;
1272		nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;
1273		nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;
1274		nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>;
1275		nvidia,default-tap = <0x3>;
1276		nvidia,default-trim = <0x3>;
1277		status = "disabled";
1278	};
1279
1280	mmc@700b0600 {
1281		compatible = "nvidia,tegra210-sdhci";
1282		reg = <0x0 0x700b0600 0x0 0x200>;
1283		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1284		clocks = <&tegra_car TEGRA210_CLK_SDMMC4>,
1285			 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>;
1286		clock-names = "sdhci", "tmclk";
1287		resets = <&tegra_car 15>;
1288		reset-names = "sdhci";
1289		pinctrl-names = "sdmmc-3v3-drv", "sdmmc-1v8-drv";
1290		pinctrl-0 = <&sdmmc4_1v8_drv>;
1291		pinctrl-1 = <&sdmmc4_1v8_drv>;
1292		nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>;
1293		nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>;
1294		nvidia,default-tap = <0x8>;
1295		nvidia,default-trim = <0x0>;
1296		assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>,
1297				  <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
1298		assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
1299		nvidia,dqs-trim = <40>;
1300		mmc-hs400-1_8v;
1301		status = "disabled";
1302	};
1303
1304	usb@700d0000 {
1305		compatible = "nvidia,tegra210-xudc";
1306		reg = <0x0 0x700d0000 0x0 0x8000>,
1307		      <0x0 0x700d8000 0x0 0x1000>,
1308		      <0x0 0x700d9000 0x0 0x1000>;
1309		reg-names = "base", "fpci", "ipfs";
1310		interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1311		clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>,
1312			 <&tegra_car TEGRA210_CLK_XUSB_SS>,
1313			 <&tegra_car TEGRA210_CLK_XUSB_SSP_SRC>,
1314			 <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>,
1315			 <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>;
1316		clock-names = "dev", "ss", "ss_src", "fs_src", "hs_src";
1317		power-domains = <&pd_xusbdev>, <&pd_xusbss>;
1318		power-domain-names = "dev", "ss";
1319		nvidia,xusb-padctl = <&padctl>;
1320		status = "disabled";
1321	};
1322
1323	soctherm: thermal-sensor@700e2000 {
1324		compatible = "nvidia,tegra210-soctherm";
1325		reg = <0x0 0x700e2000 0x0 0x600>, /* SOC_THERM reg_base */
1326		      <0x0 0x60006000 0x0 0x400>; /* CAR reg_base */
1327		reg-names = "soctherm-reg", "car-reg";
1328		interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
1329			     <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
1330		interrupt-names = "thermal", "edp";
1331		clocks = <&tegra_car TEGRA210_CLK_TSENSOR>,
1332			<&tegra_car TEGRA210_CLK_SOC_THERM>;
1333		clock-names = "tsensor", "soctherm";
1334		resets = <&tegra_car 78>;
1335		reset-names = "soctherm";
1336		#thermal-sensor-cells = <1>;
1337
1338		throttle-cfgs {
1339			throttle_heavy: heavy {
1340				nvidia,priority = <100>;
1341				nvidia,cpu-throt-percent = <85>;
1342				nvidia,gpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_HIGH>;
1343
1344				#cooling-cells = <2>;
1345			};
1346		};
1347	};
1348
1349	mipi: mipi@700e3000 {
1350		compatible = "nvidia,tegra210-mipi";
1351		reg = <0x0 0x700e3000 0x0 0x100>;
1352		clocks = <&tegra_car TEGRA210_CLK_MIPI_CAL>;
1353		clock-names = "mipi-cal";
1354		power-domains = <&pd_sor>;
1355		#nvidia,mipi-calibrate-cells = <1>;
1356	};
1357
1358	dfll: clock@70110000 {
1359		compatible = "nvidia,tegra210-dfll";
1360		reg = <0 0x70110000 0 0x100>, /* DFLL control */
1361		      <0 0x70110000 0 0x100>, /* I2C output control */
1362		      <0 0x70110100 0 0x100>, /* Integrated I2C controller */
1363		      <0 0x70110200 0 0x100>; /* Look-up table RAM */
1364		interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1365		clocks = <&tegra_car TEGRA210_CLK_DFLL_SOC>,
1366			 <&tegra_car TEGRA210_CLK_DFLL_REF>,
1367			 <&tegra_car TEGRA210_CLK_I2C5>;
1368		clock-names = "soc", "ref", "i2c";
1369		resets = <&tegra_car TEGRA210_RST_DFLL_DVCO>;
1370		reset-names = "dvco";
1371		#clock-cells = <0>;
1372		clock-output-names = "dfllCPU_out";
1373		status = "disabled";
1374	};
1375
1376	aconnect@702c0000 {
1377		compatible = "nvidia,tegra210-aconnect";
1378		clocks = <&tegra_car TEGRA210_CLK_APE>,
1379			 <&tegra_car TEGRA210_CLK_APB2APE>;
1380		clock-names = "ape", "apb2ape";
1381		power-domains = <&pd_audio>;
1382		#address-cells = <1>;
1383		#size-cells = <1>;
1384		ranges = <0x702c0000 0x0 0x702c0000 0x00040000>;
1385		status = "disabled";
1386
1387		adma: dma-controller@702e2000 {
1388			compatible = "nvidia,tegra210-adma";
1389			reg = <0x702e2000 0x2000>;
1390			interrupt-parent = <&agic>;
1391			interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
1392				     <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
1393				     <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
1394				     <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
1395				     <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
1396				     <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
1397				     <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
1398				     <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
1399				     <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
1400				     <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
1401				     <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
1402				     <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
1403				     <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
1404				     <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
1405				     <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
1406				     <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
1407				     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
1408				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
1409				     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
1410				     <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
1411				     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
1412				     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1413			#dma-cells = <1>;
1414			clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
1415			clock-names = "d_audio";
1416			status = "disabled";
1417		};
1418
1419		agic: interrupt-controller@702f9000 {
1420			compatible = "nvidia,tegra210-agic";
1421			#interrupt-cells = <3>;
1422			interrupt-controller;
1423			reg = <0x702f9000 0x1000>,
1424			      <0x702fa000 0x2000>;
1425			interrupts = <GIC_SPI 102 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1426			clocks = <&tegra_car TEGRA210_CLK_APE>;
1427			clock-names = "clk";
1428			status = "disabled";
1429		};
1430
1431		tegra_ahub: ahub@702d0800 {
1432			compatible = "nvidia,tegra210-ahub";
1433			reg = <0x702d0800 0x800>;
1434			clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
1435			clock-names = "ahub";
1436			assigned-clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
1437			assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
1438			#address-cells = <1>;
1439			#size-cells = <1>;
1440			ranges = <0x702d0000 0x702d0000 0x0000e400>;
1441			status = "disabled";
1442
1443			tegra_admaif: admaif@702d0000 {
1444				compatible = "nvidia,tegra210-admaif";
1445				reg = <0x702d0000 0x800>;
1446				dmas = <&adma 1>,  <&adma 1>,
1447				       <&adma 2>,  <&adma 2>,
1448				       <&adma 3>,  <&adma 3>,
1449				       <&adma 4>,  <&adma 4>,
1450				       <&adma 5>,  <&adma 5>,
1451				       <&adma 6>,  <&adma 6>,
1452				       <&adma 7>,  <&adma 7>,
1453				       <&adma 8>,  <&adma 8>,
1454				       <&adma 9>,  <&adma 9>,
1455				       <&adma 10>, <&adma 10>;
1456				dma-names = "rx1",  "tx1",
1457					    "rx2",  "tx2",
1458					    "rx3",  "tx3",
1459					    "rx4",  "tx4",
1460					    "rx5",  "tx5",
1461					    "rx6",  "tx6",
1462					    "rx7",  "tx7",
1463					    "rx8",  "tx8",
1464					    "rx9",  "tx9",
1465					    "rx10", "tx10";
1466				status = "disabled";
1467
1468				ports {
1469					#address-cells = <1>;
1470					#size-cells = <0>;
1471
1472					admaif1_port: port@0 {
1473						reg = <0>;
1474
1475						admaif1_ep: endpoint {
1476							remote-endpoint = <&xbar_admaif1_ep>;
1477						};
1478					};
1479
1480					admaif2_port: port@1 {
1481						reg = <1>;
1482
1483						admaif2_ep: endpoint {
1484							remote-endpoint = <&xbar_admaif2_ep>;
1485						};
1486					};
1487
1488					admaif3_port: port@2 {
1489						reg = <2>;
1490
1491						admaif3_ep: endpoint {
1492							remote-endpoint = <&xbar_admaif3_ep>;
1493						};
1494					};
1495
1496					admaif4_port: port@3 {
1497						reg = <3>;
1498
1499						admaif4_ep: endpoint {
1500							remote-endpoint = <&xbar_admaif4_ep>;
1501						};
1502					};
1503
1504					admaif5_port: port@4 {
1505						reg = <4>;
1506
1507						admaif5_ep: endpoint {
1508							remote-endpoint = <&xbar_admaif5_ep>;
1509						};
1510					};
1511
1512					admaif6_port: port@5 {
1513						reg = <5>;
1514
1515						admaif6_ep: endpoint {
1516							remote-endpoint = <&xbar_admaif6_ep>;
1517						};
1518					};
1519
1520					admaif7_port: port@6 {
1521						reg = <6>;
1522
1523						admaif7_ep: endpoint {
1524							remote-endpoint = <&xbar_admaif7_ep>;
1525						};
1526					};
1527
1528					admaif8_port: port@7 {
1529						reg = <7>;
1530
1531						admaif8_ep: endpoint {
1532							remote-endpoint = <&xbar_admaif8_ep>;
1533						};
1534					};
1535
1536					admaif9_port: port@8 {
1537						reg = <8>;
1538
1539						admaif9_ep: endpoint {
1540							remote-endpoint = <&xbar_admaif9_ep>;
1541						};
1542					};
1543
1544					admaif10_port: port@9 {
1545						reg = <9>;
1546
1547						admaif10_ep: endpoint {
1548							remote-endpoint = <&xbar_admaif10_ep>;
1549						};
1550					};
1551				};
1552			};
1553
1554			tegra_i2s1: i2s@702d1000 {
1555				compatible = "nvidia,tegra210-i2s";
1556				reg = <0x702d1000 0x100>;
1557				clocks = <&tegra_car TEGRA210_CLK_I2S0>,
1558					 <&tegra_car TEGRA210_CLK_I2S0_SYNC>;
1559				clock-names = "i2s", "sync_input";
1560				assigned-clocks = <&tegra_car TEGRA210_CLK_I2S0>;
1561				assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
1562				assigned-clock-rates = <1536000>;
1563				sound-name-prefix = "I2S1";
1564				status = "disabled";
1565			};
1566
1567			tegra_i2s2: i2s@702d1100 {
1568				compatible = "nvidia,tegra210-i2s";
1569				reg = <0x702d1100 0x100>;
1570				clocks = <&tegra_car TEGRA210_CLK_I2S1>,
1571					 <&tegra_car TEGRA210_CLK_I2S1_SYNC>;
1572				clock-names = "i2s", "sync_input";
1573				assigned-clocks = <&tegra_car TEGRA210_CLK_I2S1>;
1574				assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
1575				assigned-clock-rates = <1536000>;
1576				sound-name-prefix = "I2S2";
1577				status = "disabled";
1578			};
1579
1580			tegra_i2s3: i2s@702d1200 {
1581				compatible = "nvidia,tegra210-i2s";
1582				reg = <0x702d1200 0x100>;
1583				clocks = <&tegra_car TEGRA210_CLK_I2S2>,
1584					 <&tegra_car TEGRA210_CLK_I2S2_SYNC>;
1585				clock-names = "i2s", "sync_input";
1586				assigned-clocks = <&tegra_car TEGRA210_CLK_I2S2>;
1587				assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
1588				assigned-clock-rates = <1536000>;
1589				sound-name-prefix = "I2S3";
1590				status = "disabled";
1591			};
1592
1593			tegra_i2s4: i2s@702d1300 {
1594				compatible = "nvidia,tegra210-i2s";
1595				reg = <0x702d1300 0x100>;
1596				clocks = <&tegra_car TEGRA210_CLK_I2S3>,
1597					 <&tegra_car TEGRA210_CLK_I2S3_SYNC>;
1598				clock-names = "i2s", "sync_input";
1599				assigned-clocks = <&tegra_car TEGRA210_CLK_I2S3>;
1600				assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
1601				assigned-clock-rates = <1536000>;
1602				sound-name-prefix = "I2S4";
1603				status = "disabled";
1604			};
1605
1606			tegra_i2s5: i2s@702d1400 {
1607				compatible = "nvidia,tegra210-i2s";
1608				reg = <0x702d1400 0x100>;
1609				clocks = <&tegra_car TEGRA210_CLK_I2S4>,
1610					 <&tegra_car TEGRA210_CLK_I2S4_SYNC>;
1611				clock-names = "i2s", "sync_input";
1612				assigned-clocks = <&tegra_car TEGRA210_CLK_I2S4>;
1613				assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
1614				assigned-clock-rates = <1536000>;
1615				sound-name-prefix = "I2S5";
1616				status = "disabled";
1617			};
1618
1619			tegra_dmic1: dmic@702d4000 {
1620				compatible = "nvidia,tegra210-dmic";
1621				reg = <0x702d4000 0x100>;
1622				clocks = <&tegra_car TEGRA210_CLK_DMIC1>;
1623				clock-names = "dmic";
1624				assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC1>;
1625				assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
1626				assigned-clock-rates = <3072000>;
1627				sound-name-prefix = "DMIC1";
1628				status = "disabled";
1629			};
1630
1631			tegra_dmic2: dmic@702d4100 {
1632				compatible = "nvidia,tegra210-dmic";
1633				reg = <0x702d4100 0x100>;
1634				clocks = <&tegra_car TEGRA210_CLK_DMIC2>;
1635				clock-names = "dmic";
1636				assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC2>;
1637				assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
1638				assigned-clock-rates = <3072000>;
1639				sound-name-prefix = "DMIC2";
1640				status = "disabled";
1641			};
1642
1643			tegra_dmic3: dmic@702d4200 {
1644				compatible = "nvidia,tegra210-dmic";
1645				reg = <0x702d4200 0x100>;
1646				clocks = <&tegra_car TEGRA210_CLK_DMIC3>;
1647				clock-names = "dmic";
1648				assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC3>;
1649				assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
1650				assigned-clock-rates = <3072000>;
1651				sound-name-prefix = "DMIC3";
1652				status = "disabled";
1653			};
1654
1655			tegra_sfc1: sfc@702d2000 {
1656				compatible = "nvidia,tegra210-sfc";
1657				reg = <0x702d2000 0x200>;
1658				sound-name-prefix = "SFC1";
1659				status = "disabled";
1660			};
1661
1662			tegra_sfc2: sfc@702d2200 {
1663				compatible = "nvidia,tegra210-sfc";
1664				reg = <0x702d2200 0x200>;
1665				sound-name-prefix = "SFC2";
1666				status = "disabled";
1667			};
1668
1669			tegra_sfc3: sfc@702d2400 {
1670				compatible = "nvidia,tegra210-sfc";
1671				reg = <0x702d2400 0x200>;
1672				sound-name-prefix = "SFC3";
1673				status = "disabled";
1674			};
1675
1676			tegra_sfc4: sfc@702d2600 {
1677				compatible = "nvidia,tegra210-sfc";
1678				reg = <0x702d2600 0x200>;
1679				sound-name-prefix = "SFC4";
1680				status = "disabled";
1681			};
1682
1683			tegra_mvc1: mvc@702da000 {
1684				compatible = "nvidia,tegra210-mvc";
1685				reg = <0x702da000 0x200>;
1686				sound-name-prefix = "MVC1";
1687				status = "disabled";
1688			};
1689
1690			tegra_mvc2: mvc@702da200 {
1691				compatible = "nvidia,tegra210-mvc";
1692				reg = <0x702da200 0x200>;
1693				sound-name-prefix = "MVC2";
1694				status = "disabled";
1695			};
1696
1697			tegra_amx1: amx@702d3000 {
1698				compatible = "nvidia,tegra210-amx";
1699				reg = <0x702d3000 0x100>;
1700				sound-name-prefix = "AMX1";
1701				status = "disabled";
1702			};
1703
1704			tegra_amx2: amx@702d3100 {
1705				compatible = "nvidia,tegra210-amx";
1706				reg = <0x702d3100 0x100>;
1707				sound-name-prefix = "AMX2";
1708				status = "disabled";
1709			};
1710
1711			tegra_adx1: adx@702d3800 {
1712				compatible = "nvidia,tegra210-adx";
1713				reg = <0x702d3800 0x100>;
1714				sound-name-prefix = "ADX1";
1715				status = "disabled";
1716			};
1717
1718			tegra_adx2: adx@702d3900 {
1719				compatible = "nvidia,tegra210-adx";
1720				reg = <0x702d3900 0x100>;
1721				sound-name-prefix = "ADX2";
1722				status = "disabled";
1723			};
1724
1725			tegra_amixer: amixer@702dbb00 {
1726				compatible = "nvidia,tegra210-amixer";
1727				reg = <0x702dbb00 0x800>;
1728				sound-name-prefix = "MIXER1";
1729				status = "disabled";
1730			};
1731
1732			ports {
1733				#address-cells = <1>;
1734				#size-cells = <0>;
1735
1736				port@0 {
1737					reg = <0x0>;
1738
1739					xbar_admaif1_ep: endpoint {
1740						remote-endpoint = <&admaif1_ep>;
1741					};
1742				};
1743
1744				port@1 {
1745					reg = <0x1>;
1746
1747					xbar_admaif2_ep: endpoint {
1748						remote-endpoint = <&admaif2_ep>;
1749					};
1750				};
1751
1752				port@2 {
1753					reg = <0x2>;
1754
1755					xbar_admaif3_ep: endpoint {
1756						remote-endpoint = <&admaif3_ep>;
1757					};
1758				};
1759
1760				port@3 {
1761					reg = <0x3>;
1762
1763					xbar_admaif4_ep: endpoint {
1764						remote-endpoint = <&admaif4_ep>;
1765					};
1766				};
1767
1768				port@4 {
1769					reg = <0x4>;
1770					xbar_admaif5_ep: endpoint {
1771						remote-endpoint = <&admaif5_ep>;
1772					};
1773				};
1774				port@5 {
1775					reg = <0x5>;
1776
1777					xbar_admaif6_ep: endpoint {
1778						remote-endpoint = <&admaif6_ep>;
1779					};
1780				};
1781
1782				port@6 {
1783					reg = <0x6>;
1784
1785					xbar_admaif7_ep: endpoint {
1786						remote-endpoint = <&admaif7_ep>;
1787					};
1788				};
1789
1790				port@7 {
1791					reg = <0x7>;
1792
1793					xbar_admaif8_ep: endpoint {
1794						remote-endpoint = <&admaif8_ep>;
1795					};
1796				};
1797
1798				port@8 {
1799					reg = <0x8>;
1800
1801					xbar_admaif9_ep: endpoint {
1802						remote-endpoint = <&admaif9_ep>;
1803					};
1804				};
1805
1806				port@9 {
1807					reg = <0x9>;
1808
1809					xbar_admaif10_ep: endpoint {
1810						remote-endpoint = <&admaif10_ep>;
1811					};
1812				};
1813			};
1814		};
1815	};
1816
1817	spi@70410000 {
1818		compatible = "nvidia,tegra210-qspi";
1819		reg = <0x0 0x70410000 0x0 0x1000>;
1820		interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1821		#address-cells = <1>;
1822		#size-cells = <0>;
1823		clocks = <&tegra_car TEGRA210_CLK_QSPI>,
1824			 <&tegra_car TEGRA210_CLK_QSPI_PM>;
1825		clock-names = "qspi", "qspi_out";
1826		resets = <&tegra_car 211>;
1827		reset-names = "qspi";
1828		dmas = <&apbdma 5>, <&apbdma 5>;
1829		dma-names = "rx", "tx";
1830		status = "disabled";
1831	};
1832
1833	usb@7d000000 {
1834		compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci";
1835		reg = <0x0 0x7d000000 0x0 0x4000>;
1836		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1837		phy_type = "utmi";
1838		clocks = <&tegra_car TEGRA210_CLK_USBD>;
1839		clock-names = "usb";
1840		resets = <&tegra_car 22>;
1841		reset-names = "usb";
1842		nvidia,phy = <&phy1>;
1843		status = "disabled";
1844	};
1845
1846	phy1: usb-phy@7d000000 {
1847		compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy";
1848		reg = <0x0 0x7d000000 0x0 0x4000>,
1849		      <0x0 0x7d000000 0x0 0x4000>;
1850		phy_type = "utmi";
1851		clocks = <&tegra_car TEGRA210_CLK_USBD>,
1852			 <&tegra_car TEGRA210_CLK_PLL_U>,
1853			 <&tegra_car TEGRA210_CLK_USBD>;
1854		clock-names = "reg", "pll_u", "utmi-pads";
1855		resets = <&tegra_car 22>, <&tegra_car 22>;
1856		reset-names = "usb", "utmi-pads";
1857		nvidia,hssync-start-delay = <0>;
1858		nvidia,idle-wait-delay = <17>;
1859		nvidia,elastic-limit = <16>;
1860		nvidia,term-range-adj = <6>;
1861		nvidia,xcvr-setup = <9>;
1862		nvidia,xcvr-lsfslew = <0>;
1863		nvidia,xcvr-lsrslew = <3>;
1864		nvidia,hssquelch-level = <2>;
1865		nvidia,hsdiscon-level = <5>;
1866		nvidia,xcvr-hsslew = <12>;
1867		nvidia,has-utmi-pad-registers;
1868		status = "disabled";
1869	};
1870
1871	usb@7d004000 {
1872		compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci";
1873		reg = <0x0 0x7d004000 0x0 0x4000>;
1874		interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1875		phy_type = "utmi";
1876		clocks = <&tegra_car TEGRA210_CLK_USB2>;
1877		clock-names = "usb";
1878		resets = <&tegra_car 58>;
1879		reset-names = "usb";
1880		nvidia,phy = <&phy2>;
1881		status = "disabled";
1882	};
1883
1884	phy2: usb-phy@7d004000 {
1885		compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy";
1886		reg = <0x0 0x7d004000 0x0 0x4000>,
1887		      <0x0 0x7d000000 0x0 0x4000>;
1888		phy_type = "utmi";
1889		clocks = <&tegra_car TEGRA210_CLK_USB2>,
1890			 <&tegra_car TEGRA210_CLK_PLL_U>,
1891			 <&tegra_car TEGRA210_CLK_USBD>;
1892		clock-names = "reg", "pll_u", "utmi-pads";
1893		resets = <&tegra_car 58>, <&tegra_car 22>;
1894		reset-names = "usb", "utmi-pads";
1895		nvidia,hssync-start-delay = <0>;
1896		nvidia,idle-wait-delay = <17>;
1897		nvidia,elastic-limit = <16>;
1898		nvidia,term-range-adj = <6>;
1899		nvidia,xcvr-setup = <9>;
1900		nvidia,xcvr-lsfslew = <0>;
1901		nvidia,xcvr-lsrslew = <3>;
1902		nvidia,hssquelch-level = <2>;
1903		nvidia,hsdiscon-level = <5>;
1904		nvidia,xcvr-hsslew = <12>;
1905		status = "disabled";
1906	};
1907
1908	cpus {
1909		#address-cells = <1>;
1910		#size-cells = <0>;
1911
1912		cpu@0 {
1913			device_type = "cpu";
1914			compatible = "arm,cortex-a57";
1915			reg = <0>;
1916			clocks = <&tegra_car TEGRA210_CLK_CCLK_G>,
1917				 <&tegra_car TEGRA210_CLK_PLL_X>,
1918				 <&tegra_car TEGRA210_CLK_PLL_P_OUT4>,
1919				 <&dfll>;
1920			clock-names = "cpu_g", "pll_x", "pll_p", "dfll";
1921			clock-latency = <300000>;
1922			cpu-idle-states = <&CPU_SLEEP>;
1923			next-level-cache = <&L2>;
1924		};
1925
1926		cpu@1 {
1927			device_type = "cpu";
1928			compatible = "arm,cortex-a57";
1929			reg = <1>;
1930			cpu-idle-states = <&CPU_SLEEP>;
1931			next-level-cache = <&L2>;
1932		};
1933
1934		cpu@2 {
1935			device_type = "cpu";
1936			compatible = "arm,cortex-a57";
1937			reg = <2>;
1938			cpu-idle-states = <&CPU_SLEEP>;
1939			next-level-cache = <&L2>;
1940		};
1941
1942		cpu@3 {
1943			device_type = "cpu";
1944			compatible = "arm,cortex-a57";
1945			reg = <3>;
1946			cpu-idle-states = <&CPU_SLEEP>;
1947			next-level-cache = <&L2>;
1948		};
1949
1950		idle-states {
1951			entry-method = "psci";
1952
1953			CPU_SLEEP: cpu-sleep {
1954				compatible = "arm,idle-state";
1955				arm,psci-suspend-param = <0x40000007>;
1956				entry-latency-us = <100>;
1957				exit-latency-us = <30>;
1958				min-residency-us = <1000>;
1959				wakeup-latency-us = <130>;
1960				idle-state-name = "cpu-sleep";
1961				status = "disabled";
1962			};
1963		};
1964
1965		L2: l2-cache {
1966			compatible = "cache";
1967		};
1968	};
1969
1970	pmu {
1971		compatible = "arm,armv8-pmuv3";
1972		interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
1973			     <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1974			     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1975			     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
1976		interrupt-affinity = <&{/cpus/cpu@0} &{/cpus/cpu@1}
1977				      &{/cpus/cpu@2} &{/cpus/cpu@3}>;
1978	};
1979
1980	sound {
1981		status = "disabled";
1982
1983		clocks = <&tegra_car TEGRA210_CLK_PLL_A>,
1984			 <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
1985		clock-names = "pll_a", "plla_out0";
1986
1987		assigned-clocks = <&tegra_car TEGRA210_CLK_PLL_A>,
1988				  <&tegra_car TEGRA210_CLK_PLL_A_OUT0>,
1989				  <&tegra_car TEGRA210_CLK_EXTERN1>;
1990		assigned-clock-parents = <0>, <0>, <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
1991		assigned-clock-rates = <368640000>, <49152000>, <12288000>;
1992	};
1993
1994	thermal-zones {
1995		cpu-thermal {
1996			polling-delay-passive = <1000>;
1997			polling-delay = <0>;
1998
1999			thermal-sensors =
2000				<&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>;
2001
2002			trips {
2003				cpu-shutdown-trip {
2004					temperature = <102500>;
2005					hysteresis = <0>;
2006					type = "critical";
2007				};
2008
2009				cpu_throttle_trip: throttle-trip {
2010					temperature = <98500>;
2011					hysteresis = <1000>;
2012					type = "hot";
2013				};
2014			};
2015
2016			cooling-maps {
2017				map0 {
2018					trip = <&cpu_throttle_trip>;
2019					cooling-device = <&throttle_heavy 1 1>;
2020				};
2021			};
2022		};
2023
2024		mem-thermal {
2025			polling-delay-passive = <0>;
2026			polling-delay = <0>;
2027
2028			thermal-sensors =
2029				<&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>;
2030
2031			trips {
2032				dram_nominal: mem-nominal-trip {
2033					temperature = <50000>;
2034					hysteresis = <1000>;
2035					type = "passive";
2036				};
2037
2038				dram_throttle: mem-throttle-trip {
2039					temperature = <70000>;
2040					hysteresis = <1000>;
2041					type = "active";
2042				};
2043
2044				mem-hot-trip {
2045					temperature = <100000>;
2046					hysteresis = <1000>;
2047					type = "hot";
2048				};
2049
2050				mem-shutdown-trip {
2051					temperature = <103000>;
2052					hysteresis = <0>;
2053					type = "critical";
2054				};
2055			};
2056
2057			cooling-maps {
2058				dram-passive {
2059					cooling-device = <&emc 0 0>;
2060					trip = <&dram_nominal>;
2061				};
2062
2063				dram-active {
2064					cooling-device = <&emc 1 1>;
2065					trip = <&dram_throttle>;
2066				};
2067			};
2068		};
2069
2070		gpu-thermal {
2071			polling-delay-passive = <1000>;
2072			polling-delay = <0>;
2073
2074			thermal-sensors =
2075				<&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>;
2076
2077			trips {
2078				gpu-shutdown-trip {
2079					temperature = <103000>;
2080					hysteresis = <0>;
2081					type = "critical";
2082				};
2083
2084				gpu_throttle_trip: throttle-trip {
2085					temperature = <100000>;
2086					hysteresis = <1000>;
2087					type = "hot";
2088				};
2089			};
2090
2091			cooling-maps {
2092				map0 {
2093					trip = <&gpu_throttle_trip>;
2094					cooling-device = <&throttle_heavy 1 1>;
2095				};
2096			};
2097		};
2098
2099		pllx-thermal {
2100			polling-delay-passive = <0>;
2101			polling-delay = <0>;
2102
2103			thermal-sensors =
2104				<&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>;
2105
2106			trips {
2107				pllx-shutdown-trip {
2108					temperature = <103000>;
2109					hysteresis = <0>;
2110					type = "critical";
2111				};
2112
2113				pllx-throttle-trip {
2114					temperature = <100000>;
2115					hysteresis = <1000>;
2116					type = "hot";
2117				};
2118			};
2119
2120			cooling-maps {
2121				/*
2122				 * There are currently no cooling maps,
2123				 * because there are no cooling devices.
2124				 */
2125			};
2126		};
2127	};
2128
2129	timer {
2130		compatible = "arm,armv8-timer";
2131		interrupts = <GIC_PPI 13
2132				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2133			     <GIC_PPI 14
2134				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2135			     <GIC_PPI 11
2136				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2137			     <GIC_PPI 10
2138				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
2139		interrupt-parent = <&gic>;
2140		arm,no-tick-in-suspend;
2141	};
2142};
2143