1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra210-car.h> 3#include <dt-bindings/gpio/tegra-gpio.h> 4#include <dt-bindings/memory/tegra210-mc.h> 5#include <dt-bindings/pinctrl/pinctrl-tegra.h> 6#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 7#include <dt-bindings/reset/tegra210-car.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/thermal/tegra124-soctherm.h> 10#include <dt-bindings/soc/tegra-pmc.h> 11 12/ { 13 compatible = "nvidia,tegra210"; 14 interrupt-parent = <&lic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 pcie@1003000 { 19 compatible = "nvidia,tegra210-pcie"; 20 device_type = "pci"; 21 reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */ 22 <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */ 23 <0x0 0x02000000 0x0 0x10000000>; /* configuration space */ 24 reg-names = "pads", "afi", "cs"; 25 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 26 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 27 interrupt-names = "intr", "msi"; 28 29 #interrupt-cells = <1>; 30 interrupt-map-mask = <0 0 0 0>; 31 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 32 33 bus-range = <0x00 0xff>; 34 #address-cells = <3>; 35 #size-cells = <2>; 36 37 ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */ 38 <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */ 39 <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */ 40 <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */ 41 <0x42000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ 42 43 clocks = <&tegra_car TEGRA210_CLK_PCIE>, 44 <&tegra_car TEGRA210_CLK_AFI>, 45 <&tegra_car TEGRA210_CLK_PLL_E>, 46 <&tegra_car TEGRA210_CLK_CML0>; 47 clock-names = "pex", "afi", "pll_e", "cml"; 48 resets = <&tegra_car 70>, 49 <&tegra_car 72>, 50 <&tegra_car 74>; 51 reset-names = "pex", "afi", "pcie_x"; 52 53 pinctrl-names = "default", "idle"; 54 pinctrl-0 = <&pex_dpd_disable>; 55 pinctrl-1 = <&pex_dpd_enable>; 56 57 status = "disabled"; 58 59 pci@1,0 { 60 device_type = "pci"; 61 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>; 62 reg = <0x000800 0 0 0 0>; 63 bus-range = <0x00 0xff>; 64 status = "disabled"; 65 66 #address-cells = <3>; 67 #size-cells = <2>; 68 ranges; 69 70 nvidia,num-lanes = <4>; 71 }; 72 73 pci@2,0 { 74 device_type = "pci"; 75 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>; 76 reg = <0x001000 0 0 0 0>; 77 bus-range = <0x00 0xff>; 78 status = "disabled"; 79 80 #address-cells = <3>; 81 #size-cells = <2>; 82 ranges; 83 84 nvidia,num-lanes = <1>; 85 }; 86 }; 87 88 host1x@50000000 { 89 compatible = "nvidia,tegra210-host1x"; 90 reg = <0x0 0x50000000 0x0 0x00034000>; 91 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 92 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ 93 interrupt-names = "syncpt", "host1x"; 94 clocks = <&tegra_car TEGRA210_CLK_HOST1X>; 95 clock-names = "host1x"; 96 resets = <&tegra_car 28>, <&mc TEGRA210_MC_RESET_HC>; 97 reset-names = "host1x", "mc"; 98 99 #address-cells = <2>; 100 #size-cells = <2>; 101 102 ranges = <0x0 0x54000000 0x0 0x54000000 0x0 0x01000000>; 103 104 iommus = <&mc TEGRA_SWGROUP_HC>; 105 106 dpaux1: dpaux@54040000 { 107 compatible = "nvidia,tegra210-dpaux"; 108 reg = <0x0 0x54040000 0x0 0x00040000>; 109 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 110 clocks = <&tegra_car TEGRA210_CLK_DPAUX1>, 111 <&tegra_car TEGRA210_CLK_PLL_DP>; 112 clock-names = "dpaux", "parent"; 113 resets = <&tegra_car 207>; 114 reset-names = "dpaux"; 115 power-domains = <&pd_sor>; 116 status = "disabled"; 117 118 state_dpaux1_aux: pinmux-aux { 119 groups = "dpaux-io"; 120 function = "aux"; 121 }; 122 123 state_dpaux1_i2c: pinmux-i2c { 124 groups = "dpaux-io"; 125 function = "i2c"; 126 }; 127 128 state_dpaux1_off: pinmux-off { 129 groups = "dpaux-io"; 130 function = "off"; 131 }; 132 133 i2c-bus { 134 #address-cells = <1>; 135 #size-cells = <0>; 136 }; 137 }; 138 139 vi@54080000 { 140 compatible = "nvidia,tegra210-vi"; 141 reg = <0x0 0x54080000 0x0 0x700>; 142 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 143 status = "disabled"; 144 assigned-clocks = <&tegra_car TEGRA210_CLK_VI>; 145 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 146 147 clocks = <&tegra_car TEGRA210_CLK_VI>; 148 power-domains = <&pd_venc>; 149 150 #address-cells = <1>; 151 #size-cells = <1>; 152 153 ranges = <0x0 0x0 0x54080000 0x2000>; 154 155 csi@838 { 156 compatible = "nvidia,tegra210-csi"; 157 reg = <0x838 0x1300>; 158 status = "disabled"; 159 assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>, 160 <&tegra_car TEGRA210_CLK_CILCD>, 161 <&tegra_car TEGRA210_CLK_CILE>, 162 <&tegra_car TEGRA210_CLK_CSI_TPG>; 163 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>, 164 <&tegra_car TEGRA210_CLK_PLL_P>, 165 <&tegra_car TEGRA210_CLK_PLL_P>; 166 assigned-clock-rates = <102000000>, 167 <102000000>, 168 <102000000>, 169 <972000000>; 170 171 clocks = <&tegra_car TEGRA210_CLK_CSI>, 172 <&tegra_car TEGRA210_CLK_CILAB>, 173 <&tegra_car TEGRA210_CLK_CILCD>, 174 <&tegra_car TEGRA210_CLK_CILE>, 175 <&tegra_car TEGRA210_CLK_CSI_TPG>; 176 clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg"; 177 power-domains = <&pd_sor>; 178 }; 179 }; 180 181 tsec@54100000 { 182 compatible = "nvidia,tegra210-tsec"; 183 reg = <0x0 0x54100000 0x0 0x00040000>; 184 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 185 clocks = <&tegra_car TEGRA210_CLK_TSEC>; 186 clock-names = "tsec"; 187 resets = <&tegra_car 83>; 188 reset-names = "tsec"; 189 status = "disabled"; 190 }; 191 192 dc@54200000 { 193 compatible = "nvidia,tegra210-dc"; 194 reg = <0x0 0x54200000 0x0 0x00040000>; 195 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 196 clocks = <&tegra_car TEGRA210_CLK_DISP1>; 197 clock-names = "dc"; 198 resets = <&tegra_car 27>; 199 reset-names = "dc"; 200 201 iommus = <&mc TEGRA_SWGROUP_DC>; 202 203 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 204 nvidia,head = <0>; 205 }; 206 207 dc@54240000 { 208 compatible = "nvidia,tegra210-dc"; 209 reg = <0x0 0x54240000 0x0 0x00040000>; 210 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 211 clocks = <&tegra_car TEGRA210_CLK_DISP2>; 212 clock-names = "dc"; 213 resets = <&tegra_car 26>; 214 reset-names = "dc"; 215 216 iommus = <&mc TEGRA_SWGROUP_DCB>; 217 218 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 219 nvidia,head = <1>; 220 }; 221 222 dsia: dsi@54300000 { 223 compatible = "nvidia,tegra210-dsi"; 224 reg = <0x0 0x54300000 0x0 0x00040000>; 225 clocks = <&tegra_car TEGRA210_CLK_DSIA>, 226 <&tegra_car TEGRA210_CLK_DSIALP>, 227 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; 228 clock-names = "dsi", "lp", "parent"; 229 resets = <&tegra_car 48>; 230 reset-names = "dsi"; 231 power-domains = <&pd_sor>; 232 nvidia,mipi-calibrate = <&mipi 0x0c0>; /* DSIA & DSIB pads */ 233 234 status = "disabled"; 235 236 #address-cells = <1>; 237 #size-cells = <0>; 238 }; 239 240 vic@54340000 { 241 compatible = "nvidia,tegra210-vic"; 242 reg = <0x0 0x54340000 0x0 0x00040000>; 243 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 244 clocks = <&tegra_car TEGRA210_CLK_VIC03>; 245 clock-names = "vic"; 246 resets = <&tegra_car 178>; 247 reset-names = "vic"; 248 249 iommus = <&mc TEGRA_SWGROUP_VIC>; 250 power-domains = <&pd_vic>; 251 }; 252 253 nvjpg@54380000 { 254 compatible = "nvidia,tegra210-nvjpg"; 255 reg = <0x0 0x54380000 0x0 0x00040000>; 256 status = "disabled"; 257 }; 258 259 dsib: dsi@54400000 { 260 compatible = "nvidia,tegra210-dsi"; 261 reg = <0x0 0x54400000 0x0 0x00040000>; 262 clocks = <&tegra_car TEGRA210_CLK_DSIB>, 263 <&tegra_car TEGRA210_CLK_DSIBLP>, 264 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; 265 clock-names = "dsi", "lp", "parent"; 266 resets = <&tegra_car 82>; 267 reset-names = "dsi"; 268 power-domains = <&pd_sor>; 269 nvidia,mipi-calibrate = <&mipi 0x300>; /* DSIC & DSID pads */ 270 271 status = "disabled"; 272 273 #address-cells = <1>; 274 #size-cells = <0>; 275 }; 276 277 nvdec@54480000 { 278 compatible = "nvidia,tegra210-nvdec"; 279 reg = <0x0 0x54480000 0x0 0x00040000>; 280 status = "disabled"; 281 }; 282 283 nvenc@544c0000 { 284 compatible = "nvidia,tegra210-nvenc"; 285 reg = <0x0 0x544c0000 0x0 0x00040000>; 286 status = "disabled"; 287 }; 288 289 tsec@54500000 { 290 compatible = "nvidia,tegra210-tsec"; 291 reg = <0x0 0x54500000 0x0 0x00040000>; 292 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 293 clocks = <&tegra_car TEGRA210_CLK_TSECB>; 294 clock-names = "tsec"; 295 resets = <&tegra_car 206>; 296 reset-names = "tsec"; 297 status = "disabled"; 298 }; 299 300 sor0: sor@54540000 { 301 compatible = "nvidia,tegra210-sor"; 302 reg = <0x0 0x54540000 0x0 0x00040000>; 303 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 304 clocks = <&tegra_car TEGRA210_CLK_SOR0>, 305 <&tegra_car TEGRA210_CLK_SOR0_OUT>, 306 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>, 307 <&tegra_car TEGRA210_CLK_PLL_DP>, 308 <&tegra_car TEGRA210_CLK_SOR_SAFE>; 309 clock-names = "sor", "out", "parent", "dp", "safe"; 310 resets = <&tegra_car 182>; 311 reset-names = "sor"; 312 pinctrl-0 = <&state_dpaux_aux>; 313 pinctrl-1 = <&state_dpaux_i2c>; 314 pinctrl-2 = <&state_dpaux_off>; 315 pinctrl-names = "aux", "i2c", "off"; 316 power-domains = <&pd_sor>; 317 status = "disabled"; 318 }; 319 320 sor1: sor@54580000 { 321 compatible = "nvidia,tegra210-sor1"; 322 reg = <0x0 0x54580000 0x0 0x00040000>; 323 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 324 clocks = <&tegra_car TEGRA210_CLK_SOR1>, 325 <&tegra_car TEGRA210_CLK_SOR1_OUT>, 326 <&tegra_car TEGRA210_CLK_PLL_D2_OUT0>, 327 <&tegra_car TEGRA210_CLK_PLL_DP>, 328 <&tegra_car TEGRA210_CLK_SOR_SAFE>; 329 clock-names = "sor", "out", "parent", "dp", "safe"; 330 resets = <&tegra_car 183>; 331 reset-names = "sor"; 332 pinctrl-0 = <&state_dpaux1_aux>; 333 pinctrl-1 = <&state_dpaux1_i2c>; 334 pinctrl-2 = <&state_dpaux1_off>; 335 pinctrl-names = "aux", "i2c", "off"; 336 power-domains = <&pd_sor>; 337 status = "disabled"; 338 }; 339 340 dpaux: dpaux@545c0000 { 341 compatible = "nvidia,tegra210-dpaux"; 342 reg = <0x0 0x545c0000 0x0 0x00040000>; 343 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 344 clocks = <&tegra_car TEGRA210_CLK_DPAUX>, 345 <&tegra_car TEGRA210_CLK_PLL_DP>; 346 clock-names = "dpaux", "parent"; 347 resets = <&tegra_car 181>; 348 reset-names = "dpaux"; 349 power-domains = <&pd_sor>; 350 status = "disabled"; 351 352 state_dpaux_aux: pinmux-aux { 353 groups = "dpaux-io"; 354 function = "aux"; 355 }; 356 357 state_dpaux_i2c: pinmux-i2c { 358 groups = "dpaux-io"; 359 function = "i2c"; 360 }; 361 362 state_dpaux_off: pinmux-off { 363 groups = "dpaux-io"; 364 function = "off"; 365 }; 366 367 i2c-bus { 368 #address-cells = <1>; 369 #size-cells = <0>; 370 }; 371 }; 372 373 isp@54600000 { 374 compatible = "nvidia,tegra210-isp"; 375 reg = <0x0 0x54600000 0x0 0x00040000>; 376 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 377 clocks = <&tegra_car TEGRA210_CLK_ISPA>; 378 resets = <&tegra_car 23>; 379 reset-names = "isp"; 380 status = "disabled"; 381 }; 382 383 isp@54680000 { 384 compatible = "nvidia,tegra210-isp"; 385 reg = <0x0 0x54680000 0x0 0x00040000>; 386 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 387 clocks = <&tegra_car TEGRA210_CLK_ISPB>; 388 resets = <&tegra_car 3>; 389 reset-names = "isp"; 390 status = "disabled"; 391 }; 392 393 i2c@546c0000 { 394 compatible = "nvidia,tegra210-i2c-vi"; 395 reg = <0x0 0x546c0000 0x0 0x00040000>; 396 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 397 clocks = <&tegra_car TEGRA210_CLK_VI_I2C>, 398 <&tegra_car TEGRA210_CLK_I2CSLOW>; 399 clock-names = "div-clk", "slow"; 400 resets = <&tegra_car 208>; 401 reset-names = "i2c"; 402 power-domains = <&pd_venc>; 403 status = "disabled"; 404 405 #address-cells = <1>; 406 #size-cells = <0>; 407 }; 408 }; 409 410 gic: interrupt-controller@50041000 { 411 compatible = "arm,gic-400"; 412 #interrupt-cells = <3>; 413 interrupt-controller; 414 reg = <0x0 0x50041000 0x0 0x1000>, 415 <0x0 0x50042000 0x0 0x2000>, 416 <0x0 0x50044000 0x0 0x2000>, 417 <0x0 0x50046000 0x0 0x2000>; 418 interrupts = <GIC_PPI 9 419 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 420 interrupt-parent = <&gic>; 421 }; 422 423 gpu@57000000 { 424 compatible = "nvidia,gm20b"; 425 reg = <0x0 0x57000000 0x0 0x01000000>, 426 <0x0 0x58000000 0x0 0x01000000>; 427 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 428 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 429 interrupt-names = "stall", "nonstall"; 430 clocks = <&tegra_car TEGRA210_CLK_GPU>, 431 <&tegra_car TEGRA210_CLK_PLL_P_OUT5>, 432 <&tegra_car TEGRA210_CLK_PLL_G_REF>; 433 clock-names = "gpu", "pwr", "ref"; 434 resets = <&tegra_car 184>; 435 reset-names = "gpu"; 436 437 iommus = <&mc TEGRA_SWGROUP_GPU>; 438 439 status = "disabled"; 440 }; 441 442 lic: interrupt-controller@60004000 { 443 compatible = "nvidia,tegra210-ictlr"; 444 reg = <0x0 0x60004000 0x0 0x40>, /* primary controller */ 445 <0x0 0x60004100 0x0 0x40>, /* secondary controller */ 446 <0x0 0x60004200 0x0 0x40>, /* tertiary controller */ 447 <0x0 0x60004300 0x0 0x40>, /* quaternary controller */ 448 <0x0 0x60004400 0x0 0x40>, /* quinary controller */ 449 <0x0 0x60004500 0x0 0x40>; /* senary controller */ 450 interrupt-controller; 451 #interrupt-cells = <3>; 452 interrupt-parent = <&gic>; 453 }; 454 455 timer@60005000 { 456 compatible = "nvidia,tegra210-timer"; 457 reg = <0x0 0x60005000 0x0 0x400>; 458 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 459 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 460 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 461 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 462 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 463 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 464 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 465 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 466 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 467 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 468 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 469 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 470 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, 471 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 472 clocks = <&tegra_car TEGRA210_CLK_TIMER>; 473 clock-names = "timer"; 474 }; 475 476 tegra_car: clock@60006000 { 477 compatible = "nvidia,tegra210-car"; 478 reg = <0x0 0x60006000 0x0 0x1000>; 479 #clock-cells = <1>; 480 #reset-cells = <1>; 481 }; 482 483 flow-controller@60007000 { 484 compatible = "nvidia,tegra210-flowctrl"; 485 reg = <0x0 0x60007000 0x0 0x1000>; 486 }; 487 488 gpio: gpio@6000d000 { 489 compatible = "nvidia,tegra210-gpio", "nvidia,tegra30-gpio"; 490 reg = <0x0 0x6000d000 0x0 0x1000>; 491 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 492 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 493 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 494 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 495 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 496 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 497 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 498 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 499 #gpio-cells = <2>; 500 gpio-controller; 501 #interrupt-cells = <2>; 502 interrupt-controller; 503 }; 504 505 apbdma: dma@60020000 { 506 compatible = "nvidia,tegra210-apbdma", "nvidia,tegra148-apbdma"; 507 reg = <0x0 0x60020000 0x0 0x1400>; 508 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 509 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 510 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 511 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 512 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 513 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 514 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 515 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 516 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 517 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 518 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 519 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 520 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 521 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 522 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 523 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 524 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 525 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 526 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 527 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 528 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 529 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 530 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 531 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 532 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 533 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 534 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 535 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 536 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 537 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 538 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 539 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 540 clocks = <&tegra_car TEGRA210_CLK_APBDMA>; 541 clock-names = "dma"; 542 resets = <&tegra_car 34>; 543 reset-names = "dma"; 544 #dma-cells = <1>; 545 }; 546 547 apbmisc@70000800 { 548 compatible = "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc"; 549 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */ 550 <0x0 0x70000008 0x0 0x04>; /* Strapping options */ 551 }; 552 553 pinmux: pinmux@700008d4 { 554 compatible = "nvidia,tegra210-pinmux"; 555 reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */ 556 <0x0 0x70003000 0x0 0x294>; /* Mux registers */ 557 sdmmc1_3v3_drv: sdmmc1-3v3-drv { 558 sdmmc1 { 559 nvidia,pins = "drive_sdmmc1"; 560 nvidia,pull-down-strength = <0x8>; 561 nvidia,pull-up-strength = <0x8>; 562 }; 563 }; 564 sdmmc1_1v8_drv: sdmmc1-1v8-drv { 565 sdmmc1 { 566 nvidia,pins = "drive_sdmmc1"; 567 nvidia,pull-down-strength = <0x4>; 568 nvidia,pull-up-strength = <0x3>; 569 }; 570 }; 571 sdmmc2_1v8_drv: sdmmc2-1v8-drv { 572 sdmmc2 { 573 nvidia,pins = "drive_sdmmc2"; 574 nvidia,pull-down-strength = <0x10>; 575 nvidia,pull-up-strength = <0x10>; 576 }; 577 }; 578 sdmmc3_3v3_drv: sdmmc3-3v3-drv { 579 sdmmc3 { 580 nvidia,pins = "drive_sdmmc3"; 581 nvidia,pull-down-strength = <0x8>; 582 nvidia,pull-up-strength = <0x8>; 583 }; 584 }; 585 sdmmc3_1v8_drv: sdmmc3-1v8-drv { 586 sdmmc3 { 587 nvidia,pins = "drive_sdmmc3"; 588 nvidia,pull-down-strength = <0x4>; 589 nvidia,pull-up-strength = <0x3>; 590 }; 591 }; 592 sdmmc4_1v8_drv: sdmmc4-1v8-drv { 593 sdmmc4 { 594 nvidia,pins = "drive_sdmmc4"; 595 nvidia,pull-down-strength = <0x10>; 596 nvidia,pull-up-strength = <0x10>; 597 }; 598 }; 599 }; 600 601 /* 602 * There are two serial driver i.e. 8250 based simple serial 603 * driver and APB DMA based serial driver for higher baudrate 604 * and performance. To enable the 8250 based driver, the compatible 605 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable 606 * the APB DMA based serial driver, the compatible is 607 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". 608 */ 609 uarta: serial@70006000 { 610 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 611 reg = <0x0 0x70006000 0x0 0x40>; 612 reg-shift = <2>; 613 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 614 clocks = <&tegra_car TEGRA210_CLK_UARTA>; 615 clock-names = "serial"; 616 resets = <&tegra_car 6>; 617 reset-names = "serial"; 618 dmas = <&apbdma 8>, <&apbdma 8>; 619 dma-names = "rx", "tx"; 620 status = "disabled"; 621 }; 622 623 uartb: serial@70006040 { 624 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 625 reg = <0x0 0x70006040 0x0 0x40>; 626 reg-shift = <2>; 627 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 628 clocks = <&tegra_car TEGRA210_CLK_UARTB>; 629 clock-names = "serial"; 630 resets = <&tegra_car 7>; 631 reset-names = "serial"; 632 dmas = <&apbdma 9>, <&apbdma 9>; 633 dma-names = "rx", "tx"; 634 status = "disabled"; 635 }; 636 637 uartc: serial@70006200 { 638 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 639 reg = <0x0 0x70006200 0x0 0x40>; 640 reg-shift = <2>; 641 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 642 clocks = <&tegra_car TEGRA210_CLK_UARTC>; 643 clock-names = "serial"; 644 resets = <&tegra_car 55>; 645 reset-names = "serial"; 646 dmas = <&apbdma 10>, <&apbdma 10>; 647 dma-names = "rx", "tx"; 648 status = "disabled"; 649 }; 650 651 uartd: serial@70006300 { 652 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 653 reg = <0x0 0x70006300 0x0 0x40>; 654 reg-shift = <2>; 655 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 656 clocks = <&tegra_car TEGRA210_CLK_UARTD>; 657 clock-names = "serial"; 658 resets = <&tegra_car 65>; 659 reset-names = "serial"; 660 dmas = <&apbdma 19>, <&apbdma 19>; 661 dma-names = "rx", "tx"; 662 status = "disabled"; 663 }; 664 665 pwm: pwm@7000a000 { 666 compatible = "nvidia,tegra210-pwm", "nvidia,tegra20-pwm"; 667 reg = <0x0 0x7000a000 0x0 0x100>; 668 #pwm-cells = <2>; 669 clocks = <&tegra_car TEGRA210_CLK_PWM>; 670 resets = <&tegra_car 17>; 671 reset-names = "pwm"; 672 status = "disabled"; 673 }; 674 675 i2c@7000c000 { 676 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 677 reg = <0x0 0x7000c000 0x0 0x100>; 678 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 679 #address-cells = <1>; 680 #size-cells = <0>; 681 clocks = <&tegra_car TEGRA210_CLK_I2C1>; 682 clock-names = "div-clk"; 683 resets = <&tegra_car 12>; 684 reset-names = "i2c"; 685 dmas = <&apbdma 21>, <&apbdma 21>; 686 dma-names = "rx", "tx"; 687 status = "disabled"; 688 }; 689 690 i2c@7000c400 { 691 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 692 reg = <0x0 0x7000c400 0x0 0x100>; 693 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 694 #address-cells = <1>; 695 #size-cells = <0>; 696 clocks = <&tegra_car TEGRA210_CLK_I2C2>; 697 clock-names = "div-clk"; 698 resets = <&tegra_car 54>; 699 reset-names = "i2c"; 700 dmas = <&apbdma 22>, <&apbdma 22>; 701 dma-names = "rx", "tx"; 702 status = "disabled"; 703 }; 704 705 i2c@7000c500 { 706 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 707 reg = <0x0 0x7000c500 0x0 0x100>; 708 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 709 #address-cells = <1>; 710 #size-cells = <0>; 711 clocks = <&tegra_car TEGRA210_CLK_I2C3>; 712 clock-names = "div-clk"; 713 resets = <&tegra_car 67>; 714 reset-names = "i2c"; 715 dmas = <&apbdma 23>, <&apbdma 23>; 716 dma-names = "rx", "tx"; 717 status = "disabled"; 718 }; 719 720 i2c@7000c700 { 721 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 722 reg = <0x0 0x7000c700 0x0 0x100>; 723 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 724 #address-cells = <1>; 725 #size-cells = <0>; 726 clocks = <&tegra_car TEGRA210_CLK_I2C4>; 727 clock-names = "div-clk"; 728 resets = <&tegra_car 103>; 729 reset-names = "i2c"; 730 dmas = <&apbdma 26>, <&apbdma 26>; 731 dma-names = "rx", "tx"; 732 pinctrl-0 = <&state_dpaux1_i2c>; 733 pinctrl-1 = <&state_dpaux1_off>; 734 pinctrl-names = "default", "idle"; 735 status = "disabled"; 736 }; 737 738 i2c@7000d000 { 739 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 740 reg = <0x0 0x7000d000 0x0 0x100>; 741 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 742 #address-cells = <1>; 743 #size-cells = <0>; 744 clocks = <&tegra_car TEGRA210_CLK_I2C5>; 745 clock-names = "div-clk"; 746 resets = <&tegra_car 47>; 747 reset-names = "i2c"; 748 dmas = <&apbdma 24>, <&apbdma 24>; 749 dma-names = "rx", "tx"; 750 status = "disabled"; 751 }; 752 753 i2c@7000d100 { 754 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 755 reg = <0x0 0x7000d100 0x0 0x100>; 756 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 757 #address-cells = <1>; 758 #size-cells = <0>; 759 clocks = <&tegra_car TEGRA210_CLK_I2C6>; 760 clock-names = "div-clk"; 761 resets = <&tegra_car 166>; 762 reset-names = "i2c"; 763 dmas = <&apbdma 30>, <&apbdma 30>; 764 dma-names = "rx", "tx"; 765 pinctrl-0 = <&state_dpaux_i2c>; 766 pinctrl-1 = <&state_dpaux_off>; 767 pinctrl-names = "default", "idle"; 768 status = "disabled"; 769 }; 770 771 spi@7000d400 { 772 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 773 reg = <0x0 0x7000d400 0x0 0x200>; 774 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 775 #address-cells = <1>; 776 #size-cells = <0>; 777 clocks = <&tegra_car TEGRA210_CLK_SBC1>; 778 clock-names = "spi"; 779 resets = <&tegra_car 41>; 780 reset-names = "spi"; 781 dmas = <&apbdma 15>, <&apbdma 15>; 782 dma-names = "rx", "tx"; 783 status = "disabled"; 784 }; 785 786 spi@7000d600 { 787 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 788 reg = <0x0 0x7000d600 0x0 0x200>; 789 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 790 #address-cells = <1>; 791 #size-cells = <0>; 792 clocks = <&tegra_car TEGRA210_CLK_SBC2>; 793 clock-names = "spi"; 794 resets = <&tegra_car 44>; 795 reset-names = "spi"; 796 dmas = <&apbdma 16>, <&apbdma 16>; 797 dma-names = "rx", "tx"; 798 status = "disabled"; 799 }; 800 801 spi@7000d800 { 802 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 803 reg = <0x0 0x7000d800 0x0 0x200>; 804 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 805 #address-cells = <1>; 806 #size-cells = <0>; 807 clocks = <&tegra_car TEGRA210_CLK_SBC3>; 808 clock-names = "spi"; 809 resets = <&tegra_car 46>; 810 reset-names = "spi"; 811 dmas = <&apbdma 17>, <&apbdma 17>; 812 dma-names = "rx", "tx"; 813 status = "disabled"; 814 }; 815 816 spi@7000da00 { 817 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 818 reg = <0x0 0x7000da00 0x0 0x200>; 819 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 820 #address-cells = <1>; 821 #size-cells = <0>; 822 clocks = <&tegra_car TEGRA210_CLK_SBC4>; 823 clock-names = "spi"; 824 resets = <&tegra_car 68>; 825 reset-names = "spi"; 826 dmas = <&apbdma 18>, <&apbdma 18>; 827 dma-names = "rx", "tx"; 828 status = "disabled"; 829 }; 830 831 rtc@7000e000 { 832 compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc"; 833 reg = <0x0 0x7000e000 0x0 0x100>; 834 interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; 835 interrupt-parent = <&tegra_pmc>; 836 clocks = <&tegra_car TEGRA210_CLK_RTC>; 837 clock-names = "rtc"; 838 }; 839 840 tegra_pmc: pmc@7000e400 { 841 compatible = "nvidia,tegra210-pmc"; 842 reg = <0x0 0x7000e400 0x0 0x400>; 843 clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; 844 clock-names = "pclk", "clk32k_in"; 845 #clock-cells = <1>; 846 #interrupt-cells = <2>; 847 interrupt-controller; 848 849 powergates { 850 pd_audio: aud { 851 clocks = <&tegra_car TEGRA210_CLK_APE>, 852 <&tegra_car TEGRA210_CLK_APB2APE>; 853 resets = <&tegra_car 198>; 854 #power-domain-cells = <0>; 855 }; 856 857 pd_sor: sor { 858 clocks = <&tegra_car TEGRA210_CLK_SOR0>, 859 <&tegra_car TEGRA210_CLK_SOR1>, 860 <&tegra_car TEGRA210_CLK_CILAB>, 861 <&tegra_car TEGRA210_CLK_CILCD>, 862 <&tegra_car TEGRA210_CLK_CILE>, 863 <&tegra_car TEGRA210_CLK_DSIA>, 864 <&tegra_car TEGRA210_CLK_DSIB>, 865 <&tegra_car TEGRA210_CLK_DPAUX>, 866 <&tegra_car TEGRA210_CLK_DPAUX1>, 867 <&tegra_car TEGRA210_CLK_MIPI_CAL>; 868 resets = <&tegra_car TEGRA210_CLK_SOR0>, 869 <&tegra_car TEGRA210_CLK_SOR1>, 870 <&tegra_car TEGRA210_CLK_DSIA>, 871 <&tegra_car TEGRA210_CLK_DSIB>, 872 <&tegra_car TEGRA210_CLK_DPAUX>, 873 <&tegra_car TEGRA210_CLK_DPAUX1>, 874 <&tegra_car TEGRA210_CLK_MIPI_CAL>; 875 #power-domain-cells = <0>; 876 }; 877 878 pd_xusbss: xusba { 879 clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>; 880 resets = <&tegra_car TEGRA210_CLK_XUSB_SS>; 881 #power-domain-cells = <0>; 882 }; 883 884 pd_xusbdev: xusbb { 885 clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>; 886 resets = <&tegra_car 95>; 887 #power-domain-cells = <0>; 888 }; 889 890 pd_xusbhost: xusbc { 891 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>; 892 resets = <&tegra_car TEGRA210_CLK_XUSB_HOST>; 893 #power-domain-cells = <0>; 894 }; 895 896 pd_vic: vic { 897 clocks = <&tegra_car TEGRA210_CLK_VIC03>; 898 clock-names = "vic"; 899 resets = <&tegra_car 178>; 900 reset-names = "vic"; 901 #power-domain-cells = <0>; 902 }; 903 904 pd_venc: venc { 905 clocks = <&tegra_car TEGRA210_CLK_VI>, 906 <&tegra_car TEGRA210_CLK_CSI>; 907 resets = <&mc TEGRA210_MC_RESET_VI>, 908 <&tegra_car 20>, 909 <&tegra_car 52>; 910 #power-domain-cells = <0>; 911 }; 912 }; 913 914 sdmmc1_3v3: sdmmc1-3v3 { 915 pins = "sdmmc1"; 916 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 917 }; 918 919 sdmmc1_1v8: sdmmc1-1v8 { 920 pins = "sdmmc1"; 921 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 922 }; 923 924 sdmmc3_3v3: sdmmc3-3v3 { 925 pins = "sdmmc3"; 926 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 927 }; 928 929 sdmmc3_1v8: sdmmc3-1v8 { 930 pins = "sdmmc3"; 931 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 932 }; 933 934 pex_dpd_disable: pex_en { 935 pex-dpd-disable { 936 pins = "pex-bias", "pex-clk1", "pex-clk2"; 937 low-power-disable; 938 }; 939 }; 940 941 pex_dpd_enable: pex_dis { 942 pex-dpd-enable { 943 pins = "pex-bias", "pex-clk1", "pex-clk2"; 944 low-power-enable; 945 }; 946 }; 947 }; 948 949 fuse@7000f800 { 950 compatible = "nvidia,tegra210-efuse"; 951 reg = <0x0 0x7000f800 0x0 0x400>; 952 clocks = <&tegra_car TEGRA210_CLK_FUSE>; 953 clock-names = "fuse"; 954 resets = <&tegra_car 39>; 955 reset-names = "fuse"; 956 }; 957 958 mc: memory-controller@70019000 { 959 compatible = "nvidia,tegra210-mc"; 960 reg = <0x0 0x70019000 0x0 0x1000>; 961 clocks = <&tegra_car TEGRA210_CLK_MC>; 962 clock-names = "mc"; 963 964 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 965 966 #iommu-cells = <1>; 967 #reset-cells = <1>; 968 }; 969 970 emc: external-memory-controller@7001b000 { 971 compatible = "nvidia,tegra210-emc"; 972 reg = <0x0 0x7001b000 0x0 0x1000>, 973 <0x0 0x7001e000 0x0 0x1000>, 974 <0x0 0x7001f000 0x0 0x1000>; 975 clocks = <&tegra_car TEGRA210_CLK_EMC>; 976 clock-names = "emc"; 977 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 978 nvidia,memory-controller = <&mc>; 979 #cooling-cells = <2>; 980 }; 981 982 sata@70020000 { 983 compatible = "nvidia,tegra210-ahci"; 984 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */ 985 <0x0 0x70020000 0x0 0x7000>, /* SATA */ 986 <0x0 0x70001100 0x0 0x1000>; /* SATA AUX */ 987 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 988 clocks = <&tegra_car TEGRA210_CLK_SATA>, 989 <&tegra_car TEGRA210_CLK_SATA_OOB>; 990 clock-names = "sata", "sata-oob"; 991 resets = <&tegra_car 124>, 992 <&tegra_car 129>, 993 <&tegra_car 123>; 994 reset-names = "sata", "sata-cold", "sata-oob"; 995 status = "disabled"; 996 }; 997 998 hda@70030000 { 999 compatible = "nvidia,tegra210-hda", "nvidia,tegra30-hda"; 1000 reg = <0x0 0x70030000 0x0 0x10000>; 1001 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 1002 clocks = <&tegra_car TEGRA210_CLK_HDA>, 1003 <&tegra_car TEGRA210_CLK_HDA2HDMI>, 1004 <&tegra_car TEGRA210_CLK_HDA2CODEC_2X>; 1005 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 1006 resets = <&tegra_car 125>, /* hda */ 1007 <&tegra_car 128>, /* hda2hdmi */ 1008 <&tegra_car 111>; /* hda2codec_2x */ 1009 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 1010 power-domains = <&pd_sor>; 1011 status = "disabled"; 1012 }; 1013 1014 usb@70090000 { 1015 compatible = "nvidia,tegra210-xusb"; 1016 reg = <0x0 0x70090000 0x0 0x8000>, 1017 <0x0 0x70098000 0x0 0x1000>, 1018 <0x0 0x70099000 0x0 0x1000>; 1019 reg-names = "hcd", "fpci", "ipfs"; 1020 1021 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 1022 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 1023 1024 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>, 1025 <&tegra_car TEGRA210_CLK_XUSB_HOST_SRC>, 1026 <&tegra_car TEGRA210_CLK_XUSB_FALCON_SRC>, 1027 <&tegra_car TEGRA210_CLK_XUSB_SS>, 1028 <&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>, 1029 <&tegra_car TEGRA210_CLK_XUSB_SS_SRC>, 1030 <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>, 1031 <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>, 1032 <&tegra_car TEGRA210_CLK_PLL_U_480M>, 1033 <&tegra_car TEGRA210_CLK_CLK_M>, 1034 <&tegra_car TEGRA210_CLK_PLL_E>; 1035 clock-names = "xusb_host", "xusb_host_src", 1036 "xusb_falcon_src", "xusb_ss", 1037 "xusb_ss_div2", "xusb_ss_src", 1038 "xusb_hs_src", "xusb_fs_src", 1039 "pll_u_480m", "clk_m", "pll_e"; 1040 resets = <&tegra_car 89>, <&tegra_car 156>, 1041 <&tegra_car 143>; 1042 reset-names = "xusb_host", "xusb_ss", "xusb_src"; 1043 power-domains = <&pd_xusbhost>, <&pd_xusbss>; 1044 power-domain-names = "xusb_host", "xusb_ss"; 1045 1046 nvidia,xusb-padctl = <&padctl>; 1047 1048 status = "disabled"; 1049 }; 1050 1051 padctl: padctl@7009f000 { 1052 compatible = "nvidia,tegra210-xusb-padctl"; 1053 reg = <0x0 0x7009f000 0x0 0x1000>; 1054 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 1055 resets = <&tegra_car 142>; 1056 reset-names = "padctl"; 1057 nvidia,pmc = <&tegra_pmc>; 1058 1059 status = "disabled"; 1060 1061 pads { 1062 usb2 { 1063 clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>; 1064 clock-names = "trk"; 1065 status = "disabled"; 1066 1067 lanes { 1068 usb2-0 { 1069 status = "disabled"; 1070 #phy-cells = <0>; 1071 }; 1072 1073 usb2-1 { 1074 status = "disabled"; 1075 #phy-cells = <0>; 1076 }; 1077 1078 usb2-2 { 1079 status = "disabled"; 1080 #phy-cells = <0>; 1081 }; 1082 1083 usb2-3 { 1084 status = "disabled"; 1085 #phy-cells = <0>; 1086 }; 1087 }; 1088 }; 1089 1090 hsic { 1091 clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>; 1092 clock-names = "trk"; 1093 status = "disabled"; 1094 1095 lanes { 1096 hsic-0 { 1097 status = "disabled"; 1098 #phy-cells = <0>; 1099 }; 1100 1101 hsic-1 { 1102 status = "disabled"; 1103 #phy-cells = <0>; 1104 }; 1105 }; 1106 }; 1107 1108 pcie { 1109 clocks = <&tegra_car TEGRA210_CLK_PLL_E>; 1110 clock-names = "pll"; 1111 resets = <&tegra_car 205>; 1112 reset-names = "phy"; 1113 status = "disabled"; 1114 1115 lanes { 1116 pcie-0 { 1117 status = "disabled"; 1118 #phy-cells = <0>; 1119 }; 1120 1121 pcie-1 { 1122 status = "disabled"; 1123 #phy-cells = <0>; 1124 }; 1125 1126 pcie-2 { 1127 status = "disabled"; 1128 #phy-cells = <0>; 1129 }; 1130 1131 pcie-3 { 1132 status = "disabled"; 1133 #phy-cells = <0>; 1134 }; 1135 1136 pcie-4 { 1137 status = "disabled"; 1138 #phy-cells = <0>; 1139 }; 1140 1141 pcie-5 { 1142 status = "disabled"; 1143 #phy-cells = <0>; 1144 }; 1145 1146 pcie-6 { 1147 status = "disabled"; 1148 #phy-cells = <0>; 1149 }; 1150 }; 1151 }; 1152 1153 sata { 1154 clocks = <&tegra_car TEGRA210_CLK_PLL_E>; 1155 clock-names = "pll"; 1156 resets = <&tegra_car 204>; 1157 reset-names = "phy"; 1158 status = "disabled"; 1159 1160 lanes { 1161 sata-0 { 1162 status = "disabled"; 1163 #phy-cells = <0>; 1164 }; 1165 }; 1166 }; 1167 }; 1168 1169 ports { 1170 usb2-0 { 1171 status = "disabled"; 1172 }; 1173 1174 usb2-1 { 1175 status = "disabled"; 1176 }; 1177 1178 usb2-2 { 1179 status = "disabled"; 1180 }; 1181 1182 usb2-3 { 1183 status = "disabled"; 1184 }; 1185 1186 hsic-0 { 1187 status = "disabled"; 1188 }; 1189 1190 usb3-0 { 1191 status = "disabled"; 1192 }; 1193 1194 usb3-1 { 1195 status = "disabled"; 1196 }; 1197 1198 usb3-2 { 1199 status = "disabled"; 1200 }; 1201 1202 usb3-3 { 1203 status = "disabled"; 1204 }; 1205 }; 1206 }; 1207 1208 mmc@700b0000 { 1209 compatible = "nvidia,tegra210-sdhci"; 1210 reg = <0x0 0x700b0000 0x0 0x200>; 1211 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1212 clocks = <&tegra_car TEGRA210_CLK_SDMMC1>, 1213 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>; 1214 clock-names = "sdhci", "tmclk"; 1215 resets = <&tegra_car 14>; 1216 reset-names = "sdhci"; 1217 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8", 1218 "sdmmc-3v3-drv", "sdmmc-1v8-drv"; 1219 pinctrl-0 = <&sdmmc1_3v3>; 1220 pinctrl-1 = <&sdmmc1_1v8>; 1221 pinctrl-2 = <&sdmmc1_3v3_drv>; 1222 pinctrl-3 = <&sdmmc1_1v8_drv>; 1223 nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>; 1224 nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>; 1225 nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>; 1226 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>; 1227 nvidia,default-tap = <0x2>; 1228 nvidia,default-trim = <0x4>; 1229 assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>, 1230 <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>, 1231 <&tegra_car TEGRA210_CLK_PLL_C4>; 1232 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 1233 assigned-clock-rates = <200000000>, <1000000000>, <1000000000>; 1234 status = "disabled"; 1235 }; 1236 1237 mmc@700b0200 { 1238 compatible = "nvidia,tegra210-sdhci"; 1239 reg = <0x0 0x700b0200 0x0 0x200>; 1240 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 1241 clocks = <&tegra_car TEGRA210_CLK_SDMMC2>, 1242 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>; 1243 clock-names = "sdhci", "tmclk"; 1244 resets = <&tegra_car 9>; 1245 reset-names = "sdhci"; 1246 pinctrl-names = "sdmmc-1v8-drv"; 1247 pinctrl-0 = <&sdmmc2_1v8_drv>; 1248 nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>; 1249 nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>; 1250 nvidia,default-tap = <0x8>; 1251 nvidia,default-trim = <0x0>; 1252 status = "disabled"; 1253 }; 1254 1255 mmc@700b0400 { 1256 compatible = "nvidia,tegra210-sdhci"; 1257 reg = <0x0 0x700b0400 0x0 0x200>; 1258 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 1259 clocks = <&tegra_car TEGRA210_CLK_SDMMC3>, 1260 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>; 1261 clock-names = "sdhci", "tmclk"; 1262 resets = <&tegra_car 69>; 1263 reset-names = "sdhci"; 1264 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8", 1265 "sdmmc-3v3-drv", "sdmmc-1v8-drv"; 1266 pinctrl-0 = <&sdmmc3_3v3>; 1267 pinctrl-1 = <&sdmmc3_1v8>; 1268 pinctrl-2 = <&sdmmc3_3v3_drv>; 1269 pinctrl-3 = <&sdmmc3_1v8_drv>; 1270 nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>; 1271 nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>; 1272 nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>; 1273 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>; 1274 nvidia,default-tap = <0x3>; 1275 nvidia,default-trim = <0x3>; 1276 status = "disabled"; 1277 }; 1278 1279 mmc@700b0600 { 1280 compatible = "nvidia,tegra210-sdhci"; 1281 reg = <0x0 0x700b0600 0x0 0x200>; 1282 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1283 clocks = <&tegra_car TEGRA210_CLK_SDMMC4>, 1284 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>; 1285 clock-names = "sdhci", "tmclk"; 1286 resets = <&tegra_car 15>; 1287 reset-names = "sdhci"; 1288 pinctrl-names = "sdmmc-3v3-drv", "sdmmc-1v8-drv"; 1289 pinctrl-0 = <&sdmmc4_1v8_drv>; 1290 pinctrl-1 = <&sdmmc4_1v8_drv>; 1291 nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>; 1292 nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>; 1293 nvidia,default-tap = <0x8>; 1294 nvidia,default-trim = <0x0>; 1295 assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>, 1296 <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 1297 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 1298 nvidia,dqs-trim = <40>; 1299 mmc-hs400-1_8v; 1300 status = "disabled"; 1301 }; 1302 1303 usb@700d0000 { 1304 compatible = "nvidia,tegra210-xudc"; 1305 reg = <0x0 0x700d0000 0x0 0x8000>, 1306 <0x0 0x700d8000 0x0 0x1000>, 1307 <0x0 0x700d9000 0x0 0x1000>; 1308 reg-names = "base", "fpci", "ipfs"; 1309 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1310 clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>, 1311 <&tegra_car TEGRA210_CLK_XUSB_SS>, 1312 <&tegra_car TEGRA210_CLK_XUSB_SSP_SRC>, 1313 <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>, 1314 <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>; 1315 clock-names = "dev", "ss", "ss_src", "fs_src", "hs_src"; 1316 power-domains = <&pd_xusbdev>, <&pd_xusbss>; 1317 power-domain-names = "dev", "ss"; 1318 nvidia,xusb-padctl = <&padctl>; 1319 status = "disabled"; 1320 }; 1321 1322 soctherm: thermal-sensor@700e2000 { 1323 compatible = "nvidia,tegra210-soctherm"; 1324 reg = <0x0 0x700e2000 0x0 0x600>, /* SOC_THERM reg_base */ 1325 <0x0 0x60006000 0x0 0x400>; /* CAR reg_base */ 1326 reg-names = "soctherm-reg", "car-reg"; 1327 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 1328 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 1329 interrupt-names = "thermal", "edp"; 1330 clocks = <&tegra_car TEGRA210_CLK_TSENSOR>, 1331 <&tegra_car TEGRA210_CLK_SOC_THERM>; 1332 clock-names = "tsensor", "soctherm"; 1333 resets = <&tegra_car 78>; 1334 reset-names = "soctherm"; 1335 #thermal-sensor-cells = <1>; 1336 1337 throttle-cfgs { 1338 throttle_heavy: heavy { 1339 nvidia,priority = <100>; 1340 nvidia,cpu-throt-percent = <85>; 1341 nvidia,gpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_HIGH>; 1342 1343 #cooling-cells = <2>; 1344 }; 1345 }; 1346 }; 1347 1348 mipi: mipi@700e3000 { 1349 compatible = "nvidia,tegra210-mipi"; 1350 reg = <0x0 0x700e3000 0x0 0x100>; 1351 clocks = <&tegra_car TEGRA210_CLK_MIPI_CAL>; 1352 clock-names = "mipi-cal"; 1353 power-domains = <&pd_sor>; 1354 #nvidia,mipi-calibrate-cells = <1>; 1355 }; 1356 1357 dfll: clock@70110000 { 1358 compatible = "nvidia,tegra210-dfll"; 1359 reg = <0 0x70110000 0 0x100>, /* DFLL control */ 1360 <0 0x70110000 0 0x100>, /* I2C output control */ 1361 <0 0x70110100 0 0x100>, /* Integrated I2C controller */ 1362 <0 0x70110200 0 0x100>; /* Look-up table RAM */ 1363 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 1364 clocks = <&tegra_car TEGRA210_CLK_DFLL_SOC>, 1365 <&tegra_car TEGRA210_CLK_DFLL_REF>, 1366 <&tegra_car TEGRA210_CLK_I2C5>; 1367 clock-names = "soc", "ref", "i2c"; 1368 resets = <&tegra_car TEGRA210_RST_DFLL_DVCO>, 1369 <&tegra_car 155>; 1370 reset-names = "dvco", "dfll"; 1371 #clock-cells = <0>; 1372 clock-output-names = "dfllCPU_out"; 1373 status = "disabled"; 1374 }; 1375 1376 aconnect@702c0000 { 1377 compatible = "nvidia,tegra210-aconnect"; 1378 clocks = <&tegra_car TEGRA210_CLK_APE>, 1379 <&tegra_car TEGRA210_CLK_APB2APE>; 1380 clock-names = "ape", "apb2ape"; 1381 power-domains = <&pd_audio>; 1382 #address-cells = <1>; 1383 #size-cells = <1>; 1384 ranges = <0x702c0000 0x0 0x702c0000 0x00040000>; 1385 status = "disabled"; 1386 1387 adma: dma-controller@702e2000 { 1388 compatible = "nvidia,tegra210-adma"; 1389 reg = <0x702e2000 0x2000>; 1390 interrupt-parent = <&agic>; 1391 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 1392 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 1393 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 1394 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 1395 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 1396 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 1397 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 1398 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 1399 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 1400 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 1401 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 1402 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 1403 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 1404 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 1405 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 1406 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 1407 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 1408 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 1409 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 1410 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 1411 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 1412 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1413 #dma-cells = <1>; 1414 clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>; 1415 clock-names = "d_audio"; 1416 status = "disabled"; 1417 }; 1418 1419 agic: interrupt-controller@702f9000 { 1420 compatible = "nvidia,tegra210-agic"; 1421 #interrupt-cells = <3>; 1422 interrupt-controller; 1423 reg = <0x702f9000 0x1000>, 1424 <0x702fa000 0x2000>; 1425 interrupts = <GIC_SPI 102 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1426 clocks = <&tegra_car TEGRA210_CLK_APE>; 1427 clock-names = "clk"; 1428 status = "disabled"; 1429 }; 1430 1431 tegra_ahub: ahub@702d0800 { 1432 compatible = "nvidia,tegra210-ahub"; 1433 reg = <0x702d0800 0x800>; 1434 clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>; 1435 clock-names = "ahub"; 1436 assigned-clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>; 1437 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1438 #address-cells = <1>; 1439 #size-cells = <1>; 1440 ranges = <0x702d0000 0x702d0000 0x0000e400>; 1441 status = "disabled"; 1442 1443 tegra_admaif: admaif@702d0000 { 1444 compatible = "nvidia,tegra210-admaif"; 1445 reg = <0x702d0000 0x800>; 1446 dmas = <&adma 1>, <&adma 1>, 1447 <&adma 2>, <&adma 2>, 1448 <&adma 3>, <&adma 3>, 1449 <&adma 4>, <&adma 4>, 1450 <&adma 5>, <&adma 5>, 1451 <&adma 6>, <&adma 6>, 1452 <&adma 7>, <&adma 7>, 1453 <&adma 8>, <&adma 8>, 1454 <&adma 9>, <&adma 9>, 1455 <&adma 10>, <&adma 10>; 1456 dma-names = "rx1", "tx1", 1457 "rx2", "tx2", 1458 "rx3", "tx3", 1459 "rx4", "tx4", 1460 "rx5", "tx5", 1461 "rx6", "tx6", 1462 "rx7", "tx7", 1463 "rx8", "tx8", 1464 "rx9", "tx9", 1465 "rx10", "tx10"; 1466 status = "disabled"; 1467 1468 ports { 1469 #address-cells = <1>; 1470 #size-cells = <0>; 1471 1472 admaif1_port: port@0 { 1473 reg = <0>; 1474 1475 admaif1_ep: endpoint { 1476 remote-endpoint = <&xbar_admaif1_ep>; 1477 }; 1478 }; 1479 1480 admaif2_port: port@1 { 1481 reg = <1>; 1482 1483 admaif2_ep: endpoint { 1484 remote-endpoint = <&xbar_admaif2_ep>; 1485 }; 1486 }; 1487 1488 admaif3_port: port@2 { 1489 reg = <2>; 1490 1491 admaif3_ep: endpoint { 1492 remote-endpoint = <&xbar_admaif3_ep>; 1493 }; 1494 }; 1495 1496 admaif4_port: port@3 { 1497 reg = <3>; 1498 1499 admaif4_ep: endpoint { 1500 remote-endpoint = <&xbar_admaif4_ep>; 1501 }; 1502 }; 1503 1504 admaif5_port: port@4 { 1505 reg = <4>; 1506 1507 admaif5_ep: endpoint { 1508 remote-endpoint = <&xbar_admaif5_ep>; 1509 }; 1510 }; 1511 1512 admaif6_port: port@5 { 1513 reg = <5>; 1514 1515 admaif6_ep: endpoint { 1516 remote-endpoint = <&xbar_admaif6_ep>; 1517 }; 1518 }; 1519 1520 admaif7_port: port@6 { 1521 reg = <6>; 1522 1523 admaif7_ep: endpoint { 1524 remote-endpoint = <&xbar_admaif7_ep>; 1525 }; 1526 }; 1527 1528 admaif8_port: port@7 { 1529 reg = <7>; 1530 1531 admaif8_ep: endpoint { 1532 remote-endpoint = <&xbar_admaif8_ep>; 1533 }; 1534 }; 1535 1536 admaif9_port: port@8 { 1537 reg = <8>; 1538 1539 admaif9_ep: endpoint { 1540 remote-endpoint = <&xbar_admaif9_ep>; 1541 }; 1542 }; 1543 1544 admaif10_port: port@9 { 1545 reg = <9>; 1546 1547 admaif10_ep: endpoint { 1548 remote-endpoint = <&xbar_admaif10_ep>; 1549 }; 1550 }; 1551 }; 1552 }; 1553 1554 tegra_i2s1: i2s@702d1000 { 1555 compatible = "nvidia,tegra210-i2s"; 1556 reg = <0x702d1000 0x100>; 1557 clocks = <&tegra_car TEGRA210_CLK_I2S0>, 1558 <&tegra_car TEGRA210_CLK_I2S0_SYNC>; 1559 clock-names = "i2s", "sync_input"; 1560 assigned-clocks = <&tegra_car TEGRA210_CLK_I2S0>; 1561 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1562 assigned-clock-rates = <1536000>; 1563 sound-name-prefix = "I2S1"; 1564 status = "disabled"; 1565 }; 1566 1567 tegra_i2s2: i2s@702d1100 { 1568 compatible = "nvidia,tegra210-i2s"; 1569 reg = <0x702d1100 0x100>; 1570 clocks = <&tegra_car TEGRA210_CLK_I2S1>, 1571 <&tegra_car TEGRA210_CLK_I2S1_SYNC>; 1572 clock-names = "i2s", "sync_input"; 1573 assigned-clocks = <&tegra_car TEGRA210_CLK_I2S1>; 1574 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1575 assigned-clock-rates = <1536000>; 1576 sound-name-prefix = "I2S2"; 1577 status = "disabled"; 1578 }; 1579 1580 tegra_i2s3: i2s@702d1200 { 1581 compatible = "nvidia,tegra210-i2s"; 1582 reg = <0x702d1200 0x100>; 1583 clocks = <&tegra_car TEGRA210_CLK_I2S2>, 1584 <&tegra_car TEGRA210_CLK_I2S2_SYNC>; 1585 clock-names = "i2s", "sync_input"; 1586 assigned-clocks = <&tegra_car TEGRA210_CLK_I2S2>; 1587 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1588 assigned-clock-rates = <1536000>; 1589 sound-name-prefix = "I2S3"; 1590 status = "disabled"; 1591 }; 1592 1593 tegra_i2s4: i2s@702d1300 { 1594 compatible = "nvidia,tegra210-i2s"; 1595 reg = <0x702d1300 0x100>; 1596 clocks = <&tegra_car TEGRA210_CLK_I2S3>, 1597 <&tegra_car TEGRA210_CLK_I2S3_SYNC>; 1598 clock-names = "i2s", "sync_input"; 1599 assigned-clocks = <&tegra_car TEGRA210_CLK_I2S3>; 1600 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1601 assigned-clock-rates = <1536000>; 1602 sound-name-prefix = "I2S4"; 1603 status = "disabled"; 1604 }; 1605 1606 tegra_i2s5: i2s@702d1400 { 1607 compatible = "nvidia,tegra210-i2s"; 1608 reg = <0x702d1400 0x100>; 1609 clocks = <&tegra_car TEGRA210_CLK_I2S4>, 1610 <&tegra_car TEGRA210_CLK_I2S4_SYNC>; 1611 clock-names = "i2s", "sync_input"; 1612 assigned-clocks = <&tegra_car TEGRA210_CLK_I2S4>; 1613 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1614 assigned-clock-rates = <1536000>; 1615 sound-name-prefix = "I2S5"; 1616 status = "disabled"; 1617 }; 1618 1619 tegra_dmic1: dmic@702d4000 { 1620 compatible = "nvidia,tegra210-dmic"; 1621 reg = <0x702d4000 0x100>; 1622 clocks = <&tegra_car TEGRA210_CLK_DMIC1>; 1623 clock-names = "dmic"; 1624 assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC1>; 1625 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1626 assigned-clock-rates = <3072000>; 1627 sound-name-prefix = "DMIC1"; 1628 status = "disabled"; 1629 }; 1630 1631 tegra_dmic2: dmic@702d4100 { 1632 compatible = "nvidia,tegra210-dmic"; 1633 reg = <0x702d4100 0x100>; 1634 clocks = <&tegra_car TEGRA210_CLK_DMIC2>; 1635 clock-names = "dmic"; 1636 assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC2>; 1637 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1638 assigned-clock-rates = <3072000>; 1639 sound-name-prefix = "DMIC2"; 1640 status = "disabled"; 1641 }; 1642 1643 tegra_dmic3: dmic@702d4200 { 1644 compatible = "nvidia,tegra210-dmic"; 1645 reg = <0x702d4200 0x100>; 1646 clocks = <&tegra_car TEGRA210_CLK_DMIC3>; 1647 clock-names = "dmic"; 1648 assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC3>; 1649 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1650 assigned-clock-rates = <3072000>; 1651 sound-name-prefix = "DMIC3"; 1652 status = "disabled"; 1653 }; 1654 1655 tegra_sfc1: sfc@702d2000 { 1656 compatible = "nvidia,tegra210-sfc"; 1657 reg = <0x702d2000 0x200>; 1658 sound-name-prefix = "SFC1"; 1659 status = "disabled"; 1660 }; 1661 1662 tegra_sfc2: sfc@702d2200 { 1663 compatible = "nvidia,tegra210-sfc"; 1664 reg = <0x702d2200 0x200>; 1665 sound-name-prefix = "SFC2"; 1666 status = "disabled"; 1667 }; 1668 1669 tegra_sfc3: sfc@702d2400 { 1670 compatible = "nvidia,tegra210-sfc"; 1671 reg = <0x702d2400 0x200>; 1672 sound-name-prefix = "SFC3"; 1673 status = "disabled"; 1674 }; 1675 1676 tegra_sfc4: sfc@702d2600 { 1677 compatible = "nvidia,tegra210-sfc"; 1678 reg = <0x702d2600 0x200>; 1679 sound-name-prefix = "SFC4"; 1680 status = "disabled"; 1681 }; 1682 1683 tegra_mvc1: mvc@702da000 { 1684 compatible = "nvidia,tegra210-mvc"; 1685 reg = <0x702da000 0x200>; 1686 sound-name-prefix = "MVC1"; 1687 status = "disabled"; 1688 }; 1689 1690 tegra_mvc2: mvc@702da200 { 1691 compatible = "nvidia,tegra210-mvc"; 1692 reg = <0x702da200 0x200>; 1693 sound-name-prefix = "MVC2"; 1694 status = "disabled"; 1695 }; 1696 1697 tegra_amx1: amx@702d3000 { 1698 compatible = "nvidia,tegra210-amx"; 1699 reg = <0x702d3000 0x100>; 1700 sound-name-prefix = "AMX1"; 1701 status = "disabled"; 1702 }; 1703 1704 tegra_amx2: amx@702d3100 { 1705 compatible = "nvidia,tegra210-amx"; 1706 reg = <0x702d3100 0x100>; 1707 sound-name-prefix = "AMX2"; 1708 status = "disabled"; 1709 }; 1710 1711 tegra_adx1: adx@702d3800 { 1712 compatible = "nvidia,tegra210-adx"; 1713 reg = <0x702d3800 0x100>; 1714 sound-name-prefix = "ADX1"; 1715 status = "disabled"; 1716 }; 1717 1718 tegra_adx2: adx@702d3900 { 1719 compatible = "nvidia,tegra210-adx"; 1720 reg = <0x702d3900 0x100>; 1721 sound-name-prefix = "ADX2"; 1722 status = "disabled"; 1723 }; 1724 1725 tegra_ope1: processing-engine@702d8000 { 1726 compatible = "nvidia,tegra210-ope"; 1727 reg = <0x702d8000 0x100>; 1728 #address-cells = <1>; 1729 #size-cells = <1>; 1730 ranges; 1731 sound-name-prefix = "OPE1"; 1732 status = "disabled"; 1733 1734 equalizer@702d8100 { 1735 compatible = "nvidia,tegra210-peq"; 1736 reg = <0x702d8100 0x100>; 1737 }; 1738 1739 dynamic-range-compressor@702d8200 { 1740 compatible = "nvidia,tegra210-mbdrc"; 1741 reg = <0x702d8200 0x200>; 1742 }; 1743 }; 1744 1745 tegra_ope2: processing-engine@702d8400 { 1746 compatible = "nvidia,tegra210-ope"; 1747 reg = <0x702d8400 0x100>; 1748 #address-cells = <1>; 1749 #size-cells = <1>; 1750 ranges; 1751 sound-name-prefix = "OPE2"; 1752 status = "disabled"; 1753 1754 equalizer@702d8500 { 1755 compatible = "nvidia,tegra210-peq"; 1756 reg = <0x702d8500 0x100>; 1757 }; 1758 1759 dynamic-range-compressor@702d8600 { 1760 compatible = "nvidia,tegra210-mbdrc"; 1761 reg = <0x702d8600 0x200>; 1762 }; 1763 }; 1764 1765 tegra_amixer: amixer@702dbb00 { 1766 compatible = "nvidia,tegra210-amixer"; 1767 reg = <0x702dbb00 0x800>; 1768 sound-name-prefix = "MIXER1"; 1769 status = "disabled"; 1770 }; 1771 1772 ports { 1773 #address-cells = <1>; 1774 #size-cells = <0>; 1775 1776 port@0 { 1777 reg = <0x0>; 1778 1779 xbar_admaif1_ep: endpoint { 1780 remote-endpoint = <&admaif1_ep>; 1781 }; 1782 }; 1783 1784 port@1 { 1785 reg = <0x1>; 1786 1787 xbar_admaif2_ep: endpoint { 1788 remote-endpoint = <&admaif2_ep>; 1789 }; 1790 }; 1791 1792 port@2 { 1793 reg = <0x2>; 1794 1795 xbar_admaif3_ep: endpoint { 1796 remote-endpoint = <&admaif3_ep>; 1797 }; 1798 }; 1799 1800 port@3 { 1801 reg = <0x3>; 1802 1803 xbar_admaif4_ep: endpoint { 1804 remote-endpoint = <&admaif4_ep>; 1805 }; 1806 }; 1807 1808 port@4 { 1809 reg = <0x4>; 1810 xbar_admaif5_ep: endpoint { 1811 remote-endpoint = <&admaif5_ep>; 1812 }; 1813 }; 1814 port@5 { 1815 reg = <0x5>; 1816 1817 xbar_admaif6_ep: endpoint { 1818 remote-endpoint = <&admaif6_ep>; 1819 }; 1820 }; 1821 1822 port@6 { 1823 reg = <0x6>; 1824 1825 xbar_admaif7_ep: endpoint { 1826 remote-endpoint = <&admaif7_ep>; 1827 }; 1828 }; 1829 1830 port@7 { 1831 reg = <0x7>; 1832 1833 xbar_admaif8_ep: endpoint { 1834 remote-endpoint = <&admaif8_ep>; 1835 }; 1836 }; 1837 1838 port@8 { 1839 reg = <0x8>; 1840 1841 xbar_admaif9_ep: endpoint { 1842 remote-endpoint = <&admaif9_ep>; 1843 }; 1844 }; 1845 1846 port@9 { 1847 reg = <0x9>; 1848 1849 xbar_admaif10_ep: endpoint { 1850 remote-endpoint = <&admaif10_ep>; 1851 }; 1852 }; 1853 }; 1854 }; 1855 }; 1856 1857 spi@70410000 { 1858 compatible = "nvidia,tegra210-qspi"; 1859 reg = <0x0 0x70410000 0x0 0x1000>; 1860 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1861 #address-cells = <1>; 1862 #size-cells = <0>; 1863 clocks = <&tegra_car TEGRA210_CLK_QSPI>, 1864 <&tegra_car TEGRA210_CLK_QSPI_PM>; 1865 clock-names = "qspi", "qspi_out"; 1866 resets = <&tegra_car 211>; 1867 reset-names = "qspi"; 1868 dmas = <&apbdma 5>, <&apbdma 5>; 1869 dma-names = "rx", "tx"; 1870 status = "disabled"; 1871 }; 1872 1873 usb@7d000000 { 1874 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci"; 1875 reg = <0x0 0x7d000000 0x0 0x4000>; 1876 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1877 phy_type = "utmi"; 1878 clocks = <&tegra_car TEGRA210_CLK_USBD>; 1879 clock-names = "usb"; 1880 resets = <&tegra_car 22>; 1881 reset-names = "usb"; 1882 nvidia,phy = <&phy1>; 1883 status = "disabled"; 1884 }; 1885 1886 phy1: usb-phy@7d000000 { 1887 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; 1888 reg = <0x0 0x7d000000 0x0 0x4000>, 1889 <0x0 0x7d000000 0x0 0x4000>; 1890 phy_type = "utmi"; 1891 clocks = <&tegra_car TEGRA210_CLK_USBD>, 1892 <&tegra_car TEGRA210_CLK_PLL_U>, 1893 <&tegra_car TEGRA210_CLK_USBD>; 1894 clock-names = "reg", "pll_u", "utmi-pads"; 1895 resets = <&tegra_car 22>, <&tegra_car 22>; 1896 reset-names = "usb", "utmi-pads"; 1897 nvidia,hssync-start-delay = <0>; 1898 nvidia,idle-wait-delay = <17>; 1899 nvidia,elastic-limit = <16>; 1900 nvidia,term-range-adj = <6>; 1901 nvidia,xcvr-setup = <9>; 1902 nvidia,xcvr-lsfslew = <0>; 1903 nvidia,xcvr-lsrslew = <3>; 1904 nvidia,hssquelch-level = <2>; 1905 nvidia,hsdiscon-level = <5>; 1906 nvidia,xcvr-hsslew = <12>; 1907 nvidia,has-utmi-pad-registers; 1908 status = "disabled"; 1909 }; 1910 1911 usb@7d004000 { 1912 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci"; 1913 reg = <0x0 0x7d004000 0x0 0x4000>; 1914 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1915 phy_type = "utmi"; 1916 clocks = <&tegra_car TEGRA210_CLK_USB2>; 1917 clock-names = "usb"; 1918 resets = <&tegra_car 58>; 1919 reset-names = "usb"; 1920 nvidia,phy = <&phy2>; 1921 status = "disabled"; 1922 }; 1923 1924 phy2: usb-phy@7d004000 { 1925 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; 1926 reg = <0x0 0x7d004000 0x0 0x4000>, 1927 <0x0 0x7d000000 0x0 0x4000>; 1928 phy_type = "utmi"; 1929 clocks = <&tegra_car TEGRA210_CLK_USB2>, 1930 <&tegra_car TEGRA210_CLK_PLL_U>, 1931 <&tegra_car TEGRA210_CLK_USBD>; 1932 clock-names = "reg", "pll_u", "utmi-pads"; 1933 resets = <&tegra_car 58>, <&tegra_car 22>; 1934 reset-names = "usb", "utmi-pads"; 1935 nvidia,hssync-start-delay = <0>; 1936 nvidia,idle-wait-delay = <17>; 1937 nvidia,elastic-limit = <16>; 1938 nvidia,term-range-adj = <6>; 1939 nvidia,xcvr-setup = <9>; 1940 nvidia,xcvr-lsfslew = <0>; 1941 nvidia,xcvr-lsrslew = <3>; 1942 nvidia,hssquelch-level = <2>; 1943 nvidia,hsdiscon-level = <5>; 1944 nvidia,xcvr-hsslew = <12>; 1945 status = "disabled"; 1946 }; 1947 1948 cpus { 1949 #address-cells = <1>; 1950 #size-cells = <0>; 1951 1952 cpu@0 { 1953 device_type = "cpu"; 1954 compatible = "arm,cortex-a57"; 1955 reg = <0>; 1956 clocks = <&tegra_car TEGRA210_CLK_CCLK_G>, 1957 <&tegra_car TEGRA210_CLK_PLL_X>, 1958 <&tegra_car TEGRA210_CLK_PLL_P_OUT4>, 1959 <&dfll>; 1960 clock-names = "cpu_g", "pll_x", "pll_p", "dfll"; 1961 clock-latency = <300000>; 1962 cpu-idle-states = <&CPU_SLEEP>; 1963 next-level-cache = <&L2>; 1964 }; 1965 1966 cpu@1 { 1967 device_type = "cpu"; 1968 compatible = "arm,cortex-a57"; 1969 reg = <1>; 1970 cpu-idle-states = <&CPU_SLEEP>; 1971 next-level-cache = <&L2>; 1972 }; 1973 1974 cpu@2 { 1975 device_type = "cpu"; 1976 compatible = "arm,cortex-a57"; 1977 reg = <2>; 1978 cpu-idle-states = <&CPU_SLEEP>; 1979 next-level-cache = <&L2>; 1980 }; 1981 1982 cpu@3 { 1983 device_type = "cpu"; 1984 compatible = "arm,cortex-a57"; 1985 reg = <3>; 1986 cpu-idle-states = <&CPU_SLEEP>; 1987 next-level-cache = <&L2>; 1988 }; 1989 1990 idle-states { 1991 entry-method = "psci"; 1992 1993 CPU_SLEEP: cpu-sleep { 1994 compatible = "arm,idle-state"; 1995 arm,psci-suspend-param = <0x40000007>; 1996 entry-latency-us = <100>; 1997 exit-latency-us = <30>; 1998 min-residency-us = <1000>; 1999 wakeup-latency-us = <130>; 2000 idle-state-name = "cpu-sleep"; 2001 status = "disabled"; 2002 }; 2003 }; 2004 2005 L2: l2-cache { 2006 compatible = "cache"; 2007 cache-level = <2>; 2008 }; 2009 }; 2010 2011 pmu { 2012 compatible = "arm,armv8-pmuv3"; 2013 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 2014 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 2015 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 2016 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 2017 interrupt-affinity = <&{/cpus/cpu@0} &{/cpus/cpu@1} 2018 &{/cpus/cpu@2} &{/cpus/cpu@3}>; 2019 }; 2020 2021 sound { 2022 status = "disabled"; 2023 2024 clocks = <&tegra_car TEGRA210_CLK_PLL_A>, 2025 <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 2026 clock-names = "pll_a", "plla_out0"; 2027 2028 assigned-clocks = <&tegra_car TEGRA210_CLK_PLL_A>, 2029 <&tegra_car TEGRA210_CLK_PLL_A_OUT0>, 2030 <&tegra_car TEGRA210_CLK_EXTERN1>; 2031 assigned-clock-parents = <0>, <0>, <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 2032 assigned-clock-rates = <368640000>, <49152000>, <12288000>; 2033 }; 2034 2035 thermal-zones { 2036 cpu-thermal { 2037 polling-delay-passive = <1000>; 2038 polling-delay = <0>; 2039 2040 thermal-sensors = 2041 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; 2042 2043 trips { 2044 cpu-shutdown-trip { 2045 temperature = <102500>; 2046 hysteresis = <0>; 2047 type = "critical"; 2048 }; 2049 2050 cpu_throttle_trip: throttle-trip { 2051 temperature = <98500>; 2052 hysteresis = <1000>; 2053 type = "hot"; 2054 }; 2055 }; 2056 2057 cooling-maps { 2058 map0 { 2059 trip = <&cpu_throttle_trip>; 2060 cooling-device = <&throttle_heavy 1 1>; 2061 }; 2062 }; 2063 }; 2064 2065 mem-thermal { 2066 polling-delay-passive = <0>; 2067 polling-delay = <0>; 2068 2069 thermal-sensors = 2070 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>; 2071 2072 trips { 2073 dram_nominal: mem-nominal-trip { 2074 temperature = <50000>; 2075 hysteresis = <1000>; 2076 type = "passive"; 2077 }; 2078 2079 dram_throttle: mem-throttle-trip { 2080 temperature = <70000>; 2081 hysteresis = <1000>; 2082 type = "active"; 2083 }; 2084 2085 mem-hot-trip { 2086 temperature = <100000>; 2087 hysteresis = <1000>; 2088 type = "hot"; 2089 }; 2090 2091 mem-shutdown-trip { 2092 temperature = <103000>; 2093 hysteresis = <0>; 2094 type = "critical"; 2095 }; 2096 }; 2097 2098 cooling-maps { 2099 dram-passive { 2100 cooling-device = <&emc 0 0>; 2101 trip = <&dram_nominal>; 2102 }; 2103 2104 dram-active { 2105 cooling-device = <&emc 1 1>; 2106 trip = <&dram_throttle>; 2107 }; 2108 }; 2109 }; 2110 2111 gpu-thermal { 2112 polling-delay-passive = <1000>; 2113 polling-delay = <0>; 2114 2115 thermal-sensors = 2116 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>; 2117 2118 trips { 2119 gpu-shutdown-trip { 2120 temperature = <103000>; 2121 hysteresis = <0>; 2122 type = "critical"; 2123 }; 2124 2125 gpu_throttle_trip: throttle-trip { 2126 temperature = <100000>; 2127 hysteresis = <1000>; 2128 type = "hot"; 2129 }; 2130 }; 2131 2132 cooling-maps { 2133 map0 { 2134 trip = <&gpu_throttle_trip>; 2135 cooling-device = <&throttle_heavy 1 1>; 2136 }; 2137 }; 2138 }; 2139 2140 pllx-thermal { 2141 polling-delay-passive = <0>; 2142 polling-delay = <0>; 2143 2144 thermal-sensors = 2145 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>; 2146 2147 trips { 2148 pllx-shutdown-trip { 2149 temperature = <103000>; 2150 hysteresis = <0>; 2151 type = "critical"; 2152 }; 2153 2154 pllx-throttle-trip { 2155 temperature = <100000>; 2156 hysteresis = <1000>; 2157 type = "hot"; 2158 }; 2159 }; 2160 2161 cooling-maps { 2162 /* 2163 * There are currently no cooling maps, 2164 * because there are no cooling devices. 2165 */ 2166 }; 2167 }; 2168 }; 2169 2170 timer { 2171 compatible = "arm,armv8-timer"; 2172 interrupts = <GIC_PPI 13 2173 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2174 <GIC_PPI 14 2175 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2176 <GIC_PPI 11 2177 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2178 <GIC_PPI 10 2179 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 2180 interrupt-parent = <&gic>; 2181 arm,no-tick-in-suspend; 2182 }; 2183}; 2184