1#include <dt-bindings/clock/tegra210-car.h> 2#include <dt-bindings/gpio/tegra-gpio.h> 3#include <dt-bindings/memory/tegra210-mc.h> 4#include <dt-bindings/pinctrl/pinctrl-tegra.h> 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6#include <dt-bindings/thermal/tegra124-soctherm.h> 7 8/ { 9 compatible = "nvidia,tegra210"; 10 interrupt-parent = <&lic>; 11 #address-cells = <2>; 12 #size-cells = <2>; 13 14 pcie-controller@01003000 { 15 compatible = "nvidia,tegra210-pcie"; 16 device_type = "pci"; 17 reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */ 18 0x0 0x01003800 0x0 0x00000800 /* AFI registers */ 19 0x0 0x02000000 0x0 0x10000000>; /* configuration space */ 20 reg-names = "pads", "afi", "cs"; 21 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 22 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 23 interrupt-names = "intr", "msi"; 24 25 #interrupt-cells = <1>; 26 interrupt-map-mask = <0 0 0 0>; 27 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 28 29 bus-range = <0x00 0xff>; 30 #address-cells = <3>; 31 #size-cells = <2>; 32 33 ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */ 34 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */ 35 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */ 36 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */ 37 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ 38 39 clocks = <&tegra_car TEGRA210_CLK_PCIE>, 40 <&tegra_car TEGRA210_CLK_AFI>, 41 <&tegra_car TEGRA210_CLK_PLL_E>, 42 <&tegra_car TEGRA210_CLK_CML0>; 43 clock-names = "pex", "afi", "pll_e", "cml"; 44 resets = <&tegra_car 70>, 45 <&tegra_car 72>, 46 <&tegra_car 74>; 47 reset-names = "pex", "afi", "pcie_x"; 48 status = "disabled"; 49 50 pci@1,0 { 51 device_type = "pci"; 52 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>; 53 reg = <0x000800 0 0 0 0>; 54 status = "disabled"; 55 56 #address-cells = <3>; 57 #size-cells = <2>; 58 ranges; 59 60 nvidia,num-lanes = <4>; 61 }; 62 63 pci@2,0 { 64 device_type = "pci"; 65 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>; 66 reg = <0x001000 0 0 0 0>; 67 status = "disabled"; 68 69 #address-cells = <3>; 70 #size-cells = <2>; 71 ranges; 72 73 nvidia,num-lanes = <1>; 74 }; 75 }; 76 77 host1x@50000000 { 78 compatible = "nvidia,tegra210-host1x", "simple-bus"; 79 reg = <0x0 0x50000000 0x0 0x00034000>; 80 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 81 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ 82 clocks = <&tegra_car TEGRA210_CLK_HOST1X>; 83 clock-names = "host1x"; 84 resets = <&tegra_car 28>; 85 reset-names = "host1x"; 86 87 #address-cells = <2>; 88 #size-cells = <2>; 89 90 ranges = <0x0 0x54000000 0x0 0x54000000 0x0 0x01000000>; 91 92 dpaux1: dpaux@54040000 { 93 compatible = "nvidia,tegra210-dpaux"; 94 reg = <0x0 0x54040000 0x0 0x00040000>; 95 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 96 clocks = <&tegra_car TEGRA210_CLK_DPAUX1>, 97 <&tegra_car TEGRA210_CLK_PLL_DP>; 98 clock-names = "dpaux", "parent"; 99 resets = <&tegra_car 207>; 100 reset-names = "dpaux"; 101 power-domains = <&pd_sor>; 102 status = "disabled"; 103 104 state_dpaux1_aux: pinmux-aux { 105 groups = "dpaux-io"; 106 function = "aux"; 107 }; 108 109 state_dpaux1_i2c: pinmux-i2c { 110 groups = "dpaux-io"; 111 function = "i2c"; 112 }; 113 114 state_dpaux1_off: pinmux-off { 115 groups = "dpaux-io"; 116 function = "off"; 117 }; 118 119 i2c-bus { 120 #address-cells = <1>; 121 #size-cells = <0>; 122 }; 123 }; 124 125 vi@54080000 { 126 compatible = "nvidia,tegra210-vi"; 127 reg = <0x0 0x54080000 0x0 0x00040000>; 128 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 129 status = "disabled"; 130 }; 131 132 tsec@54100000 { 133 compatible = "nvidia,tegra210-tsec"; 134 reg = <0x0 0x54100000 0x0 0x00040000>; 135 }; 136 137 dc@54200000 { 138 compatible = "nvidia,tegra210-dc"; 139 reg = <0x0 0x54200000 0x0 0x00040000>; 140 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 141 clocks = <&tegra_car TEGRA210_CLK_DISP1>, 142 <&tegra_car TEGRA210_CLK_PLL_P>; 143 clock-names = "dc", "parent"; 144 resets = <&tegra_car 27>; 145 reset-names = "dc"; 146 147 iommus = <&mc TEGRA_SWGROUP_DC>; 148 149 nvidia,head = <0>; 150 }; 151 152 dc@54240000 { 153 compatible = "nvidia,tegra210-dc"; 154 reg = <0x0 0x54240000 0x0 0x00040000>; 155 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 156 clocks = <&tegra_car TEGRA210_CLK_DISP2>, 157 <&tegra_car TEGRA210_CLK_PLL_P>; 158 clock-names = "dc", "parent"; 159 resets = <&tegra_car 26>; 160 reset-names = "dc"; 161 162 iommus = <&mc TEGRA_SWGROUP_DCB>; 163 164 nvidia,head = <1>; 165 }; 166 167 dsi@54300000 { 168 compatible = "nvidia,tegra210-dsi"; 169 reg = <0x0 0x54300000 0x0 0x00040000>; 170 clocks = <&tegra_car TEGRA210_CLK_DSIA>, 171 <&tegra_car TEGRA210_CLK_DSIALP>, 172 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; 173 clock-names = "dsi", "lp", "parent"; 174 resets = <&tegra_car 48>; 175 reset-names = "dsi"; 176 power-domains = <&pd_sor>; 177 nvidia,mipi-calibrate = <&mipi 0x0c0>; /* DSIA & DSIB pads */ 178 179 status = "disabled"; 180 181 #address-cells = <1>; 182 #size-cells = <0>; 183 }; 184 185 vic@54340000 { 186 compatible = "nvidia,tegra210-vic"; 187 reg = <0x0 0x54340000 0x0 0x00040000>; 188 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 189 clocks = <&tegra_car TEGRA210_CLK_VIC03>; 190 clock-names = "vic"; 191 resets = <&tegra_car 178>; 192 reset-names = "vic"; 193 194 iommus = <&mc TEGRA_SWGROUP_VIC>; 195 power-domains = <&pd_vic>; 196 }; 197 198 nvjpg@54380000 { 199 compatible = "nvidia,tegra210-nvjpg"; 200 reg = <0x0 0x54380000 0x0 0x00040000>; 201 status = "disabled"; 202 }; 203 204 dsi@54400000 { 205 compatible = "nvidia,tegra210-dsi"; 206 reg = <0x0 0x54400000 0x0 0x00040000>; 207 clocks = <&tegra_car TEGRA210_CLK_DSIB>, 208 <&tegra_car TEGRA210_CLK_DSIBLP>, 209 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; 210 clock-names = "dsi", "lp", "parent"; 211 resets = <&tegra_car 82>; 212 reset-names = "dsi"; 213 power-domains = <&pd_sor>; 214 nvidia,mipi-calibrate = <&mipi 0x300>; /* DSIC & DSID pads */ 215 216 status = "disabled"; 217 218 #address-cells = <1>; 219 #size-cells = <0>; 220 }; 221 222 nvdec@54480000 { 223 compatible = "nvidia,tegra210-nvdec"; 224 reg = <0x0 0x54480000 0x0 0x00040000>; 225 status = "disabled"; 226 }; 227 228 nvenc@544c0000 { 229 compatible = "nvidia,tegra210-nvenc"; 230 reg = <0x0 0x544c0000 0x0 0x00040000>; 231 status = "disabled"; 232 }; 233 234 tsec@54500000 { 235 compatible = "nvidia,tegra210-tsec"; 236 reg = <0x0 0x54500000 0x0 0x00040000>; 237 status = "disabled"; 238 }; 239 240 sor@54540000 { 241 compatible = "nvidia,tegra210-sor"; 242 reg = <0x0 0x54540000 0x0 0x00040000>; 243 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 244 clocks = <&tegra_car TEGRA210_CLK_SOR0>, 245 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>, 246 <&tegra_car TEGRA210_CLK_PLL_DP>, 247 <&tegra_car TEGRA210_CLK_SOR_SAFE>; 248 clock-names = "sor", "parent", "dp", "safe"; 249 resets = <&tegra_car 182>; 250 reset-names = "sor"; 251 pinctrl-0 = <&state_dpaux_aux>; 252 pinctrl-1 = <&state_dpaux_i2c>; 253 pinctrl-2 = <&state_dpaux_off>; 254 pinctrl-names = "aux", "i2c", "off"; 255 power-domains = <&pd_sor>; 256 status = "disabled"; 257 }; 258 259 sor@54580000 { 260 compatible = "nvidia,tegra210-sor1"; 261 reg = <0x0 0x54580000 0x0 0x00040000>; 262 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 263 clocks = <&tegra_car TEGRA210_CLK_SOR1>, 264 <&tegra_car TEGRA210_CLK_SOR1_SRC>, 265 <&tegra_car TEGRA210_CLK_PLL_D2_OUT0>, 266 <&tegra_car TEGRA210_CLK_PLL_DP>, 267 <&tegra_car TEGRA210_CLK_SOR_SAFE>; 268 clock-names = "sor", "source", "parent", "dp", "safe"; 269 resets = <&tegra_car 183>; 270 reset-names = "sor"; 271 pinctrl-0 = <&state_dpaux1_aux>; 272 pinctrl-1 = <&state_dpaux1_i2c>; 273 pinctrl-2 = <&state_dpaux1_off>; 274 pinctrl-names = "aux", "i2c", "off"; 275 power-domains = <&pd_sor>; 276 status = "disabled"; 277 }; 278 279 dpaux: dpaux@545c0000 { 280 compatible = "nvidia,tegra124-dpaux"; 281 reg = <0x0 0x545c0000 0x0 0x00040000>; 282 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 283 clocks = <&tegra_car TEGRA210_CLK_DPAUX>, 284 <&tegra_car TEGRA210_CLK_PLL_DP>; 285 clock-names = "dpaux", "parent"; 286 resets = <&tegra_car 181>; 287 reset-names = "dpaux"; 288 power-domains = <&pd_sor>; 289 status = "disabled"; 290 291 state_dpaux_aux: pinmux-aux { 292 groups = "dpaux-io"; 293 function = "aux"; 294 }; 295 296 state_dpaux_i2c: pinmux-i2c { 297 groups = "dpaux-io"; 298 function = "i2c"; 299 }; 300 301 state_dpaux_off: pinmux-off { 302 groups = "dpaux-io"; 303 function = "off"; 304 }; 305 306 i2c-bus { 307 #address-cells = <1>; 308 #size-cells = <0>; 309 }; 310 }; 311 312 isp@54600000 { 313 compatible = "nvidia,tegra210-isp"; 314 reg = <0x0 0x54600000 0x0 0x00040000>; 315 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 316 status = "disabled"; 317 }; 318 319 isp@54680000 { 320 compatible = "nvidia,tegra210-isp"; 321 reg = <0x0 0x54680000 0x0 0x00040000>; 322 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 323 status = "disabled"; 324 }; 325 326 i2c@546c0000 { 327 compatible = "nvidia,tegra210-i2c-vi"; 328 reg = <0x0 0x546c0000 0x0 0x00040000>; 329 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 330 status = "disabled"; 331 }; 332 }; 333 334 gic: interrupt-controller@50041000 { 335 compatible = "arm,gic-400"; 336 #interrupt-cells = <3>; 337 interrupt-controller; 338 reg = <0x0 0x50041000 0x0 0x1000>, 339 <0x0 0x50042000 0x0 0x2000>, 340 <0x0 0x50044000 0x0 0x2000>, 341 <0x0 0x50046000 0x0 0x2000>; 342 interrupts = <GIC_PPI 9 343 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 344 interrupt-parent = <&gic>; 345 }; 346 347 gpu@57000000 { 348 compatible = "nvidia,gm20b"; 349 reg = <0x0 0x57000000 0x0 0x01000000>, 350 <0x0 0x58000000 0x0 0x01000000>; 351 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 352 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 353 interrupt-names = "stall", "nonstall"; 354 clocks = <&tegra_car TEGRA210_CLK_GPU>, 355 <&tegra_car TEGRA210_CLK_PLL_P_OUT5>, 356 <&tegra_car TEGRA210_CLK_PLL_G_REF>; 357 clock-names = "gpu", "pwr", "ref"; 358 resets = <&tegra_car 184>; 359 reset-names = "gpu"; 360 361 iommus = <&mc TEGRA_SWGROUP_GPU>; 362 363 status = "disabled"; 364 }; 365 366 lic: interrupt-controller@60004000 { 367 compatible = "nvidia,tegra210-ictlr"; 368 reg = <0x0 0x60004000 0x0 0x40>, /* primary controller */ 369 <0x0 0x60004100 0x0 0x40>, /* secondary controller */ 370 <0x0 0x60004200 0x0 0x40>, /* tertiary controller */ 371 <0x0 0x60004300 0x0 0x40>, /* quaternary controller */ 372 <0x0 0x60004400 0x0 0x40>, /* quinary controller */ 373 <0x0 0x60004500 0x0 0x40>; /* senary controller */ 374 interrupt-controller; 375 #interrupt-cells = <3>; 376 interrupt-parent = <&gic>; 377 }; 378 379 timer@60005000 { 380 compatible = "nvidia,tegra210-timer", "nvidia,tegra20-timer"; 381 reg = <0x0 0x60005000 0x0 0x400>; 382 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 383 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 384 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 385 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 386 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 387 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 388 clocks = <&tegra_car TEGRA210_CLK_TIMER>; 389 clock-names = "timer"; 390 }; 391 392 tegra_car: clock@60006000 { 393 compatible = "nvidia,tegra210-car"; 394 reg = <0x0 0x60006000 0x0 0x1000>; 395 #clock-cells = <1>; 396 #reset-cells = <1>; 397 }; 398 399 flow-controller@60007000 { 400 compatible = "nvidia,tegra210-flowctrl"; 401 reg = <0x0 0x60007000 0x0 0x1000>; 402 }; 403 404 gpio: gpio@6000d000 { 405 compatible = "nvidia,tegra210-gpio", "nvidia,tegra30-gpio"; 406 reg = <0x0 0x6000d000 0x0 0x1000>; 407 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 408 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 409 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 410 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 411 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 412 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 413 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 414 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 415 #gpio-cells = <2>; 416 gpio-controller; 417 #interrupt-cells = <2>; 418 interrupt-controller; 419 }; 420 421 apbdma: dma@60020000 { 422 compatible = "nvidia,tegra210-apbdma", "nvidia,tegra148-apbdma"; 423 reg = <0x0 0x60020000 0x0 0x1400>; 424 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 425 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 426 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 427 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 428 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 429 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 430 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 431 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 432 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 433 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 434 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 435 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 436 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 437 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 438 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 439 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 440 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 441 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 442 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 443 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 444 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 445 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 446 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 447 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 448 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 449 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 450 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 451 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 452 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 453 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 454 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 455 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 456 clocks = <&tegra_car TEGRA210_CLK_APBDMA>; 457 clock-names = "dma"; 458 resets = <&tegra_car 34>; 459 reset-names = "dma"; 460 #dma-cells = <1>; 461 }; 462 463 apbmisc@70000800 { 464 compatible = "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc"; 465 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */ 466 <0x0 0x7000e864 0x0 0x04>; /* Strapping options */ 467 }; 468 469 pinmux: pinmux@700008d4 { 470 compatible = "nvidia,tegra210-pinmux"; 471 reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */ 472 <0x0 0x70003000 0x0 0x294>; /* Mux registers */ 473 }; 474 475 /* 476 * There are two serial driver i.e. 8250 based simple serial 477 * driver and APB DMA based serial driver for higher baudrate 478 * and performance. To enable the 8250 based driver, the compatible 479 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable 480 * the APB DMA based serial driver, the compatible is 481 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". 482 */ 483 uarta: serial@70006000 { 484 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 485 reg = <0x0 0x70006000 0x0 0x40>; 486 reg-shift = <2>; 487 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 488 clocks = <&tegra_car TEGRA210_CLK_UARTA>; 489 clock-names = "serial"; 490 resets = <&tegra_car 6>; 491 reset-names = "serial"; 492 dmas = <&apbdma 8>, <&apbdma 8>; 493 dma-names = "rx", "tx"; 494 status = "disabled"; 495 }; 496 497 uartb: serial@70006040 { 498 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 499 reg = <0x0 0x70006040 0x0 0x40>; 500 reg-shift = <2>; 501 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 502 clocks = <&tegra_car TEGRA210_CLK_UARTB>; 503 clock-names = "serial"; 504 resets = <&tegra_car 7>; 505 reset-names = "serial"; 506 dmas = <&apbdma 9>, <&apbdma 9>; 507 dma-names = "rx", "tx"; 508 status = "disabled"; 509 }; 510 511 uartc: serial@70006200 { 512 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 513 reg = <0x0 0x70006200 0x0 0x40>; 514 reg-shift = <2>; 515 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 516 clocks = <&tegra_car TEGRA210_CLK_UARTC>; 517 clock-names = "serial"; 518 resets = <&tegra_car 55>; 519 reset-names = "serial"; 520 dmas = <&apbdma 10>, <&apbdma 10>; 521 dma-names = "rx", "tx"; 522 status = "disabled"; 523 }; 524 525 uartd: serial@70006300 { 526 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 527 reg = <0x0 0x70006300 0x0 0x40>; 528 reg-shift = <2>; 529 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 530 clocks = <&tegra_car TEGRA210_CLK_UARTD>; 531 clock-names = "serial"; 532 resets = <&tegra_car 65>; 533 reset-names = "serial"; 534 dmas = <&apbdma 19>, <&apbdma 19>; 535 dma-names = "rx", "tx"; 536 status = "disabled"; 537 }; 538 539 pwm: pwm@7000a000 { 540 compatible = "nvidia,tegra210-pwm", "nvidia,tegra20-pwm"; 541 reg = <0x0 0x7000a000 0x0 0x100>; 542 #pwm-cells = <2>; 543 clocks = <&tegra_car TEGRA210_CLK_PWM>; 544 clock-names = "pwm"; 545 resets = <&tegra_car 17>; 546 reset-names = "pwm"; 547 status = "disabled"; 548 }; 549 550 i2c@7000c000 { 551 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 552 reg = <0x0 0x7000c000 0x0 0x100>; 553 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 554 #address-cells = <1>; 555 #size-cells = <0>; 556 clocks = <&tegra_car TEGRA210_CLK_I2C1>; 557 clock-names = "div-clk"; 558 resets = <&tegra_car 12>; 559 reset-names = "i2c"; 560 dmas = <&apbdma 21>, <&apbdma 21>; 561 dma-names = "rx", "tx"; 562 status = "disabled"; 563 }; 564 565 i2c@7000c400 { 566 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 567 reg = <0x0 0x7000c400 0x0 0x100>; 568 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 569 #address-cells = <1>; 570 #size-cells = <0>; 571 clocks = <&tegra_car TEGRA210_CLK_I2C2>; 572 clock-names = "div-clk"; 573 resets = <&tegra_car 54>; 574 reset-names = "i2c"; 575 dmas = <&apbdma 22>, <&apbdma 22>; 576 dma-names = "rx", "tx"; 577 status = "disabled"; 578 }; 579 580 i2c@7000c500 { 581 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 582 reg = <0x0 0x7000c500 0x0 0x100>; 583 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 584 #address-cells = <1>; 585 #size-cells = <0>; 586 clocks = <&tegra_car TEGRA210_CLK_I2C3>; 587 clock-names = "div-clk"; 588 resets = <&tegra_car 67>; 589 reset-names = "i2c"; 590 dmas = <&apbdma 23>, <&apbdma 23>; 591 dma-names = "rx", "tx"; 592 status = "disabled"; 593 }; 594 595 i2c@7000c700 { 596 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 597 reg = <0x0 0x7000c700 0x0 0x100>; 598 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 599 #address-cells = <1>; 600 #size-cells = <0>; 601 clocks = <&tegra_car TEGRA210_CLK_I2C4>; 602 clock-names = "div-clk"; 603 resets = <&tegra_car 103>; 604 reset-names = "i2c"; 605 dmas = <&apbdma 26>, <&apbdma 26>; 606 dma-names = "rx", "tx"; 607 pinctrl-0 = <&state_dpaux1_i2c>; 608 pinctrl-1 = <&state_dpaux1_off>; 609 pinctrl-names = "default", "idle"; 610 status = "disabled"; 611 }; 612 613 i2c@7000d000 { 614 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 615 reg = <0x0 0x7000d000 0x0 0x100>; 616 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 617 #address-cells = <1>; 618 #size-cells = <0>; 619 clocks = <&tegra_car TEGRA210_CLK_I2C5>; 620 clock-names = "div-clk"; 621 resets = <&tegra_car 47>; 622 reset-names = "i2c"; 623 dmas = <&apbdma 24>, <&apbdma 24>; 624 dma-names = "rx", "tx"; 625 status = "disabled"; 626 }; 627 628 i2c@7000d100 { 629 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 630 reg = <0x0 0x7000d100 0x0 0x100>; 631 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 632 #address-cells = <1>; 633 #size-cells = <0>; 634 clocks = <&tegra_car TEGRA210_CLK_I2C6>; 635 clock-names = "div-clk"; 636 resets = <&tegra_car 166>; 637 reset-names = "i2c"; 638 dmas = <&apbdma 30>, <&apbdma 30>; 639 dma-names = "rx", "tx"; 640 pinctrl-0 = <&state_dpaux_i2c>; 641 pinctrl-1 = <&state_dpaux_off>; 642 pinctrl-names = "default", "idle"; 643 status = "disabled"; 644 }; 645 646 spi@7000d400 { 647 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 648 reg = <0x0 0x7000d400 0x0 0x200>; 649 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 650 #address-cells = <1>; 651 #size-cells = <0>; 652 clocks = <&tegra_car TEGRA210_CLK_SBC1>; 653 clock-names = "spi"; 654 resets = <&tegra_car 41>; 655 reset-names = "spi"; 656 dmas = <&apbdma 15>, <&apbdma 15>; 657 dma-names = "rx", "tx"; 658 status = "disabled"; 659 }; 660 661 spi@7000d600 { 662 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 663 reg = <0x0 0x7000d600 0x0 0x200>; 664 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 665 #address-cells = <1>; 666 #size-cells = <0>; 667 clocks = <&tegra_car TEGRA210_CLK_SBC2>; 668 clock-names = "spi"; 669 resets = <&tegra_car 44>; 670 reset-names = "spi"; 671 dmas = <&apbdma 16>, <&apbdma 16>; 672 dma-names = "rx", "tx"; 673 status = "disabled"; 674 }; 675 676 spi@7000d800 { 677 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 678 reg = <0x0 0x7000d800 0x0 0x200>; 679 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 680 #address-cells = <1>; 681 #size-cells = <0>; 682 clocks = <&tegra_car TEGRA210_CLK_SBC3>; 683 clock-names = "spi"; 684 resets = <&tegra_car 46>; 685 reset-names = "spi"; 686 dmas = <&apbdma 17>, <&apbdma 17>; 687 dma-names = "rx", "tx"; 688 status = "disabled"; 689 }; 690 691 spi@7000da00 { 692 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 693 reg = <0x0 0x7000da00 0x0 0x200>; 694 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 695 #address-cells = <1>; 696 #size-cells = <0>; 697 clocks = <&tegra_car TEGRA210_CLK_SBC4>; 698 clock-names = "spi"; 699 resets = <&tegra_car 68>; 700 reset-names = "spi"; 701 dmas = <&apbdma 18>, <&apbdma 18>; 702 dma-names = "rx", "tx"; 703 status = "disabled"; 704 }; 705 706 rtc@7000e000 { 707 compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc"; 708 reg = <0x0 0x7000e000 0x0 0x100>; 709 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 710 clocks = <&tegra_car TEGRA210_CLK_RTC>; 711 clock-names = "rtc"; 712 }; 713 714 pmc: pmc@7000e400 { 715 compatible = "nvidia,tegra210-pmc"; 716 reg = <0x0 0x7000e400 0x0 0x400>; 717 clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; 718 clock-names = "pclk", "clk32k_in"; 719 720 powergates { 721 pd_audio: aud { 722 clocks = <&tegra_car TEGRA210_CLK_APE>, 723 <&tegra_car TEGRA210_CLK_APB2APE>; 724 resets = <&tegra_car 198>; 725 #power-domain-cells = <0>; 726 }; 727 728 pd_sor: sor { 729 clocks = <&tegra_car TEGRA210_CLK_SOR0>, 730 <&tegra_car TEGRA210_CLK_SOR1>, 731 <&tegra_car TEGRA210_CLK_CSI>, 732 <&tegra_car TEGRA210_CLK_DSIA>, 733 <&tegra_car TEGRA210_CLK_DSIB>, 734 <&tegra_car TEGRA210_CLK_DPAUX>, 735 <&tegra_car TEGRA210_CLK_DPAUX1>, 736 <&tegra_car TEGRA210_CLK_MIPI_CAL>; 737 resets = <&tegra_car TEGRA210_CLK_SOR0>, 738 <&tegra_car TEGRA210_CLK_SOR1>, 739 <&tegra_car TEGRA210_CLK_CSI>, 740 <&tegra_car TEGRA210_CLK_DSIA>, 741 <&tegra_car TEGRA210_CLK_DSIB>, 742 <&tegra_car TEGRA210_CLK_DPAUX>, 743 <&tegra_car TEGRA210_CLK_DPAUX1>, 744 <&tegra_car TEGRA210_CLK_MIPI_CAL>; 745 #power-domain-cells = <0>; 746 }; 747 748 pd_xusbss: xusba { 749 clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>; 750 resets = <&tegra_car TEGRA210_CLK_XUSB_SS>; 751 #power-domain-cells = <0>; 752 }; 753 754 pd_xusbdev: xusbb { 755 clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>; 756 resets = <&tegra_car 95>; 757 #power-domain-cells = <0>; 758 }; 759 760 pd_xusbhost: xusbc { 761 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>; 762 resets = <&tegra_car TEGRA210_CLK_XUSB_HOST>; 763 #power-domain-cells = <0>; 764 }; 765 766 pd_vic: vic { 767 clocks = <&tegra_car TEGRA210_CLK_VIC03>; 768 clock-names = "vic"; 769 resets = <&tegra_car 178>; 770 reset-names = "vic"; 771 #power-domain-cells = <0>; 772 }; 773 }; 774 }; 775 776 fuse@7000f800 { 777 compatible = "nvidia,tegra210-efuse"; 778 reg = <0x0 0x7000f800 0x0 0x400>; 779 clocks = <&tegra_car TEGRA210_CLK_FUSE>; 780 clock-names = "fuse"; 781 resets = <&tegra_car 39>; 782 reset-names = "fuse"; 783 }; 784 785 mc: memory-controller@70019000 { 786 compatible = "nvidia,tegra210-mc"; 787 reg = <0x0 0x70019000 0x0 0x1000>; 788 clocks = <&tegra_car TEGRA210_CLK_MC>; 789 clock-names = "mc"; 790 791 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 792 793 #iommu-cells = <1>; 794 }; 795 796 hda@70030000 { 797 compatible = "nvidia,tegra210-hda", "nvidia,tegra30-hda"; 798 reg = <0x0 0x70030000 0x0 0x10000>; 799 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 800 clocks = <&tegra_car TEGRA210_CLK_HDA>, 801 <&tegra_car TEGRA210_CLK_HDA2HDMI>, 802 <&tegra_car TEGRA210_CLK_HDA2CODEC_2X>; 803 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 804 resets = <&tegra_car 125>, /* hda */ 805 <&tegra_car 128>, /* hda2hdmi */ 806 <&tegra_car 111>; /* hda2codec_2x */ 807 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 808 status = "disabled"; 809 }; 810 811 usb@70090000 { 812 compatible = "nvidia,tegra210-xusb"; 813 reg = <0x0 0x70090000 0x0 0x8000>, 814 <0x0 0x70098000 0x0 0x1000>, 815 <0x0 0x70099000 0x0 0x1000>; 816 reg-names = "hcd", "fpci", "ipfs"; 817 818 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 819 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 820 821 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>, 822 <&tegra_car TEGRA210_CLK_XUSB_HOST_SRC>, 823 <&tegra_car TEGRA210_CLK_XUSB_FALCON_SRC>, 824 <&tegra_car TEGRA210_CLK_XUSB_SS>, 825 <&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>, 826 <&tegra_car TEGRA210_CLK_XUSB_SS_SRC>, 827 <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>, 828 <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>, 829 <&tegra_car TEGRA210_CLK_PLL_U_480M>, 830 <&tegra_car TEGRA210_CLK_CLK_M>, 831 <&tegra_car TEGRA210_CLK_PLL_E>; 832 clock-names = "xusb_host", "xusb_host_src", 833 "xusb_falcon_src", "xusb_ss", 834 "xusb_ss_div2", "xusb_ss_src", 835 "xusb_hs_src", "xusb_fs_src", 836 "pll_u_480m", "clk_m", "pll_e"; 837 resets = <&tegra_car 89>, <&tegra_car 156>, 838 <&tegra_car 143>; 839 reset-names = "xusb_host", "xusb_ss", "xusb_src"; 840 841 nvidia,xusb-padctl = <&padctl>; 842 843 status = "disabled"; 844 }; 845 846 padctl: padctl@7009f000 { 847 compatible = "nvidia,tegra210-xusb-padctl"; 848 reg = <0x0 0x7009f000 0x0 0x1000>; 849 resets = <&tegra_car 142>; 850 reset-names = "padctl"; 851 852 status = "disabled"; 853 854 pads { 855 usb2 { 856 clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>; 857 clock-names = "trk"; 858 status = "disabled"; 859 860 lanes { 861 usb2-0 { 862 status = "disabled"; 863 #phy-cells = <0>; 864 }; 865 866 usb2-1 { 867 status = "disabled"; 868 #phy-cells = <0>; 869 }; 870 871 usb2-2 { 872 status = "disabled"; 873 #phy-cells = <0>; 874 }; 875 876 usb2-3 { 877 status = "disabled"; 878 #phy-cells = <0>; 879 }; 880 }; 881 }; 882 883 hsic { 884 clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>; 885 clock-names = "trk"; 886 status = "disabled"; 887 888 lanes { 889 hsic-0 { 890 status = "disabled"; 891 #phy-cells = <0>; 892 }; 893 894 hsic-1 { 895 status = "disabled"; 896 #phy-cells = <0>; 897 }; 898 }; 899 }; 900 901 pcie { 902 clocks = <&tegra_car TEGRA210_CLK_PLL_E>; 903 clock-names = "pll"; 904 resets = <&tegra_car 205>; 905 reset-names = "phy"; 906 status = "disabled"; 907 908 lanes { 909 pcie-0 { 910 status = "disabled"; 911 #phy-cells = <0>; 912 }; 913 914 pcie-1 { 915 status = "disabled"; 916 #phy-cells = <0>; 917 }; 918 919 pcie-2 { 920 status = "disabled"; 921 #phy-cells = <0>; 922 }; 923 924 pcie-3 { 925 status = "disabled"; 926 #phy-cells = <0>; 927 }; 928 929 pcie-4 { 930 status = "disabled"; 931 #phy-cells = <0>; 932 }; 933 934 pcie-5 { 935 status = "disabled"; 936 #phy-cells = <0>; 937 }; 938 939 pcie-6 { 940 status = "disabled"; 941 #phy-cells = <0>; 942 }; 943 }; 944 }; 945 946 sata { 947 clocks = <&tegra_car TEGRA210_CLK_PLL_E>; 948 clock-names = "pll"; 949 resets = <&tegra_car 204>; 950 reset-names = "phy"; 951 status = "disabled"; 952 953 lanes { 954 sata-0 { 955 status = "disabled"; 956 #phy-cells = <0>; 957 }; 958 }; 959 }; 960 }; 961 962 ports { 963 usb2-0 { 964 status = "disabled"; 965 }; 966 967 usb2-1 { 968 status = "disabled"; 969 }; 970 971 usb2-2 { 972 status = "disabled"; 973 }; 974 975 usb2-3 { 976 status = "disabled"; 977 }; 978 979 hsic-0 { 980 status = "disabled"; 981 }; 982 983 usb3-0 { 984 status = "disabled"; 985 }; 986 987 usb3-1 { 988 status = "disabled"; 989 }; 990 991 usb3-2 { 992 status = "disabled"; 993 }; 994 995 usb3-3 { 996 status = "disabled"; 997 }; 998 }; 999 }; 1000 1001 sdhci@700b0000 { 1002 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; 1003 reg = <0x0 0x700b0000 0x0 0x200>; 1004 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1005 clocks = <&tegra_car TEGRA210_CLK_SDMMC1>; 1006 clock-names = "sdhci"; 1007 resets = <&tegra_car 14>; 1008 reset-names = "sdhci"; 1009 status = "disabled"; 1010 }; 1011 1012 sdhci@700b0200 { 1013 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; 1014 reg = <0x0 0x700b0200 0x0 0x200>; 1015 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 1016 clocks = <&tegra_car TEGRA210_CLK_SDMMC2>; 1017 clock-names = "sdhci"; 1018 resets = <&tegra_car 9>; 1019 reset-names = "sdhci"; 1020 status = "disabled"; 1021 }; 1022 1023 sdhci@700b0400 { 1024 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; 1025 reg = <0x0 0x700b0400 0x0 0x200>; 1026 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 1027 clocks = <&tegra_car TEGRA210_CLK_SDMMC3>; 1028 clock-names = "sdhci"; 1029 resets = <&tegra_car 69>; 1030 reset-names = "sdhci"; 1031 status = "disabled"; 1032 }; 1033 1034 sdhci@700b0600 { 1035 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; 1036 reg = <0x0 0x700b0600 0x0 0x200>; 1037 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1038 clocks = <&tegra_car TEGRA210_CLK_SDMMC4>; 1039 clock-names = "sdhci"; 1040 resets = <&tegra_car 15>; 1041 reset-names = "sdhci"; 1042 status = "disabled"; 1043 }; 1044 1045 mipi: mipi@700e3000 { 1046 compatible = "nvidia,tegra210-mipi"; 1047 reg = <0x0 0x700e3000 0x0 0x100>; 1048 clocks = <&tegra_car TEGRA210_CLK_MIPI_CAL>; 1049 clock-names = "mipi-cal"; 1050 power-domains = <&pd_sor>; 1051 #nvidia,mipi-calibrate-cells = <1>; 1052 }; 1053 1054 aconnect@702c0000 { 1055 compatible = "nvidia,tegra210-aconnect"; 1056 clocks = <&tegra_car TEGRA210_CLK_APE>, 1057 <&tegra_car TEGRA210_CLK_APB2APE>; 1058 clock-names = "ape", "apb2ape"; 1059 power-domains = <&pd_audio>; 1060 #address-cells = <1>; 1061 #size-cells = <1>; 1062 ranges = <0x702c0000 0x0 0x702c0000 0x00040000>; 1063 status = "disabled"; 1064 1065 adma: dma@702e2000 { 1066 compatible = "nvidia,tegra210-adma"; 1067 reg = <0x702e2000 0x2000>; 1068 interrupt-parent = <&agic>; 1069 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 1070 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 1071 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 1072 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 1073 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 1074 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 1075 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 1076 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 1077 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 1078 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 1079 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 1080 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 1081 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 1082 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 1083 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 1084 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 1085 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 1086 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 1087 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 1088 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 1089 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 1090 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1091 #dma-cells = <1>; 1092 clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>; 1093 clock-names = "d_audio"; 1094 status = "disabled"; 1095 }; 1096 1097 agic: agic@702f9000 { 1098 compatible = "nvidia,tegra210-agic"; 1099 #interrupt-cells = <3>; 1100 interrupt-controller; 1101 reg = <0x702f9000 0x2000>, 1102 <0x702fa000 0x2000>; 1103 interrupts = <GIC_SPI 102 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1104 clocks = <&tegra_car TEGRA210_CLK_APE>; 1105 clock-names = "clk"; 1106 status = "disabled"; 1107 }; 1108 }; 1109 1110 spi@70410000 { 1111 compatible = "nvidia,tegra210-qspi"; 1112 reg = <0x0 0x70410000 0x0 0x1000>; 1113 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1114 #address-cells = <1>; 1115 #size-cells = <0>; 1116 clocks = <&tegra_car TEGRA210_CLK_QSPI>; 1117 clock-names = "qspi"; 1118 resets = <&tegra_car 211>; 1119 reset-names = "qspi"; 1120 dmas = <&apbdma 5>, <&apbdma 5>; 1121 dma-names = "rx", "tx"; 1122 status = "disabled"; 1123 }; 1124 1125 usb@7d000000 { 1126 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 1127 reg = <0x0 0x7d000000 0x0 0x4000>; 1128 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1129 phy_type = "utmi"; 1130 clocks = <&tegra_car TEGRA210_CLK_USBD>; 1131 clock-names = "usb"; 1132 resets = <&tegra_car 22>; 1133 reset-names = "usb"; 1134 nvidia,phy = <&phy1>; 1135 status = "disabled"; 1136 }; 1137 1138 phy1: usb-phy@7d000000 { 1139 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; 1140 reg = <0x0 0x7d000000 0x0 0x4000>, 1141 <0x0 0x7d000000 0x0 0x4000>; 1142 phy_type = "utmi"; 1143 clocks = <&tegra_car TEGRA210_CLK_USBD>, 1144 <&tegra_car TEGRA210_CLK_PLL_U>, 1145 <&tegra_car TEGRA210_CLK_USBD>; 1146 clock-names = "reg", "pll_u", "utmi-pads"; 1147 resets = <&tegra_car 22>, <&tegra_car 22>; 1148 reset-names = "usb", "utmi-pads"; 1149 nvidia,hssync-start-delay = <0>; 1150 nvidia,idle-wait-delay = <17>; 1151 nvidia,elastic-limit = <16>; 1152 nvidia,term-range-adj = <6>; 1153 nvidia,xcvr-setup = <9>; 1154 nvidia,xcvr-lsfslew = <0>; 1155 nvidia,xcvr-lsrslew = <3>; 1156 nvidia,hssquelch-level = <2>; 1157 nvidia,hsdiscon-level = <5>; 1158 nvidia,xcvr-hsslew = <12>; 1159 nvidia,has-utmi-pad-registers; 1160 status = "disabled"; 1161 }; 1162 1163 usb@7d004000 { 1164 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 1165 reg = <0x0 0x7d004000 0x0 0x4000>; 1166 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1167 phy_type = "utmi"; 1168 clocks = <&tegra_car TEGRA210_CLK_USB2>; 1169 clock-names = "usb"; 1170 resets = <&tegra_car 58>; 1171 reset-names = "usb"; 1172 nvidia,phy = <&phy2>; 1173 status = "disabled"; 1174 }; 1175 1176 phy2: usb-phy@7d004000 { 1177 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; 1178 reg = <0x0 0x7d004000 0x0 0x4000>, 1179 <0x0 0x7d000000 0x0 0x4000>; 1180 phy_type = "utmi"; 1181 clocks = <&tegra_car TEGRA210_CLK_USB2>, 1182 <&tegra_car TEGRA210_CLK_PLL_U>, 1183 <&tegra_car TEGRA210_CLK_USBD>; 1184 clock-names = "reg", "pll_u", "utmi-pads"; 1185 resets = <&tegra_car 58>, <&tegra_car 22>; 1186 reset-names = "usb", "utmi-pads"; 1187 nvidia,hssync-start-delay = <0>; 1188 nvidia,idle-wait-delay = <17>; 1189 nvidia,elastic-limit = <16>; 1190 nvidia,term-range-adj = <6>; 1191 nvidia,xcvr-setup = <9>; 1192 nvidia,xcvr-lsfslew = <0>; 1193 nvidia,xcvr-lsrslew = <3>; 1194 nvidia,hssquelch-level = <2>; 1195 nvidia,hsdiscon-level = <5>; 1196 nvidia,xcvr-hsslew = <12>; 1197 status = "disabled"; 1198 }; 1199 1200 cpus { 1201 #address-cells = <1>; 1202 #size-cells = <0>; 1203 1204 cpu@0 { 1205 device_type = "cpu"; 1206 compatible = "arm,cortex-a57"; 1207 reg = <0>; 1208 }; 1209 1210 cpu@1 { 1211 device_type = "cpu"; 1212 compatible = "arm,cortex-a57"; 1213 reg = <1>; 1214 }; 1215 1216 cpu@2 { 1217 device_type = "cpu"; 1218 compatible = "arm,cortex-a57"; 1219 reg = <2>; 1220 }; 1221 1222 cpu@3 { 1223 device_type = "cpu"; 1224 compatible = "arm,cortex-a57"; 1225 reg = <3>; 1226 }; 1227 }; 1228 1229 timer { 1230 compatible = "arm,armv8-timer"; 1231 interrupts = <GIC_PPI 13 1232 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1233 <GIC_PPI 14 1234 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1235 <GIC_PPI 11 1236 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1237 <GIC_PPI 10 1238 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1239 interrupt-parent = <&gic>; 1240 }; 1241 1242 soctherm: thermal-sensor@700e2000 { 1243 compatible = "nvidia,tegra210-soctherm"; 1244 reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */ 1245 0x0 0x60006000 0x0 0x400>; /* CAR reg_base */ 1246 reg-names = "soctherm-reg", "car-reg"; 1247 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 1248 clocks = <&tegra_car TEGRA210_CLK_TSENSOR>, 1249 <&tegra_car TEGRA210_CLK_SOC_THERM>; 1250 clock-names = "tsensor", "soctherm"; 1251 resets = <&tegra_car 78>; 1252 reset-names = "soctherm"; 1253 #thermal-sensor-cells = <1>; 1254 1255 throttle-cfgs { 1256 throttle_heavy: heavy { 1257 nvidia,priority = <100>; 1258 nvidia,cpu-throt-percent = <85>; 1259 1260 #cooling-cells = <2>; 1261 }; 1262 }; 1263 }; 1264 1265 thermal-zones { 1266 cpu { 1267 polling-delay-passive = <1000>; 1268 polling-delay = <0>; 1269 1270 thermal-sensors = 1271 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; 1272 1273 trips { 1274 cpu-shutdown-trip { 1275 temperature = <102500>; 1276 hysteresis = <0>; 1277 type = "critical"; 1278 }; 1279 1280 cpu_throttle_trip: throttle-trip { 1281 temperature = <98500>; 1282 hysteresis = <1000>; 1283 type = "hot"; 1284 }; 1285 }; 1286 1287 cooling-maps { 1288 map0 { 1289 trip = <&cpu_throttle_trip>; 1290 cooling-device = <&throttle_heavy 1 1>; 1291 }; 1292 }; 1293 }; 1294 mem { 1295 polling-delay-passive = <0>; 1296 polling-delay = <0>; 1297 1298 thermal-sensors = 1299 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>; 1300 1301 trips { 1302 mem-shutdown-trip { 1303 temperature = <103000>; 1304 hysteresis = <0>; 1305 type = "critical"; 1306 }; 1307 }; 1308 1309 cooling-maps { 1310 /* 1311 * There are currently no cooling maps, 1312 * because there are no cooling devices. 1313 */ 1314 }; 1315 }; 1316 gpu { 1317 polling-delay-passive = <1000>; 1318 polling-delay = <0>; 1319 1320 thermal-sensors = 1321 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>; 1322 1323 trips { 1324 gpu-shutdown-trip { 1325 temperature = <103000>; 1326 hysteresis = <0>; 1327 type = "critical"; 1328 }; 1329 1330 gpu_throttle_trip: throttle-trip { 1331 temperature = <100000>; 1332 hysteresis = <1000>; 1333 type = "hot"; 1334 }; 1335 }; 1336 1337 cooling-maps { 1338 map0 { 1339 trip = <&gpu_throttle_trip>; 1340 cooling-device = <&throttle_heavy 1 1>; 1341 }; 1342 }; 1343 }; 1344 pllx { 1345 polling-delay-passive = <0>; 1346 polling-delay = <0>; 1347 1348 thermal-sensors = 1349 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>; 1350 1351 trips { 1352 pllx-shutdown-trip { 1353 temperature = <103000>; 1354 hysteresis = <0>; 1355 type = "critical"; 1356 }; 1357 }; 1358 1359 cooling-maps { 1360 /* 1361 * There are currently no cooling maps, 1362 * because there are no cooling devices. 1363 */ 1364 }; 1365 }; 1366 }; 1367}; 1368