1#include <dt-bindings/clock/tegra210-car.h> 2#include <dt-bindings/gpio/tegra-gpio.h> 3#include <dt-bindings/memory/tegra210-mc.h> 4#include <dt-bindings/pinctrl/pinctrl-tegra.h> 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6 7/ { 8 compatible = "nvidia,tegra210"; 9 interrupt-parent = <&lic>; 10 #address-cells = <2>; 11 #size-cells = <2>; 12 13 host1x@50000000 { 14 compatible = "nvidia,tegra210-host1x", "simple-bus"; 15 reg = <0x0 0x50000000 0x0 0x00034000>; 16 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 17 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ 18 clocks = <&tegra_car TEGRA210_CLK_HOST1X>; 19 clock-names = "host1x"; 20 resets = <&tegra_car 28>; 21 reset-names = "host1x"; 22 23 #address-cells = <2>; 24 #size-cells = <2>; 25 26 ranges = <0x0 0x54000000 0x0 0x54000000 0x0 0x01000000>; 27 28 dpaux1: dpaux@54040000 { 29 compatible = "nvidia,tegra210-dpaux"; 30 reg = <0x0 0x54040000 0x0 0x00040000>; 31 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 32 clocks = <&tegra_car TEGRA210_CLK_DPAUX1>, 33 <&tegra_car TEGRA210_CLK_PLL_DP>; 34 clock-names = "dpaux", "parent"; 35 resets = <&tegra_car 207>; 36 reset-names = "dpaux"; 37 status = "disabled"; 38 39 state_dpaux1_aux: pinmux-aux { 40 groups = "dpaux-io"; 41 function = "aux"; 42 }; 43 44 state_dpaux1_i2c: pinmux-i2c { 45 groups = "dpaux-io"; 46 function = "i2c"; 47 }; 48 49 state_dpaux1_off: pinmux-off { 50 groups = "dpaux-io"; 51 function = "off"; 52 }; 53 54 i2c-bus { 55 #address-cells = <1>; 56 #size-cells = <0>; 57 }; 58 }; 59 60 vi@54080000 { 61 compatible = "nvidia,tegra210-vi"; 62 reg = <0x0 0x54080000 0x0 0x00040000>; 63 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 64 status = "disabled"; 65 }; 66 67 tsec@54100000 { 68 compatible = "nvidia,tegra210-tsec"; 69 reg = <0x0 0x54100000 0x0 0x00040000>; 70 }; 71 72 dc@54200000 { 73 compatible = "nvidia,tegra210-dc"; 74 reg = <0x0 0x54200000 0x0 0x00040000>; 75 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 76 clocks = <&tegra_car TEGRA210_CLK_DISP1>, 77 <&tegra_car TEGRA210_CLK_PLL_P>; 78 clock-names = "dc", "parent"; 79 resets = <&tegra_car 27>; 80 reset-names = "dc"; 81 82 iommus = <&mc TEGRA_SWGROUP_DC>; 83 84 nvidia,head = <0>; 85 }; 86 87 dc@54240000 { 88 compatible = "nvidia,tegra210-dc"; 89 reg = <0x0 0x54240000 0x0 0x00040000>; 90 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 91 clocks = <&tegra_car TEGRA210_CLK_DISP2>, 92 <&tegra_car TEGRA210_CLK_PLL_P>; 93 clock-names = "dc", "parent"; 94 resets = <&tegra_car 26>; 95 reset-names = "dc"; 96 97 iommus = <&mc TEGRA_SWGROUP_DCB>; 98 99 nvidia,head = <1>; 100 }; 101 102 dsi@54300000 { 103 compatible = "nvidia,tegra210-dsi"; 104 reg = <0x0 0x54300000 0x0 0x00040000>; 105 clocks = <&tegra_car TEGRA210_CLK_DSIA>, 106 <&tegra_car TEGRA210_CLK_DSIALP>, 107 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; 108 clock-names = "dsi", "lp", "parent"; 109 resets = <&tegra_car 48>; 110 reset-names = "dsi"; 111 nvidia,mipi-calibrate = <&mipi 0x0c0>; /* DSIA & DSIB pads */ 112 113 status = "disabled"; 114 115 #address-cells = <1>; 116 #size-cells = <0>; 117 }; 118 119 vic@54340000 { 120 compatible = "nvidia,tegra210-vic"; 121 reg = <0x0 0x54340000 0x0 0x00040000>; 122 status = "disabled"; 123 }; 124 125 nvjpg@54380000 { 126 compatible = "nvidia,tegra210-nvjpg"; 127 reg = <0x0 0x54380000 0x0 0x00040000>; 128 status = "disabled"; 129 }; 130 131 dsi@54400000 { 132 compatible = "nvidia,tegra210-dsi"; 133 reg = <0x0 0x54400000 0x0 0x00040000>; 134 clocks = <&tegra_car TEGRA210_CLK_DSIB>, 135 <&tegra_car TEGRA210_CLK_DSIBLP>, 136 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; 137 clock-names = "dsi", "lp", "parent"; 138 resets = <&tegra_car 82>; 139 reset-names = "dsi"; 140 nvidia,mipi-calibrate = <&mipi 0x300>; /* DSIC & DSID pads */ 141 142 status = "disabled"; 143 144 #address-cells = <1>; 145 #size-cells = <0>; 146 }; 147 148 nvdec@54480000 { 149 compatible = "nvidia,tegra210-nvdec"; 150 reg = <0x0 0x54480000 0x0 0x00040000>; 151 status = "disabled"; 152 }; 153 154 nvenc@544c0000 { 155 compatible = "nvidia,tegra210-nvenc"; 156 reg = <0x0 0x544c0000 0x0 0x00040000>; 157 status = "disabled"; 158 }; 159 160 tsec@54500000 { 161 compatible = "nvidia,tegra210-tsec"; 162 reg = <0x0 0x54500000 0x0 0x00040000>; 163 status = "disabled"; 164 }; 165 166 sor@54540000 { 167 compatible = "nvidia,tegra210-sor"; 168 reg = <0x0 0x54540000 0x0 0x00040000>; 169 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 170 clocks = <&tegra_car TEGRA210_CLK_SOR0>, 171 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>, 172 <&tegra_car TEGRA210_CLK_PLL_DP>, 173 <&tegra_car TEGRA210_CLK_SOR_SAFE>; 174 clock-names = "sor", "parent", "dp", "safe"; 175 resets = <&tegra_car 182>; 176 reset-names = "sor"; 177 pinctrl-0 = <&state_dpaux_aux>; 178 pinctrl-1 = <&state_dpaux_i2c>; 179 pinctrl-2 = <&state_dpaux_off>; 180 pinctrl-names = "aux", "i2c", "off"; 181 status = "disabled"; 182 }; 183 184 sor@54580000 { 185 compatible = "nvidia,tegra210-sor1"; 186 reg = <0x0 0x54580000 0x0 0x00040000>; 187 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 188 clocks = <&tegra_car TEGRA210_CLK_SOR1>, 189 <&tegra_car TEGRA210_CLK_SOR1_SRC>, 190 <&tegra_car TEGRA210_CLK_PLL_D2_OUT0>, 191 <&tegra_car TEGRA210_CLK_PLL_DP>, 192 <&tegra_car TEGRA210_CLK_SOR_SAFE>; 193 clock-names = "sor", "source", "parent", "dp", "safe"; 194 resets = <&tegra_car 183>; 195 reset-names = "sor"; 196 pinctrl-0 = <&state_dpaux1_aux>; 197 pinctrl-1 = <&state_dpaux1_i2c>; 198 pinctrl-2 = <&state_dpaux1_off>; 199 pinctrl-names = "aux", "i2c", "off"; 200 status = "disabled"; 201 }; 202 203 dpaux: dpaux@545c0000 { 204 compatible = "nvidia,tegra124-dpaux"; 205 reg = <0x0 0x545c0000 0x0 0x00040000>; 206 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 207 clocks = <&tegra_car TEGRA210_CLK_DPAUX>, 208 <&tegra_car TEGRA210_CLK_PLL_DP>; 209 clock-names = "dpaux", "parent"; 210 resets = <&tegra_car 181>; 211 reset-names = "dpaux"; 212 status = "disabled"; 213 214 state_dpaux_aux: pinmux-aux { 215 groups = "dpaux-io"; 216 function = "aux"; 217 }; 218 219 state_dpaux_i2c: pinmux-i2c { 220 groups = "dpaux-io"; 221 function = "i2c"; 222 }; 223 224 state_dpaux_off: pinmux-off { 225 groups = "dpaux-io"; 226 function = "off"; 227 }; 228 229 i2c-bus { 230 #address-cells = <1>; 231 #size-cells = <0>; 232 }; 233 }; 234 235 isp@54600000 { 236 compatible = "nvidia,tegra210-isp"; 237 reg = <0x0 0x54600000 0x0 0x00040000>; 238 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 239 status = "disabled"; 240 }; 241 242 isp@54680000 { 243 compatible = "nvidia,tegra210-isp"; 244 reg = <0x0 0x54680000 0x0 0x00040000>; 245 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 246 status = "disabled"; 247 }; 248 249 i2c@546c0000 { 250 compatible = "nvidia,tegra210-i2c-vi"; 251 reg = <0x0 0x546c0000 0x0 0x00040000>; 252 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 253 status = "disabled"; 254 }; 255 }; 256 257 gic: interrupt-controller@50041000 { 258 compatible = "arm,gic-400"; 259 #interrupt-cells = <3>; 260 interrupt-controller; 261 reg = <0x0 0x50041000 0x0 0x1000>, 262 <0x0 0x50042000 0x0 0x2000>, 263 <0x0 0x50044000 0x0 0x2000>, 264 <0x0 0x50046000 0x0 0x2000>; 265 interrupts = <GIC_PPI 9 266 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 267 interrupt-parent = <&gic>; 268 }; 269 270 gpu@57000000 { 271 compatible = "nvidia,gm20b"; 272 reg = <0x0 0x57000000 0x0 0x01000000>, 273 <0x0 0x58000000 0x0 0x01000000>; 274 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 275 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 276 interrupt-names = "stall", "nonstall"; 277 clocks = <&tegra_car TEGRA210_CLK_GPU>, 278 <&tegra_car TEGRA210_CLK_PLL_P_OUT5>, 279 <&tegra_car TEGRA210_CLK_PLL_G_REF>; 280 clock-names = "gpu", "pwr", "ref"; 281 resets = <&tegra_car 184>; 282 reset-names = "gpu"; 283 284 iommus = <&mc TEGRA_SWGROUP_GPU>; 285 286 status = "disabled"; 287 }; 288 289 lic: interrupt-controller@60004000 { 290 compatible = "nvidia,tegra210-ictlr"; 291 reg = <0x0 0x60004000 0x0 0x40>, /* primary controller */ 292 <0x0 0x60004100 0x0 0x40>, /* secondary controller */ 293 <0x0 0x60004200 0x0 0x40>, /* tertiary controller */ 294 <0x0 0x60004300 0x0 0x40>, /* quaternary controller */ 295 <0x0 0x60004400 0x0 0x40>, /* quinary controller */ 296 <0x0 0x60004500 0x0 0x40>; /* senary controller */ 297 interrupt-controller; 298 #interrupt-cells = <3>; 299 interrupt-parent = <&gic>; 300 }; 301 302 timer@60005000 { 303 compatible = "nvidia,tegra210-timer", "nvidia,tegra20-timer"; 304 reg = <0x0 0x60005000 0x0 0x400>; 305 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 306 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 307 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 308 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 309 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 310 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 311 clocks = <&tegra_car TEGRA210_CLK_TIMER>; 312 clock-names = "timer"; 313 }; 314 315 tegra_car: clock@60006000 { 316 compatible = "nvidia,tegra210-car"; 317 reg = <0x0 0x60006000 0x0 0x1000>; 318 #clock-cells = <1>; 319 #reset-cells = <1>; 320 }; 321 322 flow-controller@60007000 { 323 compatible = "nvidia,tegra210-flowctrl"; 324 reg = <0x0 0x60007000 0x0 0x1000>; 325 }; 326 327 gpio: gpio@6000d000 { 328 compatible = "nvidia,tegra210-gpio", "nvidia,tegra30-gpio"; 329 reg = <0x0 0x6000d000 0x0 0x1000>; 330 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 331 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 332 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 333 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 334 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 335 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 336 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 337 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 338 #gpio-cells = <2>; 339 gpio-controller; 340 #interrupt-cells = <2>; 341 interrupt-controller; 342 }; 343 344 apbdma: dma@60020000 { 345 compatible = "nvidia,tegra210-apbdma", "nvidia,tegra148-apbdma"; 346 reg = <0x0 0x60020000 0x0 0x1400>; 347 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 348 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 349 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 350 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 351 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 352 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 353 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 354 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 355 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 356 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 357 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 358 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 359 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 360 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 361 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 362 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 363 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 364 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 365 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 366 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 367 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 368 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 369 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 370 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 371 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 372 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 373 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 374 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 375 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 376 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 377 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 378 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 379 clocks = <&tegra_car TEGRA210_CLK_APBDMA>; 380 clock-names = "dma"; 381 resets = <&tegra_car 34>; 382 reset-names = "dma"; 383 #dma-cells = <1>; 384 }; 385 386 apbmisc@70000800 { 387 compatible = "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc"; 388 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */ 389 <0x0 0x7000e864 0x0 0x04>; /* Strapping options */ 390 }; 391 392 pinmux: pinmux@700008d4 { 393 compatible = "nvidia,tegra210-pinmux"; 394 reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */ 395 <0x0 0x70003000 0x0 0x294>; /* Mux registers */ 396 }; 397 398 /* 399 * There are two serial driver i.e. 8250 based simple serial 400 * driver and APB DMA based serial driver for higher baudrate 401 * and performance. To enable the 8250 based driver, the compatible 402 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable 403 * the APB DMA based serial driver, the compatible is 404 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". 405 */ 406 uarta: serial@70006000 { 407 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 408 reg = <0x0 0x70006000 0x0 0x40>; 409 reg-shift = <2>; 410 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 411 clocks = <&tegra_car TEGRA210_CLK_UARTA>; 412 clock-names = "serial"; 413 resets = <&tegra_car 6>; 414 reset-names = "serial"; 415 dmas = <&apbdma 8>, <&apbdma 8>; 416 dma-names = "rx", "tx"; 417 status = "disabled"; 418 }; 419 420 uartb: serial@70006040 { 421 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 422 reg = <0x0 0x70006040 0x0 0x40>; 423 reg-shift = <2>; 424 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 425 clocks = <&tegra_car TEGRA210_CLK_UARTB>; 426 clock-names = "serial"; 427 resets = <&tegra_car 7>; 428 reset-names = "serial"; 429 dmas = <&apbdma 9>, <&apbdma 9>; 430 dma-names = "rx", "tx"; 431 status = "disabled"; 432 }; 433 434 uartc: serial@70006200 { 435 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 436 reg = <0x0 0x70006200 0x0 0x40>; 437 reg-shift = <2>; 438 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 439 clocks = <&tegra_car TEGRA210_CLK_UARTC>; 440 clock-names = "serial"; 441 resets = <&tegra_car 55>; 442 reset-names = "serial"; 443 dmas = <&apbdma 10>, <&apbdma 10>; 444 dma-names = "rx", "tx"; 445 status = "disabled"; 446 }; 447 448 uartd: serial@70006300 { 449 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 450 reg = <0x0 0x70006300 0x0 0x40>; 451 reg-shift = <2>; 452 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 453 clocks = <&tegra_car TEGRA210_CLK_UARTD>; 454 clock-names = "serial"; 455 resets = <&tegra_car 65>; 456 reset-names = "serial"; 457 dmas = <&apbdma 19>, <&apbdma 19>; 458 dma-names = "rx", "tx"; 459 status = "disabled"; 460 }; 461 462 pwm: pwm@7000a000 { 463 compatible = "nvidia,tegra210-pwm", "nvidia,tegra20-pwm"; 464 reg = <0x0 0x7000a000 0x0 0x100>; 465 #pwm-cells = <2>; 466 clocks = <&tegra_car TEGRA210_CLK_PWM>; 467 clock-names = "pwm"; 468 resets = <&tegra_car 17>; 469 reset-names = "pwm"; 470 status = "disabled"; 471 }; 472 473 i2c@7000c000 { 474 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 475 reg = <0x0 0x7000c000 0x0 0x100>; 476 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 477 #address-cells = <1>; 478 #size-cells = <0>; 479 clocks = <&tegra_car TEGRA210_CLK_I2C1>; 480 clock-names = "div-clk"; 481 resets = <&tegra_car 12>; 482 reset-names = "i2c"; 483 dmas = <&apbdma 21>, <&apbdma 21>; 484 dma-names = "rx", "tx"; 485 status = "disabled"; 486 }; 487 488 i2c@7000c400 { 489 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 490 reg = <0x0 0x7000c400 0x0 0x100>; 491 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 492 #address-cells = <1>; 493 #size-cells = <0>; 494 clocks = <&tegra_car TEGRA210_CLK_I2C2>; 495 clock-names = "div-clk"; 496 resets = <&tegra_car 54>; 497 reset-names = "i2c"; 498 dmas = <&apbdma 22>, <&apbdma 22>; 499 dma-names = "rx", "tx"; 500 status = "disabled"; 501 }; 502 503 i2c@7000c500 { 504 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 505 reg = <0x0 0x7000c500 0x0 0x100>; 506 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 507 #address-cells = <1>; 508 #size-cells = <0>; 509 clocks = <&tegra_car TEGRA210_CLK_I2C3>; 510 clock-names = "div-clk"; 511 resets = <&tegra_car 67>; 512 reset-names = "i2c"; 513 dmas = <&apbdma 23>, <&apbdma 23>; 514 dma-names = "rx", "tx"; 515 status = "disabled"; 516 }; 517 518 i2c@7000c700 { 519 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 520 reg = <0x0 0x7000c700 0x0 0x100>; 521 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 522 #address-cells = <1>; 523 #size-cells = <0>; 524 clocks = <&tegra_car TEGRA210_CLK_I2C4>; 525 clock-names = "div-clk"; 526 resets = <&tegra_car 103>; 527 reset-names = "i2c"; 528 dmas = <&apbdma 26>, <&apbdma 26>; 529 dma-names = "rx", "tx"; 530 pinctrl-0 = <&state_dpaux1_i2c>; 531 pinctrl-1 = <&state_dpaux1_off>; 532 pinctrl-names = "default", "idle"; 533 status = "disabled"; 534 }; 535 536 i2c@7000d000 { 537 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 538 reg = <0x0 0x7000d000 0x0 0x100>; 539 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 540 #address-cells = <1>; 541 #size-cells = <0>; 542 clocks = <&tegra_car TEGRA210_CLK_I2C5>; 543 clock-names = "div-clk"; 544 resets = <&tegra_car 47>; 545 reset-names = "i2c"; 546 dmas = <&apbdma 24>, <&apbdma 24>; 547 dma-names = "rx", "tx"; 548 status = "disabled"; 549 }; 550 551 i2c@7000d100 { 552 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 553 reg = <0x0 0x7000d100 0x0 0x100>; 554 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 555 #address-cells = <1>; 556 #size-cells = <0>; 557 clocks = <&tegra_car TEGRA210_CLK_I2C6>; 558 clock-names = "div-clk"; 559 resets = <&tegra_car 166>; 560 reset-names = "i2c"; 561 dmas = <&apbdma 30>, <&apbdma 30>; 562 dma-names = "rx", "tx"; 563 pinctrl-0 = <&state_dpaux_i2c>; 564 pinctrl-1 = <&state_dpaux_off>; 565 pinctrl-names = "default", "idle"; 566 status = "disabled"; 567 }; 568 569 spi@7000d400 { 570 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 571 reg = <0x0 0x7000d400 0x0 0x200>; 572 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 573 #address-cells = <1>; 574 #size-cells = <0>; 575 clocks = <&tegra_car TEGRA210_CLK_SBC1>; 576 clock-names = "spi"; 577 resets = <&tegra_car 41>; 578 reset-names = "spi"; 579 dmas = <&apbdma 15>, <&apbdma 15>; 580 dma-names = "rx", "tx"; 581 status = "disabled"; 582 }; 583 584 spi@7000d600 { 585 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 586 reg = <0x0 0x7000d600 0x0 0x200>; 587 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 588 #address-cells = <1>; 589 #size-cells = <0>; 590 clocks = <&tegra_car TEGRA210_CLK_SBC2>; 591 clock-names = "spi"; 592 resets = <&tegra_car 44>; 593 reset-names = "spi"; 594 dmas = <&apbdma 16>, <&apbdma 16>; 595 dma-names = "rx", "tx"; 596 status = "disabled"; 597 }; 598 599 spi@7000d800 { 600 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 601 reg = <0x0 0x7000d800 0x0 0x200>; 602 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 603 #address-cells = <1>; 604 #size-cells = <0>; 605 clocks = <&tegra_car TEGRA210_CLK_SBC3>; 606 clock-names = "spi"; 607 resets = <&tegra_car 46>; 608 reset-names = "spi"; 609 dmas = <&apbdma 17>, <&apbdma 17>; 610 dma-names = "rx", "tx"; 611 status = "disabled"; 612 }; 613 614 spi@7000da00 { 615 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 616 reg = <0x0 0x7000da00 0x0 0x200>; 617 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 618 #address-cells = <1>; 619 #size-cells = <0>; 620 clocks = <&tegra_car TEGRA210_CLK_SBC4>; 621 clock-names = "spi"; 622 resets = <&tegra_car 68>; 623 reset-names = "spi"; 624 dmas = <&apbdma 18>, <&apbdma 18>; 625 dma-names = "rx", "tx"; 626 status = "disabled"; 627 }; 628 629 rtc@7000e000 { 630 compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc"; 631 reg = <0x0 0x7000e000 0x0 0x100>; 632 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 633 clocks = <&tegra_car TEGRA210_CLK_RTC>; 634 clock-names = "rtc"; 635 }; 636 637 pmc: pmc@7000e400 { 638 compatible = "nvidia,tegra210-pmc"; 639 reg = <0x0 0x7000e400 0x0 0x400>; 640 clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; 641 clock-names = "pclk", "clk32k_in"; 642 643 powergates { 644 pd_audio: aud { 645 clocks = <&tegra_car TEGRA210_CLK_APE>, 646 <&tegra_car TEGRA210_CLK_APB2APE>; 647 resets = <&tegra_car 198>; 648 #power-domain-cells = <0>; 649 }; 650 651 pd_xusbss: xusba { 652 clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>; 653 resets = <&tegra_car TEGRA210_CLK_XUSB_SS>; 654 #power-domain-cells = <0>; 655 }; 656 657 pd_xusbdev: xusbb { 658 clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>; 659 resets = <&tegra_car 95>; 660 #power-domain-cells = <0>; 661 }; 662 663 pd_xusbhost: xusbc { 664 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>; 665 resets = <&tegra_car TEGRA210_CLK_XUSB_HOST>; 666 #power-domain-cells = <0>; 667 }; 668 }; 669 }; 670 671 fuse@7000f800 { 672 compatible = "nvidia,tegra210-efuse"; 673 reg = <0x0 0x7000f800 0x0 0x400>; 674 clocks = <&tegra_car TEGRA210_CLK_FUSE>; 675 clock-names = "fuse"; 676 resets = <&tegra_car 39>; 677 reset-names = "fuse"; 678 }; 679 680 mc: memory-controller@70019000 { 681 compatible = "nvidia,tegra210-mc"; 682 reg = <0x0 0x70019000 0x0 0x1000>; 683 clocks = <&tegra_car TEGRA210_CLK_MC>; 684 clock-names = "mc"; 685 686 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 687 688 #iommu-cells = <1>; 689 }; 690 691 hda@70030000 { 692 compatible = "nvidia,tegra210-hda", "nvidia,tegra30-hda"; 693 reg = <0x0 0x70030000 0x0 0x10000>; 694 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 695 clocks = <&tegra_car TEGRA210_CLK_HDA>, 696 <&tegra_car TEGRA210_CLK_HDA2HDMI>, 697 <&tegra_car TEGRA210_CLK_HDA2CODEC_2X>; 698 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 699 resets = <&tegra_car 125>, /* hda */ 700 <&tegra_car 128>, /* hda2hdmi */ 701 <&tegra_car 111>; /* hda2codec_2x */ 702 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 703 status = "disabled"; 704 }; 705 706 usb@70090000 { 707 compatible = "nvidia,tegra210-xusb"; 708 reg = <0x0 0x70090000 0x0 0x8000>, 709 <0x0 0x70098000 0x0 0x1000>, 710 <0x0 0x70099000 0x0 0x1000>; 711 reg-names = "hcd", "fpci", "ipfs"; 712 713 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 714 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 715 716 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>, 717 <&tegra_car TEGRA210_CLK_XUSB_HOST_SRC>, 718 <&tegra_car TEGRA210_CLK_XUSB_FALCON_SRC>, 719 <&tegra_car TEGRA210_CLK_XUSB_SS>, 720 <&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>, 721 <&tegra_car TEGRA210_CLK_XUSB_SS_SRC>, 722 <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>, 723 <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>, 724 <&tegra_car TEGRA210_CLK_PLL_U_480M>, 725 <&tegra_car TEGRA210_CLK_CLK_M>, 726 <&tegra_car TEGRA210_CLK_PLL_E>; 727 clock-names = "xusb_host", "xusb_host_src", 728 "xusb_falcon_src", "xusb_ss", 729 "xusb_ss_div2", "xusb_ss_src", 730 "xusb_hs_src", "xusb_fs_src", 731 "pll_u_480m", "clk_m", "pll_e"; 732 resets = <&tegra_car 89>, <&tegra_car 156>, 733 <&tegra_car 143>; 734 reset-names = "xusb_host", "xusb_ss", "xusb_src"; 735 736 nvidia,xusb-padctl = <&padctl>; 737 738 status = "disabled"; 739 }; 740 741 padctl: padctl@7009f000 { 742 compatible = "nvidia,tegra210-xusb-padctl"; 743 reg = <0x0 0x7009f000 0x0 0x1000>; 744 resets = <&tegra_car 142>; 745 reset-names = "padctl"; 746 747 status = "disabled"; 748 749 pads { 750 usb2 { 751 clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>; 752 clock-names = "trk"; 753 status = "disabled"; 754 755 lanes { 756 usb2-0 { 757 status = "disabled"; 758 #phy-cells = <0>; 759 }; 760 761 usb2-1 { 762 status = "disabled"; 763 #phy-cells = <0>; 764 }; 765 766 usb2-2 { 767 status = "disabled"; 768 #phy-cells = <0>; 769 }; 770 771 usb2-3 { 772 status = "disabled"; 773 #phy-cells = <0>; 774 }; 775 }; 776 }; 777 778 hsic { 779 clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>; 780 clock-names = "trk"; 781 status = "disabled"; 782 783 lanes { 784 hsic-0 { 785 status = "disabled"; 786 #phy-cells = <0>; 787 }; 788 789 hsic-1 { 790 status = "disabled"; 791 #phy-cells = <0>; 792 }; 793 }; 794 }; 795 796 pcie { 797 clocks = <&tegra_car TEGRA210_CLK_PLL_E>; 798 clock-names = "pll"; 799 resets = <&tegra_car 205>; 800 reset-names = "phy"; 801 status = "disabled"; 802 803 lanes { 804 pcie-0 { 805 status = "disabled"; 806 #phy-cells = <0>; 807 }; 808 809 pcie-1 { 810 status = "disabled"; 811 #phy-cells = <0>; 812 }; 813 814 pcie-2 { 815 status = "disabled"; 816 #phy-cells = <0>; 817 }; 818 819 pcie-3 { 820 status = "disabled"; 821 #phy-cells = <0>; 822 }; 823 824 pcie-4 { 825 status = "disabled"; 826 #phy-cells = <0>; 827 }; 828 829 pcie-5 { 830 status = "disabled"; 831 #phy-cells = <0>; 832 }; 833 834 pcie-6 { 835 status = "disabled"; 836 #phy-cells = <0>; 837 }; 838 }; 839 }; 840 841 sata { 842 clocks = <&tegra_car TEGRA210_CLK_PLL_E>; 843 clock-names = "pll"; 844 resets = <&tegra_car 204>; 845 reset-names = "phy"; 846 status = "disabled"; 847 848 lanes { 849 sata-0 { 850 status = "disabled"; 851 #phy-cells = <0>; 852 }; 853 }; 854 }; 855 }; 856 857 ports { 858 usb2-0 { 859 status = "disabled"; 860 }; 861 862 usb2-1 { 863 status = "disabled"; 864 }; 865 866 usb2-2 { 867 status = "disabled"; 868 }; 869 870 usb2-3 { 871 status = "disabled"; 872 }; 873 874 hsic-0 { 875 status = "disabled"; 876 }; 877 878 usb3-0 { 879 status = "disabled"; 880 }; 881 882 usb3-1 { 883 status = "disabled"; 884 }; 885 886 usb3-2 { 887 status = "disabled"; 888 }; 889 890 usb3-3 { 891 status = "disabled"; 892 }; 893 }; 894 }; 895 896 sdhci@700b0000 { 897 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; 898 reg = <0x0 0x700b0000 0x0 0x200>; 899 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 900 clocks = <&tegra_car TEGRA210_CLK_SDMMC1>; 901 clock-names = "sdhci"; 902 resets = <&tegra_car 14>; 903 reset-names = "sdhci"; 904 status = "disabled"; 905 }; 906 907 sdhci@700b0200 { 908 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; 909 reg = <0x0 0x700b0200 0x0 0x200>; 910 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 911 clocks = <&tegra_car TEGRA210_CLK_SDMMC2>; 912 clock-names = "sdhci"; 913 resets = <&tegra_car 9>; 914 reset-names = "sdhci"; 915 status = "disabled"; 916 }; 917 918 sdhci@700b0400 { 919 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; 920 reg = <0x0 0x700b0400 0x0 0x200>; 921 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 922 clocks = <&tegra_car TEGRA210_CLK_SDMMC3>; 923 clock-names = "sdhci"; 924 resets = <&tegra_car 69>; 925 reset-names = "sdhci"; 926 status = "disabled"; 927 }; 928 929 sdhci@700b0600 { 930 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; 931 reg = <0x0 0x700b0600 0x0 0x200>; 932 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 933 clocks = <&tegra_car TEGRA210_CLK_SDMMC4>; 934 clock-names = "sdhci"; 935 resets = <&tegra_car 15>; 936 reset-names = "sdhci"; 937 status = "disabled"; 938 }; 939 940 mipi: mipi@700e3000 { 941 compatible = "nvidia,tegra210-mipi"; 942 reg = <0x0 0x700e3000 0x0 0x100>; 943 clocks = <&tegra_car TEGRA210_CLK_MIPI_CAL>; 944 clock-names = "mipi-cal"; 945 #nvidia,mipi-calibrate-cells = <1>; 946 }; 947 948 aconnect@702c0000 { 949 compatible = "nvidia,tegra210-aconnect"; 950 clocks = <&tegra_car TEGRA210_CLK_APE>, 951 <&tegra_car TEGRA210_CLK_APB2APE>; 952 clock-names = "ape", "apb2ape"; 953 power-domains = <&pd_audio>; 954 #address-cells = <1>; 955 #size-cells = <1>; 956 ranges = <0x702c0000 0x0 0x702c0000 0x00040000>; 957 status = "disabled"; 958 959 adma: dma@702e2000 { 960 compatible = "nvidia,tegra210-adma"; 961 reg = <0x702e2000 0x2000>; 962 interrupt-parent = <&agic>; 963 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 964 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 965 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 966 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 967 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 968 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 969 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 970 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 971 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 972 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 973 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 974 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 975 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 976 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 977 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 978 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 979 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 980 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 981 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 982 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 983 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 984 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 985 #dma-cells = <1>; 986 clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>; 987 clock-names = "d_audio"; 988 status = "disabled"; 989 }; 990 991 agic: agic@702f9000 { 992 compatible = "nvidia,tegra210-agic"; 993 #interrupt-cells = <3>; 994 interrupt-controller; 995 reg = <0x702f9000 0x2000>, 996 <0x702fa000 0x2000>; 997 interrupts = <GIC_SPI 102 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 998 clocks = <&tegra_car TEGRA210_CLK_APE>; 999 clock-names = "clk"; 1000 status = "disabled"; 1001 }; 1002 }; 1003 1004 spi@70410000 { 1005 compatible = "nvidia,tegra210-qspi"; 1006 reg = <0x0 0x70410000 0x0 0x1000>; 1007 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1008 #address-cells = <1>; 1009 #size-cells = <0>; 1010 clocks = <&tegra_car TEGRA210_CLK_QSPI>; 1011 clock-names = "qspi"; 1012 resets = <&tegra_car 211>; 1013 reset-names = "qspi"; 1014 dmas = <&apbdma 5>, <&apbdma 5>; 1015 dma-names = "rx", "tx"; 1016 status = "disabled"; 1017 }; 1018 1019 usb@7d000000 { 1020 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 1021 reg = <0x0 0x7d000000 0x0 0x4000>; 1022 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1023 phy_type = "utmi"; 1024 clocks = <&tegra_car TEGRA210_CLK_USBD>; 1025 clock-names = "usb"; 1026 resets = <&tegra_car 22>; 1027 reset-names = "usb"; 1028 nvidia,phy = <&phy1>; 1029 status = "disabled"; 1030 }; 1031 1032 phy1: usb-phy@7d000000 { 1033 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; 1034 reg = <0x0 0x7d000000 0x0 0x4000>, 1035 <0x0 0x7d000000 0x0 0x4000>; 1036 phy_type = "utmi"; 1037 clocks = <&tegra_car TEGRA210_CLK_USBD>, 1038 <&tegra_car TEGRA210_CLK_PLL_U>, 1039 <&tegra_car TEGRA210_CLK_USBD>; 1040 clock-names = "reg", "pll_u", "utmi-pads"; 1041 resets = <&tegra_car 22>, <&tegra_car 22>; 1042 reset-names = "usb", "utmi-pads"; 1043 nvidia,hssync-start-delay = <0>; 1044 nvidia,idle-wait-delay = <17>; 1045 nvidia,elastic-limit = <16>; 1046 nvidia,term-range-adj = <6>; 1047 nvidia,xcvr-setup = <9>; 1048 nvidia,xcvr-lsfslew = <0>; 1049 nvidia,xcvr-lsrslew = <3>; 1050 nvidia,hssquelch-level = <2>; 1051 nvidia,hsdiscon-level = <5>; 1052 nvidia,xcvr-hsslew = <12>; 1053 nvidia,has-utmi-pad-registers; 1054 status = "disabled"; 1055 }; 1056 1057 usb@7d004000 { 1058 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 1059 reg = <0x0 0x7d004000 0x0 0x4000>; 1060 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1061 phy_type = "utmi"; 1062 clocks = <&tegra_car TEGRA210_CLK_USB2>; 1063 clock-names = "usb"; 1064 resets = <&tegra_car 58>; 1065 reset-names = "usb"; 1066 nvidia,phy = <&phy2>; 1067 status = "disabled"; 1068 }; 1069 1070 phy2: usb-phy@7d004000 { 1071 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; 1072 reg = <0x0 0x7d004000 0x0 0x4000>, 1073 <0x0 0x7d000000 0x0 0x4000>; 1074 phy_type = "utmi"; 1075 clocks = <&tegra_car TEGRA210_CLK_USB2>, 1076 <&tegra_car TEGRA210_CLK_PLL_U>, 1077 <&tegra_car TEGRA210_CLK_USBD>; 1078 clock-names = "reg", "pll_u", "utmi-pads"; 1079 resets = <&tegra_car 58>, <&tegra_car 22>; 1080 reset-names = "usb", "utmi-pads"; 1081 nvidia,hssync-start-delay = <0>; 1082 nvidia,idle-wait-delay = <17>; 1083 nvidia,elastic-limit = <16>; 1084 nvidia,term-range-adj = <6>; 1085 nvidia,xcvr-setup = <9>; 1086 nvidia,xcvr-lsfslew = <0>; 1087 nvidia,xcvr-lsrslew = <3>; 1088 nvidia,hssquelch-level = <2>; 1089 nvidia,hsdiscon-level = <5>; 1090 nvidia,xcvr-hsslew = <12>; 1091 status = "disabled"; 1092 }; 1093 1094 cpus { 1095 #address-cells = <1>; 1096 #size-cells = <0>; 1097 1098 cpu@0 { 1099 device_type = "cpu"; 1100 compatible = "arm,cortex-a57"; 1101 reg = <0>; 1102 }; 1103 1104 cpu@1 { 1105 device_type = "cpu"; 1106 compatible = "arm,cortex-a57"; 1107 reg = <1>; 1108 }; 1109 1110 cpu@2 { 1111 device_type = "cpu"; 1112 compatible = "arm,cortex-a57"; 1113 reg = <2>; 1114 }; 1115 1116 cpu@3 { 1117 device_type = "cpu"; 1118 compatible = "arm,cortex-a57"; 1119 reg = <3>; 1120 }; 1121 }; 1122 1123 timer { 1124 compatible = "arm,armv8-timer"; 1125 interrupts = <GIC_PPI 13 1126 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1127 <GIC_PPI 14 1128 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1129 <GIC_PPI 11 1130 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1131 <GIC_PPI 10 1132 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1133 interrupt-parent = <&gic>; 1134 }; 1135}; 1136