1742af7e7SThierry Reding#include <dt-bindings/clock/tegra210-car.h> 2742af7e7SThierry Reding#include <dt-bindings/gpio/tegra-gpio.h> 3742af7e7SThierry Reding#include <dt-bindings/memory/tegra210-mc.h> 4742af7e7SThierry Reding#include <dt-bindings/pinctrl/pinctrl-tegra.h> 5742af7e7SThierry Reding#include <dt-bindings/interrupt-controller/arm-gic.h> 6e2bed1ebSWei Ni#include <dt-bindings/thermal/tegra124-soctherm.h> 7742af7e7SThierry Reding 8742af7e7SThierry Reding/ { 9742af7e7SThierry Reding compatible = "nvidia,tegra210"; 10742af7e7SThierry Reding interrupt-parent = <&lic>; 11742af7e7SThierry Reding #address-cells = <2>; 12742af7e7SThierry Reding #size-cells = <2>; 13742af7e7SThierry Reding 14be70771dSThierry Reding host1x@50000000 { 15742af7e7SThierry Reding compatible = "nvidia,tegra210-host1x", "simple-bus"; 16742af7e7SThierry Reding reg = <0x0 0x50000000 0x0 0x00034000>; 17742af7e7SThierry Reding interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 18742af7e7SThierry Reding <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ 19742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_HOST1X>; 20742af7e7SThierry Reding clock-names = "host1x"; 21742af7e7SThierry Reding resets = <&tegra_car 28>; 22742af7e7SThierry Reding reset-names = "host1x"; 23742af7e7SThierry Reding 24742af7e7SThierry Reding #address-cells = <2>; 25742af7e7SThierry Reding #size-cells = <2>; 26742af7e7SThierry Reding 27742af7e7SThierry Reding ranges = <0x0 0x54000000 0x0 0x54000000 0x0 0x01000000>; 28742af7e7SThierry Reding 29be70771dSThierry Reding dpaux1: dpaux@54040000 { 30742af7e7SThierry Reding compatible = "nvidia,tegra210-dpaux"; 31742af7e7SThierry Reding reg = <0x0 0x54040000 0x0 0x00040000>; 32742af7e7SThierry Reding interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 33742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_DPAUX1>, 34742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_PLL_DP>; 35742af7e7SThierry Reding clock-names = "dpaux", "parent"; 36742af7e7SThierry Reding resets = <&tegra_car 207>; 37742af7e7SThierry Reding reset-names = "dpaux"; 38742af7e7SThierry Reding status = "disabled"; 3966b2d6e9SJon Hunter 4066b2d6e9SJon Hunter state_dpaux1_aux: pinmux-aux { 4166b2d6e9SJon Hunter groups = "dpaux-io"; 4266b2d6e9SJon Hunter function = "aux"; 4366b2d6e9SJon Hunter }; 4466b2d6e9SJon Hunter 4566b2d6e9SJon Hunter state_dpaux1_i2c: pinmux-i2c { 4666b2d6e9SJon Hunter groups = "dpaux-io"; 4766b2d6e9SJon Hunter function = "i2c"; 4866b2d6e9SJon Hunter }; 4966b2d6e9SJon Hunter 5066b2d6e9SJon Hunter state_dpaux1_off: pinmux-off { 5166b2d6e9SJon Hunter groups = "dpaux-io"; 5266b2d6e9SJon Hunter function = "off"; 5366b2d6e9SJon Hunter }; 5466b2d6e9SJon Hunter 5566b2d6e9SJon Hunter i2c-bus { 5666b2d6e9SJon Hunter #address-cells = <1>; 5766b2d6e9SJon Hunter #size-cells = <0>; 5866b2d6e9SJon Hunter }; 59742af7e7SThierry Reding }; 60742af7e7SThierry Reding 61be70771dSThierry Reding vi@54080000 { 62742af7e7SThierry Reding compatible = "nvidia,tegra210-vi"; 63742af7e7SThierry Reding reg = <0x0 0x54080000 0x0 0x00040000>; 64742af7e7SThierry Reding interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 65742af7e7SThierry Reding status = "disabled"; 66742af7e7SThierry Reding }; 67742af7e7SThierry Reding 68be70771dSThierry Reding tsec@54100000 { 69742af7e7SThierry Reding compatible = "nvidia,tegra210-tsec"; 70742af7e7SThierry Reding reg = <0x0 0x54100000 0x0 0x00040000>; 71742af7e7SThierry Reding }; 72742af7e7SThierry Reding 73be70771dSThierry Reding dc@54200000 { 74742af7e7SThierry Reding compatible = "nvidia,tegra210-dc"; 75742af7e7SThierry Reding reg = <0x0 0x54200000 0x0 0x00040000>; 76742af7e7SThierry Reding interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 77742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_DISP1>, 78742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_PLL_P>; 79742af7e7SThierry Reding clock-names = "dc", "parent"; 80742af7e7SThierry Reding resets = <&tegra_car 27>; 81742af7e7SThierry Reding reset-names = "dc"; 82742af7e7SThierry Reding 83742af7e7SThierry Reding iommus = <&mc TEGRA_SWGROUP_DC>; 84742af7e7SThierry Reding 85742af7e7SThierry Reding nvidia,head = <0>; 86742af7e7SThierry Reding }; 87742af7e7SThierry Reding 88be70771dSThierry Reding dc@54240000 { 89742af7e7SThierry Reding compatible = "nvidia,tegra210-dc"; 90742af7e7SThierry Reding reg = <0x0 0x54240000 0x0 0x00040000>; 91742af7e7SThierry Reding interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 92742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_DISP2>, 93742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_PLL_P>; 94742af7e7SThierry Reding clock-names = "dc", "parent"; 95742af7e7SThierry Reding resets = <&tegra_car 26>; 96742af7e7SThierry Reding reset-names = "dc"; 97742af7e7SThierry Reding 98742af7e7SThierry Reding iommus = <&mc TEGRA_SWGROUP_DCB>; 99742af7e7SThierry Reding 100742af7e7SThierry Reding nvidia,head = <1>; 101742af7e7SThierry Reding }; 102742af7e7SThierry Reding 103be70771dSThierry Reding dsi@54300000 { 104742af7e7SThierry Reding compatible = "nvidia,tegra210-dsi"; 105742af7e7SThierry Reding reg = <0x0 0x54300000 0x0 0x00040000>; 106742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_DSIA>, 107742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_DSIALP>, 108742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; 109742af7e7SThierry Reding clock-names = "dsi", "lp", "parent"; 110742af7e7SThierry Reding resets = <&tegra_car 48>; 111742af7e7SThierry Reding reset-names = "dsi"; 112742af7e7SThierry Reding nvidia,mipi-calibrate = <&mipi 0x0c0>; /* DSIA & DSIB pads */ 113742af7e7SThierry Reding 114742af7e7SThierry Reding status = "disabled"; 115742af7e7SThierry Reding 116742af7e7SThierry Reding #address-cells = <1>; 117742af7e7SThierry Reding #size-cells = <0>; 118742af7e7SThierry Reding }; 119742af7e7SThierry Reding 120be70771dSThierry Reding vic@54340000 { 121742af7e7SThierry Reding compatible = "nvidia,tegra210-vic"; 122742af7e7SThierry Reding reg = <0x0 0x54340000 0x0 0x00040000>; 123742af7e7SThierry Reding status = "disabled"; 124742af7e7SThierry Reding }; 125742af7e7SThierry Reding 126be70771dSThierry Reding nvjpg@54380000 { 127742af7e7SThierry Reding compatible = "nvidia,tegra210-nvjpg"; 128742af7e7SThierry Reding reg = <0x0 0x54380000 0x0 0x00040000>; 129742af7e7SThierry Reding status = "disabled"; 130742af7e7SThierry Reding }; 131742af7e7SThierry Reding 132be70771dSThierry Reding dsi@54400000 { 133742af7e7SThierry Reding compatible = "nvidia,tegra210-dsi"; 134742af7e7SThierry Reding reg = <0x0 0x54400000 0x0 0x00040000>; 135742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_DSIB>, 136742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_DSIBLP>, 137742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; 138742af7e7SThierry Reding clock-names = "dsi", "lp", "parent"; 139742af7e7SThierry Reding resets = <&tegra_car 82>; 140742af7e7SThierry Reding reset-names = "dsi"; 141742af7e7SThierry Reding nvidia,mipi-calibrate = <&mipi 0x300>; /* DSIC & DSID pads */ 142742af7e7SThierry Reding 143742af7e7SThierry Reding status = "disabled"; 144742af7e7SThierry Reding 145742af7e7SThierry Reding #address-cells = <1>; 146742af7e7SThierry Reding #size-cells = <0>; 147742af7e7SThierry Reding }; 148742af7e7SThierry Reding 149be70771dSThierry Reding nvdec@54480000 { 150742af7e7SThierry Reding compatible = "nvidia,tegra210-nvdec"; 151742af7e7SThierry Reding reg = <0x0 0x54480000 0x0 0x00040000>; 152742af7e7SThierry Reding status = "disabled"; 153742af7e7SThierry Reding }; 154742af7e7SThierry Reding 155be70771dSThierry Reding nvenc@544c0000 { 156742af7e7SThierry Reding compatible = "nvidia,tegra210-nvenc"; 157742af7e7SThierry Reding reg = <0x0 0x544c0000 0x0 0x00040000>; 158742af7e7SThierry Reding status = "disabled"; 159742af7e7SThierry Reding }; 160742af7e7SThierry Reding 161be70771dSThierry Reding tsec@54500000 { 162742af7e7SThierry Reding compatible = "nvidia,tegra210-tsec"; 163742af7e7SThierry Reding reg = <0x0 0x54500000 0x0 0x00040000>; 164742af7e7SThierry Reding status = "disabled"; 165742af7e7SThierry Reding }; 166742af7e7SThierry Reding 167be70771dSThierry Reding sor@54540000 { 168742af7e7SThierry Reding compatible = "nvidia,tegra210-sor"; 169742af7e7SThierry Reding reg = <0x0 0x54540000 0x0 0x00040000>; 170742af7e7SThierry Reding interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 171742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_SOR0>, 172742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_PLL_D_OUT0>, 173742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_PLL_DP>, 174742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_SOR_SAFE>; 175742af7e7SThierry Reding clock-names = "sor", "parent", "dp", "safe"; 176742af7e7SThierry Reding resets = <&tegra_car 182>; 177742af7e7SThierry Reding reset-names = "sor"; 17866b2d6e9SJon Hunter pinctrl-0 = <&state_dpaux_aux>; 17966b2d6e9SJon Hunter pinctrl-1 = <&state_dpaux_i2c>; 18066b2d6e9SJon Hunter pinctrl-2 = <&state_dpaux_off>; 18166b2d6e9SJon Hunter pinctrl-names = "aux", "i2c", "off"; 182742af7e7SThierry Reding status = "disabled"; 183742af7e7SThierry Reding }; 184742af7e7SThierry Reding 185be70771dSThierry Reding sor@54580000 { 186742af7e7SThierry Reding compatible = "nvidia,tegra210-sor1"; 187742af7e7SThierry Reding reg = <0x0 0x54580000 0x0 0x00040000>; 188742af7e7SThierry Reding interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 189742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_SOR1>, 190237d5cc7SThierry Reding <&tegra_car TEGRA210_CLK_SOR1_SRC>, 191742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_PLL_D2_OUT0>, 192742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_PLL_DP>, 193742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_SOR_SAFE>; 194237d5cc7SThierry Reding clock-names = "sor", "source", "parent", "dp", "safe"; 195742af7e7SThierry Reding resets = <&tegra_car 183>; 196742af7e7SThierry Reding reset-names = "sor"; 19766b2d6e9SJon Hunter pinctrl-0 = <&state_dpaux1_aux>; 19866b2d6e9SJon Hunter pinctrl-1 = <&state_dpaux1_i2c>; 19966b2d6e9SJon Hunter pinctrl-2 = <&state_dpaux1_off>; 20066b2d6e9SJon Hunter pinctrl-names = "aux", "i2c", "off"; 201742af7e7SThierry Reding status = "disabled"; 202742af7e7SThierry Reding }; 203742af7e7SThierry Reding 204be70771dSThierry Reding dpaux: dpaux@545c0000 { 205742af7e7SThierry Reding compatible = "nvidia,tegra124-dpaux"; 206742af7e7SThierry Reding reg = <0x0 0x545c0000 0x0 0x00040000>; 207742af7e7SThierry Reding interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 208742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_DPAUX>, 209742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_PLL_DP>; 210742af7e7SThierry Reding clock-names = "dpaux", "parent"; 211742af7e7SThierry Reding resets = <&tegra_car 181>; 212742af7e7SThierry Reding reset-names = "dpaux"; 213742af7e7SThierry Reding status = "disabled"; 21466b2d6e9SJon Hunter 21566b2d6e9SJon Hunter state_dpaux_aux: pinmux-aux { 21666b2d6e9SJon Hunter groups = "dpaux-io"; 21766b2d6e9SJon Hunter function = "aux"; 21866b2d6e9SJon Hunter }; 21966b2d6e9SJon Hunter 22066b2d6e9SJon Hunter state_dpaux_i2c: pinmux-i2c { 22166b2d6e9SJon Hunter groups = "dpaux-io"; 22266b2d6e9SJon Hunter function = "i2c"; 22366b2d6e9SJon Hunter }; 22466b2d6e9SJon Hunter 22566b2d6e9SJon Hunter state_dpaux_off: pinmux-off { 22666b2d6e9SJon Hunter groups = "dpaux-io"; 22766b2d6e9SJon Hunter function = "off"; 22866b2d6e9SJon Hunter }; 22966b2d6e9SJon Hunter 23066b2d6e9SJon Hunter i2c-bus { 23166b2d6e9SJon Hunter #address-cells = <1>; 23266b2d6e9SJon Hunter #size-cells = <0>; 23366b2d6e9SJon Hunter }; 234742af7e7SThierry Reding }; 235742af7e7SThierry Reding 236be70771dSThierry Reding isp@54600000 { 237742af7e7SThierry Reding compatible = "nvidia,tegra210-isp"; 238742af7e7SThierry Reding reg = <0x0 0x54600000 0x0 0x00040000>; 239742af7e7SThierry Reding interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 240742af7e7SThierry Reding status = "disabled"; 241742af7e7SThierry Reding }; 242742af7e7SThierry Reding 243be70771dSThierry Reding isp@54680000 { 244742af7e7SThierry Reding compatible = "nvidia,tegra210-isp"; 245742af7e7SThierry Reding reg = <0x0 0x54680000 0x0 0x00040000>; 246742af7e7SThierry Reding interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 247742af7e7SThierry Reding status = "disabled"; 248742af7e7SThierry Reding }; 249742af7e7SThierry Reding 250be70771dSThierry Reding i2c@546c0000 { 251742af7e7SThierry Reding compatible = "nvidia,tegra210-i2c-vi"; 252742af7e7SThierry Reding reg = <0x0 0x546c0000 0x0 0x00040000>; 253742af7e7SThierry Reding interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 254742af7e7SThierry Reding status = "disabled"; 255742af7e7SThierry Reding }; 256742af7e7SThierry Reding }; 257742af7e7SThierry Reding 258be70771dSThierry Reding gic: interrupt-controller@50041000 { 259742af7e7SThierry Reding compatible = "arm,gic-400"; 260742af7e7SThierry Reding #interrupt-cells = <3>; 261742af7e7SThierry Reding interrupt-controller; 262742af7e7SThierry Reding reg = <0x0 0x50041000 0x0 0x1000>, 263742af7e7SThierry Reding <0x0 0x50042000 0x0 0x2000>, 264742af7e7SThierry Reding <0x0 0x50044000 0x0 0x2000>, 265742af7e7SThierry Reding <0x0 0x50046000 0x0 0x2000>; 266742af7e7SThierry Reding interrupts = <GIC_PPI 9 267742af7e7SThierry Reding (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 268742af7e7SThierry Reding interrupt-parent = <&gic>; 269742af7e7SThierry Reding }; 270742af7e7SThierry Reding 271be70771dSThierry Reding gpu@57000000 { 272742af7e7SThierry Reding compatible = "nvidia,gm20b"; 273742af7e7SThierry Reding reg = <0x0 0x57000000 0x0 0x01000000>, 274742af7e7SThierry Reding <0x0 0x58000000 0x0 0x01000000>; 275742af7e7SThierry Reding interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 276742af7e7SThierry Reding <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 277742af7e7SThierry Reding interrupt-names = "stall", "nonstall"; 278742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_GPU>, 2794a0778e9SAlexandre Courbot <&tegra_car TEGRA210_CLK_PLL_P_OUT5>, 2804a0778e9SAlexandre Courbot <&tegra_car TEGRA210_CLK_PLL_G_REF>; 2814a0778e9SAlexandre Courbot clock-names = "gpu", "pwr", "ref"; 282742af7e7SThierry Reding resets = <&tegra_car 184>; 283742af7e7SThierry Reding reset-names = "gpu"; 28430f949bcSAlexandre Courbot 28530f949bcSAlexandre Courbot iommus = <&mc TEGRA_SWGROUP_GPU>; 28630f949bcSAlexandre Courbot 287742af7e7SThierry Reding status = "disabled"; 288742af7e7SThierry Reding }; 289742af7e7SThierry Reding 290be70771dSThierry Reding lic: interrupt-controller@60004000 { 291742af7e7SThierry Reding compatible = "nvidia,tegra210-ictlr"; 292742af7e7SThierry Reding reg = <0x0 0x60004000 0x0 0x40>, /* primary controller */ 293742af7e7SThierry Reding <0x0 0x60004100 0x0 0x40>, /* secondary controller */ 294742af7e7SThierry Reding <0x0 0x60004200 0x0 0x40>, /* tertiary controller */ 295742af7e7SThierry Reding <0x0 0x60004300 0x0 0x40>, /* quaternary controller */ 296742af7e7SThierry Reding <0x0 0x60004400 0x0 0x40>, /* quinary controller */ 297742af7e7SThierry Reding <0x0 0x60004500 0x0 0x40>; /* senary controller */ 298742af7e7SThierry Reding interrupt-controller; 299742af7e7SThierry Reding #interrupt-cells = <3>; 300742af7e7SThierry Reding interrupt-parent = <&gic>; 301742af7e7SThierry Reding }; 302742af7e7SThierry Reding 303be70771dSThierry Reding timer@60005000 { 304742af7e7SThierry Reding compatible = "nvidia,tegra210-timer", "nvidia,tegra20-timer"; 305742af7e7SThierry Reding reg = <0x0 0x60005000 0x0 0x400>; 306742af7e7SThierry Reding interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 307742af7e7SThierry Reding <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 308742af7e7SThierry Reding <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 309742af7e7SThierry Reding <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 310742af7e7SThierry Reding <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 311742af7e7SThierry Reding <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 312742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_TIMER>; 313742af7e7SThierry Reding clock-names = "timer"; 314742af7e7SThierry Reding }; 315742af7e7SThierry Reding 316be70771dSThierry Reding tegra_car: clock@60006000 { 317742af7e7SThierry Reding compatible = "nvidia,tegra210-car"; 318742af7e7SThierry Reding reg = <0x0 0x60006000 0x0 0x1000>; 319742af7e7SThierry Reding #clock-cells = <1>; 320742af7e7SThierry Reding #reset-cells = <1>; 321742af7e7SThierry Reding }; 322742af7e7SThierry Reding 323be70771dSThierry Reding flow-controller@60007000 { 324742af7e7SThierry Reding compatible = "nvidia,tegra210-flowctrl"; 325742af7e7SThierry Reding reg = <0x0 0x60007000 0x0 0x1000>; 326742af7e7SThierry Reding }; 327742af7e7SThierry Reding 328be70771dSThierry Reding gpio: gpio@6000d000 { 329742af7e7SThierry Reding compatible = "nvidia,tegra210-gpio", "nvidia,tegra124-gpio", "nvidia,tegra30-gpio"; 330742af7e7SThierry Reding reg = <0x0 0x6000d000 0x0 0x1000>; 331742af7e7SThierry Reding interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 332742af7e7SThierry Reding <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 333742af7e7SThierry Reding <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 334742af7e7SThierry Reding <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 335742af7e7SThierry Reding <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 336742af7e7SThierry Reding <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 337742af7e7SThierry Reding <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 338742af7e7SThierry Reding <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 339742af7e7SThierry Reding #gpio-cells = <2>; 340742af7e7SThierry Reding gpio-controller; 341742af7e7SThierry Reding #interrupt-cells = <2>; 342742af7e7SThierry Reding interrupt-controller; 343742af7e7SThierry Reding }; 344742af7e7SThierry Reding 345be70771dSThierry Reding apbdma: dma@60020000 { 346742af7e7SThierry Reding compatible = "nvidia,tegra210-apbdma", "nvidia,tegra148-apbdma"; 347742af7e7SThierry Reding reg = <0x0 0x60020000 0x0 0x1400>; 348742af7e7SThierry Reding interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 349742af7e7SThierry Reding <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 350742af7e7SThierry Reding <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 351742af7e7SThierry Reding <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 352742af7e7SThierry Reding <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 353742af7e7SThierry Reding <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 354742af7e7SThierry Reding <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 355742af7e7SThierry Reding <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 356742af7e7SThierry Reding <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 357742af7e7SThierry Reding <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 358742af7e7SThierry Reding <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 359742af7e7SThierry Reding <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 360742af7e7SThierry Reding <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 361742af7e7SThierry Reding <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 362742af7e7SThierry Reding <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 363742af7e7SThierry Reding <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 364742af7e7SThierry Reding <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 365742af7e7SThierry Reding <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 366742af7e7SThierry Reding <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 367742af7e7SThierry Reding <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 368742af7e7SThierry Reding <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 369742af7e7SThierry Reding <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 370742af7e7SThierry Reding <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 371742af7e7SThierry Reding <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 372742af7e7SThierry Reding <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 373742af7e7SThierry Reding <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 374742af7e7SThierry Reding <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 375742af7e7SThierry Reding <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 376742af7e7SThierry Reding <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 377742af7e7SThierry Reding <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 378742af7e7SThierry Reding <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 379742af7e7SThierry Reding <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 380742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_APBDMA>; 381742af7e7SThierry Reding clock-names = "dma"; 382742af7e7SThierry Reding resets = <&tegra_car 34>; 383742af7e7SThierry Reding reset-names = "dma"; 384742af7e7SThierry Reding #dma-cells = <1>; 385742af7e7SThierry Reding }; 386742af7e7SThierry Reding 387be70771dSThierry Reding apbmisc@70000800 { 388742af7e7SThierry Reding compatible = "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc"; 389742af7e7SThierry Reding reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */ 390742af7e7SThierry Reding <0x0 0x7000e864 0x0 0x04>; /* Strapping options */ 391742af7e7SThierry Reding }; 392742af7e7SThierry Reding 393be70771dSThierry Reding pinmux: pinmux@700008d4 { 394742af7e7SThierry Reding compatible = "nvidia,tegra210-pinmux"; 395742af7e7SThierry Reding reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */ 396742af7e7SThierry Reding <0x0 0x70003000 0x0 0x294>; /* Mux registers */ 397742af7e7SThierry Reding }; 398742af7e7SThierry Reding 399742af7e7SThierry Reding /* 400742af7e7SThierry Reding * There are two serial driver i.e. 8250 based simple serial 401742af7e7SThierry Reding * driver and APB DMA based serial driver for higher baudrate 402ef769e32SAdam Buchbinder * and performance. To enable the 8250 based driver, the compatible 403742af7e7SThierry Reding * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable 40468cd8b2eSThierry Reding * the APB DMA based serial driver, the compatible is 405742af7e7SThierry Reding * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". 406742af7e7SThierry Reding */ 407be70771dSThierry Reding uarta: serial@70006000 { 408742af7e7SThierry Reding compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 409742af7e7SThierry Reding reg = <0x0 0x70006000 0x0 0x40>; 410742af7e7SThierry Reding reg-shift = <2>; 411742af7e7SThierry Reding interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 412742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_UARTA>; 413742af7e7SThierry Reding clock-names = "serial"; 414742af7e7SThierry Reding resets = <&tegra_car 6>; 415742af7e7SThierry Reding reset-names = "serial"; 416742af7e7SThierry Reding dmas = <&apbdma 8>, <&apbdma 8>; 417742af7e7SThierry Reding dma-names = "rx", "tx"; 418742af7e7SThierry Reding status = "disabled"; 419742af7e7SThierry Reding }; 420742af7e7SThierry Reding 421be70771dSThierry Reding uartb: serial@70006040 { 422742af7e7SThierry Reding compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 423742af7e7SThierry Reding reg = <0x0 0x70006040 0x0 0x40>; 424742af7e7SThierry Reding reg-shift = <2>; 425742af7e7SThierry Reding interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 426742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_UARTB>; 427742af7e7SThierry Reding clock-names = "serial"; 428742af7e7SThierry Reding resets = <&tegra_car 7>; 429742af7e7SThierry Reding reset-names = "serial"; 430742af7e7SThierry Reding dmas = <&apbdma 9>, <&apbdma 9>; 431742af7e7SThierry Reding dma-names = "rx", "tx"; 432742af7e7SThierry Reding status = "disabled"; 433742af7e7SThierry Reding }; 434742af7e7SThierry Reding 435be70771dSThierry Reding uartc: serial@70006200 { 436742af7e7SThierry Reding compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 437742af7e7SThierry Reding reg = <0x0 0x70006200 0x0 0x40>; 438742af7e7SThierry Reding reg-shift = <2>; 439742af7e7SThierry Reding interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 440742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_UARTC>; 441742af7e7SThierry Reding clock-names = "serial"; 442742af7e7SThierry Reding resets = <&tegra_car 55>; 443742af7e7SThierry Reding reset-names = "serial"; 444742af7e7SThierry Reding dmas = <&apbdma 10>, <&apbdma 10>; 445742af7e7SThierry Reding dma-names = "rx", "tx"; 446742af7e7SThierry Reding status = "disabled"; 447742af7e7SThierry Reding }; 448742af7e7SThierry Reding 449be70771dSThierry Reding uartd: serial@70006300 { 450742af7e7SThierry Reding compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 451742af7e7SThierry Reding reg = <0x0 0x70006300 0x0 0x40>; 452742af7e7SThierry Reding reg-shift = <2>; 453742af7e7SThierry Reding interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 454742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_UARTD>; 455742af7e7SThierry Reding clock-names = "serial"; 456742af7e7SThierry Reding resets = <&tegra_car 65>; 457742af7e7SThierry Reding reset-names = "serial"; 458742af7e7SThierry Reding dmas = <&apbdma 19>, <&apbdma 19>; 459742af7e7SThierry Reding dma-names = "rx", "tx"; 460742af7e7SThierry Reding status = "disabled"; 461742af7e7SThierry Reding }; 462742af7e7SThierry Reding 463be70771dSThierry Reding pwm: pwm@7000a000 { 464742af7e7SThierry Reding compatible = "nvidia,tegra210-pwm", "nvidia,tegra20-pwm"; 465742af7e7SThierry Reding reg = <0x0 0x7000a000 0x0 0x100>; 466742af7e7SThierry Reding #pwm-cells = <2>; 467742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_PWM>; 468742af7e7SThierry Reding clock-names = "pwm"; 469742af7e7SThierry Reding resets = <&tegra_car 17>; 470742af7e7SThierry Reding reset-names = "pwm"; 471742af7e7SThierry Reding status = "disabled"; 472742af7e7SThierry Reding }; 473742af7e7SThierry Reding 474be70771dSThierry Reding i2c@7000c000 { 475742af7e7SThierry Reding compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 476742af7e7SThierry Reding reg = <0x0 0x7000c000 0x0 0x100>; 477742af7e7SThierry Reding interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 478742af7e7SThierry Reding #address-cells = <1>; 479742af7e7SThierry Reding #size-cells = <0>; 480742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_I2C1>; 481742af7e7SThierry Reding clock-names = "div-clk"; 482742af7e7SThierry Reding resets = <&tegra_car 12>; 483742af7e7SThierry Reding reset-names = "i2c"; 484742af7e7SThierry Reding dmas = <&apbdma 21>, <&apbdma 21>; 485742af7e7SThierry Reding dma-names = "rx", "tx"; 486742af7e7SThierry Reding status = "disabled"; 487742af7e7SThierry Reding }; 488742af7e7SThierry Reding 489be70771dSThierry Reding i2c@7000c400 { 490742af7e7SThierry Reding compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 491742af7e7SThierry Reding reg = <0x0 0x7000c400 0x0 0x100>; 492742af7e7SThierry Reding interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 493742af7e7SThierry Reding #address-cells = <1>; 494742af7e7SThierry Reding #size-cells = <0>; 495742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_I2C2>; 496742af7e7SThierry Reding clock-names = "div-clk"; 497742af7e7SThierry Reding resets = <&tegra_car 54>; 498742af7e7SThierry Reding reset-names = "i2c"; 499742af7e7SThierry Reding dmas = <&apbdma 22>, <&apbdma 22>; 500742af7e7SThierry Reding dma-names = "rx", "tx"; 501742af7e7SThierry Reding status = "disabled"; 502742af7e7SThierry Reding }; 503742af7e7SThierry Reding 504be70771dSThierry Reding i2c@7000c500 { 505742af7e7SThierry Reding compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 506742af7e7SThierry Reding reg = <0x0 0x7000c500 0x0 0x100>; 507742af7e7SThierry Reding interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 508742af7e7SThierry Reding #address-cells = <1>; 509742af7e7SThierry Reding #size-cells = <0>; 510742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_I2C3>; 511742af7e7SThierry Reding clock-names = "div-clk"; 512742af7e7SThierry Reding resets = <&tegra_car 67>; 513742af7e7SThierry Reding reset-names = "i2c"; 514742af7e7SThierry Reding dmas = <&apbdma 23>, <&apbdma 23>; 515742af7e7SThierry Reding dma-names = "rx", "tx"; 516742af7e7SThierry Reding status = "disabled"; 517742af7e7SThierry Reding }; 518742af7e7SThierry Reding 519be70771dSThierry Reding i2c@7000c700 { 520742af7e7SThierry Reding compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 521742af7e7SThierry Reding reg = <0x0 0x7000c700 0x0 0x100>; 522742af7e7SThierry Reding interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 523742af7e7SThierry Reding #address-cells = <1>; 524742af7e7SThierry Reding #size-cells = <0>; 525742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_I2C4>; 526742af7e7SThierry Reding clock-names = "div-clk"; 527742af7e7SThierry Reding resets = <&tegra_car 103>; 528742af7e7SThierry Reding reset-names = "i2c"; 529742af7e7SThierry Reding dmas = <&apbdma 26>, <&apbdma 26>; 530742af7e7SThierry Reding dma-names = "rx", "tx"; 53166b2d6e9SJon Hunter pinctrl-0 = <&state_dpaux1_i2c>; 53266b2d6e9SJon Hunter pinctrl-1 = <&state_dpaux1_off>; 53366b2d6e9SJon Hunter pinctrl-names = "default", "idle"; 534742af7e7SThierry Reding status = "disabled"; 535742af7e7SThierry Reding }; 536742af7e7SThierry Reding 537be70771dSThierry Reding i2c@7000d000 { 538742af7e7SThierry Reding compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 539742af7e7SThierry Reding reg = <0x0 0x7000d000 0x0 0x100>; 540742af7e7SThierry Reding interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 541742af7e7SThierry Reding #address-cells = <1>; 542742af7e7SThierry Reding #size-cells = <0>; 543742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_I2C5>; 544742af7e7SThierry Reding clock-names = "div-clk"; 545742af7e7SThierry Reding resets = <&tegra_car 47>; 546742af7e7SThierry Reding reset-names = "i2c"; 547742af7e7SThierry Reding dmas = <&apbdma 24>, <&apbdma 24>; 548742af7e7SThierry Reding dma-names = "rx", "tx"; 549742af7e7SThierry Reding status = "disabled"; 550742af7e7SThierry Reding }; 551742af7e7SThierry Reding 552be70771dSThierry Reding i2c@7000d100 { 553742af7e7SThierry Reding compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 554742af7e7SThierry Reding reg = <0x0 0x7000d100 0x0 0x100>; 555742af7e7SThierry Reding interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 556742af7e7SThierry Reding #address-cells = <1>; 557742af7e7SThierry Reding #size-cells = <0>; 558742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_I2C6>; 559742af7e7SThierry Reding clock-names = "div-clk"; 560742af7e7SThierry Reding resets = <&tegra_car 166>; 561742af7e7SThierry Reding reset-names = "i2c"; 562742af7e7SThierry Reding dmas = <&apbdma 30>, <&apbdma 30>; 563742af7e7SThierry Reding dma-names = "rx", "tx"; 56466b2d6e9SJon Hunter pinctrl-0 = <&state_dpaux_i2c>; 56566b2d6e9SJon Hunter pinctrl-1 = <&state_dpaux_off>; 56666b2d6e9SJon Hunter pinctrl-names = "default", "idle"; 567742af7e7SThierry Reding status = "disabled"; 568742af7e7SThierry Reding }; 569742af7e7SThierry Reding 570be70771dSThierry Reding spi@7000d400 { 571742af7e7SThierry Reding compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 572742af7e7SThierry Reding reg = <0x0 0x7000d400 0x0 0x200>; 573742af7e7SThierry Reding interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 574742af7e7SThierry Reding #address-cells = <1>; 575742af7e7SThierry Reding #size-cells = <0>; 576742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_SBC1>; 577742af7e7SThierry Reding clock-names = "spi"; 578742af7e7SThierry Reding resets = <&tegra_car 41>; 579742af7e7SThierry Reding reset-names = "spi"; 580742af7e7SThierry Reding dmas = <&apbdma 15>, <&apbdma 15>; 581742af7e7SThierry Reding dma-names = "rx", "tx"; 582742af7e7SThierry Reding status = "disabled"; 583742af7e7SThierry Reding }; 584742af7e7SThierry Reding 585be70771dSThierry Reding spi@7000d600 { 586742af7e7SThierry Reding compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 587742af7e7SThierry Reding reg = <0x0 0x7000d600 0x0 0x200>; 588742af7e7SThierry Reding interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 589742af7e7SThierry Reding #address-cells = <1>; 590742af7e7SThierry Reding #size-cells = <0>; 591742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_SBC2>; 592742af7e7SThierry Reding clock-names = "spi"; 593742af7e7SThierry Reding resets = <&tegra_car 44>; 594742af7e7SThierry Reding reset-names = "spi"; 595742af7e7SThierry Reding dmas = <&apbdma 16>, <&apbdma 16>; 596742af7e7SThierry Reding dma-names = "rx", "tx"; 597742af7e7SThierry Reding status = "disabled"; 598742af7e7SThierry Reding }; 599742af7e7SThierry Reding 600be70771dSThierry Reding spi@7000d800 { 601742af7e7SThierry Reding compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 602742af7e7SThierry Reding reg = <0x0 0x7000d800 0x0 0x200>; 603742af7e7SThierry Reding interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 604742af7e7SThierry Reding #address-cells = <1>; 605742af7e7SThierry Reding #size-cells = <0>; 606742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_SBC3>; 607742af7e7SThierry Reding clock-names = "spi"; 608742af7e7SThierry Reding resets = <&tegra_car 46>; 609742af7e7SThierry Reding reset-names = "spi"; 610742af7e7SThierry Reding dmas = <&apbdma 17>, <&apbdma 17>; 611742af7e7SThierry Reding dma-names = "rx", "tx"; 612742af7e7SThierry Reding status = "disabled"; 613742af7e7SThierry Reding }; 614742af7e7SThierry Reding 615be70771dSThierry Reding spi@7000da00 { 616742af7e7SThierry Reding compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 617742af7e7SThierry Reding reg = <0x0 0x7000da00 0x0 0x200>; 618742af7e7SThierry Reding interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 619742af7e7SThierry Reding #address-cells = <1>; 620742af7e7SThierry Reding #size-cells = <0>; 621742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_SBC4>; 622742af7e7SThierry Reding clock-names = "spi"; 623742af7e7SThierry Reding resets = <&tegra_car 68>; 624742af7e7SThierry Reding reset-names = "spi"; 625742af7e7SThierry Reding dmas = <&apbdma 18>, <&apbdma 18>; 626742af7e7SThierry Reding dma-names = "rx", "tx"; 627742af7e7SThierry Reding status = "disabled"; 628742af7e7SThierry Reding }; 629742af7e7SThierry Reding 630be70771dSThierry Reding rtc@7000e000 { 631742af7e7SThierry Reding compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc"; 632742af7e7SThierry Reding reg = <0x0 0x7000e000 0x0 0x100>; 633742af7e7SThierry Reding interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 634742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_RTC>; 635742af7e7SThierry Reding clock-names = "rtc"; 636742af7e7SThierry Reding }; 637742af7e7SThierry Reding 638be70771dSThierry Reding pmc: pmc@7000e400 { 639742af7e7SThierry Reding compatible = "nvidia,tegra210-pmc"; 640742af7e7SThierry Reding reg = <0x0 0x7000e400 0x0 0x400>; 641742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; 642742af7e7SThierry Reding clock-names = "pclk", "clk32k_in"; 643c2b82445SJon Hunter 644c2b82445SJon Hunter powergates { 645c2b82445SJon Hunter pd_audio: aud { 646c2b82445SJon Hunter clocks = <&tegra_car TEGRA210_CLK_APE>, 647c2b82445SJon Hunter <&tegra_car TEGRA210_CLK_APB2APE>; 648c2b82445SJon Hunter resets = <&tegra_car 198>; 649c2b82445SJon Hunter #power-domain-cells = <0>; 650c2b82445SJon Hunter }; 651241f02baSJon Hunter 652241f02baSJon Hunter pd_xusbss: xusba { 653241f02baSJon Hunter clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>; 654241f02baSJon Hunter clock-names = "xusb-ss"; 655241f02baSJon Hunter resets = <&tegra_car TEGRA210_CLK_XUSB_SS>; 656241f02baSJon Hunter reset-names = "xusb-ss"; 657241f02baSJon Hunter #power-domain-cells = <0>; 658241f02baSJon Hunter }; 659241f02baSJon Hunter 660241f02baSJon Hunter pd_xusbdev: xusbb { 661241f02baSJon Hunter clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>; 662241f02baSJon Hunter clock-names = "xusb-dev"; 663241f02baSJon Hunter resets = <&tegra_car 95>; 664241f02baSJon Hunter reset-names = "xusb-dev"; 665241f02baSJon Hunter #power-domain-cells = <0>; 666241f02baSJon Hunter }; 667241f02baSJon Hunter 668241f02baSJon Hunter pd_xusbhost: xusbc { 669241f02baSJon Hunter clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>; 670241f02baSJon Hunter clock-names = "xusb-host"; 671241f02baSJon Hunter resets = <&tegra_car TEGRA210_CLK_XUSB_HOST>; 672241f02baSJon Hunter reset-names = "xusb-host"; 673241f02baSJon Hunter #power-domain-cells = <0>; 674241f02baSJon Hunter }; 675c2b82445SJon Hunter }; 676742af7e7SThierry Reding }; 677742af7e7SThierry Reding 678be70771dSThierry Reding fuse@7000f800 { 679742af7e7SThierry Reding compatible = "nvidia,tegra210-efuse"; 680742af7e7SThierry Reding reg = <0x0 0x7000f800 0x0 0x400>; 681742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_FUSE>; 682742af7e7SThierry Reding clock-names = "fuse"; 683742af7e7SThierry Reding resets = <&tegra_car 39>; 684742af7e7SThierry Reding reset-names = "fuse"; 685742af7e7SThierry Reding }; 686742af7e7SThierry Reding 687be70771dSThierry Reding mc: memory-controller@70019000 { 688742af7e7SThierry Reding compatible = "nvidia,tegra210-mc"; 689742af7e7SThierry Reding reg = <0x0 0x70019000 0x0 0x1000>; 690742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_MC>; 691742af7e7SThierry Reding clock-names = "mc"; 692742af7e7SThierry Reding 693742af7e7SThierry Reding interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 694742af7e7SThierry Reding 695742af7e7SThierry Reding #iommu-cells = <1>; 696742af7e7SThierry Reding }; 697742af7e7SThierry Reding 698be70771dSThierry Reding hda@70030000 { 699742af7e7SThierry Reding compatible = "nvidia,tegra210-hda", "nvidia,tegra30-hda"; 700742af7e7SThierry Reding reg = <0x0 0x70030000 0x0 0x10000>; 701742af7e7SThierry Reding interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 702742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_HDA>, 703742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_HDA2HDMI>, 704742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_HDA2CODEC_2X>; 705742af7e7SThierry Reding clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 706742af7e7SThierry Reding resets = <&tegra_car 125>, /* hda */ 707742af7e7SThierry Reding <&tegra_car 128>, /* hda2hdmi */ 708742af7e7SThierry Reding <&tegra_car 111>; /* hda2codec_2x */ 709742af7e7SThierry Reding reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 710742af7e7SThierry Reding status = "disabled"; 711742af7e7SThierry Reding }; 712742af7e7SThierry Reding 713e7a99ac2SThierry Reding usb@70090000 { 714e7a99ac2SThierry Reding compatible = "nvidia,tegra210-xusb"; 715e7a99ac2SThierry Reding reg = <0x0 0x70090000 0x0 0x8000>, 716e7a99ac2SThierry Reding <0x0 0x70098000 0x0 0x1000>, 717e7a99ac2SThierry Reding <0x0 0x70099000 0x0 0x1000>; 718e7a99ac2SThierry Reding reg-names = "hcd", "fpci", "ipfs"; 719e7a99ac2SThierry Reding 720e7a99ac2SThierry Reding interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 7219168e1dbSJon Hunter <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 722e7a99ac2SThierry Reding 723e7a99ac2SThierry Reding clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>, 724e7a99ac2SThierry Reding <&tegra_car TEGRA210_CLK_XUSB_HOST_SRC>, 725e7a99ac2SThierry Reding <&tegra_car TEGRA210_CLK_XUSB_FALCON_SRC>, 726e7a99ac2SThierry Reding <&tegra_car TEGRA210_CLK_XUSB_SS>, 727e7a99ac2SThierry Reding <&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>, 728e7a99ac2SThierry Reding <&tegra_car TEGRA210_CLK_XUSB_SS_SRC>, 729e7a99ac2SThierry Reding <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>, 730e7a99ac2SThierry Reding <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>, 731e7a99ac2SThierry Reding <&tegra_car TEGRA210_CLK_PLL_U_480M>, 732e7a99ac2SThierry Reding <&tegra_car TEGRA210_CLK_CLK_M>, 733e7a99ac2SThierry Reding <&tegra_car TEGRA210_CLK_PLL_E>; 734e7a99ac2SThierry Reding clock-names = "xusb_host", "xusb_host_src", 735e7a99ac2SThierry Reding "xusb_falcon_src", "xusb_ss", 736e7a99ac2SThierry Reding "xusb_ss_div2", "xusb_ss_src", 737e7a99ac2SThierry Reding "xusb_hs_src", "xusb_fs_src", 738e7a99ac2SThierry Reding "pll_u_480m", "clk_m", "pll_e"; 739e7a99ac2SThierry Reding resets = <&tegra_car 89>, <&tegra_car 156>, 740e7a99ac2SThierry Reding <&tegra_car 143>; 741e7a99ac2SThierry Reding reset-names = "xusb_host", "xusb_ss", "xusb_src"; 742e7a99ac2SThierry Reding 743e7a99ac2SThierry Reding nvidia,xusb-padctl = <&padctl>; 744e7a99ac2SThierry Reding 745e7a99ac2SThierry Reding status = "disabled"; 746e7a99ac2SThierry Reding }; 747e7a99ac2SThierry Reding 7484e07ac90SThierry Reding padctl: padctl@7009f000 { 7494e07ac90SThierry Reding compatible = "nvidia,tegra210-xusb-padctl"; 7504e07ac90SThierry Reding reg = <0x0 0x7009f000 0x0 0x1000>; 7514e07ac90SThierry Reding resets = <&tegra_car 142>; 7524e07ac90SThierry Reding reset-names = "padctl"; 7534e07ac90SThierry Reding 7544e07ac90SThierry Reding status = "disabled"; 7554e07ac90SThierry Reding 7564e07ac90SThierry Reding pads { 7574e07ac90SThierry Reding usb2 { 7584e07ac90SThierry Reding clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>; 7594e07ac90SThierry Reding clock-names = "trk"; 7604e07ac90SThierry Reding status = "disabled"; 7614e07ac90SThierry Reding 7624e07ac90SThierry Reding lanes { 7634e07ac90SThierry Reding usb2-0 { 7644e07ac90SThierry Reding status = "disabled"; 7654e07ac90SThierry Reding #phy-cells = <0>; 7664e07ac90SThierry Reding }; 7674e07ac90SThierry Reding 7684e07ac90SThierry Reding usb2-1 { 7694e07ac90SThierry Reding status = "disabled"; 7704e07ac90SThierry Reding #phy-cells = <0>; 7714e07ac90SThierry Reding }; 7724e07ac90SThierry Reding 7734e07ac90SThierry Reding usb2-2 { 7744e07ac90SThierry Reding status = "disabled"; 7754e07ac90SThierry Reding #phy-cells = <0>; 7764e07ac90SThierry Reding }; 7774e07ac90SThierry Reding 7784e07ac90SThierry Reding usb2-3 { 7794e07ac90SThierry Reding status = "disabled"; 7804e07ac90SThierry Reding #phy-cells = <0>; 7814e07ac90SThierry Reding }; 7824e07ac90SThierry Reding }; 7834e07ac90SThierry Reding }; 7844e07ac90SThierry Reding 7854e07ac90SThierry Reding hsic { 7864e07ac90SThierry Reding clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>; 7874e07ac90SThierry Reding clock-names = "trk"; 7884e07ac90SThierry Reding status = "disabled"; 7894e07ac90SThierry Reding 7904e07ac90SThierry Reding lanes { 7914e07ac90SThierry Reding hsic-0 { 7924e07ac90SThierry Reding status = "disabled"; 7934e07ac90SThierry Reding #phy-cells = <0>; 7944e07ac90SThierry Reding }; 7954e07ac90SThierry Reding 7964e07ac90SThierry Reding hsic-1 { 7974e07ac90SThierry Reding status = "disabled"; 7984e07ac90SThierry Reding #phy-cells = <0>; 7994e07ac90SThierry Reding }; 8004e07ac90SThierry Reding }; 8014e07ac90SThierry Reding }; 8024e07ac90SThierry Reding 8034e07ac90SThierry Reding pcie { 8044e07ac90SThierry Reding clocks = <&tegra_car TEGRA210_CLK_PLL_E>; 8054e07ac90SThierry Reding clock-names = "pll"; 8064e07ac90SThierry Reding resets = <&tegra_car 205>; 8074e07ac90SThierry Reding reset-names = "phy"; 8084e07ac90SThierry Reding status = "disabled"; 8094e07ac90SThierry Reding 8104e07ac90SThierry Reding lanes { 8114e07ac90SThierry Reding pcie-0 { 8124e07ac90SThierry Reding status = "disabled"; 8134e07ac90SThierry Reding #phy-cells = <0>; 8144e07ac90SThierry Reding }; 8154e07ac90SThierry Reding 8164e07ac90SThierry Reding pcie-1 { 8174e07ac90SThierry Reding status = "disabled"; 8184e07ac90SThierry Reding #phy-cells = <0>; 8194e07ac90SThierry Reding }; 8204e07ac90SThierry Reding 8214e07ac90SThierry Reding pcie-2 { 8224e07ac90SThierry Reding status = "disabled"; 8234e07ac90SThierry Reding #phy-cells = <0>; 8244e07ac90SThierry Reding }; 8254e07ac90SThierry Reding 8264e07ac90SThierry Reding pcie-3 { 8274e07ac90SThierry Reding status = "disabled"; 8284e07ac90SThierry Reding #phy-cells = <0>; 8294e07ac90SThierry Reding }; 8304e07ac90SThierry Reding 8314e07ac90SThierry Reding pcie-4 { 8324e07ac90SThierry Reding status = "disabled"; 8334e07ac90SThierry Reding #phy-cells = <0>; 8344e07ac90SThierry Reding }; 8354e07ac90SThierry Reding 8364e07ac90SThierry Reding pcie-5 { 8374e07ac90SThierry Reding status = "disabled"; 8384e07ac90SThierry Reding #phy-cells = <0>; 8394e07ac90SThierry Reding }; 8404e07ac90SThierry Reding 8414e07ac90SThierry Reding pcie-6 { 8424e07ac90SThierry Reding status = "disabled"; 8434e07ac90SThierry Reding #phy-cells = <0>; 8444e07ac90SThierry Reding }; 8454e07ac90SThierry Reding }; 8464e07ac90SThierry Reding }; 8474e07ac90SThierry Reding 8484e07ac90SThierry Reding sata { 8494e07ac90SThierry Reding clocks = <&tegra_car TEGRA210_CLK_PLL_E>; 8504e07ac90SThierry Reding clock-names = "pll"; 8514e07ac90SThierry Reding resets = <&tegra_car 204>; 8524e07ac90SThierry Reding reset-names = "phy"; 8534e07ac90SThierry Reding status = "disabled"; 8544e07ac90SThierry Reding 8554e07ac90SThierry Reding lanes { 8564e07ac90SThierry Reding sata-0 { 8574e07ac90SThierry Reding status = "disabled"; 8584e07ac90SThierry Reding #phy-cells = <0>; 8594e07ac90SThierry Reding }; 8604e07ac90SThierry Reding }; 8614e07ac90SThierry Reding }; 8624e07ac90SThierry Reding }; 8634e07ac90SThierry Reding 8644e07ac90SThierry Reding ports { 8654e07ac90SThierry Reding usb2-0 { 8664e07ac90SThierry Reding status = "disabled"; 8674e07ac90SThierry Reding }; 8684e07ac90SThierry Reding 8694e07ac90SThierry Reding usb2-1 { 8704e07ac90SThierry Reding status = "disabled"; 8714e07ac90SThierry Reding }; 8724e07ac90SThierry Reding 8734e07ac90SThierry Reding usb2-2 { 8744e07ac90SThierry Reding status = "disabled"; 8754e07ac90SThierry Reding }; 8764e07ac90SThierry Reding 8774e07ac90SThierry Reding usb2-3 { 8784e07ac90SThierry Reding status = "disabled"; 8794e07ac90SThierry Reding }; 8804e07ac90SThierry Reding 8814e07ac90SThierry Reding hsic-0 { 8824e07ac90SThierry Reding status = "disabled"; 8834e07ac90SThierry Reding }; 8844e07ac90SThierry Reding 8854e07ac90SThierry Reding usb3-0 { 8864e07ac90SThierry Reding status = "disabled"; 8874e07ac90SThierry Reding }; 8884e07ac90SThierry Reding 8894e07ac90SThierry Reding usb3-1 { 8904e07ac90SThierry Reding status = "disabled"; 8914e07ac90SThierry Reding }; 8924e07ac90SThierry Reding 8934e07ac90SThierry Reding usb3-2 { 8944e07ac90SThierry Reding status = "disabled"; 8954e07ac90SThierry Reding }; 8964e07ac90SThierry Reding 8974e07ac90SThierry Reding usb3-3 { 8984e07ac90SThierry Reding status = "disabled"; 8994e07ac90SThierry Reding }; 9004e07ac90SThierry Reding }; 9014e07ac90SThierry Reding }; 9024e07ac90SThierry Reding 903be70771dSThierry Reding sdhci@700b0000 { 904742af7e7SThierry Reding compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; 905742af7e7SThierry Reding reg = <0x0 0x700b0000 0x0 0x200>; 906742af7e7SThierry Reding interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 907742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_SDMMC1>; 908742af7e7SThierry Reding clock-names = "sdhci"; 909742af7e7SThierry Reding resets = <&tegra_car 14>; 910742af7e7SThierry Reding reset-names = "sdhci"; 911742af7e7SThierry Reding status = "disabled"; 912742af7e7SThierry Reding }; 913742af7e7SThierry Reding 914be70771dSThierry Reding sdhci@700b0200 { 915742af7e7SThierry Reding compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; 916742af7e7SThierry Reding reg = <0x0 0x700b0200 0x0 0x200>; 917742af7e7SThierry Reding interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 918742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_SDMMC2>; 919742af7e7SThierry Reding clock-names = "sdhci"; 920742af7e7SThierry Reding resets = <&tegra_car 9>; 921742af7e7SThierry Reding reset-names = "sdhci"; 922742af7e7SThierry Reding status = "disabled"; 923742af7e7SThierry Reding }; 924742af7e7SThierry Reding 925be70771dSThierry Reding sdhci@700b0400 { 926742af7e7SThierry Reding compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; 927742af7e7SThierry Reding reg = <0x0 0x700b0400 0x0 0x200>; 928742af7e7SThierry Reding interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 929742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_SDMMC3>; 930742af7e7SThierry Reding clock-names = "sdhci"; 931742af7e7SThierry Reding resets = <&tegra_car 69>; 932742af7e7SThierry Reding reset-names = "sdhci"; 933742af7e7SThierry Reding status = "disabled"; 934742af7e7SThierry Reding }; 935742af7e7SThierry Reding 936be70771dSThierry Reding sdhci@700b0600 { 937742af7e7SThierry Reding compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; 938742af7e7SThierry Reding reg = <0x0 0x700b0600 0x0 0x200>; 939742af7e7SThierry Reding interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 940742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_SDMMC4>; 941742af7e7SThierry Reding clock-names = "sdhci"; 942742af7e7SThierry Reding resets = <&tegra_car 15>; 943742af7e7SThierry Reding reset-names = "sdhci"; 944742af7e7SThierry Reding status = "disabled"; 945742af7e7SThierry Reding }; 946742af7e7SThierry Reding 947be70771dSThierry Reding mipi: mipi@700e3000 { 948742af7e7SThierry Reding compatible = "nvidia,tegra210-mipi"; 949742af7e7SThierry Reding reg = <0x0 0x700e3000 0x0 0x100>; 950742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_MIPI_CAL>; 951742af7e7SThierry Reding clock-names = "mipi-cal"; 952742af7e7SThierry Reding #nvidia,mipi-calibrate-cells = <1>; 953742af7e7SThierry Reding }; 954742af7e7SThierry Reding 9550f133090SJon Hunter aconnect@702c0000 { 9560f133090SJon Hunter compatible = "nvidia,tegra210-aconnect"; 9570f133090SJon Hunter clocks = <&tegra_car TEGRA210_CLK_APE>, 9580f133090SJon Hunter <&tegra_car TEGRA210_CLK_APB2APE>; 9590f133090SJon Hunter clock-names = "ape", "apb2ape"; 9600f133090SJon Hunter power-domains = <&pd_audio>; 9610f133090SJon Hunter #address-cells = <1>; 9620f133090SJon Hunter #size-cells = <1>; 9630f133090SJon Hunter ranges = <0x702c0000 0x0 0x702c0000 0x00040000>; 9640f133090SJon Hunter status = "disabled"; 9650f133090SJon Hunter }; 9660f133090SJon Hunter 967be70771dSThierry Reding spi@70410000 { 968742af7e7SThierry Reding compatible = "nvidia,tegra210-qspi"; 969742af7e7SThierry Reding reg = <0x0 0x70410000 0x0 0x1000>; 970742af7e7SThierry Reding interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 971742af7e7SThierry Reding #address-cells = <1>; 972742af7e7SThierry Reding #size-cells = <0>; 973742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_QSPI>; 974742af7e7SThierry Reding clock-names = "qspi"; 975742af7e7SThierry Reding resets = <&tegra_car 211>; 976742af7e7SThierry Reding reset-names = "qspi"; 977742af7e7SThierry Reding dmas = <&apbdma 5>, <&apbdma 5>; 978742af7e7SThierry Reding dma-names = "rx", "tx"; 979742af7e7SThierry Reding status = "disabled"; 980742af7e7SThierry Reding }; 981742af7e7SThierry Reding 982be70771dSThierry Reding usb@7d000000 { 983742af7e7SThierry Reding compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 984742af7e7SThierry Reding reg = <0x0 0x7d000000 0x0 0x4000>; 985742af7e7SThierry Reding interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 986742af7e7SThierry Reding phy_type = "utmi"; 987742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_USBD>; 988742af7e7SThierry Reding clock-names = "usb"; 989742af7e7SThierry Reding resets = <&tegra_car 22>; 990742af7e7SThierry Reding reset-names = "usb"; 991742af7e7SThierry Reding nvidia,phy = <&phy1>; 992742af7e7SThierry Reding status = "disabled"; 993742af7e7SThierry Reding }; 994742af7e7SThierry Reding 995be70771dSThierry Reding phy1: usb-phy@7d000000 { 996742af7e7SThierry Reding compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; 997742af7e7SThierry Reding reg = <0x0 0x7d000000 0x0 0x4000>, 998742af7e7SThierry Reding <0x0 0x7d000000 0x0 0x4000>; 999742af7e7SThierry Reding phy_type = "utmi"; 1000742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_USBD>, 1001742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_PLL_U>, 1002742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_USBD>; 1003742af7e7SThierry Reding clock-names = "reg", "pll_u", "utmi-pads"; 1004742af7e7SThierry Reding resets = <&tegra_car 22>, <&tegra_car 22>; 1005742af7e7SThierry Reding reset-names = "usb", "utmi-pads"; 1006742af7e7SThierry Reding nvidia,hssync-start-delay = <0>; 1007742af7e7SThierry Reding nvidia,idle-wait-delay = <17>; 1008742af7e7SThierry Reding nvidia,elastic-limit = <16>; 1009742af7e7SThierry Reding nvidia,term-range-adj = <6>; 1010742af7e7SThierry Reding nvidia,xcvr-setup = <9>; 1011742af7e7SThierry Reding nvidia,xcvr-lsfslew = <0>; 1012742af7e7SThierry Reding nvidia,xcvr-lsrslew = <3>; 1013742af7e7SThierry Reding nvidia,hssquelch-level = <2>; 1014742af7e7SThierry Reding nvidia,hsdiscon-level = <5>; 1015742af7e7SThierry Reding nvidia,xcvr-hsslew = <12>; 1016742af7e7SThierry Reding nvidia,has-utmi-pad-registers; 1017742af7e7SThierry Reding status = "disabled"; 1018742af7e7SThierry Reding }; 1019742af7e7SThierry Reding 1020be70771dSThierry Reding usb@7d004000 { 1021742af7e7SThierry Reding compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 1022742af7e7SThierry Reding reg = <0x0 0x7d004000 0x0 0x4000>; 1023742af7e7SThierry Reding interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1024742af7e7SThierry Reding phy_type = "utmi"; 1025742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_USB2>; 1026742af7e7SThierry Reding clock-names = "usb"; 1027742af7e7SThierry Reding resets = <&tegra_car 58>; 1028742af7e7SThierry Reding reset-names = "usb"; 1029742af7e7SThierry Reding nvidia,phy = <&phy2>; 1030742af7e7SThierry Reding status = "disabled"; 1031742af7e7SThierry Reding }; 1032742af7e7SThierry Reding 1033be70771dSThierry Reding phy2: usb-phy@7d004000 { 1034742af7e7SThierry Reding compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; 1035742af7e7SThierry Reding reg = <0x0 0x7d004000 0x0 0x4000>, 1036742af7e7SThierry Reding <0x0 0x7d000000 0x0 0x4000>; 1037742af7e7SThierry Reding phy_type = "utmi"; 1038742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_USB2>, 1039742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_PLL_U>, 1040742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_USBD>; 1041742af7e7SThierry Reding clock-names = "reg", "pll_u", "utmi-pads"; 1042742af7e7SThierry Reding resets = <&tegra_car 58>, <&tegra_car 22>; 1043742af7e7SThierry Reding reset-names = "usb", "utmi-pads"; 1044742af7e7SThierry Reding nvidia,hssync-start-delay = <0>; 1045742af7e7SThierry Reding nvidia,idle-wait-delay = <17>; 1046742af7e7SThierry Reding nvidia,elastic-limit = <16>; 1047742af7e7SThierry Reding nvidia,term-range-adj = <6>; 1048742af7e7SThierry Reding nvidia,xcvr-setup = <9>; 1049742af7e7SThierry Reding nvidia,xcvr-lsfslew = <0>; 1050742af7e7SThierry Reding nvidia,xcvr-lsrslew = <3>; 1051742af7e7SThierry Reding nvidia,hssquelch-level = <2>; 1052742af7e7SThierry Reding nvidia,hsdiscon-level = <5>; 1053742af7e7SThierry Reding nvidia,xcvr-hsslew = <12>; 1054742af7e7SThierry Reding status = "disabled"; 1055742af7e7SThierry Reding }; 1056742af7e7SThierry Reding 1057742af7e7SThierry Reding cpus { 1058742af7e7SThierry Reding #address-cells = <1>; 1059742af7e7SThierry Reding #size-cells = <0>; 1060742af7e7SThierry Reding 1061742af7e7SThierry Reding cpu@0 { 1062742af7e7SThierry Reding device_type = "cpu"; 1063742af7e7SThierry Reding compatible = "arm,cortex-a57"; 1064742af7e7SThierry Reding reg = <0>; 1065742af7e7SThierry Reding }; 1066742af7e7SThierry Reding 1067742af7e7SThierry Reding cpu@1 { 1068742af7e7SThierry Reding device_type = "cpu"; 1069742af7e7SThierry Reding compatible = "arm,cortex-a57"; 1070742af7e7SThierry Reding reg = <1>; 1071742af7e7SThierry Reding }; 1072742af7e7SThierry Reding 1073742af7e7SThierry Reding cpu@2 { 1074742af7e7SThierry Reding device_type = "cpu"; 1075742af7e7SThierry Reding compatible = "arm,cortex-a57"; 1076742af7e7SThierry Reding reg = <2>; 1077742af7e7SThierry Reding }; 1078742af7e7SThierry Reding 1079742af7e7SThierry Reding cpu@3 { 1080742af7e7SThierry Reding device_type = "cpu"; 1081742af7e7SThierry Reding compatible = "arm,cortex-a57"; 1082742af7e7SThierry Reding reg = <3>; 1083742af7e7SThierry Reding }; 1084742af7e7SThierry Reding }; 1085742af7e7SThierry Reding 1086742af7e7SThierry Reding timer { 1087742af7e7SThierry Reding compatible = "arm,armv8-timer"; 1088742af7e7SThierry Reding interrupts = <GIC_PPI 13 1089742af7e7SThierry Reding (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1090742af7e7SThierry Reding <GIC_PPI 14 1091742af7e7SThierry Reding (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1092742af7e7SThierry Reding <GIC_PPI 11 1093742af7e7SThierry Reding (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1094742af7e7SThierry Reding <GIC_PPI 10 1095742af7e7SThierry Reding (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1096742af7e7SThierry Reding interrupt-parent = <&gic>; 1097742af7e7SThierry Reding }; 1098e2bed1ebSWei Ni 1099e2bed1ebSWei Ni soctherm: thermal-sensor@700e2000 { 1100e2bed1ebSWei Ni compatible = "nvidia,tegra210-soctherm"; 1101e2bed1ebSWei Ni reg = <0x0 0x700e2000 0x0 0x1000>; 1102e2bed1ebSWei Ni interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 1103e2bed1ebSWei Ni clocks = <&tegra_car TEGRA210_CLK_TSENSOR>, 1104e2bed1ebSWei Ni <&tegra_car TEGRA210_CLK_SOC_THERM>; 1105e2bed1ebSWei Ni clock-names = "tsensor", "soctherm"; 1106e2bed1ebSWei Ni resets = <&tegra_car 78>; 1107e2bed1ebSWei Ni reset-names = "soctherm"; 1108e2bed1ebSWei Ni #thermal-sensor-cells = <1>; 1109e2bed1ebSWei Ni }; 1110e2bed1ebSWei Ni 1111e2bed1ebSWei Ni thermal-zones { 1112e2bed1ebSWei Ni cpu { 1113e2bed1ebSWei Ni polling-delay-passive = <1000>; 1114e2bed1ebSWei Ni polling-delay = <0>; 1115e2bed1ebSWei Ni 1116e2bed1ebSWei Ni thermal-sensors = 1117e2bed1ebSWei Ni <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; 1118e2bed1ebSWei Ni }; 1119e2bed1ebSWei Ni mem { 1120e2bed1ebSWei Ni polling-delay-passive = <0>; 1121e2bed1ebSWei Ni polling-delay = <0>; 1122e2bed1ebSWei Ni 1123e2bed1ebSWei Ni thermal-sensors = 1124e2bed1ebSWei Ni <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>; 1125e2bed1ebSWei Ni }; 1126e2bed1ebSWei Ni gpu { 1127e2bed1ebSWei Ni polling-delay-passive = <1000>; 1128e2bed1ebSWei Ni polling-delay = <0>; 1129e2bed1ebSWei Ni 1130e2bed1ebSWei Ni thermal-sensors = 1131e2bed1ebSWei Ni <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>; 1132e2bed1ebSWei Ni }; 1133e2bed1ebSWei Ni pllx { 1134e2bed1ebSWei Ni polling-delay-passive = <0>; 1135e2bed1ebSWei Ni polling-delay = <0>; 1136e2bed1ebSWei Ni 1137e2bed1ebSWei Ni thermal-sensors = 1138e2bed1ebSWei Ni <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>; 1139e2bed1ebSWei Ni }; 1140e2bed1ebSWei Ni }; 1141742af7e7SThierry Reding}; 1142