1742af7e7SThierry Reding#include <dt-bindings/clock/tegra210-car.h> 2742af7e7SThierry Reding#include <dt-bindings/gpio/tegra-gpio.h> 3742af7e7SThierry Reding#include <dt-bindings/memory/tegra210-mc.h> 4742af7e7SThierry Reding#include <dt-bindings/pinctrl/pinctrl-tegra.h> 5742af7e7SThierry Reding#include <dt-bindings/interrupt-controller/arm-gic.h> 6742af7e7SThierry Reding 7742af7e7SThierry Reding/ { 8742af7e7SThierry Reding compatible = "nvidia,tegra210"; 9742af7e7SThierry Reding interrupt-parent = <&lic>; 10742af7e7SThierry Reding #address-cells = <2>; 11742af7e7SThierry Reding #size-cells = <2>; 12742af7e7SThierry Reding 13be70771dSThierry Reding host1x@50000000 { 14742af7e7SThierry Reding compatible = "nvidia,tegra210-host1x", "simple-bus"; 15742af7e7SThierry Reding reg = <0x0 0x50000000 0x0 0x00034000>; 16742af7e7SThierry Reding interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 17742af7e7SThierry Reding <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ 18742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_HOST1X>; 19742af7e7SThierry Reding clock-names = "host1x"; 20742af7e7SThierry Reding resets = <&tegra_car 28>; 21742af7e7SThierry Reding reset-names = "host1x"; 22742af7e7SThierry Reding 23742af7e7SThierry Reding #address-cells = <2>; 24742af7e7SThierry Reding #size-cells = <2>; 25742af7e7SThierry Reding 26742af7e7SThierry Reding ranges = <0x0 0x54000000 0x0 0x54000000 0x0 0x01000000>; 27742af7e7SThierry Reding 28be70771dSThierry Reding dpaux1: dpaux@54040000 { 29742af7e7SThierry Reding compatible = "nvidia,tegra210-dpaux"; 30742af7e7SThierry Reding reg = <0x0 0x54040000 0x0 0x00040000>; 31742af7e7SThierry Reding interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 32742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_DPAUX1>, 33742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_PLL_DP>; 34742af7e7SThierry Reding clock-names = "dpaux", "parent"; 35742af7e7SThierry Reding resets = <&tegra_car 207>; 36742af7e7SThierry Reding reset-names = "dpaux"; 37742af7e7SThierry Reding status = "disabled"; 38742af7e7SThierry Reding }; 39742af7e7SThierry Reding 40be70771dSThierry Reding vi@54080000 { 41742af7e7SThierry Reding compatible = "nvidia,tegra210-vi"; 42742af7e7SThierry Reding reg = <0x0 0x54080000 0x0 0x00040000>; 43742af7e7SThierry Reding interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 44742af7e7SThierry Reding status = "disabled"; 45742af7e7SThierry Reding }; 46742af7e7SThierry Reding 47be70771dSThierry Reding tsec@54100000 { 48742af7e7SThierry Reding compatible = "nvidia,tegra210-tsec"; 49742af7e7SThierry Reding reg = <0x0 0x54100000 0x0 0x00040000>; 50742af7e7SThierry Reding }; 51742af7e7SThierry Reding 52be70771dSThierry Reding dc@54200000 { 53742af7e7SThierry Reding compatible = "nvidia,tegra210-dc"; 54742af7e7SThierry Reding reg = <0x0 0x54200000 0x0 0x00040000>; 55742af7e7SThierry Reding interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 56742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_DISP1>, 57742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_PLL_P>; 58742af7e7SThierry Reding clock-names = "dc", "parent"; 59742af7e7SThierry Reding resets = <&tegra_car 27>; 60742af7e7SThierry Reding reset-names = "dc"; 61742af7e7SThierry Reding 62742af7e7SThierry Reding iommus = <&mc TEGRA_SWGROUP_DC>; 63742af7e7SThierry Reding 64742af7e7SThierry Reding nvidia,head = <0>; 65742af7e7SThierry Reding }; 66742af7e7SThierry Reding 67be70771dSThierry Reding dc@54240000 { 68742af7e7SThierry Reding compatible = "nvidia,tegra210-dc"; 69742af7e7SThierry Reding reg = <0x0 0x54240000 0x0 0x00040000>; 70742af7e7SThierry Reding interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 71742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_DISP2>, 72742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_PLL_P>; 73742af7e7SThierry Reding clock-names = "dc", "parent"; 74742af7e7SThierry Reding resets = <&tegra_car 26>; 75742af7e7SThierry Reding reset-names = "dc"; 76742af7e7SThierry Reding 77742af7e7SThierry Reding iommus = <&mc TEGRA_SWGROUP_DCB>; 78742af7e7SThierry Reding 79742af7e7SThierry Reding nvidia,head = <1>; 80742af7e7SThierry Reding }; 81742af7e7SThierry Reding 82be70771dSThierry Reding dsi@54300000 { 83742af7e7SThierry Reding compatible = "nvidia,tegra210-dsi"; 84742af7e7SThierry Reding reg = <0x0 0x54300000 0x0 0x00040000>; 85742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_DSIA>, 86742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_DSIALP>, 87742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; 88742af7e7SThierry Reding clock-names = "dsi", "lp", "parent"; 89742af7e7SThierry Reding resets = <&tegra_car 48>; 90742af7e7SThierry Reding reset-names = "dsi"; 91742af7e7SThierry Reding nvidia,mipi-calibrate = <&mipi 0x0c0>; /* DSIA & DSIB pads */ 92742af7e7SThierry Reding 93742af7e7SThierry Reding status = "disabled"; 94742af7e7SThierry Reding 95742af7e7SThierry Reding #address-cells = <1>; 96742af7e7SThierry Reding #size-cells = <0>; 97742af7e7SThierry Reding }; 98742af7e7SThierry Reding 99be70771dSThierry Reding vic@54340000 { 100742af7e7SThierry Reding compatible = "nvidia,tegra210-vic"; 101742af7e7SThierry Reding reg = <0x0 0x54340000 0x0 0x00040000>; 102742af7e7SThierry Reding status = "disabled"; 103742af7e7SThierry Reding }; 104742af7e7SThierry Reding 105be70771dSThierry Reding nvjpg@54380000 { 106742af7e7SThierry Reding compatible = "nvidia,tegra210-nvjpg"; 107742af7e7SThierry Reding reg = <0x0 0x54380000 0x0 0x00040000>; 108742af7e7SThierry Reding status = "disabled"; 109742af7e7SThierry Reding }; 110742af7e7SThierry Reding 111be70771dSThierry Reding dsi@54400000 { 112742af7e7SThierry Reding compatible = "nvidia,tegra210-dsi"; 113742af7e7SThierry Reding reg = <0x0 0x54400000 0x0 0x00040000>; 114742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_DSIB>, 115742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_DSIBLP>, 116742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; 117742af7e7SThierry Reding clock-names = "dsi", "lp", "parent"; 118742af7e7SThierry Reding resets = <&tegra_car 82>; 119742af7e7SThierry Reding reset-names = "dsi"; 120742af7e7SThierry Reding nvidia,mipi-calibrate = <&mipi 0x300>; /* DSIC & DSID pads */ 121742af7e7SThierry Reding 122742af7e7SThierry Reding status = "disabled"; 123742af7e7SThierry Reding 124742af7e7SThierry Reding #address-cells = <1>; 125742af7e7SThierry Reding #size-cells = <0>; 126742af7e7SThierry Reding }; 127742af7e7SThierry Reding 128be70771dSThierry Reding nvdec@54480000 { 129742af7e7SThierry Reding compatible = "nvidia,tegra210-nvdec"; 130742af7e7SThierry Reding reg = <0x0 0x54480000 0x0 0x00040000>; 131742af7e7SThierry Reding status = "disabled"; 132742af7e7SThierry Reding }; 133742af7e7SThierry Reding 134be70771dSThierry Reding nvenc@544c0000 { 135742af7e7SThierry Reding compatible = "nvidia,tegra210-nvenc"; 136742af7e7SThierry Reding reg = <0x0 0x544c0000 0x0 0x00040000>; 137742af7e7SThierry Reding status = "disabled"; 138742af7e7SThierry Reding }; 139742af7e7SThierry Reding 140be70771dSThierry Reding tsec@54500000 { 141742af7e7SThierry Reding compatible = "nvidia,tegra210-tsec"; 142742af7e7SThierry Reding reg = <0x0 0x54500000 0x0 0x00040000>; 143742af7e7SThierry Reding status = "disabled"; 144742af7e7SThierry Reding }; 145742af7e7SThierry Reding 146be70771dSThierry Reding sor@54540000 { 147742af7e7SThierry Reding compatible = "nvidia,tegra210-sor"; 148742af7e7SThierry Reding reg = <0x0 0x54540000 0x0 0x00040000>; 149742af7e7SThierry Reding interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 150742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_SOR0>, 151742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_PLL_D_OUT0>, 152742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_PLL_DP>, 153742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_SOR_SAFE>; 154742af7e7SThierry Reding clock-names = "sor", "parent", "dp", "safe"; 155742af7e7SThierry Reding resets = <&tegra_car 182>; 156742af7e7SThierry Reding reset-names = "sor"; 157742af7e7SThierry Reding status = "disabled"; 158742af7e7SThierry Reding }; 159742af7e7SThierry Reding 160be70771dSThierry Reding sor@54580000 { 161742af7e7SThierry Reding compatible = "nvidia,tegra210-sor1"; 162742af7e7SThierry Reding reg = <0x0 0x54580000 0x0 0x00040000>; 163742af7e7SThierry Reding interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 164742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_SOR1>, 165742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_PLL_D2_OUT0>, 166742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_PLL_DP>, 167742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_SOR_SAFE>; 168742af7e7SThierry Reding clock-names = "sor", "parent", "dp", "safe"; 169742af7e7SThierry Reding resets = <&tegra_car 183>; 170742af7e7SThierry Reding reset-names = "sor"; 171742af7e7SThierry Reding status = "disabled"; 172742af7e7SThierry Reding }; 173742af7e7SThierry Reding 174be70771dSThierry Reding dpaux: dpaux@545c0000 { 175742af7e7SThierry Reding compatible = "nvidia,tegra124-dpaux"; 176742af7e7SThierry Reding reg = <0x0 0x545c0000 0x0 0x00040000>; 177742af7e7SThierry Reding interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 178742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_DPAUX>, 179742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_PLL_DP>; 180742af7e7SThierry Reding clock-names = "dpaux", "parent"; 181742af7e7SThierry Reding resets = <&tegra_car 181>; 182742af7e7SThierry Reding reset-names = "dpaux"; 183742af7e7SThierry Reding status = "disabled"; 184742af7e7SThierry Reding }; 185742af7e7SThierry Reding 186be70771dSThierry Reding isp@54600000 { 187742af7e7SThierry Reding compatible = "nvidia,tegra210-isp"; 188742af7e7SThierry Reding reg = <0x0 0x54600000 0x0 0x00040000>; 189742af7e7SThierry Reding interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 190742af7e7SThierry Reding status = "disabled"; 191742af7e7SThierry Reding }; 192742af7e7SThierry Reding 193be70771dSThierry Reding isp@54680000 { 194742af7e7SThierry Reding compatible = "nvidia,tegra210-isp"; 195742af7e7SThierry Reding reg = <0x0 0x54680000 0x0 0x00040000>; 196742af7e7SThierry Reding interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 197742af7e7SThierry Reding status = "disabled"; 198742af7e7SThierry Reding }; 199742af7e7SThierry Reding 200be70771dSThierry Reding i2c@546c0000 { 201742af7e7SThierry Reding compatible = "nvidia,tegra210-i2c-vi"; 202742af7e7SThierry Reding reg = <0x0 0x546c0000 0x0 0x00040000>; 203742af7e7SThierry Reding interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 204742af7e7SThierry Reding status = "disabled"; 205742af7e7SThierry Reding }; 206742af7e7SThierry Reding }; 207742af7e7SThierry Reding 208be70771dSThierry Reding gic: interrupt-controller@50041000 { 209742af7e7SThierry Reding compatible = "arm,gic-400"; 210742af7e7SThierry Reding #interrupt-cells = <3>; 211742af7e7SThierry Reding interrupt-controller; 212742af7e7SThierry Reding reg = <0x0 0x50041000 0x0 0x1000>, 213742af7e7SThierry Reding <0x0 0x50042000 0x0 0x2000>, 214742af7e7SThierry Reding <0x0 0x50044000 0x0 0x2000>, 215742af7e7SThierry Reding <0x0 0x50046000 0x0 0x2000>; 216742af7e7SThierry Reding interrupts = <GIC_PPI 9 217742af7e7SThierry Reding (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 218742af7e7SThierry Reding interrupt-parent = <&gic>; 219742af7e7SThierry Reding }; 220742af7e7SThierry Reding 221be70771dSThierry Reding gpu@57000000 { 222742af7e7SThierry Reding compatible = "nvidia,gm20b"; 223742af7e7SThierry Reding reg = <0x0 0x57000000 0x0 0x01000000>, 224742af7e7SThierry Reding <0x0 0x58000000 0x0 0x01000000>; 225742af7e7SThierry Reding interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 226742af7e7SThierry Reding <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 227742af7e7SThierry Reding interrupt-names = "stall", "nonstall"; 228742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_GPU>, 229742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_PLL_P_OUT5>; 230742af7e7SThierry Reding clock-names = "gpu", "pwr"; 231742af7e7SThierry Reding resets = <&tegra_car 184>; 232742af7e7SThierry Reding reset-names = "gpu"; 233742af7e7SThierry Reding status = "disabled"; 234742af7e7SThierry Reding }; 235742af7e7SThierry Reding 236be70771dSThierry Reding lic: interrupt-controller@60004000 { 237742af7e7SThierry Reding compatible = "nvidia,tegra210-ictlr"; 238742af7e7SThierry Reding reg = <0x0 0x60004000 0x0 0x40>, /* primary controller */ 239742af7e7SThierry Reding <0x0 0x60004100 0x0 0x40>, /* secondary controller */ 240742af7e7SThierry Reding <0x0 0x60004200 0x0 0x40>, /* tertiary controller */ 241742af7e7SThierry Reding <0x0 0x60004300 0x0 0x40>, /* quaternary controller */ 242742af7e7SThierry Reding <0x0 0x60004400 0x0 0x40>, /* quinary controller */ 243742af7e7SThierry Reding <0x0 0x60004500 0x0 0x40>; /* senary controller */ 244742af7e7SThierry Reding interrupt-controller; 245742af7e7SThierry Reding #interrupt-cells = <3>; 246742af7e7SThierry Reding interrupt-parent = <&gic>; 247742af7e7SThierry Reding }; 248742af7e7SThierry Reding 249be70771dSThierry Reding timer@60005000 { 250742af7e7SThierry Reding compatible = "nvidia,tegra210-timer", "nvidia,tegra20-timer"; 251742af7e7SThierry Reding reg = <0x0 0x60005000 0x0 0x400>; 252742af7e7SThierry Reding interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 253742af7e7SThierry Reding <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 254742af7e7SThierry Reding <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 255742af7e7SThierry Reding <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 256742af7e7SThierry Reding <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 257742af7e7SThierry Reding <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 258742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_TIMER>; 259742af7e7SThierry Reding clock-names = "timer"; 260742af7e7SThierry Reding }; 261742af7e7SThierry Reding 262be70771dSThierry Reding tegra_car: clock@60006000 { 263742af7e7SThierry Reding compatible = "nvidia,tegra210-car"; 264742af7e7SThierry Reding reg = <0x0 0x60006000 0x0 0x1000>; 265742af7e7SThierry Reding #clock-cells = <1>; 266742af7e7SThierry Reding #reset-cells = <1>; 267742af7e7SThierry Reding }; 268742af7e7SThierry Reding 269be70771dSThierry Reding flow-controller@60007000 { 270742af7e7SThierry Reding compatible = "nvidia,tegra210-flowctrl"; 271742af7e7SThierry Reding reg = <0x0 0x60007000 0x0 0x1000>; 272742af7e7SThierry Reding }; 273742af7e7SThierry Reding 274be70771dSThierry Reding gpio: gpio@6000d000 { 275742af7e7SThierry Reding compatible = "nvidia,tegra210-gpio", "nvidia,tegra124-gpio", "nvidia,tegra30-gpio"; 276742af7e7SThierry Reding reg = <0x0 0x6000d000 0x0 0x1000>; 277742af7e7SThierry Reding interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 278742af7e7SThierry Reding <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 279742af7e7SThierry Reding <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 280742af7e7SThierry Reding <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 281742af7e7SThierry Reding <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 282742af7e7SThierry Reding <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 283742af7e7SThierry Reding <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 284742af7e7SThierry Reding <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 285742af7e7SThierry Reding #gpio-cells = <2>; 286742af7e7SThierry Reding gpio-controller; 287742af7e7SThierry Reding #interrupt-cells = <2>; 288742af7e7SThierry Reding interrupt-controller; 289742af7e7SThierry Reding }; 290742af7e7SThierry Reding 291be70771dSThierry Reding apbdma: dma@60020000 { 292742af7e7SThierry Reding compatible = "nvidia,tegra210-apbdma", "nvidia,tegra148-apbdma"; 293742af7e7SThierry Reding reg = <0x0 0x60020000 0x0 0x1400>; 294742af7e7SThierry Reding interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 295742af7e7SThierry Reding <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 296742af7e7SThierry Reding <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 297742af7e7SThierry Reding <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 298742af7e7SThierry Reding <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 299742af7e7SThierry Reding <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 300742af7e7SThierry Reding <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 301742af7e7SThierry Reding <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 302742af7e7SThierry Reding <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 303742af7e7SThierry Reding <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 304742af7e7SThierry Reding <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 305742af7e7SThierry Reding <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 306742af7e7SThierry Reding <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 307742af7e7SThierry Reding <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 308742af7e7SThierry Reding <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 309742af7e7SThierry Reding <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 310742af7e7SThierry Reding <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 311742af7e7SThierry Reding <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 312742af7e7SThierry Reding <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 313742af7e7SThierry Reding <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 314742af7e7SThierry Reding <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 315742af7e7SThierry Reding <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 316742af7e7SThierry Reding <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 317742af7e7SThierry Reding <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 318742af7e7SThierry Reding <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 319742af7e7SThierry Reding <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 320742af7e7SThierry Reding <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 321742af7e7SThierry Reding <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 322742af7e7SThierry Reding <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 323742af7e7SThierry Reding <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 324742af7e7SThierry Reding <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 325742af7e7SThierry Reding <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 326742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_APBDMA>; 327742af7e7SThierry Reding clock-names = "dma"; 328742af7e7SThierry Reding resets = <&tegra_car 34>; 329742af7e7SThierry Reding reset-names = "dma"; 330742af7e7SThierry Reding #dma-cells = <1>; 331742af7e7SThierry Reding }; 332742af7e7SThierry Reding 333be70771dSThierry Reding apbmisc@70000800 { 334742af7e7SThierry Reding compatible = "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc"; 335742af7e7SThierry Reding reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */ 336742af7e7SThierry Reding <0x0 0x7000e864 0x0 0x04>; /* Strapping options */ 337742af7e7SThierry Reding }; 338742af7e7SThierry Reding 339be70771dSThierry Reding pinmux: pinmux@700008d4 { 340742af7e7SThierry Reding compatible = "nvidia,tegra210-pinmux"; 341742af7e7SThierry Reding reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */ 342742af7e7SThierry Reding <0x0 0x70003000 0x0 0x294>; /* Mux registers */ 343742af7e7SThierry Reding }; 344742af7e7SThierry Reding 345742af7e7SThierry Reding /* 346742af7e7SThierry Reding * There are two serial driver i.e. 8250 based simple serial 347742af7e7SThierry Reding * driver and APB DMA based serial driver for higher baudrate 348ef769e32SAdam Buchbinder * and performance. To enable the 8250 based driver, the compatible 349742af7e7SThierry Reding * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable 350742af7e7SThierry Reding * the APB DMA based serial driver, the comptible is 351742af7e7SThierry Reding * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". 352742af7e7SThierry Reding */ 353be70771dSThierry Reding uarta: serial@70006000 { 354742af7e7SThierry Reding compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 355742af7e7SThierry Reding reg = <0x0 0x70006000 0x0 0x40>; 356742af7e7SThierry Reding reg-shift = <2>; 357742af7e7SThierry Reding interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 358742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_UARTA>; 359742af7e7SThierry Reding clock-names = "serial"; 360742af7e7SThierry Reding resets = <&tegra_car 6>; 361742af7e7SThierry Reding reset-names = "serial"; 362742af7e7SThierry Reding dmas = <&apbdma 8>, <&apbdma 8>; 363742af7e7SThierry Reding dma-names = "rx", "tx"; 364742af7e7SThierry Reding status = "disabled"; 365742af7e7SThierry Reding }; 366742af7e7SThierry Reding 367be70771dSThierry Reding uartb: serial@70006040 { 368742af7e7SThierry Reding compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 369742af7e7SThierry Reding reg = <0x0 0x70006040 0x0 0x40>; 370742af7e7SThierry Reding reg-shift = <2>; 371742af7e7SThierry Reding interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 372742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_UARTB>; 373742af7e7SThierry Reding clock-names = "serial"; 374742af7e7SThierry Reding resets = <&tegra_car 7>; 375742af7e7SThierry Reding reset-names = "serial"; 376742af7e7SThierry Reding dmas = <&apbdma 9>, <&apbdma 9>; 377742af7e7SThierry Reding dma-names = "rx", "tx"; 378742af7e7SThierry Reding status = "disabled"; 379742af7e7SThierry Reding }; 380742af7e7SThierry Reding 381be70771dSThierry Reding uartc: serial@70006200 { 382742af7e7SThierry Reding compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 383742af7e7SThierry Reding reg = <0x0 0x70006200 0x0 0x40>; 384742af7e7SThierry Reding reg-shift = <2>; 385742af7e7SThierry Reding interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 386742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_UARTC>; 387742af7e7SThierry Reding clock-names = "serial"; 388742af7e7SThierry Reding resets = <&tegra_car 55>; 389742af7e7SThierry Reding reset-names = "serial"; 390742af7e7SThierry Reding dmas = <&apbdma 10>, <&apbdma 10>; 391742af7e7SThierry Reding dma-names = "rx", "tx"; 392742af7e7SThierry Reding status = "disabled"; 393742af7e7SThierry Reding }; 394742af7e7SThierry Reding 395be70771dSThierry Reding uartd: serial@70006300 { 396742af7e7SThierry Reding compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 397742af7e7SThierry Reding reg = <0x0 0x70006300 0x0 0x40>; 398742af7e7SThierry Reding reg-shift = <2>; 399742af7e7SThierry Reding interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 400742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_UARTD>; 401742af7e7SThierry Reding clock-names = "serial"; 402742af7e7SThierry Reding resets = <&tegra_car 65>; 403742af7e7SThierry Reding reset-names = "serial"; 404742af7e7SThierry Reding dmas = <&apbdma 19>, <&apbdma 19>; 405742af7e7SThierry Reding dma-names = "rx", "tx"; 406742af7e7SThierry Reding status = "disabled"; 407742af7e7SThierry Reding }; 408742af7e7SThierry Reding 409be70771dSThierry Reding pwm: pwm@7000a000 { 410742af7e7SThierry Reding compatible = "nvidia,tegra210-pwm", "nvidia,tegra20-pwm"; 411742af7e7SThierry Reding reg = <0x0 0x7000a000 0x0 0x100>; 412742af7e7SThierry Reding #pwm-cells = <2>; 413742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_PWM>; 414742af7e7SThierry Reding clock-names = "pwm"; 415742af7e7SThierry Reding resets = <&tegra_car 17>; 416742af7e7SThierry Reding reset-names = "pwm"; 417742af7e7SThierry Reding status = "disabled"; 418742af7e7SThierry Reding }; 419742af7e7SThierry Reding 420be70771dSThierry Reding i2c@7000c000 { 421742af7e7SThierry Reding compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 422742af7e7SThierry Reding reg = <0x0 0x7000c000 0x0 0x100>; 423742af7e7SThierry Reding interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 424742af7e7SThierry Reding #address-cells = <1>; 425742af7e7SThierry Reding #size-cells = <0>; 426742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_I2C1>; 427742af7e7SThierry Reding clock-names = "div-clk"; 428742af7e7SThierry Reding resets = <&tegra_car 12>; 429742af7e7SThierry Reding reset-names = "i2c"; 430742af7e7SThierry Reding dmas = <&apbdma 21>, <&apbdma 21>; 431742af7e7SThierry Reding dma-names = "rx", "tx"; 432742af7e7SThierry Reding status = "disabled"; 433742af7e7SThierry Reding }; 434742af7e7SThierry Reding 435be70771dSThierry Reding i2c@7000c400 { 436742af7e7SThierry Reding compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 437742af7e7SThierry Reding reg = <0x0 0x7000c400 0x0 0x100>; 438742af7e7SThierry Reding interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 439742af7e7SThierry Reding #address-cells = <1>; 440742af7e7SThierry Reding #size-cells = <0>; 441742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_I2C2>; 442742af7e7SThierry Reding clock-names = "div-clk"; 443742af7e7SThierry Reding resets = <&tegra_car 54>; 444742af7e7SThierry Reding reset-names = "i2c"; 445742af7e7SThierry Reding dmas = <&apbdma 22>, <&apbdma 22>; 446742af7e7SThierry Reding dma-names = "rx", "tx"; 447742af7e7SThierry Reding status = "disabled"; 448742af7e7SThierry Reding }; 449742af7e7SThierry Reding 450be70771dSThierry Reding i2c@7000c500 { 451742af7e7SThierry Reding compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 452742af7e7SThierry Reding reg = <0x0 0x7000c500 0x0 0x100>; 453742af7e7SThierry Reding interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 454742af7e7SThierry Reding #address-cells = <1>; 455742af7e7SThierry Reding #size-cells = <0>; 456742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_I2C3>; 457742af7e7SThierry Reding clock-names = "div-clk"; 458742af7e7SThierry Reding resets = <&tegra_car 67>; 459742af7e7SThierry Reding reset-names = "i2c"; 460742af7e7SThierry Reding dmas = <&apbdma 23>, <&apbdma 23>; 461742af7e7SThierry Reding dma-names = "rx", "tx"; 462742af7e7SThierry Reding status = "disabled"; 463742af7e7SThierry Reding }; 464742af7e7SThierry Reding 465be70771dSThierry Reding i2c@7000c700 { 466742af7e7SThierry Reding compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 467742af7e7SThierry Reding reg = <0x0 0x7000c700 0x0 0x100>; 468742af7e7SThierry Reding interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 469742af7e7SThierry Reding #address-cells = <1>; 470742af7e7SThierry Reding #size-cells = <0>; 471742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_I2C4>; 472742af7e7SThierry Reding clock-names = "div-clk"; 473742af7e7SThierry Reding resets = <&tegra_car 103>; 474742af7e7SThierry Reding reset-names = "i2c"; 475742af7e7SThierry Reding dmas = <&apbdma 26>, <&apbdma 26>; 476742af7e7SThierry Reding dma-names = "rx", "tx"; 477742af7e7SThierry Reding status = "disabled"; 478742af7e7SThierry Reding }; 479742af7e7SThierry Reding 480be70771dSThierry Reding i2c@7000d000 { 481742af7e7SThierry Reding compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 482742af7e7SThierry Reding reg = <0x0 0x7000d000 0x0 0x100>; 483742af7e7SThierry Reding interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 484742af7e7SThierry Reding #address-cells = <1>; 485742af7e7SThierry Reding #size-cells = <0>; 486742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_I2C5>; 487742af7e7SThierry Reding clock-names = "div-clk"; 488742af7e7SThierry Reding resets = <&tegra_car 47>; 489742af7e7SThierry Reding reset-names = "i2c"; 490742af7e7SThierry Reding dmas = <&apbdma 24>, <&apbdma 24>; 491742af7e7SThierry Reding dma-names = "rx", "tx"; 492742af7e7SThierry Reding status = "disabled"; 493742af7e7SThierry Reding }; 494742af7e7SThierry Reding 495be70771dSThierry Reding i2c@7000d100 { 496742af7e7SThierry Reding compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 497742af7e7SThierry Reding reg = <0x0 0x7000d100 0x0 0x100>; 498742af7e7SThierry Reding interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 499742af7e7SThierry Reding #address-cells = <1>; 500742af7e7SThierry Reding #size-cells = <0>; 501742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_I2C6>; 502742af7e7SThierry Reding clock-names = "div-clk"; 503742af7e7SThierry Reding resets = <&tegra_car 166>; 504742af7e7SThierry Reding reset-names = "i2c"; 505742af7e7SThierry Reding dmas = <&apbdma 30>, <&apbdma 30>; 506742af7e7SThierry Reding dma-names = "rx", "tx"; 507742af7e7SThierry Reding status = "disabled"; 508742af7e7SThierry Reding }; 509742af7e7SThierry Reding 510be70771dSThierry Reding spi@7000d400 { 511742af7e7SThierry Reding compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 512742af7e7SThierry Reding reg = <0x0 0x7000d400 0x0 0x200>; 513742af7e7SThierry Reding interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 514742af7e7SThierry Reding #address-cells = <1>; 515742af7e7SThierry Reding #size-cells = <0>; 516742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_SBC1>; 517742af7e7SThierry Reding clock-names = "spi"; 518742af7e7SThierry Reding resets = <&tegra_car 41>; 519742af7e7SThierry Reding reset-names = "spi"; 520742af7e7SThierry Reding dmas = <&apbdma 15>, <&apbdma 15>; 521742af7e7SThierry Reding dma-names = "rx", "tx"; 522742af7e7SThierry Reding status = "disabled"; 523742af7e7SThierry Reding }; 524742af7e7SThierry Reding 525be70771dSThierry Reding spi@7000d600 { 526742af7e7SThierry Reding compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 527742af7e7SThierry Reding reg = <0x0 0x7000d600 0x0 0x200>; 528742af7e7SThierry Reding interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 529742af7e7SThierry Reding #address-cells = <1>; 530742af7e7SThierry Reding #size-cells = <0>; 531742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_SBC2>; 532742af7e7SThierry Reding clock-names = "spi"; 533742af7e7SThierry Reding resets = <&tegra_car 44>; 534742af7e7SThierry Reding reset-names = "spi"; 535742af7e7SThierry Reding dmas = <&apbdma 16>, <&apbdma 16>; 536742af7e7SThierry Reding dma-names = "rx", "tx"; 537742af7e7SThierry Reding status = "disabled"; 538742af7e7SThierry Reding }; 539742af7e7SThierry Reding 540be70771dSThierry Reding spi@7000d800 { 541742af7e7SThierry Reding compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 542742af7e7SThierry Reding reg = <0x0 0x7000d800 0x0 0x200>; 543742af7e7SThierry Reding interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 544742af7e7SThierry Reding #address-cells = <1>; 545742af7e7SThierry Reding #size-cells = <0>; 546742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_SBC3>; 547742af7e7SThierry Reding clock-names = "spi"; 548742af7e7SThierry Reding resets = <&tegra_car 46>; 549742af7e7SThierry Reding reset-names = "spi"; 550742af7e7SThierry Reding dmas = <&apbdma 17>, <&apbdma 17>; 551742af7e7SThierry Reding dma-names = "rx", "tx"; 552742af7e7SThierry Reding status = "disabled"; 553742af7e7SThierry Reding }; 554742af7e7SThierry Reding 555be70771dSThierry Reding spi@7000da00 { 556742af7e7SThierry Reding compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 557742af7e7SThierry Reding reg = <0x0 0x7000da00 0x0 0x200>; 558742af7e7SThierry Reding interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 559742af7e7SThierry Reding #address-cells = <1>; 560742af7e7SThierry Reding #size-cells = <0>; 561742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_SBC4>; 562742af7e7SThierry Reding clock-names = "spi"; 563742af7e7SThierry Reding resets = <&tegra_car 68>; 564742af7e7SThierry Reding reset-names = "spi"; 565742af7e7SThierry Reding dmas = <&apbdma 18>, <&apbdma 18>; 566742af7e7SThierry Reding dma-names = "rx", "tx"; 567742af7e7SThierry Reding status = "disabled"; 568742af7e7SThierry Reding }; 569742af7e7SThierry Reding 570be70771dSThierry Reding rtc@7000e000 { 571742af7e7SThierry Reding compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc"; 572742af7e7SThierry Reding reg = <0x0 0x7000e000 0x0 0x100>; 573742af7e7SThierry Reding interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 574742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_RTC>; 575742af7e7SThierry Reding clock-names = "rtc"; 576742af7e7SThierry Reding }; 577742af7e7SThierry Reding 578be70771dSThierry Reding pmc: pmc@7000e400 { 579742af7e7SThierry Reding compatible = "nvidia,tegra210-pmc"; 580742af7e7SThierry Reding reg = <0x0 0x7000e400 0x0 0x400>; 581742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; 582742af7e7SThierry Reding clock-names = "pclk", "clk32k_in"; 583742af7e7SThierry Reding 584742af7e7SThierry Reding #power-domain-cells = <1>; 585742af7e7SThierry Reding }; 586742af7e7SThierry Reding 587be70771dSThierry Reding fuse@7000f800 { 588742af7e7SThierry Reding compatible = "nvidia,tegra210-efuse"; 589742af7e7SThierry Reding reg = <0x0 0x7000f800 0x0 0x400>; 590742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_FUSE>; 591742af7e7SThierry Reding clock-names = "fuse"; 592742af7e7SThierry Reding resets = <&tegra_car 39>; 593742af7e7SThierry Reding reset-names = "fuse"; 594742af7e7SThierry Reding }; 595742af7e7SThierry Reding 596be70771dSThierry Reding mc: memory-controller@70019000 { 597742af7e7SThierry Reding compatible = "nvidia,tegra210-mc"; 598742af7e7SThierry Reding reg = <0x0 0x70019000 0x0 0x1000>; 599742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_MC>; 600742af7e7SThierry Reding clock-names = "mc"; 601742af7e7SThierry Reding 602742af7e7SThierry Reding interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 603742af7e7SThierry Reding 604742af7e7SThierry Reding #iommu-cells = <1>; 605742af7e7SThierry Reding }; 606742af7e7SThierry Reding 607be70771dSThierry Reding hda@70030000 { 608742af7e7SThierry Reding compatible = "nvidia,tegra210-hda", "nvidia,tegra30-hda"; 609742af7e7SThierry Reding reg = <0x0 0x70030000 0x0 0x10000>; 610742af7e7SThierry Reding interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 611742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_HDA>, 612742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_HDA2HDMI>, 613742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_HDA2CODEC_2X>; 614742af7e7SThierry Reding clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 615742af7e7SThierry Reding resets = <&tegra_car 125>, /* hda */ 616742af7e7SThierry Reding <&tegra_car 128>, /* hda2hdmi */ 617742af7e7SThierry Reding <&tegra_car 111>; /* hda2codec_2x */ 618742af7e7SThierry Reding reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 619742af7e7SThierry Reding status = "disabled"; 620742af7e7SThierry Reding }; 621742af7e7SThierry Reding 622be70771dSThierry Reding sdhci@700b0000 { 623742af7e7SThierry Reding compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; 624742af7e7SThierry Reding reg = <0x0 0x700b0000 0x0 0x200>; 625742af7e7SThierry Reding interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 626742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_SDMMC1>; 627742af7e7SThierry Reding clock-names = "sdhci"; 628742af7e7SThierry Reding resets = <&tegra_car 14>; 629742af7e7SThierry Reding reset-names = "sdhci"; 630742af7e7SThierry Reding status = "disabled"; 631742af7e7SThierry Reding }; 632742af7e7SThierry Reding 633be70771dSThierry Reding sdhci@700b0200 { 634742af7e7SThierry Reding compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; 635742af7e7SThierry Reding reg = <0x0 0x700b0200 0x0 0x200>; 636742af7e7SThierry Reding interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 637742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_SDMMC2>; 638742af7e7SThierry Reding clock-names = "sdhci"; 639742af7e7SThierry Reding resets = <&tegra_car 9>; 640742af7e7SThierry Reding reset-names = "sdhci"; 641742af7e7SThierry Reding status = "disabled"; 642742af7e7SThierry Reding }; 643742af7e7SThierry Reding 644be70771dSThierry Reding sdhci@700b0400 { 645742af7e7SThierry Reding compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; 646742af7e7SThierry Reding reg = <0x0 0x700b0400 0x0 0x200>; 647742af7e7SThierry Reding interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 648742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_SDMMC3>; 649742af7e7SThierry Reding clock-names = "sdhci"; 650742af7e7SThierry Reding resets = <&tegra_car 69>; 651742af7e7SThierry Reding reset-names = "sdhci"; 652742af7e7SThierry Reding status = "disabled"; 653742af7e7SThierry Reding }; 654742af7e7SThierry Reding 655be70771dSThierry Reding sdhci@700b0600 { 656742af7e7SThierry Reding compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; 657742af7e7SThierry Reding reg = <0x0 0x700b0600 0x0 0x200>; 658742af7e7SThierry Reding interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 659742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_SDMMC4>; 660742af7e7SThierry Reding clock-names = "sdhci"; 661742af7e7SThierry Reding resets = <&tegra_car 15>; 662742af7e7SThierry Reding reset-names = "sdhci"; 663742af7e7SThierry Reding status = "disabled"; 664742af7e7SThierry Reding }; 665742af7e7SThierry Reding 666be70771dSThierry Reding mipi: mipi@700e3000 { 667742af7e7SThierry Reding compatible = "nvidia,tegra210-mipi"; 668742af7e7SThierry Reding reg = <0x0 0x700e3000 0x0 0x100>; 669742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_MIPI_CAL>; 670742af7e7SThierry Reding clock-names = "mipi-cal"; 671742af7e7SThierry Reding #nvidia,mipi-calibrate-cells = <1>; 672742af7e7SThierry Reding }; 673742af7e7SThierry Reding 674be70771dSThierry Reding spi@70410000 { 675742af7e7SThierry Reding compatible = "nvidia,tegra210-qspi"; 676742af7e7SThierry Reding reg = <0x0 0x70410000 0x0 0x1000>; 677742af7e7SThierry Reding interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 678742af7e7SThierry Reding #address-cells = <1>; 679742af7e7SThierry Reding #size-cells = <0>; 680742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_QSPI>; 681742af7e7SThierry Reding clock-names = "qspi"; 682742af7e7SThierry Reding resets = <&tegra_car 211>; 683742af7e7SThierry Reding reset-names = "qspi"; 684742af7e7SThierry Reding dmas = <&apbdma 5>, <&apbdma 5>; 685742af7e7SThierry Reding dma-names = "rx", "tx"; 686742af7e7SThierry Reding status = "disabled"; 687742af7e7SThierry Reding }; 688742af7e7SThierry Reding 689be70771dSThierry Reding usb@7d000000 { 690742af7e7SThierry Reding compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 691742af7e7SThierry Reding reg = <0x0 0x7d000000 0x0 0x4000>; 692742af7e7SThierry Reding interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 693742af7e7SThierry Reding phy_type = "utmi"; 694742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_USBD>; 695742af7e7SThierry Reding clock-names = "usb"; 696742af7e7SThierry Reding resets = <&tegra_car 22>; 697742af7e7SThierry Reding reset-names = "usb"; 698742af7e7SThierry Reding nvidia,phy = <&phy1>; 699742af7e7SThierry Reding status = "disabled"; 700742af7e7SThierry Reding }; 701742af7e7SThierry Reding 702be70771dSThierry Reding phy1: usb-phy@7d000000 { 703742af7e7SThierry Reding compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; 704742af7e7SThierry Reding reg = <0x0 0x7d000000 0x0 0x4000>, 705742af7e7SThierry Reding <0x0 0x7d000000 0x0 0x4000>; 706742af7e7SThierry Reding phy_type = "utmi"; 707742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_USBD>, 708742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_PLL_U>, 709742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_USBD>; 710742af7e7SThierry Reding clock-names = "reg", "pll_u", "utmi-pads"; 711742af7e7SThierry Reding resets = <&tegra_car 22>, <&tegra_car 22>; 712742af7e7SThierry Reding reset-names = "usb", "utmi-pads"; 713742af7e7SThierry Reding nvidia,hssync-start-delay = <0>; 714742af7e7SThierry Reding nvidia,idle-wait-delay = <17>; 715742af7e7SThierry Reding nvidia,elastic-limit = <16>; 716742af7e7SThierry Reding nvidia,term-range-adj = <6>; 717742af7e7SThierry Reding nvidia,xcvr-setup = <9>; 718742af7e7SThierry Reding nvidia,xcvr-lsfslew = <0>; 719742af7e7SThierry Reding nvidia,xcvr-lsrslew = <3>; 720742af7e7SThierry Reding nvidia,hssquelch-level = <2>; 721742af7e7SThierry Reding nvidia,hsdiscon-level = <5>; 722742af7e7SThierry Reding nvidia,xcvr-hsslew = <12>; 723742af7e7SThierry Reding nvidia,has-utmi-pad-registers; 724742af7e7SThierry Reding status = "disabled"; 725742af7e7SThierry Reding }; 726742af7e7SThierry Reding 727be70771dSThierry Reding usb@7d004000 { 728742af7e7SThierry Reding compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 729742af7e7SThierry Reding reg = <0x0 0x7d004000 0x0 0x4000>; 730742af7e7SThierry Reding interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 731742af7e7SThierry Reding phy_type = "utmi"; 732742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_USB2>; 733742af7e7SThierry Reding clock-names = "usb"; 734742af7e7SThierry Reding resets = <&tegra_car 58>; 735742af7e7SThierry Reding reset-names = "usb"; 736742af7e7SThierry Reding nvidia,phy = <&phy2>; 737742af7e7SThierry Reding status = "disabled"; 738742af7e7SThierry Reding }; 739742af7e7SThierry Reding 740be70771dSThierry Reding phy2: usb-phy@7d004000 { 741742af7e7SThierry Reding compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; 742742af7e7SThierry Reding reg = <0x0 0x7d004000 0x0 0x4000>, 743742af7e7SThierry Reding <0x0 0x7d000000 0x0 0x4000>; 744742af7e7SThierry Reding phy_type = "utmi"; 745742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_USB2>, 746742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_PLL_U>, 747742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_USBD>; 748742af7e7SThierry Reding clock-names = "reg", "pll_u", "utmi-pads"; 749742af7e7SThierry Reding resets = <&tegra_car 58>, <&tegra_car 22>; 750742af7e7SThierry Reding reset-names = "usb", "utmi-pads"; 751742af7e7SThierry Reding nvidia,hssync-start-delay = <0>; 752742af7e7SThierry Reding nvidia,idle-wait-delay = <17>; 753742af7e7SThierry Reding nvidia,elastic-limit = <16>; 754742af7e7SThierry Reding nvidia,term-range-adj = <6>; 755742af7e7SThierry Reding nvidia,xcvr-setup = <9>; 756742af7e7SThierry Reding nvidia,xcvr-lsfslew = <0>; 757742af7e7SThierry Reding nvidia,xcvr-lsrslew = <3>; 758742af7e7SThierry Reding nvidia,hssquelch-level = <2>; 759742af7e7SThierry Reding nvidia,hsdiscon-level = <5>; 760742af7e7SThierry Reding nvidia,xcvr-hsslew = <12>; 761742af7e7SThierry Reding status = "disabled"; 762742af7e7SThierry Reding }; 763742af7e7SThierry Reding 764742af7e7SThierry Reding cpus { 765742af7e7SThierry Reding #address-cells = <1>; 766742af7e7SThierry Reding #size-cells = <0>; 767742af7e7SThierry Reding 768742af7e7SThierry Reding cpu@0 { 769742af7e7SThierry Reding device_type = "cpu"; 770742af7e7SThierry Reding compatible = "arm,cortex-a57"; 771742af7e7SThierry Reding reg = <0>; 772742af7e7SThierry Reding }; 773742af7e7SThierry Reding 774742af7e7SThierry Reding cpu@1 { 775742af7e7SThierry Reding device_type = "cpu"; 776742af7e7SThierry Reding compatible = "arm,cortex-a57"; 777742af7e7SThierry Reding reg = <1>; 778742af7e7SThierry Reding }; 779742af7e7SThierry Reding 780742af7e7SThierry Reding cpu@2 { 781742af7e7SThierry Reding device_type = "cpu"; 782742af7e7SThierry Reding compatible = "arm,cortex-a57"; 783742af7e7SThierry Reding reg = <2>; 784742af7e7SThierry Reding }; 785742af7e7SThierry Reding 786742af7e7SThierry Reding cpu@3 { 787742af7e7SThierry Reding device_type = "cpu"; 788742af7e7SThierry Reding compatible = "arm,cortex-a57"; 789742af7e7SThierry Reding reg = <3>; 790742af7e7SThierry Reding }; 791742af7e7SThierry Reding }; 792742af7e7SThierry Reding 793742af7e7SThierry Reding timer { 794742af7e7SThierry Reding compatible = "arm,armv8-timer"; 795742af7e7SThierry Reding interrupts = <GIC_PPI 13 796742af7e7SThierry Reding (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 797742af7e7SThierry Reding <GIC_PPI 14 798742af7e7SThierry Reding (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 799742af7e7SThierry Reding <GIC_PPI 11 800742af7e7SThierry Reding (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 801742af7e7SThierry Reding <GIC_PPI 10 802742af7e7SThierry Reding (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 803742af7e7SThierry Reding interrupt-parent = <&gic>; 804742af7e7SThierry Reding }; 805742af7e7SThierry Reding}; 806