1b2441318SGreg Kroah-Hartman// SPDX-License-Identifier: GPL-2.0 2742af7e7SThierry Reding#include <dt-bindings/clock/tegra210-car.h> 3742af7e7SThierry Reding#include <dt-bindings/gpio/tegra-gpio.h> 4742af7e7SThierry Reding#include <dt-bindings/memory/tegra210-mc.h> 5742af7e7SThierry Reding#include <dt-bindings/pinctrl/pinctrl-tegra.h> 66641af7eSAapo Vienamo#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 72ceed593SJoseph Lo#include <dt-bindings/reset/tegra210-car.h> 8742af7e7SThierry Reding#include <dt-bindings/interrupt-controller/arm-gic.h> 9e2bed1ebSWei Ni#include <dt-bindings/thermal/tegra124-soctherm.h> 10359ae651SSowjanya Komatineni#include <dt-bindings/soc/tegra-pmc.h> 11742af7e7SThierry Reding 12742af7e7SThierry Reding/ { 13742af7e7SThierry Reding compatible = "nvidia,tegra210"; 14742af7e7SThierry Reding interrupt-parent = <&lic>; 15742af7e7SThierry Reding #address-cells = <2>; 16742af7e7SThierry Reding #size-cells = <2>; 17742af7e7SThierry Reding 18475d99fcSRob Herring pcie@1003000 { 19589a2d3fSThierry Reding compatible = "nvidia,tegra210-pcie"; 20589a2d3fSThierry Reding device_type = "pci"; 21589a2d3fSThierry Reding reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */ 22589a2d3fSThierry Reding 0x0 0x01003800 0x0 0x00000800 /* AFI registers */ 23589a2d3fSThierry Reding 0x0 0x02000000 0x0 0x10000000>; /* configuration space */ 24589a2d3fSThierry Reding reg-names = "pads", "afi", "cs"; 25589a2d3fSThierry Reding interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 26589a2d3fSThierry Reding <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 27589a2d3fSThierry Reding interrupt-names = "intr", "msi"; 28589a2d3fSThierry Reding 29589a2d3fSThierry Reding #interrupt-cells = <1>; 30589a2d3fSThierry Reding interrupt-map-mask = <0 0 0 0>; 31589a2d3fSThierry Reding interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 32589a2d3fSThierry Reding 33589a2d3fSThierry Reding bus-range = <0x00 0xff>; 34589a2d3fSThierry Reding #address-cells = <3>; 35589a2d3fSThierry Reding #size-cells = <2>; 36589a2d3fSThierry Reding 37589a2d3fSThierry Reding ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */ 38589a2d3fSThierry Reding 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */ 39589a2d3fSThierry Reding 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */ 40589a2d3fSThierry Reding 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */ 41589a2d3fSThierry Reding 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ 42589a2d3fSThierry Reding 43589a2d3fSThierry Reding clocks = <&tegra_car TEGRA210_CLK_PCIE>, 44589a2d3fSThierry Reding <&tegra_car TEGRA210_CLK_AFI>, 45589a2d3fSThierry Reding <&tegra_car TEGRA210_CLK_PLL_E>, 46589a2d3fSThierry Reding <&tegra_car TEGRA210_CLK_CML0>; 47589a2d3fSThierry Reding clock-names = "pex", "afi", "pll_e", "cml"; 48589a2d3fSThierry Reding resets = <&tegra_car 70>, 49589a2d3fSThierry Reding <&tegra_car 72>, 50589a2d3fSThierry Reding <&tegra_car 74>; 51589a2d3fSThierry Reding reset-names = "pex", "afi", "pcie_x"; 52871be845SManikanta Maddireddy 53871be845SManikanta Maddireddy pinctrl-names = "default", "idle"; 54871be845SManikanta Maddireddy pinctrl-0 = <&pex_dpd_disable>; 55871be845SManikanta Maddireddy pinctrl-1 = <&pex_dpd_enable>; 56871be845SManikanta Maddireddy 57589a2d3fSThierry Reding status = "disabled"; 58589a2d3fSThierry Reding 59589a2d3fSThierry Reding pci@1,0 { 60589a2d3fSThierry Reding device_type = "pci"; 61589a2d3fSThierry Reding assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>; 62589a2d3fSThierry Reding reg = <0x000800 0 0 0 0>; 63475d99fcSRob Herring bus-range = <0x00 0xff>; 64589a2d3fSThierry Reding status = "disabled"; 65589a2d3fSThierry Reding 66589a2d3fSThierry Reding #address-cells = <3>; 67589a2d3fSThierry Reding #size-cells = <2>; 68589a2d3fSThierry Reding ranges; 69589a2d3fSThierry Reding 70589a2d3fSThierry Reding nvidia,num-lanes = <4>; 71589a2d3fSThierry Reding }; 72589a2d3fSThierry Reding 73589a2d3fSThierry Reding pci@2,0 { 74589a2d3fSThierry Reding device_type = "pci"; 75589a2d3fSThierry Reding assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>; 76589a2d3fSThierry Reding reg = <0x001000 0 0 0 0>; 77475d99fcSRob Herring bus-range = <0x00 0xff>; 78589a2d3fSThierry Reding status = "disabled"; 79589a2d3fSThierry Reding 80589a2d3fSThierry Reding #address-cells = <3>; 81589a2d3fSThierry Reding #size-cells = <2>; 82589a2d3fSThierry Reding ranges; 83589a2d3fSThierry Reding 84589a2d3fSThierry Reding nvidia,num-lanes = <1>; 85589a2d3fSThierry Reding }; 86589a2d3fSThierry Reding }; 87589a2d3fSThierry Reding 88be70771dSThierry Reding host1x@50000000 { 89742af7e7SThierry Reding compatible = "nvidia,tegra210-host1x", "simple-bus"; 90742af7e7SThierry Reding reg = <0x0 0x50000000 0x0 0x00034000>; 91742af7e7SThierry Reding interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 92742af7e7SThierry Reding <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ 93742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_HOST1X>; 94742af7e7SThierry Reding clock-names = "host1x"; 95742af7e7SThierry Reding resets = <&tegra_car 28>; 96742af7e7SThierry Reding reset-names = "host1x"; 97742af7e7SThierry Reding 98742af7e7SThierry Reding #address-cells = <2>; 99742af7e7SThierry Reding #size-cells = <2>; 100742af7e7SThierry Reding 101742af7e7SThierry Reding ranges = <0x0 0x54000000 0x0 0x54000000 0x0 0x01000000>; 102742af7e7SThierry Reding 103116503a6SMikko Perttunen iommus = <&mc TEGRA_SWGROUP_HC>; 104116503a6SMikko Perttunen 105be70771dSThierry Reding dpaux1: dpaux@54040000 { 106742af7e7SThierry Reding compatible = "nvidia,tegra210-dpaux"; 107742af7e7SThierry Reding reg = <0x0 0x54040000 0x0 0x00040000>; 108742af7e7SThierry Reding interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 109742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_DPAUX1>, 110742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_PLL_DP>; 111742af7e7SThierry Reding clock-names = "dpaux", "parent"; 112742af7e7SThierry Reding resets = <&tegra_car 207>; 113742af7e7SThierry Reding reset-names = "dpaux"; 11496d1f078SJon Hunter power-domains = <&pd_sor>; 115742af7e7SThierry Reding status = "disabled"; 11666b2d6e9SJon Hunter 11766b2d6e9SJon Hunter state_dpaux1_aux: pinmux-aux { 11866b2d6e9SJon Hunter groups = "dpaux-io"; 11966b2d6e9SJon Hunter function = "aux"; 12066b2d6e9SJon Hunter }; 12166b2d6e9SJon Hunter 12266b2d6e9SJon Hunter state_dpaux1_i2c: pinmux-i2c { 12366b2d6e9SJon Hunter groups = "dpaux-io"; 12466b2d6e9SJon Hunter function = "i2c"; 12566b2d6e9SJon Hunter }; 12666b2d6e9SJon Hunter 12766b2d6e9SJon Hunter state_dpaux1_off: pinmux-off { 12866b2d6e9SJon Hunter groups = "dpaux-io"; 12966b2d6e9SJon Hunter function = "off"; 13066b2d6e9SJon Hunter }; 13166b2d6e9SJon Hunter 13266b2d6e9SJon Hunter i2c-bus { 13366b2d6e9SJon Hunter #address-cells = <1>; 13466b2d6e9SJon Hunter #size-cells = <0>; 13566b2d6e9SJon Hunter }; 136742af7e7SThierry Reding }; 137742af7e7SThierry Reding 138be70771dSThierry Reding vi@54080000 { 139742af7e7SThierry Reding compatible = "nvidia,tegra210-vi"; 140c4153885SSowjanya Komatineni reg = <0x0 0x54080000 0x0 0x700>; 141742af7e7SThierry Reding interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 142742af7e7SThierry Reding status = "disabled"; 143c4153885SSowjanya Komatineni assigned-clocks = <&tegra_car TEGRA210_CLK_VI>; 144c4153885SSowjanya Komatineni assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 145c4153885SSowjanya Komatineni 146c4153885SSowjanya Komatineni clocks = <&tegra_car TEGRA210_CLK_VI>; 147c4153885SSowjanya Komatineni power-domains = <&pd_venc>; 148c4153885SSowjanya Komatineni 149c4153885SSowjanya Komatineni #address-cells = <1>; 150c4153885SSowjanya Komatineni #size-cells = <1>; 151c4153885SSowjanya Komatineni 152c4153885SSowjanya Komatineni ranges = <0x0 0x0 0x54080000 0x2000>; 153c4153885SSowjanya Komatineni 154c4153885SSowjanya Komatineni csi@838 { 155c4153885SSowjanya Komatineni compatible = "nvidia,tegra210-csi"; 156c4153885SSowjanya Komatineni reg = <0x838 0x1300>; 157c4153885SSowjanya Komatineni status = "disabled"; 158c4153885SSowjanya Komatineni assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>, 159c4153885SSowjanya Komatineni <&tegra_car TEGRA210_CLK_CILCD>, 160c4153885SSowjanya Komatineni <&tegra_car TEGRA210_CLK_CILE>, 161c4153885SSowjanya Komatineni <&tegra_car TEGRA210_CLK_CSI_TPG>; 162c4153885SSowjanya Komatineni assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>, 163c4153885SSowjanya Komatineni <&tegra_car TEGRA210_CLK_PLL_P>, 164c4153885SSowjanya Komatineni <&tegra_car TEGRA210_CLK_PLL_P>; 165c4153885SSowjanya Komatineni assigned-clock-rates = <102000000>, 166c4153885SSowjanya Komatineni <102000000>, 167c4153885SSowjanya Komatineni <102000000>, 168c4153885SSowjanya Komatineni <972000000>; 169c4153885SSowjanya Komatineni 170c4153885SSowjanya Komatineni clocks = <&tegra_car TEGRA210_CLK_CSI>, 171c4153885SSowjanya Komatineni <&tegra_car TEGRA210_CLK_CILAB>, 172c4153885SSowjanya Komatineni <&tegra_car TEGRA210_CLK_CILCD>, 173c4153885SSowjanya Komatineni <&tegra_car TEGRA210_CLK_CILE>, 174c4153885SSowjanya Komatineni <&tegra_car TEGRA210_CLK_CSI_TPG>; 175c4153885SSowjanya Komatineni clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg"; 176c4153885SSowjanya Komatineni power-domains = <&pd_sor>; 177c4153885SSowjanya Komatineni }; 178742af7e7SThierry Reding }; 179742af7e7SThierry Reding 180be70771dSThierry Reding tsec@54100000 { 181742af7e7SThierry Reding compatible = "nvidia,tegra210-tsec"; 182742af7e7SThierry Reding reg = <0x0 0x54100000 0x0 0x00040000>; 183742af7e7SThierry Reding }; 184742af7e7SThierry Reding 185be70771dSThierry Reding dc@54200000 { 186742af7e7SThierry Reding compatible = "nvidia,tegra210-dc"; 187742af7e7SThierry Reding reg = <0x0 0x54200000 0x0 0x00040000>; 188742af7e7SThierry Reding interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 189742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_DISP1>, 190742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_PLL_P>; 191742af7e7SThierry Reding clock-names = "dc", "parent"; 192742af7e7SThierry Reding resets = <&tegra_car 27>; 193742af7e7SThierry Reding reset-names = "dc"; 194742af7e7SThierry Reding 195742af7e7SThierry Reding iommus = <&mc TEGRA_SWGROUP_DC>; 196742af7e7SThierry Reding 197742af7e7SThierry Reding nvidia,head = <0>; 198742af7e7SThierry Reding }; 199742af7e7SThierry Reding 200be70771dSThierry Reding dc@54240000 { 201742af7e7SThierry Reding compatible = "nvidia,tegra210-dc"; 202742af7e7SThierry Reding reg = <0x0 0x54240000 0x0 0x00040000>; 203742af7e7SThierry Reding interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 204742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_DISP2>, 205742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_PLL_P>; 206742af7e7SThierry Reding clock-names = "dc", "parent"; 207742af7e7SThierry Reding resets = <&tegra_car 26>; 208742af7e7SThierry Reding reset-names = "dc"; 209742af7e7SThierry Reding 210742af7e7SThierry Reding iommus = <&mc TEGRA_SWGROUP_DCB>; 211742af7e7SThierry Reding 212742af7e7SThierry Reding nvidia,head = <1>; 213742af7e7SThierry Reding }; 214742af7e7SThierry Reding 215be70771dSThierry Reding dsi@54300000 { 216742af7e7SThierry Reding compatible = "nvidia,tegra210-dsi"; 217742af7e7SThierry Reding reg = <0x0 0x54300000 0x0 0x00040000>; 218742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_DSIA>, 219742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_DSIALP>, 220742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; 221742af7e7SThierry Reding clock-names = "dsi", "lp", "parent"; 222742af7e7SThierry Reding resets = <&tegra_car 48>; 223742af7e7SThierry Reding reset-names = "dsi"; 22496d1f078SJon Hunter power-domains = <&pd_sor>; 225742af7e7SThierry Reding nvidia,mipi-calibrate = <&mipi 0x0c0>; /* DSIA & DSIB pads */ 226742af7e7SThierry Reding 227742af7e7SThierry Reding status = "disabled"; 228742af7e7SThierry Reding 229742af7e7SThierry Reding #address-cells = <1>; 230742af7e7SThierry Reding #size-cells = <0>; 231742af7e7SThierry Reding }; 232742af7e7SThierry Reding 233be70771dSThierry Reding vic@54340000 { 234742af7e7SThierry Reding compatible = "nvidia,tegra210-vic"; 235742af7e7SThierry Reding reg = <0x0 0x54340000 0x0 0x00040000>; 23624963d1bSMikko Perttunen interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 23724963d1bSMikko Perttunen clocks = <&tegra_car TEGRA210_CLK_VIC03>; 23824963d1bSMikko Perttunen clock-names = "vic"; 23924963d1bSMikko Perttunen resets = <&tegra_car 178>; 24024963d1bSMikko Perttunen reset-names = "vic"; 24124963d1bSMikko Perttunen 24224963d1bSMikko Perttunen iommus = <&mc TEGRA_SWGROUP_VIC>; 24324963d1bSMikko Perttunen power-domains = <&pd_vic>; 244742af7e7SThierry Reding }; 245742af7e7SThierry Reding 246be70771dSThierry Reding nvjpg@54380000 { 247742af7e7SThierry Reding compatible = "nvidia,tegra210-nvjpg"; 248742af7e7SThierry Reding reg = <0x0 0x54380000 0x0 0x00040000>; 249742af7e7SThierry Reding status = "disabled"; 250742af7e7SThierry Reding }; 251742af7e7SThierry Reding 252be70771dSThierry Reding dsi@54400000 { 253742af7e7SThierry Reding compatible = "nvidia,tegra210-dsi"; 254742af7e7SThierry Reding reg = <0x0 0x54400000 0x0 0x00040000>; 255742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_DSIB>, 256742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_DSIBLP>, 257742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; 258742af7e7SThierry Reding clock-names = "dsi", "lp", "parent"; 259742af7e7SThierry Reding resets = <&tegra_car 82>; 260742af7e7SThierry Reding reset-names = "dsi"; 26196d1f078SJon Hunter power-domains = <&pd_sor>; 262742af7e7SThierry Reding nvidia,mipi-calibrate = <&mipi 0x300>; /* DSIC & DSID pads */ 263742af7e7SThierry Reding 264742af7e7SThierry Reding status = "disabled"; 265742af7e7SThierry Reding 266742af7e7SThierry Reding #address-cells = <1>; 267742af7e7SThierry Reding #size-cells = <0>; 268742af7e7SThierry Reding }; 269742af7e7SThierry Reding 270be70771dSThierry Reding nvdec@54480000 { 271742af7e7SThierry Reding compatible = "nvidia,tegra210-nvdec"; 272742af7e7SThierry Reding reg = <0x0 0x54480000 0x0 0x00040000>; 273742af7e7SThierry Reding status = "disabled"; 274742af7e7SThierry Reding }; 275742af7e7SThierry Reding 276be70771dSThierry Reding nvenc@544c0000 { 277742af7e7SThierry Reding compatible = "nvidia,tegra210-nvenc"; 278742af7e7SThierry Reding reg = <0x0 0x544c0000 0x0 0x00040000>; 279742af7e7SThierry Reding status = "disabled"; 280742af7e7SThierry Reding }; 281742af7e7SThierry Reding 282be70771dSThierry Reding tsec@54500000 { 283742af7e7SThierry Reding compatible = "nvidia,tegra210-tsec"; 284742af7e7SThierry Reding reg = <0x0 0x54500000 0x0 0x00040000>; 285742af7e7SThierry Reding status = "disabled"; 286742af7e7SThierry Reding }; 287742af7e7SThierry Reding 288be70771dSThierry Reding sor@54540000 { 289742af7e7SThierry Reding compatible = "nvidia,tegra210-sor"; 290742af7e7SThierry Reding reg = <0x0 0x54540000 0x0 0x00040000>; 291742af7e7SThierry Reding interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 292742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_SOR0>, 293ed93a666SThierry Reding <&tegra_car TEGRA210_CLK_SOR0_OUT>, 294742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_PLL_D_OUT0>, 295742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_PLL_DP>, 296742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_SOR_SAFE>; 297ed93a666SThierry Reding clock-names = "sor", "out", "parent", "dp", "safe"; 298742af7e7SThierry Reding resets = <&tegra_car 182>; 299742af7e7SThierry Reding reset-names = "sor"; 30066b2d6e9SJon Hunter pinctrl-0 = <&state_dpaux_aux>; 30166b2d6e9SJon Hunter pinctrl-1 = <&state_dpaux_i2c>; 30266b2d6e9SJon Hunter pinctrl-2 = <&state_dpaux_off>; 30366b2d6e9SJon Hunter pinctrl-names = "aux", "i2c", "off"; 30496d1f078SJon Hunter power-domains = <&pd_sor>; 305742af7e7SThierry Reding status = "disabled"; 306742af7e7SThierry Reding }; 307742af7e7SThierry Reding 308be70771dSThierry Reding sor@54580000 { 309742af7e7SThierry Reding compatible = "nvidia,tegra210-sor1"; 310742af7e7SThierry Reding reg = <0x0 0x54580000 0x0 0x00040000>; 311742af7e7SThierry Reding interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 312742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_SOR1>, 31350f5b841SThierry Reding <&tegra_car TEGRA210_CLK_SOR1_OUT>, 314742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_PLL_D2_OUT0>, 315742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_PLL_DP>, 316742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_SOR_SAFE>; 31750f5b841SThierry Reding clock-names = "sor", "out", "parent", "dp", "safe"; 318742af7e7SThierry Reding resets = <&tegra_car 183>; 319742af7e7SThierry Reding reset-names = "sor"; 32066b2d6e9SJon Hunter pinctrl-0 = <&state_dpaux1_aux>; 32166b2d6e9SJon Hunter pinctrl-1 = <&state_dpaux1_i2c>; 32266b2d6e9SJon Hunter pinctrl-2 = <&state_dpaux1_off>; 32366b2d6e9SJon Hunter pinctrl-names = "aux", "i2c", "off"; 32496d1f078SJon Hunter power-domains = <&pd_sor>; 325742af7e7SThierry Reding status = "disabled"; 326742af7e7SThierry Reding }; 327742af7e7SThierry Reding 328be70771dSThierry Reding dpaux: dpaux@545c0000 { 329742af7e7SThierry Reding compatible = "nvidia,tegra124-dpaux"; 330742af7e7SThierry Reding reg = <0x0 0x545c0000 0x0 0x00040000>; 331742af7e7SThierry Reding interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 332742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_DPAUX>, 333742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_PLL_DP>; 334742af7e7SThierry Reding clock-names = "dpaux", "parent"; 335742af7e7SThierry Reding resets = <&tegra_car 181>; 336742af7e7SThierry Reding reset-names = "dpaux"; 33796d1f078SJon Hunter power-domains = <&pd_sor>; 338742af7e7SThierry Reding status = "disabled"; 33966b2d6e9SJon Hunter 34066b2d6e9SJon Hunter state_dpaux_aux: pinmux-aux { 34166b2d6e9SJon Hunter groups = "dpaux-io"; 34266b2d6e9SJon Hunter function = "aux"; 34366b2d6e9SJon Hunter }; 34466b2d6e9SJon Hunter 34566b2d6e9SJon Hunter state_dpaux_i2c: pinmux-i2c { 34666b2d6e9SJon Hunter groups = "dpaux-io"; 34766b2d6e9SJon Hunter function = "i2c"; 34866b2d6e9SJon Hunter }; 34966b2d6e9SJon Hunter 35066b2d6e9SJon Hunter state_dpaux_off: pinmux-off { 35166b2d6e9SJon Hunter groups = "dpaux-io"; 35266b2d6e9SJon Hunter function = "off"; 35366b2d6e9SJon Hunter }; 35466b2d6e9SJon Hunter 35566b2d6e9SJon Hunter i2c-bus { 35666b2d6e9SJon Hunter #address-cells = <1>; 35766b2d6e9SJon Hunter #size-cells = <0>; 35866b2d6e9SJon Hunter }; 359742af7e7SThierry Reding }; 360742af7e7SThierry Reding 361be70771dSThierry Reding isp@54600000 { 362742af7e7SThierry Reding compatible = "nvidia,tegra210-isp"; 363742af7e7SThierry Reding reg = <0x0 0x54600000 0x0 0x00040000>; 364742af7e7SThierry Reding interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 365742af7e7SThierry Reding status = "disabled"; 366742af7e7SThierry Reding }; 367742af7e7SThierry Reding 368be70771dSThierry Reding isp@54680000 { 369742af7e7SThierry Reding compatible = "nvidia,tegra210-isp"; 370742af7e7SThierry Reding reg = <0x0 0x54680000 0x0 0x00040000>; 371742af7e7SThierry Reding interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 372742af7e7SThierry Reding status = "disabled"; 373742af7e7SThierry Reding }; 374742af7e7SThierry Reding 375be70771dSThierry Reding i2c@546c0000 { 376742af7e7SThierry Reding compatible = "nvidia,tegra210-i2c-vi"; 377742af7e7SThierry Reding reg = <0x0 0x546c0000 0x0 0x00040000>; 378742af7e7SThierry Reding interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 379742af7e7SThierry Reding status = "disabled"; 380742af7e7SThierry Reding }; 381742af7e7SThierry Reding }; 382742af7e7SThierry Reding 383be70771dSThierry Reding gic: interrupt-controller@50041000 { 384742af7e7SThierry Reding compatible = "arm,gic-400"; 385742af7e7SThierry Reding #interrupt-cells = <3>; 386742af7e7SThierry Reding interrupt-controller; 387742af7e7SThierry Reding reg = <0x0 0x50041000 0x0 0x1000>, 388742af7e7SThierry Reding <0x0 0x50042000 0x0 0x2000>, 389742af7e7SThierry Reding <0x0 0x50044000 0x0 0x2000>, 390742af7e7SThierry Reding <0x0 0x50046000 0x0 0x2000>; 391742af7e7SThierry Reding interrupts = <GIC_PPI 9 392742af7e7SThierry Reding (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 393742af7e7SThierry Reding interrupt-parent = <&gic>; 394742af7e7SThierry Reding }; 395742af7e7SThierry Reding 396be70771dSThierry Reding gpu@57000000 { 397742af7e7SThierry Reding compatible = "nvidia,gm20b"; 398742af7e7SThierry Reding reg = <0x0 0x57000000 0x0 0x01000000>, 399742af7e7SThierry Reding <0x0 0x58000000 0x0 0x01000000>; 400742af7e7SThierry Reding interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 401742af7e7SThierry Reding <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 402742af7e7SThierry Reding interrupt-names = "stall", "nonstall"; 403742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_GPU>, 4044a0778e9SAlexandre Courbot <&tegra_car TEGRA210_CLK_PLL_P_OUT5>, 4054a0778e9SAlexandre Courbot <&tegra_car TEGRA210_CLK_PLL_G_REF>; 4064a0778e9SAlexandre Courbot clock-names = "gpu", "pwr", "ref"; 407742af7e7SThierry Reding resets = <&tegra_car 184>; 408742af7e7SThierry Reding reset-names = "gpu"; 40930f949bcSAlexandre Courbot 41030f949bcSAlexandre Courbot iommus = <&mc TEGRA_SWGROUP_GPU>; 41130f949bcSAlexandre Courbot 412742af7e7SThierry Reding status = "disabled"; 413742af7e7SThierry Reding }; 414742af7e7SThierry Reding 415be70771dSThierry Reding lic: interrupt-controller@60004000 { 416742af7e7SThierry Reding compatible = "nvidia,tegra210-ictlr"; 417742af7e7SThierry Reding reg = <0x0 0x60004000 0x0 0x40>, /* primary controller */ 418742af7e7SThierry Reding <0x0 0x60004100 0x0 0x40>, /* secondary controller */ 419742af7e7SThierry Reding <0x0 0x60004200 0x0 0x40>, /* tertiary controller */ 420742af7e7SThierry Reding <0x0 0x60004300 0x0 0x40>, /* quaternary controller */ 421742af7e7SThierry Reding <0x0 0x60004400 0x0 0x40>, /* quinary controller */ 422742af7e7SThierry Reding <0x0 0x60004500 0x0 0x40>; /* senary controller */ 423742af7e7SThierry Reding interrupt-controller; 424742af7e7SThierry Reding #interrupt-cells = <3>; 425742af7e7SThierry Reding interrupt-parent = <&gic>; 426742af7e7SThierry Reding }; 427742af7e7SThierry Reding 428be70771dSThierry Reding timer@60005000 { 429d9931a18SJoseph Lo compatible = "nvidia,tegra210-timer"; 430742af7e7SThierry Reding reg = <0x0 0x60005000 0x0 0x400>; 431d9931a18SJoseph Lo interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 432d9931a18SJoseph Lo <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 433742af7e7SThierry Reding <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 434742af7e7SThierry Reding <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 435742af7e7SThierry Reding <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 436742af7e7SThierry Reding <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 437d9931a18SJoseph Lo <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 438d9931a18SJoseph Lo <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 439d9931a18SJoseph Lo <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 440d9931a18SJoseph Lo <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 441d9931a18SJoseph Lo <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 442d9931a18SJoseph Lo <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 443d9931a18SJoseph Lo <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, 444d9931a18SJoseph Lo <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 445742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_TIMER>; 446742af7e7SThierry Reding clock-names = "timer"; 447742af7e7SThierry Reding }; 448742af7e7SThierry Reding 449be70771dSThierry Reding tegra_car: clock@60006000 { 450742af7e7SThierry Reding compatible = "nvidia,tegra210-car"; 451742af7e7SThierry Reding reg = <0x0 0x60006000 0x0 0x1000>; 452742af7e7SThierry Reding #clock-cells = <1>; 453742af7e7SThierry Reding #reset-cells = <1>; 454742af7e7SThierry Reding }; 455742af7e7SThierry Reding 456be70771dSThierry Reding flow-controller@60007000 { 457742af7e7SThierry Reding compatible = "nvidia,tegra210-flowctrl"; 458742af7e7SThierry Reding reg = <0x0 0x60007000 0x0 0x1000>; 459742af7e7SThierry Reding }; 460742af7e7SThierry Reding 461be70771dSThierry Reding gpio: gpio@6000d000 { 46201665512SStephen Warren compatible = "nvidia,tegra210-gpio", "nvidia,tegra30-gpio"; 463742af7e7SThierry Reding reg = <0x0 0x6000d000 0x0 0x1000>; 464742af7e7SThierry Reding interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 465742af7e7SThierry Reding <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 466742af7e7SThierry Reding <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 467742af7e7SThierry Reding <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 468742af7e7SThierry Reding <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 469742af7e7SThierry Reding <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 470742af7e7SThierry Reding <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 471742af7e7SThierry Reding <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 472742af7e7SThierry Reding #gpio-cells = <2>; 473742af7e7SThierry Reding gpio-controller; 474742af7e7SThierry Reding #interrupt-cells = <2>; 475742af7e7SThierry Reding interrupt-controller; 476742af7e7SThierry Reding }; 477742af7e7SThierry Reding 478be70771dSThierry Reding apbdma: dma@60020000 { 479742af7e7SThierry Reding compatible = "nvidia,tegra210-apbdma", "nvidia,tegra148-apbdma"; 480742af7e7SThierry Reding reg = <0x0 0x60020000 0x0 0x1400>; 481742af7e7SThierry Reding interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 482742af7e7SThierry Reding <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 483742af7e7SThierry Reding <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 484742af7e7SThierry Reding <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 485742af7e7SThierry Reding <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 486742af7e7SThierry Reding <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 487742af7e7SThierry Reding <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 488742af7e7SThierry Reding <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 489742af7e7SThierry Reding <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 490742af7e7SThierry Reding <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 491742af7e7SThierry Reding <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 492742af7e7SThierry Reding <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 493742af7e7SThierry Reding <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 494742af7e7SThierry Reding <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 495742af7e7SThierry Reding <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 496742af7e7SThierry Reding <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 497742af7e7SThierry Reding <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 498742af7e7SThierry Reding <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 499742af7e7SThierry Reding <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 500742af7e7SThierry Reding <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 501742af7e7SThierry Reding <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 502742af7e7SThierry Reding <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 503742af7e7SThierry Reding <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 504742af7e7SThierry Reding <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 505742af7e7SThierry Reding <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 506742af7e7SThierry Reding <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 507742af7e7SThierry Reding <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 508742af7e7SThierry Reding <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 509742af7e7SThierry Reding <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 510742af7e7SThierry Reding <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 511742af7e7SThierry Reding <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 512742af7e7SThierry Reding <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 513742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_APBDMA>; 514742af7e7SThierry Reding clock-names = "dma"; 515742af7e7SThierry Reding resets = <&tegra_car 34>; 516742af7e7SThierry Reding reset-names = "dma"; 517742af7e7SThierry Reding #dma-cells = <1>; 518742af7e7SThierry Reding }; 519742af7e7SThierry Reding 520be70771dSThierry Reding apbmisc@70000800 { 521742af7e7SThierry Reding compatible = "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc"; 522742af7e7SThierry Reding reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */ 52346e4b227SJoseph Lo <0x0 0x70000008 0x0 0x04>; /* Strapping options */ 524742af7e7SThierry Reding }; 525742af7e7SThierry Reding 526be70771dSThierry Reding pinmux: pinmux@700008d4 { 527742af7e7SThierry Reding compatible = "nvidia,tegra210-pinmux"; 528742af7e7SThierry Reding reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */ 529742af7e7SThierry Reding <0x0 0x70003000 0x0 0x294>; /* Mux registers */ 5304e0f1229SSowjanya Komatineni sdmmc1_3v3_drv: sdmmc1-3v3-drv { 5314e0f1229SSowjanya Komatineni sdmmc1 { 5324e0f1229SSowjanya Komatineni nvidia,pins = "drive_sdmmc1"; 5334e0f1229SSowjanya Komatineni nvidia,pull-down-strength = <0x8>; 5344e0f1229SSowjanya Komatineni nvidia,pull-up-strength = <0x8>; 5354e0f1229SSowjanya Komatineni }; 5364e0f1229SSowjanya Komatineni }; 5374e0f1229SSowjanya Komatineni sdmmc1_1v8_drv: sdmmc1-1v8-drv { 5384e0f1229SSowjanya Komatineni sdmmc1 { 5394e0f1229SSowjanya Komatineni nvidia,pins = "drive_sdmmc1"; 5404e0f1229SSowjanya Komatineni nvidia,pull-down-strength = <0x4>; 5414e0f1229SSowjanya Komatineni nvidia,pull-up-strength = <0x3>; 5424e0f1229SSowjanya Komatineni }; 5434e0f1229SSowjanya Komatineni }; 5444e0f1229SSowjanya Komatineni sdmmc2_1v8_drv: sdmmc2-1v8-drv { 5454e0f1229SSowjanya Komatineni sdmmc2 { 5464e0f1229SSowjanya Komatineni nvidia,pins = "drive_sdmmc2"; 5474e0f1229SSowjanya Komatineni nvidia,pull-down-strength = <0x10>; 5484e0f1229SSowjanya Komatineni nvidia,pull-up-strength = <0x10>; 5494e0f1229SSowjanya Komatineni }; 5504e0f1229SSowjanya Komatineni }; 5514e0f1229SSowjanya Komatineni sdmmc3_3v3_drv: sdmmc3-3v3-drv { 5524e0f1229SSowjanya Komatineni sdmmc3 { 5534e0f1229SSowjanya Komatineni nvidia,pins = "drive_sdmmc3"; 5544e0f1229SSowjanya Komatineni nvidia,pull-down-strength = <0x8>; 5554e0f1229SSowjanya Komatineni nvidia,pull-up-strength = <0x8>; 5564e0f1229SSowjanya Komatineni }; 5574e0f1229SSowjanya Komatineni }; 5584e0f1229SSowjanya Komatineni sdmmc3_1v8_drv: sdmmc3-1v8-drv { 5594e0f1229SSowjanya Komatineni sdmmc3 { 5604e0f1229SSowjanya Komatineni nvidia,pins = "drive_sdmmc3"; 5614e0f1229SSowjanya Komatineni nvidia,pull-down-strength = <0x4>; 5624e0f1229SSowjanya Komatineni nvidia,pull-up-strength = <0x3>; 5634e0f1229SSowjanya Komatineni }; 5644e0f1229SSowjanya Komatineni }; 5654e0f1229SSowjanya Komatineni sdmmc4_1v8_drv: sdmmc4-1v8-drv { 5664e0f1229SSowjanya Komatineni sdmmc4 { 5674e0f1229SSowjanya Komatineni nvidia,pins = "drive_sdmmc4"; 5684e0f1229SSowjanya Komatineni nvidia,pull-down-strength = <0x10>; 5694e0f1229SSowjanya Komatineni nvidia,pull-up-strength = <0x10>; 5704e0f1229SSowjanya Komatineni }; 5714e0f1229SSowjanya Komatineni }; 572742af7e7SThierry Reding }; 573742af7e7SThierry Reding 574742af7e7SThierry Reding /* 575742af7e7SThierry Reding * There are two serial driver i.e. 8250 based simple serial 576742af7e7SThierry Reding * driver and APB DMA based serial driver for higher baudrate 577ef769e32SAdam Buchbinder * and performance. To enable the 8250 based driver, the compatible 578742af7e7SThierry Reding * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable 57968cd8b2eSThierry Reding * the APB DMA based serial driver, the compatible is 580742af7e7SThierry Reding * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". 581742af7e7SThierry Reding */ 582be70771dSThierry Reding uarta: serial@70006000 { 583742af7e7SThierry Reding compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 584742af7e7SThierry Reding reg = <0x0 0x70006000 0x0 0x40>; 585742af7e7SThierry Reding reg-shift = <2>; 586742af7e7SThierry Reding interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 587742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_UARTA>; 588742af7e7SThierry Reding clock-names = "serial"; 589742af7e7SThierry Reding resets = <&tegra_car 6>; 590742af7e7SThierry Reding reset-names = "serial"; 591742af7e7SThierry Reding dmas = <&apbdma 8>, <&apbdma 8>; 592742af7e7SThierry Reding dma-names = "rx", "tx"; 593742af7e7SThierry Reding status = "disabled"; 594742af7e7SThierry Reding }; 595742af7e7SThierry Reding 596be70771dSThierry Reding uartb: serial@70006040 { 597742af7e7SThierry Reding compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 598742af7e7SThierry Reding reg = <0x0 0x70006040 0x0 0x40>; 599742af7e7SThierry Reding reg-shift = <2>; 600742af7e7SThierry Reding interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 601742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_UARTB>; 602742af7e7SThierry Reding clock-names = "serial"; 603742af7e7SThierry Reding resets = <&tegra_car 7>; 604742af7e7SThierry Reding reset-names = "serial"; 605742af7e7SThierry Reding dmas = <&apbdma 9>, <&apbdma 9>; 606742af7e7SThierry Reding dma-names = "rx", "tx"; 607742af7e7SThierry Reding status = "disabled"; 608742af7e7SThierry Reding }; 609742af7e7SThierry Reding 610be70771dSThierry Reding uartc: serial@70006200 { 611742af7e7SThierry Reding compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 612742af7e7SThierry Reding reg = <0x0 0x70006200 0x0 0x40>; 613742af7e7SThierry Reding reg-shift = <2>; 614742af7e7SThierry Reding interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 615742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_UARTC>; 616742af7e7SThierry Reding clock-names = "serial"; 617742af7e7SThierry Reding resets = <&tegra_car 55>; 618742af7e7SThierry Reding reset-names = "serial"; 619742af7e7SThierry Reding dmas = <&apbdma 10>, <&apbdma 10>; 620742af7e7SThierry Reding dma-names = "rx", "tx"; 621742af7e7SThierry Reding status = "disabled"; 622742af7e7SThierry Reding }; 623742af7e7SThierry Reding 624be70771dSThierry Reding uartd: serial@70006300 { 625742af7e7SThierry Reding compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 626742af7e7SThierry Reding reg = <0x0 0x70006300 0x0 0x40>; 627742af7e7SThierry Reding reg-shift = <2>; 628742af7e7SThierry Reding interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 629742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_UARTD>; 630742af7e7SThierry Reding clock-names = "serial"; 631742af7e7SThierry Reding resets = <&tegra_car 65>; 632742af7e7SThierry Reding reset-names = "serial"; 633742af7e7SThierry Reding dmas = <&apbdma 19>, <&apbdma 19>; 634742af7e7SThierry Reding dma-names = "rx", "tx"; 635742af7e7SThierry Reding status = "disabled"; 636742af7e7SThierry Reding }; 637742af7e7SThierry Reding 638be70771dSThierry Reding pwm: pwm@7000a000 { 639742af7e7SThierry Reding compatible = "nvidia,tegra210-pwm", "nvidia,tegra20-pwm"; 640742af7e7SThierry Reding reg = <0x0 0x7000a000 0x0 0x100>; 641742af7e7SThierry Reding #pwm-cells = <2>; 642742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_PWM>; 643742af7e7SThierry Reding clock-names = "pwm"; 644742af7e7SThierry Reding resets = <&tegra_car 17>; 645742af7e7SThierry Reding reset-names = "pwm"; 646742af7e7SThierry Reding status = "disabled"; 647742af7e7SThierry Reding }; 648742af7e7SThierry Reding 649be70771dSThierry Reding i2c@7000c000 { 650140723b9SSowjanya Komatineni compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 651742af7e7SThierry Reding reg = <0x0 0x7000c000 0x0 0x100>; 652742af7e7SThierry Reding interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 653742af7e7SThierry Reding #address-cells = <1>; 654742af7e7SThierry Reding #size-cells = <0>; 655742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_I2C1>; 656742af7e7SThierry Reding clock-names = "div-clk"; 657742af7e7SThierry Reding resets = <&tegra_car 12>; 658742af7e7SThierry Reding reset-names = "i2c"; 659742af7e7SThierry Reding dmas = <&apbdma 21>, <&apbdma 21>; 660742af7e7SThierry Reding dma-names = "rx", "tx"; 661742af7e7SThierry Reding status = "disabled"; 662742af7e7SThierry Reding }; 663742af7e7SThierry Reding 664be70771dSThierry Reding i2c@7000c400 { 665140723b9SSowjanya Komatineni compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 666742af7e7SThierry Reding reg = <0x0 0x7000c400 0x0 0x100>; 667742af7e7SThierry Reding interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 668742af7e7SThierry Reding #address-cells = <1>; 669742af7e7SThierry Reding #size-cells = <0>; 670742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_I2C2>; 671742af7e7SThierry Reding clock-names = "div-clk"; 672742af7e7SThierry Reding resets = <&tegra_car 54>; 673742af7e7SThierry Reding reset-names = "i2c"; 674742af7e7SThierry Reding dmas = <&apbdma 22>, <&apbdma 22>; 675742af7e7SThierry Reding dma-names = "rx", "tx"; 676742af7e7SThierry Reding status = "disabled"; 677742af7e7SThierry Reding }; 678742af7e7SThierry Reding 679be70771dSThierry Reding i2c@7000c500 { 680140723b9SSowjanya Komatineni compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 681742af7e7SThierry Reding reg = <0x0 0x7000c500 0x0 0x100>; 682742af7e7SThierry Reding interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 683742af7e7SThierry Reding #address-cells = <1>; 684742af7e7SThierry Reding #size-cells = <0>; 685742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_I2C3>; 686742af7e7SThierry Reding clock-names = "div-clk"; 687742af7e7SThierry Reding resets = <&tegra_car 67>; 688742af7e7SThierry Reding reset-names = "i2c"; 689742af7e7SThierry Reding dmas = <&apbdma 23>, <&apbdma 23>; 690742af7e7SThierry Reding dma-names = "rx", "tx"; 691742af7e7SThierry Reding status = "disabled"; 692742af7e7SThierry Reding }; 693742af7e7SThierry Reding 694be70771dSThierry Reding i2c@7000c700 { 695140723b9SSowjanya Komatineni compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 696742af7e7SThierry Reding reg = <0x0 0x7000c700 0x0 0x100>; 697742af7e7SThierry Reding interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 698742af7e7SThierry Reding #address-cells = <1>; 699742af7e7SThierry Reding #size-cells = <0>; 700742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_I2C4>; 701742af7e7SThierry Reding clock-names = "div-clk"; 702742af7e7SThierry Reding resets = <&tegra_car 103>; 703742af7e7SThierry Reding reset-names = "i2c"; 704742af7e7SThierry Reding dmas = <&apbdma 26>, <&apbdma 26>; 705742af7e7SThierry Reding dma-names = "rx", "tx"; 70666b2d6e9SJon Hunter pinctrl-0 = <&state_dpaux1_i2c>; 70766b2d6e9SJon Hunter pinctrl-1 = <&state_dpaux1_off>; 70866b2d6e9SJon Hunter pinctrl-names = "default", "idle"; 709742af7e7SThierry Reding status = "disabled"; 710742af7e7SThierry Reding }; 711742af7e7SThierry Reding 712be70771dSThierry Reding i2c@7000d000 { 713140723b9SSowjanya Komatineni compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 714742af7e7SThierry Reding reg = <0x0 0x7000d000 0x0 0x100>; 715742af7e7SThierry Reding interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 716742af7e7SThierry Reding #address-cells = <1>; 717742af7e7SThierry Reding #size-cells = <0>; 718742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_I2C5>; 719742af7e7SThierry Reding clock-names = "div-clk"; 720742af7e7SThierry Reding resets = <&tegra_car 47>; 721742af7e7SThierry Reding reset-names = "i2c"; 722742af7e7SThierry Reding dmas = <&apbdma 24>, <&apbdma 24>; 723742af7e7SThierry Reding dma-names = "rx", "tx"; 724742af7e7SThierry Reding status = "disabled"; 725742af7e7SThierry Reding }; 726742af7e7SThierry Reding 727be70771dSThierry Reding i2c@7000d100 { 728140723b9SSowjanya Komatineni compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 729742af7e7SThierry Reding reg = <0x0 0x7000d100 0x0 0x100>; 730742af7e7SThierry Reding interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 731742af7e7SThierry Reding #address-cells = <1>; 732742af7e7SThierry Reding #size-cells = <0>; 733742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_I2C6>; 734742af7e7SThierry Reding clock-names = "div-clk"; 735742af7e7SThierry Reding resets = <&tegra_car 166>; 736742af7e7SThierry Reding reset-names = "i2c"; 737742af7e7SThierry Reding dmas = <&apbdma 30>, <&apbdma 30>; 738742af7e7SThierry Reding dma-names = "rx", "tx"; 73966b2d6e9SJon Hunter pinctrl-0 = <&state_dpaux_i2c>; 74066b2d6e9SJon Hunter pinctrl-1 = <&state_dpaux_off>; 74166b2d6e9SJon Hunter pinctrl-names = "default", "idle"; 742742af7e7SThierry Reding status = "disabled"; 743742af7e7SThierry Reding }; 744742af7e7SThierry Reding 745be70771dSThierry Reding spi@7000d400 { 746742af7e7SThierry Reding compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 747742af7e7SThierry Reding reg = <0x0 0x7000d400 0x0 0x200>; 748742af7e7SThierry Reding interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 749742af7e7SThierry Reding #address-cells = <1>; 750742af7e7SThierry Reding #size-cells = <0>; 751742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_SBC1>; 752742af7e7SThierry Reding clock-names = "spi"; 753742af7e7SThierry Reding resets = <&tegra_car 41>; 754742af7e7SThierry Reding reset-names = "spi"; 755742af7e7SThierry Reding dmas = <&apbdma 15>, <&apbdma 15>; 756742af7e7SThierry Reding dma-names = "rx", "tx"; 757742af7e7SThierry Reding status = "disabled"; 758742af7e7SThierry Reding }; 759742af7e7SThierry Reding 760be70771dSThierry Reding spi@7000d600 { 761742af7e7SThierry Reding compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 762742af7e7SThierry Reding reg = <0x0 0x7000d600 0x0 0x200>; 763742af7e7SThierry Reding interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 764742af7e7SThierry Reding #address-cells = <1>; 765742af7e7SThierry Reding #size-cells = <0>; 766742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_SBC2>; 767742af7e7SThierry Reding clock-names = "spi"; 768742af7e7SThierry Reding resets = <&tegra_car 44>; 769742af7e7SThierry Reding reset-names = "spi"; 770742af7e7SThierry Reding dmas = <&apbdma 16>, <&apbdma 16>; 771742af7e7SThierry Reding dma-names = "rx", "tx"; 772742af7e7SThierry Reding status = "disabled"; 773742af7e7SThierry Reding }; 774742af7e7SThierry Reding 775be70771dSThierry Reding spi@7000d800 { 776742af7e7SThierry Reding compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 777742af7e7SThierry Reding reg = <0x0 0x7000d800 0x0 0x200>; 778742af7e7SThierry Reding interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 779742af7e7SThierry Reding #address-cells = <1>; 780742af7e7SThierry Reding #size-cells = <0>; 781742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_SBC3>; 782742af7e7SThierry Reding clock-names = "spi"; 783742af7e7SThierry Reding resets = <&tegra_car 46>; 784742af7e7SThierry Reding reset-names = "spi"; 785742af7e7SThierry Reding dmas = <&apbdma 17>, <&apbdma 17>; 786742af7e7SThierry Reding dma-names = "rx", "tx"; 787742af7e7SThierry Reding status = "disabled"; 788742af7e7SThierry Reding }; 789742af7e7SThierry Reding 790be70771dSThierry Reding spi@7000da00 { 791742af7e7SThierry Reding compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 792742af7e7SThierry Reding reg = <0x0 0x7000da00 0x0 0x200>; 793742af7e7SThierry Reding interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 794742af7e7SThierry Reding #address-cells = <1>; 795742af7e7SThierry Reding #size-cells = <0>; 796742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_SBC4>; 797742af7e7SThierry Reding clock-names = "spi"; 798742af7e7SThierry Reding resets = <&tegra_car 68>; 799742af7e7SThierry Reding reset-names = "spi"; 800742af7e7SThierry Reding dmas = <&apbdma 18>, <&apbdma 18>; 801742af7e7SThierry Reding dma-names = "rx", "tx"; 802742af7e7SThierry Reding status = "disabled"; 803742af7e7SThierry Reding }; 804742af7e7SThierry Reding 805be70771dSThierry Reding rtc@7000e000 { 806742af7e7SThierry Reding compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc"; 807742af7e7SThierry Reding reg = <0x0 0x7000e000 0x0 0x100>; 808d13c13f4SSowjanya Komatineni interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; 809359ae651SSowjanya Komatineni interrupt-parent = <&tegra_pmc>; 810742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_RTC>; 811742af7e7SThierry Reding clock-names = "rtc"; 812742af7e7SThierry Reding }; 813742af7e7SThierry Reding 814359ae651SSowjanya Komatineni tegra_pmc: pmc@7000e400 { 815742af7e7SThierry Reding compatible = "nvidia,tegra210-pmc"; 816742af7e7SThierry Reding reg = <0x0 0x7000e400 0x0 0x400>; 817742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; 818742af7e7SThierry Reding clock-names = "pclk", "clk32k_in"; 819359ae651SSowjanya Komatineni #clock-cells = <1>; 820d13c13f4SSowjanya Komatineni #interrupt-cells = <2>; 821d13c13f4SSowjanya Komatineni interrupt-controller; 822c2b82445SJon Hunter 823c2b82445SJon Hunter powergates { 824c2b82445SJon Hunter pd_audio: aud { 825c2b82445SJon Hunter clocks = <&tegra_car TEGRA210_CLK_APE>, 826c2b82445SJon Hunter <&tegra_car TEGRA210_CLK_APB2APE>; 827c2b82445SJon Hunter resets = <&tegra_car 198>; 828c2b82445SJon Hunter #power-domain-cells = <0>; 829c2b82445SJon Hunter }; 830241f02baSJon Hunter 83196d1f078SJon Hunter pd_sor: sor { 83296d1f078SJon Hunter clocks = <&tegra_car TEGRA210_CLK_SOR0>, 83396d1f078SJon Hunter <&tegra_car TEGRA210_CLK_SOR1>, 834b4f99176SSowjanya Komatineni <&tegra_car TEGRA210_CLK_CILAB>, 835b4f99176SSowjanya Komatineni <&tegra_car TEGRA210_CLK_CILCD>, 836b4f99176SSowjanya Komatineni <&tegra_car TEGRA210_CLK_CILE>, 83796d1f078SJon Hunter <&tegra_car TEGRA210_CLK_DSIA>, 83896d1f078SJon Hunter <&tegra_car TEGRA210_CLK_DSIB>, 83996d1f078SJon Hunter <&tegra_car TEGRA210_CLK_DPAUX>, 84096d1f078SJon Hunter <&tegra_car TEGRA210_CLK_DPAUX1>, 84196d1f078SJon Hunter <&tegra_car TEGRA210_CLK_MIPI_CAL>; 84296d1f078SJon Hunter resets = <&tegra_car TEGRA210_CLK_SOR0>, 84396d1f078SJon Hunter <&tegra_car TEGRA210_CLK_SOR1>, 84496d1f078SJon Hunter <&tegra_car TEGRA210_CLK_DSIA>, 84596d1f078SJon Hunter <&tegra_car TEGRA210_CLK_DSIB>, 84696d1f078SJon Hunter <&tegra_car TEGRA210_CLK_DPAUX>, 84796d1f078SJon Hunter <&tegra_car TEGRA210_CLK_DPAUX1>, 84896d1f078SJon Hunter <&tegra_car TEGRA210_CLK_MIPI_CAL>; 84996d1f078SJon Hunter #power-domain-cells = <0>; 85096d1f078SJon Hunter }; 85196d1f078SJon Hunter 852241f02baSJon Hunter pd_xusbss: xusba { 853241f02baSJon Hunter clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>; 854241f02baSJon Hunter resets = <&tegra_car TEGRA210_CLK_XUSB_SS>; 855241f02baSJon Hunter #power-domain-cells = <0>; 856241f02baSJon Hunter }; 857241f02baSJon Hunter 858241f02baSJon Hunter pd_xusbdev: xusbb { 859241f02baSJon Hunter clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>; 860241f02baSJon Hunter resets = <&tegra_car 95>; 861241f02baSJon Hunter #power-domain-cells = <0>; 862241f02baSJon Hunter }; 863241f02baSJon Hunter 864241f02baSJon Hunter pd_xusbhost: xusbc { 865241f02baSJon Hunter clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>; 866241f02baSJon Hunter resets = <&tegra_car TEGRA210_CLK_XUSB_HOST>; 867241f02baSJon Hunter #power-domain-cells = <0>; 868241f02baSJon Hunter }; 86924963d1bSMikko Perttunen 87024963d1bSMikko Perttunen pd_vic: vic { 87124963d1bSMikko Perttunen clocks = <&tegra_car TEGRA210_CLK_VIC03>; 87224963d1bSMikko Perttunen clock-names = "vic"; 87324963d1bSMikko Perttunen resets = <&tegra_car 178>; 87424963d1bSMikko Perttunen reset-names = "vic"; 87524963d1bSMikko Perttunen #power-domain-cells = <0>; 87624963d1bSMikko Perttunen }; 877c4153885SSowjanya Komatineni 878c4153885SSowjanya Komatineni pd_venc: venc { 879c4153885SSowjanya Komatineni clocks = <&tegra_car TEGRA210_CLK_VI>, 880c4153885SSowjanya Komatineni <&tegra_car TEGRA210_CLK_CSI>; 881c4153885SSowjanya Komatineni resets = <&mc TEGRA210_MC_RESET_VI>, 882c4153885SSowjanya Komatineni <&tegra_car 20>, 883c4153885SSowjanya Komatineni <&tegra_car 52>; 884c4153885SSowjanya Komatineni #power-domain-cells = <0>; 885c4153885SSowjanya Komatineni }; 886c2b82445SJon Hunter }; 8876641af7eSAapo Vienamo 8886641af7eSAapo Vienamo sdmmc1_3v3: sdmmc1-3v3 { 8896641af7eSAapo Vienamo pins = "sdmmc1"; 8906641af7eSAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 8916641af7eSAapo Vienamo }; 8926641af7eSAapo Vienamo 8936641af7eSAapo Vienamo sdmmc1_1v8: sdmmc1-1v8 { 8946641af7eSAapo Vienamo pins = "sdmmc1"; 8956641af7eSAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 8966641af7eSAapo Vienamo }; 8976641af7eSAapo Vienamo 8986641af7eSAapo Vienamo sdmmc3_3v3: sdmmc3-3v3 { 8996641af7eSAapo Vienamo pins = "sdmmc3"; 9006641af7eSAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 9016641af7eSAapo Vienamo }; 9026641af7eSAapo Vienamo 9036641af7eSAapo Vienamo sdmmc3_1v8: sdmmc3-1v8 { 9046641af7eSAapo Vienamo pins = "sdmmc3"; 9056641af7eSAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 9066641af7eSAapo Vienamo }; 907871be845SManikanta Maddireddy 908871be845SManikanta Maddireddy pex_dpd_disable: pex_en { 909871be845SManikanta Maddireddy pex-dpd-disable { 910871be845SManikanta Maddireddy pins = "pex-bias", "pex-clk1", "pex-clk2"; 911871be845SManikanta Maddireddy low-power-disable; 912871be845SManikanta Maddireddy }; 913871be845SManikanta Maddireddy }; 914871be845SManikanta Maddireddy 915871be845SManikanta Maddireddy pex_dpd_enable: pex_dis { 916871be845SManikanta Maddireddy pex-dpd-enable { 917871be845SManikanta Maddireddy pins = "pex-bias", "pex-clk1", "pex-clk2"; 918871be845SManikanta Maddireddy low-power-enable; 919871be845SManikanta Maddireddy }; 920871be845SManikanta Maddireddy }; 921742af7e7SThierry Reding }; 922742af7e7SThierry Reding 923be70771dSThierry Reding fuse@7000f800 { 924742af7e7SThierry Reding compatible = "nvidia,tegra210-efuse"; 925742af7e7SThierry Reding reg = <0x0 0x7000f800 0x0 0x400>; 926742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_FUSE>; 927742af7e7SThierry Reding clock-names = "fuse"; 928742af7e7SThierry Reding resets = <&tegra_car 39>; 929742af7e7SThierry Reding reset-names = "fuse"; 930742af7e7SThierry Reding }; 931742af7e7SThierry Reding 932be70771dSThierry Reding mc: memory-controller@70019000 { 933742af7e7SThierry Reding compatible = "nvidia,tegra210-mc"; 934742af7e7SThierry Reding reg = <0x0 0x70019000 0x0 0x1000>; 935742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_MC>; 936742af7e7SThierry Reding clock-names = "mc"; 937742af7e7SThierry Reding 938742af7e7SThierry Reding interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 939742af7e7SThierry Reding 940742af7e7SThierry Reding #iommu-cells = <1>; 9412eb8e1a4SSowjanya Komatineni #reset-cells = <1>; 942742af7e7SThierry Reding }; 943742af7e7SThierry Reding 944e12325f6SThierry Reding emc: external-memory-controller@7001b000 { 945cd9350c5SJoseph Lo compatible = "nvidia,tegra210-emc"; 946cd9350c5SJoseph Lo reg = <0x0 0x7001b000 0x0 0x1000>, 947cd9350c5SJoseph Lo <0x0 0x7001e000 0x0 0x1000>, 948cd9350c5SJoseph Lo <0x0 0x7001f000 0x0 0x1000>; 949cd9350c5SJoseph Lo clocks = <&tegra_car TEGRA210_CLK_EMC>; 950cd9350c5SJoseph Lo clock-names = "emc"; 951cd9350c5SJoseph Lo interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 952cd9350c5SJoseph Lo nvidia,memory-controller = <&mc>; 953e12325f6SThierry Reding #cooling-cells = <2>; 954cd9350c5SJoseph Lo }; 955cd9350c5SJoseph Lo 9566cb60ec4SPreetham Ramchandra sata@70020000 { 9576cb60ec4SPreetham Ramchandra compatible = "nvidia,tegra210-ahci"; 9586cb60ec4SPreetham Ramchandra reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */ 9596cb60ec4SPreetham Ramchandra <0x0 0x70020000 0x0 0x7000>, /* SATA */ 9606cb60ec4SPreetham Ramchandra <0x0 0x70001100 0x0 0x1000>; /* SATA AUX */ 9616cb60ec4SPreetham Ramchandra interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 9626cb60ec4SPreetham Ramchandra clocks = <&tegra_car TEGRA210_CLK_SATA>, 9636cb60ec4SPreetham Ramchandra <&tegra_car TEGRA210_CLK_SATA_OOB>; 9646cb60ec4SPreetham Ramchandra clock-names = "sata", "sata-oob"; 9656cb60ec4SPreetham Ramchandra resets = <&tegra_car 124>, 9666cb60ec4SPreetham Ramchandra <&tegra_car 123>, 9676cb60ec4SPreetham Ramchandra <&tegra_car 129>; 9686cb60ec4SPreetham Ramchandra reset-names = "sata", "sata-oob", "sata-cold"; 9696cb60ec4SPreetham Ramchandra status = "disabled"; 9706cb60ec4SPreetham Ramchandra }; 9716cb60ec4SPreetham Ramchandra 972be70771dSThierry Reding hda@70030000 { 973742af7e7SThierry Reding compatible = "nvidia,tegra210-hda", "nvidia,tegra30-hda"; 974742af7e7SThierry Reding reg = <0x0 0x70030000 0x0 0x10000>; 975742af7e7SThierry Reding interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 976742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_HDA>, 977742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_HDA2HDMI>, 978742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_HDA2CODEC_2X>; 979742af7e7SThierry Reding clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 980742af7e7SThierry Reding resets = <&tegra_car 125>, /* hda */ 981742af7e7SThierry Reding <&tegra_car 128>, /* hda2hdmi */ 982742af7e7SThierry Reding <&tegra_car 111>; /* hda2codec_2x */ 983742af7e7SThierry Reding reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 984742af7e7SThierry Reding status = "disabled"; 985742af7e7SThierry Reding }; 986742af7e7SThierry Reding 987e7a99ac2SThierry Reding usb@70090000 { 988e7a99ac2SThierry Reding compatible = "nvidia,tegra210-xusb"; 989e7a99ac2SThierry Reding reg = <0x0 0x70090000 0x0 0x8000>, 990e7a99ac2SThierry Reding <0x0 0x70098000 0x0 0x1000>, 991e7a99ac2SThierry Reding <0x0 0x70099000 0x0 0x1000>; 992e7a99ac2SThierry Reding reg-names = "hcd", "fpci", "ipfs"; 993e7a99ac2SThierry Reding 994e7a99ac2SThierry Reding interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 9959168e1dbSJon Hunter <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 996e7a99ac2SThierry Reding 997e7a99ac2SThierry Reding clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>, 998e7a99ac2SThierry Reding <&tegra_car TEGRA210_CLK_XUSB_HOST_SRC>, 999e7a99ac2SThierry Reding <&tegra_car TEGRA210_CLK_XUSB_FALCON_SRC>, 1000e7a99ac2SThierry Reding <&tegra_car TEGRA210_CLK_XUSB_SS>, 1001e7a99ac2SThierry Reding <&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>, 1002e7a99ac2SThierry Reding <&tegra_car TEGRA210_CLK_XUSB_SS_SRC>, 1003e7a99ac2SThierry Reding <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>, 1004e7a99ac2SThierry Reding <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>, 1005e7a99ac2SThierry Reding <&tegra_car TEGRA210_CLK_PLL_U_480M>, 1006e7a99ac2SThierry Reding <&tegra_car TEGRA210_CLK_CLK_M>, 1007e7a99ac2SThierry Reding <&tegra_car TEGRA210_CLK_PLL_E>; 1008e7a99ac2SThierry Reding clock-names = "xusb_host", "xusb_host_src", 1009e7a99ac2SThierry Reding "xusb_falcon_src", "xusb_ss", 1010e7a99ac2SThierry Reding "xusb_ss_div2", "xusb_ss_src", 1011e7a99ac2SThierry Reding "xusb_hs_src", "xusb_fs_src", 1012e7a99ac2SThierry Reding "pll_u_480m", "clk_m", "pll_e"; 1013e7a99ac2SThierry Reding resets = <&tegra_car 89>, <&tegra_car 156>, 1014e7a99ac2SThierry Reding <&tegra_car 143>; 1015e7a99ac2SThierry Reding reset-names = "xusb_host", "xusb_ss", "xusb_src"; 101636ec29f7SJon Hunter power-domains = <&pd_xusbhost>, <&pd_xusbss>; 101736ec29f7SJon Hunter power-domain-names = "xusb_host", "xusb_ss"; 1018e7a99ac2SThierry Reding 1019e7a99ac2SThierry Reding nvidia,xusb-padctl = <&padctl>; 1020e7a99ac2SThierry Reding 1021e7a99ac2SThierry Reding status = "disabled"; 1022e7a99ac2SThierry Reding }; 1023e7a99ac2SThierry Reding 10244e07ac90SThierry Reding padctl: padctl@7009f000 { 10254e07ac90SThierry Reding compatible = "nvidia,tegra210-xusb-padctl"; 10264e07ac90SThierry Reding reg = <0x0 0x7009f000 0x0 0x1000>; 10274e07ac90SThierry Reding resets = <&tegra_car 142>; 10284e07ac90SThierry Reding reset-names = "padctl"; 10294e07ac90SThierry Reding 10304e07ac90SThierry Reding status = "disabled"; 10314e07ac90SThierry Reding 10324e07ac90SThierry Reding pads { 10334e07ac90SThierry Reding usb2 { 10344e07ac90SThierry Reding clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>; 10354e07ac90SThierry Reding clock-names = "trk"; 10364e07ac90SThierry Reding status = "disabled"; 10374e07ac90SThierry Reding 10384e07ac90SThierry Reding lanes { 10394e07ac90SThierry Reding usb2-0 { 10404e07ac90SThierry Reding status = "disabled"; 10414e07ac90SThierry Reding #phy-cells = <0>; 10424e07ac90SThierry Reding }; 10434e07ac90SThierry Reding 10444e07ac90SThierry Reding usb2-1 { 10454e07ac90SThierry Reding status = "disabled"; 10464e07ac90SThierry Reding #phy-cells = <0>; 10474e07ac90SThierry Reding }; 10484e07ac90SThierry Reding 10494e07ac90SThierry Reding usb2-2 { 10504e07ac90SThierry Reding status = "disabled"; 10514e07ac90SThierry Reding #phy-cells = <0>; 10524e07ac90SThierry Reding }; 10534e07ac90SThierry Reding 10544e07ac90SThierry Reding usb2-3 { 10554e07ac90SThierry Reding status = "disabled"; 10564e07ac90SThierry Reding #phy-cells = <0>; 10574e07ac90SThierry Reding }; 10584e07ac90SThierry Reding }; 10594e07ac90SThierry Reding }; 10604e07ac90SThierry Reding 10614e07ac90SThierry Reding hsic { 10624e07ac90SThierry Reding clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>; 10634e07ac90SThierry Reding clock-names = "trk"; 10644e07ac90SThierry Reding status = "disabled"; 10654e07ac90SThierry Reding 10664e07ac90SThierry Reding lanes { 10674e07ac90SThierry Reding hsic-0 { 10684e07ac90SThierry Reding status = "disabled"; 10694e07ac90SThierry Reding #phy-cells = <0>; 10704e07ac90SThierry Reding }; 10714e07ac90SThierry Reding 10724e07ac90SThierry Reding hsic-1 { 10734e07ac90SThierry Reding status = "disabled"; 10744e07ac90SThierry Reding #phy-cells = <0>; 10754e07ac90SThierry Reding }; 10764e07ac90SThierry Reding }; 10774e07ac90SThierry Reding }; 10784e07ac90SThierry Reding 10794e07ac90SThierry Reding pcie { 10804e07ac90SThierry Reding clocks = <&tegra_car TEGRA210_CLK_PLL_E>; 10814e07ac90SThierry Reding clock-names = "pll"; 10824e07ac90SThierry Reding resets = <&tegra_car 205>; 10834e07ac90SThierry Reding reset-names = "phy"; 10844e07ac90SThierry Reding status = "disabled"; 10854e07ac90SThierry Reding 10864e07ac90SThierry Reding lanes { 10874e07ac90SThierry Reding pcie-0 { 10884e07ac90SThierry Reding status = "disabled"; 10894e07ac90SThierry Reding #phy-cells = <0>; 10904e07ac90SThierry Reding }; 10914e07ac90SThierry Reding 10924e07ac90SThierry Reding pcie-1 { 10934e07ac90SThierry Reding status = "disabled"; 10944e07ac90SThierry Reding #phy-cells = <0>; 10954e07ac90SThierry Reding }; 10964e07ac90SThierry Reding 10974e07ac90SThierry Reding pcie-2 { 10984e07ac90SThierry Reding status = "disabled"; 10994e07ac90SThierry Reding #phy-cells = <0>; 11004e07ac90SThierry Reding }; 11014e07ac90SThierry Reding 11024e07ac90SThierry Reding pcie-3 { 11034e07ac90SThierry Reding status = "disabled"; 11044e07ac90SThierry Reding #phy-cells = <0>; 11054e07ac90SThierry Reding }; 11064e07ac90SThierry Reding 11074e07ac90SThierry Reding pcie-4 { 11084e07ac90SThierry Reding status = "disabled"; 11094e07ac90SThierry Reding #phy-cells = <0>; 11104e07ac90SThierry Reding }; 11114e07ac90SThierry Reding 11124e07ac90SThierry Reding pcie-5 { 11134e07ac90SThierry Reding status = "disabled"; 11144e07ac90SThierry Reding #phy-cells = <0>; 11154e07ac90SThierry Reding }; 11164e07ac90SThierry Reding 11174e07ac90SThierry Reding pcie-6 { 11184e07ac90SThierry Reding status = "disabled"; 11194e07ac90SThierry Reding #phy-cells = <0>; 11204e07ac90SThierry Reding }; 11214e07ac90SThierry Reding }; 11224e07ac90SThierry Reding }; 11234e07ac90SThierry Reding 11244e07ac90SThierry Reding sata { 11254e07ac90SThierry Reding clocks = <&tegra_car TEGRA210_CLK_PLL_E>; 11264e07ac90SThierry Reding clock-names = "pll"; 11274e07ac90SThierry Reding resets = <&tegra_car 204>; 11284e07ac90SThierry Reding reset-names = "phy"; 11294e07ac90SThierry Reding status = "disabled"; 11304e07ac90SThierry Reding 11314e07ac90SThierry Reding lanes { 11324e07ac90SThierry Reding sata-0 { 11334e07ac90SThierry Reding status = "disabled"; 11344e07ac90SThierry Reding #phy-cells = <0>; 11354e07ac90SThierry Reding }; 11364e07ac90SThierry Reding }; 11374e07ac90SThierry Reding }; 11384e07ac90SThierry Reding }; 11394e07ac90SThierry Reding 11404e07ac90SThierry Reding ports { 11414e07ac90SThierry Reding usb2-0 { 11424e07ac90SThierry Reding status = "disabled"; 11434e07ac90SThierry Reding }; 11444e07ac90SThierry Reding 11454e07ac90SThierry Reding usb2-1 { 11464e07ac90SThierry Reding status = "disabled"; 11474e07ac90SThierry Reding }; 11484e07ac90SThierry Reding 11494e07ac90SThierry Reding usb2-2 { 11504e07ac90SThierry Reding status = "disabled"; 11514e07ac90SThierry Reding }; 11524e07ac90SThierry Reding 11534e07ac90SThierry Reding usb2-3 { 11544e07ac90SThierry Reding status = "disabled"; 11554e07ac90SThierry Reding }; 11564e07ac90SThierry Reding 11574e07ac90SThierry Reding hsic-0 { 11584e07ac90SThierry Reding status = "disabled"; 11594e07ac90SThierry Reding }; 11604e07ac90SThierry Reding 11614e07ac90SThierry Reding usb3-0 { 11624e07ac90SThierry Reding status = "disabled"; 11634e07ac90SThierry Reding }; 11644e07ac90SThierry Reding 11654e07ac90SThierry Reding usb3-1 { 11664e07ac90SThierry Reding status = "disabled"; 11674e07ac90SThierry Reding }; 11684e07ac90SThierry Reding 11694e07ac90SThierry Reding usb3-2 { 11704e07ac90SThierry Reding status = "disabled"; 11714e07ac90SThierry Reding }; 11724e07ac90SThierry Reding 11734e07ac90SThierry Reding usb3-3 { 11744e07ac90SThierry Reding status = "disabled"; 11754e07ac90SThierry Reding }; 11764e07ac90SThierry Reding }; 11774e07ac90SThierry Reding }; 11784e07ac90SThierry Reding 1179be70771dSThierry Reding sdhci@700b0000 { 1180b3fa0e03SThierry Reding compatible = "nvidia,tegra210-sdhci"; 1181742af7e7SThierry Reding reg = <0x0 0x700b0000 0x0 0x200>; 1182742af7e7SThierry Reding interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1183742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_SDMMC1>; 1184742af7e7SThierry Reding clock-names = "sdhci"; 1185742af7e7SThierry Reding resets = <&tegra_car 14>; 1186742af7e7SThierry Reding reset-names = "sdhci"; 11874e0f1229SSowjanya Komatineni pinctrl-names = "sdmmc-3v3", "sdmmc-1v8", 11884e0f1229SSowjanya Komatineni "sdmmc-3v3-drv", "sdmmc-1v8-drv"; 11896641af7eSAapo Vienamo pinctrl-0 = <&sdmmc1_3v3>; 11906641af7eSAapo Vienamo pinctrl-1 = <&sdmmc1_1v8>; 11914e0f1229SSowjanya Komatineni pinctrl-2 = <&sdmmc1_3v3_drv>; 11924e0f1229SSowjanya Komatineni pinctrl-3 = <&sdmmc1_1v8_drv>; 11931ea06718SAapo Vienamo nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>; 11941ea06718SAapo Vienamo nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>; 11951ea06718SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>; 11961ea06718SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>; 119763af8bcdSAapo Vienamo nvidia,default-tap = <0x2>; 119863af8bcdSAapo Vienamo nvidia,default-trim = <0x4>; 1199918f9671SAapo Vienamo assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>, 1200918f9671SAapo Vienamo <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>, 1201918f9671SAapo Vienamo <&tegra_car TEGRA210_CLK_PLL_C4>; 1202918f9671SAapo Vienamo assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 1203918f9671SAapo Vienamo assigned-clock-rates = <200000000>, <1000000000>, <1000000000>; 1204742af7e7SThierry Reding status = "disabled"; 1205742af7e7SThierry Reding }; 1206742af7e7SThierry Reding 1207be70771dSThierry Reding sdhci@700b0200 { 1208b3fa0e03SThierry Reding compatible = "nvidia,tegra210-sdhci"; 1209742af7e7SThierry Reding reg = <0x0 0x700b0200 0x0 0x200>; 1210742af7e7SThierry Reding interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 1211742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_SDMMC2>; 1212742af7e7SThierry Reding clock-names = "sdhci"; 1213742af7e7SThierry Reding resets = <&tegra_car 9>; 1214742af7e7SThierry Reding reset-names = "sdhci"; 12154e0f1229SSowjanya Komatineni pinctrl-names = "sdmmc-1v8-drv"; 12164e0f1229SSowjanya Komatineni pinctrl-0 = <&sdmmc2_1v8_drv>; 12171ea06718SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>; 12181ea06718SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>; 121963af8bcdSAapo Vienamo nvidia,default-tap = <0x8>; 122063af8bcdSAapo Vienamo nvidia,default-trim = <0x0>; 1221742af7e7SThierry Reding status = "disabled"; 1222742af7e7SThierry Reding }; 1223742af7e7SThierry Reding 1224be70771dSThierry Reding sdhci@700b0400 { 1225b3fa0e03SThierry Reding compatible = "nvidia,tegra210-sdhci"; 1226742af7e7SThierry Reding reg = <0x0 0x700b0400 0x0 0x200>; 1227742af7e7SThierry Reding interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 1228742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_SDMMC3>; 1229742af7e7SThierry Reding clock-names = "sdhci"; 1230742af7e7SThierry Reding resets = <&tegra_car 69>; 1231742af7e7SThierry Reding reset-names = "sdhci"; 12324e0f1229SSowjanya Komatineni pinctrl-names = "sdmmc-3v3", "sdmmc-1v8", 12334e0f1229SSowjanya Komatineni "sdmmc-3v3-drv", "sdmmc-1v8-drv"; 12346641af7eSAapo Vienamo pinctrl-0 = <&sdmmc3_3v3>; 12356641af7eSAapo Vienamo pinctrl-1 = <&sdmmc3_1v8>; 12364e0f1229SSowjanya Komatineni pinctrl-2 = <&sdmmc3_3v3_drv>; 12374e0f1229SSowjanya Komatineni pinctrl-3 = <&sdmmc3_1v8_drv>; 12381ea06718SAapo Vienamo nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>; 12391ea06718SAapo Vienamo nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>; 12401ea06718SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>; 12411ea06718SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>; 124263af8bcdSAapo Vienamo nvidia,default-tap = <0x3>; 124363af8bcdSAapo Vienamo nvidia,default-trim = <0x3>; 1244742af7e7SThierry Reding status = "disabled"; 1245742af7e7SThierry Reding }; 1246742af7e7SThierry Reding 1247be70771dSThierry Reding sdhci@700b0600 { 1248b3fa0e03SThierry Reding compatible = "nvidia,tegra210-sdhci"; 1249742af7e7SThierry Reding reg = <0x0 0x700b0600 0x0 0x200>; 1250742af7e7SThierry Reding interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1251742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_SDMMC4>; 1252742af7e7SThierry Reding clock-names = "sdhci"; 1253742af7e7SThierry Reding resets = <&tegra_car 15>; 1254742af7e7SThierry Reding reset-names = "sdhci"; 12554e0f1229SSowjanya Komatineni pinctrl-names = "sdmmc-3v3-drv", "sdmmc-1v8-drv"; 12564e0f1229SSowjanya Komatineni pinctrl-0 = <&sdmmc4_1v8_drv>; 12574e0f1229SSowjanya Komatineni pinctrl-1 = <&sdmmc4_1v8_drv>; 12581ea06718SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>; 12591ea06718SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>; 126063af8bcdSAapo Vienamo nvidia,default-tap = <0x8>; 126163af8bcdSAapo Vienamo nvidia,default-trim = <0x0>; 1262918f9671SAapo Vienamo assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>, 1263918f9671SAapo Vienamo <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 1264918f9671SAapo Vienamo assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 12655879600aSAapo Vienamo nvidia,dqs-trim = <40>; 1266d5d6b468SAapo Vienamo mmc-hs400-1_8v; 1267742af7e7SThierry Reding status = "disabled"; 1268742af7e7SThierry Reding }; 1269742af7e7SThierry Reding 1270e74db5a5SNagarjuna Kristam usb@700d0000 { 1271e74db5a5SNagarjuna Kristam compatible = "nvidia,tegra210-xudc"; 1272e74db5a5SNagarjuna Kristam reg = <0x0 0x700d0000 0x0 0x8000>, 1273e74db5a5SNagarjuna Kristam <0x0 0x700d8000 0x0 0x1000>, 1274e74db5a5SNagarjuna Kristam <0x0 0x700d9000 0x0 0x1000>; 1275e74db5a5SNagarjuna Kristam reg-names = "base", "fpci", "ipfs"; 1276e74db5a5SNagarjuna Kristam interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1277e74db5a5SNagarjuna Kristam clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>, 1278e74db5a5SNagarjuna Kristam <&tegra_car TEGRA210_CLK_XUSB_SS>, 1279e74db5a5SNagarjuna Kristam <&tegra_car TEGRA210_CLK_XUSB_SSP_SRC>, 1280e74db5a5SNagarjuna Kristam <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>, 1281e74db5a5SNagarjuna Kristam <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>; 1282e74db5a5SNagarjuna Kristam clock-names = "dev", "ss", "ss_src", "fs_src", "hs_src"; 1283e74db5a5SNagarjuna Kristam power-domains = <&pd_xusbdev>, <&pd_xusbss>; 1284e74db5a5SNagarjuna Kristam power-domain-names = "dev", "ss"; 1285e74db5a5SNagarjuna Kristam nvidia,xusb-padctl = <&padctl>; 1286e74db5a5SNagarjuna Kristam status = "disabled"; 1287e74db5a5SNagarjuna Kristam }; 1288e74db5a5SNagarjuna Kristam 1289be70771dSThierry Reding mipi: mipi@700e3000 { 1290742af7e7SThierry Reding compatible = "nvidia,tegra210-mipi"; 1291742af7e7SThierry Reding reg = <0x0 0x700e3000 0x0 0x100>; 1292742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_MIPI_CAL>; 1293742af7e7SThierry Reding clock-names = "mipi-cal"; 129496d1f078SJon Hunter power-domains = <&pd_sor>; 1295742af7e7SThierry Reding #nvidia,mipi-calibrate-cells = <1>; 1296742af7e7SThierry Reding }; 1297742af7e7SThierry Reding 12982ceed593SJoseph Lo dfll: clock@70110000 { 12992ceed593SJoseph Lo compatible = "nvidia,tegra210-dfll"; 13002ceed593SJoseph Lo reg = <0 0x70110000 0 0x100>, /* DFLL control */ 13012ceed593SJoseph Lo <0 0x70110000 0 0x100>, /* I2C output control */ 13022ceed593SJoseph Lo <0 0x70110100 0 0x100>, /* Integrated I2C controller */ 13032ceed593SJoseph Lo <0 0x70110200 0 0x100>; /* Look-up table RAM */ 13042ceed593SJoseph Lo interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 13052ceed593SJoseph Lo clocks = <&tegra_car TEGRA210_CLK_DFLL_SOC>, 13062ceed593SJoseph Lo <&tegra_car TEGRA210_CLK_DFLL_REF>, 13072ceed593SJoseph Lo <&tegra_car TEGRA210_CLK_I2C5>; 13082ceed593SJoseph Lo clock-names = "soc", "ref", "i2c"; 13092ceed593SJoseph Lo resets = <&tegra_car TEGRA210_RST_DFLL_DVCO>; 13102ceed593SJoseph Lo reset-names = "dvco"; 13112ceed593SJoseph Lo #clock-cells = <0>; 13122ceed593SJoseph Lo clock-output-names = "dfllCPU_out"; 13132ceed593SJoseph Lo status = "disabled"; 13142ceed593SJoseph Lo }; 13152ceed593SJoseph Lo 13160f133090SJon Hunter aconnect@702c0000 { 13170f133090SJon Hunter compatible = "nvidia,tegra210-aconnect"; 13180f133090SJon Hunter clocks = <&tegra_car TEGRA210_CLK_APE>, 13190f133090SJon Hunter <&tegra_car TEGRA210_CLK_APB2APE>; 13200f133090SJon Hunter clock-names = "ape", "apb2ape"; 13210f133090SJon Hunter power-domains = <&pd_audio>; 13220f133090SJon Hunter #address-cells = <1>; 13230f133090SJon Hunter #size-cells = <1>; 13240f133090SJon Hunter ranges = <0x702c0000 0x0 0x702c0000 0x00040000>; 13250f133090SJon Hunter status = "disabled"; 1326bcdbde43SJon Hunter 132719e61213SJon Hunter adma: dma@702e2000 { 132819e61213SJon Hunter compatible = "nvidia,tegra210-adma"; 132919e61213SJon Hunter reg = <0x702e2000 0x2000>; 133019e61213SJon Hunter interrupt-parent = <&agic>; 133119e61213SJon Hunter interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 133219e61213SJon Hunter <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 133319e61213SJon Hunter <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 133419e61213SJon Hunter <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 133519e61213SJon Hunter <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 133619e61213SJon Hunter <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 133719e61213SJon Hunter <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 133819e61213SJon Hunter <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 133919e61213SJon Hunter <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 134019e61213SJon Hunter <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 134119e61213SJon Hunter <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 134219e61213SJon Hunter <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 134319e61213SJon Hunter <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 134419e61213SJon Hunter <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 134519e61213SJon Hunter <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 134619e61213SJon Hunter <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 134719e61213SJon Hunter <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 134819e61213SJon Hunter <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 134919e61213SJon Hunter <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 135019e61213SJon Hunter <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 135119e61213SJon Hunter <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 135219e61213SJon Hunter <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 135319e61213SJon Hunter #dma-cells = <1>; 135419e61213SJon Hunter clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>; 135519e61213SJon Hunter clock-names = "d_audio"; 135619e61213SJon Hunter status = "disabled"; 135719e61213SJon Hunter }; 135819e61213SJon Hunter 1359bcdbde43SJon Hunter agic: agic@702f9000 { 1360bcdbde43SJon Hunter compatible = "nvidia,tegra210-agic"; 1361bcdbde43SJon Hunter #interrupt-cells = <3>; 1362bcdbde43SJon Hunter interrupt-controller; 1363ba24eee6SJon Hunter reg = <0x702f9000 0x1000>, 1364bcdbde43SJon Hunter <0x702fa000 0x2000>; 1365bcdbde43SJon Hunter interrupts = <GIC_SPI 102 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1366bcdbde43SJon Hunter clocks = <&tegra_car TEGRA210_CLK_APE>; 1367bcdbde43SJon Hunter clock-names = "clk"; 1368bcdbde43SJon Hunter status = "disabled"; 1369bcdbde43SJon Hunter }; 13700f133090SJon Hunter }; 13710f133090SJon Hunter 1372be70771dSThierry Reding spi@70410000 { 1373742af7e7SThierry Reding compatible = "nvidia,tegra210-qspi"; 1374742af7e7SThierry Reding reg = <0x0 0x70410000 0x0 0x1000>; 1375742af7e7SThierry Reding interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1376742af7e7SThierry Reding #address-cells = <1>; 1377742af7e7SThierry Reding #size-cells = <0>; 1378742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_QSPI>; 1379742af7e7SThierry Reding clock-names = "qspi"; 1380742af7e7SThierry Reding resets = <&tegra_car 211>; 1381742af7e7SThierry Reding reset-names = "qspi"; 1382742af7e7SThierry Reding dmas = <&apbdma 5>, <&apbdma 5>; 1383742af7e7SThierry Reding dma-names = "rx", "tx"; 1384742af7e7SThierry Reding status = "disabled"; 1385742af7e7SThierry Reding }; 1386742af7e7SThierry Reding 1387be70771dSThierry Reding usb@7d000000 { 1388742af7e7SThierry Reding compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 1389742af7e7SThierry Reding reg = <0x0 0x7d000000 0x0 0x4000>; 1390742af7e7SThierry Reding interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1391742af7e7SThierry Reding phy_type = "utmi"; 1392742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_USBD>; 1393742af7e7SThierry Reding clock-names = "usb"; 1394742af7e7SThierry Reding resets = <&tegra_car 22>; 1395742af7e7SThierry Reding reset-names = "usb"; 1396742af7e7SThierry Reding nvidia,phy = <&phy1>; 1397742af7e7SThierry Reding status = "disabled"; 1398742af7e7SThierry Reding }; 1399742af7e7SThierry Reding 1400be70771dSThierry Reding phy1: usb-phy@7d000000 { 1401742af7e7SThierry Reding compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; 1402742af7e7SThierry Reding reg = <0x0 0x7d000000 0x0 0x4000>, 1403742af7e7SThierry Reding <0x0 0x7d000000 0x0 0x4000>; 1404742af7e7SThierry Reding phy_type = "utmi"; 1405742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_USBD>, 1406742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_PLL_U>, 1407742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_USBD>; 1408742af7e7SThierry Reding clock-names = "reg", "pll_u", "utmi-pads"; 1409742af7e7SThierry Reding resets = <&tegra_car 22>, <&tegra_car 22>; 1410742af7e7SThierry Reding reset-names = "usb", "utmi-pads"; 1411742af7e7SThierry Reding nvidia,hssync-start-delay = <0>; 1412742af7e7SThierry Reding nvidia,idle-wait-delay = <17>; 1413742af7e7SThierry Reding nvidia,elastic-limit = <16>; 1414742af7e7SThierry Reding nvidia,term-range-adj = <6>; 1415742af7e7SThierry Reding nvidia,xcvr-setup = <9>; 1416742af7e7SThierry Reding nvidia,xcvr-lsfslew = <0>; 1417742af7e7SThierry Reding nvidia,xcvr-lsrslew = <3>; 1418742af7e7SThierry Reding nvidia,hssquelch-level = <2>; 1419742af7e7SThierry Reding nvidia,hsdiscon-level = <5>; 1420742af7e7SThierry Reding nvidia,xcvr-hsslew = <12>; 1421742af7e7SThierry Reding nvidia,has-utmi-pad-registers; 1422742af7e7SThierry Reding status = "disabled"; 1423742af7e7SThierry Reding }; 1424742af7e7SThierry Reding 1425be70771dSThierry Reding usb@7d004000 { 1426742af7e7SThierry Reding compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 1427742af7e7SThierry Reding reg = <0x0 0x7d004000 0x0 0x4000>; 1428742af7e7SThierry Reding interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1429742af7e7SThierry Reding phy_type = "utmi"; 1430742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_USB2>; 1431742af7e7SThierry Reding clock-names = "usb"; 1432742af7e7SThierry Reding resets = <&tegra_car 58>; 1433742af7e7SThierry Reding reset-names = "usb"; 1434742af7e7SThierry Reding nvidia,phy = <&phy2>; 1435742af7e7SThierry Reding status = "disabled"; 1436742af7e7SThierry Reding }; 1437742af7e7SThierry Reding 1438be70771dSThierry Reding phy2: usb-phy@7d004000 { 1439742af7e7SThierry Reding compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; 1440742af7e7SThierry Reding reg = <0x0 0x7d004000 0x0 0x4000>, 1441742af7e7SThierry Reding <0x0 0x7d000000 0x0 0x4000>; 1442742af7e7SThierry Reding phy_type = "utmi"; 1443742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_USB2>, 1444742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_PLL_U>, 1445742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_USBD>; 1446742af7e7SThierry Reding clock-names = "reg", "pll_u", "utmi-pads"; 1447742af7e7SThierry Reding resets = <&tegra_car 58>, <&tegra_car 22>; 1448742af7e7SThierry Reding reset-names = "usb", "utmi-pads"; 1449742af7e7SThierry Reding nvidia,hssync-start-delay = <0>; 1450742af7e7SThierry Reding nvidia,idle-wait-delay = <17>; 1451742af7e7SThierry Reding nvidia,elastic-limit = <16>; 1452742af7e7SThierry Reding nvidia,term-range-adj = <6>; 1453742af7e7SThierry Reding nvidia,xcvr-setup = <9>; 1454742af7e7SThierry Reding nvidia,xcvr-lsfslew = <0>; 1455742af7e7SThierry Reding nvidia,xcvr-lsrslew = <3>; 1456742af7e7SThierry Reding nvidia,hssquelch-level = <2>; 1457742af7e7SThierry Reding nvidia,hsdiscon-level = <5>; 1458742af7e7SThierry Reding nvidia,xcvr-hsslew = <12>; 1459742af7e7SThierry Reding status = "disabled"; 1460742af7e7SThierry Reding }; 1461742af7e7SThierry Reding 1462742af7e7SThierry Reding cpus { 1463742af7e7SThierry Reding #address-cells = <1>; 1464742af7e7SThierry Reding #size-cells = <0>; 1465742af7e7SThierry Reding 1466742af7e7SThierry Reding cpu@0 { 1467742af7e7SThierry Reding device_type = "cpu"; 1468742af7e7SThierry Reding compatible = "arm,cortex-a57"; 1469742af7e7SThierry Reding reg = <0>; 147043b9b402SJoseph Lo clocks = <&tegra_car TEGRA210_CLK_CCLK_G>, 147143b9b402SJoseph Lo <&tegra_car TEGRA210_CLK_PLL_X>, 147243b9b402SJoseph Lo <&tegra_car TEGRA210_CLK_PLL_P_OUT4>, 147343b9b402SJoseph Lo <&dfll>; 147443b9b402SJoseph Lo clock-names = "cpu_g", "pll_x", "pll_p", "dfll"; 147543b9b402SJoseph Lo clock-latency = <300000>; 1476da77c6d9SJoseph Lo cpu-idle-states = <&CPU_SLEEP>; 14776c00cac1SJoseph Lo next-level-cache = <&L2>; 1478742af7e7SThierry Reding }; 1479742af7e7SThierry Reding 1480742af7e7SThierry Reding cpu@1 { 1481742af7e7SThierry Reding device_type = "cpu"; 1482742af7e7SThierry Reding compatible = "arm,cortex-a57"; 1483742af7e7SThierry Reding reg = <1>; 1484da77c6d9SJoseph Lo cpu-idle-states = <&CPU_SLEEP>; 14856c00cac1SJoseph Lo next-level-cache = <&L2>; 1486742af7e7SThierry Reding }; 1487742af7e7SThierry Reding 1488742af7e7SThierry Reding cpu@2 { 1489742af7e7SThierry Reding device_type = "cpu"; 1490742af7e7SThierry Reding compatible = "arm,cortex-a57"; 1491742af7e7SThierry Reding reg = <2>; 1492da77c6d9SJoseph Lo cpu-idle-states = <&CPU_SLEEP>; 14936c00cac1SJoseph Lo next-level-cache = <&L2>; 1494742af7e7SThierry Reding }; 1495742af7e7SThierry Reding 1496742af7e7SThierry Reding cpu@3 { 1497742af7e7SThierry Reding device_type = "cpu"; 1498742af7e7SThierry Reding compatible = "arm,cortex-a57"; 1499742af7e7SThierry Reding reg = <3>; 1500da77c6d9SJoseph Lo cpu-idle-states = <&CPU_SLEEP>; 15016c00cac1SJoseph Lo next-level-cache = <&L2>; 1502da77c6d9SJoseph Lo }; 1503da77c6d9SJoseph Lo 1504da77c6d9SJoseph Lo idle-states { 1505da77c6d9SJoseph Lo entry-method = "psci"; 1506da77c6d9SJoseph Lo 1507da77c6d9SJoseph Lo CPU_SLEEP: cpu-sleep { 1508da77c6d9SJoseph Lo compatible = "arm,idle-state"; 1509da77c6d9SJoseph Lo arm,psci-suspend-param = <0x40000007>; 1510da77c6d9SJoseph Lo entry-latency-us = <100>; 1511da77c6d9SJoseph Lo exit-latency-us = <30>; 1512da77c6d9SJoseph Lo min-residency-us = <1000>; 1513da77c6d9SJoseph Lo wakeup-latency-us = <130>; 1514da77c6d9SJoseph Lo idle-state-name = "cpu-sleep"; 1515da77c6d9SJoseph Lo status = "disabled"; 1516da77c6d9SJoseph Lo }; 1517742af7e7SThierry Reding }; 15186c00cac1SJoseph Lo 15196c00cac1SJoseph Lo L2: l2-cache { 15206c00cac1SJoseph Lo compatible = "cache"; 15216c00cac1SJoseph Lo }; 1522742af7e7SThierry Reding }; 1523742af7e7SThierry Reding 1524264064abSThierry Reding pmu { 1525264064abSThierry Reding compatible = "arm,armv8-pmuv3"; 1526264064abSThierry Reding interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1527264064abSThierry Reding <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1528264064abSThierry Reding <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1529264064abSThierry Reding <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 1530264064abSThierry Reding interrupt-affinity = <&{/cpus/cpu@0} &{/cpus/cpu@1} 1531264064abSThierry Reding &{/cpus/cpu@2} &{/cpus/cpu@3}>; 1532264064abSThierry Reding }; 1533264064abSThierry Reding 1534742af7e7SThierry Reding timer { 1535742af7e7SThierry Reding compatible = "arm,armv8-timer"; 1536742af7e7SThierry Reding interrupts = <GIC_PPI 13 1537742af7e7SThierry Reding (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1538742af7e7SThierry Reding <GIC_PPI 14 1539742af7e7SThierry Reding (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1540742af7e7SThierry Reding <GIC_PPI 11 1541742af7e7SThierry Reding (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1542742af7e7SThierry Reding <GIC_PPI 10 1543742af7e7SThierry Reding (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1544742af7e7SThierry Reding interrupt-parent = <&gic>; 15456b9e263bSThierry Reding arm,no-tick-in-suspend; 1546742af7e7SThierry Reding }; 1547e2bed1ebSWei Ni 1548e2bed1ebSWei Ni soctherm: thermal-sensor@700e2000 { 1549e2bed1ebSWei Ni compatible = "nvidia,tegra210-soctherm"; 1550cbd0f000SWei Ni reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */ 1551cbd0f000SWei Ni 0x0 0x60006000 0x0 0x400>; /* CAR reg_base */ 1552cbd0f000SWei Ni reg-names = "soctherm-reg", "car-reg"; 155344ff822cSThierry Reding interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 155444ff822cSThierry Reding <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 155544ff822cSThierry Reding interrupt-names = "thermal", "edp"; 1556e2bed1ebSWei Ni clocks = <&tegra_car TEGRA210_CLK_TSENSOR>, 1557e2bed1ebSWei Ni <&tegra_car TEGRA210_CLK_SOC_THERM>; 1558e2bed1ebSWei Ni clock-names = "tsensor", "soctherm"; 1559e2bed1ebSWei Ni resets = <&tegra_car 78>; 1560e2bed1ebSWei Ni reset-names = "soctherm"; 1561e2bed1ebSWei Ni #thermal-sensor-cells = <1>; 1562cbd0f000SWei Ni 1563cbd0f000SWei Ni throttle-cfgs { 1564cbd0f000SWei Ni throttle_heavy: heavy { 1565cbd0f000SWei Ni nvidia,priority = <100>; 1566cbd0f000SWei Ni nvidia,cpu-throt-percent = <85>; 1567cbd0f000SWei Ni 1568cbd0f000SWei Ni #cooling-cells = <2>; 1569cbd0f000SWei Ni }; 1570cbd0f000SWei Ni }; 1571e2bed1ebSWei Ni }; 1572e2bed1ebSWei Ni 1573e2bed1ebSWei Ni thermal-zones { 1574e2bed1ebSWei Ni cpu { 1575e2bed1ebSWei Ni polling-delay-passive = <1000>; 1576e2bed1ebSWei Ni polling-delay = <0>; 1577e2bed1ebSWei Ni 1578e2bed1ebSWei Ni thermal-sensors = 1579e2bed1ebSWei Ni <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; 15805e03f663SWei Ni 15815e03f663SWei Ni trips { 15825e03f663SWei Ni cpu-shutdown-trip { 15835e03f663SWei Ni temperature = <102500>; 15845e03f663SWei Ni hysteresis = <0>; 15855e03f663SWei Ni type = "critical"; 15865e03f663SWei Ni }; 1587cbd0f000SWei Ni 1588cbd0f000SWei Ni cpu_throttle_trip: throttle-trip { 1589cbd0f000SWei Ni temperature = <98500>; 1590cbd0f000SWei Ni hysteresis = <1000>; 1591cbd0f000SWei Ni type = "hot"; 1592cbd0f000SWei Ni }; 15935e03f663SWei Ni }; 15945e03f663SWei Ni 15955e03f663SWei Ni cooling-maps { 1596cbd0f000SWei Ni map0 { 1597cbd0f000SWei Ni trip = <&cpu_throttle_trip>; 1598cbd0f000SWei Ni cooling-device = <&throttle_heavy 1 1>; 1599cbd0f000SWei Ni }; 16005e03f663SWei Ni }; 1601e2bed1ebSWei Ni }; 160224fc3363SThierry Reding 1603e2bed1ebSWei Ni mem { 1604e2bed1ebSWei Ni polling-delay-passive = <0>; 1605e2bed1ebSWei Ni polling-delay = <0>; 1606e2bed1ebSWei Ni 1607e2bed1ebSWei Ni thermal-sensors = 1608e2bed1ebSWei Ni <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>; 16095e03f663SWei Ni 16105e03f663SWei Ni trips { 1611e12325f6SThierry Reding dram_nominal: mem-nominal-trip { 1612e12325f6SThierry Reding temperature = <50000>; 1613e12325f6SThierry Reding hysteresis = <1000>; 1614e12325f6SThierry Reding type = "passive"; 1615e12325f6SThierry Reding }; 1616e12325f6SThierry Reding 1617e12325f6SThierry Reding dram_throttle: mem-throttle-trip { 1618e12325f6SThierry Reding temperature = <70000>; 1619e12325f6SThierry Reding hysteresis = <1000>; 1620e12325f6SThierry Reding type = "active"; 1621e12325f6SThierry Reding }; 1622e12325f6SThierry Reding 16235e03f663SWei Ni mem-shutdown-trip { 16245e03f663SWei Ni temperature = <103000>; 16255e03f663SWei Ni hysteresis = <0>; 16265e03f663SWei Ni type = "critical"; 16275e03f663SWei Ni }; 16285e03f663SWei Ni }; 16295e03f663SWei Ni 16305e03f663SWei Ni cooling-maps { 1631e12325f6SThierry Reding dram-passive { 1632e12325f6SThierry Reding cooling-device = <&emc 0 0>; 1633e12325f6SThierry Reding trip = <&dram_nominal>; 1634e12325f6SThierry Reding }; 1635e12325f6SThierry Reding 1636e12325f6SThierry Reding dram-active { 1637e12325f6SThierry Reding cooling-device = <&emc 1 1>; 1638e12325f6SThierry Reding trip = <&dram_throttle>; 1639e12325f6SThierry Reding }; 16405e03f663SWei Ni }; 1641e2bed1ebSWei Ni }; 164224fc3363SThierry Reding 1643e2bed1ebSWei Ni gpu { 1644e2bed1ebSWei Ni polling-delay-passive = <1000>; 1645e2bed1ebSWei Ni polling-delay = <0>; 1646e2bed1ebSWei Ni 1647e2bed1ebSWei Ni thermal-sensors = 1648e2bed1ebSWei Ni <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>; 16495e03f663SWei Ni 16505e03f663SWei Ni trips { 16515e03f663SWei Ni gpu-shutdown-trip { 16525e03f663SWei Ni temperature = <103000>; 16535e03f663SWei Ni hysteresis = <0>; 16545e03f663SWei Ni type = "critical"; 16555e03f663SWei Ni }; 1656cbd0f000SWei Ni 1657cbd0f000SWei Ni gpu_throttle_trip: throttle-trip { 1658cbd0f000SWei Ni temperature = <100000>; 1659cbd0f000SWei Ni hysteresis = <1000>; 1660cbd0f000SWei Ni type = "hot"; 1661cbd0f000SWei Ni }; 16625e03f663SWei Ni }; 16635e03f663SWei Ni 16645e03f663SWei Ni cooling-maps { 1665cbd0f000SWei Ni map0 { 1666cbd0f000SWei Ni trip = <&gpu_throttle_trip>; 1667cbd0f000SWei Ni cooling-device = <&throttle_heavy 1 1>; 1668cbd0f000SWei Ni }; 16695e03f663SWei Ni }; 1670e2bed1ebSWei Ni }; 167124fc3363SThierry Reding 1672e2bed1ebSWei Ni pllx { 1673e2bed1ebSWei Ni polling-delay-passive = <0>; 1674e2bed1ebSWei Ni polling-delay = <0>; 1675e2bed1ebSWei Ni 1676e2bed1ebSWei Ni thermal-sensors = 1677e2bed1ebSWei Ni <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>; 16785e03f663SWei Ni 16795e03f663SWei Ni trips { 16805e03f663SWei Ni pllx-shutdown-trip { 16815e03f663SWei Ni temperature = <103000>; 16825e03f663SWei Ni hysteresis = <0>; 16835e03f663SWei Ni type = "critical"; 16845e03f663SWei Ni }; 16855e03f663SWei Ni }; 16865e03f663SWei Ni 16875e03f663SWei Ni cooling-maps { 16885e03f663SWei Ni /* 16895e03f663SWei Ni * There are currently no cooling maps, 16905e03f663SWei Ni * because there are no cooling devices. 16915e03f663SWei Ni */ 16925e03f663SWei Ni }; 1693e2bed1ebSWei Ni }; 1694e2bed1ebSWei Ni }; 1695742af7e7SThierry Reding}; 1696