1b2441318SGreg Kroah-Hartman// SPDX-License-Identifier: GPL-2.0 2742af7e7SThierry Reding#include <dt-bindings/clock/tegra210-car.h> 3742af7e7SThierry Reding#include <dt-bindings/gpio/tegra-gpio.h> 4742af7e7SThierry Reding#include <dt-bindings/memory/tegra210-mc.h> 5742af7e7SThierry Reding#include <dt-bindings/pinctrl/pinctrl-tegra.h> 66641af7eSAapo Vienamo#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 72ceed593SJoseph Lo#include <dt-bindings/reset/tegra210-car.h> 8742af7e7SThierry Reding#include <dt-bindings/interrupt-controller/arm-gic.h> 9e2bed1ebSWei Ni#include <dt-bindings/thermal/tegra124-soctherm.h> 10359ae651SSowjanya Komatineni#include <dt-bindings/soc/tegra-pmc.h> 11742af7e7SThierry Reding 12742af7e7SThierry Reding/ { 13742af7e7SThierry Reding compatible = "nvidia,tegra210"; 14742af7e7SThierry Reding interrupt-parent = <&lic>; 15742af7e7SThierry Reding #address-cells = <2>; 16742af7e7SThierry Reding #size-cells = <2>; 17742af7e7SThierry Reding 18475d99fcSRob Herring pcie@1003000 { 19589a2d3fSThierry Reding compatible = "nvidia,tegra210-pcie"; 20589a2d3fSThierry Reding device_type = "pci"; 21644c569dSThierry Reding reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */ 22644c569dSThierry Reding <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */ 23644c569dSThierry Reding <0x0 0x02000000 0x0 0x10000000>; /* configuration space */ 24589a2d3fSThierry Reding reg-names = "pads", "afi", "cs"; 25589a2d3fSThierry Reding interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 26589a2d3fSThierry Reding <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 27589a2d3fSThierry Reding interrupt-names = "intr", "msi"; 28589a2d3fSThierry Reding 29589a2d3fSThierry Reding #interrupt-cells = <1>; 30589a2d3fSThierry Reding interrupt-map-mask = <0 0 0 0>; 31589a2d3fSThierry Reding interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 32589a2d3fSThierry Reding 33589a2d3fSThierry Reding bus-range = <0x00 0xff>; 34589a2d3fSThierry Reding #address-cells = <3>; 35589a2d3fSThierry Reding #size-cells = <2>; 36589a2d3fSThierry Reding 37644c569dSThierry Reding ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */ 38644c569dSThierry Reding <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */ 39644c569dSThierry Reding <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */ 40644c569dSThierry Reding <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */ 41644c569dSThierry Reding <0x42000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ 42589a2d3fSThierry Reding 43589a2d3fSThierry Reding clocks = <&tegra_car TEGRA210_CLK_PCIE>, 44589a2d3fSThierry Reding <&tegra_car TEGRA210_CLK_AFI>, 45589a2d3fSThierry Reding <&tegra_car TEGRA210_CLK_PLL_E>, 46589a2d3fSThierry Reding <&tegra_car TEGRA210_CLK_CML0>; 47589a2d3fSThierry Reding clock-names = "pex", "afi", "pll_e", "cml"; 48589a2d3fSThierry Reding resets = <&tegra_car 70>, 49589a2d3fSThierry Reding <&tegra_car 72>, 50589a2d3fSThierry Reding <&tegra_car 74>; 51589a2d3fSThierry Reding reset-names = "pex", "afi", "pcie_x"; 52871be845SManikanta Maddireddy 53871be845SManikanta Maddireddy pinctrl-names = "default", "idle"; 54871be845SManikanta Maddireddy pinctrl-0 = <&pex_dpd_disable>; 55871be845SManikanta Maddireddy pinctrl-1 = <&pex_dpd_enable>; 56871be845SManikanta Maddireddy 57589a2d3fSThierry Reding status = "disabled"; 58589a2d3fSThierry Reding 59589a2d3fSThierry Reding pci@1,0 { 60589a2d3fSThierry Reding device_type = "pci"; 61589a2d3fSThierry Reding assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>; 62589a2d3fSThierry Reding reg = <0x000800 0 0 0 0>; 63475d99fcSRob Herring bus-range = <0x00 0xff>; 64589a2d3fSThierry Reding status = "disabled"; 65589a2d3fSThierry Reding 66589a2d3fSThierry Reding #address-cells = <3>; 67589a2d3fSThierry Reding #size-cells = <2>; 68589a2d3fSThierry Reding ranges; 69589a2d3fSThierry Reding 70589a2d3fSThierry Reding nvidia,num-lanes = <4>; 71589a2d3fSThierry Reding }; 72589a2d3fSThierry Reding 73589a2d3fSThierry Reding pci@2,0 { 74589a2d3fSThierry Reding device_type = "pci"; 75589a2d3fSThierry Reding assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>; 76589a2d3fSThierry Reding reg = <0x001000 0 0 0 0>; 77475d99fcSRob Herring bus-range = <0x00 0xff>; 78589a2d3fSThierry Reding status = "disabled"; 79589a2d3fSThierry Reding 80589a2d3fSThierry Reding #address-cells = <3>; 81589a2d3fSThierry Reding #size-cells = <2>; 82589a2d3fSThierry Reding ranges; 83589a2d3fSThierry Reding 84589a2d3fSThierry Reding nvidia,num-lanes = <1>; 85589a2d3fSThierry Reding }; 86589a2d3fSThierry Reding }; 87589a2d3fSThierry Reding 88be70771dSThierry Reding host1x@50000000 { 89ef126bc4SThierry Reding compatible = "nvidia,tegra210-host1x"; 90742af7e7SThierry Reding reg = <0x0 0x50000000 0x0 0x00034000>; 91742af7e7SThierry Reding interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 92742af7e7SThierry Reding <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ 93052d3f65SThierry Reding interrupt-names = "syncpt", "host1x"; 94742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_HOST1X>; 95742af7e7SThierry Reding clock-names = "host1x"; 96914ed1f5SThierry Reding resets = <&tegra_car 28>, <&mc TEGRA210_MC_RESET_HC>; 97914ed1f5SThierry Reding reset-names = "host1x", "mc"; 98742af7e7SThierry Reding 99742af7e7SThierry Reding #address-cells = <2>; 100742af7e7SThierry Reding #size-cells = <2>; 101742af7e7SThierry Reding 102742af7e7SThierry Reding ranges = <0x0 0x54000000 0x0 0x54000000 0x0 0x01000000>; 103742af7e7SThierry Reding 104116503a6SMikko Perttunen iommus = <&mc TEGRA_SWGROUP_HC>; 105116503a6SMikko Perttunen 106be70771dSThierry Reding dpaux1: dpaux@54040000 { 107742af7e7SThierry Reding compatible = "nvidia,tegra210-dpaux"; 108742af7e7SThierry Reding reg = <0x0 0x54040000 0x0 0x00040000>; 109742af7e7SThierry Reding interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 110742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_DPAUX1>, 111742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_PLL_DP>; 112742af7e7SThierry Reding clock-names = "dpaux", "parent"; 113742af7e7SThierry Reding resets = <&tegra_car 207>; 114742af7e7SThierry Reding reset-names = "dpaux"; 11596d1f078SJon Hunter power-domains = <&pd_sor>; 116742af7e7SThierry Reding status = "disabled"; 11766b2d6e9SJon Hunter 11866b2d6e9SJon Hunter state_dpaux1_aux: pinmux-aux { 11966b2d6e9SJon Hunter groups = "dpaux-io"; 12066b2d6e9SJon Hunter function = "aux"; 12166b2d6e9SJon Hunter }; 12266b2d6e9SJon Hunter 12366b2d6e9SJon Hunter state_dpaux1_i2c: pinmux-i2c { 12466b2d6e9SJon Hunter groups = "dpaux-io"; 12566b2d6e9SJon Hunter function = "i2c"; 12666b2d6e9SJon Hunter }; 12766b2d6e9SJon Hunter 12866b2d6e9SJon Hunter state_dpaux1_off: pinmux-off { 12966b2d6e9SJon Hunter groups = "dpaux-io"; 13066b2d6e9SJon Hunter function = "off"; 13166b2d6e9SJon Hunter }; 13266b2d6e9SJon Hunter 13366b2d6e9SJon Hunter i2c-bus { 13466b2d6e9SJon Hunter #address-cells = <1>; 13566b2d6e9SJon Hunter #size-cells = <0>; 13666b2d6e9SJon Hunter }; 137742af7e7SThierry Reding }; 138742af7e7SThierry Reding 139be70771dSThierry Reding vi@54080000 { 140742af7e7SThierry Reding compatible = "nvidia,tegra210-vi"; 141c4153885SSowjanya Komatineni reg = <0x0 0x54080000 0x0 0x700>; 142742af7e7SThierry Reding interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 143742af7e7SThierry Reding status = "disabled"; 144c4153885SSowjanya Komatineni assigned-clocks = <&tegra_car TEGRA210_CLK_VI>; 145c4153885SSowjanya Komatineni assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 146c4153885SSowjanya Komatineni 147c4153885SSowjanya Komatineni clocks = <&tegra_car TEGRA210_CLK_VI>; 148c4153885SSowjanya Komatineni power-domains = <&pd_venc>; 149c4153885SSowjanya Komatineni 150c4153885SSowjanya Komatineni #address-cells = <1>; 151c4153885SSowjanya Komatineni #size-cells = <1>; 152c4153885SSowjanya Komatineni 153c4153885SSowjanya Komatineni ranges = <0x0 0x0 0x54080000 0x2000>; 154c4153885SSowjanya Komatineni 155c4153885SSowjanya Komatineni csi@838 { 156c4153885SSowjanya Komatineni compatible = "nvidia,tegra210-csi"; 157c4153885SSowjanya Komatineni reg = <0x838 0x1300>; 158c4153885SSowjanya Komatineni status = "disabled"; 159c4153885SSowjanya Komatineni assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>, 160c4153885SSowjanya Komatineni <&tegra_car TEGRA210_CLK_CILCD>, 161c4153885SSowjanya Komatineni <&tegra_car TEGRA210_CLK_CILE>, 162c4153885SSowjanya Komatineni <&tegra_car TEGRA210_CLK_CSI_TPG>; 163c4153885SSowjanya Komatineni assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>, 164c4153885SSowjanya Komatineni <&tegra_car TEGRA210_CLK_PLL_P>, 165c4153885SSowjanya Komatineni <&tegra_car TEGRA210_CLK_PLL_P>; 166c4153885SSowjanya Komatineni assigned-clock-rates = <102000000>, 167c4153885SSowjanya Komatineni <102000000>, 168c4153885SSowjanya Komatineni <102000000>, 169c4153885SSowjanya Komatineni <972000000>; 170c4153885SSowjanya Komatineni 171c4153885SSowjanya Komatineni clocks = <&tegra_car TEGRA210_CLK_CSI>, 172c4153885SSowjanya Komatineni <&tegra_car TEGRA210_CLK_CILAB>, 173c4153885SSowjanya Komatineni <&tegra_car TEGRA210_CLK_CILCD>, 174c4153885SSowjanya Komatineni <&tegra_car TEGRA210_CLK_CILE>, 175c4153885SSowjanya Komatineni <&tegra_car TEGRA210_CLK_CSI_TPG>; 176c4153885SSowjanya Komatineni clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg"; 177c4153885SSowjanya Komatineni power-domains = <&pd_sor>; 178c4153885SSowjanya Komatineni }; 179742af7e7SThierry Reding }; 180742af7e7SThierry Reding 181be70771dSThierry Reding tsec@54100000 { 182742af7e7SThierry Reding compatible = "nvidia,tegra210-tsec"; 183742af7e7SThierry Reding reg = <0x0 0x54100000 0x0 0x00040000>; 18428a44b90SThierry Reding interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 18528a44b90SThierry Reding clocks = <&tegra_car TEGRA210_CLK_TSEC>; 18628a44b90SThierry Reding clock-names = "tsec"; 18728a44b90SThierry Reding resets = <&tegra_car 83>; 18828a44b90SThierry Reding reset-names = "tsec"; 18928a44b90SThierry Reding status = "disabled"; 190742af7e7SThierry Reding }; 191742af7e7SThierry Reding 192be70771dSThierry Reding dc@54200000 { 193742af7e7SThierry Reding compatible = "nvidia,tegra210-dc"; 194742af7e7SThierry Reding reg = <0x0 0x54200000 0x0 0x00040000>; 195742af7e7SThierry Reding interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 196352092b0SThierry Reding clocks = <&tegra_car TEGRA210_CLK_DISP1>; 197352092b0SThierry Reding clock-names = "dc"; 198742af7e7SThierry Reding resets = <&tegra_car 27>; 199742af7e7SThierry Reding reset-names = "dc"; 200742af7e7SThierry Reding 201742af7e7SThierry Reding iommus = <&mc TEGRA_SWGROUP_DC>; 202742af7e7SThierry Reding 2030cc6ba3cSThierry Reding nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 204742af7e7SThierry Reding nvidia,head = <0>; 205742af7e7SThierry Reding }; 206742af7e7SThierry Reding 207be70771dSThierry Reding dc@54240000 { 208742af7e7SThierry Reding compatible = "nvidia,tegra210-dc"; 209742af7e7SThierry Reding reg = <0x0 0x54240000 0x0 0x00040000>; 210742af7e7SThierry Reding interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 211352092b0SThierry Reding clocks = <&tegra_car TEGRA210_CLK_DISP2>; 212352092b0SThierry Reding clock-names = "dc"; 213742af7e7SThierry Reding resets = <&tegra_car 26>; 214742af7e7SThierry Reding reset-names = "dc"; 215742af7e7SThierry Reding 216742af7e7SThierry Reding iommus = <&mc TEGRA_SWGROUP_DCB>; 217742af7e7SThierry Reding 2180cc6ba3cSThierry Reding nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 219742af7e7SThierry Reding nvidia,head = <1>; 220742af7e7SThierry Reding }; 221742af7e7SThierry Reding 2220cc6ba3cSThierry Reding dsia: dsi@54300000 { 223742af7e7SThierry Reding compatible = "nvidia,tegra210-dsi"; 224742af7e7SThierry Reding reg = <0x0 0x54300000 0x0 0x00040000>; 225742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_DSIA>, 226742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_DSIALP>, 227742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; 228742af7e7SThierry Reding clock-names = "dsi", "lp", "parent"; 229742af7e7SThierry Reding resets = <&tegra_car 48>; 230742af7e7SThierry Reding reset-names = "dsi"; 23196d1f078SJon Hunter power-domains = <&pd_sor>; 232742af7e7SThierry Reding nvidia,mipi-calibrate = <&mipi 0x0c0>; /* DSIA & DSIB pads */ 233742af7e7SThierry Reding 234742af7e7SThierry Reding status = "disabled"; 235742af7e7SThierry Reding 236742af7e7SThierry Reding #address-cells = <1>; 237742af7e7SThierry Reding #size-cells = <0>; 238742af7e7SThierry Reding }; 239742af7e7SThierry Reding 240be70771dSThierry Reding vic@54340000 { 241742af7e7SThierry Reding compatible = "nvidia,tegra210-vic"; 242742af7e7SThierry Reding reg = <0x0 0x54340000 0x0 0x00040000>; 24324963d1bSMikko Perttunen interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 24424963d1bSMikko Perttunen clocks = <&tegra_car TEGRA210_CLK_VIC03>; 24524963d1bSMikko Perttunen clock-names = "vic"; 24624963d1bSMikko Perttunen resets = <&tegra_car 178>; 24724963d1bSMikko Perttunen reset-names = "vic"; 24824963d1bSMikko Perttunen 24924963d1bSMikko Perttunen iommus = <&mc TEGRA_SWGROUP_VIC>; 25024963d1bSMikko Perttunen power-domains = <&pd_vic>; 251742af7e7SThierry Reding }; 252742af7e7SThierry Reding 253be70771dSThierry Reding nvjpg@54380000 { 254742af7e7SThierry Reding compatible = "nvidia,tegra210-nvjpg"; 255742af7e7SThierry Reding reg = <0x0 0x54380000 0x0 0x00040000>; 256742af7e7SThierry Reding status = "disabled"; 257742af7e7SThierry Reding }; 258742af7e7SThierry Reding 2590cc6ba3cSThierry Reding dsib: dsi@54400000 { 260742af7e7SThierry Reding compatible = "nvidia,tegra210-dsi"; 261742af7e7SThierry Reding reg = <0x0 0x54400000 0x0 0x00040000>; 262742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_DSIB>, 263742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_DSIBLP>, 264742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; 265742af7e7SThierry Reding clock-names = "dsi", "lp", "parent"; 266742af7e7SThierry Reding resets = <&tegra_car 82>; 267742af7e7SThierry Reding reset-names = "dsi"; 26896d1f078SJon Hunter power-domains = <&pd_sor>; 269742af7e7SThierry Reding nvidia,mipi-calibrate = <&mipi 0x300>; /* DSIC & DSID pads */ 270742af7e7SThierry Reding 271742af7e7SThierry Reding status = "disabled"; 272742af7e7SThierry Reding 273742af7e7SThierry Reding #address-cells = <1>; 274742af7e7SThierry Reding #size-cells = <0>; 275742af7e7SThierry Reding }; 276742af7e7SThierry Reding 277be70771dSThierry Reding nvdec@54480000 { 278742af7e7SThierry Reding compatible = "nvidia,tegra210-nvdec"; 279742af7e7SThierry Reding reg = <0x0 0x54480000 0x0 0x00040000>; 280742af7e7SThierry Reding status = "disabled"; 281742af7e7SThierry Reding }; 282742af7e7SThierry Reding 283be70771dSThierry Reding nvenc@544c0000 { 284742af7e7SThierry Reding compatible = "nvidia,tegra210-nvenc"; 285742af7e7SThierry Reding reg = <0x0 0x544c0000 0x0 0x00040000>; 286742af7e7SThierry Reding status = "disabled"; 287742af7e7SThierry Reding }; 288742af7e7SThierry Reding 289be70771dSThierry Reding tsec@54500000 { 290742af7e7SThierry Reding compatible = "nvidia,tegra210-tsec"; 291742af7e7SThierry Reding reg = <0x0 0x54500000 0x0 0x00040000>; 29228a44b90SThierry Reding interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 29328a44b90SThierry Reding clocks = <&tegra_car TEGRA210_CLK_TSECB>; 29428a44b90SThierry Reding clock-names = "tsec"; 29528a44b90SThierry Reding resets = <&tegra_car 206>; 29628a44b90SThierry Reding reset-names = "tsec"; 297742af7e7SThierry Reding status = "disabled"; 298742af7e7SThierry Reding }; 299742af7e7SThierry Reding 3000cc6ba3cSThierry Reding sor0: sor@54540000 { 301742af7e7SThierry Reding compatible = "nvidia,tegra210-sor"; 302742af7e7SThierry Reding reg = <0x0 0x54540000 0x0 0x00040000>; 303742af7e7SThierry Reding interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 304742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_SOR0>, 305ed93a666SThierry Reding <&tegra_car TEGRA210_CLK_SOR0_OUT>, 306742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_PLL_D_OUT0>, 307742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_PLL_DP>, 308742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_SOR_SAFE>; 309ed93a666SThierry Reding clock-names = "sor", "out", "parent", "dp", "safe"; 310742af7e7SThierry Reding resets = <&tegra_car 182>; 311742af7e7SThierry Reding reset-names = "sor"; 31266b2d6e9SJon Hunter pinctrl-0 = <&state_dpaux_aux>; 31366b2d6e9SJon Hunter pinctrl-1 = <&state_dpaux_i2c>; 31466b2d6e9SJon Hunter pinctrl-2 = <&state_dpaux_off>; 31566b2d6e9SJon Hunter pinctrl-names = "aux", "i2c", "off"; 31696d1f078SJon Hunter power-domains = <&pd_sor>; 317742af7e7SThierry Reding status = "disabled"; 318742af7e7SThierry Reding }; 319742af7e7SThierry Reding 3200cc6ba3cSThierry Reding sor1: sor@54580000 { 321742af7e7SThierry Reding compatible = "nvidia,tegra210-sor1"; 322742af7e7SThierry Reding reg = <0x0 0x54580000 0x0 0x00040000>; 323742af7e7SThierry Reding interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 324742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_SOR1>, 32550f5b841SThierry Reding <&tegra_car TEGRA210_CLK_SOR1_OUT>, 326742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_PLL_D2_OUT0>, 327742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_PLL_DP>, 328742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_SOR_SAFE>; 32950f5b841SThierry Reding clock-names = "sor", "out", "parent", "dp", "safe"; 330742af7e7SThierry Reding resets = <&tegra_car 183>; 331742af7e7SThierry Reding reset-names = "sor"; 33266b2d6e9SJon Hunter pinctrl-0 = <&state_dpaux1_aux>; 33366b2d6e9SJon Hunter pinctrl-1 = <&state_dpaux1_i2c>; 33466b2d6e9SJon Hunter pinctrl-2 = <&state_dpaux1_off>; 33566b2d6e9SJon Hunter pinctrl-names = "aux", "i2c", "off"; 33696d1f078SJon Hunter power-domains = <&pd_sor>; 337742af7e7SThierry Reding status = "disabled"; 338742af7e7SThierry Reding }; 339742af7e7SThierry Reding 340be70771dSThierry Reding dpaux: dpaux@545c0000 { 341e989992aSThierry Reding compatible = "nvidia,tegra210-dpaux"; 342742af7e7SThierry Reding reg = <0x0 0x545c0000 0x0 0x00040000>; 343742af7e7SThierry Reding interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 344742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_DPAUX>, 345742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_PLL_DP>; 346742af7e7SThierry Reding clock-names = "dpaux", "parent"; 347742af7e7SThierry Reding resets = <&tegra_car 181>; 348742af7e7SThierry Reding reset-names = "dpaux"; 34996d1f078SJon Hunter power-domains = <&pd_sor>; 350742af7e7SThierry Reding status = "disabled"; 35166b2d6e9SJon Hunter 35266b2d6e9SJon Hunter state_dpaux_aux: pinmux-aux { 35366b2d6e9SJon Hunter groups = "dpaux-io"; 35466b2d6e9SJon Hunter function = "aux"; 35566b2d6e9SJon Hunter }; 35666b2d6e9SJon Hunter 35766b2d6e9SJon Hunter state_dpaux_i2c: pinmux-i2c { 35866b2d6e9SJon Hunter groups = "dpaux-io"; 35966b2d6e9SJon Hunter function = "i2c"; 36066b2d6e9SJon Hunter }; 36166b2d6e9SJon Hunter 36266b2d6e9SJon Hunter state_dpaux_off: pinmux-off { 36366b2d6e9SJon Hunter groups = "dpaux-io"; 36466b2d6e9SJon Hunter function = "off"; 36566b2d6e9SJon Hunter }; 36666b2d6e9SJon Hunter 36766b2d6e9SJon Hunter i2c-bus { 36866b2d6e9SJon Hunter #address-cells = <1>; 36966b2d6e9SJon Hunter #size-cells = <0>; 37066b2d6e9SJon Hunter }; 371742af7e7SThierry Reding }; 372742af7e7SThierry Reding 373be70771dSThierry Reding isp@54600000 { 374742af7e7SThierry Reding compatible = "nvidia,tegra210-isp"; 375742af7e7SThierry Reding reg = <0x0 0x54600000 0x0 0x00040000>; 376742af7e7SThierry Reding interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 37797ace1b4SThierry Reding clocks = <&tegra_car TEGRA210_CLK_ISPA>; 37897ace1b4SThierry Reding resets = <&tegra_car 23>; 37997ace1b4SThierry Reding reset-names = "isp"; 380742af7e7SThierry Reding status = "disabled"; 381742af7e7SThierry Reding }; 382742af7e7SThierry Reding 383be70771dSThierry Reding isp@54680000 { 384742af7e7SThierry Reding compatible = "nvidia,tegra210-isp"; 385742af7e7SThierry Reding reg = <0x0 0x54680000 0x0 0x00040000>; 386742af7e7SThierry Reding interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 38797ace1b4SThierry Reding clocks = <&tegra_car TEGRA210_CLK_ISPB>; 38897ace1b4SThierry Reding resets = <&tegra_car 3>; 38997ace1b4SThierry Reding reset-names = "isp"; 390742af7e7SThierry Reding status = "disabled"; 391742af7e7SThierry Reding }; 392742af7e7SThierry Reding 393be70771dSThierry Reding i2c@546c0000 { 394742af7e7SThierry Reding compatible = "nvidia,tegra210-i2c-vi"; 395742af7e7SThierry Reding reg = <0x0 0x546c0000 0x0 0x00040000>; 396742af7e7SThierry Reding interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 397139a390cSSowjanya Komatineni clocks = <&tegra_car TEGRA210_CLK_VI_I2C>, 398139a390cSSowjanya Komatineni <&tegra_car TEGRA210_CLK_I2CSLOW>; 399139a390cSSowjanya Komatineni clock-names = "div-clk", "slow"; 400139a390cSSowjanya Komatineni resets = <&tegra_car 208>; 401139a390cSSowjanya Komatineni reset-names = "i2c"; 402139a390cSSowjanya Komatineni power-domains = <&pd_venc>; 403742af7e7SThierry Reding status = "disabled"; 4044087162fSThierry Reding 4054087162fSThierry Reding #address-cells = <1>; 4064087162fSThierry Reding #size-cells = <0>; 407742af7e7SThierry Reding }; 408742af7e7SThierry Reding }; 409742af7e7SThierry Reding 410be70771dSThierry Reding gic: interrupt-controller@50041000 { 411742af7e7SThierry Reding compatible = "arm,gic-400"; 412742af7e7SThierry Reding #interrupt-cells = <3>; 413742af7e7SThierry Reding interrupt-controller; 414742af7e7SThierry Reding reg = <0x0 0x50041000 0x0 0x1000>, 415742af7e7SThierry Reding <0x0 0x50042000 0x0 0x2000>, 416742af7e7SThierry Reding <0x0 0x50044000 0x0 0x2000>, 417742af7e7SThierry Reding <0x0 0x50046000 0x0 0x2000>; 418742af7e7SThierry Reding interrupts = <GIC_PPI 9 419742af7e7SThierry Reding (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 420742af7e7SThierry Reding interrupt-parent = <&gic>; 421742af7e7SThierry Reding }; 422742af7e7SThierry Reding 423be70771dSThierry Reding gpu@57000000 { 424742af7e7SThierry Reding compatible = "nvidia,gm20b"; 425742af7e7SThierry Reding reg = <0x0 0x57000000 0x0 0x01000000>, 426742af7e7SThierry Reding <0x0 0x58000000 0x0 0x01000000>; 427742af7e7SThierry Reding interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 428742af7e7SThierry Reding <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 429742af7e7SThierry Reding interrupt-names = "stall", "nonstall"; 430742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_GPU>, 4314a0778e9SAlexandre Courbot <&tegra_car TEGRA210_CLK_PLL_P_OUT5>, 4324a0778e9SAlexandre Courbot <&tegra_car TEGRA210_CLK_PLL_G_REF>; 4334a0778e9SAlexandre Courbot clock-names = "gpu", "pwr", "ref"; 434742af7e7SThierry Reding resets = <&tegra_car 184>; 435742af7e7SThierry Reding reset-names = "gpu"; 43630f949bcSAlexandre Courbot 43730f949bcSAlexandre Courbot iommus = <&mc TEGRA_SWGROUP_GPU>; 43830f949bcSAlexandre Courbot 439742af7e7SThierry Reding status = "disabled"; 440742af7e7SThierry Reding }; 441742af7e7SThierry Reding 442be70771dSThierry Reding lic: interrupt-controller@60004000 { 443742af7e7SThierry Reding compatible = "nvidia,tegra210-ictlr"; 444742af7e7SThierry Reding reg = <0x0 0x60004000 0x0 0x40>, /* primary controller */ 445742af7e7SThierry Reding <0x0 0x60004100 0x0 0x40>, /* secondary controller */ 446742af7e7SThierry Reding <0x0 0x60004200 0x0 0x40>, /* tertiary controller */ 447742af7e7SThierry Reding <0x0 0x60004300 0x0 0x40>, /* quaternary controller */ 448742af7e7SThierry Reding <0x0 0x60004400 0x0 0x40>, /* quinary controller */ 449742af7e7SThierry Reding <0x0 0x60004500 0x0 0x40>; /* senary controller */ 450742af7e7SThierry Reding interrupt-controller; 451742af7e7SThierry Reding #interrupt-cells = <3>; 452742af7e7SThierry Reding interrupt-parent = <&gic>; 453742af7e7SThierry Reding }; 454742af7e7SThierry Reding 455be70771dSThierry Reding timer@60005000 { 456d9931a18SJoseph Lo compatible = "nvidia,tegra210-timer"; 457742af7e7SThierry Reding reg = <0x0 0x60005000 0x0 0x400>; 458d9931a18SJoseph Lo interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 459d9931a18SJoseph Lo <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 460742af7e7SThierry Reding <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 461742af7e7SThierry Reding <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 462742af7e7SThierry Reding <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 463742af7e7SThierry Reding <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 464d9931a18SJoseph Lo <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 465d9931a18SJoseph Lo <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 466d9931a18SJoseph Lo <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 467d9931a18SJoseph Lo <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 468d9931a18SJoseph Lo <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 469d9931a18SJoseph Lo <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 470d9931a18SJoseph Lo <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, 471d9931a18SJoseph Lo <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 472742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_TIMER>; 473742af7e7SThierry Reding clock-names = "timer"; 474742af7e7SThierry Reding }; 475742af7e7SThierry Reding 476be70771dSThierry Reding tegra_car: clock@60006000 { 477742af7e7SThierry Reding compatible = "nvidia,tegra210-car"; 478742af7e7SThierry Reding reg = <0x0 0x60006000 0x0 0x1000>; 479742af7e7SThierry Reding #clock-cells = <1>; 480742af7e7SThierry Reding #reset-cells = <1>; 481742af7e7SThierry Reding }; 482742af7e7SThierry Reding 483be70771dSThierry Reding flow-controller@60007000 { 484742af7e7SThierry Reding compatible = "nvidia,tegra210-flowctrl"; 485742af7e7SThierry Reding reg = <0x0 0x60007000 0x0 0x1000>; 486742af7e7SThierry Reding }; 487742af7e7SThierry Reding 488be70771dSThierry Reding gpio: gpio@6000d000 { 48901665512SStephen Warren compatible = "nvidia,tegra210-gpio", "nvidia,tegra30-gpio"; 490742af7e7SThierry Reding reg = <0x0 0x6000d000 0x0 0x1000>; 491742af7e7SThierry Reding interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 492742af7e7SThierry Reding <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 493742af7e7SThierry Reding <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 494742af7e7SThierry Reding <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 495742af7e7SThierry Reding <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 496742af7e7SThierry Reding <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 497742af7e7SThierry Reding <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 498742af7e7SThierry Reding <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 499742af7e7SThierry Reding #gpio-cells = <2>; 500742af7e7SThierry Reding gpio-controller; 501742af7e7SThierry Reding #interrupt-cells = <2>; 502742af7e7SThierry Reding interrupt-controller; 503742af7e7SThierry Reding }; 504742af7e7SThierry Reding 505be70771dSThierry Reding apbdma: dma@60020000 { 506742af7e7SThierry Reding compatible = "nvidia,tegra210-apbdma", "nvidia,tegra148-apbdma"; 507742af7e7SThierry Reding reg = <0x0 0x60020000 0x0 0x1400>; 508742af7e7SThierry Reding interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 509742af7e7SThierry Reding <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 510742af7e7SThierry Reding <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 511742af7e7SThierry Reding <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 512742af7e7SThierry Reding <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 513742af7e7SThierry Reding <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 514742af7e7SThierry Reding <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 515742af7e7SThierry Reding <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 516742af7e7SThierry Reding <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 517742af7e7SThierry Reding <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 518742af7e7SThierry Reding <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 519742af7e7SThierry Reding <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 520742af7e7SThierry Reding <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 521742af7e7SThierry Reding <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 522742af7e7SThierry Reding <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 523742af7e7SThierry Reding <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 524742af7e7SThierry Reding <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 525742af7e7SThierry Reding <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 526742af7e7SThierry Reding <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 527742af7e7SThierry Reding <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 528742af7e7SThierry Reding <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 529742af7e7SThierry Reding <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 530742af7e7SThierry Reding <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 531742af7e7SThierry Reding <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 532742af7e7SThierry Reding <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 533742af7e7SThierry Reding <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 534742af7e7SThierry Reding <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 535742af7e7SThierry Reding <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 536742af7e7SThierry Reding <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 537742af7e7SThierry Reding <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 538742af7e7SThierry Reding <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 539742af7e7SThierry Reding <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 540742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_APBDMA>; 541742af7e7SThierry Reding clock-names = "dma"; 542742af7e7SThierry Reding resets = <&tegra_car 34>; 543742af7e7SThierry Reding reset-names = "dma"; 544742af7e7SThierry Reding #dma-cells = <1>; 545742af7e7SThierry Reding }; 546742af7e7SThierry Reding 547be70771dSThierry Reding apbmisc@70000800 { 548742af7e7SThierry Reding compatible = "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc"; 549742af7e7SThierry Reding reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */ 55046e4b227SJoseph Lo <0x0 0x70000008 0x0 0x04>; /* Strapping options */ 551742af7e7SThierry Reding }; 552742af7e7SThierry Reding 553be70771dSThierry Reding pinmux: pinmux@700008d4 { 554742af7e7SThierry Reding compatible = "nvidia,tegra210-pinmux"; 555742af7e7SThierry Reding reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */ 556742af7e7SThierry Reding <0x0 0x70003000 0x0 0x294>; /* Mux registers */ 5574e0f1229SSowjanya Komatineni sdmmc1_3v3_drv: sdmmc1-3v3-drv { 5584e0f1229SSowjanya Komatineni sdmmc1 { 5594e0f1229SSowjanya Komatineni nvidia,pins = "drive_sdmmc1"; 5604e0f1229SSowjanya Komatineni nvidia,pull-down-strength = <0x8>; 5614e0f1229SSowjanya Komatineni nvidia,pull-up-strength = <0x8>; 5624e0f1229SSowjanya Komatineni }; 5634e0f1229SSowjanya Komatineni }; 5644e0f1229SSowjanya Komatineni sdmmc1_1v8_drv: sdmmc1-1v8-drv { 5654e0f1229SSowjanya Komatineni sdmmc1 { 5664e0f1229SSowjanya Komatineni nvidia,pins = "drive_sdmmc1"; 5674e0f1229SSowjanya Komatineni nvidia,pull-down-strength = <0x4>; 5684e0f1229SSowjanya Komatineni nvidia,pull-up-strength = <0x3>; 5694e0f1229SSowjanya Komatineni }; 5704e0f1229SSowjanya Komatineni }; 5714e0f1229SSowjanya Komatineni sdmmc2_1v8_drv: sdmmc2-1v8-drv { 5724e0f1229SSowjanya Komatineni sdmmc2 { 5734e0f1229SSowjanya Komatineni nvidia,pins = "drive_sdmmc2"; 5744e0f1229SSowjanya Komatineni nvidia,pull-down-strength = <0x10>; 5754e0f1229SSowjanya Komatineni nvidia,pull-up-strength = <0x10>; 5764e0f1229SSowjanya Komatineni }; 5774e0f1229SSowjanya Komatineni }; 5784e0f1229SSowjanya Komatineni sdmmc3_3v3_drv: sdmmc3-3v3-drv { 5794e0f1229SSowjanya Komatineni sdmmc3 { 5804e0f1229SSowjanya Komatineni nvidia,pins = "drive_sdmmc3"; 5814e0f1229SSowjanya Komatineni nvidia,pull-down-strength = <0x8>; 5824e0f1229SSowjanya Komatineni nvidia,pull-up-strength = <0x8>; 5834e0f1229SSowjanya Komatineni }; 5844e0f1229SSowjanya Komatineni }; 5854e0f1229SSowjanya Komatineni sdmmc3_1v8_drv: sdmmc3-1v8-drv { 5864e0f1229SSowjanya Komatineni sdmmc3 { 5874e0f1229SSowjanya Komatineni nvidia,pins = "drive_sdmmc3"; 5884e0f1229SSowjanya Komatineni nvidia,pull-down-strength = <0x4>; 5894e0f1229SSowjanya Komatineni nvidia,pull-up-strength = <0x3>; 5904e0f1229SSowjanya Komatineni }; 5914e0f1229SSowjanya Komatineni }; 5924e0f1229SSowjanya Komatineni sdmmc4_1v8_drv: sdmmc4-1v8-drv { 5934e0f1229SSowjanya Komatineni sdmmc4 { 5944e0f1229SSowjanya Komatineni nvidia,pins = "drive_sdmmc4"; 5954e0f1229SSowjanya Komatineni nvidia,pull-down-strength = <0x10>; 5964e0f1229SSowjanya Komatineni nvidia,pull-up-strength = <0x10>; 5974e0f1229SSowjanya Komatineni }; 5984e0f1229SSowjanya Komatineni }; 599742af7e7SThierry Reding }; 600742af7e7SThierry Reding 601742af7e7SThierry Reding /* 602742af7e7SThierry Reding * There are two serial driver i.e. 8250 based simple serial 603742af7e7SThierry Reding * driver and APB DMA based serial driver for higher baudrate 604ef769e32SAdam Buchbinder * and performance. To enable the 8250 based driver, the compatible 605742af7e7SThierry Reding * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable 60668cd8b2eSThierry Reding * the APB DMA based serial driver, the compatible is 607742af7e7SThierry Reding * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". 608742af7e7SThierry Reding */ 609be70771dSThierry Reding uarta: serial@70006000 { 610742af7e7SThierry Reding compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 611742af7e7SThierry Reding reg = <0x0 0x70006000 0x0 0x40>; 612742af7e7SThierry Reding reg-shift = <2>; 613742af7e7SThierry Reding interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 614742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_UARTA>; 615742af7e7SThierry Reding clock-names = "serial"; 616742af7e7SThierry Reding resets = <&tegra_car 6>; 617742af7e7SThierry Reding reset-names = "serial"; 618742af7e7SThierry Reding dmas = <&apbdma 8>, <&apbdma 8>; 619742af7e7SThierry Reding dma-names = "rx", "tx"; 620742af7e7SThierry Reding status = "disabled"; 621742af7e7SThierry Reding }; 622742af7e7SThierry Reding 623be70771dSThierry Reding uartb: serial@70006040 { 624742af7e7SThierry Reding compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 625742af7e7SThierry Reding reg = <0x0 0x70006040 0x0 0x40>; 626742af7e7SThierry Reding reg-shift = <2>; 627742af7e7SThierry Reding interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 628742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_UARTB>; 629742af7e7SThierry Reding clock-names = "serial"; 630742af7e7SThierry Reding resets = <&tegra_car 7>; 631742af7e7SThierry Reding reset-names = "serial"; 632742af7e7SThierry Reding dmas = <&apbdma 9>, <&apbdma 9>; 633742af7e7SThierry Reding dma-names = "rx", "tx"; 634742af7e7SThierry Reding status = "disabled"; 635742af7e7SThierry Reding }; 636742af7e7SThierry Reding 637be70771dSThierry Reding uartc: serial@70006200 { 638742af7e7SThierry Reding compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 639742af7e7SThierry Reding reg = <0x0 0x70006200 0x0 0x40>; 640742af7e7SThierry Reding reg-shift = <2>; 641742af7e7SThierry Reding interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 642742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_UARTC>; 643742af7e7SThierry Reding clock-names = "serial"; 644742af7e7SThierry Reding resets = <&tegra_car 55>; 645742af7e7SThierry Reding reset-names = "serial"; 646742af7e7SThierry Reding dmas = <&apbdma 10>, <&apbdma 10>; 647742af7e7SThierry Reding dma-names = "rx", "tx"; 648742af7e7SThierry Reding status = "disabled"; 649742af7e7SThierry Reding }; 650742af7e7SThierry Reding 651be70771dSThierry Reding uartd: serial@70006300 { 652742af7e7SThierry Reding compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 653742af7e7SThierry Reding reg = <0x0 0x70006300 0x0 0x40>; 654742af7e7SThierry Reding reg-shift = <2>; 655742af7e7SThierry Reding interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 656742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_UARTD>; 657742af7e7SThierry Reding clock-names = "serial"; 658742af7e7SThierry Reding resets = <&tegra_car 65>; 659742af7e7SThierry Reding reset-names = "serial"; 660742af7e7SThierry Reding dmas = <&apbdma 19>, <&apbdma 19>; 661742af7e7SThierry Reding dma-names = "rx", "tx"; 662742af7e7SThierry Reding status = "disabled"; 663742af7e7SThierry Reding }; 664742af7e7SThierry Reding 665be70771dSThierry Reding pwm: pwm@7000a000 { 666742af7e7SThierry Reding compatible = "nvidia,tegra210-pwm", "nvidia,tegra20-pwm"; 667742af7e7SThierry Reding reg = <0x0 0x7000a000 0x0 0x100>; 668742af7e7SThierry Reding #pwm-cells = <2>; 669742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_PWM>; 670742af7e7SThierry Reding resets = <&tegra_car 17>; 671742af7e7SThierry Reding reset-names = "pwm"; 672742af7e7SThierry Reding status = "disabled"; 673742af7e7SThierry Reding }; 674742af7e7SThierry Reding 675be70771dSThierry Reding i2c@7000c000 { 676140723b9SSowjanya Komatineni compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 677742af7e7SThierry Reding reg = <0x0 0x7000c000 0x0 0x100>; 678742af7e7SThierry Reding interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 679742af7e7SThierry Reding #address-cells = <1>; 680742af7e7SThierry Reding #size-cells = <0>; 681742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_I2C1>; 682742af7e7SThierry Reding clock-names = "div-clk"; 683742af7e7SThierry Reding resets = <&tegra_car 12>; 684742af7e7SThierry Reding reset-names = "i2c"; 685742af7e7SThierry Reding dmas = <&apbdma 21>, <&apbdma 21>; 686742af7e7SThierry Reding dma-names = "rx", "tx"; 687742af7e7SThierry Reding status = "disabled"; 688742af7e7SThierry Reding }; 689742af7e7SThierry Reding 690be70771dSThierry Reding i2c@7000c400 { 691140723b9SSowjanya Komatineni compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 692742af7e7SThierry Reding reg = <0x0 0x7000c400 0x0 0x100>; 693742af7e7SThierry Reding interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 694742af7e7SThierry Reding #address-cells = <1>; 695742af7e7SThierry Reding #size-cells = <0>; 696742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_I2C2>; 697742af7e7SThierry Reding clock-names = "div-clk"; 698742af7e7SThierry Reding resets = <&tegra_car 54>; 699742af7e7SThierry Reding reset-names = "i2c"; 700742af7e7SThierry Reding dmas = <&apbdma 22>, <&apbdma 22>; 701742af7e7SThierry Reding dma-names = "rx", "tx"; 702742af7e7SThierry Reding status = "disabled"; 703742af7e7SThierry Reding }; 704742af7e7SThierry Reding 705be70771dSThierry Reding i2c@7000c500 { 706140723b9SSowjanya Komatineni compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 707742af7e7SThierry Reding reg = <0x0 0x7000c500 0x0 0x100>; 708742af7e7SThierry Reding interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 709742af7e7SThierry Reding #address-cells = <1>; 710742af7e7SThierry Reding #size-cells = <0>; 711742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_I2C3>; 712742af7e7SThierry Reding clock-names = "div-clk"; 713742af7e7SThierry Reding resets = <&tegra_car 67>; 714742af7e7SThierry Reding reset-names = "i2c"; 715742af7e7SThierry Reding dmas = <&apbdma 23>, <&apbdma 23>; 716742af7e7SThierry Reding dma-names = "rx", "tx"; 717742af7e7SThierry Reding status = "disabled"; 718742af7e7SThierry Reding }; 719742af7e7SThierry Reding 720be70771dSThierry Reding i2c@7000c700 { 721140723b9SSowjanya Komatineni compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 722742af7e7SThierry Reding reg = <0x0 0x7000c700 0x0 0x100>; 723742af7e7SThierry Reding interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 724742af7e7SThierry Reding #address-cells = <1>; 725742af7e7SThierry Reding #size-cells = <0>; 726742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_I2C4>; 727742af7e7SThierry Reding clock-names = "div-clk"; 728742af7e7SThierry Reding resets = <&tegra_car 103>; 729742af7e7SThierry Reding reset-names = "i2c"; 730742af7e7SThierry Reding dmas = <&apbdma 26>, <&apbdma 26>; 731742af7e7SThierry Reding dma-names = "rx", "tx"; 73266b2d6e9SJon Hunter pinctrl-0 = <&state_dpaux1_i2c>; 73366b2d6e9SJon Hunter pinctrl-1 = <&state_dpaux1_off>; 73466b2d6e9SJon Hunter pinctrl-names = "default", "idle"; 735742af7e7SThierry Reding status = "disabled"; 736742af7e7SThierry Reding }; 737742af7e7SThierry Reding 738be70771dSThierry Reding i2c@7000d000 { 739140723b9SSowjanya Komatineni compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 740742af7e7SThierry Reding reg = <0x0 0x7000d000 0x0 0x100>; 741742af7e7SThierry Reding interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 742742af7e7SThierry Reding #address-cells = <1>; 743742af7e7SThierry Reding #size-cells = <0>; 744742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_I2C5>; 745742af7e7SThierry Reding clock-names = "div-clk"; 746742af7e7SThierry Reding resets = <&tegra_car 47>; 747742af7e7SThierry Reding reset-names = "i2c"; 748742af7e7SThierry Reding dmas = <&apbdma 24>, <&apbdma 24>; 749742af7e7SThierry Reding dma-names = "rx", "tx"; 750742af7e7SThierry Reding status = "disabled"; 751742af7e7SThierry Reding }; 752742af7e7SThierry Reding 753be70771dSThierry Reding i2c@7000d100 { 754140723b9SSowjanya Komatineni compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 755742af7e7SThierry Reding reg = <0x0 0x7000d100 0x0 0x100>; 756742af7e7SThierry Reding interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 757742af7e7SThierry Reding #address-cells = <1>; 758742af7e7SThierry Reding #size-cells = <0>; 759742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_I2C6>; 760742af7e7SThierry Reding clock-names = "div-clk"; 761742af7e7SThierry Reding resets = <&tegra_car 166>; 762742af7e7SThierry Reding reset-names = "i2c"; 763742af7e7SThierry Reding dmas = <&apbdma 30>, <&apbdma 30>; 764742af7e7SThierry Reding dma-names = "rx", "tx"; 76566b2d6e9SJon Hunter pinctrl-0 = <&state_dpaux_i2c>; 76666b2d6e9SJon Hunter pinctrl-1 = <&state_dpaux_off>; 76766b2d6e9SJon Hunter pinctrl-names = "default", "idle"; 768742af7e7SThierry Reding status = "disabled"; 769742af7e7SThierry Reding }; 770742af7e7SThierry Reding 771be70771dSThierry Reding spi@7000d400 { 772742af7e7SThierry Reding compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 773742af7e7SThierry Reding reg = <0x0 0x7000d400 0x0 0x200>; 774742af7e7SThierry Reding interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 775742af7e7SThierry Reding #address-cells = <1>; 776742af7e7SThierry Reding #size-cells = <0>; 777742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_SBC1>; 778742af7e7SThierry Reding clock-names = "spi"; 779742af7e7SThierry Reding resets = <&tegra_car 41>; 780742af7e7SThierry Reding reset-names = "spi"; 781742af7e7SThierry Reding dmas = <&apbdma 15>, <&apbdma 15>; 782742af7e7SThierry Reding dma-names = "rx", "tx"; 783742af7e7SThierry Reding status = "disabled"; 784742af7e7SThierry Reding }; 785742af7e7SThierry Reding 786be70771dSThierry Reding spi@7000d600 { 787742af7e7SThierry Reding compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 788742af7e7SThierry Reding reg = <0x0 0x7000d600 0x0 0x200>; 789742af7e7SThierry Reding interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 790742af7e7SThierry Reding #address-cells = <1>; 791742af7e7SThierry Reding #size-cells = <0>; 792742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_SBC2>; 793742af7e7SThierry Reding clock-names = "spi"; 794742af7e7SThierry Reding resets = <&tegra_car 44>; 795742af7e7SThierry Reding reset-names = "spi"; 796742af7e7SThierry Reding dmas = <&apbdma 16>, <&apbdma 16>; 797742af7e7SThierry Reding dma-names = "rx", "tx"; 798742af7e7SThierry Reding status = "disabled"; 799742af7e7SThierry Reding }; 800742af7e7SThierry Reding 801be70771dSThierry Reding spi@7000d800 { 802742af7e7SThierry Reding compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 803742af7e7SThierry Reding reg = <0x0 0x7000d800 0x0 0x200>; 804742af7e7SThierry Reding interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 805742af7e7SThierry Reding #address-cells = <1>; 806742af7e7SThierry Reding #size-cells = <0>; 807742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_SBC3>; 808742af7e7SThierry Reding clock-names = "spi"; 809742af7e7SThierry Reding resets = <&tegra_car 46>; 810742af7e7SThierry Reding reset-names = "spi"; 811742af7e7SThierry Reding dmas = <&apbdma 17>, <&apbdma 17>; 812742af7e7SThierry Reding dma-names = "rx", "tx"; 813742af7e7SThierry Reding status = "disabled"; 814742af7e7SThierry Reding }; 815742af7e7SThierry Reding 816be70771dSThierry Reding spi@7000da00 { 817742af7e7SThierry Reding compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 818742af7e7SThierry Reding reg = <0x0 0x7000da00 0x0 0x200>; 819742af7e7SThierry Reding interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 820742af7e7SThierry Reding #address-cells = <1>; 821742af7e7SThierry Reding #size-cells = <0>; 822742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_SBC4>; 823742af7e7SThierry Reding clock-names = "spi"; 824742af7e7SThierry Reding resets = <&tegra_car 68>; 825742af7e7SThierry Reding reset-names = "spi"; 826742af7e7SThierry Reding dmas = <&apbdma 18>, <&apbdma 18>; 827742af7e7SThierry Reding dma-names = "rx", "tx"; 828742af7e7SThierry Reding status = "disabled"; 829742af7e7SThierry Reding }; 830742af7e7SThierry Reding 831be70771dSThierry Reding rtc@7000e000 { 832742af7e7SThierry Reding compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc"; 833742af7e7SThierry Reding reg = <0x0 0x7000e000 0x0 0x100>; 834d13c13f4SSowjanya Komatineni interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; 835359ae651SSowjanya Komatineni interrupt-parent = <&tegra_pmc>; 836742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_RTC>; 837742af7e7SThierry Reding clock-names = "rtc"; 838742af7e7SThierry Reding }; 839742af7e7SThierry Reding 840359ae651SSowjanya Komatineni tegra_pmc: pmc@7000e400 { 841742af7e7SThierry Reding compatible = "nvidia,tegra210-pmc"; 842742af7e7SThierry Reding reg = <0x0 0x7000e400 0x0 0x400>; 843742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; 844742af7e7SThierry Reding clock-names = "pclk", "clk32k_in"; 845359ae651SSowjanya Komatineni #clock-cells = <1>; 846d13c13f4SSowjanya Komatineni #interrupt-cells = <2>; 847d13c13f4SSowjanya Komatineni interrupt-controller; 848c2b82445SJon Hunter 849c2b82445SJon Hunter powergates { 850c2b82445SJon Hunter pd_audio: aud { 851c2b82445SJon Hunter clocks = <&tegra_car TEGRA210_CLK_APE>, 852c2b82445SJon Hunter <&tegra_car TEGRA210_CLK_APB2APE>; 853c2b82445SJon Hunter resets = <&tegra_car 198>; 854c2b82445SJon Hunter #power-domain-cells = <0>; 855c2b82445SJon Hunter }; 856241f02baSJon Hunter 85796d1f078SJon Hunter pd_sor: sor { 85896d1f078SJon Hunter clocks = <&tegra_car TEGRA210_CLK_SOR0>, 85996d1f078SJon Hunter <&tegra_car TEGRA210_CLK_SOR1>, 860b4f99176SSowjanya Komatineni <&tegra_car TEGRA210_CLK_CILAB>, 861b4f99176SSowjanya Komatineni <&tegra_car TEGRA210_CLK_CILCD>, 862b4f99176SSowjanya Komatineni <&tegra_car TEGRA210_CLK_CILE>, 86396d1f078SJon Hunter <&tegra_car TEGRA210_CLK_DSIA>, 86496d1f078SJon Hunter <&tegra_car TEGRA210_CLK_DSIB>, 86596d1f078SJon Hunter <&tegra_car TEGRA210_CLK_DPAUX>, 86696d1f078SJon Hunter <&tegra_car TEGRA210_CLK_DPAUX1>, 86796d1f078SJon Hunter <&tegra_car TEGRA210_CLK_MIPI_CAL>; 86896d1f078SJon Hunter resets = <&tegra_car TEGRA210_CLK_SOR0>, 86996d1f078SJon Hunter <&tegra_car TEGRA210_CLK_SOR1>, 87096d1f078SJon Hunter <&tegra_car TEGRA210_CLK_DSIA>, 87196d1f078SJon Hunter <&tegra_car TEGRA210_CLK_DSIB>, 87296d1f078SJon Hunter <&tegra_car TEGRA210_CLK_DPAUX>, 87396d1f078SJon Hunter <&tegra_car TEGRA210_CLK_DPAUX1>, 87496d1f078SJon Hunter <&tegra_car TEGRA210_CLK_MIPI_CAL>; 87596d1f078SJon Hunter #power-domain-cells = <0>; 87696d1f078SJon Hunter }; 87796d1f078SJon Hunter 878241f02baSJon Hunter pd_xusbss: xusba { 879241f02baSJon Hunter clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>; 880241f02baSJon Hunter resets = <&tegra_car TEGRA210_CLK_XUSB_SS>; 881241f02baSJon Hunter #power-domain-cells = <0>; 882241f02baSJon Hunter }; 883241f02baSJon Hunter 884241f02baSJon Hunter pd_xusbdev: xusbb { 885241f02baSJon Hunter clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>; 886241f02baSJon Hunter resets = <&tegra_car 95>; 887241f02baSJon Hunter #power-domain-cells = <0>; 888241f02baSJon Hunter }; 889241f02baSJon Hunter 890241f02baSJon Hunter pd_xusbhost: xusbc { 891241f02baSJon Hunter clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>; 892241f02baSJon Hunter resets = <&tegra_car TEGRA210_CLK_XUSB_HOST>; 893241f02baSJon Hunter #power-domain-cells = <0>; 894241f02baSJon Hunter }; 89524963d1bSMikko Perttunen 89624963d1bSMikko Perttunen pd_vic: vic { 89724963d1bSMikko Perttunen clocks = <&tegra_car TEGRA210_CLK_VIC03>; 89824963d1bSMikko Perttunen clock-names = "vic"; 89924963d1bSMikko Perttunen resets = <&tegra_car 178>; 90024963d1bSMikko Perttunen reset-names = "vic"; 90124963d1bSMikko Perttunen #power-domain-cells = <0>; 90224963d1bSMikko Perttunen }; 903c4153885SSowjanya Komatineni 904c4153885SSowjanya Komatineni pd_venc: venc { 905c4153885SSowjanya Komatineni clocks = <&tegra_car TEGRA210_CLK_VI>, 906c4153885SSowjanya Komatineni <&tegra_car TEGRA210_CLK_CSI>; 907c4153885SSowjanya Komatineni resets = <&mc TEGRA210_MC_RESET_VI>, 908c4153885SSowjanya Komatineni <&tegra_car 20>, 909c4153885SSowjanya Komatineni <&tegra_car 52>; 910c4153885SSowjanya Komatineni #power-domain-cells = <0>; 911c4153885SSowjanya Komatineni }; 912c2b82445SJon Hunter }; 9136641af7eSAapo Vienamo 914*85ab13c1SThierry Reding pinmux { 9156641af7eSAapo Vienamo sdmmc1_3v3: sdmmc1-3v3 { 9166641af7eSAapo Vienamo pins = "sdmmc1"; 9176641af7eSAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 9186641af7eSAapo Vienamo }; 9196641af7eSAapo Vienamo 9206641af7eSAapo Vienamo sdmmc1_1v8: sdmmc1-1v8 { 9216641af7eSAapo Vienamo pins = "sdmmc1"; 9226641af7eSAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 9236641af7eSAapo Vienamo }; 9246641af7eSAapo Vienamo 9256641af7eSAapo Vienamo sdmmc3_3v3: sdmmc3-3v3 { 9266641af7eSAapo Vienamo pins = "sdmmc3"; 9276641af7eSAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 9286641af7eSAapo Vienamo }; 9296641af7eSAapo Vienamo 9306641af7eSAapo Vienamo sdmmc3_1v8: sdmmc3-1v8 { 9316641af7eSAapo Vienamo pins = "sdmmc3"; 9326641af7eSAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 9336641af7eSAapo Vienamo }; 934871be845SManikanta Maddireddy 935*85ab13c1SThierry Reding pex_dpd_disable: pex-dpd-disable { 936871be845SManikanta Maddireddy pins = "pex-bias", "pex-clk1", "pex-clk2"; 937871be845SManikanta Maddireddy low-power-disable; 938871be845SManikanta Maddireddy }; 939871be845SManikanta Maddireddy 940*85ab13c1SThierry Reding pex_dpd_enable: pex-dpd-enable { 941871be845SManikanta Maddireddy pins = "pex-bias", "pex-clk1", "pex-clk2"; 942871be845SManikanta Maddireddy low-power-enable; 943871be845SManikanta Maddireddy }; 944871be845SManikanta Maddireddy }; 945742af7e7SThierry Reding }; 946742af7e7SThierry Reding 947be70771dSThierry Reding fuse@7000f800 { 948742af7e7SThierry Reding compatible = "nvidia,tegra210-efuse"; 949742af7e7SThierry Reding reg = <0x0 0x7000f800 0x0 0x400>; 950742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_FUSE>; 951742af7e7SThierry Reding clock-names = "fuse"; 952742af7e7SThierry Reding resets = <&tegra_car 39>; 953742af7e7SThierry Reding reset-names = "fuse"; 954742af7e7SThierry Reding }; 955742af7e7SThierry Reding 956be70771dSThierry Reding mc: memory-controller@70019000 { 957742af7e7SThierry Reding compatible = "nvidia,tegra210-mc"; 958742af7e7SThierry Reding reg = <0x0 0x70019000 0x0 0x1000>; 959742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_MC>; 960742af7e7SThierry Reding clock-names = "mc"; 961742af7e7SThierry Reding 962742af7e7SThierry Reding interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 963742af7e7SThierry Reding 964742af7e7SThierry Reding #iommu-cells = <1>; 9652eb8e1a4SSowjanya Komatineni #reset-cells = <1>; 966742af7e7SThierry Reding }; 967742af7e7SThierry Reding 968e12325f6SThierry Reding emc: external-memory-controller@7001b000 { 969cd9350c5SJoseph Lo compatible = "nvidia,tegra210-emc"; 970cd9350c5SJoseph Lo reg = <0x0 0x7001b000 0x0 0x1000>, 971cd9350c5SJoseph Lo <0x0 0x7001e000 0x0 0x1000>, 972cd9350c5SJoseph Lo <0x0 0x7001f000 0x0 0x1000>; 973cd9350c5SJoseph Lo clocks = <&tegra_car TEGRA210_CLK_EMC>; 974cd9350c5SJoseph Lo clock-names = "emc"; 975cd9350c5SJoseph Lo interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 976cd9350c5SJoseph Lo nvidia,memory-controller = <&mc>; 977e12325f6SThierry Reding #cooling-cells = <2>; 978cd9350c5SJoseph Lo }; 979cd9350c5SJoseph Lo 9806cb60ec4SPreetham Ramchandra sata@70020000 { 9816cb60ec4SPreetham Ramchandra compatible = "nvidia,tegra210-ahci"; 9826cb60ec4SPreetham Ramchandra reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */ 9836cb60ec4SPreetham Ramchandra <0x0 0x70020000 0x0 0x7000>, /* SATA */ 9846cb60ec4SPreetham Ramchandra <0x0 0x70001100 0x0 0x1000>; /* SATA AUX */ 9856cb60ec4SPreetham Ramchandra interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 9866cb60ec4SPreetham Ramchandra clocks = <&tegra_car TEGRA210_CLK_SATA>, 9876cb60ec4SPreetham Ramchandra <&tegra_car TEGRA210_CLK_SATA_OOB>; 9886cb60ec4SPreetham Ramchandra clock-names = "sata", "sata-oob"; 9896cb60ec4SPreetham Ramchandra resets = <&tegra_car 124>, 990c84ebdfdSSowjanya Komatineni <&tegra_car 129>, 991c84ebdfdSSowjanya Komatineni <&tegra_car 123>; 992c84ebdfdSSowjanya Komatineni reset-names = "sata", "sata-cold", "sata-oob"; 9936cb60ec4SPreetham Ramchandra status = "disabled"; 9946cb60ec4SPreetham Ramchandra }; 9956cb60ec4SPreetham Ramchandra 996be70771dSThierry Reding hda@70030000 { 997742af7e7SThierry Reding compatible = "nvidia,tegra210-hda", "nvidia,tegra30-hda"; 998742af7e7SThierry Reding reg = <0x0 0x70030000 0x0 0x10000>; 999742af7e7SThierry Reding interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 1000742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_HDA>, 1001742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_HDA2HDMI>, 1002742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_HDA2CODEC_2X>; 1003742af7e7SThierry Reding clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 1004742af7e7SThierry Reding resets = <&tegra_car 125>, /* hda */ 1005742af7e7SThierry Reding <&tegra_car 128>, /* hda2hdmi */ 1006742af7e7SThierry Reding <&tegra_car 111>; /* hda2codec_2x */ 1007742af7e7SThierry Reding reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 10081e0ca546SSameer Pujar power-domains = <&pd_sor>; 1009742af7e7SThierry Reding status = "disabled"; 1010742af7e7SThierry Reding }; 1011742af7e7SThierry Reding 1012e7a99ac2SThierry Reding usb@70090000 { 1013e7a99ac2SThierry Reding compatible = "nvidia,tegra210-xusb"; 1014e7a99ac2SThierry Reding reg = <0x0 0x70090000 0x0 0x8000>, 1015e7a99ac2SThierry Reding <0x0 0x70098000 0x0 0x1000>, 1016e7a99ac2SThierry Reding <0x0 0x70099000 0x0 0x1000>; 1017e7a99ac2SThierry Reding reg-names = "hcd", "fpci", "ipfs"; 1018e7a99ac2SThierry Reding 1019e7a99ac2SThierry Reding interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 10209168e1dbSJon Hunter <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 1021e7a99ac2SThierry Reding 1022e7a99ac2SThierry Reding clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>, 1023e7a99ac2SThierry Reding <&tegra_car TEGRA210_CLK_XUSB_HOST_SRC>, 1024e7a99ac2SThierry Reding <&tegra_car TEGRA210_CLK_XUSB_FALCON_SRC>, 1025e7a99ac2SThierry Reding <&tegra_car TEGRA210_CLK_XUSB_SS>, 1026d19532e6SThierry Reding <&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>, 1027f2ef6a91SThierry Reding <&tegra_car TEGRA210_CLK_XUSB_SS_SRC>, 1028e7a99ac2SThierry Reding <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>, 1029e7a99ac2SThierry Reding <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>, 1030e7a99ac2SThierry Reding <&tegra_car TEGRA210_CLK_PLL_U_480M>, 1031e7a99ac2SThierry Reding <&tegra_car TEGRA210_CLK_CLK_M>, 1032e7a99ac2SThierry Reding <&tegra_car TEGRA210_CLK_PLL_E>; 1033e7a99ac2SThierry Reding clock-names = "xusb_host", "xusb_host_src", 1034e7a99ac2SThierry Reding "xusb_falcon_src", "xusb_ss", 1035f2ef6a91SThierry Reding "xusb_ss_div2", "xusb_ss_src", 1036e7a99ac2SThierry Reding "xusb_hs_src", "xusb_fs_src", 1037e7a99ac2SThierry Reding "pll_u_480m", "clk_m", "pll_e"; 1038e7a99ac2SThierry Reding resets = <&tegra_car 89>, <&tegra_car 156>, 1039e7a99ac2SThierry Reding <&tegra_car 143>; 1040e7a99ac2SThierry Reding reset-names = "xusb_host", "xusb_ss", "xusb_src"; 104136ec29f7SJon Hunter power-domains = <&pd_xusbhost>, <&pd_xusbss>; 104236ec29f7SJon Hunter power-domain-names = "xusb_host", "xusb_ss"; 1043e7a99ac2SThierry Reding 1044e7a99ac2SThierry Reding nvidia,xusb-padctl = <&padctl>; 1045e7a99ac2SThierry Reding 1046e7a99ac2SThierry Reding status = "disabled"; 1047e7a99ac2SThierry Reding }; 1048e7a99ac2SThierry Reding 10494e07ac90SThierry Reding padctl: padctl@7009f000 { 10504e07ac90SThierry Reding compatible = "nvidia,tegra210-xusb-padctl"; 10514e07ac90SThierry Reding reg = <0x0 0x7009f000 0x0 0x1000>; 10526450da3dSJC Kuo interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 10534e07ac90SThierry Reding resets = <&tegra_car 142>; 10544e07ac90SThierry Reding reset-names = "padctl"; 10554ff5e30dSJC Kuo nvidia,pmc = <&tegra_pmc>; 10564e07ac90SThierry Reding 10574e07ac90SThierry Reding status = "disabled"; 10584e07ac90SThierry Reding 10594e07ac90SThierry Reding pads { 10604e07ac90SThierry Reding usb2 { 10614e07ac90SThierry Reding clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>; 10624e07ac90SThierry Reding clock-names = "trk"; 10634e07ac90SThierry Reding status = "disabled"; 10644e07ac90SThierry Reding 10654e07ac90SThierry Reding lanes { 10664e07ac90SThierry Reding usb2-0 { 10674e07ac90SThierry Reding status = "disabled"; 10684e07ac90SThierry Reding #phy-cells = <0>; 10694e07ac90SThierry Reding }; 10704e07ac90SThierry Reding 10714e07ac90SThierry Reding usb2-1 { 10724e07ac90SThierry Reding status = "disabled"; 10734e07ac90SThierry Reding #phy-cells = <0>; 10744e07ac90SThierry Reding }; 10754e07ac90SThierry Reding 10764e07ac90SThierry Reding usb2-2 { 10774e07ac90SThierry Reding status = "disabled"; 10784e07ac90SThierry Reding #phy-cells = <0>; 10794e07ac90SThierry Reding }; 10804e07ac90SThierry Reding 10814e07ac90SThierry Reding usb2-3 { 10824e07ac90SThierry Reding status = "disabled"; 10834e07ac90SThierry Reding #phy-cells = <0>; 10844e07ac90SThierry Reding }; 10854e07ac90SThierry Reding }; 10864e07ac90SThierry Reding }; 10874e07ac90SThierry Reding 10884e07ac90SThierry Reding hsic { 10894e07ac90SThierry Reding clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>; 10904e07ac90SThierry Reding clock-names = "trk"; 10914e07ac90SThierry Reding status = "disabled"; 10924e07ac90SThierry Reding 10934e07ac90SThierry Reding lanes { 10944e07ac90SThierry Reding hsic-0 { 10954e07ac90SThierry Reding status = "disabled"; 10964e07ac90SThierry Reding #phy-cells = <0>; 10974e07ac90SThierry Reding }; 10984e07ac90SThierry Reding 10994e07ac90SThierry Reding hsic-1 { 11004e07ac90SThierry Reding status = "disabled"; 11014e07ac90SThierry Reding #phy-cells = <0>; 11024e07ac90SThierry Reding }; 11034e07ac90SThierry Reding }; 11044e07ac90SThierry Reding }; 11054e07ac90SThierry Reding 11064e07ac90SThierry Reding pcie { 11074e07ac90SThierry Reding clocks = <&tegra_car TEGRA210_CLK_PLL_E>; 11084e07ac90SThierry Reding clock-names = "pll"; 11094e07ac90SThierry Reding resets = <&tegra_car 205>; 11104e07ac90SThierry Reding reset-names = "phy"; 11114e07ac90SThierry Reding status = "disabled"; 11124e07ac90SThierry Reding 11134e07ac90SThierry Reding lanes { 11144e07ac90SThierry Reding pcie-0 { 11154e07ac90SThierry Reding status = "disabled"; 11164e07ac90SThierry Reding #phy-cells = <0>; 11174e07ac90SThierry Reding }; 11184e07ac90SThierry Reding 11194e07ac90SThierry Reding pcie-1 { 11204e07ac90SThierry Reding status = "disabled"; 11214e07ac90SThierry Reding #phy-cells = <0>; 11224e07ac90SThierry Reding }; 11234e07ac90SThierry Reding 11244e07ac90SThierry Reding pcie-2 { 11254e07ac90SThierry Reding status = "disabled"; 11264e07ac90SThierry Reding #phy-cells = <0>; 11274e07ac90SThierry Reding }; 11284e07ac90SThierry Reding 11294e07ac90SThierry Reding pcie-3 { 11304e07ac90SThierry Reding status = "disabled"; 11314e07ac90SThierry Reding #phy-cells = <0>; 11324e07ac90SThierry Reding }; 11334e07ac90SThierry Reding 11344e07ac90SThierry Reding pcie-4 { 11354e07ac90SThierry Reding status = "disabled"; 11364e07ac90SThierry Reding #phy-cells = <0>; 11374e07ac90SThierry Reding }; 11384e07ac90SThierry Reding 11394e07ac90SThierry Reding pcie-5 { 11404e07ac90SThierry Reding status = "disabled"; 11414e07ac90SThierry Reding #phy-cells = <0>; 11424e07ac90SThierry Reding }; 11434e07ac90SThierry Reding 11444e07ac90SThierry Reding pcie-6 { 11454e07ac90SThierry Reding status = "disabled"; 11464e07ac90SThierry Reding #phy-cells = <0>; 11474e07ac90SThierry Reding }; 11484e07ac90SThierry Reding }; 11494e07ac90SThierry Reding }; 11504e07ac90SThierry Reding 11514e07ac90SThierry Reding sata { 11524e07ac90SThierry Reding clocks = <&tegra_car TEGRA210_CLK_PLL_E>; 11534e07ac90SThierry Reding clock-names = "pll"; 11544e07ac90SThierry Reding resets = <&tegra_car 204>; 11554e07ac90SThierry Reding reset-names = "phy"; 11564e07ac90SThierry Reding status = "disabled"; 11574e07ac90SThierry Reding 11584e07ac90SThierry Reding lanes { 11594e07ac90SThierry Reding sata-0 { 11604e07ac90SThierry Reding status = "disabled"; 11614e07ac90SThierry Reding #phy-cells = <0>; 11624e07ac90SThierry Reding }; 11634e07ac90SThierry Reding }; 11644e07ac90SThierry Reding }; 11654e07ac90SThierry Reding }; 11664e07ac90SThierry Reding 11674e07ac90SThierry Reding ports { 11684e07ac90SThierry Reding usb2-0 { 11694e07ac90SThierry Reding status = "disabled"; 11704e07ac90SThierry Reding }; 11714e07ac90SThierry Reding 11724e07ac90SThierry Reding usb2-1 { 11734e07ac90SThierry Reding status = "disabled"; 11744e07ac90SThierry Reding }; 11754e07ac90SThierry Reding 11764e07ac90SThierry Reding usb2-2 { 11774e07ac90SThierry Reding status = "disabled"; 11784e07ac90SThierry Reding }; 11794e07ac90SThierry Reding 11804e07ac90SThierry Reding usb2-3 { 11814e07ac90SThierry Reding status = "disabled"; 11824e07ac90SThierry Reding }; 11834e07ac90SThierry Reding 11844e07ac90SThierry Reding hsic-0 { 11854e07ac90SThierry Reding status = "disabled"; 11864e07ac90SThierry Reding }; 11874e07ac90SThierry Reding 11884e07ac90SThierry Reding usb3-0 { 11894e07ac90SThierry Reding status = "disabled"; 11904e07ac90SThierry Reding }; 11914e07ac90SThierry Reding 11924e07ac90SThierry Reding usb3-1 { 11934e07ac90SThierry Reding status = "disabled"; 11944e07ac90SThierry Reding }; 11954e07ac90SThierry Reding 11964e07ac90SThierry Reding usb3-2 { 11974e07ac90SThierry Reding status = "disabled"; 11984e07ac90SThierry Reding }; 11994e07ac90SThierry Reding 12004e07ac90SThierry Reding usb3-3 { 12014e07ac90SThierry Reding status = "disabled"; 12024e07ac90SThierry Reding }; 12034e07ac90SThierry Reding }; 12044e07ac90SThierry Reding }; 12054e07ac90SThierry Reding 120667bb17f6SThierry Reding mmc@700b0000 { 1207b3fa0e03SThierry Reding compatible = "nvidia,tegra210-sdhci"; 1208742af7e7SThierry Reding reg = <0x0 0x700b0000 0x0 0x200>; 1209742af7e7SThierry Reding interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1210679f71faSSowjanya Komatineni clocks = <&tegra_car TEGRA210_CLK_SDMMC1>, 1211679f71faSSowjanya Komatineni <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>; 1212679f71faSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 1213742af7e7SThierry Reding resets = <&tegra_car 14>; 1214742af7e7SThierry Reding reset-names = "sdhci"; 12154e0f1229SSowjanya Komatineni pinctrl-names = "sdmmc-3v3", "sdmmc-1v8", 12164e0f1229SSowjanya Komatineni "sdmmc-3v3-drv", "sdmmc-1v8-drv"; 12176641af7eSAapo Vienamo pinctrl-0 = <&sdmmc1_3v3>; 12186641af7eSAapo Vienamo pinctrl-1 = <&sdmmc1_1v8>; 12194e0f1229SSowjanya Komatineni pinctrl-2 = <&sdmmc1_3v3_drv>; 12204e0f1229SSowjanya Komatineni pinctrl-3 = <&sdmmc1_1v8_drv>; 12211ea06718SAapo Vienamo nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>; 12221ea06718SAapo Vienamo nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>; 12231ea06718SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>; 12241ea06718SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>; 122563af8bcdSAapo Vienamo nvidia,default-tap = <0x2>; 122663af8bcdSAapo Vienamo nvidia,default-trim = <0x4>; 1227918f9671SAapo Vienamo assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>, 1228918f9671SAapo Vienamo <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>, 1229918f9671SAapo Vienamo <&tegra_car TEGRA210_CLK_PLL_C4>; 1230918f9671SAapo Vienamo assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 1231918f9671SAapo Vienamo assigned-clock-rates = <200000000>, <1000000000>, <1000000000>; 1232742af7e7SThierry Reding status = "disabled"; 1233742af7e7SThierry Reding }; 1234742af7e7SThierry Reding 123567bb17f6SThierry Reding mmc@700b0200 { 1236b3fa0e03SThierry Reding compatible = "nvidia,tegra210-sdhci"; 1237742af7e7SThierry Reding reg = <0x0 0x700b0200 0x0 0x200>; 1238742af7e7SThierry Reding interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 1239679f71faSSowjanya Komatineni clocks = <&tegra_car TEGRA210_CLK_SDMMC2>, 1240679f71faSSowjanya Komatineni <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>; 1241679f71faSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 1242742af7e7SThierry Reding resets = <&tegra_car 9>; 1243742af7e7SThierry Reding reset-names = "sdhci"; 12444e0f1229SSowjanya Komatineni pinctrl-names = "sdmmc-1v8-drv"; 12454e0f1229SSowjanya Komatineni pinctrl-0 = <&sdmmc2_1v8_drv>; 12461ea06718SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>; 12471ea06718SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>; 124863af8bcdSAapo Vienamo nvidia,default-tap = <0x8>; 124963af8bcdSAapo Vienamo nvidia,default-trim = <0x0>; 1250742af7e7SThierry Reding status = "disabled"; 1251742af7e7SThierry Reding }; 1252742af7e7SThierry Reding 125367bb17f6SThierry Reding mmc@700b0400 { 1254b3fa0e03SThierry Reding compatible = "nvidia,tegra210-sdhci"; 1255742af7e7SThierry Reding reg = <0x0 0x700b0400 0x0 0x200>; 1256742af7e7SThierry Reding interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 1257679f71faSSowjanya Komatineni clocks = <&tegra_car TEGRA210_CLK_SDMMC3>, 1258679f71faSSowjanya Komatineni <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>; 1259679f71faSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 1260742af7e7SThierry Reding resets = <&tegra_car 69>; 1261742af7e7SThierry Reding reset-names = "sdhci"; 12624e0f1229SSowjanya Komatineni pinctrl-names = "sdmmc-3v3", "sdmmc-1v8", 12634e0f1229SSowjanya Komatineni "sdmmc-3v3-drv", "sdmmc-1v8-drv"; 12646641af7eSAapo Vienamo pinctrl-0 = <&sdmmc3_3v3>; 12656641af7eSAapo Vienamo pinctrl-1 = <&sdmmc3_1v8>; 12664e0f1229SSowjanya Komatineni pinctrl-2 = <&sdmmc3_3v3_drv>; 12674e0f1229SSowjanya Komatineni pinctrl-3 = <&sdmmc3_1v8_drv>; 12681ea06718SAapo Vienamo nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>; 12691ea06718SAapo Vienamo nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>; 12701ea06718SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>; 12711ea06718SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>; 127263af8bcdSAapo Vienamo nvidia,default-tap = <0x3>; 127363af8bcdSAapo Vienamo nvidia,default-trim = <0x3>; 1274742af7e7SThierry Reding status = "disabled"; 1275742af7e7SThierry Reding }; 1276742af7e7SThierry Reding 127767bb17f6SThierry Reding mmc@700b0600 { 1278b3fa0e03SThierry Reding compatible = "nvidia,tegra210-sdhci"; 1279742af7e7SThierry Reding reg = <0x0 0x700b0600 0x0 0x200>; 1280742af7e7SThierry Reding interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1281679f71faSSowjanya Komatineni clocks = <&tegra_car TEGRA210_CLK_SDMMC4>, 1282679f71faSSowjanya Komatineni <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>; 1283679f71faSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 1284742af7e7SThierry Reding resets = <&tegra_car 15>; 1285742af7e7SThierry Reding reset-names = "sdhci"; 12864e0f1229SSowjanya Komatineni pinctrl-names = "sdmmc-3v3-drv", "sdmmc-1v8-drv"; 12874e0f1229SSowjanya Komatineni pinctrl-0 = <&sdmmc4_1v8_drv>; 12884e0f1229SSowjanya Komatineni pinctrl-1 = <&sdmmc4_1v8_drv>; 12891ea06718SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>; 12901ea06718SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>; 129163af8bcdSAapo Vienamo nvidia,default-tap = <0x8>; 129263af8bcdSAapo Vienamo nvidia,default-trim = <0x0>; 1293918f9671SAapo Vienamo assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>, 1294918f9671SAapo Vienamo <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 1295918f9671SAapo Vienamo assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 12965879600aSAapo Vienamo nvidia,dqs-trim = <40>; 1297d5d6b468SAapo Vienamo mmc-hs400-1_8v; 1298742af7e7SThierry Reding status = "disabled"; 1299742af7e7SThierry Reding }; 1300742af7e7SThierry Reding 1301e74db5a5SNagarjuna Kristam usb@700d0000 { 1302e74db5a5SNagarjuna Kristam compatible = "nvidia,tegra210-xudc"; 1303e74db5a5SNagarjuna Kristam reg = <0x0 0x700d0000 0x0 0x8000>, 1304e74db5a5SNagarjuna Kristam <0x0 0x700d8000 0x0 0x1000>, 1305e74db5a5SNagarjuna Kristam <0x0 0x700d9000 0x0 0x1000>; 1306e74db5a5SNagarjuna Kristam reg-names = "base", "fpci", "ipfs"; 1307e74db5a5SNagarjuna Kristam interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1308e74db5a5SNagarjuna Kristam clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>, 1309e74db5a5SNagarjuna Kristam <&tegra_car TEGRA210_CLK_XUSB_SS>, 1310e74db5a5SNagarjuna Kristam <&tegra_car TEGRA210_CLK_XUSB_SSP_SRC>, 1311e74db5a5SNagarjuna Kristam <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>, 1312e74db5a5SNagarjuna Kristam <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>; 1313e74db5a5SNagarjuna Kristam clock-names = "dev", "ss", "ss_src", "fs_src", "hs_src"; 1314e74db5a5SNagarjuna Kristam power-domains = <&pd_xusbdev>, <&pd_xusbss>; 1315e74db5a5SNagarjuna Kristam power-domain-names = "dev", "ss"; 1316e74db5a5SNagarjuna Kristam nvidia,xusb-padctl = <&padctl>; 1317e74db5a5SNagarjuna Kristam status = "disabled"; 1318e74db5a5SNagarjuna Kristam }; 1319e74db5a5SNagarjuna Kristam 132038254d19SThierry Reding soctherm: thermal-sensor@700e2000 { 132138254d19SThierry Reding compatible = "nvidia,tegra210-soctherm"; 132238254d19SThierry Reding reg = <0x0 0x700e2000 0x0 0x600>, /* SOC_THERM reg_base */ 132338254d19SThierry Reding <0x0 0x60006000 0x0 0x400>; /* CAR reg_base */ 132438254d19SThierry Reding reg-names = "soctherm-reg", "car-reg"; 132538254d19SThierry Reding interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 132638254d19SThierry Reding <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 132738254d19SThierry Reding interrupt-names = "thermal", "edp"; 132838254d19SThierry Reding clocks = <&tegra_car TEGRA210_CLK_TSENSOR>, 132938254d19SThierry Reding <&tegra_car TEGRA210_CLK_SOC_THERM>; 133038254d19SThierry Reding clock-names = "tsensor", "soctherm"; 133138254d19SThierry Reding resets = <&tegra_car 78>; 133238254d19SThierry Reding reset-names = "soctherm"; 133338254d19SThierry Reding #thermal-sensor-cells = <1>; 133438254d19SThierry Reding 133538254d19SThierry Reding throttle-cfgs { 133638254d19SThierry Reding throttle_heavy: heavy { 133738254d19SThierry Reding nvidia,priority = <100>; 133838254d19SThierry Reding nvidia,cpu-throt-percent = <85>; 133938254d19SThierry Reding nvidia,gpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_HIGH>; 134038254d19SThierry Reding 134138254d19SThierry Reding #cooling-cells = <2>; 134238254d19SThierry Reding }; 134338254d19SThierry Reding }; 134438254d19SThierry Reding }; 134538254d19SThierry Reding 1346be70771dSThierry Reding mipi: mipi@700e3000 { 1347742af7e7SThierry Reding compatible = "nvidia,tegra210-mipi"; 1348742af7e7SThierry Reding reg = <0x0 0x700e3000 0x0 0x100>; 1349742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_MIPI_CAL>; 1350742af7e7SThierry Reding clock-names = "mipi-cal"; 135196d1f078SJon Hunter power-domains = <&pd_sor>; 1352742af7e7SThierry Reding #nvidia,mipi-calibrate-cells = <1>; 1353742af7e7SThierry Reding }; 1354742af7e7SThierry Reding 13552ceed593SJoseph Lo dfll: clock@70110000 { 13562ceed593SJoseph Lo compatible = "nvidia,tegra210-dfll"; 13572ceed593SJoseph Lo reg = <0 0x70110000 0 0x100>, /* DFLL control */ 13582ceed593SJoseph Lo <0 0x70110000 0 0x100>, /* I2C output control */ 13592ceed593SJoseph Lo <0 0x70110100 0 0x100>, /* Integrated I2C controller */ 13602ceed593SJoseph Lo <0 0x70110200 0 0x100>; /* Look-up table RAM */ 13612ceed593SJoseph Lo interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 13622ceed593SJoseph Lo clocks = <&tegra_car TEGRA210_CLK_DFLL_SOC>, 13632ceed593SJoseph Lo <&tegra_car TEGRA210_CLK_DFLL_REF>, 13642ceed593SJoseph Lo <&tegra_car TEGRA210_CLK_I2C5>; 13652ceed593SJoseph Lo clock-names = "soc", "ref", "i2c"; 13660017f2c8SDiogo Ivo resets = <&tegra_car TEGRA210_RST_DFLL_DVCO>, 13670017f2c8SDiogo Ivo <&tegra_car 155>; 13680017f2c8SDiogo Ivo reset-names = "dvco", "dfll"; 13692ceed593SJoseph Lo #clock-cells = <0>; 13702ceed593SJoseph Lo clock-output-names = "dfllCPU_out"; 13712ceed593SJoseph Lo status = "disabled"; 13722ceed593SJoseph Lo }; 13732ceed593SJoseph Lo 13740f133090SJon Hunter aconnect@702c0000 { 13750f133090SJon Hunter compatible = "nvidia,tegra210-aconnect"; 13760f133090SJon Hunter clocks = <&tegra_car TEGRA210_CLK_APE>, 13770f133090SJon Hunter <&tegra_car TEGRA210_CLK_APB2APE>; 13780f133090SJon Hunter clock-names = "ape", "apb2ape"; 13790f133090SJon Hunter power-domains = <&pd_audio>; 13800f133090SJon Hunter #address-cells = <1>; 13810f133090SJon Hunter #size-cells = <1>; 13820f133090SJon Hunter ranges = <0x702c0000 0x0 0x702c0000 0x00040000>; 13830f133090SJon Hunter status = "disabled"; 1384bcdbde43SJon Hunter 1385b6e136c7SSameer Pujar adma: dma-controller@702e2000 { 138619e61213SJon Hunter compatible = "nvidia,tegra210-adma"; 138719e61213SJon Hunter reg = <0x702e2000 0x2000>; 138819e61213SJon Hunter interrupt-parent = <&agic>; 138919e61213SJon Hunter interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 139019e61213SJon Hunter <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 139119e61213SJon Hunter <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 139219e61213SJon Hunter <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 139319e61213SJon Hunter <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 139419e61213SJon Hunter <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 139519e61213SJon Hunter <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 139619e61213SJon Hunter <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 139719e61213SJon Hunter <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 139819e61213SJon Hunter <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 139919e61213SJon Hunter <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 140019e61213SJon Hunter <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 140119e61213SJon Hunter <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 140219e61213SJon Hunter <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 140319e61213SJon Hunter <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 140419e61213SJon Hunter <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 140519e61213SJon Hunter <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 140619e61213SJon Hunter <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 140719e61213SJon Hunter <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 140819e61213SJon Hunter <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 140919e61213SJon Hunter <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 141019e61213SJon Hunter <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 141119e61213SJon Hunter #dma-cells = <1>; 141219e61213SJon Hunter clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>; 141319e61213SJon Hunter clock-names = "d_audio"; 141419e61213SJon Hunter status = "disabled"; 141519e61213SJon Hunter }; 141619e61213SJon Hunter 1417df93557bSThierry Reding agic: interrupt-controller@702f9000 { 1418bcdbde43SJon Hunter compatible = "nvidia,tegra210-agic"; 1419bcdbde43SJon Hunter #interrupt-cells = <3>; 1420bcdbde43SJon Hunter interrupt-controller; 1421ba24eee6SJon Hunter reg = <0x702f9000 0x1000>, 1422bcdbde43SJon Hunter <0x702fa000 0x2000>; 1423bcdbde43SJon Hunter interrupts = <GIC_SPI 102 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1424bcdbde43SJon Hunter clocks = <&tegra_car TEGRA210_CLK_APE>; 1425bcdbde43SJon Hunter clock-names = "clk"; 1426bcdbde43SJon Hunter status = "disabled"; 1427bcdbde43SJon Hunter }; 1428177208f7SSameer Pujar 1429177208f7SSameer Pujar tegra_ahub: ahub@702d0800 { 1430177208f7SSameer Pujar compatible = "nvidia,tegra210-ahub"; 1431177208f7SSameer Pujar reg = <0x702d0800 0x800>; 1432177208f7SSameer Pujar clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>; 1433177208f7SSameer Pujar clock-names = "ahub"; 1434177208f7SSameer Pujar assigned-clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>; 1435177208f7SSameer Pujar assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1436177208f7SSameer Pujar #address-cells = <1>; 1437177208f7SSameer Pujar #size-cells = <1>; 1438177208f7SSameer Pujar ranges = <0x702d0000 0x702d0000 0x0000e400>; 1439177208f7SSameer Pujar status = "disabled"; 1440177208f7SSameer Pujar 1441177208f7SSameer Pujar tegra_admaif: admaif@702d0000 { 1442177208f7SSameer Pujar compatible = "nvidia,tegra210-admaif"; 1443177208f7SSameer Pujar reg = <0x702d0000 0x800>; 1444177208f7SSameer Pujar dmas = <&adma 1>, <&adma 1>, 1445177208f7SSameer Pujar <&adma 2>, <&adma 2>, 1446177208f7SSameer Pujar <&adma 3>, <&adma 3>, 1447177208f7SSameer Pujar <&adma 4>, <&adma 4>, 1448177208f7SSameer Pujar <&adma 5>, <&adma 5>, 1449177208f7SSameer Pujar <&adma 6>, <&adma 6>, 1450177208f7SSameer Pujar <&adma 7>, <&adma 7>, 1451177208f7SSameer Pujar <&adma 8>, <&adma 8>, 1452177208f7SSameer Pujar <&adma 9>, <&adma 9>, 1453177208f7SSameer Pujar <&adma 10>, <&adma 10>; 1454177208f7SSameer Pujar dma-names = "rx1", "tx1", 1455177208f7SSameer Pujar "rx2", "tx2", 1456177208f7SSameer Pujar "rx3", "tx3", 1457177208f7SSameer Pujar "rx4", "tx4", 1458177208f7SSameer Pujar "rx5", "tx5", 1459177208f7SSameer Pujar "rx6", "tx6", 1460177208f7SSameer Pujar "rx7", "tx7", 1461177208f7SSameer Pujar "rx8", "tx8", 1462177208f7SSameer Pujar "rx9", "tx9", 1463177208f7SSameer Pujar "rx10", "tx10"; 1464177208f7SSameer Pujar status = "disabled"; 1465f5208672SSameer Pujar 1466f5208672SSameer Pujar ports { 1467f5208672SSameer Pujar #address-cells = <1>; 1468f5208672SSameer Pujar #size-cells = <0>; 1469f5208672SSameer Pujar 1470f5208672SSameer Pujar admaif1_port: port@0 { 1471f5208672SSameer Pujar reg = <0>; 1472f5208672SSameer Pujar 1473f5208672SSameer Pujar admaif1_ep: endpoint { 1474f5208672SSameer Pujar remote-endpoint = <&xbar_admaif1_ep>; 1475f5208672SSameer Pujar }; 1476f5208672SSameer Pujar }; 1477f5208672SSameer Pujar 1478f5208672SSameer Pujar admaif2_port: port@1 { 1479f5208672SSameer Pujar reg = <1>; 1480f5208672SSameer Pujar 1481f5208672SSameer Pujar admaif2_ep: endpoint { 1482f5208672SSameer Pujar remote-endpoint = <&xbar_admaif2_ep>; 1483f5208672SSameer Pujar }; 1484f5208672SSameer Pujar }; 1485f5208672SSameer Pujar 1486f5208672SSameer Pujar admaif3_port: port@2 { 1487f5208672SSameer Pujar reg = <2>; 1488f5208672SSameer Pujar 1489f5208672SSameer Pujar admaif3_ep: endpoint { 1490f5208672SSameer Pujar remote-endpoint = <&xbar_admaif3_ep>; 1491f5208672SSameer Pujar }; 1492f5208672SSameer Pujar }; 1493f5208672SSameer Pujar 1494f5208672SSameer Pujar admaif4_port: port@3 { 1495f5208672SSameer Pujar reg = <3>; 1496f5208672SSameer Pujar 1497f5208672SSameer Pujar admaif4_ep: endpoint { 1498f5208672SSameer Pujar remote-endpoint = <&xbar_admaif4_ep>; 1499f5208672SSameer Pujar }; 1500f5208672SSameer Pujar }; 1501f5208672SSameer Pujar 1502f5208672SSameer Pujar admaif5_port: port@4 { 1503f5208672SSameer Pujar reg = <4>; 1504f5208672SSameer Pujar 1505f5208672SSameer Pujar admaif5_ep: endpoint { 1506f5208672SSameer Pujar remote-endpoint = <&xbar_admaif5_ep>; 1507f5208672SSameer Pujar }; 1508f5208672SSameer Pujar }; 1509f5208672SSameer Pujar 1510f5208672SSameer Pujar admaif6_port: port@5 { 1511f5208672SSameer Pujar reg = <5>; 1512f5208672SSameer Pujar 1513f5208672SSameer Pujar admaif6_ep: endpoint { 1514f5208672SSameer Pujar remote-endpoint = <&xbar_admaif6_ep>; 1515f5208672SSameer Pujar }; 1516f5208672SSameer Pujar }; 1517f5208672SSameer Pujar 1518f5208672SSameer Pujar admaif7_port: port@6 { 1519f5208672SSameer Pujar reg = <6>; 1520f5208672SSameer Pujar 1521f5208672SSameer Pujar admaif7_ep: endpoint { 1522f5208672SSameer Pujar remote-endpoint = <&xbar_admaif7_ep>; 1523f5208672SSameer Pujar }; 1524f5208672SSameer Pujar }; 1525f5208672SSameer Pujar 1526f5208672SSameer Pujar admaif8_port: port@7 { 1527f5208672SSameer Pujar reg = <7>; 1528f5208672SSameer Pujar 1529f5208672SSameer Pujar admaif8_ep: endpoint { 1530f5208672SSameer Pujar remote-endpoint = <&xbar_admaif8_ep>; 1531f5208672SSameer Pujar }; 1532f5208672SSameer Pujar }; 1533f5208672SSameer Pujar 1534f5208672SSameer Pujar admaif9_port: port@8 { 1535f5208672SSameer Pujar reg = <8>; 1536f5208672SSameer Pujar 1537f5208672SSameer Pujar admaif9_ep: endpoint { 1538f5208672SSameer Pujar remote-endpoint = <&xbar_admaif9_ep>; 1539f5208672SSameer Pujar }; 1540f5208672SSameer Pujar }; 1541f5208672SSameer Pujar 1542f5208672SSameer Pujar admaif10_port: port@9 { 1543f5208672SSameer Pujar reg = <9>; 1544f5208672SSameer Pujar 1545f5208672SSameer Pujar admaif10_ep: endpoint { 1546f5208672SSameer Pujar remote-endpoint = <&xbar_admaif10_ep>; 1547f5208672SSameer Pujar }; 1548f5208672SSameer Pujar }; 1549f5208672SSameer Pujar }; 1550177208f7SSameer Pujar }; 1551177208f7SSameer Pujar 1552177208f7SSameer Pujar tegra_i2s1: i2s@702d1000 { 1553177208f7SSameer Pujar compatible = "nvidia,tegra210-i2s"; 1554177208f7SSameer Pujar reg = <0x702d1000 0x100>; 1555177208f7SSameer Pujar clocks = <&tegra_car TEGRA210_CLK_I2S0>, 1556177208f7SSameer Pujar <&tegra_car TEGRA210_CLK_I2S0_SYNC>; 1557177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 1558177208f7SSameer Pujar assigned-clocks = <&tegra_car TEGRA210_CLK_I2S0>; 1559177208f7SSameer Pujar assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1560177208f7SSameer Pujar assigned-clock-rates = <1536000>; 1561177208f7SSameer Pujar sound-name-prefix = "I2S1"; 1562177208f7SSameer Pujar status = "disabled"; 1563177208f7SSameer Pujar }; 1564177208f7SSameer Pujar 1565177208f7SSameer Pujar tegra_i2s2: i2s@702d1100 { 1566177208f7SSameer Pujar compatible = "nvidia,tegra210-i2s"; 1567177208f7SSameer Pujar reg = <0x702d1100 0x100>; 1568177208f7SSameer Pujar clocks = <&tegra_car TEGRA210_CLK_I2S1>, 1569177208f7SSameer Pujar <&tegra_car TEGRA210_CLK_I2S1_SYNC>; 1570177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 1571177208f7SSameer Pujar assigned-clocks = <&tegra_car TEGRA210_CLK_I2S1>; 1572177208f7SSameer Pujar assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1573177208f7SSameer Pujar assigned-clock-rates = <1536000>; 1574177208f7SSameer Pujar sound-name-prefix = "I2S2"; 1575177208f7SSameer Pujar status = "disabled"; 1576177208f7SSameer Pujar }; 1577177208f7SSameer Pujar 1578177208f7SSameer Pujar tegra_i2s3: i2s@702d1200 { 1579177208f7SSameer Pujar compatible = "nvidia,tegra210-i2s"; 1580177208f7SSameer Pujar reg = <0x702d1200 0x100>; 1581177208f7SSameer Pujar clocks = <&tegra_car TEGRA210_CLK_I2S2>, 1582177208f7SSameer Pujar <&tegra_car TEGRA210_CLK_I2S2_SYNC>; 1583177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 1584177208f7SSameer Pujar assigned-clocks = <&tegra_car TEGRA210_CLK_I2S2>; 1585177208f7SSameer Pujar assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1586177208f7SSameer Pujar assigned-clock-rates = <1536000>; 1587177208f7SSameer Pujar sound-name-prefix = "I2S3"; 1588177208f7SSameer Pujar status = "disabled"; 1589177208f7SSameer Pujar }; 1590177208f7SSameer Pujar 1591177208f7SSameer Pujar tegra_i2s4: i2s@702d1300 { 1592177208f7SSameer Pujar compatible = "nvidia,tegra210-i2s"; 1593177208f7SSameer Pujar reg = <0x702d1300 0x100>; 1594177208f7SSameer Pujar clocks = <&tegra_car TEGRA210_CLK_I2S3>, 1595177208f7SSameer Pujar <&tegra_car TEGRA210_CLK_I2S3_SYNC>; 1596177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 1597177208f7SSameer Pujar assigned-clocks = <&tegra_car TEGRA210_CLK_I2S3>; 1598177208f7SSameer Pujar assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1599177208f7SSameer Pujar assigned-clock-rates = <1536000>; 1600177208f7SSameer Pujar sound-name-prefix = "I2S4"; 1601177208f7SSameer Pujar status = "disabled"; 1602177208f7SSameer Pujar }; 1603177208f7SSameer Pujar 1604177208f7SSameer Pujar tegra_i2s5: i2s@702d1400 { 1605177208f7SSameer Pujar compatible = "nvidia,tegra210-i2s"; 1606177208f7SSameer Pujar reg = <0x702d1400 0x100>; 1607177208f7SSameer Pujar clocks = <&tegra_car TEGRA210_CLK_I2S4>, 1608177208f7SSameer Pujar <&tegra_car TEGRA210_CLK_I2S4_SYNC>; 1609177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 1610177208f7SSameer Pujar assigned-clocks = <&tegra_car TEGRA210_CLK_I2S4>; 1611177208f7SSameer Pujar assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1612177208f7SSameer Pujar assigned-clock-rates = <1536000>; 1613177208f7SSameer Pujar sound-name-prefix = "I2S5"; 1614177208f7SSameer Pujar status = "disabled"; 1615177208f7SSameer Pujar }; 1616177208f7SSameer Pujar 1617177208f7SSameer Pujar tegra_dmic1: dmic@702d4000 { 1618177208f7SSameer Pujar compatible = "nvidia,tegra210-dmic"; 1619177208f7SSameer Pujar reg = <0x702d4000 0x100>; 1620177208f7SSameer Pujar clocks = <&tegra_car TEGRA210_CLK_DMIC1>; 1621177208f7SSameer Pujar clock-names = "dmic"; 1622177208f7SSameer Pujar assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC1>; 1623177208f7SSameer Pujar assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1624177208f7SSameer Pujar assigned-clock-rates = <3072000>; 1625177208f7SSameer Pujar sound-name-prefix = "DMIC1"; 1626177208f7SSameer Pujar status = "disabled"; 1627177208f7SSameer Pujar }; 1628177208f7SSameer Pujar 1629177208f7SSameer Pujar tegra_dmic2: dmic@702d4100 { 1630177208f7SSameer Pujar compatible = "nvidia,tegra210-dmic"; 1631177208f7SSameer Pujar reg = <0x702d4100 0x100>; 1632177208f7SSameer Pujar clocks = <&tegra_car TEGRA210_CLK_DMIC2>; 1633177208f7SSameer Pujar clock-names = "dmic"; 1634177208f7SSameer Pujar assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC2>; 1635177208f7SSameer Pujar assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1636177208f7SSameer Pujar assigned-clock-rates = <3072000>; 1637177208f7SSameer Pujar sound-name-prefix = "DMIC2"; 1638177208f7SSameer Pujar status = "disabled"; 1639177208f7SSameer Pujar }; 1640177208f7SSameer Pujar 1641177208f7SSameer Pujar tegra_dmic3: dmic@702d4200 { 1642177208f7SSameer Pujar compatible = "nvidia,tegra210-dmic"; 1643177208f7SSameer Pujar reg = <0x702d4200 0x100>; 1644177208f7SSameer Pujar clocks = <&tegra_car TEGRA210_CLK_DMIC3>; 1645177208f7SSameer Pujar clock-names = "dmic"; 1646177208f7SSameer Pujar assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC3>; 1647177208f7SSameer Pujar assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1648177208f7SSameer Pujar assigned-clock-rates = <3072000>; 1649177208f7SSameer Pujar sound-name-prefix = "DMIC3"; 1650177208f7SSameer Pujar status = "disabled"; 1651177208f7SSameer Pujar }; 1652f5208672SSameer Pujar 1653848f3290SSameer Pujar tegra_sfc1: sfc@702d2000 { 1654848f3290SSameer Pujar compatible = "nvidia,tegra210-sfc"; 1655848f3290SSameer Pujar reg = <0x702d2000 0x200>; 1656848f3290SSameer Pujar sound-name-prefix = "SFC1"; 1657848f3290SSameer Pujar status = "disabled"; 1658848f3290SSameer Pujar }; 1659848f3290SSameer Pujar 1660848f3290SSameer Pujar tegra_sfc2: sfc@702d2200 { 1661848f3290SSameer Pujar compatible = "nvidia,tegra210-sfc"; 1662848f3290SSameer Pujar reg = <0x702d2200 0x200>; 1663848f3290SSameer Pujar sound-name-prefix = "SFC2"; 1664848f3290SSameer Pujar status = "disabled"; 1665848f3290SSameer Pujar }; 1666848f3290SSameer Pujar 1667848f3290SSameer Pujar tegra_sfc3: sfc@702d2400 { 1668848f3290SSameer Pujar compatible = "nvidia,tegra210-sfc"; 1669848f3290SSameer Pujar reg = <0x702d2400 0x200>; 1670848f3290SSameer Pujar sound-name-prefix = "SFC3"; 1671848f3290SSameer Pujar status = "disabled"; 1672848f3290SSameer Pujar }; 1673848f3290SSameer Pujar 1674848f3290SSameer Pujar tegra_sfc4: sfc@702d2600 { 1675848f3290SSameer Pujar compatible = "nvidia,tegra210-sfc"; 1676848f3290SSameer Pujar reg = <0x702d2600 0x200>; 1677848f3290SSameer Pujar sound-name-prefix = "SFC4"; 1678848f3290SSameer Pujar status = "disabled"; 1679848f3290SSameer Pujar }; 1680848f3290SSameer Pujar 1681848f3290SSameer Pujar tegra_mvc1: mvc@702da000 { 1682848f3290SSameer Pujar compatible = "nvidia,tegra210-mvc"; 1683848f3290SSameer Pujar reg = <0x702da000 0x200>; 1684848f3290SSameer Pujar sound-name-prefix = "MVC1"; 1685848f3290SSameer Pujar status = "disabled"; 1686848f3290SSameer Pujar }; 1687848f3290SSameer Pujar 1688848f3290SSameer Pujar tegra_mvc2: mvc@702da200 { 1689848f3290SSameer Pujar compatible = "nvidia,tegra210-mvc"; 1690848f3290SSameer Pujar reg = <0x702da200 0x200>; 1691848f3290SSameer Pujar sound-name-prefix = "MVC2"; 1692848f3290SSameer Pujar status = "disabled"; 1693848f3290SSameer Pujar }; 1694848f3290SSameer Pujar 1695848f3290SSameer Pujar tegra_amx1: amx@702d3000 { 1696848f3290SSameer Pujar compatible = "nvidia,tegra210-amx"; 1697848f3290SSameer Pujar reg = <0x702d3000 0x100>; 1698848f3290SSameer Pujar sound-name-prefix = "AMX1"; 1699848f3290SSameer Pujar status = "disabled"; 1700848f3290SSameer Pujar }; 1701848f3290SSameer Pujar 1702848f3290SSameer Pujar tegra_amx2: amx@702d3100 { 1703848f3290SSameer Pujar compatible = "nvidia,tegra210-amx"; 1704848f3290SSameer Pujar reg = <0x702d3100 0x100>; 1705848f3290SSameer Pujar sound-name-prefix = "AMX2"; 1706848f3290SSameer Pujar status = "disabled"; 1707848f3290SSameer Pujar }; 1708848f3290SSameer Pujar 1709848f3290SSameer Pujar tegra_adx1: adx@702d3800 { 1710848f3290SSameer Pujar compatible = "nvidia,tegra210-adx"; 1711848f3290SSameer Pujar reg = <0x702d3800 0x100>; 1712848f3290SSameer Pujar sound-name-prefix = "ADX1"; 1713848f3290SSameer Pujar status = "disabled"; 1714848f3290SSameer Pujar }; 1715848f3290SSameer Pujar 1716848f3290SSameer Pujar tegra_adx2: adx@702d3900 { 1717848f3290SSameer Pujar compatible = "nvidia,tegra210-adx"; 1718848f3290SSameer Pujar reg = <0x702d3900 0x100>; 1719848f3290SSameer Pujar sound-name-prefix = "ADX2"; 1720848f3290SSameer Pujar status = "disabled"; 1721848f3290SSameer Pujar }; 1722848f3290SSameer Pujar 17234b6a1b7cSSameer Pujar tegra_ope1: processing-engine@702d8000 { 17244b6a1b7cSSameer Pujar compatible = "nvidia,tegra210-ope"; 17254b6a1b7cSSameer Pujar reg = <0x702d8000 0x100>; 17264b6a1b7cSSameer Pujar #address-cells = <1>; 17274b6a1b7cSSameer Pujar #size-cells = <1>; 17284b6a1b7cSSameer Pujar ranges; 17294b6a1b7cSSameer Pujar sound-name-prefix = "OPE1"; 17304b6a1b7cSSameer Pujar status = "disabled"; 17314b6a1b7cSSameer Pujar 17324b6a1b7cSSameer Pujar equalizer@702d8100 { 17334b6a1b7cSSameer Pujar compatible = "nvidia,tegra210-peq"; 17344b6a1b7cSSameer Pujar reg = <0x702d8100 0x100>; 17354b6a1b7cSSameer Pujar }; 17364b6a1b7cSSameer Pujar 17374b6a1b7cSSameer Pujar dynamic-range-compressor@702d8200 { 17384b6a1b7cSSameer Pujar compatible = "nvidia,tegra210-mbdrc"; 17394b6a1b7cSSameer Pujar reg = <0x702d8200 0x200>; 17404b6a1b7cSSameer Pujar }; 17414b6a1b7cSSameer Pujar }; 17424b6a1b7cSSameer Pujar 17434b6a1b7cSSameer Pujar tegra_ope2: processing-engine@702d8400 { 17444b6a1b7cSSameer Pujar compatible = "nvidia,tegra210-ope"; 17454b6a1b7cSSameer Pujar reg = <0x702d8400 0x100>; 17464b6a1b7cSSameer Pujar #address-cells = <1>; 17474b6a1b7cSSameer Pujar #size-cells = <1>; 17484b6a1b7cSSameer Pujar ranges; 17494b6a1b7cSSameer Pujar sound-name-prefix = "OPE2"; 17504b6a1b7cSSameer Pujar status = "disabled"; 17514b6a1b7cSSameer Pujar 17524b6a1b7cSSameer Pujar equalizer@702d8500 { 17534b6a1b7cSSameer Pujar compatible = "nvidia,tegra210-peq"; 17544b6a1b7cSSameer Pujar reg = <0x702d8500 0x100>; 17554b6a1b7cSSameer Pujar }; 17564b6a1b7cSSameer Pujar 17574b6a1b7cSSameer Pujar dynamic-range-compressor@702d8600 { 17584b6a1b7cSSameer Pujar compatible = "nvidia,tegra210-mbdrc"; 17594b6a1b7cSSameer Pujar reg = <0x702d8600 0x200>; 17604b6a1b7cSSameer Pujar }; 17614b6a1b7cSSameer Pujar }; 17624b6a1b7cSSameer Pujar 1763848f3290SSameer Pujar tegra_amixer: amixer@702dbb00 { 1764848f3290SSameer Pujar compatible = "nvidia,tegra210-amixer"; 1765848f3290SSameer Pujar reg = <0x702dbb00 0x800>; 1766848f3290SSameer Pujar sound-name-prefix = "MIXER1"; 1767848f3290SSameer Pujar status = "disabled"; 1768848f3290SSameer Pujar }; 1769848f3290SSameer Pujar 1770f5208672SSameer Pujar ports { 1771f5208672SSameer Pujar #address-cells = <1>; 1772f5208672SSameer Pujar #size-cells = <0>; 1773f5208672SSameer Pujar 1774f5208672SSameer Pujar port@0 { 1775f5208672SSameer Pujar reg = <0x0>; 1776f5208672SSameer Pujar 1777f5208672SSameer Pujar xbar_admaif1_ep: endpoint { 1778f5208672SSameer Pujar remote-endpoint = <&admaif1_ep>; 1779f5208672SSameer Pujar }; 1780f5208672SSameer Pujar }; 1781f5208672SSameer Pujar 1782f5208672SSameer Pujar port@1 { 1783f5208672SSameer Pujar reg = <0x1>; 1784f5208672SSameer Pujar 1785f5208672SSameer Pujar xbar_admaif2_ep: endpoint { 1786f5208672SSameer Pujar remote-endpoint = <&admaif2_ep>; 1787f5208672SSameer Pujar }; 1788f5208672SSameer Pujar }; 1789f5208672SSameer Pujar 1790f5208672SSameer Pujar port@2 { 1791f5208672SSameer Pujar reg = <0x2>; 1792f5208672SSameer Pujar 1793f5208672SSameer Pujar xbar_admaif3_ep: endpoint { 1794f5208672SSameer Pujar remote-endpoint = <&admaif3_ep>; 1795f5208672SSameer Pujar }; 1796f5208672SSameer Pujar }; 1797f5208672SSameer Pujar 1798f5208672SSameer Pujar port@3 { 1799f5208672SSameer Pujar reg = <0x3>; 1800f5208672SSameer Pujar 1801f5208672SSameer Pujar xbar_admaif4_ep: endpoint { 1802f5208672SSameer Pujar remote-endpoint = <&admaif4_ep>; 1803f5208672SSameer Pujar }; 1804f5208672SSameer Pujar }; 1805f5208672SSameer Pujar 1806f5208672SSameer Pujar port@4 { 1807f5208672SSameer Pujar reg = <0x4>; 1808f5208672SSameer Pujar xbar_admaif5_ep: endpoint { 1809f5208672SSameer Pujar remote-endpoint = <&admaif5_ep>; 1810f5208672SSameer Pujar }; 1811f5208672SSameer Pujar }; 1812f5208672SSameer Pujar port@5 { 1813f5208672SSameer Pujar reg = <0x5>; 1814f5208672SSameer Pujar 1815f5208672SSameer Pujar xbar_admaif6_ep: endpoint { 1816f5208672SSameer Pujar remote-endpoint = <&admaif6_ep>; 1817f5208672SSameer Pujar }; 1818f5208672SSameer Pujar }; 1819f5208672SSameer Pujar 1820f5208672SSameer Pujar port@6 { 1821f5208672SSameer Pujar reg = <0x6>; 1822f5208672SSameer Pujar 1823f5208672SSameer Pujar xbar_admaif7_ep: endpoint { 1824f5208672SSameer Pujar remote-endpoint = <&admaif7_ep>; 1825f5208672SSameer Pujar }; 1826f5208672SSameer Pujar }; 1827f5208672SSameer Pujar 1828f5208672SSameer Pujar port@7 { 1829f5208672SSameer Pujar reg = <0x7>; 1830f5208672SSameer Pujar 1831f5208672SSameer Pujar xbar_admaif8_ep: endpoint { 1832f5208672SSameer Pujar remote-endpoint = <&admaif8_ep>; 1833f5208672SSameer Pujar }; 1834f5208672SSameer Pujar }; 1835f5208672SSameer Pujar 1836f5208672SSameer Pujar port@8 { 1837f5208672SSameer Pujar reg = <0x8>; 1838f5208672SSameer Pujar 1839f5208672SSameer Pujar xbar_admaif9_ep: endpoint { 1840f5208672SSameer Pujar remote-endpoint = <&admaif9_ep>; 1841f5208672SSameer Pujar }; 1842f5208672SSameer Pujar }; 1843f5208672SSameer Pujar 1844f5208672SSameer Pujar port@9 { 1845f5208672SSameer Pujar reg = <0x9>; 1846f5208672SSameer Pujar 1847f5208672SSameer Pujar xbar_admaif10_ep: endpoint { 1848f5208672SSameer Pujar remote-endpoint = <&admaif10_ep>; 1849f5208672SSameer Pujar }; 1850f5208672SSameer Pujar }; 1851f5208672SSameer Pujar }; 1852177208f7SSameer Pujar }; 18530f133090SJon Hunter }; 18540f133090SJon Hunter 1855be70771dSThierry Reding spi@70410000 { 1856742af7e7SThierry Reding compatible = "nvidia,tegra210-qspi"; 1857742af7e7SThierry Reding reg = <0x0 0x70410000 0x0 0x1000>; 1858742af7e7SThierry Reding interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1859742af7e7SThierry Reding #address-cells = <1>; 1860742af7e7SThierry Reding #size-cells = <0>; 186107910a79SSowjanya Komatineni clocks = <&tegra_car TEGRA210_CLK_QSPI>, 186207910a79SSowjanya Komatineni <&tegra_car TEGRA210_CLK_QSPI_PM>; 186307910a79SSowjanya Komatineni clock-names = "qspi", "qspi_out"; 1864742af7e7SThierry Reding resets = <&tegra_car 211>; 1865742af7e7SThierry Reding reset-names = "qspi"; 1866742af7e7SThierry Reding dmas = <&apbdma 5>, <&apbdma 5>; 1867742af7e7SThierry Reding dma-names = "rx", "tx"; 1868742af7e7SThierry Reding status = "disabled"; 1869742af7e7SThierry Reding }; 1870742af7e7SThierry Reding 1871be70771dSThierry Reding usb@7d000000 { 187205647401SThierry Reding compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci"; 1873742af7e7SThierry Reding reg = <0x0 0x7d000000 0x0 0x4000>; 1874742af7e7SThierry Reding interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1875742af7e7SThierry Reding phy_type = "utmi"; 1876742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_USBD>; 1877742af7e7SThierry Reding clock-names = "usb"; 1878742af7e7SThierry Reding resets = <&tegra_car 22>; 1879742af7e7SThierry Reding reset-names = "usb"; 1880742af7e7SThierry Reding nvidia,phy = <&phy1>; 1881742af7e7SThierry Reding status = "disabled"; 1882742af7e7SThierry Reding }; 1883742af7e7SThierry Reding 1884be70771dSThierry Reding phy1: usb-phy@7d000000 { 1885742af7e7SThierry Reding compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; 1886742af7e7SThierry Reding reg = <0x0 0x7d000000 0x0 0x4000>, 1887742af7e7SThierry Reding <0x0 0x7d000000 0x0 0x4000>; 1888742af7e7SThierry Reding phy_type = "utmi"; 1889742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_USBD>, 1890742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_PLL_U>, 1891742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_USBD>; 1892742af7e7SThierry Reding clock-names = "reg", "pll_u", "utmi-pads"; 1893742af7e7SThierry Reding resets = <&tegra_car 22>, <&tegra_car 22>; 1894742af7e7SThierry Reding reset-names = "usb", "utmi-pads"; 1895742af7e7SThierry Reding nvidia,hssync-start-delay = <0>; 1896742af7e7SThierry Reding nvidia,idle-wait-delay = <17>; 1897742af7e7SThierry Reding nvidia,elastic-limit = <16>; 1898742af7e7SThierry Reding nvidia,term-range-adj = <6>; 1899742af7e7SThierry Reding nvidia,xcvr-setup = <9>; 1900742af7e7SThierry Reding nvidia,xcvr-lsfslew = <0>; 1901742af7e7SThierry Reding nvidia,xcvr-lsrslew = <3>; 1902742af7e7SThierry Reding nvidia,hssquelch-level = <2>; 1903742af7e7SThierry Reding nvidia,hsdiscon-level = <5>; 1904742af7e7SThierry Reding nvidia,xcvr-hsslew = <12>; 1905742af7e7SThierry Reding nvidia,has-utmi-pad-registers; 1906742af7e7SThierry Reding status = "disabled"; 1907742af7e7SThierry Reding }; 1908742af7e7SThierry Reding 1909be70771dSThierry Reding usb@7d004000 { 191005647401SThierry Reding compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci"; 1911742af7e7SThierry Reding reg = <0x0 0x7d004000 0x0 0x4000>; 1912742af7e7SThierry Reding interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1913742af7e7SThierry Reding phy_type = "utmi"; 1914742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_USB2>; 1915742af7e7SThierry Reding clock-names = "usb"; 1916742af7e7SThierry Reding resets = <&tegra_car 58>; 1917742af7e7SThierry Reding reset-names = "usb"; 1918742af7e7SThierry Reding nvidia,phy = <&phy2>; 1919742af7e7SThierry Reding status = "disabled"; 1920742af7e7SThierry Reding }; 1921742af7e7SThierry Reding 1922be70771dSThierry Reding phy2: usb-phy@7d004000 { 1923742af7e7SThierry Reding compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; 1924742af7e7SThierry Reding reg = <0x0 0x7d004000 0x0 0x4000>, 1925742af7e7SThierry Reding <0x0 0x7d000000 0x0 0x4000>; 1926742af7e7SThierry Reding phy_type = "utmi"; 1927742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_USB2>, 1928742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_PLL_U>, 1929742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_USBD>; 1930742af7e7SThierry Reding clock-names = "reg", "pll_u", "utmi-pads"; 1931742af7e7SThierry Reding resets = <&tegra_car 58>, <&tegra_car 22>; 1932742af7e7SThierry Reding reset-names = "usb", "utmi-pads"; 1933742af7e7SThierry Reding nvidia,hssync-start-delay = <0>; 1934742af7e7SThierry Reding nvidia,idle-wait-delay = <17>; 1935742af7e7SThierry Reding nvidia,elastic-limit = <16>; 1936742af7e7SThierry Reding nvidia,term-range-adj = <6>; 1937742af7e7SThierry Reding nvidia,xcvr-setup = <9>; 1938742af7e7SThierry Reding nvidia,xcvr-lsfslew = <0>; 1939742af7e7SThierry Reding nvidia,xcvr-lsrslew = <3>; 1940742af7e7SThierry Reding nvidia,hssquelch-level = <2>; 1941742af7e7SThierry Reding nvidia,hsdiscon-level = <5>; 1942742af7e7SThierry Reding nvidia,xcvr-hsslew = <12>; 1943742af7e7SThierry Reding status = "disabled"; 1944742af7e7SThierry Reding }; 1945742af7e7SThierry Reding 1946742af7e7SThierry Reding cpus { 1947742af7e7SThierry Reding #address-cells = <1>; 1948742af7e7SThierry Reding #size-cells = <0>; 1949742af7e7SThierry Reding 1950742af7e7SThierry Reding cpu@0 { 1951742af7e7SThierry Reding device_type = "cpu"; 1952742af7e7SThierry Reding compatible = "arm,cortex-a57"; 1953742af7e7SThierry Reding reg = <0>; 195443b9b402SJoseph Lo clocks = <&tegra_car TEGRA210_CLK_CCLK_G>, 195543b9b402SJoseph Lo <&tegra_car TEGRA210_CLK_PLL_X>, 195643b9b402SJoseph Lo <&tegra_car TEGRA210_CLK_PLL_P_OUT4>, 195743b9b402SJoseph Lo <&dfll>; 195843b9b402SJoseph Lo clock-names = "cpu_g", "pll_x", "pll_p", "dfll"; 195943b9b402SJoseph Lo clock-latency = <300000>; 1960da77c6d9SJoseph Lo cpu-idle-states = <&CPU_SLEEP>; 19616c00cac1SJoseph Lo next-level-cache = <&L2>; 1962742af7e7SThierry Reding }; 1963742af7e7SThierry Reding 1964742af7e7SThierry Reding cpu@1 { 1965742af7e7SThierry Reding device_type = "cpu"; 1966742af7e7SThierry Reding compatible = "arm,cortex-a57"; 1967742af7e7SThierry Reding reg = <1>; 1968da77c6d9SJoseph Lo cpu-idle-states = <&CPU_SLEEP>; 19696c00cac1SJoseph Lo next-level-cache = <&L2>; 1970742af7e7SThierry Reding }; 1971742af7e7SThierry Reding 1972742af7e7SThierry Reding cpu@2 { 1973742af7e7SThierry Reding device_type = "cpu"; 1974742af7e7SThierry Reding compatible = "arm,cortex-a57"; 1975742af7e7SThierry Reding reg = <2>; 1976da77c6d9SJoseph Lo cpu-idle-states = <&CPU_SLEEP>; 19776c00cac1SJoseph Lo next-level-cache = <&L2>; 1978742af7e7SThierry Reding }; 1979742af7e7SThierry Reding 1980742af7e7SThierry Reding cpu@3 { 1981742af7e7SThierry Reding device_type = "cpu"; 1982742af7e7SThierry Reding compatible = "arm,cortex-a57"; 1983742af7e7SThierry Reding reg = <3>; 1984da77c6d9SJoseph Lo cpu-idle-states = <&CPU_SLEEP>; 19856c00cac1SJoseph Lo next-level-cache = <&L2>; 1986da77c6d9SJoseph Lo }; 1987da77c6d9SJoseph Lo 1988da77c6d9SJoseph Lo idle-states { 1989da77c6d9SJoseph Lo entry-method = "psci"; 1990da77c6d9SJoseph Lo 1991da77c6d9SJoseph Lo CPU_SLEEP: cpu-sleep { 1992da77c6d9SJoseph Lo compatible = "arm,idle-state"; 1993da77c6d9SJoseph Lo arm,psci-suspend-param = <0x40000007>; 1994da77c6d9SJoseph Lo entry-latency-us = <100>; 1995da77c6d9SJoseph Lo exit-latency-us = <30>; 1996da77c6d9SJoseph Lo min-residency-us = <1000>; 1997da77c6d9SJoseph Lo wakeup-latency-us = <130>; 1998da77c6d9SJoseph Lo idle-state-name = "cpu-sleep"; 1999da77c6d9SJoseph Lo status = "disabled"; 2000da77c6d9SJoseph Lo }; 2001742af7e7SThierry Reding }; 20026c00cac1SJoseph Lo 20036c00cac1SJoseph Lo L2: l2-cache { 20046c00cac1SJoseph Lo compatible = "cache"; 200527f1568bSPierre Gondois cache-level = <2>; 20066c00cac1SJoseph Lo }; 2007742af7e7SThierry Reding }; 2008742af7e7SThierry Reding 2009264064abSThierry Reding pmu { 2010264064abSThierry Reding compatible = "arm,armv8-pmuv3"; 2011264064abSThierry Reding interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 2012264064abSThierry Reding <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 2013264064abSThierry Reding <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 2014264064abSThierry Reding <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 2015264064abSThierry Reding interrupt-affinity = <&{/cpus/cpu@0} &{/cpus/cpu@1} 2016264064abSThierry Reding &{/cpus/cpu@2} &{/cpus/cpu@3}>; 2017264064abSThierry Reding }; 2018264064abSThierry Reding 2019f5208672SSameer Pujar sound { 2020f5208672SSameer Pujar status = "disabled"; 2021f5208672SSameer Pujar 2022f5208672SSameer Pujar clocks = <&tegra_car TEGRA210_CLK_PLL_A>, 2023f5208672SSameer Pujar <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 2024f5208672SSameer Pujar clock-names = "pll_a", "plla_out0"; 2025f5208672SSameer Pujar 2026f5208672SSameer Pujar assigned-clocks = <&tegra_car TEGRA210_CLK_PLL_A>, 2027f5208672SSameer Pujar <&tegra_car TEGRA210_CLK_PLL_A_OUT0>, 2028f5208672SSameer Pujar <&tegra_car TEGRA210_CLK_EXTERN1>; 2029f5208672SSameer Pujar assigned-clock-parents = <0>, <0>, <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 2030f5208672SSameer Pujar assigned-clock-rates = <368640000>, <49152000>, <12288000>; 2031f5208672SSameer Pujar }; 2032f5208672SSameer Pujar 2033e2bed1ebSWei Ni thermal-zones { 2034fe57ff53SThierry Reding cpu-thermal { 2035e2bed1ebSWei Ni polling-delay-passive = <1000>; 2036e2bed1ebSWei Ni polling-delay = <0>; 2037e2bed1ebSWei Ni 2038e2bed1ebSWei Ni thermal-sensors = 2039e2bed1ebSWei Ni <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; 20405e03f663SWei Ni 20415e03f663SWei Ni trips { 20425e03f663SWei Ni cpu-shutdown-trip { 20435e03f663SWei Ni temperature = <102500>; 20445e03f663SWei Ni hysteresis = <0>; 20455e03f663SWei Ni type = "critical"; 20465e03f663SWei Ni }; 2047cbd0f000SWei Ni 2048cbd0f000SWei Ni cpu_throttle_trip: throttle-trip { 2049cbd0f000SWei Ni temperature = <98500>; 2050cbd0f000SWei Ni hysteresis = <1000>; 2051cbd0f000SWei Ni type = "hot"; 2052cbd0f000SWei Ni }; 20535e03f663SWei Ni }; 20545e03f663SWei Ni 20555e03f663SWei Ni cooling-maps { 2056cbd0f000SWei Ni map0 { 2057cbd0f000SWei Ni trip = <&cpu_throttle_trip>; 2058cbd0f000SWei Ni cooling-device = <&throttle_heavy 1 1>; 2059cbd0f000SWei Ni }; 20605e03f663SWei Ni }; 2061e2bed1ebSWei Ni }; 206224fc3363SThierry Reding 2063fe57ff53SThierry Reding mem-thermal { 2064e2bed1ebSWei Ni polling-delay-passive = <0>; 2065e2bed1ebSWei Ni polling-delay = <0>; 2066e2bed1ebSWei Ni 2067e2bed1ebSWei Ni thermal-sensors = 2068e2bed1ebSWei Ni <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>; 20695e03f663SWei Ni 20705e03f663SWei Ni trips { 2071e12325f6SThierry Reding dram_nominal: mem-nominal-trip { 2072e12325f6SThierry Reding temperature = <50000>; 2073e12325f6SThierry Reding hysteresis = <1000>; 2074e12325f6SThierry Reding type = "passive"; 2075e12325f6SThierry Reding }; 2076e12325f6SThierry Reding 2077e12325f6SThierry Reding dram_throttle: mem-throttle-trip { 2078e12325f6SThierry Reding temperature = <70000>; 2079e12325f6SThierry Reding hysteresis = <1000>; 2080e12325f6SThierry Reding type = "active"; 2081e12325f6SThierry Reding }; 2082e12325f6SThierry Reding 2083fdf27825SNicolas Chauvet mem-hot-trip { 2084fdf27825SNicolas Chauvet temperature = <100000>; 2085fdf27825SNicolas Chauvet hysteresis = <1000>; 2086fdf27825SNicolas Chauvet type = "hot"; 2087fdf27825SNicolas Chauvet }; 2088fdf27825SNicolas Chauvet 20895e03f663SWei Ni mem-shutdown-trip { 20905e03f663SWei Ni temperature = <103000>; 20915e03f663SWei Ni hysteresis = <0>; 20925e03f663SWei Ni type = "critical"; 20935e03f663SWei Ni }; 20945e03f663SWei Ni }; 20955e03f663SWei Ni 20965e03f663SWei Ni cooling-maps { 2097e12325f6SThierry Reding dram-passive { 2098e12325f6SThierry Reding cooling-device = <&emc 0 0>; 2099e12325f6SThierry Reding trip = <&dram_nominal>; 2100e12325f6SThierry Reding }; 2101e12325f6SThierry Reding 2102e12325f6SThierry Reding dram-active { 2103e12325f6SThierry Reding cooling-device = <&emc 1 1>; 2104e12325f6SThierry Reding trip = <&dram_throttle>; 2105e12325f6SThierry Reding }; 21065e03f663SWei Ni }; 2107e2bed1ebSWei Ni }; 210824fc3363SThierry Reding 2109fe57ff53SThierry Reding gpu-thermal { 2110e2bed1ebSWei Ni polling-delay-passive = <1000>; 2111e2bed1ebSWei Ni polling-delay = <0>; 2112e2bed1ebSWei Ni 2113e2bed1ebSWei Ni thermal-sensors = 2114e2bed1ebSWei Ni <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>; 21155e03f663SWei Ni 21165e03f663SWei Ni trips { 21175e03f663SWei Ni gpu-shutdown-trip { 21185e03f663SWei Ni temperature = <103000>; 21195e03f663SWei Ni hysteresis = <0>; 21205e03f663SWei Ni type = "critical"; 21215e03f663SWei Ni }; 2122cbd0f000SWei Ni 2123cbd0f000SWei Ni gpu_throttle_trip: throttle-trip { 2124cbd0f000SWei Ni temperature = <100000>; 2125cbd0f000SWei Ni hysteresis = <1000>; 2126cbd0f000SWei Ni type = "hot"; 2127cbd0f000SWei Ni }; 21285e03f663SWei Ni }; 21295e03f663SWei Ni 21305e03f663SWei Ni cooling-maps { 2131cbd0f000SWei Ni map0 { 2132cbd0f000SWei Ni trip = <&gpu_throttle_trip>; 2133cbd0f000SWei Ni cooling-device = <&throttle_heavy 1 1>; 2134cbd0f000SWei Ni }; 21355e03f663SWei Ni }; 2136e2bed1ebSWei Ni }; 213724fc3363SThierry Reding 2138fe57ff53SThierry Reding pllx-thermal { 2139e2bed1ebSWei Ni polling-delay-passive = <0>; 2140e2bed1ebSWei Ni polling-delay = <0>; 2141e2bed1ebSWei Ni 2142e2bed1ebSWei Ni thermal-sensors = 2143e2bed1ebSWei Ni <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>; 21445e03f663SWei Ni 21455e03f663SWei Ni trips { 21465e03f663SWei Ni pllx-shutdown-trip { 21475e03f663SWei Ni temperature = <103000>; 21485e03f663SWei Ni hysteresis = <0>; 21495e03f663SWei Ni type = "critical"; 21505e03f663SWei Ni }; 2151fdf27825SNicolas Chauvet 2152fdf27825SNicolas Chauvet pllx-throttle-trip { 2153fdf27825SNicolas Chauvet temperature = <100000>; 2154fdf27825SNicolas Chauvet hysteresis = <1000>; 2155fdf27825SNicolas Chauvet type = "hot"; 2156fdf27825SNicolas Chauvet }; 21575e03f663SWei Ni }; 21585e03f663SWei Ni 21595e03f663SWei Ni cooling-maps { 21605e03f663SWei Ni /* 21615e03f663SWei Ni * There are currently no cooling maps, 21625e03f663SWei Ni * because there are no cooling devices. 21635e03f663SWei Ni */ 21645e03f663SWei Ni }; 2165e2bed1ebSWei Ni }; 2166e2bed1ebSWei Ni }; 216738254d19SThierry Reding 216838254d19SThierry Reding timer { 216938254d19SThierry Reding compatible = "arm,armv8-timer"; 217038254d19SThierry Reding interrupts = <GIC_PPI 13 217138254d19SThierry Reding (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 217238254d19SThierry Reding <GIC_PPI 14 217338254d19SThierry Reding (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 217438254d19SThierry Reding <GIC_PPI 11 217538254d19SThierry Reding (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 217638254d19SThierry Reding <GIC_PPI 10 217738254d19SThierry Reding (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 217838254d19SThierry Reding interrupt-parent = <&gic>; 217938254d19SThierry Reding arm,no-tick-in-suspend; 218038254d19SThierry Reding }; 2181742af7e7SThierry Reding}; 2182