1b2441318SGreg Kroah-Hartman// SPDX-License-Identifier: GPL-2.0 2742af7e7SThierry Reding#include <dt-bindings/clock/tegra210-car.h> 3742af7e7SThierry Reding#include <dt-bindings/gpio/tegra-gpio.h> 4742af7e7SThierry Reding#include <dt-bindings/memory/tegra210-mc.h> 5742af7e7SThierry Reding#include <dt-bindings/pinctrl/pinctrl-tegra.h> 66641af7eSAapo Vienamo#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 72ceed593SJoseph Lo#include <dt-bindings/reset/tegra210-car.h> 8742af7e7SThierry Reding#include <dt-bindings/interrupt-controller/arm-gic.h> 9e2bed1ebSWei Ni#include <dt-bindings/thermal/tegra124-soctherm.h> 10359ae651SSowjanya Komatineni#include <dt-bindings/soc/tegra-pmc.h> 11742af7e7SThierry Reding 12742af7e7SThierry Reding/ { 13742af7e7SThierry Reding compatible = "nvidia,tegra210"; 14742af7e7SThierry Reding interrupt-parent = <&lic>; 15742af7e7SThierry Reding #address-cells = <2>; 16742af7e7SThierry Reding #size-cells = <2>; 17742af7e7SThierry Reding 18475d99fcSRob Herring pcie@1003000 { 19589a2d3fSThierry Reding compatible = "nvidia,tegra210-pcie"; 20589a2d3fSThierry Reding device_type = "pci"; 21644c569dSThierry Reding reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */ 22644c569dSThierry Reding <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */ 23644c569dSThierry Reding <0x0 0x02000000 0x0 0x10000000>; /* configuration space */ 24589a2d3fSThierry Reding reg-names = "pads", "afi", "cs"; 25589a2d3fSThierry Reding interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 26589a2d3fSThierry Reding <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 27589a2d3fSThierry Reding interrupt-names = "intr", "msi"; 28589a2d3fSThierry Reding 29589a2d3fSThierry Reding #interrupt-cells = <1>; 30589a2d3fSThierry Reding interrupt-map-mask = <0 0 0 0>; 31589a2d3fSThierry Reding interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 32589a2d3fSThierry Reding 33589a2d3fSThierry Reding bus-range = <0x00 0xff>; 34589a2d3fSThierry Reding #address-cells = <3>; 35589a2d3fSThierry Reding #size-cells = <2>; 36589a2d3fSThierry Reding 37644c569dSThierry Reding ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */ 38644c569dSThierry Reding <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */ 39644c569dSThierry Reding <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */ 40644c569dSThierry Reding <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */ 41644c569dSThierry Reding <0x42000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ 42589a2d3fSThierry Reding 43589a2d3fSThierry Reding clocks = <&tegra_car TEGRA210_CLK_PCIE>, 44589a2d3fSThierry Reding <&tegra_car TEGRA210_CLK_AFI>, 45589a2d3fSThierry Reding <&tegra_car TEGRA210_CLK_PLL_E>, 46589a2d3fSThierry Reding <&tegra_car TEGRA210_CLK_CML0>; 47589a2d3fSThierry Reding clock-names = "pex", "afi", "pll_e", "cml"; 48589a2d3fSThierry Reding resets = <&tegra_car 70>, 49589a2d3fSThierry Reding <&tegra_car 72>, 50589a2d3fSThierry Reding <&tegra_car 74>; 51589a2d3fSThierry Reding reset-names = "pex", "afi", "pcie_x"; 52871be845SManikanta Maddireddy 53871be845SManikanta Maddireddy pinctrl-names = "default", "idle"; 54871be845SManikanta Maddireddy pinctrl-0 = <&pex_dpd_disable>; 55871be845SManikanta Maddireddy pinctrl-1 = <&pex_dpd_enable>; 56871be845SManikanta Maddireddy 57589a2d3fSThierry Reding status = "disabled"; 58589a2d3fSThierry Reding 59589a2d3fSThierry Reding pci@1,0 { 60589a2d3fSThierry Reding device_type = "pci"; 61589a2d3fSThierry Reding assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>; 62589a2d3fSThierry Reding reg = <0x000800 0 0 0 0>; 63475d99fcSRob Herring bus-range = <0x00 0xff>; 64589a2d3fSThierry Reding status = "disabled"; 65589a2d3fSThierry Reding 66589a2d3fSThierry Reding #address-cells = <3>; 67589a2d3fSThierry Reding #size-cells = <2>; 68589a2d3fSThierry Reding ranges; 69589a2d3fSThierry Reding 70589a2d3fSThierry Reding nvidia,num-lanes = <4>; 71589a2d3fSThierry Reding }; 72589a2d3fSThierry Reding 73589a2d3fSThierry Reding pci@2,0 { 74589a2d3fSThierry Reding device_type = "pci"; 75589a2d3fSThierry Reding assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>; 76589a2d3fSThierry Reding reg = <0x001000 0 0 0 0>; 77475d99fcSRob Herring bus-range = <0x00 0xff>; 78589a2d3fSThierry Reding status = "disabled"; 79589a2d3fSThierry Reding 80589a2d3fSThierry Reding #address-cells = <3>; 81589a2d3fSThierry Reding #size-cells = <2>; 82589a2d3fSThierry Reding ranges; 83589a2d3fSThierry Reding 84589a2d3fSThierry Reding nvidia,num-lanes = <1>; 85589a2d3fSThierry Reding }; 86589a2d3fSThierry Reding }; 87589a2d3fSThierry Reding 88be70771dSThierry Reding host1x@50000000 { 89ef126bc4SThierry Reding compatible = "nvidia,tegra210-host1x"; 90742af7e7SThierry Reding reg = <0x0 0x50000000 0x0 0x00034000>; 91742af7e7SThierry Reding interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 92742af7e7SThierry Reding <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ 93052d3f65SThierry Reding interrupt-names = "syncpt", "host1x"; 94742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_HOST1X>; 95742af7e7SThierry Reding clock-names = "host1x"; 96742af7e7SThierry Reding resets = <&tegra_car 28>; 97742af7e7SThierry Reding reset-names = "host1x"; 98742af7e7SThierry Reding 99742af7e7SThierry Reding #address-cells = <2>; 100742af7e7SThierry Reding #size-cells = <2>; 101742af7e7SThierry Reding 102742af7e7SThierry Reding ranges = <0x0 0x54000000 0x0 0x54000000 0x0 0x01000000>; 103742af7e7SThierry Reding 104116503a6SMikko Perttunen iommus = <&mc TEGRA_SWGROUP_HC>; 105116503a6SMikko Perttunen 106be70771dSThierry Reding dpaux1: dpaux@54040000 { 107742af7e7SThierry Reding compatible = "nvidia,tegra210-dpaux"; 108742af7e7SThierry Reding reg = <0x0 0x54040000 0x0 0x00040000>; 109742af7e7SThierry Reding interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 110742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_DPAUX1>, 111742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_PLL_DP>; 112742af7e7SThierry Reding clock-names = "dpaux", "parent"; 113742af7e7SThierry Reding resets = <&tegra_car 207>; 114742af7e7SThierry Reding reset-names = "dpaux"; 11596d1f078SJon Hunter power-domains = <&pd_sor>; 116742af7e7SThierry Reding status = "disabled"; 11766b2d6e9SJon Hunter 11866b2d6e9SJon Hunter state_dpaux1_aux: pinmux-aux { 11966b2d6e9SJon Hunter groups = "dpaux-io"; 12066b2d6e9SJon Hunter function = "aux"; 12166b2d6e9SJon Hunter }; 12266b2d6e9SJon Hunter 12366b2d6e9SJon Hunter state_dpaux1_i2c: pinmux-i2c { 12466b2d6e9SJon Hunter groups = "dpaux-io"; 12566b2d6e9SJon Hunter function = "i2c"; 12666b2d6e9SJon Hunter }; 12766b2d6e9SJon Hunter 12866b2d6e9SJon Hunter state_dpaux1_off: pinmux-off { 12966b2d6e9SJon Hunter groups = "dpaux-io"; 13066b2d6e9SJon Hunter function = "off"; 13166b2d6e9SJon Hunter }; 13266b2d6e9SJon Hunter 13366b2d6e9SJon Hunter i2c-bus { 13466b2d6e9SJon Hunter #address-cells = <1>; 13566b2d6e9SJon Hunter #size-cells = <0>; 13666b2d6e9SJon Hunter }; 137742af7e7SThierry Reding }; 138742af7e7SThierry Reding 139be70771dSThierry Reding vi@54080000 { 140742af7e7SThierry Reding compatible = "nvidia,tegra210-vi"; 141c4153885SSowjanya Komatineni reg = <0x0 0x54080000 0x0 0x700>; 142742af7e7SThierry Reding interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 143742af7e7SThierry Reding status = "disabled"; 144c4153885SSowjanya Komatineni assigned-clocks = <&tegra_car TEGRA210_CLK_VI>; 145c4153885SSowjanya Komatineni assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 146c4153885SSowjanya Komatineni 147c4153885SSowjanya Komatineni clocks = <&tegra_car TEGRA210_CLK_VI>; 148c4153885SSowjanya Komatineni power-domains = <&pd_venc>; 149c4153885SSowjanya Komatineni 150c4153885SSowjanya Komatineni #address-cells = <1>; 151c4153885SSowjanya Komatineni #size-cells = <1>; 152c4153885SSowjanya Komatineni 153c4153885SSowjanya Komatineni ranges = <0x0 0x0 0x54080000 0x2000>; 154c4153885SSowjanya Komatineni 155c4153885SSowjanya Komatineni csi@838 { 156c4153885SSowjanya Komatineni compatible = "nvidia,tegra210-csi"; 157c4153885SSowjanya Komatineni reg = <0x838 0x1300>; 158c4153885SSowjanya Komatineni status = "disabled"; 159c4153885SSowjanya Komatineni assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>, 160c4153885SSowjanya Komatineni <&tegra_car TEGRA210_CLK_CILCD>, 161c4153885SSowjanya Komatineni <&tegra_car TEGRA210_CLK_CILE>, 162c4153885SSowjanya Komatineni <&tegra_car TEGRA210_CLK_CSI_TPG>; 163c4153885SSowjanya Komatineni assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>, 164c4153885SSowjanya Komatineni <&tegra_car TEGRA210_CLK_PLL_P>, 165c4153885SSowjanya Komatineni <&tegra_car TEGRA210_CLK_PLL_P>; 166c4153885SSowjanya Komatineni assigned-clock-rates = <102000000>, 167c4153885SSowjanya Komatineni <102000000>, 168c4153885SSowjanya Komatineni <102000000>, 169c4153885SSowjanya Komatineni <972000000>; 170c4153885SSowjanya Komatineni 171c4153885SSowjanya Komatineni clocks = <&tegra_car TEGRA210_CLK_CSI>, 172c4153885SSowjanya Komatineni <&tegra_car TEGRA210_CLK_CILAB>, 173c4153885SSowjanya Komatineni <&tegra_car TEGRA210_CLK_CILCD>, 174c4153885SSowjanya Komatineni <&tegra_car TEGRA210_CLK_CILE>, 175c4153885SSowjanya Komatineni <&tegra_car TEGRA210_CLK_CSI_TPG>; 176c4153885SSowjanya Komatineni clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg"; 177c4153885SSowjanya Komatineni power-domains = <&pd_sor>; 178c4153885SSowjanya Komatineni }; 179742af7e7SThierry Reding }; 180742af7e7SThierry Reding 181be70771dSThierry Reding tsec@54100000 { 182742af7e7SThierry Reding compatible = "nvidia,tegra210-tsec"; 183742af7e7SThierry Reding reg = <0x0 0x54100000 0x0 0x00040000>; 184742af7e7SThierry Reding }; 185742af7e7SThierry Reding 186be70771dSThierry Reding dc@54200000 { 187742af7e7SThierry Reding compatible = "nvidia,tegra210-dc"; 188742af7e7SThierry Reding reg = <0x0 0x54200000 0x0 0x00040000>; 189742af7e7SThierry Reding interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 190352092b0SThierry Reding clocks = <&tegra_car TEGRA210_CLK_DISP1>; 191352092b0SThierry Reding clock-names = "dc"; 192742af7e7SThierry Reding resets = <&tegra_car 27>; 193742af7e7SThierry Reding reset-names = "dc"; 194742af7e7SThierry Reding 195742af7e7SThierry Reding iommus = <&mc TEGRA_SWGROUP_DC>; 196742af7e7SThierry Reding 197742af7e7SThierry Reding nvidia,head = <0>; 198742af7e7SThierry Reding }; 199742af7e7SThierry Reding 200be70771dSThierry Reding dc@54240000 { 201742af7e7SThierry Reding compatible = "nvidia,tegra210-dc"; 202742af7e7SThierry Reding reg = <0x0 0x54240000 0x0 0x00040000>; 203742af7e7SThierry Reding interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 204352092b0SThierry Reding clocks = <&tegra_car TEGRA210_CLK_DISP2>; 205352092b0SThierry Reding clock-names = "dc"; 206742af7e7SThierry Reding resets = <&tegra_car 26>; 207742af7e7SThierry Reding reset-names = "dc"; 208742af7e7SThierry Reding 209742af7e7SThierry Reding iommus = <&mc TEGRA_SWGROUP_DCB>; 210742af7e7SThierry Reding 211742af7e7SThierry Reding nvidia,head = <1>; 212742af7e7SThierry Reding }; 213742af7e7SThierry Reding 214be70771dSThierry Reding dsi@54300000 { 215742af7e7SThierry Reding compatible = "nvidia,tegra210-dsi"; 216742af7e7SThierry Reding reg = <0x0 0x54300000 0x0 0x00040000>; 217742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_DSIA>, 218742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_DSIALP>, 219742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; 220742af7e7SThierry Reding clock-names = "dsi", "lp", "parent"; 221742af7e7SThierry Reding resets = <&tegra_car 48>; 222742af7e7SThierry Reding reset-names = "dsi"; 22396d1f078SJon Hunter power-domains = <&pd_sor>; 224742af7e7SThierry Reding nvidia,mipi-calibrate = <&mipi 0x0c0>; /* DSIA & DSIB pads */ 225742af7e7SThierry Reding 226742af7e7SThierry Reding status = "disabled"; 227742af7e7SThierry Reding 228742af7e7SThierry Reding #address-cells = <1>; 229742af7e7SThierry Reding #size-cells = <0>; 230742af7e7SThierry Reding }; 231742af7e7SThierry Reding 232be70771dSThierry Reding vic@54340000 { 233742af7e7SThierry Reding compatible = "nvidia,tegra210-vic"; 234742af7e7SThierry Reding reg = <0x0 0x54340000 0x0 0x00040000>; 23524963d1bSMikko Perttunen interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 23624963d1bSMikko Perttunen clocks = <&tegra_car TEGRA210_CLK_VIC03>; 23724963d1bSMikko Perttunen clock-names = "vic"; 23824963d1bSMikko Perttunen resets = <&tegra_car 178>; 23924963d1bSMikko Perttunen reset-names = "vic"; 24024963d1bSMikko Perttunen 24124963d1bSMikko Perttunen iommus = <&mc TEGRA_SWGROUP_VIC>; 24224963d1bSMikko Perttunen power-domains = <&pd_vic>; 243742af7e7SThierry Reding }; 244742af7e7SThierry Reding 245be70771dSThierry Reding nvjpg@54380000 { 246742af7e7SThierry Reding compatible = "nvidia,tegra210-nvjpg"; 247742af7e7SThierry Reding reg = <0x0 0x54380000 0x0 0x00040000>; 248742af7e7SThierry Reding status = "disabled"; 249742af7e7SThierry Reding }; 250742af7e7SThierry Reding 251be70771dSThierry Reding dsi@54400000 { 252742af7e7SThierry Reding compatible = "nvidia,tegra210-dsi"; 253742af7e7SThierry Reding reg = <0x0 0x54400000 0x0 0x00040000>; 254742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_DSIB>, 255742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_DSIBLP>, 256742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; 257742af7e7SThierry Reding clock-names = "dsi", "lp", "parent"; 258742af7e7SThierry Reding resets = <&tegra_car 82>; 259742af7e7SThierry Reding reset-names = "dsi"; 26096d1f078SJon Hunter power-domains = <&pd_sor>; 261742af7e7SThierry Reding nvidia,mipi-calibrate = <&mipi 0x300>; /* DSIC & DSID pads */ 262742af7e7SThierry Reding 263742af7e7SThierry Reding status = "disabled"; 264742af7e7SThierry Reding 265742af7e7SThierry Reding #address-cells = <1>; 266742af7e7SThierry Reding #size-cells = <0>; 267742af7e7SThierry Reding }; 268742af7e7SThierry Reding 269be70771dSThierry Reding nvdec@54480000 { 270742af7e7SThierry Reding compatible = "nvidia,tegra210-nvdec"; 271742af7e7SThierry Reding reg = <0x0 0x54480000 0x0 0x00040000>; 272742af7e7SThierry Reding status = "disabled"; 273742af7e7SThierry Reding }; 274742af7e7SThierry Reding 275be70771dSThierry Reding nvenc@544c0000 { 276742af7e7SThierry Reding compatible = "nvidia,tegra210-nvenc"; 277742af7e7SThierry Reding reg = <0x0 0x544c0000 0x0 0x00040000>; 278742af7e7SThierry Reding status = "disabled"; 279742af7e7SThierry Reding }; 280742af7e7SThierry Reding 281be70771dSThierry Reding tsec@54500000 { 282742af7e7SThierry Reding compatible = "nvidia,tegra210-tsec"; 283742af7e7SThierry Reding reg = <0x0 0x54500000 0x0 0x00040000>; 284742af7e7SThierry Reding status = "disabled"; 285742af7e7SThierry Reding }; 286742af7e7SThierry Reding 287be70771dSThierry Reding sor@54540000 { 288742af7e7SThierry Reding compatible = "nvidia,tegra210-sor"; 289742af7e7SThierry Reding reg = <0x0 0x54540000 0x0 0x00040000>; 290742af7e7SThierry Reding interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 291742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_SOR0>, 292ed93a666SThierry Reding <&tegra_car TEGRA210_CLK_SOR0_OUT>, 293742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_PLL_D_OUT0>, 294742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_PLL_DP>, 295742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_SOR_SAFE>; 296ed93a666SThierry Reding clock-names = "sor", "out", "parent", "dp", "safe"; 297742af7e7SThierry Reding resets = <&tegra_car 182>; 298742af7e7SThierry Reding reset-names = "sor"; 29966b2d6e9SJon Hunter pinctrl-0 = <&state_dpaux_aux>; 30066b2d6e9SJon Hunter pinctrl-1 = <&state_dpaux_i2c>; 30166b2d6e9SJon Hunter pinctrl-2 = <&state_dpaux_off>; 30266b2d6e9SJon Hunter pinctrl-names = "aux", "i2c", "off"; 30396d1f078SJon Hunter power-domains = <&pd_sor>; 304742af7e7SThierry Reding status = "disabled"; 305742af7e7SThierry Reding }; 306742af7e7SThierry Reding 307be70771dSThierry Reding sor@54580000 { 308742af7e7SThierry Reding compatible = "nvidia,tegra210-sor1"; 309742af7e7SThierry Reding reg = <0x0 0x54580000 0x0 0x00040000>; 310742af7e7SThierry Reding interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 311742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_SOR1>, 31250f5b841SThierry Reding <&tegra_car TEGRA210_CLK_SOR1_OUT>, 313742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_PLL_D2_OUT0>, 314742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_PLL_DP>, 315742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_SOR_SAFE>; 31650f5b841SThierry Reding clock-names = "sor", "out", "parent", "dp", "safe"; 317742af7e7SThierry Reding resets = <&tegra_car 183>; 318742af7e7SThierry Reding reset-names = "sor"; 31966b2d6e9SJon Hunter pinctrl-0 = <&state_dpaux1_aux>; 32066b2d6e9SJon Hunter pinctrl-1 = <&state_dpaux1_i2c>; 32166b2d6e9SJon Hunter pinctrl-2 = <&state_dpaux1_off>; 32266b2d6e9SJon Hunter pinctrl-names = "aux", "i2c", "off"; 32396d1f078SJon Hunter power-domains = <&pd_sor>; 324742af7e7SThierry Reding status = "disabled"; 325742af7e7SThierry Reding }; 326742af7e7SThierry Reding 327be70771dSThierry Reding dpaux: dpaux@545c0000 { 328e989992aSThierry Reding compatible = "nvidia,tegra210-dpaux"; 329742af7e7SThierry Reding reg = <0x0 0x545c0000 0x0 0x00040000>; 330742af7e7SThierry Reding interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 331742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_DPAUX>, 332742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_PLL_DP>; 333742af7e7SThierry Reding clock-names = "dpaux", "parent"; 334742af7e7SThierry Reding resets = <&tegra_car 181>; 335742af7e7SThierry Reding reset-names = "dpaux"; 33696d1f078SJon Hunter power-domains = <&pd_sor>; 337742af7e7SThierry Reding status = "disabled"; 33866b2d6e9SJon Hunter 33966b2d6e9SJon Hunter state_dpaux_aux: pinmux-aux { 34066b2d6e9SJon Hunter groups = "dpaux-io"; 34166b2d6e9SJon Hunter function = "aux"; 34266b2d6e9SJon Hunter }; 34366b2d6e9SJon Hunter 34466b2d6e9SJon Hunter state_dpaux_i2c: pinmux-i2c { 34566b2d6e9SJon Hunter groups = "dpaux-io"; 34666b2d6e9SJon Hunter function = "i2c"; 34766b2d6e9SJon Hunter }; 34866b2d6e9SJon Hunter 34966b2d6e9SJon Hunter state_dpaux_off: pinmux-off { 35066b2d6e9SJon Hunter groups = "dpaux-io"; 35166b2d6e9SJon Hunter function = "off"; 35266b2d6e9SJon Hunter }; 35366b2d6e9SJon Hunter 35466b2d6e9SJon Hunter i2c-bus { 35566b2d6e9SJon Hunter #address-cells = <1>; 35666b2d6e9SJon Hunter #size-cells = <0>; 35766b2d6e9SJon Hunter }; 358742af7e7SThierry Reding }; 359742af7e7SThierry Reding 360be70771dSThierry Reding isp@54600000 { 361742af7e7SThierry Reding compatible = "nvidia,tegra210-isp"; 362742af7e7SThierry Reding reg = <0x0 0x54600000 0x0 0x00040000>; 363742af7e7SThierry Reding interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 36497ace1b4SThierry Reding clocks = <&tegra_car TEGRA210_CLK_ISPA>; 36597ace1b4SThierry Reding resets = <&tegra_car 23>; 36697ace1b4SThierry Reding reset-names = "isp"; 367742af7e7SThierry Reding status = "disabled"; 368742af7e7SThierry Reding }; 369742af7e7SThierry Reding 370be70771dSThierry Reding isp@54680000 { 371742af7e7SThierry Reding compatible = "nvidia,tegra210-isp"; 372742af7e7SThierry Reding reg = <0x0 0x54680000 0x0 0x00040000>; 373742af7e7SThierry Reding interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 37497ace1b4SThierry Reding clocks = <&tegra_car TEGRA210_CLK_ISPB>; 37597ace1b4SThierry Reding resets = <&tegra_car 3>; 37697ace1b4SThierry Reding reset-names = "isp"; 377742af7e7SThierry Reding status = "disabled"; 378742af7e7SThierry Reding }; 379742af7e7SThierry Reding 380be70771dSThierry Reding i2c@546c0000 { 381742af7e7SThierry Reding compatible = "nvidia,tegra210-i2c-vi"; 382742af7e7SThierry Reding reg = <0x0 0x546c0000 0x0 0x00040000>; 383742af7e7SThierry Reding interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 384139a390cSSowjanya Komatineni clocks = <&tegra_car TEGRA210_CLK_VI_I2C>, 385139a390cSSowjanya Komatineni <&tegra_car TEGRA210_CLK_I2CSLOW>; 386139a390cSSowjanya Komatineni clock-names = "div-clk", "slow"; 387139a390cSSowjanya Komatineni resets = <&tegra_car 208>; 388139a390cSSowjanya Komatineni reset-names = "i2c"; 389139a390cSSowjanya Komatineni power-domains = <&pd_venc>; 390742af7e7SThierry Reding status = "disabled"; 3914087162fSThierry Reding 3924087162fSThierry Reding #address-cells = <1>; 3934087162fSThierry Reding #size-cells = <0>; 394742af7e7SThierry Reding }; 395742af7e7SThierry Reding }; 396742af7e7SThierry Reding 397be70771dSThierry Reding gic: interrupt-controller@50041000 { 398742af7e7SThierry Reding compatible = "arm,gic-400"; 399742af7e7SThierry Reding #interrupt-cells = <3>; 400742af7e7SThierry Reding interrupt-controller; 401742af7e7SThierry Reding reg = <0x0 0x50041000 0x0 0x1000>, 402742af7e7SThierry Reding <0x0 0x50042000 0x0 0x2000>, 403742af7e7SThierry Reding <0x0 0x50044000 0x0 0x2000>, 404742af7e7SThierry Reding <0x0 0x50046000 0x0 0x2000>; 405742af7e7SThierry Reding interrupts = <GIC_PPI 9 406742af7e7SThierry Reding (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 407742af7e7SThierry Reding interrupt-parent = <&gic>; 408742af7e7SThierry Reding }; 409742af7e7SThierry Reding 410be70771dSThierry Reding gpu@57000000 { 411742af7e7SThierry Reding compatible = "nvidia,gm20b"; 412742af7e7SThierry Reding reg = <0x0 0x57000000 0x0 0x01000000>, 413742af7e7SThierry Reding <0x0 0x58000000 0x0 0x01000000>; 414742af7e7SThierry Reding interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 415742af7e7SThierry Reding <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 416742af7e7SThierry Reding interrupt-names = "stall", "nonstall"; 417742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_GPU>, 4184a0778e9SAlexandre Courbot <&tegra_car TEGRA210_CLK_PLL_P_OUT5>, 4194a0778e9SAlexandre Courbot <&tegra_car TEGRA210_CLK_PLL_G_REF>; 4204a0778e9SAlexandre Courbot clock-names = "gpu", "pwr", "ref"; 421742af7e7SThierry Reding resets = <&tegra_car 184>; 422742af7e7SThierry Reding reset-names = "gpu"; 42330f949bcSAlexandre Courbot 42430f949bcSAlexandre Courbot iommus = <&mc TEGRA_SWGROUP_GPU>; 42530f949bcSAlexandre Courbot 426742af7e7SThierry Reding status = "disabled"; 427742af7e7SThierry Reding }; 428742af7e7SThierry Reding 429be70771dSThierry Reding lic: interrupt-controller@60004000 { 430742af7e7SThierry Reding compatible = "nvidia,tegra210-ictlr"; 431742af7e7SThierry Reding reg = <0x0 0x60004000 0x0 0x40>, /* primary controller */ 432742af7e7SThierry Reding <0x0 0x60004100 0x0 0x40>, /* secondary controller */ 433742af7e7SThierry Reding <0x0 0x60004200 0x0 0x40>, /* tertiary controller */ 434742af7e7SThierry Reding <0x0 0x60004300 0x0 0x40>, /* quaternary controller */ 435742af7e7SThierry Reding <0x0 0x60004400 0x0 0x40>, /* quinary controller */ 436742af7e7SThierry Reding <0x0 0x60004500 0x0 0x40>; /* senary controller */ 437742af7e7SThierry Reding interrupt-controller; 438742af7e7SThierry Reding #interrupt-cells = <3>; 439742af7e7SThierry Reding interrupt-parent = <&gic>; 440742af7e7SThierry Reding }; 441742af7e7SThierry Reding 442be70771dSThierry Reding timer@60005000 { 443d9931a18SJoseph Lo compatible = "nvidia,tegra210-timer"; 444742af7e7SThierry Reding reg = <0x0 0x60005000 0x0 0x400>; 445d9931a18SJoseph Lo interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 446d9931a18SJoseph Lo <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 447742af7e7SThierry Reding <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 448742af7e7SThierry Reding <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 449742af7e7SThierry Reding <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 450742af7e7SThierry Reding <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 451d9931a18SJoseph Lo <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 452d9931a18SJoseph Lo <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 453d9931a18SJoseph Lo <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 454d9931a18SJoseph Lo <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 455d9931a18SJoseph Lo <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 456d9931a18SJoseph Lo <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 457d9931a18SJoseph Lo <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, 458d9931a18SJoseph Lo <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 459742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_TIMER>; 460742af7e7SThierry Reding clock-names = "timer"; 461742af7e7SThierry Reding }; 462742af7e7SThierry Reding 463be70771dSThierry Reding tegra_car: clock@60006000 { 464742af7e7SThierry Reding compatible = "nvidia,tegra210-car"; 465742af7e7SThierry Reding reg = <0x0 0x60006000 0x0 0x1000>; 466742af7e7SThierry Reding #clock-cells = <1>; 467742af7e7SThierry Reding #reset-cells = <1>; 468742af7e7SThierry Reding }; 469742af7e7SThierry Reding 470be70771dSThierry Reding flow-controller@60007000 { 471742af7e7SThierry Reding compatible = "nvidia,tegra210-flowctrl"; 472742af7e7SThierry Reding reg = <0x0 0x60007000 0x0 0x1000>; 473742af7e7SThierry Reding }; 474742af7e7SThierry Reding 475be70771dSThierry Reding gpio: gpio@6000d000 { 47601665512SStephen Warren compatible = "nvidia,tegra210-gpio", "nvidia,tegra30-gpio"; 477742af7e7SThierry Reding reg = <0x0 0x6000d000 0x0 0x1000>; 478742af7e7SThierry Reding interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 479742af7e7SThierry Reding <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 480742af7e7SThierry Reding <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 481742af7e7SThierry Reding <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 482742af7e7SThierry Reding <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 483742af7e7SThierry Reding <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 484742af7e7SThierry Reding <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 485742af7e7SThierry Reding <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 486742af7e7SThierry Reding #gpio-cells = <2>; 487742af7e7SThierry Reding gpio-controller; 488742af7e7SThierry Reding #interrupt-cells = <2>; 489742af7e7SThierry Reding interrupt-controller; 490742af7e7SThierry Reding }; 491742af7e7SThierry Reding 492be70771dSThierry Reding apbdma: dma@60020000 { 493742af7e7SThierry Reding compatible = "nvidia,tegra210-apbdma", "nvidia,tegra148-apbdma"; 494742af7e7SThierry Reding reg = <0x0 0x60020000 0x0 0x1400>; 495742af7e7SThierry Reding interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 496742af7e7SThierry Reding <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 497742af7e7SThierry Reding <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 498742af7e7SThierry Reding <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 499742af7e7SThierry Reding <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 500742af7e7SThierry Reding <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 501742af7e7SThierry Reding <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 502742af7e7SThierry Reding <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 503742af7e7SThierry Reding <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 504742af7e7SThierry Reding <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 505742af7e7SThierry Reding <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 506742af7e7SThierry Reding <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 507742af7e7SThierry Reding <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 508742af7e7SThierry Reding <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 509742af7e7SThierry Reding <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 510742af7e7SThierry Reding <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 511742af7e7SThierry Reding <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 512742af7e7SThierry Reding <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 513742af7e7SThierry Reding <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 514742af7e7SThierry Reding <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 515742af7e7SThierry Reding <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 516742af7e7SThierry Reding <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 517742af7e7SThierry Reding <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 518742af7e7SThierry Reding <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 519742af7e7SThierry Reding <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 520742af7e7SThierry Reding <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 521742af7e7SThierry Reding <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 522742af7e7SThierry Reding <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 523742af7e7SThierry Reding <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 524742af7e7SThierry Reding <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 525742af7e7SThierry Reding <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 526742af7e7SThierry Reding <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 527742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_APBDMA>; 528742af7e7SThierry Reding clock-names = "dma"; 529742af7e7SThierry Reding resets = <&tegra_car 34>; 530742af7e7SThierry Reding reset-names = "dma"; 531742af7e7SThierry Reding #dma-cells = <1>; 532742af7e7SThierry Reding }; 533742af7e7SThierry Reding 534be70771dSThierry Reding apbmisc@70000800 { 535742af7e7SThierry Reding compatible = "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc"; 536742af7e7SThierry Reding reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */ 53746e4b227SJoseph Lo <0x0 0x70000008 0x0 0x04>; /* Strapping options */ 538742af7e7SThierry Reding }; 539742af7e7SThierry Reding 540be70771dSThierry Reding pinmux: pinmux@700008d4 { 541742af7e7SThierry Reding compatible = "nvidia,tegra210-pinmux"; 542742af7e7SThierry Reding reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */ 543742af7e7SThierry Reding <0x0 0x70003000 0x0 0x294>; /* Mux registers */ 5444e0f1229SSowjanya Komatineni sdmmc1_3v3_drv: sdmmc1-3v3-drv { 5454e0f1229SSowjanya Komatineni sdmmc1 { 5464e0f1229SSowjanya Komatineni nvidia,pins = "drive_sdmmc1"; 5474e0f1229SSowjanya Komatineni nvidia,pull-down-strength = <0x8>; 5484e0f1229SSowjanya Komatineni nvidia,pull-up-strength = <0x8>; 5494e0f1229SSowjanya Komatineni }; 5504e0f1229SSowjanya Komatineni }; 5514e0f1229SSowjanya Komatineni sdmmc1_1v8_drv: sdmmc1-1v8-drv { 5524e0f1229SSowjanya Komatineni sdmmc1 { 5534e0f1229SSowjanya Komatineni nvidia,pins = "drive_sdmmc1"; 5544e0f1229SSowjanya Komatineni nvidia,pull-down-strength = <0x4>; 5554e0f1229SSowjanya Komatineni nvidia,pull-up-strength = <0x3>; 5564e0f1229SSowjanya Komatineni }; 5574e0f1229SSowjanya Komatineni }; 5584e0f1229SSowjanya Komatineni sdmmc2_1v8_drv: sdmmc2-1v8-drv { 5594e0f1229SSowjanya Komatineni sdmmc2 { 5604e0f1229SSowjanya Komatineni nvidia,pins = "drive_sdmmc2"; 5614e0f1229SSowjanya Komatineni nvidia,pull-down-strength = <0x10>; 5624e0f1229SSowjanya Komatineni nvidia,pull-up-strength = <0x10>; 5634e0f1229SSowjanya Komatineni }; 5644e0f1229SSowjanya Komatineni }; 5654e0f1229SSowjanya Komatineni sdmmc3_3v3_drv: sdmmc3-3v3-drv { 5664e0f1229SSowjanya Komatineni sdmmc3 { 5674e0f1229SSowjanya Komatineni nvidia,pins = "drive_sdmmc3"; 5684e0f1229SSowjanya Komatineni nvidia,pull-down-strength = <0x8>; 5694e0f1229SSowjanya Komatineni nvidia,pull-up-strength = <0x8>; 5704e0f1229SSowjanya Komatineni }; 5714e0f1229SSowjanya Komatineni }; 5724e0f1229SSowjanya Komatineni sdmmc3_1v8_drv: sdmmc3-1v8-drv { 5734e0f1229SSowjanya Komatineni sdmmc3 { 5744e0f1229SSowjanya Komatineni nvidia,pins = "drive_sdmmc3"; 5754e0f1229SSowjanya Komatineni nvidia,pull-down-strength = <0x4>; 5764e0f1229SSowjanya Komatineni nvidia,pull-up-strength = <0x3>; 5774e0f1229SSowjanya Komatineni }; 5784e0f1229SSowjanya Komatineni }; 5794e0f1229SSowjanya Komatineni sdmmc4_1v8_drv: sdmmc4-1v8-drv { 5804e0f1229SSowjanya Komatineni sdmmc4 { 5814e0f1229SSowjanya Komatineni nvidia,pins = "drive_sdmmc4"; 5824e0f1229SSowjanya Komatineni nvidia,pull-down-strength = <0x10>; 5834e0f1229SSowjanya Komatineni nvidia,pull-up-strength = <0x10>; 5844e0f1229SSowjanya Komatineni }; 5854e0f1229SSowjanya Komatineni }; 586742af7e7SThierry Reding }; 587742af7e7SThierry Reding 588742af7e7SThierry Reding /* 589742af7e7SThierry Reding * There are two serial driver i.e. 8250 based simple serial 590742af7e7SThierry Reding * driver and APB DMA based serial driver for higher baudrate 591ef769e32SAdam Buchbinder * and performance. To enable the 8250 based driver, the compatible 592742af7e7SThierry Reding * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable 59368cd8b2eSThierry Reding * the APB DMA based serial driver, the compatible is 594742af7e7SThierry Reding * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". 595742af7e7SThierry Reding */ 596be70771dSThierry Reding uarta: serial@70006000 { 597742af7e7SThierry Reding compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 598742af7e7SThierry Reding reg = <0x0 0x70006000 0x0 0x40>; 599742af7e7SThierry Reding reg-shift = <2>; 600742af7e7SThierry Reding interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 601742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_UARTA>; 602742af7e7SThierry Reding clock-names = "serial"; 603742af7e7SThierry Reding resets = <&tegra_car 6>; 604742af7e7SThierry Reding reset-names = "serial"; 605742af7e7SThierry Reding dmas = <&apbdma 8>, <&apbdma 8>; 606742af7e7SThierry Reding dma-names = "rx", "tx"; 607742af7e7SThierry Reding status = "disabled"; 608742af7e7SThierry Reding }; 609742af7e7SThierry Reding 610be70771dSThierry Reding uartb: serial@70006040 { 611742af7e7SThierry Reding compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 612742af7e7SThierry Reding reg = <0x0 0x70006040 0x0 0x40>; 613742af7e7SThierry Reding reg-shift = <2>; 614742af7e7SThierry Reding interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 615742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_UARTB>; 616742af7e7SThierry Reding clock-names = "serial"; 617742af7e7SThierry Reding resets = <&tegra_car 7>; 618742af7e7SThierry Reding reset-names = "serial"; 619742af7e7SThierry Reding dmas = <&apbdma 9>, <&apbdma 9>; 620742af7e7SThierry Reding dma-names = "rx", "tx"; 621742af7e7SThierry Reding status = "disabled"; 622742af7e7SThierry Reding }; 623742af7e7SThierry Reding 624be70771dSThierry Reding uartc: serial@70006200 { 625742af7e7SThierry Reding compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 626742af7e7SThierry Reding reg = <0x0 0x70006200 0x0 0x40>; 627742af7e7SThierry Reding reg-shift = <2>; 628742af7e7SThierry Reding interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 629742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_UARTC>; 630742af7e7SThierry Reding clock-names = "serial"; 631742af7e7SThierry Reding resets = <&tegra_car 55>; 632742af7e7SThierry Reding reset-names = "serial"; 633742af7e7SThierry Reding dmas = <&apbdma 10>, <&apbdma 10>; 634742af7e7SThierry Reding dma-names = "rx", "tx"; 635742af7e7SThierry Reding status = "disabled"; 636742af7e7SThierry Reding }; 637742af7e7SThierry Reding 638be70771dSThierry Reding uartd: serial@70006300 { 639742af7e7SThierry Reding compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 640742af7e7SThierry Reding reg = <0x0 0x70006300 0x0 0x40>; 641742af7e7SThierry Reding reg-shift = <2>; 642742af7e7SThierry Reding interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 643742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_UARTD>; 644742af7e7SThierry Reding clock-names = "serial"; 645742af7e7SThierry Reding resets = <&tegra_car 65>; 646742af7e7SThierry Reding reset-names = "serial"; 647742af7e7SThierry Reding dmas = <&apbdma 19>, <&apbdma 19>; 648742af7e7SThierry Reding dma-names = "rx", "tx"; 649742af7e7SThierry Reding status = "disabled"; 650742af7e7SThierry Reding }; 651742af7e7SThierry Reding 652be70771dSThierry Reding pwm: pwm@7000a000 { 653742af7e7SThierry Reding compatible = "nvidia,tegra210-pwm", "nvidia,tegra20-pwm"; 654742af7e7SThierry Reding reg = <0x0 0x7000a000 0x0 0x100>; 655742af7e7SThierry Reding #pwm-cells = <2>; 656742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_PWM>; 657742af7e7SThierry Reding clock-names = "pwm"; 658742af7e7SThierry Reding resets = <&tegra_car 17>; 659742af7e7SThierry Reding reset-names = "pwm"; 660742af7e7SThierry Reding status = "disabled"; 661742af7e7SThierry Reding }; 662742af7e7SThierry Reding 663be70771dSThierry Reding i2c@7000c000 { 664140723b9SSowjanya Komatineni compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 665742af7e7SThierry Reding reg = <0x0 0x7000c000 0x0 0x100>; 666742af7e7SThierry Reding interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 667742af7e7SThierry Reding #address-cells = <1>; 668742af7e7SThierry Reding #size-cells = <0>; 669742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_I2C1>; 670742af7e7SThierry Reding clock-names = "div-clk"; 671742af7e7SThierry Reding resets = <&tegra_car 12>; 672742af7e7SThierry Reding reset-names = "i2c"; 673742af7e7SThierry Reding dmas = <&apbdma 21>, <&apbdma 21>; 674742af7e7SThierry Reding dma-names = "rx", "tx"; 675742af7e7SThierry Reding status = "disabled"; 676742af7e7SThierry Reding }; 677742af7e7SThierry Reding 678be70771dSThierry Reding i2c@7000c400 { 679140723b9SSowjanya Komatineni compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 680742af7e7SThierry Reding reg = <0x0 0x7000c400 0x0 0x100>; 681742af7e7SThierry Reding interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 682742af7e7SThierry Reding #address-cells = <1>; 683742af7e7SThierry Reding #size-cells = <0>; 684742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_I2C2>; 685742af7e7SThierry Reding clock-names = "div-clk"; 686742af7e7SThierry Reding resets = <&tegra_car 54>; 687742af7e7SThierry Reding reset-names = "i2c"; 688742af7e7SThierry Reding dmas = <&apbdma 22>, <&apbdma 22>; 689742af7e7SThierry Reding dma-names = "rx", "tx"; 690742af7e7SThierry Reding status = "disabled"; 691742af7e7SThierry Reding }; 692742af7e7SThierry Reding 693be70771dSThierry Reding i2c@7000c500 { 694140723b9SSowjanya Komatineni compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 695742af7e7SThierry Reding reg = <0x0 0x7000c500 0x0 0x100>; 696742af7e7SThierry Reding interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 697742af7e7SThierry Reding #address-cells = <1>; 698742af7e7SThierry Reding #size-cells = <0>; 699742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_I2C3>; 700742af7e7SThierry Reding clock-names = "div-clk"; 701742af7e7SThierry Reding resets = <&tegra_car 67>; 702742af7e7SThierry Reding reset-names = "i2c"; 703742af7e7SThierry Reding dmas = <&apbdma 23>, <&apbdma 23>; 704742af7e7SThierry Reding dma-names = "rx", "tx"; 705742af7e7SThierry Reding status = "disabled"; 706742af7e7SThierry Reding }; 707742af7e7SThierry Reding 708be70771dSThierry Reding i2c@7000c700 { 709140723b9SSowjanya Komatineni compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 710742af7e7SThierry Reding reg = <0x0 0x7000c700 0x0 0x100>; 711742af7e7SThierry Reding interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 712742af7e7SThierry Reding #address-cells = <1>; 713742af7e7SThierry Reding #size-cells = <0>; 714742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_I2C4>; 715742af7e7SThierry Reding clock-names = "div-clk"; 716742af7e7SThierry Reding resets = <&tegra_car 103>; 717742af7e7SThierry Reding reset-names = "i2c"; 718742af7e7SThierry Reding dmas = <&apbdma 26>, <&apbdma 26>; 719742af7e7SThierry Reding dma-names = "rx", "tx"; 72066b2d6e9SJon Hunter pinctrl-0 = <&state_dpaux1_i2c>; 72166b2d6e9SJon Hunter pinctrl-1 = <&state_dpaux1_off>; 72266b2d6e9SJon Hunter pinctrl-names = "default", "idle"; 723742af7e7SThierry Reding status = "disabled"; 724742af7e7SThierry Reding }; 725742af7e7SThierry Reding 726be70771dSThierry Reding i2c@7000d000 { 727140723b9SSowjanya Komatineni compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 728742af7e7SThierry Reding reg = <0x0 0x7000d000 0x0 0x100>; 729742af7e7SThierry Reding interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 730742af7e7SThierry Reding #address-cells = <1>; 731742af7e7SThierry Reding #size-cells = <0>; 732742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_I2C5>; 733742af7e7SThierry Reding clock-names = "div-clk"; 734742af7e7SThierry Reding resets = <&tegra_car 47>; 735742af7e7SThierry Reding reset-names = "i2c"; 736742af7e7SThierry Reding dmas = <&apbdma 24>, <&apbdma 24>; 737742af7e7SThierry Reding dma-names = "rx", "tx"; 738742af7e7SThierry Reding status = "disabled"; 739742af7e7SThierry Reding }; 740742af7e7SThierry Reding 741be70771dSThierry Reding i2c@7000d100 { 742140723b9SSowjanya Komatineni compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 743742af7e7SThierry Reding reg = <0x0 0x7000d100 0x0 0x100>; 744742af7e7SThierry Reding interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 745742af7e7SThierry Reding #address-cells = <1>; 746742af7e7SThierry Reding #size-cells = <0>; 747742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_I2C6>; 748742af7e7SThierry Reding clock-names = "div-clk"; 749742af7e7SThierry Reding resets = <&tegra_car 166>; 750742af7e7SThierry Reding reset-names = "i2c"; 751742af7e7SThierry Reding dmas = <&apbdma 30>, <&apbdma 30>; 752742af7e7SThierry Reding dma-names = "rx", "tx"; 75366b2d6e9SJon Hunter pinctrl-0 = <&state_dpaux_i2c>; 75466b2d6e9SJon Hunter pinctrl-1 = <&state_dpaux_off>; 75566b2d6e9SJon Hunter pinctrl-names = "default", "idle"; 756742af7e7SThierry Reding status = "disabled"; 757742af7e7SThierry Reding }; 758742af7e7SThierry Reding 759be70771dSThierry Reding spi@7000d400 { 760742af7e7SThierry Reding compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 761742af7e7SThierry Reding reg = <0x0 0x7000d400 0x0 0x200>; 762742af7e7SThierry Reding interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 763742af7e7SThierry Reding #address-cells = <1>; 764742af7e7SThierry Reding #size-cells = <0>; 765742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_SBC1>; 766742af7e7SThierry Reding clock-names = "spi"; 767742af7e7SThierry Reding resets = <&tegra_car 41>; 768742af7e7SThierry Reding reset-names = "spi"; 769742af7e7SThierry Reding dmas = <&apbdma 15>, <&apbdma 15>; 770742af7e7SThierry Reding dma-names = "rx", "tx"; 771742af7e7SThierry Reding status = "disabled"; 772742af7e7SThierry Reding }; 773742af7e7SThierry Reding 774be70771dSThierry Reding spi@7000d600 { 775742af7e7SThierry Reding compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 776742af7e7SThierry Reding reg = <0x0 0x7000d600 0x0 0x200>; 777742af7e7SThierry Reding interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 778742af7e7SThierry Reding #address-cells = <1>; 779742af7e7SThierry Reding #size-cells = <0>; 780742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_SBC2>; 781742af7e7SThierry Reding clock-names = "spi"; 782742af7e7SThierry Reding resets = <&tegra_car 44>; 783742af7e7SThierry Reding reset-names = "spi"; 784742af7e7SThierry Reding dmas = <&apbdma 16>, <&apbdma 16>; 785742af7e7SThierry Reding dma-names = "rx", "tx"; 786742af7e7SThierry Reding status = "disabled"; 787742af7e7SThierry Reding }; 788742af7e7SThierry Reding 789be70771dSThierry Reding spi@7000d800 { 790742af7e7SThierry Reding compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 791742af7e7SThierry Reding reg = <0x0 0x7000d800 0x0 0x200>; 792742af7e7SThierry Reding interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 793742af7e7SThierry Reding #address-cells = <1>; 794742af7e7SThierry Reding #size-cells = <0>; 795742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_SBC3>; 796742af7e7SThierry Reding clock-names = "spi"; 797742af7e7SThierry Reding resets = <&tegra_car 46>; 798742af7e7SThierry Reding reset-names = "spi"; 799742af7e7SThierry Reding dmas = <&apbdma 17>, <&apbdma 17>; 800742af7e7SThierry Reding dma-names = "rx", "tx"; 801742af7e7SThierry Reding status = "disabled"; 802742af7e7SThierry Reding }; 803742af7e7SThierry Reding 804be70771dSThierry Reding spi@7000da00 { 805742af7e7SThierry Reding compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 806742af7e7SThierry Reding reg = <0x0 0x7000da00 0x0 0x200>; 807742af7e7SThierry Reding interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 808742af7e7SThierry Reding #address-cells = <1>; 809742af7e7SThierry Reding #size-cells = <0>; 810742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_SBC4>; 811742af7e7SThierry Reding clock-names = "spi"; 812742af7e7SThierry Reding resets = <&tegra_car 68>; 813742af7e7SThierry Reding reset-names = "spi"; 814742af7e7SThierry Reding dmas = <&apbdma 18>, <&apbdma 18>; 815742af7e7SThierry Reding dma-names = "rx", "tx"; 816742af7e7SThierry Reding status = "disabled"; 817742af7e7SThierry Reding }; 818742af7e7SThierry Reding 819be70771dSThierry Reding rtc@7000e000 { 820742af7e7SThierry Reding compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc"; 821742af7e7SThierry Reding reg = <0x0 0x7000e000 0x0 0x100>; 822d13c13f4SSowjanya Komatineni interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; 823359ae651SSowjanya Komatineni interrupt-parent = <&tegra_pmc>; 824742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_RTC>; 825742af7e7SThierry Reding clock-names = "rtc"; 826742af7e7SThierry Reding }; 827742af7e7SThierry Reding 828359ae651SSowjanya Komatineni tegra_pmc: pmc@7000e400 { 829742af7e7SThierry Reding compatible = "nvidia,tegra210-pmc"; 830742af7e7SThierry Reding reg = <0x0 0x7000e400 0x0 0x400>; 831742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; 832742af7e7SThierry Reding clock-names = "pclk", "clk32k_in"; 833359ae651SSowjanya Komatineni #clock-cells = <1>; 834d13c13f4SSowjanya Komatineni #interrupt-cells = <2>; 835d13c13f4SSowjanya Komatineni interrupt-controller; 836c2b82445SJon Hunter 837c2b82445SJon Hunter powergates { 838c2b82445SJon Hunter pd_audio: aud { 839c2b82445SJon Hunter clocks = <&tegra_car TEGRA210_CLK_APE>, 840c2b82445SJon Hunter <&tegra_car TEGRA210_CLK_APB2APE>; 841c2b82445SJon Hunter resets = <&tegra_car 198>; 842c2b82445SJon Hunter #power-domain-cells = <0>; 843c2b82445SJon Hunter }; 844241f02baSJon Hunter 84596d1f078SJon Hunter pd_sor: sor { 84696d1f078SJon Hunter clocks = <&tegra_car TEGRA210_CLK_SOR0>, 84796d1f078SJon Hunter <&tegra_car TEGRA210_CLK_SOR1>, 848b4f99176SSowjanya Komatineni <&tegra_car TEGRA210_CLK_CILAB>, 849b4f99176SSowjanya Komatineni <&tegra_car TEGRA210_CLK_CILCD>, 850b4f99176SSowjanya Komatineni <&tegra_car TEGRA210_CLK_CILE>, 85196d1f078SJon Hunter <&tegra_car TEGRA210_CLK_DSIA>, 85296d1f078SJon Hunter <&tegra_car TEGRA210_CLK_DSIB>, 85396d1f078SJon Hunter <&tegra_car TEGRA210_CLK_DPAUX>, 85496d1f078SJon Hunter <&tegra_car TEGRA210_CLK_DPAUX1>, 85596d1f078SJon Hunter <&tegra_car TEGRA210_CLK_MIPI_CAL>; 85696d1f078SJon Hunter resets = <&tegra_car TEGRA210_CLK_SOR0>, 85796d1f078SJon Hunter <&tegra_car TEGRA210_CLK_SOR1>, 85896d1f078SJon Hunter <&tegra_car TEGRA210_CLK_DSIA>, 85996d1f078SJon Hunter <&tegra_car TEGRA210_CLK_DSIB>, 86096d1f078SJon Hunter <&tegra_car TEGRA210_CLK_DPAUX>, 86196d1f078SJon Hunter <&tegra_car TEGRA210_CLK_DPAUX1>, 86296d1f078SJon Hunter <&tegra_car TEGRA210_CLK_MIPI_CAL>; 86396d1f078SJon Hunter #power-domain-cells = <0>; 86496d1f078SJon Hunter }; 86596d1f078SJon Hunter 866241f02baSJon Hunter pd_xusbss: xusba { 867241f02baSJon Hunter clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>; 868241f02baSJon Hunter resets = <&tegra_car TEGRA210_CLK_XUSB_SS>; 869241f02baSJon Hunter #power-domain-cells = <0>; 870241f02baSJon Hunter }; 871241f02baSJon Hunter 872241f02baSJon Hunter pd_xusbdev: xusbb { 873241f02baSJon Hunter clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>; 874241f02baSJon Hunter resets = <&tegra_car 95>; 875241f02baSJon Hunter #power-domain-cells = <0>; 876241f02baSJon Hunter }; 877241f02baSJon Hunter 878241f02baSJon Hunter pd_xusbhost: xusbc { 879241f02baSJon Hunter clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>; 880241f02baSJon Hunter resets = <&tegra_car TEGRA210_CLK_XUSB_HOST>; 881241f02baSJon Hunter #power-domain-cells = <0>; 882241f02baSJon Hunter }; 88324963d1bSMikko Perttunen 88424963d1bSMikko Perttunen pd_vic: vic { 88524963d1bSMikko Perttunen clocks = <&tegra_car TEGRA210_CLK_VIC03>; 88624963d1bSMikko Perttunen clock-names = "vic"; 88724963d1bSMikko Perttunen resets = <&tegra_car 178>; 88824963d1bSMikko Perttunen reset-names = "vic"; 88924963d1bSMikko Perttunen #power-domain-cells = <0>; 89024963d1bSMikko Perttunen }; 891c4153885SSowjanya Komatineni 892c4153885SSowjanya Komatineni pd_venc: venc { 893c4153885SSowjanya Komatineni clocks = <&tegra_car TEGRA210_CLK_VI>, 894c4153885SSowjanya Komatineni <&tegra_car TEGRA210_CLK_CSI>; 895c4153885SSowjanya Komatineni resets = <&mc TEGRA210_MC_RESET_VI>, 896c4153885SSowjanya Komatineni <&tegra_car 20>, 897c4153885SSowjanya Komatineni <&tegra_car 52>; 898c4153885SSowjanya Komatineni #power-domain-cells = <0>; 899c4153885SSowjanya Komatineni }; 900c2b82445SJon Hunter }; 9016641af7eSAapo Vienamo 9026641af7eSAapo Vienamo sdmmc1_3v3: sdmmc1-3v3 { 9036641af7eSAapo Vienamo pins = "sdmmc1"; 9046641af7eSAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 9056641af7eSAapo Vienamo }; 9066641af7eSAapo Vienamo 9076641af7eSAapo Vienamo sdmmc1_1v8: sdmmc1-1v8 { 9086641af7eSAapo Vienamo pins = "sdmmc1"; 9096641af7eSAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 9106641af7eSAapo Vienamo }; 9116641af7eSAapo Vienamo 9126641af7eSAapo Vienamo sdmmc3_3v3: sdmmc3-3v3 { 9136641af7eSAapo Vienamo pins = "sdmmc3"; 9146641af7eSAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 9156641af7eSAapo Vienamo }; 9166641af7eSAapo Vienamo 9176641af7eSAapo Vienamo sdmmc3_1v8: sdmmc3-1v8 { 9186641af7eSAapo Vienamo pins = "sdmmc3"; 9196641af7eSAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 9206641af7eSAapo Vienamo }; 921871be845SManikanta Maddireddy 922871be845SManikanta Maddireddy pex_dpd_disable: pex_en { 923871be845SManikanta Maddireddy pex-dpd-disable { 924871be845SManikanta Maddireddy pins = "pex-bias", "pex-clk1", "pex-clk2"; 925871be845SManikanta Maddireddy low-power-disable; 926871be845SManikanta Maddireddy }; 927871be845SManikanta Maddireddy }; 928871be845SManikanta Maddireddy 929871be845SManikanta Maddireddy pex_dpd_enable: pex_dis { 930871be845SManikanta Maddireddy pex-dpd-enable { 931871be845SManikanta Maddireddy pins = "pex-bias", "pex-clk1", "pex-clk2"; 932871be845SManikanta Maddireddy low-power-enable; 933871be845SManikanta Maddireddy }; 934871be845SManikanta Maddireddy }; 935742af7e7SThierry Reding }; 936742af7e7SThierry Reding 937be70771dSThierry Reding fuse@7000f800 { 938742af7e7SThierry Reding compatible = "nvidia,tegra210-efuse"; 939742af7e7SThierry Reding reg = <0x0 0x7000f800 0x0 0x400>; 940742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_FUSE>; 941742af7e7SThierry Reding clock-names = "fuse"; 942742af7e7SThierry Reding resets = <&tegra_car 39>; 943742af7e7SThierry Reding reset-names = "fuse"; 944742af7e7SThierry Reding }; 945742af7e7SThierry Reding 946be70771dSThierry Reding mc: memory-controller@70019000 { 947742af7e7SThierry Reding compatible = "nvidia,tegra210-mc"; 948742af7e7SThierry Reding reg = <0x0 0x70019000 0x0 0x1000>; 949742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_MC>; 950742af7e7SThierry Reding clock-names = "mc"; 951742af7e7SThierry Reding 952742af7e7SThierry Reding interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 953742af7e7SThierry Reding 954742af7e7SThierry Reding #iommu-cells = <1>; 9552eb8e1a4SSowjanya Komatineni #reset-cells = <1>; 956742af7e7SThierry Reding }; 957742af7e7SThierry Reding 958e12325f6SThierry Reding emc: external-memory-controller@7001b000 { 959cd9350c5SJoseph Lo compatible = "nvidia,tegra210-emc"; 960cd9350c5SJoseph Lo reg = <0x0 0x7001b000 0x0 0x1000>, 961cd9350c5SJoseph Lo <0x0 0x7001e000 0x0 0x1000>, 962cd9350c5SJoseph Lo <0x0 0x7001f000 0x0 0x1000>; 963cd9350c5SJoseph Lo clocks = <&tegra_car TEGRA210_CLK_EMC>; 964cd9350c5SJoseph Lo clock-names = "emc"; 965cd9350c5SJoseph Lo interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 966cd9350c5SJoseph Lo nvidia,memory-controller = <&mc>; 967e12325f6SThierry Reding #cooling-cells = <2>; 968cd9350c5SJoseph Lo }; 969cd9350c5SJoseph Lo 9706cb60ec4SPreetham Ramchandra sata@70020000 { 9716cb60ec4SPreetham Ramchandra compatible = "nvidia,tegra210-ahci"; 9726cb60ec4SPreetham Ramchandra reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */ 9736cb60ec4SPreetham Ramchandra <0x0 0x70020000 0x0 0x7000>, /* SATA */ 9746cb60ec4SPreetham Ramchandra <0x0 0x70001100 0x0 0x1000>; /* SATA AUX */ 9756cb60ec4SPreetham Ramchandra interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 9766cb60ec4SPreetham Ramchandra clocks = <&tegra_car TEGRA210_CLK_SATA>, 9776cb60ec4SPreetham Ramchandra <&tegra_car TEGRA210_CLK_SATA_OOB>; 9786cb60ec4SPreetham Ramchandra clock-names = "sata", "sata-oob"; 9796cb60ec4SPreetham Ramchandra resets = <&tegra_car 124>, 9806cb60ec4SPreetham Ramchandra <&tegra_car 123>, 9816cb60ec4SPreetham Ramchandra <&tegra_car 129>; 9826cb60ec4SPreetham Ramchandra reset-names = "sata", "sata-oob", "sata-cold"; 9836cb60ec4SPreetham Ramchandra status = "disabled"; 9846cb60ec4SPreetham Ramchandra }; 9856cb60ec4SPreetham Ramchandra 986be70771dSThierry Reding hda@70030000 { 987742af7e7SThierry Reding compatible = "nvidia,tegra210-hda", "nvidia,tegra30-hda"; 988742af7e7SThierry Reding reg = <0x0 0x70030000 0x0 0x10000>; 989742af7e7SThierry Reding interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 990742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_HDA>, 991742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_HDA2HDMI>, 992742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_HDA2CODEC_2X>; 993742af7e7SThierry Reding clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 994742af7e7SThierry Reding resets = <&tegra_car 125>, /* hda */ 995742af7e7SThierry Reding <&tegra_car 128>, /* hda2hdmi */ 996742af7e7SThierry Reding <&tegra_car 111>; /* hda2codec_2x */ 997742af7e7SThierry Reding reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 998742af7e7SThierry Reding status = "disabled"; 999742af7e7SThierry Reding }; 1000742af7e7SThierry Reding 1001e7a99ac2SThierry Reding usb@70090000 { 1002e7a99ac2SThierry Reding compatible = "nvidia,tegra210-xusb"; 1003e7a99ac2SThierry Reding reg = <0x0 0x70090000 0x0 0x8000>, 1004e7a99ac2SThierry Reding <0x0 0x70098000 0x0 0x1000>, 1005e7a99ac2SThierry Reding <0x0 0x70099000 0x0 0x1000>; 1006e7a99ac2SThierry Reding reg-names = "hcd", "fpci", "ipfs"; 1007e7a99ac2SThierry Reding 1008e7a99ac2SThierry Reding interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 10099168e1dbSJon Hunter <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 1010e7a99ac2SThierry Reding 1011e7a99ac2SThierry Reding clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>, 1012e7a99ac2SThierry Reding <&tegra_car TEGRA210_CLK_XUSB_HOST_SRC>, 1013e7a99ac2SThierry Reding <&tegra_car TEGRA210_CLK_XUSB_FALCON_SRC>, 1014e7a99ac2SThierry Reding <&tegra_car TEGRA210_CLK_XUSB_SS>, 1015e7a99ac2SThierry Reding <&tegra_car TEGRA210_CLK_XUSB_SS_SRC>, 1016d19532e6SThierry Reding <&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>, 1017e7a99ac2SThierry Reding <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>, 1018e7a99ac2SThierry Reding <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>, 1019e7a99ac2SThierry Reding <&tegra_car TEGRA210_CLK_PLL_U_480M>, 1020e7a99ac2SThierry Reding <&tegra_car TEGRA210_CLK_CLK_M>, 1021e7a99ac2SThierry Reding <&tegra_car TEGRA210_CLK_PLL_E>; 1022e7a99ac2SThierry Reding clock-names = "xusb_host", "xusb_host_src", 1023e7a99ac2SThierry Reding "xusb_falcon_src", "xusb_ss", 1024d19532e6SThierry Reding "xusb_ss_src", "xusb_ss_div2", 1025e7a99ac2SThierry Reding "xusb_hs_src", "xusb_fs_src", 1026e7a99ac2SThierry Reding "pll_u_480m", "clk_m", "pll_e"; 1027e7a99ac2SThierry Reding resets = <&tegra_car 89>, <&tegra_car 156>, 1028e7a99ac2SThierry Reding <&tegra_car 143>; 1029e7a99ac2SThierry Reding reset-names = "xusb_host", "xusb_ss", "xusb_src"; 103036ec29f7SJon Hunter power-domains = <&pd_xusbhost>, <&pd_xusbss>; 103136ec29f7SJon Hunter power-domain-names = "xusb_host", "xusb_ss"; 1032e7a99ac2SThierry Reding 1033e7a99ac2SThierry Reding nvidia,xusb-padctl = <&padctl>; 1034e7a99ac2SThierry Reding 1035e7a99ac2SThierry Reding status = "disabled"; 1036e7a99ac2SThierry Reding }; 1037e7a99ac2SThierry Reding 10384e07ac90SThierry Reding padctl: padctl@7009f000 { 10394e07ac90SThierry Reding compatible = "nvidia,tegra210-xusb-padctl"; 10404e07ac90SThierry Reding reg = <0x0 0x7009f000 0x0 0x1000>; 10414e07ac90SThierry Reding resets = <&tegra_car 142>; 10424e07ac90SThierry Reding reset-names = "padctl"; 10434e07ac90SThierry Reding 10444e07ac90SThierry Reding status = "disabled"; 10454e07ac90SThierry Reding 10464e07ac90SThierry Reding pads { 10474e07ac90SThierry Reding usb2 { 10484e07ac90SThierry Reding clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>; 10494e07ac90SThierry Reding clock-names = "trk"; 10504e07ac90SThierry Reding status = "disabled"; 10514e07ac90SThierry Reding 10524e07ac90SThierry Reding lanes { 10534e07ac90SThierry Reding usb2-0 { 10544e07ac90SThierry Reding status = "disabled"; 10554e07ac90SThierry Reding #phy-cells = <0>; 10564e07ac90SThierry Reding }; 10574e07ac90SThierry Reding 10584e07ac90SThierry Reding usb2-1 { 10594e07ac90SThierry Reding status = "disabled"; 10604e07ac90SThierry Reding #phy-cells = <0>; 10614e07ac90SThierry Reding }; 10624e07ac90SThierry Reding 10634e07ac90SThierry Reding usb2-2 { 10644e07ac90SThierry Reding status = "disabled"; 10654e07ac90SThierry Reding #phy-cells = <0>; 10664e07ac90SThierry Reding }; 10674e07ac90SThierry Reding 10684e07ac90SThierry Reding usb2-3 { 10694e07ac90SThierry Reding status = "disabled"; 10704e07ac90SThierry Reding #phy-cells = <0>; 10714e07ac90SThierry Reding }; 10724e07ac90SThierry Reding }; 10734e07ac90SThierry Reding }; 10744e07ac90SThierry Reding 10754e07ac90SThierry Reding hsic { 10764e07ac90SThierry Reding clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>; 10774e07ac90SThierry Reding clock-names = "trk"; 10784e07ac90SThierry Reding status = "disabled"; 10794e07ac90SThierry Reding 10804e07ac90SThierry Reding lanes { 10814e07ac90SThierry Reding hsic-0 { 10824e07ac90SThierry Reding status = "disabled"; 10834e07ac90SThierry Reding #phy-cells = <0>; 10844e07ac90SThierry Reding }; 10854e07ac90SThierry Reding 10864e07ac90SThierry Reding hsic-1 { 10874e07ac90SThierry Reding status = "disabled"; 10884e07ac90SThierry Reding #phy-cells = <0>; 10894e07ac90SThierry Reding }; 10904e07ac90SThierry Reding }; 10914e07ac90SThierry Reding }; 10924e07ac90SThierry Reding 10934e07ac90SThierry Reding pcie { 10944e07ac90SThierry Reding clocks = <&tegra_car TEGRA210_CLK_PLL_E>; 10954e07ac90SThierry Reding clock-names = "pll"; 10964e07ac90SThierry Reding resets = <&tegra_car 205>; 10974e07ac90SThierry Reding reset-names = "phy"; 10984e07ac90SThierry Reding status = "disabled"; 10994e07ac90SThierry Reding 11004e07ac90SThierry Reding lanes { 11014e07ac90SThierry Reding pcie-0 { 11024e07ac90SThierry Reding status = "disabled"; 11034e07ac90SThierry Reding #phy-cells = <0>; 11044e07ac90SThierry Reding }; 11054e07ac90SThierry Reding 11064e07ac90SThierry Reding pcie-1 { 11074e07ac90SThierry Reding status = "disabled"; 11084e07ac90SThierry Reding #phy-cells = <0>; 11094e07ac90SThierry Reding }; 11104e07ac90SThierry Reding 11114e07ac90SThierry Reding pcie-2 { 11124e07ac90SThierry Reding status = "disabled"; 11134e07ac90SThierry Reding #phy-cells = <0>; 11144e07ac90SThierry Reding }; 11154e07ac90SThierry Reding 11164e07ac90SThierry Reding pcie-3 { 11174e07ac90SThierry Reding status = "disabled"; 11184e07ac90SThierry Reding #phy-cells = <0>; 11194e07ac90SThierry Reding }; 11204e07ac90SThierry Reding 11214e07ac90SThierry Reding pcie-4 { 11224e07ac90SThierry Reding status = "disabled"; 11234e07ac90SThierry Reding #phy-cells = <0>; 11244e07ac90SThierry Reding }; 11254e07ac90SThierry Reding 11264e07ac90SThierry Reding pcie-5 { 11274e07ac90SThierry Reding status = "disabled"; 11284e07ac90SThierry Reding #phy-cells = <0>; 11294e07ac90SThierry Reding }; 11304e07ac90SThierry Reding 11314e07ac90SThierry Reding pcie-6 { 11324e07ac90SThierry Reding status = "disabled"; 11334e07ac90SThierry Reding #phy-cells = <0>; 11344e07ac90SThierry Reding }; 11354e07ac90SThierry Reding }; 11364e07ac90SThierry Reding }; 11374e07ac90SThierry Reding 11384e07ac90SThierry Reding sata { 11394e07ac90SThierry Reding clocks = <&tegra_car TEGRA210_CLK_PLL_E>; 11404e07ac90SThierry Reding clock-names = "pll"; 11414e07ac90SThierry Reding resets = <&tegra_car 204>; 11424e07ac90SThierry Reding reset-names = "phy"; 11434e07ac90SThierry Reding status = "disabled"; 11444e07ac90SThierry Reding 11454e07ac90SThierry Reding lanes { 11464e07ac90SThierry Reding sata-0 { 11474e07ac90SThierry Reding status = "disabled"; 11484e07ac90SThierry Reding #phy-cells = <0>; 11494e07ac90SThierry Reding }; 11504e07ac90SThierry Reding }; 11514e07ac90SThierry Reding }; 11524e07ac90SThierry Reding }; 11534e07ac90SThierry Reding 11544e07ac90SThierry Reding ports { 11554e07ac90SThierry Reding usb2-0 { 11564e07ac90SThierry Reding status = "disabled"; 11574e07ac90SThierry Reding }; 11584e07ac90SThierry Reding 11594e07ac90SThierry Reding usb2-1 { 11604e07ac90SThierry Reding status = "disabled"; 11614e07ac90SThierry Reding }; 11624e07ac90SThierry Reding 11634e07ac90SThierry Reding usb2-2 { 11644e07ac90SThierry Reding status = "disabled"; 11654e07ac90SThierry Reding }; 11664e07ac90SThierry Reding 11674e07ac90SThierry Reding usb2-3 { 11684e07ac90SThierry Reding status = "disabled"; 11694e07ac90SThierry Reding }; 11704e07ac90SThierry Reding 11714e07ac90SThierry Reding hsic-0 { 11724e07ac90SThierry Reding status = "disabled"; 11734e07ac90SThierry Reding }; 11744e07ac90SThierry Reding 11754e07ac90SThierry Reding usb3-0 { 11764e07ac90SThierry Reding status = "disabled"; 11774e07ac90SThierry Reding }; 11784e07ac90SThierry Reding 11794e07ac90SThierry Reding usb3-1 { 11804e07ac90SThierry Reding status = "disabled"; 11814e07ac90SThierry Reding }; 11824e07ac90SThierry Reding 11834e07ac90SThierry Reding usb3-2 { 11844e07ac90SThierry Reding status = "disabled"; 11854e07ac90SThierry Reding }; 11864e07ac90SThierry Reding 11874e07ac90SThierry Reding usb3-3 { 11884e07ac90SThierry Reding status = "disabled"; 11894e07ac90SThierry Reding }; 11904e07ac90SThierry Reding }; 11914e07ac90SThierry Reding }; 11924e07ac90SThierry Reding 119367bb17f6SThierry Reding mmc@700b0000 { 1194b3fa0e03SThierry Reding compatible = "nvidia,tegra210-sdhci"; 1195742af7e7SThierry Reding reg = <0x0 0x700b0000 0x0 0x200>; 1196742af7e7SThierry Reding interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1197742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_SDMMC1>; 1198742af7e7SThierry Reding clock-names = "sdhci"; 1199742af7e7SThierry Reding resets = <&tegra_car 14>; 1200742af7e7SThierry Reding reset-names = "sdhci"; 12014e0f1229SSowjanya Komatineni pinctrl-names = "sdmmc-3v3", "sdmmc-1v8", 12024e0f1229SSowjanya Komatineni "sdmmc-3v3-drv", "sdmmc-1v8-drv"; 12036641af7eSAapo Vienamo pinctrl-0 = <&sdmmc1_3v3>; 12046641af7eSAapo Vienamo pinctrl-1 = <&sdmmc1_1v8>; 12054e0f1229SSowjanya Komatineni pinctrl-2 = <&sdmmc1_3v3_drv>; 12064e0f1229SSowjanya Komatineni pinctrl-3 = <&sdmmc1_1v8_drv>; 12071ea06718SAapo Vienamo nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>; 12081ea06718SAapo Vienamo nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>; 12091ea06718SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>; 12101ea06718SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>; 121163af8bcdSAapo Vienamo nvidia,default-tap = <0x2>; 121263af8bcdSAapo Vienamo nvidia,default-trim = <0x4>; 1213918f9671SAapo Vienamo assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>, 1214918f9671SAapo Vienamo <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>, 1215918f9671SAapo Vienamo <&tegra_car TEGRA210_CLK_PLL_C4>; 1216918f9671SAapo Vienamo assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 1217918f9671SAapo Vienamo assigned-clock-rates = <200000000>, <1000000000>, <1000000000>; 1218742af7e7SThierry Reding status = "disabled"; 1219742af7e7SThierry Reding }; 1220742af7e7SThierry Reding 122167bb17f6SThierry Reding mmc@700b0200 { 1222b3fa0e03SThierry Reding compatible = "nvidia,tegra210-sdhci"; 1223742af7e7SThierry Reding reg = <0x0 0x700b0200 0x0 0x200>; 1224742af7e7SThierry Reding interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 1225742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_SDMMC2>; 1226742af7e7SThierry Reding clock-names = "sdhci"; 1227742af7e7SThierry Reding resets = <&tegra_car 9>; 1228742af7e7SThierry Reding reset-names = "sdhci"; 12294e0f1229SSowjanya Komatineni pinctrl-names = "sdmmc-1v8-drv"; 12304e0f1229SSowjanya Komatineni pinctrl-0 = <&sdmmc2_1v8_drv>; 12311ea06718SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>; 12321ea06718SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>; 123363af8bcdSAapo Vienamo nvidia,default-tap = <0x8>; 123463af8bcdSAapo Vienamo nvidia,default-trim = <0x0>; 1235742af7e7SThierry Reding status = "disabled"; 1236742af7e7SThierry Reding }; 1237742af7e7SThierry Reding 123867bb17f6SThierry Reding mmc@700b0400 { 1239b3fa0e03SThierry Reding compatible = "nvidia,tegra210-sdhci"; 1240742af7e7SThierry Reding reg = <0x0 0x700b0400 0x0 0x200>; 1241742af7e7SThierry Reding interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 1242742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_SDMMC3>; 1243742af7e7SThierry Reding clock-names = "sdhci"; 1244742af7e7SThierry Reding resets = <&tegra_car 69>; 1245742af7e7SThierry Reding reset-names = "sdhci"; 12464e0f1229SSowjanya Komatineni pinctrl-names = "sdmmc-3v3", "sdmmc-1v8", 12474e0f1229SSowjanya Komatineni "sdmmc-3v3-drv", "sdmmc-1v8-drv"; 12486641af7eSAapo Vienamo pinctrl-0 = <&sdmmc3_3v3>; 12496641af7eSAapo Vienamo pinctrl-1 = <&sdmmc3_1v8>; 12504e0f1229SSowjanya Komatineni pinctrl-2 = <&sdmmc3_3v3_drv>; 12514e0f1229SSowjanya Komatineni pinctrl-3 = <&sdmmc3_1v8_drv>; 12521ea06718SAapo Vienamo nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>; 12531ea06718SAapo Vienamo nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>; 12541ea06718SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>; 12551ea06718SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>; 125663af8bcdSAapo Vienamo nvidia,default-tap = <0x3>; 125763af8bcdSAapo Vienamo nvidia,default-trim = <0x3>; 1258742af7e7SThierry Reding status = "disabled"; 1259742af7e7SThierry Reding }; 1260742af7e7SThierry Reding 126167bb17f6SThierry Reding mmc@700b0600 { 1262b3fa0e03SThierry Reding compatible = "nvidia,tegra210-sdhci"; 1263742af7e7SThierry Reding reg = <0x0 0x700b0600 0x0 0x200>; 1264742af7e7SThierry Reding interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1265742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_SDMMC4>; 1266742af7e7SThierry Reding clock-names = "sdhci"; 1267742af7e7SThierry Reding resets = <&tegra_car 15>; 1268742af7e7SThierry Reding reset-names = "sdhci"; 12694e0f1229SSowjanya Komatineni pinctrl-names = "sdmmc-3v3-drv", "sdmmc-1v8-drv"; 12704e0f1229SSowjanya Komatineni pinctrl-0 = <&sdmmc4_1v8_drv>; 12714e0f1229SSowjanya Komatineni pinctrl-1 = <&sdmmc4_1v8_drv>; 12721ea06718SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>; 12731ea06718SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>; 127463af8bcdSAapo Vienamo nvidia,default-tap = <0x8>; 127563af8bcdSAapo Vienamo nvidia,default-trim = <0x0>; 1276918f9671SAapo Vienamo assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>, 1277918f9671SAapo Vienamo <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 1278918f9671SAapo Vienamo assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 12795879600aSAapo Vienamo nvidia,dqs-trim = <40>; 1280d5d6b468SAapo Vienamo mmc-hs400-1_8v; 1281742af7e7SThierry Reding status = "disabled"; 1282742af7e7SThierry Reding }; 1283742af7e7SThierry Reding 1284e74db5a5SNagarjuna Kristam usb@700d0000 { 1285e74db5a5SNagarjuna Kristam compatible = "nvidia,tegra210-xudc"; 1286e74db5a5SNagarjuna Kristam reg = <0x0 0x700d0000 0x0 0x8000>, 1287e74db5a5SNagarjuna Kristam <0x0 0x700d8000 0x0 0x1000>, 1288e74db5a5SNagarjuna Kristam <0x0 0x700d9000 0x0 0x1000>; 1289e74db5a5SNagarjuna Kristam reg-names = "base", "fpci", "ipfs"; 1290e74db5a5SNagarjuna Kristam interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1291e74db5a5SNagarjuna Kristam clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>, 1292e74db5a5SNagarjuna Kristam <&tegra_car TEGRA210_CLK_XUSB_SS>, 1293e74db5a5SNagarjuna Kristam <&tegra_car TEGRA210_CLK_XUSB_SSP_SRC>, 1294e74db5a5SNagarjuna Kristam <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>, 1295e74db5a5SNagarjuna Kristam <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>; 1296e74db5a5SNagarjuna Kristam clock-names = "dev", "ss", "ss_src", "fs_src", "hs_src"; 1297e74db5a5SNagarjuna Kristam power-domains = <&pd_xusbdev>, <&pd_xusbss>; 1298e74db5a5SNagarjuna Kristam power-domain-names = "dev", "ss"; 1299e74db5a5SNagarjuna Kristam nvidia,xusb-padctl = <&padctl>; 1300e74db5a5SNagarjuna Kristam status = "disabled"; 1301e74db5a5SNagarjuna Kristam }; 1302e74db5a5SNagarjuna Kristam 1303be70771dSThierry Reding mipi: mipi@700e3000 { 1304742af7e7SThierry Reding compatible = "nvidia,tegra210-mipi"; 1305742af7e7SThierry Reding reg = <0x0 0x700e3000 0x0 0x100>; 1306742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_MIPI_CAL>; 1307742af7e7SThierry Reding clock-names = "mipi-cal"; 130896d1f078SJon Hunter power-domains = <&pd_sor>; 1309742af7e7SThierry Reding #nvidia,mipi-calibrate-cells = <1>; 1310742af7e7SThierry Reding }; 1311742af7e7SThierry Reding 13122ceed593SJoseph Lo dfll: clock@70110000 { 13132ceed593SJoseph Lo compatible = "nvidia,tegra210-dfll"; 13142ceed593SJoseph Lo reg = <0 0x70110000 0 0x100>, /* DFLL control */ 13152ceed593SJoseph Lo <0 0x70110000 0 0x100>, /* I2C output control */ 13162ceed593SJoseph Lo <0 0x70110100 0 0x100>, /* Integrated I2C controller */ 13172ceed593SJoseph Lo <0 0x70110200 0 0x100>; /* Look-up table RAM */ 13182ceed593SJoseph Lo interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 13192ceed593SJoseph Lo clocks = <&tegra_car TEGRA210_CLK_DFLL_SOC>, 13202ceed593SJoseph Lo <&tegra_car TEGRA210_CLK_DFLL_REF>, 13212ceed593SJoseph Lo <&tegra_car TEGRA210_CLK_I2C5>; 13222ceed593SJoseph Lo clock-names = "soc", "ref", "i2c"; 13232ceed593SJoseph Lo resets = <&tegra_car TEGRA210_RST_DFLL_DVCO>; 13242ceed593SJoseph Lo reset-names = "dvco"; 13252ceed593SJoseph Lo #clock-cells = <0>; 13262ceed593SJoseph Lo clock-output-names = "dfllCPU_out"; 13272ceed593SJoseph Lo status = "disabled"; 13282ceed593SJoseph Lo }; 13292ceed593SJoseph Lo 13300f133090SJon Hunter aconnect@702c0000 { 13310f133090SJon Hunter compatible = "nvidia,tegra210-aconnect"; 13320f133090SJon Hunter clocks = <&tegra_car TEGRA210_CLK_APE>, 13330f133090SJon Hunter <&tegra_car TEGRA210_CLK_APB2APE>; 13340f133090SJon Hunter clock-names = "ape", "apb2ape"; 13350f133090SJon Hunter power-domains = <&pd_audio>; 13360f133090SJon Hunter #address-cells = <1>; 13370f133090SJon Hunter #size-cells = <1>; 13380f133090SJon Hunter ranges = <0x702c0000 0x0 0x702c0000 0x00040000>; 13390f133090SJon Hunter status = "disabled"; 1340bcdbde43SJon Hunter 134119e61213SJon Hunter adma: dma@702e2000 { 134219e61213SJon Hunter compatible = "nvidia,tegra210-adma"; 134319e61213SJon Hunter reg = <0x702e2000 0x2000>; 134419e61213SJon Hunter interrupt-parent = <&agic>; 134519e61213SJon Hunter interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 134619e61213SJon Hunter <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 134719e61213SJon Hunter <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 134819e61213SJon Hunter <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 134919e61213SJon Hunter <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 135019e61213SJon Hunter <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 135119e61213SJon Hunter <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 135219e61213SJon Hunter <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 135319e61213SJon Hunter <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 135419e61213SJon Hunter <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 135519e61213SJon Hunter <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 135619e61213SJon Hunter <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 135719e61213SJon Hunter <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 135819e61213SJon Hunter <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 135919e61213SJon Hunter <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 136019e61213SJon Hunter <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 136119e61213SJon Hunter <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 136219e61213SJon Hunter <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 136319e61213SJon Hunter <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 136419e61213SJon Hunter <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 136519e61213SJon Hunter <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 136619e61213SJon Hunter <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 136719e61213SJon Hunter #dma-cells = <1>; 136819e61213SJon Hunter clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>; 136919e61213SJon Hunter clock-names = "d_audio"; 137019e61213SJon Hunter status = "disabled"; 137119e61213SJon Hunter }; 137219e61213SJon Hunter 1373df93557bSThierry Reding agic: interrupt-controller@702f9000 { 1374bcdbde43SJon Hunter compatible = "nvidia,tegra210-agic"; 1375bcdbde43SJon Hunter #interrupt-cells = <3>; 1376bcdbde43SJon Hunter interrupt-controller; 1377ba24eee6SJon Hunter reg = <0x702f9000 0x1000>, 1378bcdbde43SJon Hunter <0x702fa000 0x2000>; 1379bcdbde43SJon Hunter interrupts = <GIC_SPI 102 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1380bcdbde43SJon Hunter clocks = <&tegra_car TEGRA210_CLK_APE>; 1381bcdbde43SJon Hunter clock-names = "clk"; 1382bcdbde43SJon Hunter status = "disabled"; 1383bcdbde43SJon Hunter }; 13840f133090SJon Hunter }; 13850f133090SJon Hunter 1386be70771dSThierry Reding spi@70410000 { 1387742af7e7SThierry Reding compatible = "nvidia,tegra210-qspi"; 1388742af7e7SThierry Reding reg = <0x0 0x70410000 0x0 0x1000>; 1389742af7e7SThierry Reding interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1390742af7e7SThierry Reding #address-cells = <1>; 1391742af7e7SThierry Reding #size-cells = <0>; 1392742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_QSPI>; 1393742af7e7SThierry Reding clock-names = "qspi"; 1394742af7e7SThierry Reding resets = <&tegra_car 211>; 1395742af7e7SThierry Reding reset-names = "qspi"; 1396742af7e7SThierry Reding dmas = <&apbdma 5>, <&apbdma 5>; 1397742af7e7SThierry Reding dma-names = "rx", "tx"; 1398742af7e7SThierry Reding status = "disabled"; 1399742af7e7SThierry Reding }; 1400742af7e7SThierry Reding 1401be70771dSThierry Reding usb@7d000000 { 1402742af7e7SThierry Reding compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 1403742af7e7SThierry Reding reg = <0x0 0x7d000000 0x0 0x4000>; 1404742af7e7SThierry Reding interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1405742af7e7SThierry Reding phy_type = "utmi"; 1406742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_USBD>; 1407742af7e7SThierry Reding clock-names = "usb"; 1408742af7e7SThierry Reding resets = <&tegra_car 22>; 1409742af7e7SThierry Reding reset-names = "usb"; 1410742af7e7SThierry Reding nvidia,phy = <&phy1>; 1411742af7e7SThierry Reding status = "disabled"; 1412742af7e7SThierry Reding }; 1413742af7e7SThierry Reding 1414be70771dSThierry Reding phy1: usb-phy@7d000000 { 1415742af7e7SThierry Reding compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; 1416742af7e7SThierry Reding reg = <0x0 0x7d000000 0x0 0x4000>, 1417742af7e7SThierry Reding <0x0 0x7d000000 0x0 0x4000>; 1418742af7e7SThierry Reding phy_type = "utmi"; 1419742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_USBD>, 1420742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_PLL_U>, 1421742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_USBD>; 1422742af7e7SThierry Reding clock-names = "reg", "pll_u", "utmi-pads"; 1423742af7e7SThierry Reding resets = <&tegra_car 22>, <&tegra_car 22>; 1424742af7e7SThierry Reding reset-names = "usb", "utmi-pads"; 1425742af7e7SThierry Reding nvidia,hssync-start-delay = <0>; 1426742af7e7SThierry Reding nvidia,idle-wait-delay = <17>; 1427742af7e7SThierry Reding nvidia,elastic-limit = <16>; 1428742af7e7SThierry Reding nvidia,term-range-adj = <6>; 1429742af7e7SThierry Reding nvidia,xcvr-setup = <9>; 1430742af7e7SThierry Reding nvidia,xcvr-lsfslew = <0>; 1431742af7e7SThierry Reding nvidia,xcvr-lsrslew = <3>; 1432742af7e7SThierry Reding nvidia,hssquelch-level = <2>; 1433742af7e7SThierry Reding nvidia,hsdiscon-level = <5>; 1434742af7e7SThierry Reding nvidia,xcvr-hsslew = <12>; 1435742af7e7SThierry Reding nvidia,has-utmi-pad-registers; 1436742af7e7SThierry Reding status = "disabled"; 1437742af7e7SThierry Reding }; 1438742af7e7SThierry Reding 1439be70771dSThierry Reding usb@7d004000 { 1440742af7e7SThierry Reding compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 1441742af7e7SThierry Reding reg = <0x0 0x7d004000 0x0 0x4000>; 1442742af7e7SThierry Reding interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1443742af7e7SThierry Reding phy_type = "utmi"; 1444742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_USB2>; 1445742af7e7SThierry Reding clock-names = "usb"; 1446742af7e7SThierry Reding resets = <&tegra_car 58>; 1447742af7e7SThierry Reding reset-names = "usb"; 1448742af7e7SThierry Reding nvidia,phy = <&phy2>; 1449742af7e7SThierry Reding status = "disabled"; 1450742af7e7SThierry Reding }; 1451742af7e7SThierry Reding 1452be70771dSThierry Reding phy2: usb-phy@7d004000 { 1453742af7e7SThierry Reding compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; 1454742af7e7SThierry Reding reg = <0x0 0x7d004000 0x0 0x4000>, 1455742af7e7SThierry Reding <0x0 0x7d000000 0x0 0x4000>; 1456742af7e7SThierry Reding phy_type = "utmi"; 1457742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_USB2>, 1458742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_PLL_U>, 1459742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_USBD>; 1460742af7e7SThierry Reding clock-names = "reg", "pll_u", "utmi-pads"; 1461742af7e7SThierry Reding resets = <&tegra_car 58>, <&tegra_car 22>; 1462742af7e7SThierry Reding reset-names = "usb", "utmi-pads"; 1463742af7e7SThierry Reding nvidia,hssync-start-delay = <0>; 1464742af7e7SThierry Reding nvidia,idle-wait-delay = <17>; 1465742af7e7SThierry Reding nvidia,elastic-limit = <16>; 1466742af7e7SThierry Reding nvidia,term-range-adj = <6>; 1467742af7e7SThierry Reding nvidia,xcvr-setup = <9>; 1468742af7e7SThierry Reding nvidia,xcvr-lsfslew = <0>; 1469742af7e7SThierry Reding nvidia,xcvr-lsrslew = <3>; 1470742af7e7SThierry Reding nvidia,hssquelch-level = <2>; 1471742af7e7SThierry Reding nvidia,hsdiscon-level = <5>; 1472742af7e7SThierry Reding nvidia,xcvr-hsslew = <12>; 1473742af7e7SThierry Reding status = "disabled"; 1474742af7e7SThierry Reding }; 1475742af7e7SThierry Reding 1476742af7e7SThierry Reding cpus { 1477742af7e7SThierry Reding #address-cells = <1>; 1478742af7e7SThierry Reding #size-cells = <0>; 1479742af7e7SThierry Reding 1480742af7e7SThierry Reding cpu@0 { 1481742af7e7SThierry Reding device_type = "cpu"; 1482742af7e7SThierry Reding compatible = "arm,cortex-a57"; 1483742af7e7SThierry Reding reg = <0>; 148443b9b402SJoseph Lo clocks = <&tegra_car TEGRA210_CLK_CCLK_G>, 148543b9b402SJoseph Lo <&tegra_car TEGRA210_CLK_PLL_X>, 148643b9b402SJoseph Lo <&tegra_car TEGRA210_CLK_PLL_P_OUT4>, 148743b9b402SJoseph Lo <&dfll>; 148843b9b402SJoseph Lo clock-names = "cpu_g", "pll_x", "pll_p", "dfll"; 148943b9b402SJoseph Lo clock-latency = <300000>; 1490da77c6d9SJoseph Lo cpu-idle-states = <&CPU_SLEEP>; 14916c00cac1SJoseph Lo next-level-cache = <&L2>; 1492742af7e7SThierry Reding }; 1493742af7e7SThierry Reding 1494742af7e7SThierry Reding cpu@1 { 1495742af7e7SThierry Reding device_type = "cpu"; 1496742af7e7SThierry Reding compatible = "arm,cortex-a57"; 1497742af7e7SThierry Reding reg = <1>; 1498da77c6d9SJoseph Lo cpu-idle-states = <&CPU_SLEEP>; 14996c00cac1SJoseph Lo next-level-cache = <&L2>; 1500742af7e7SThierry Reding }; 1501742af7e7SThierry Reding 1502742af7e7SThierry Reding cpu@2 { 1503742af7e7SThierry Reding device_type = "cpu"; 1504742af7e7SThierry Reding compatible = "arm,cortex-a57"; 1505742af7e7SThierry Reding reg = <2>; 1506da77c6d9SJoseph Lo cpu-idle-states = <&CPU_SLEEP>; 15076c00cac1SJoseph Lo next-level-cache = <&L2>; 1508742af7e7SThierry Reding }; 1509742af7e7SThierry Reding 1510742af7e7SThierry Reding cpu@3 { 1511742af7e7SThierry Reding device_type = "cpu"; 1512742af7e7SThierry Reding compatible = "arm,cortex-a57"; 1513742af7e7SThierry Reding reg = <3>; 1514da77c6d9SJoseph Lo cpu-idle-states = <&CPU_SLEEP>; 15156c00cac1SJoseph Lo next-level-cache = <&L2>; 1516da77c6d9SJoseph Lo }; 1517da77c6d9SJoseph Lo 1518da77c6d9SJoseph Lo idle-states { 1519da77c6d9SJoseph Lo entry-method = "psci"; 1520da77c6d9SJoseph Lo 1521da77c6d9SJoseph Lo CPU_SLEEP: cpu-sleep { 1522da77c6d9SJoseph Lo compatible = "arm,idle-state"; 1523da77c6d9SJoseph Lo arm,psci-suspend-param = <0x40000007>; 1524da77c6d9SJoseph Lo entry-latency-us = <100>; 1525da77c6d9SJoseph Lo exit-latency-us = <30>; 1526da77c6d9SJoseph Lo min-residency-us = <1000>; 1527da77c6d9SJoseph Lo wakeup-latency-us = <130>; 1528da77c6d9SJoseph Lo idle-state-name = "cpu-sleep"; 1529da77c6d9SJoseph Lo status = "disabled"; 1530da77c6d9SJoseph Lo }; 1531742af7e7SThierry Reding }; 15326c00cac1SJoseph Lo 15336c00cac1SJoseph Lo L2: l2-cache { 15346c00cac1SJoseph Lo compatible = "cache"; 15356c00cac1SJoseph Lo }; 1536742af7e7SThierry Reding }; 1537742af7e7SThierry Reding 1538264064abSThierry Reding pmu { 1539264064abSThierry Reding compatible = "arm,armv8-pmuv3"; 1540264064abSThierry Reding interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1541264064abSThierry Reding <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1542264064abSThierry Reding <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1543264064abSThierry Reding <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 1544264064abSThierry Reding interrupt-affinity = <&{/cpus/cpu@0} &{/cpus/cpu@1} 1545264064abSThierry Reding &{/cpus/cpu@2} &{/cpus/cpu@3}>; 1546264064abSThierry Reding }; 1547264064abSThierry Reding 1548742af7e7SThierry Reding timer { 1549742af7e7SThierry Reding compatible = "arm,armv8-timer"; 1550742af7e7SThierry Reding interrupts = <GIC_PPI 13 1551742af7e7SThierry Reding (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1552742af7e7SThierry Reding <GIC_PPI 14 1553742af7e7SThierry Reding (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1554742af7e7SThierry Reding <GIC_PPI 11 1555742af7e7SThierry Reding (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1556742af7e7SThierry Reding <GIC_PPI 10 1557742af7e7SThierry Reding (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1558742af7e7SThierry Reding interrupt-parent = <&gic>; 15596b9e263bSThierry Reding arm,no-tick-in-suspend; 1560742af7e7SThierry Reding }; 1561e2bed1ebSWei Ni 1562e2bed1ebSWei Ni soctherm: thermal-sensor@700e2000 { 1563e2bed1ebSWei Ni compatible = "nvidia,tegra210-soctherm"; 1564644c569dSThierry Reding reg = <0x0 0x700e2000 0x0 0x600>, /* SOC_THERM reg_base */ 1565644c569dSThierry Reding <0x0 0x60006000 0x0 0x400>; /* CAR reg_base */ 1566cbd0f000SWei Ni reg-names = "soctherm-reg", "car-reg"; 156744ff822cSThierry Reding interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 156844ff822cSThierry Reding <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 156944ff822cSThierry Reding interrupt-names = "thermal", "edp"; 1570e2bed1ebSWei Ni clocks = <&tegra_car TEGRA210_CLK_TSENSOR>, 1571e2bed1ebSWei Ni <&tegra_car TEGRA210_CLK_SOC_THERM>; 1572e2bed1ebSWei Ni clock-names = "tsensor", "soctherm"; 1573e2bed1ebSWei Ni resets = <&tegra_car 78>; 1574e2bed1ebSWei Ni reset-names = "soctherm"; 1575e2bed1ebSWei Ni #thermal-sensor-cells = <1>; 1576cbd0f000SWei Ni 1577cbd0f000SWei Ni throttle-cfgs { 1578cbd0f000SWei Ni throttle_heavy: heavy { 1579cbd0f000SWei Ni nvidia,priority = <100>; 1580cbd0f000SWei Ni nvidia,cpu-throt-percent = <85>; 1581cbd0f000SWei Ni 1582cbd0f000SWei Ni #cooling-cells = <2>; 1583cbd0f000SWei Ni }; 1584cbd0f000SWei Ni }; 1585e2bed1ebSWei Ni }; 1586e2bed1ebSWei Ni 1587e2bed1ebSWei Ni thermal-zones { 1588e2bed1ebSWei Ni cpu { 1589e2bed1ebSWei Ni polling-delay-passive = <1000>; 1590e2bed1ebSWei Ni polling-delay = <0>; 1591e2bed1ebSWei Ni 1592e2bed1ebSWei Ni thermal-sensors = 1593e2bed1ebSWei Ni <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; 15945e03f663SWei Ni 15955e03f663SWei Ni trips { 15965e03f663SWei Ni cpu-shutdown-trip { 15975e03f663SWei Ni temperature = <102500>; 15985e03f663SWei Ni hysteresis = <0>; 15995e03f663SWei Ni type = "critical"; 16005e03f663SWei Ni }; 1601cbd0f000SWei Ni 1602cbd0f000SWei Ni cpu_throttle_trip: throttle-trip { 1603cbd0f000SWei Ni temperature = <98500>; 1604cbd0f000SWei Ni hysteresis = <1000>; 1605cbd0f000SWei Ni type = "hot"; 1606cbd0f000SWei Ni }; 16075e03f663SWei Ni }; 16085e03f663SWei Ni 16095e03f663SWei Ni cooling-maps { 1610cbd0f000SWei Ni map0 { 1611cbd0f000SWei Ni trip = <&cpu_throttle_trip>; 1612cbd0f000SWei Ni cooling-device = <&throttle_heavy 1 1>; 1613cbd0f000SWei Ni }; 16145e03f663SWei Ni }; 1615e2bed1ebSWei Ni }; 161624fc3363SThierry Reding 1617e2bed1ebSWei Ni mem { 1618e2bed1ebSWei Ni polling-delay-passive = <0>; 1619e2bed1ebSWei Ni polling-delay = <0>; 1620e2bed1ebSWei Ni 1621e2bed1ebSWei Ni thermal-sensors = 1622e2bed1ebSWei Ni <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>; 16235e03f663SWei Ni 16245e03f663SWei Ni trips { 1625e12325f6SThierry Reding dram_nominal: mem-nominal-trip { 1626e12325f6SThierry Reding temperature = <50000>; 1627e12325f6SThierry Reding hysteresis = <1000>; 1628e12325f6SThierry Reding type = "passive"; 1629e12325f6SThierry Reding }; 1630e12325f6SThierry Reding 1631e12325f6SThierry Reding dram_throttle: mem-throttle-trip { 1632e12325f6SThierry Reding temperature = <70000>; 1633e12325f6SThierry Reding hysteresis = <1000>; 1634e12325f6SThierry Reding type = "active"; 1635e12325f6SThierry Reding }; 1636e12325f6SThierry Reding 16375e03f663SWei Ni mem-shutdown-trip { 16385e03f663SWei Ni temperature = <103000>; 16395e03f663SWei Ni hysteresis = <0>; 16405e03f663SWei Ni type = "critical"; 16415e03f663SWei Ni }; 16425e03f663SWei Ni }; 16435e03f663SWei Ni 16445e03f663SWei Ni cooling-maps { 1645e12325f6SThierry Reding dram-passive { 1646e12325f6SThierry Reding cooling-device = <&emc 0 0>; 1647e12325f6SThierry Reding trip = <&dram_nominal>; 1648e12325f6SThierry Reding }; 1649e12325f6SThierry Reding 1650e12325f6SThierry Reding dram-active { 1651e12325f6SThierry Reding cooling-device = <&emc 1 1>; 1652e12325f6SThierry Reding trip = <&dram_throttle>; 1653e12325f6SThierry Reding }; 16545e03f663SWei Ni }; 1655e2bed1ebSWei Ni }; 165624fc3363SThierry Reding 1657e2bed1ebSWei Ni gpu { 1658e2bed1ebSWei Ni polling-delay-passive = <1000>; 1659e2bed1ebSWei Ni polling-delay = <0>; 1660e2bed1ebSWei Ni 1661e2bed1ebSWei Ni thermal-sensors = 1662e2bed1ebSWei Ni <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>; 16635e03f663SWei Ni 16645e03f663SWei Ni trips { 16655e03f663SWei Ni gpu-shutdown-trip { 16665e03f663SWei Ni temperature = <103000>; 16675e03f663SWei Ni hysteresis = <0>; 16685e03f663SWei Ni type = "critical"; 16695e03f663SWei Ni }; 1670cbd0f000SWei Ni 1671cbd0f000SWei Ni gpu_throttle_trip: throttle-trip { 1672cbd0f000SWei Ni temperature = <100000>; 1673cbd0f000SWei Ni hysteresis = <1000>; 1674cbd0f000SWei Ni type = "hot"; 1675cbd0f000SWei Ni }; 16765e03f663SWei Ni }; 16775e03f663SWei Ni 16785e03f663SWei Ni cooling-maps { 1679cbd0f000SWei Ni map0 { 1680cbd0f000SWei Ni trip = <&gpu_throttle_trip>; 1681cbd0f000SWei Ni cooling-device = <&throttle_heavy 1 1>; 1682cbd0f000SWei Ni }; 16835e03f663SWei Ni }; 1684e2bed1ebSWei Ni }; 168524fc3363SThierry Reding 1686e2bed1ebSWei Ni pllx { 1687e2bed1ebSWei Ni polling-delay-passive = <0>; 1688e2bed1ebSWei Ni polling-delay = <0>; 1689e2bed1ebSWei Ni 1690e2bed1ebSWei Ni thermal-sensors = 1691e2bed1ebSWei Ni <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>; 16925e03f663SWei Ni 16935e03f663SWei Ni trips { 16945e03f663SWei Ni pllx-shutdown-trip { 16955e03f663SWei Ni temperature = <103000>; 16965e03f663SWei Ni hysteresis = <0>; 16975e03f663SWei Ni type = "critical"; 16985e03f663SWei Ni }; 16995e03f663SWei Ni }; 17005e03f663SWei Ni 17015e03f663SWei Ni cooling-maps { 17025e03f663SWei Ni /* 17035e03f663SWei Ni * There are currently no cooling maps, 17045e03f663SWei Ni * because there are no cooling devices. 17055e03f663SWei Ni */ 17065e03f663SWei Ni }; 1707e2bed1ebSWei Ni }; 1708e2bed1ebSWei Ni }; 1709742af7e7SThierry Reding}; 1710