1b2441318SGreg Kroah-Hartman// SPDX-License-Identifier: GPL-2.0 2742af7e7SThierry Reding#include <dt-bindings/clock/tegra210-car.h> 3742af7e7SThierry Reding#include <dt-bindings/gpio/tegra-gpio.h> 4742af7e7SThierry Reding#include <dt-bindings/memory/tegra210-mc.h> 5742af7e7SThierry Reding#include <dt-bindings/pinctrl/pinctrl-tegra.h> 66641af7eSAapo Vienamo#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 72ceed593SJoseph Lo#include <dt-bindings/reset/tegra210-car.h> 8742af7e7SThierry Reding#include <dt-bindings/interrupt-controller/arm-gic.h> 9e2bed1ebSWei Ni#include <dt-bindings/thermal/tegra124-soctherm.h> 10359ae651SSowjanya Komatineni#include <dt-bindings/soc/tegra-pmc.h> 11742af7e7SThierry Reding 12742af7e7SThierry Reding/ { 13742af7e7SThierry Reding compatible = "nvidia,tegra210"; 14742af7e7SThierry Reding interrupt-parent = <&lic>; 15742af7e7SThierry Reding #address-cells = <2>; 16742af7e7SThierry Reding #size-cells = <2>; 17742af7e7SThierry Reding 18475d99fcSRob Herring pcie@1003000 { 19589a2d3fSThierry Reding compatible = "nvidia,tegra210-pcie"; 20589a2d3fSThierry Reding device_type = "pci"; 21644c569dSThierry Reding reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */ 22644c569dSThierry Reding <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */ 23644c569dSThierry Reding <0x0 0x02000000 0x0 0x10000000>; /* configuration space */ 24589a2d3fSThierry Reding reg-names = "pads", "afi", "cs"; 25589a2d3fSThierry Reding interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 26589a2d3fSThierry Reding <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 27589a2d3fSThierry Reding interrupt-names = "intr", "msi"; 28589a2d3fSThierry Reding 29589a2d3fSThierry Reding #interrupt-cells = <1>; 30589a2d3fSThierry Reding interrupt-map-mask = <0 0 0 0>; 31589a2d3fSThierry Reding interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 32589a2d3fSThierry Reding 33589a2d3fSThierry Reding bus-range = <0x00 0xff>; 34589a2d3fSThierry Reding #address-cells = <3>; 35589a2d3fSThierry Reding #size-cells = <2>; 36589a2d3fSThierry Reding 37644c569dSThierry Reding ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */ 38644c569dSThierry Reding <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */ 39644c569dSThierry Reding <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */ 40644c569dSThierry Reding <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */ 41644c569dSThierry Reding <0x42000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ 42589a2d3fSThierry Reding 43589a2d3fSThierry Reding clocks = <&tegra_car TEGRA210_CLK_PCIE>, 44589a2d3fSThierry Reding <&tegra_car TEGRA210_CLK_AFI>, 45589a2d3fSThierry Reding <&tegra_car TEGRA210_CLK_PLL_E>, 46589a2d3fSThierry Reding <&tegra_car TEGRA210_CLK_CML0>; 47589a2d3fSThierry Reding clock-names = "pex", "afi", "pll_e", "cml"; 48589a2d3fSThierry Reding resets = <&tegra_car 70>, 49589a2d3fSThierry Reding <&tegra_car 72>, 50589a2d3fSThierry Reding <&tegra_car 74>; 51589a2d3fSThierry Reding reset-names = "pex", "afi", "pcie_x"; 52871be845SManikanta Maddireddy 53871be845SManikanta Maddireddy pinctrl-names = "default", "idle"; 54871be845SManikanta Maddireddy pinctrl-0 = <&pex_dpd_disable>; 55871be845SManikanta Maddireddy pinctrl-1 = <&pex_dpd_enable>; 56871be845SManikanta Maddireddy 57589a2d3fSThierry Reding status = "disabled"; 58589a2d3fSThierry Reding 59589a2d3fSThierry Reding pci@1,0 { 60589a2d3fSThierry Reding device_type = "pci"; 61589a2d3fSThierry Reding assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>; 62589a2d3fSThierry Reding reg = <0x000800 0 0 0 0>; 63475d99fcSRob Herring bus-range = <0x00 0xff>; 64589a2d3fSThierry Reding status = "disabled"; 65589a2d3fSThierry Reding 66589a2d3fSThierry Reding #address-cells = <3>; 67589a2d3fSThierry Reding #size-cells = <2>; 68589a2d3fSThierry Reding ranges; 69589a2d3fSThierry Reding 70589a2d3fSThierry Reding nvidia,num-lanes = <4>; 71589a2d3fSThierry Reding }; 72589a2d3fSThierry Reding 73589a2d3fSThierry Reding pci@2,0 { 74589a2d3fSThierry Reding device_type = "pci"; 75589a2d3fSThierry Reding assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>; 76589a2d3fSThierry Reding reg = <0x001000 0 0 0 0>; 77475d99fcSRob Herring bus-range = <0x00 0xff>; 78589a2d3fSThierry Reding status = "disabled"; 79589a2d3fSThierry Reding 80589a2d3fSThierry Reding #address-cells = <3>; 81589a2d3fSThierry Reding #size-cells = <2>; 82589a2d3fSThierry Reding ranges; 83589a2d3fSThierry Reding 84589a2d3fSThierry Reding nvidia,num-lanes = <1>; 85589a2d3fSThierry Reding }; 86589a2d3fSThierry Reding }; 87589a2d3fSThierry Reding 88be70771dSThierry Reding host1x@50000000 { 89ef126bc4SThierry Reding compatible = "nvidia,tegra210-host1x"; 90742af7e7SThierry Reding reg = <0x0 0x50000000 0x0 0x00034000>; 91742af7e7SThierry Reding interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 92742af7e7SThierry Reding <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ 93052d3f65SThierry Reding interrupt-names = "syncpt", "host1x"; 94742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_HOST1X>; 95742af7e7SThierry Reding clock-names = "host1x"; 96742af7e7SThierry Reding resets = <&tegra_car 28>; 97742af7e7SThierry Reding reset-names = "host1x"; 98742af7e7SThierry Reding 99742af7e7SThierry Reding #address-cells = <2>; 100742af7e7SThierry Reding #size-cells = <2>; 101742af7e7SThierry Reding 102742af7e7SThierry Reding ranges = <0x0 0x54000000 0x0 0x54000000 0x0 0x01000000>; 103742af7e7SThierry Reding 104116503a6SMikko Perttunen iommus = <&mc TEGRA_SWGROUP_HC>; 105116503a6SMikko Perttunen 106be70771dSThierry Reding dpaux1: dpaux@54040000 { 107742af7e7SThierry Reding compatible = "nvidia,tegra210-dpaux"; 108742af7e7SThierry Reding reg = <0x0 0x54040000 0x0 0x00040000>; 109742af7e7SThierry Reding interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 110742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_DPAUX1>, 111742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_PLL_DP>; 112742af7e7SThierry Reding clock-names = "dpaux", "parent"; 113742af7e7SThierry Reding resets = <&tegra_car 207>; 114742af7e7SThierry Reding reset-names = "dpaux"; 11596d1f078SJon Hunter power-domains = <&pd_sor>; 116742af7e7SThierry Reding status = "disabled"; 11766b2d6e9SJon Hunter 11866b2d6e9SJon Hunter state_dpaux1_aux: pinmux-aux { 11966b2d6e9SJon Hunter groups = "dpaux-io"; 12066b2d6e9SJon Hunter function = "aux"; 12166b2d6e9SJon Hunter }; 12266b2d6e9SJon Hunter 12366b2d6e9SJon Hunter state_dpaux1_i2c: pinmux-i2c { 12466b2d6e9SJon Hunter groups = "dpaux-io"; 12566b2d6e9SJon Hunter function = "i2c"; 12666b2d6e9SJon Hunter }; 12766b2d6e9SJon Hunter 12866b2d6e9SJon Hunter state_dpaux1_off: pinmux-off { 12966b2d6e9SJon Hunter groups = "dpaux-io"; 13066b2d6e9SJon Hunter function = "off"; 13166b2d6e9SJon Hunter }; 13266b2d6e9SJon Hunter 13366b2d6e9SJon Hunter i2c-bus { 13466b2d6e9SJon Hunter #address-cells = <1>; 13566b2d6e9SJon Hunter #size-cells = <0>; 13666b2d6e9SJon Hunter }; 137742af7e7SThierry Reding }; 138742af7e7SThierry Reding 139be70771dSThierry Reding vi@54080000 { 140742af7e7SThierry Reding compatible = "nvidia,tegra210-vi"; 141c4153885SSowjanya Komatineni reg = <0x0 0x54080000 0x0 0x700>; 142742af7e7SThierry Reding interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 143742af7e7SThierry Reding status = "disabled"; 144c4153885SSowjanya Komatineni assigned-clocks = <&tegra_car TEGRA210_CLK_VI>; 145c4153885SSowjanya Komatineni assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 146c4153885SSowjanya Komatineni 147c4153885SSowjanya Komatineni clocks = <&tegra_car TEGRA210_CLK_VI>; 148c4153885SSowjanya Komatineni power-domains = <&pd_venc>; 149c4153885SSowjanya Komatineni 150c4153885SSowjanya Komatineni #address-cells = <1>; 151c4153885SSowjanya Komatineni #size-cells = <1>; 152c4153885SSowjanya Komatineni 153c4153885SSowjanya Komatineni ranges = <0x0 0x0 0x54080000 0x2000>; 154c4153885SSowjanya Komatineni 155c4153885SSowjanya Komatineni csi@838 { 156c4153885SSowjanya Komatineni compatible = "nvidia,tegra210-csi"; 157c4153885SSowjanya Komatineni reg = <0x838 0x1300>; 158c4153885SSowjanya Komatineni status = "disabled"; 159c4153885SSowjanya Komatineni assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>, 160c4153885SSowjanya Komatineni <&tegra_car TEGRA210_CLK_CILCD>, 161c4153885SSowjanya Komatineni <&tegra_car TEGRA210_CLK_CILE>, 162c4153885SSowjanya Komatineni <&tegra_car TEGRA210_CLK_CSI_TPG>; 163c4153885SSowjanya Komatineni assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>, 164c4153885SSowjanya Komatineni <&tegra_car TEGRA210_CLK_PLL_P>, 165c4153885SSowjanya Komatineni <&tegra_car TEGRA210_CLK_PLL_P>; 166c4153885SSowjanya Komatineni assigned-clock-rates = <102000000>, 167c4153885SSowjanya Komatineni <102000000>, 168c4153885SSowjanya Komatineni <102000000>, 169c4153885SSowjanya Komatineni <972000000>; 170c4153885SSowjanya Komatineni 171c4153885SSowjanya Komatineni clocks = <&tegra_car TEGRA210_CLK_CSI>, 172c4153885SSowjanya Komatineni <&tegra_car TEGRA210_CLK_CILAB>, 173c4153885SSowjanya Komatineni <&tegra_car TEGRA210_CLK_CILCD>, 174c4153885SSowjanya Komatineni <&tegra_car TEGRA210_CLK_CILE>, 175c4153885SSowjanya Komatineni <&tegra_car TEGRA210_CLK_CSI_TPG>; 176c4153885SSowjanya Komatineni clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg"; 177c4153885SSowjanya Komatineni power-domains = <&pd_sor>; 178c4153885SSowjanya Komatineni }; 179742af7e7SThierry Reding }; 180742af7e7SThierry Reding 181be70771dSThierry Reding tsec@54100000 { 182742af7e7SThierry Reding compatible = "nvidia,tegra210-tsec"; 183742af7e7SThierry Reding reg = <0x0 0x54100000 0x0 0x00040000>; 184742af7e7SThierry Reding }; 185742af7e7SThierry Reding 186be70771dSThierry Reding dc@54200000 { 187742af7e7SThierry Reding compatible = "nvidia,tegra210-dc"; 188742af7e7SThierry Reding reg = <0x0 0x54200000 0x0 0x00040000>; 189742af7e7SThierry Reding interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 190352092b0SThierry Reding clocks = <&tegra_car TEGRA210_CLK_DISP1>; 191352092b0SThierry Reding clock-names = "dc"; 192742af7e7SThierry Reding resets = <&tegra_car 27>; 193742af7e7SThierry Reding reset-names = "dc"; 194742af7e7SThierry Reding 195742af7e7SThierry Reding iommus = <&mc TEGRA_SWGROUP_DC>; 196742af7e7SThierry Reding 1970cc6ba3cSThierry Reding nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 198742af7e7SThierry Reding nvidia,head = <0>; 199742af7e7SThierry Reding }; 200742af7e7SThierry Reding 201be70771dSThierry Reding dc@54240000 { 202742af7e7SThierry Reding compatible = "nvidia,tegra210-dc"; 203742af7e7SThierry Reding reg = <0x0 0x54240000 0x0 0x00040000>; 204742af7e7SThierry Reding interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 205352092b0SThierry Reding clocks = <&tegra_car TEGRA210_CLK_DISP2>; 206352092b0SThierry Reding clock-names = "dc"; 207742af7e7SThierry Reding resets = <&tegra_car 26>; 208742af7e7SThierry Reding reset-names = "dc"; 209742af7e7SThierry Reding 210742af7e7SThierry Reding iommus = <&mc TEGRA_SWGROUP_DCB>; 211742af7e7SThierry Reding 2120cc6ba3cSThierry Reding nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 213742af7e7SThierry Reding nvidia,head = <1>; 214742af7e7SThierry Reding }; 215742af7e7SThierry Reding 2160cc6ba3cSThierry Reding dsia: dsi@54300000 { 217742af7e7SThierry Reding compatible = "nvidia,tegra210-dsi"; 218742af7e7SThierry Reding reg = <0x0 0x54300000 0x0 0x00040000>; 219742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_DSIA>, 220742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_DSIALP>, 221742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; 222742af7e7SThierry Reding clock-names = "dsi", "lp", "parent"; 223742af7e7SThierry Reding resets = <&tegra_car 48>; 224742af7e7SThierry Reding reset-names = "dsi"; 22596d1f078SJon Hunter power-domains = <&pd_sor>; 226742af7e7SThierry Reding nvidia,mipi-calibrate = <&mipi 0x0c0>; /* DSIA & DSIB pads */ 227742af7e7SThierry Reding 228742af7e7SThierry Reding status = "disabled"; 229742af7e7SThierry Reding 230742af7e7SThierry Reding #address-cells = <1>; 231742af7e7SThierry Reding #size-cells = <0>; 232742af7e7SThierry Reding }; 233742af7e7SThierry Reding 234be70771dSThierry Reding vic@54340000 { 235742af7e7SThierry Reding compatible = "nvidia,tegra210-vic"; 236742af7e7SThierry Reding reg = <0x0 0x54340000 0x0 0x00040000>; 23724963d1bSMikko Perttunen interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 23824963d1bSMikko Perttunen clocks = <&tegra_car TEGRA210_CLK_VIC03>; 23924963d1bSMikko Perttunen clock-names = "vic"; 24024963d1bSMikko Perttunen resets = <&tegra_car 178>; 24124963d1bSMikko Perttunen reset-names = "vic"; 24224963d1bSMikko Perttunen 24324963d1bSMikko Perttunen iommus = <&mc TEGRA_SWGROUP_VIC>; 24424963d1bSMikko Perttunen power-domains = <&pd_vic>; 245742af7e7SThierry Reding }; 246742af7e7SThierry Reding 247be70771dSThierry Reding nvjpg@54380000 { 248742af7e7SThierry Reding compatible = "nvidia,tegra210-nvjpg"; 249742af7e7SThierry Reding reg = <0x0 0x54380000 0x0 0x00040000>; 250742af7e7SThierry Reding status = "disabled"; 251742af7e7SThierry Reding }; 252742af7e7SThierry Reding 2530cc6ba3cSThierry Reding dsib: dsi@54400000 { 254742af7e7SThierry Reding compatible = "nvidia,tegra210-dsi"; 255742af7e7SThierry Reding reg = <0x0 0x54400000 0x0 0x00040000>; 256742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_DSIB>, 257742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_DSIBLP>, 258742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; 259742af7e7SThierry Reding clock-names = "dsi", "lp", "parent"; 260742af7e7SThierry Reding resets = <&tegra_car 82>; 261742af7e7SThierry Reding reset-names = "dsi"; 26296d1f078SJon Hunter power-domains = <&pd_sor>; 263742af7e7SThierry Reding nvidia,mipi-calibrate = <&mipi 0x300>; /* DSIC & DSID pads */ 264742af7e7SThierry Reding 265742af7e7SThierry Reding status = "disabled"; 266742af7e7SThierry Reding 267742af7e7SThierry Reding #address-cells = <1>; 268742af7e7SThierry Reding #size-cells = <0>; 269742af7e7SThierry Reding }; 270742af7e7SThierry Reding 271be70771dSThierry Reding nvdec@54480000 { 272742af7e7SThierry Reding compatible = "nvidia,tegra210-nvdec"; 273742af7e7SThierry Reding reg = <0x0 0x54480000 0x0 0x00040000>; 274742af7e7SThierry Reding status = "disabled"; 275742af7e7SThierry Reding }; 276742af7e7SThierry Reding 277be70771dSThierry Reding nvenc@544c0000 { 278742af7e7SThierry Reding compatible = "nvidia,tegra210-nvenc"; 279742af7e7SThierry Reding reg = <0x0 0x544c0000 0x0 0x00040000>; 280742af7e7SThierry Reding status = "disabled"; 281742af7e7SThierry Reding }; 282742af7e7SThierry Reding 283be70771dSThierry Reding tsec@54500000 { 284742af7e7SThierry Reding compatible = "nvidia,tegra210-tsec"; 285742af7e7SThierry Reding reg = <0x0 0x54500000 0x0 0x00040000>; 286742af7e7SThierry Reding status = "disabled"; 287742af7e7SThierry Reding }; 288742af7e7SThierry Reding 2890cc6ba3cSThierry Reding sor0: sor@54540000 { 290742af7e7SThierry Reding compatible = "nvidia,tegra210-sor"; 291742af7e7SThierry Reding reg = <0x0 0x54540000 0x0 0x00040000>; 292742af7e7SThierry Reding interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 293742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_SOR0>, 294ed93a666SThierry Reding <&tegra_car TEGRA210_CLK_SOR0_OUT>, 295742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_PLL_D_OUT0>, 296742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_PLL_DP>, 297742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_SOR_SAFE>; 298ed93a666SThierry Reding clock-names = "sor", "out", "parent", "dp", "safe"; 299742af7e7SThierry Reding resets = <&tegra_car 182>; 300742af7e7SThierry Reding reset-names = "sor"; 30166b2d6e9SJon Hunter pinctrl-0 = <&state_dpaux_aux>; 30266b2d6e9SJon Hunter pinctrl-1 = <&state_dpaux_i2c>; 30366b2d6e9SJon Hunter pinctrl-2 = <&state_dpaux_off>; 30466b2d6e9SJon Hunter pinctrl-names = "aux", "i2c", "off"; 30596d1f078SJon Hunter power-domains = <&pd_sor>; 306742af7e7SThierry Reding status = "disabled"; 307742af7e7SThierry Reding }; 308742af7e7SThierry Reding 3090cc6ba3cSThierry Reding sor1: sor@54580000 { 310742af7e7SThierry Reding compatible = "nvidia,tegra210-sor1"; 311742af7e7SThierry Reding reg = <0x0 0x54580000 0x0 0x00040000>; 312742af7e7SThierry Reding interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 313742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_SOR1>, 31450f5b841SThierry Reding <&tegra_car TEGRA210_CLK_SOR1_OUT>, 315742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_PLL_D2_OUT0>, 316742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_PLL_DP>, 317742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_SOR_SAFE>; 31850f5b841SThierry Reding clock-names = "sor", "out", "parent", "dp", "safe"; 319742af7e7SThierry Reding resets = <&tegra_car 183>; 320742af7e7SThierry Reding reset-names = "sor"; 32166b2d6e9SJon Hunter pinctrl-0 = <&state_dpaux1_aux>; 32266b2d6e9SJon Hunter pinctrl-1 = <&state_dpaux1_i2c>; 32366b2d6e9SJon Hunter pinctrl-2 = <&state_dpaux1_off>; 32466b2d6e9SJon Hunter pinctrl-names = "aux", "i2c", "off"; 32596d1f078SJon Hunter power-domains = <&pd_sor>; 326742af7e7SThierry Reding status = "disabled"; 327742af7e7SThierry Reding }; 328742af7e7SThierry Reding 329be70771dSThierry Reding dpaux: dpaux@545c0000 { 330e989992aSThierry Reding compatible = "nvidia,tegra210-dpaux"; 331742af7e7SThierry Reding reg = <0x0 0x545c0000 0x0 0x00040000>; 332742af7e7SThierry Reding interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 333742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_DPAUX>, 334742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_PLL_DP>; 335742af7e7SThierry Reding clock-names = "dpaux", "parent"; 336742af7e7SThierry Reding resets = <&tegra_car 181>; 337742af7e7SThierry Reding reset-names = "dpaux"; 33896d1f078SJon Hunter power-domains = <&pd_sor>; 339742af7e7SThierry Reding status = "disabled"; 34066b2d6e9SJon Hunter 34166b2d6e9SJon Hunter state_dpaux_aux: pinmux-aux { 34266b2d6e9SJon Hunter groups = "dpaux-io"; 34366b2d6e9SJon Hunter function = "aux"; 34466b2d6e9SJon Hunter }; 34566b2d6e9SJon Hunter 34666b2d6e9SJon Hunter state_dpaux_i2c: pinmux-i2c { 34766b2d6e9SJon Hunter groups = "dpaux-io"; 34866b2d6e9SJon Hunter function = "i2c"; 34966b2d6e9SJon Hunter }; 35066b2d6e9SJon Hunter 35166b2d6e9SJon Hunter state_dpaux_off: pinmux-off { 35266b2d6e9SJon Hunter groups = "dpaux-io"; 35366b2d6e9SJon Hunter function = "off"; 35466b2d6e9SJon Hunter }; 35566b2d6e9SJon Hunter 35666b2d6e9SJon Hunter i2c-bus { 35766b2d6e9SJon Hunter #address-cells = <1>; 35866b2d6e9SJon Hunter #size-cells = <0>; 35966b2d6e9SJon Hunter }; 360742af7e7SThierry Reding }; 361742af7e7SThierry Reding 362be70771dSThierry Reding isp@54600000 { 363742af7e7SThierry Reding compatible = "nvidia,tegra210-isp"; 364742af7e7SThierry Reding reg = <0x0 0x54600000 0x0 0x00040000>; 365742af7e7SThierry Reding interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 36697ace1b4SThierry Reding clocks = <&tegra_car TEGRA210_CLK_ISPA>; 36797ace1b4SThierry Reding resets = <&tegra_car 23>; 36897ace1b4SThierry Reding reset-names = "isp"; 369742af7e7SThierry Reding status = "disabled"; 370742af7e7SThierry Reding }; 371742af7e7SThierry Reding 372be70771dSThierry Reding isp@54680000 { 373742af7e7SThierry Reding compatible = "nvidia,tegra210-isp"; 374742af7e7SThierry Reding reg = <0x0 0x54680000 0x0 0x00040000>; 375742af7e7SThierry Reding interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 37697ace1b4SThierry Reding clocks = <&tegra_car TEGRA210_CLK_ISPB>; 37797ace1b4SThierry Reding resets = <&tegra_car 3>; 37897ace1b4SThierry Reding reset-names = "isp"; 379742af7e7SThierry Reding status = "disabled"; 380742af7e7SThierry Reding }; 381742af7e7SThierry Reding 382be70771dSThierry Reding i2c@546c0000 { 383742af7e7SThierry Reding compatible = "nvidia,tegra210-i2c-vi"; 384742af7e7SThierry Reding reg = <0x0 0x546c0000 0x0 0x00040000>; 385742af7e7SThierry Reding interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 386139a390cSSowjanya Komatineni clocks = <&tegra_car TEGRA210_CLK_VI_I2C>, 387139a390cSSowjanya Komatineni <&tegra_car TEGRA210_CLK_I2CSLOW>; 388139a390cSSowjanya Komatineni clock-names = "div-clk", "slow"; 389139a390cSSowjanya Komatineni resets = <&tegra_car 208>; 390139a390cSSowjanya Komatineni reset-names = "i2c"; 391139a390cSSowjanya Komatineni power-domains = <&pd_venc>; 392742af7e7SThierry Reding status = "disabled"; 3934087162fSThierry Reding 3944087162fSThierry Reding #address-cells = <1>; 3954087162fSThierry Reding #size-cells = <0>; 396742af7e7SThierry Reding }; 397742af7e7SThierry Reding }; 398742af7e7SThierry Reding 399be70771dSThierry Reding gic: interrupt-controller@50041000 { 400742af7e7SThierry Reding compatible = "arm,gic-400"; 401742af7e7SThierry Reding #interrupt-cells = <3>; 402742af7e7SThierry Reding interrupt-controller; 403742af7e7SThierry Reding reg = <0x0 0x50041000 0x0 0x1000>, 404742af7e7SThierry Reding <0x0 0x50042000 0x0 0x2000>, 405742af7e7SThierry Reding <0x0 0x50044000 0x0 0x2000>, 406742af7e7SThierry Reding <0x0 0x50046000 0x0 0x2000>; 407742af7e7SThierry Reding interrupts = <GIC_PPI 9 408742af7e7SThierry Reding (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 409742af7e7SThierry Reding interrupt-parent = <&gic>; 410742af7e7SThierry Reding }; 411742af7e7SThierry Reding 412be70771dSThierry Reding gpu@57000000 { 413742af7e7SThierry Reding compatible = "nvidia,gm20b"; 414742af7e7SThierry Reding reg = <0x0 0x57000000 0x0 0x01000000>, 415742af7e7SThierry Reding <0x0 0x58000000 0x0 0x01000000>; 416742af7e7SThierry Reding interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 417742af7e7SThierry Reding <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 418742af7e7SThierry Reding interrupt-names = "stall", "nonstall"; 419742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_GPU>, 4204a0778e9SAlexandre Courbot <&tegra_car TEGRA210_CLK_PLL_P_OUT5>, 4214a0778e9SAlexandre Courbot <&tegra_car TEGRA210_CLK_PLL_G_REF>; 4224a0778e9SAlexandre Courbot clock-names = "gpu", "pwr", "ref"; 423742af7e7SThierry Reding resets = <&tegra_car 184>; 424742af7e7SThierry Reding reset-names = "gpu"; 42530f949bcSAlexandre Courbot 42630f949bcSAlexandre Courbot iommus = <&mc TEGRA_SWGROUP_GPU>; 42730f949bcSAlexandre Courbot 428742af7e7SThierry Reding status = "disabled"; 429742af7e7SThierry Reding }; 430742af7e7SThierry Reding 431be70771dSThierry Reding lic: interrupt-controller@60004000 { 432742af7e7SThierry Reding compatible = "nvidia,tegra210-ictlr"; 433742af7e7SThierry Reding reg = <0x0 0x60004000 0x0 0x40>, /* primary controller */ 434742af7e7SThierry Reding <0x0 0x60004100 0x0 0x40>, /* secondary controller */ 435742af7e7SThierry Reding <0x0 0x60004200 0x0 0x40>, /* tertiary controller */ 436742af7e7SThierry Reding <0x0 0x60004300 0x0 0x40>, /* quaternary controller */ 437742af7e7SThierry Reding <0x0 0x60004400 0x0 0x40>, /* quinary controller */ 438742af7e7SThierry Reding <0x0 0x60004500 0x0 0x40>; /* senary controller */ 439742af7e7SThierry Reding interrupt-controller; 440742af7e7SThierry Reding #interrupt-cells = <3>; 441742af7e7SThierry Reding interrupt-parent = <&gic>; 442742af7e7SThierry Reding }; 443742af7e7SThierry Reding 444be70771dSThierry Reding timer@60005000 { 445d9931a18SJoseph Lo compatible = "nvidia,tegra210-timer"; 446742af7e7SThierry Reding reg = <0x0 0x60005000 0x0 0x400>; 447d9931a18SJoseph Lo interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 448d9931a18SJoseph Lo <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 449742af7e7SThierry Reding <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 450742af7e7SThierry Reding <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 451742af7e7SThierry Reding <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 452742af7e7SThierry Reding <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 453d9931a18SJoseph Lo <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 454d9931a18SJoseph Lo <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 455d9931a18SJoseph Lo <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 456d9931a18SJoseph Lo <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 457d9931a18SJoseph Lo <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 458d9931a18SJoseph Lo <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 459d9931a18SJoseph Lo <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, 460d9931a18SJoseph Lo <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 461742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_TIMER>; 462742af7e7SThierry Reding clock-names = "timer"; 463742af7e7SThierry Reding }; 464742af7e7SThierry Reding 465be70771dSThierry Reding tegra_car: clock@60006000 { 466742af7e7SThierry Reding compatible = "nvidia,tegra210-car"; 467742af7e7SThierry Reding reg = <0x0 0x60006000 0x0 0x1000>; 468742af7e7SThierry Reding #clock-cells = <1>; 469742af7e7SThierry Reding #reset-cells = <1>; 470742af7e7SThierry Reding }; 471742af7e7SThierry Reding 472be70771dSThierry Reding flow-controller@60007000 { 473742af7e7SThierry Reding compatible = "nvidia,tegra210-flowctrl"; 474742af7e7SThierry Reding reg = <0x0 0x60007000 0x0 0x1000>; 475742af7e7SThierry Reding }; 476742af7e7SThierry Reding 477be70771dSThierry Reding gpio: gpio@6000d000 { 47801665512SStephen Warren compatible = "nvidia,tegra210-gpio", "nvidia,tegra30-gpio"; 479742af7e7SThierry Reding reg = <0x0 0x6000d000 0x0 0x1000>; 480742af7e7SThierry Reding interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 481742af7e7SThierry Reding <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 482742af7e7SThierry Reding <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 483742af7e7SThierry Reding <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 484742af7e7SThierry Reding <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 485742af7e7SThierry Reding <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 486742af7e7SThierry Reding <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 487742af7e7SThierry Reding <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 488742af7e7SThierry Reding #gpio-cells = <2>; 489742af7e7SThierry Reding gpio-controller; 490742af7e7SThierry Reding #interrupt-cells = <2>; 491742af7e7SThierry Reding interrupt-controller; 492742af7e7SThierry Reding }; 493742af7e7SThierry Reding 494be70771dSThierry Reding apbdma: dma@60020000 { 495742af7e7SThierry Reding compatible = "nvidia,tegra210-apbdma", "nvidia,tegra148-apbdma"; 496742af7e7SThierry Reding reg = <0x0 0x60020000 0x0 0x1400>; 497742af7e7SThierry Reding interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 498742af7e7SThierry Reding <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 499742af7e7SThierry Reding <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 500742af7e7SThierry Reding <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 501742af7e7SThierry Reding <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 502742af7e7SThierry Reding <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 503742af7e7SThierry Reding <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 504742af7e7SThierry Reding <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 505742af7e7SThierry Reding <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 506742af7e7SThierry Reding <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 507742af7e7SThierry Reding <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 508742af7e7SThierry Reding <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 509742af7e7SThierry Reding <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 510742af7e7SThierry Reding <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 511742af7e7SThierry Reding <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 512742af7e7SThierry Reding <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 513742af7e7SThierry Reding <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 514742af7e7SThierry Reding <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 515742af7e7SThierry Reding <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 516742af7e7SThierry Reding <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 517742af7e7SThierry Reding <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 518742af7e7SThierry Reding <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 519742af7e7SThierry Reding <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 520742af7e7SThierry Reding <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 521742af7e7SThierry Reding <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 522742af7e7SThierry Reding <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 523742af7e7SThierry Reding <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 524742af7e7SThierry Reding <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 525742af7e7SThierry Reding <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 526742af7e7SThierry Reding <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 527742af7e7SThierry Reding <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 528742af7e7SThierry Reding <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 529742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_APBDMA>; 530742af7e7SThierry Reding clock-names = "dma"; 531742af7e7SThierry Reding resets = <&tegra_car 34>; 532742af7e7SThierry Reding reset-names = "dma"; 533742af7e7SThierry Reding #dma-cells = <1>; 534742af7e7SThierry Reding }; 535742af7e7SThierry Reding 536be70771dSThierry Reding apbmisc@70000800 { 537742af7e7SThierry Reding compatible = "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc"; 538742af7e7SThierry Reding reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */ 53946e4b227SJoseph Lo <0x0 0x70000008 0x0 0x04>; /* Strapping options */ 540742af7e7SThierry Reding }; 541742af7e7SThierry Reding 542be70771dSThierry Reding pinmux: pinmux@700008d4 { 543742af7e7SThierry Reding compatible = "nvidia,tegra210-pinmux"; 544742af7e7SThierry Reding reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */ 545742af7e7SThierry Reding <0x0 0x70003000 0x0 0x294>; /* Mux registers */ 5464e0f1229SSowjanya Komatineni sdmmc1_3v3_drv: sdmmc1-3v3-drv { 5474e0f1229SSowjanya Komatineni sdmmc1 { 5484e0f1229SSowjanya Komatineni nvidia,pins = "drive_sdmmc1"; 5494e0f1229SSowjanya Komatineni nvidia,pull-down-strength = <0x8>; 5504e0f1229SSowjanya Komatineni nvidia,pull-up-strength = <0x8>; 5514e0f1229SSowjanya Komatineni }; 5524e0f1229SSowjanya Komatineni }; 5534e0f1229SSowjanya Komatineni sdmmc1_1v8_drv: sdmmc1-1v8-drv { 5544e0f1229SSowjanya Komatineni sdmmc1 { 5554e0f1229SSowjanya Komatineni nvidia,pins = "drive_sdmmc1"; 5564e0f1229SSowjanya Komatineni nvidia,pull-down-strength = <0x4>; 5574e0f1229SSowjanya Komatineni nvidia,pull-up-strength = <0x3>; 5584e0f1229SSowjanya Komatineni }; 5594e0f1229SSowjanya Komatineni }; 5604e0f1229SSowjanya Komatineni sdmmc2_1v8_drv: sdmmc2-1v8-drv { 5614e0f1229SSowjanya Komatineni sdmmc2 { 5624e0f1229SSowjanya Komatineni nvidia,pins = "drive_sdmmc2"; 5634e0f1229SSowjanya Komatineni nvidia,pull-down-strength = <0x10>; 5644e0f1229SSowjanya Komatineni nvidia,pull-up-strength = <0x10>; 5654e0f1229SSowjanya Komatineni }; 5664e0f1229SSowjanya Komatineni }; 5674e0f1229SSowjanya Komatineni sdmmc3_3v3_drv: sdmmc3-3v3-drv { 5684e0f1229SSowjanya Komatineni sdmmc3 { 5694e0f1229SSowjanya Komatineni nvidia,pins = "drive_sdmmc3"; 5704e0f1229SSowjanya Komatineni nvidia,pull-down-strength = <0x8>; 5714e0f1229SSowjanya Komatineni nvidia,pull-up-strength = <0x8>; 5724e0f1229SSowjanya Komatineni }; 5734e0f1229SSowjanya Komatineni }; 5744e0f1229SSowjanya Komatineni sdmmc3_1v8_drv: sdmmc3-1v8-drv { 5754e0f1229SSowjanya Komatineni sdmmc3 { 5764e0f1229SSowjanya Komatineni nvidia,pins = "drive_sdmmc3"; 5774e0f1229SSowjanya Komatineni nvidia,pull-down-strength = <0x4>; 5784e0f1229SSowjanya Komatineni nvidia,pull-up-strength = <0x3>; 5794e0f1229SSowjanya Komatineni }; 5804e0f1229SSowjanya Komatineni }; 5814e0f1229SSowjanya Komatineni sdmmc4_1v8_drv: sdmmc4-1v8-drv { 5824e0f1229SSowjanya Komatineni sdmmc4 { 5834e0f1229SSowjanya Komatineni nvidia,pins = "drive_sdmmc4"; 5844e0f1229SSowjanya Komatineni nvidia,pull-down-strength = <0x10>; 5854e0f1229SSowjanya Komatineni nvidia,pull-up-strength = <0x10>; 5864e0f1229SSowjanya Komatineni }; 5874e0f1229SSowjanya Komatineni }; 588742af7e7SThierry Reding }; 589742af7e7SThierry Reding 590742af7e7SThierry Reding /* 591742af7e7SThierry Reding * There are two serial driver i.e. 8250 based simple serial 592742af7e7SThierry Reding * driver and APB DMA based serial driver for higher baudrate 593ef769e32SAdam Buchbinder * and performance. To enable the 8250 based driver, the compatible 594742af7e7SThierry Reding * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable 59568cd8b2eSThierry Reding * the APB DMA based serial driver, the compatible is 596742af7e7SThierry Reding * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". 597742af7e7SThierry Reding */ 598be70771dSThierry Reding uarta: serial@70006000 { 599742af7e7SThierry Reding compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 600742af7e7SThierry Reding reg = <0x0 0x70006000 0x0 0x40>; 601742af7e7SThierry Reding reg-shift = <2>; 602742af7e7SThierry Reding interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 603742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_UARTA>; 604742af7e7SThierry Reding clock-names = "serial"; 605742af7e7SThierry Reding resets = <&tegra_car 6>; 606742af7e7SThierry Reding reset-names = "serial"; 607742af7e7SThierry Reding dmas = <&apbdma 8>, <&apbdma 8>; 608742af7e7SThierry Reding dma-names = "rx", "tx"; 609742af7e7SThierry Reding status = "disabled"; 610742af7e7SThierry Reding }; 611742af7e7SThierry Reding 612be70771dSThierry Reding uartb: serial@70006040 { 613742af7e7SThierry Reding compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 614742af7e7SThierry Reding reg = <0x0 0x70006040 0x0 0x40>; 615742af7e7SThierry Reding reg-shift = <2>; 616742af7e7SThierry Reding interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 617742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_UARTB>; 618742af7e7SThierry Reding clock-names = "serial"; 619742af7e7SThierry Reding resets = <&tegra_car 7>; 620742af7e7SThierry Reding reset-names = "serial"; 621742af7e7SThierry Reding dmas = <&apbdma 9>, <&apbdma 9>; 622742af7e7SThierry Reding dma-names = "rx", "tx"; 623742af7e7SThierry Reding status = "disabled"; 624742af7e7SThierry Reding }; 625742af7e7SThierry Reding 626be70771dSThierry Reding uartc: serial@70006200 { 627742af7e7SThierry Reding compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 628742af7e7SThierry Reding reg = <0x0 0x70006200 0x0 0x40>; 629742af7e7SThierry Reding reg-shift = <2>; 630742af7e7SThierry Reding interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 631742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_UARTC>; 632742af7e7SThierry Reding clock-names = "serial"; 633742af7e7SThierry Reding resets = <&tegra_car 55>; 634742af7e7SThierry Reding reset-names = "serial"; 635742af7e7SThierry Reding dmas = <&apbdma 10>, <&apbdma 10>; 636742af7e7SThierry Reding dma-names = "rx", "tx"; 637742af7e7SThierry Reding status = "disabled"; 638742af7e7SThierry Reding }; 639742af7e7SThierry Reding 640be70771dSThierry Reding uartd: serial@70006300 { 641742af7e7SThierry Reding compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 642742af7e7SThierry Reding reg = <0x0 0x70006300 0x0 0x40>; 643742af7e7SThierry Reding reg-shift = <2>; 644742af7e7SThierry Reding interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 645742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_UARTD>; 646742af7e7SThierry Reding clock-names = "serial"; 647742af7e7SThierry Reding resets = <&tegra_car 65>; 648742af7e7SThierry Reding reset-names = "serial"; 649742af7e7SThierry Reding dmas = <&apbdma 19>, <&apbdma 19>; 650742af7e7SThierry Reding dma-names = "rx", "tx"; 651742af7e7SThierry Reding status = "disabled"; 652742af7e7SThierry Reding }; 653742af7e7SThierry Reding 654be70771dSThierry Reding pwm: pwm@7000a000 { 655742af7e7SThierry Reding compatible = "nvidia,tegra210-pwm", "nvidia,tegra20-pwm"; 656742af7e7SThierry Reding reg = <0x0 0x7000a000 0x0 0x100>; 657742af7e7SThierry Reding #pwm-cells = <2>; 658742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_PWM>; 659742af7e7SThierry Reding clock-names = "pwm"; 660742af7e7SThierry Reding resets = <&tegra_car 17>; 661742af7e7SThierry Reding reset-names = "pwm"; 662742af7e7SThierry Reding status = "disabled"; 663742af7e7SThierry Reding }; 664742af7e7SThierry Reding 665be70771dSThierry Reding i2c@7000c000 { 666140723b9SSowjanya Komatineni compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 667742af7e7SThierry Reding reg = <0x0 0x7000c000 0x0 0x100>; 668742af7e7SThierry Reding interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 669742af7e7SThierry Reding #address-cells = <1>; 670742af7e7SThierry Reding #size-cells = <0>; 671742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_I2C1>; 672742af7e7SThierry Reding clock-names = "div-clk"; 673742af7e7SThierry Reding resets = <&tegra_car 12>; 674742af7e7SThierry Reding reset-names = "i2c"; 675742af7e7SThierry Reding dmas = <&apbdma 21>, <&apbdma 21>; 676742af7e7SThierry Reding dma-names = "rx", "tx"; 677742af7e7SThierry Reding status = "disabled"; 678742af7e7SThierry Reding }; 679742af7e7SThierry Reding 680be70771dSThierry Reding i2c@7000c400 { 681140723b9SSowjanya Komatineni compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 682742af7e7SThierry Reding reg = <0x0 0x7000c400 0x0 0x100>; 683742af7e7SThierry Reding interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 684742af7e7SThierry Reding #address-cells = <1>; 685742af7e7SThierry Reding #size-cells = <0>; 686742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_I2C2>; 687742af7e7SThierry Reding clock-names = "div-clk"; 688742af7e7SThierry Reding resets = <&tegra_car 54>; 689742af7e7SThierry Reding reset-names = "i2c"; 690742af7e7SThierry Reding dmas = <&apbdma 22>, <&apbdma 22>; 691742af7e7SThierry Reding dma-names = "rx", "tx"; 692742af7e7SThierry Reding status = "disabled"; 693742af7e7SThierry Reding }; 694742af7e7SThierry Reding 695be70771dSThierry Reding i2c@7000c500 { 696140723b9SSowjanya Komatineni compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 697742af7e7SThierry Reding reg = <0x0 0x7000c500 0x0 0x100>; 698742af7e7SThierry Reding interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 699742af7e7SThierry Reding #address-cells = <1>; 700742af7e7SThierry Reding #size-cells = <0>; 701742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_I2C3>; 702742af7e7SThierry Reding clock-names = "div-clk"; 703742af7e7SThierry Reding resets = <&tegra_car 67>; 704742af7e7SThierry Reding reset-names = "i2c"; 705742af7e7SThierry Reding dmas = <&apbdma 23>, <&apbdma 23>; 706742af7e7SThierry Reding dma-names = "rx", "tx"; 707742af7e7SThierry Reding status = "disabled"; 708742af7e7SThierry Reding }; 709742af7e7SThierry Reding 710be70771dSThierry Reding i2c@7000c700 { 711140723b9SSowjanya Komatineni compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 712742af7e7SThierry Reding reg = <0x0 0x7000c700 0x0 0x100>; 713742af7e7SThierry Reding interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 714742af7e7SThierry Reding #address-cells = <1>; 715742af7e7SThierry Reding #size-cells = <0>; 716742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_I2C4>; 717742af7e7SThierry Reding clock-names = "div-clk"; 718742af7e7SThierry Reding resets = <&tegra_car 103>; 719742af7e7SThierry Reding reset-names = "i2c"; 720742af7e7SThierry Reding dmas = <&apbdma 26>, <&apbdma 26>; 721742af7e7SThierry Reding dma-names = "rx", "tx"; 72266b2d6e9SJon Hunter pinctrl-0 = <&state_dpaux1_i2c>; 72366b2d6e9SJon Hunter pinctrl-1 = <&state_dpaux1_off>; 72466b2d6e9SJon Hunter pinctrl-names = "default", "idle"; 725742af7e7SThierry Reding status = "disabled"; 726742af7e7SThierry Reding }; 727742af7e7SThierry Reding 728be70771dSThierry Reding i2c@7000d000 { 729140723b9SSowjanya Komatineni compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 730742af7e7SThierry Reding reg = <0x0 0x7000d000 0x0 0x100>; 731742af7e7SThierry Reding interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 732742af7e7SThierry Reding #address-cells = <1>; 733742af7e7SThierry Reding #size-cells = <0>; 734742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_I2C5>; 735742af7e7SThierry Reding clock-names = "div-clk"; 736742af7e7SThierry Reding resets = <&tegra_car 47>; 737742af7e7SThierry Reding reset-names = "i2c"; 738742af7e7SThierry Reding dmas = <&apbdma 24>, <&apbdma 24>; 739742af7e7SThierry Reding dma-names = "rx", "tx"; 740742af7e7SThierry Reding status = "disabled"; 741742af7e7SThierry Reding }; 742742af7e7SThierry Reding 743be70771dSThierry Reding i2c@7000d100 { 744140723b9SSowjanya Komatineni compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 745742af7e7SThierry Reding reg = <0x0 0x7000d100 0x0 0x100>; 746742af7e7SThierry Reding interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 747742af7e7SThierry Reding #address-cells = <1>; 748742af7e7SThierry Reding #size-cells = <0>; 749742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_I2C6>; 750742af7e7SThierry Reding clock-names = "div-clk"; 751742af7e7SThierry Reding resets = <&tegra_car 166>; 752742af7e7SThierry Reding reset-names = "i2c"; 753742af7e7SThierry Reding dmas = <&apbdma 30>, <&apbdma 30>; 754742af7e7SThierry Reding dma-names = "rx", "tx"; 75566b2d6e9SJon Hunter pinctrl-0 = <&state_dpaux_i2c>; 75666b2d6e9SJon Hunter pinctrl-1 = <&state_dpaux_off>; 75766b2d6e9SJon Hunter pinctrl-names = "default", "idle"; 758742af7e7SThierry Reding status = "disabled"; 759742af7e7SThierry Reding }; 760742af7e7SThierry Reding 761be70771dSThierry Reding spi@7000d400 { 762742af7e7SThierry Reding compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 763742af7e7SThierry Reding reg = <0x0 0x7000d400 0x0 0x200>; 764742af7e7SThierry Reding interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 765742af7e7SThierry Reding #address-cells = <1>; 766742af7e7SThierry Reding #size-cells = <0>; 767742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_SBC1>; 768742af7e7SThierry Reding clock-names = "spi"; 769742af7e7SThierry Reding resets = <&tegra_car 41>; 770742af7e7SThierry Reding reset-names = "spi"; 771742af7e7SThierry Reding dmas = <&apbdma 15>, <&apbdma 15>; 772742af7e7SThierry Reding dma-names = "rx", "tx"; 773742af7e7SThierry Reding status = "disabled"; 774742af7e7SThierry Reding }; 775742af7e7SThierry Reding 776be70771dSThierry Reding spi@7000d600 { 777742af7e7SThierry Reding compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 778742af7e7SThierry Reding reg = <0x0 0x7000d600 0x0 0x200>; 779742af7e7SThierry Reding interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 780742af7e7SThierry Reding #address-cells = <1>; 781742af7e7SThierry Reding #size-cells = <0>; 782742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_SBC2>; 783742af7e7SThierry Reding clock-names = "spi"; 784742af7e7SThierry Reding resets = <&tegra_car 44>; 785742af7e7SThierry Reding reset-names = "spi"; 786742af7e7SThierry Reding dmas = <&apbdma 16>, <&apbdma 16>; 787742af7e7SThierry Reding dma-names = "rx", "tx"; 788742af7e7SThierry Reding status = "disabled"; 789742af7e7SThierry Reding }; 790742af7e7SThierry Reding 791be70771dSThierry Reding spi@7000d800 { 792742af7e7SThierry Reding compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 793742af7e7SThierry Reding reg = <0x0 0x7000d800 0x0 0x200>; 794742af7e7SThierry Reding interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 795742af7e7SThierry Reding #address-cells = <1>; 796742af7e7SThierry Reding #size-cells = <0>; 797742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_SBC3>; 798742af7e7SThierry Reding clock-names = "spi"; 799742af7e7SThierry Reding resets = <&tegra_car 46>; 800742af7e7SThierry Reding reset-names = "spi"; 801742af7e7SThierry Reding dmas = <&apbdma 17>, <&apbdma 17>; 802742af7e7SThierry Reding dma-names = "rx", "tx"; 803742af7e7SThierry Reding status = "disabled"; 804742af7e7SThierry Reding }; 805742af7e7SThierry Reding 806be70771dSThierry Reding spi@7000da00 { 807742af7e7SThierry Reding compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 808742af7e7SThierry Reding reg = <0x0 0x7000da00 0x0 0x200>; 809742af7e7SThierry Reding interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 810742af7e7SThierry Reding #address-cells = <1>; 811742af7e7SThierry Reding #size-cells = <0>; 812742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_SBC4>; 813742af7e7SThierry Reding clock-names = "spi"; 814742af7e7SThierry Reding resets = <&tegra_car 68>; 815742af7e7SThierry Reding reset-names = "spi"; 816742af7e7SThierry Reding dmas = <&apbdma 18>, <&apbdma 18>; 817742af7e7SThierry Reding dma-names = "rx", "tx"; 818742af7e7SThierry Reding status = "disabled"; 819742af7e7SThierry Reding }; 820742af7e7SThierry Reding 821be70771dSThierry Reding rtc@7000e000 { 822742af7e7SThierry Reding compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc"; 823742af7e7SThierry Reding reg = <0x0 0x7000e000 0x0 0x100>; 824d13c13f4SSowjanya Komatineni interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; 825359ae651SSowjanya Komatineni interrupt-parent = <&tegra_pmc>; 826742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_RTC>; 827742af7e7SThierry Reding clock-names = "rtc"; 828742af7e7SThierry Reding }; 829742af7e7SThierry Reding 830359ae651SSowjanya Komatineni tegra_pmc: pmc@7000e400 { 831742af7e7SThierry Reding compatible = "nvidia,tegra210-pmc"; 832742af7e7SThierry Reding reg = <0x0 0x7000e400 0x0 0x400>; 833742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; 834742af7e7SThierry Reding clock-names = "pclk", "clk32k_in"; 835359ae651SSowjanya Komatineni #clock-cells = <1>; 836d13c13f4SSowjanya Komatineni #interrupt-cells = <2>; 837d13c13f4SSowjanya Komatineni interrupt-controller; 838c2b82445SJon Hunter 839c2b82445SJon Hunter powergates { 840c2b82445SJon Hunter pd_audio: aud { 841c2b82445SJon Hunter clocks = <&tegra_car TEGRA210_CLK_APE>, 842c2b82445SJon Hunter <&tegra_car TEGRA210_CLK_APB2APE>; 843c2b82445SJon Hunter resets = <&tegra_car 198>; 844c2b82445SJon Hunter #power-domain-cells = <0>; 845c2b82445SJon Hunter }; 846241f02baSJon Hunter 84796d1f078SJon Hunter pd_sor: sor { 84896d1f078SJon Hunter clocks = <&tegra_car TEGRA210_CLK_SOR0>, 84996d1f078SJon Hunter <&tegra_car TEGRA210_CLK_SOR1>, 850b4f99176SSowjanya Komatineni <&tegra_car TEGRA210_CLK_CILAB>, 851b4f99176SSowjanya Komatineni <&tegra_car TEGRA210_CLK_CILCD>, 852b4f99176SSowjanya Komatineni <&tegra_car TEGRA210_CLK_CILE>, 85396d1f078SJon Hunter <&tegra_car TEGRA210_CLK_DSIA>, 85496d1f078SJon Hunter <&tegra_car TEGRA210_CLK_DSIB>, 85596d1f078SJon Hunter <&tegra_car TEGRA210_CLK_DPAUX>, 85696d1f078SJon Hunter <&tegra_car TEGRA210_CLK_DPAUX1>, 85796d1f078SJon Hunter <&tegra_car TEGRA210_CLK_MIPI_CAL>; 85896d1f078SJon Hunter resets = <&tegra_car TEGRA210_CLK_SOR0>, 85996d1f078SJon Hunter <&tegra_car TEGRA210_CLK_SOR1>, 86096d1f078SJon Hunter <&tegra_car TEGRA210_CLK_DSIA>, 86196d1f078SJon Hunter <&tegra_car TEGRA210_CLK_DSIB>, 86296d1f078SJon Hunter <&tegra_car TEGRA210_CLK_DPAUX>, 86396d1f078SJon Hunter <&tegra_car TEGRA210_CLK_DPAUX1>, 86496d1f078SJon Hunter <&tegra_car TEGRA210_CLK_MIPI_CAL>; 86596d1f078SJon Hunter #power-domain-cells = <0>; 86696d1f078SJon Hunter }; 86796d1f078SJon Hunter 868241f02baSJon Hunter pd_xusbss: xusba { 869241f02baSJon Hunter clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>; 870241f02baSJon Hunter resets = <&tegra_car TEGRA210_CLK_XUSB_SS>; 871241f02baSJon Hunter #power-domain-cells = <0>; 872241f02baSJon Hunter }; 873241f02baSJon Hunter 874241f02baSJon Hunter pd_xusbdev: xusbb { 875241f02baSJon Hunter clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>; 876241f02baSJon Hunter resets = <&tegra_car 95>; 877241f02baSJon Hunter #power-domain-cells = <0>; 878241f02baSJon Hunter }; 879241f02baSJon Hunter 880241f02baSJon Hunter pd_xusbhost: xusbc { 881241f02baSJon Hunter clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>; 882241f02baSJon Hunter resets = <&tegra_car TEGRA210_CLK_XUSB_HOST>; 883241f02baSJon Hunter #power-domain-cells = <0>; 884241f02baSJon Hunter }; 88524963d1bSMikko Perttunen 88624963d1bSMikko Perttunen pd_vic: vic { 88724963d1bSMikko Perttunen clocks = <&tegra_car TEGRA210_CLK_VIC03>; 88824963d1bSMikko Perttunen clock-names = "vic"; 88924963d1bSMikko Perttunen resets = <&tegra_car 178>; 89024963d1bSMikko Perttunen reset-names = "vic"; 89124963d1bSMikko Perttunen #power-domain-cells = <0>; 89224963d1bSMikko Perttunen }; 893c4153885SSowjanya Komatineni 894c4153885SSowjanya Komatineni pd_venc: venc { 895c4153885SSowjanya Komatineni clocks = <&tegra_car TEGRA210_CLK_VI>, 896c4153885SSowjanya Komatineni <&tegra_car TEGRA210_CLK_CSI>; 897c4153885SSowjanya Komatineni resets = <&mc TEGRA210_MC_RESET_VI>, 898c4153885SSowjanya Komatineni <&tegra_car 20>, 899c4153885SSowjanya Komatineni <&tegra_car 52>; 900c4153885SSowjanya Komatineni #power-domain-cells = <0>; 901c4153885SSowjanya Komatineni }; 902c2b82445SJon Hunter }; 9036641af7eSAapo Vienamo 9046641af7eSAapo Vienamo sdmmc1_3v3: sdmmc1-3v3 { 9056641af7eSAapo Vienamo pins = "sdmmc1"; 9066641af7eSAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 9076641af7eSAapo Vienamo }; 9086641af7eSAapo Vienamo 9096641af7eSAapo Vienamo sdmmc1_1v8: sdmmc1-1v8 { 9106641af7eSAapo Vienamo pins = "sdmmc1"; 9116641af7eSAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 9126641af7eSAapo Vienamo }; 9136641af7eSAapo Vienamo 9146641af7eSAapo Vienamo sdmmc3_3v3: sdmmc3-3v3 { 9156641af7eSAapo Vienamo pins = "sdmmc3"; 9166641af7eSAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 9176641af7eSAapo Vienamo }; 9186641af7eSAapo Vienamo 9196641af7eSAapo Vienamo sdmmc3_1v8: sdmmc3-1v8 { 9206641af7eSAapo Vienamo pins = "sdmmc3"; 9216641af7eSAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 9226641af7eSAapo Vienamo }; 923871be845SManikanta Maddireddy 924871be845SManikanta Maddireddy pex_dpd_disable: pex_en { 925871be845SManikanta Maddireddy pex-dpd-disable { 926871be845SManikanta Maddireddy pins = "pex-bias", "pex-clk1", "pex-clk2"; 927871be845SManikanta Maddireddy low-power-disable; 928871be845SManikanta Maddireddy }; 929871be845SManikanta Maddireddy }; 930871be845SManikanta Maddireddy 931871be845SManikanta Maddireddy pex_dpd_enable: pex_dis { 932871be845SManikanta Maddireddy pex-dpd-enable { 933871be845SManikanta Maddireddy pins = "pex-bias", "pex-clk1", "pex-clk2"; 934871be845SManikanta Maddireddy low-power-enable; 935871be845SManikanta Maddireddy }; 936871be845SManikanta Maddireddy }; 937742af7e7SThierry Reding }; 938742af7e7SThierry Reding 939be70771dSThierry Reding fuse@7000f800 { 940742af7e7SThierry Reding compatible = "nvidia,tegra210-efuse"; 941742af7e7SThierry Reding reg = <0x0 0x7000f800 0x0 0x400>; 942742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_FUSE>; 943742af7e7SThierry Reding clock-names = "fuse"; 944742af7e7SThierry Reding resets = <&tegra_car 39>; 945742af7e7SThierry Reding reset-names = "fuse"; 946742af7e7SThierry Reding }; 947742af7e7SThierry Reding 948be70771dSThierry Reding mc: memory-controller@70019000 { 949742af7e7SThierry Reding compatible = "nvidia,tegra210-mc"; 950742af7e7SThierry Reding reg = <0x0 0x70019000 0x0 0x1000>; 951742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_MC>; 952742af7e7SThierry Reding clock-names = "mc"; 953742af7e7SThierry Reding 954742af7e7SThierry Reding interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 955742af7e7SThierry Reding 956742af7e7SThierry Reding #iommu-cells = <1>; 9572eb8e1a4SSowjanya Komatineni #reset-cells = <1>; 958742af7e7SThierry Reding }; 959742af7e7SThierry Reding 960e12325f6SThierry Reding emc: external-memory-controller@7001b000 { 961cd9350c5SJoseph Lo compatible = "nvidia,tegra210-emc"; 962cd9350c5SJoseph Lo reg = <0x0 0x7001b000 0x0 0x1000>, 963cd9350c5SJoseph Lo <0x0 0x7001e000 0x0 0x1000>, 964cd9350c5SJoseph Lo <0x0 0x7001f000 0x0 0x1000>; 965cd9350c5SJoseph Lo clocks = <&tegra_car TEGRA210_CLK_EMC>; 966cd9350c5SJoseph Lo clock-names = "emc"; 967cd9350c5SJoseph Lo interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 968cd9350c5SJoseph Lo nvidia,memory-controller = <&mc>; 969e12325f6SThierry Reding #cooling-cells = <2>; 970cd9350c5SJoseph Lo }; 971cd9350c5SJoseph Lo 9726cb60ec4SPreetham Ramchandra sata@70020000 { 9736cb60ec4SPreetham Ramchandra compatible = "nvidia,tegra210-ahci"; 9746cb60ec4SPreetham Ramchandra reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */ 9756cb60ec4SPreetham Ramchandra <0x0 0x70020000 0x0 0x7000>, /* SATA */ 9766cb60ec4SPreetham Ramchandra <0x0 0x70001100 0x0 0x1000>; /* SATA AUX */ 9776cb60ec4SPreetham Ramchandra interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 9786cb60ec4SPreetham Ramchandra clocks = <&tegra_car TEGRA210_CLK_SATA>, 9796cb60ec4SPreetham Ramchandra <&tegra_car TEGRA210_CLK_SATA_OOB>; 9806cb60ec4SPreetham Ramchandra clock-names = "sata", "sata-oob"; 9816cb60ec4SPreetham Ramchandra resets = <&tegra_car 124>, 982c84ebdfdSSowjanya Komatineni <&tegra_car 129>, 983c84ebdfdSSowjanya Komatineni <&tegra_car 123>; 984c84ebdfdSSowjanya Komatineni reset-names = "sata", "sata-cold", "sata-oob"; 9856cb60ec4SPreetham Ramchandra status = "disabled"; 9866cb60ec4SPreetham Ramchandra }; 9876cb60ec4SPreetham Ramchandra 988be70771dSThierry Reding hda@70030000 { 989742af7e7SThierry Reding compatible = "nvidia,tegra210-hda", "nvidia,tegra30-hda"; 990742af7e7SThierry Reding reg = <0x0 0x70030000 0x0 0x10000>; 991742af7e7SThierry Reding interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 992742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_HDA>, 993742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_HDA2HDMI>, 994742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_HDA2CODEC_2X>; 995742af7e7SThierry Reding clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 996742af7e7SThierry Reding resets = <&tegra_car 125>, /* hda */ 997742af7e7SThierry Reding <&tegra_car 128>, /* hda2hdmi */ 998742af7e7SThierry Reding <&tegra_car 111>; /* hda2codec_2x */ 999742af7e7SThierry Reding reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 1000*1e0ca546SSameer Pujar power-domains = <&pd_sor>; 1001742af7e7SThierry Reding status = "disabled"; 1002742af7e7SThierry Reding }; 1003742af7e7SThierry Reding 1004e7a99ac2SThierry Reding usb@70090000 { 1005e7a99ac2SThierry Reding compatible = "nvidia,tegra210-xusb"; 1006e7a99ac2SThierry Reding reg = <0x0 0x70090000 0x0 0x8000>, 1007e7a99ac2SThierry Reding <0x0 0x70098000 0x0 0x1000>, 1008e7a99ac2SThierry Reding <0x0 0x70099000 0x0 0x1000>; 1009e7a99ac2SThierry Reding reg-names = "hcd", "fpci", "ipfs"; 1010e7a99ac2SThierry Reding 1011e7a99ac2SThierry Reding interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 10129168e1dbSJon Hunter <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 1013e7a99ac2SThierry Reding 1014e7a99ac2SThierry Reding clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>, 1015e7a99ac2SThierry Reding <&tegra_car TEGRA210_CLK_XUSB_HOST_SRC>, 1016e7a99ac2SThierry Reding <&tegra_car TEGRA210_CLK_XUSB_FALCON_SRC>, 1017e7a99ac2SThierry Reding <&tegra_car TEGRA210_CLK_XUSB_SS>, 1018e7a99ac2SThierry Reding <&tegra_car TEGRA210_CLK_XUSB_SS_SRC>, 1019d19532e6SThierry Reding <&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>, 1020e7a99ac2SThierry Reding <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>, 1021e7a99ac2SThierry Reding <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>, 1022e7a99ac2SThierry Reding <&tegra_car TEGRA210_CLK_PLL_U_480M>, 1023e7a99ac2SThierry Reding <&tegra_car TEGRA210_CLK_CLK_M>, 1024e7a99ac2SThierry Reding <&tegra_car TEGRA210_CLK_PLL_E>; 1025e7a99ac2SThierry Reding clock-names = "xusb_host", "xusb_host_src", 1026e7a99ac2SThierry Reding "xusb_falcon_src", "xusb_ss", 1027d19532e6SThierry Reding "xusb_ss_src", "xusb_ss_div2", 1028e7a99ac2SThierry Reding "xusb_hs_src", "xusb_fs_src", 1029e7a99ac2SThierry Reding "pll_u_480m", "clk_m", "pll_e"; 1030e7a99ac2SThierry Reding resets = <&tegra_car 89>, <&tegra_car 156>, 1031e7a99ac2SThierry Reding <&tegra_car 143>; 1032e7a99ac2SThierry Reding reset-names = "xusb_host", "xusb_ss", "xusb_src"; 103336ec29f7SJon Hunter power-domains = <&pd_xusbhost>, <&pd_xusbss>; 103436ec29f7SJon Hunter power-domain-names = "xusb_host", "xusb_ss"; 1035e7a99ac2SThierry Reding 1036e7a99ac2SThierry Reding nvidia,xusb-padctl = <&padctl>; 1037e7a99ac2SThierry Reding 1038e7a99ac2SThierry Reding status = "disabled"; 1039e7a99ac2SThierry Reding }; 1040e7a99ac2SThierry Reding 10414e07ac90SThierry Reding padctl: padctl@7009f000 { 10424e07ac90SThierry Reding compatible = "nvidia,tegra210-xusb-padctl"; 10434e07ac90SThierry Reding reg = <0x0 0x7009f000 0x0 0x1000>; 10446450da3dSJC Kuo interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 10454e07ac90SThierry Reding resets = <&tegra_car 142>; 10464e07ac90SThierry Reding reset-names = "padctl"; 10474e07ac90SThierry Reding 10484e07ac90SThierry Reding status = "disabled"; 10494e07ac90SThierry Reding 10504e07ac90SThierry Reding pads { 10514e07ac90SThierry Reding usb2 { 10524e07ac90SThierry Reding clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>; 10534e07ac90SThierry Reding clock-names = "trk"; 10544e07ac90SThierry Reding status = "disabled"; 10554e07ac90SThierry Reding 10564e07ac90SThierry Reding lanes { 10574e07ac90SThierry Reding usb2-0 { 10584e07ac90SThierry Reding status = "disabled"; 10594e07ac90SThierry Reding #phy-cells = <0>; 10604e07ac90SThierry Reding }; 10614e07ac90SThierry Reding 10624e07ac90SThierry Reding usb2-1 { 10634e07ac90SThierry Reding status = "disabled"; 10644e07ac90SThierry Reding #phy-cells = <0>; 10654e07ac90SThierry Reding }; 10664e07ac90SThierry Reding 10674e07ac90SThierry Reding usb2-2 { 10684e07ac90SThierry Reding status = "disabled"; 10694e07ac90SThierry Reding #phy-cells = <0>; 10704e07ac90SThierry Reding }; 10714e07ac90SThierry Reding 10724e07ac90SThierry Reding usb2-3 { 10734e07ac90SThierry Reding status = "disabled"; 10744e07ac90SThierry Reding #phy-cells = <0>; 10754e07ac90SThierry Reding }; 10764e07ac90SThierry Reding }; 10774e07ac90SThierry Reding }; 10784e07ac90SThierry Reding 10794e07ac90SThierry Reding hsic { 10804e07ac90SThierry Reding clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>; 10814e07ac90SThierry Reding clock-names = "trk"; 10824e07ac90SThierry Reding status = "disabled"; 10834e07ac90SThierry Reding 10844e07ac90SThierry Reding lanes { 10854e07ac90SThierry Reding hsic-0 { 10864e07ac90SThierry Reding status = "disabled"; 10874e07ac90SThierry Reding #phy-cells = <0>; 10884e07ac90SThierry Reding }; 10894e07ac90SThierry Reding 10904e07ac90SThierry Reding hsic-1 { 10914e07ac90SThierry Reding status = "disabled"; 10924e07ac90SThierry Reding #phy-cells = <0>; 10934e07ac90SThierry Reding }; 10944e07ac90SThierry Reding }; 10954e07ac90SThierry Reding }; 10964e07ac90SThierry Reding 10974e07ac90SThierry Reding pcie { 10984e07ac90SThierry Reding clocks = <&tegra_car TEGRA210_CLK_PLL_E>; 10994e07ac90SThierry Reding clock-names = "pll"; 11004e07ac90SThierry Reding resets = <&tegra_car 205>; 11014e07ac90SThierry Reding reset-names = "phy"; 11024e07ac90SThierry Reding status = "disabled"; 11034e07ac90SThierry Reding 11044e07ac90SThierry Reding lanes { 11054e07ac90SThierry Reding pcie-0 { 11064e07ac90SThierry Reding status = "disabled"; 11074e07ac90SThierry Reding #phy-cells = <0>; 11084e07ac90SThierry Reding }; 11094e07ac90SThierry Reding 11104e07ac90SThierry Reding pcie-1 { 11114e07ac90SThierry Reding status = "disabled"; 11124e07ac90SThierry Reding #phy-cells = <0>; 11134e07ac90SThierry Reding }; 11144e07ac90SThierry Reding 11154e07ac90SThierry Reding pcie-2 { 11164e07ac90SThierry Reding status = "disabled"; 11174e07ac90SThierry Reding #phy-cells = <0>; 11184e07ac90SThierry Reding }; 11194e07ac90SThierry Reding 11204e07ac90SThierry Reding pcie-3 { 11214e07ac90SThierry Reding status = "disabled"; 11224e07ac90SThierry Reding #phy-cells = <0>; 11234e07ac90SThierry Reding }; 11244e07ac90SThierry Reding 11254e07ac90SThierry Reding pcie-4 { 11264e07ac90SThierry Reding status = "disabled"; 11274e07ac90SThierry Reding #phy-cells = <0>; 11284e07ac90SThierry Reding }; 11294e07ac90SThierry Reding 11304e07ac90SThierry Reding pcie-5 { 11314e07ac90SThierry Reding status = "disabled"; 11324e07ac90SThierry Reding #phy-cells = <0>; 11334e07ac90SThierry Reding }; 11344e07ac90SThierry Reding 11354e07ac90SThierry Reding pcie-6 { 11364e07ac90SThierry Reding status = "disabled"; 11374e07ac90SThierry Reding #phy-cells = <0>; 11384e07ac90SThierry Reding }; 11394e07ac90SThierry Reding }; 11404e07ac90SThierry Reding }; 11414e07ac90SThierry Reding 11424e07ac90SThierry Reding sata { 11434e07ac90SThierry Reding clocks = <&tegra_car TEGRA210_CLK_PLL_E>; 11444e07ac90SThierry Reding clock-names = "pll"; 11454e07ac90SThierry Reding resets = <&tegra_car 204>; 11464e07ac90SThierry Reding reset-names = "phy"; 11474e07ac90SThierry Reding status = "disabled"; 11484e07ac90SThierry Reding 11494e07ac90SThierry Reding lanes { 11504e07ac90SThierry Reding sata-0 { 11514e07ac90SThierry Reding status = "disabled"; 11524e07ac90SThierry Reding #phy-cells = <0>; 11534e07ac90SThierry Reding }; 11544e07ac90SThierry Reding }; 11554e07ac90SThierry Reding }; 11564e07ac90SThierry Reding }; 11574e07ac90SThierry Reding 11584e07ac90SThierry Reding ports { 11594e07ac90SThierry Reding usb2-0 { 11604e07ac90SThierry Reding status = "disabled"; 11614e07ac90SThierry Reding }; 11624e07ac90SThierry Reding 11634e07ac90SThierry Reding usb2-1 { 11644e07ac90SThierry Reding status = "disabled"; 11654e07ac90SThierry Reding }; 11664e07ac90SThierry Reding 11674e07ac90SThierry Reding usb2-2 { 11684e07ac90SThierry Reding status = "disabled"; 11694e07ac90SThierry Reding }; 11704e07ac90SThierry Reding 11714e07ac90SThierry Reding usb2-3 { 11724e07ac90SThierry Reding status = "disabled"; 11734e07ac90SThierry Reding }; 11744e07ac90SThierry Reding 11754e07ac90SThierry Reding hsic-0 { 11764e07ac90SThierry Reding status = "disabled"; 11774e07ac90SThierry Reding }; 11784e07ac90SThierry Reding 11794e07ac90SThierry Reding usb3-0 { 11804e07ac90SThierry Reding status = "disabled"; 11814e07ac90SThierry Reding }; 11824e07ac90SThierry Reding 11834e07ac90SThierry Reding usb3-1 { 11844e07ac90SThierry Reding status = "disabled"; 11854e07ac90SThierry Reding }; 11864e07ac90SThierry Reding 11874e07ac90SThierry Reding usb3-2 { 11884e07ac90SThierry Reding status = "disabled"; 11894e07ac90SThierry Reding }; 11904e07ac90SThierry Reding 11914e07ac90SThierry Reding usb3-3 { 11924e07ac90SThierry Reding status = "disabled"; 11934e07ac90SThierry Reding }; 11944e07ac90SThierry Reding }; 11954e07ac90SThierry Reding }; 11964e07ac90SThierry Reding 119767bb17f6SThierry Reding mmc@700b0000 { 1198b3fa0e03SThierry Reding compatible = "nvidia,tegra210-sdhci"; 1199742af7e7SThierry Reding reg = <0x0 0x700b0000 0x0 0x200>; 1200742af7e7SThierry Reding interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1201679f71faSSowjanya Komatineni clocks = <&tegra_car TEGRA210_CLK_SDMMC1>, 1202679f71faSSowjanya Komatineni <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>; 1203679f71faSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 1204742af7e7SThierry Reding resets = <&tegra_car 14>; 1205742af7e7SThierry Reding reset-names = "sdhci"; 12064e0f1229SSowjanya Komatineni pinctrl-names = "sdmmc-3v3", "sdmmc-1v8", 12074e0f1229SSowjanya Komatineni "sdmmc-3v3-drv", "sdmmc-1v8-drv"; 12086641af7eSAapo Vienamo pinctrl-0 = <&sdmmc1_3v3>; 12096641af7eSAapo Vienamo pinctrl-1 = <&sdmmc1_1v8>; 12104e0f1229SSowjanya Komatineni pinctrl-2 = <&sdmmc1_3v3_drv>; 12114e0f1229SSowjanya Komatineni pinctrl-3 = <&sdmmc1_1v8_drv>; 12121ea06718SAapo Vienamo nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>; 12131ea06718SAapo Vienamo nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>; 12141ea06718SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>; 12151ea06718SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>; 121663af8bcdSAapo Vienamo nvidia,default-tap = <0x2>; 121763af8bcdSAapo Vienamo nvidia,default-trim = <0x4>; 1218918f9671SAapo Vienamo assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>, 1219918f9671SAapo Vienamo <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>, 1220918f9671SAapo Vienamo <&tegra_car TEGRA210_CLK_PLL_C4>; 1221918f9671SAapo Vienamo assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 1222918f9671SAapo Vienamo assigned-clock-rates = <200000000>, <1000000000>, <1000000000>; 1223742af7e7SThierry Reding status = "disabled"; 1224742af7e7SThierry Reding }; 1225742af7e7SThierry Reding 122667bb17f6SThierry Reding mmc@700b0200 { 1227b3fa0e03SThierry Reding compatible = "nvidia,tegra210-sdhci"; 1228742af7e7SThierry Reding reg = <0x0 0x700b0200 0x0 0x200>; 1229742af7e7SThierry Reding interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 1230679f71faSSowjanya Komatineni clocks = <&tegra_car TEGRA210_CLK_SDMMC2>, 1231679f71faSSowjanya Komatineni <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>; 1232679f71faSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 1233742af7e7SThierry Reding resets = <&tegra_car 9>; 1234742af7e7SThierry Reding reset-names = "sdhci"; 12354e0f1229SSowjanya Komatineni pinctrl-names = "sdmmc-1v8-drv"; 12364e0f1229SSowjanya Komatineni pinctrl-0 = <&sdmmc2_1v8_drv>; 12371ea06718SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>; 12381ea06718SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>; 123963af8bcdSAapo Vienamo nvidia,default-tap = <0x8>; 124063af8bcdSAapo Vienamo nvidia,default-trim = <0x0>; 1241742af7e7SThierry Reding status = "disabled"; 1242742af7e7SThierry Reding }; 1243742af7e7SThierry Reding 124467bb17f6SThierry Reding mmc@700b0400 { 1245b3fa0e03SThierry Reding compatible = "nvidia,tegra210-sdhci"; 1246742af7e7SThierry Reding reg = <0x0 0x700b0400 0x0 0x200>; 1247742af7e7SThierry Reding interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 1248679f71faSSowjanya Komatineni clocks = <&tegra_car TEGRA210_CLK_SDMMC3>, 1249679f71faSSowjanya Komatineni <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>; 1250679f71faSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 1251742af7e7SThierry Reding resets = <&tegra_car 69>; 1252742af7e7SThierry Reding reset-names = "sdhci"; 12534e0f1229SSowjanya Komatineni pinctrl-names = "sdmmc-3v3", "sdmmc-1v8", 12544e0f1229SSowjanya Komatineni "sdmmc-3v3-drv", "sdmmc-1v8-drv"; 12556641af7eSAapo Vienamo pinctrl-0 = <&sdmmc3_3v3>; 12566641af7eSAapo Vienamo pinctrl-1 = <&sdmmc3_1v8>; 12574e0f1229SSowjanya Komatineni pinctrl-2 = <&sdmmc3_3v3_drv>; 12584e0f1229SSowjanya Komatineni pinctrl-3 = <&sdmmc3_1v8_drv>; 12591ea06718SAapo Vienamo nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>; 12601ea06718SAapo Vienamo nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>; 12611ea06718SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>; 12621ea06718SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>; 126363af8bcdSAapo Vienamo nvidia,default-tap = <0x3>; 126463af8bcdSAapo Vienamo nvidia,default-trim = <0x3>; 1265742af7e7SThierry Reding status = "disabled"; 1266742af7e7SThierry Reding }; 1267742af7e7SThierry Reding 126867bb17f6SThierry Reding mmc@700b0600 { 1269b3fa0e03SThierry Reding compatible = "nvidia,tegra210-sdhci"; 1270742af7e7SThierry Reding reg = <0x0 0x700b0600 0x0 0x200>; 1271742af7e7SThierry Reding interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1272679f71faSSowjanya Komatineni clocks = <&tegra_car TEGRA210_CLK_SDMMC4>, 1273679f71faSSowjanya Komatineni <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>; 1274679f71faSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 1275742af7e7SThierry Reding resets = <&tegra_car 15>; 1276742af7e7SThierry Reding reset-names = "sdhci"; 12774e0f1229SSowjanya Komatineni pinctrl-names = "sdmmc-3v3-drv", "sdmmc-1v8-drv"; 12784e0f1229SSowjanya Komatineni pinctrl-0 = <&sdmmc4_1v8_drv>; 12794e0f1229SSowjanya Komatineni pinctrl-1 = <&sdmmc4_1v8_drv>; 12801ea06718SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>; 12811ea06718SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>; 128263af8bcdSAapo Vienamo nvidia,default-tap = <0x8>; 128363af8bcdSAapo Vienamo nvidia,default-trim = <0x0>; 1284918f9671SAapo Vienamo assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>, 1285918f9671SAapo Vienamo <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 1286918f9671SAapo Vienamo assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 12875879600aSAapo Vienamo nvidia,dqs-trim = <40>; 1288d5d6b468SAapo Vienamo mmc-hs400-1_8v; 1289742af7e7SThierry Reding status = "disabled"; 1290742af7e7SThierry Reding }; 1291742af7e7SThierry Reding 1292e74db5a5SNagarjuna Kristam usb@700d0000 { 1293e74db5a5SNagarjuna Kristam compatible = "nvidia,tegra210-xudc"; 1294e74db5a5SNagarjuna Kristam reg = <0x0 0x700d0000 0x0 0x8000>, 1295e74db5a5SNagarjuna Kristam <0x0 0x700d8000 0x0 0x1000>, 1296e74db5a5SNagarjuna Kristam <0x0 0x700d9000 0x0 0x1000>; 1297e74db5a5SNagarjuna Kristam reg-names = "base", "fpci", "ipfs"; 1298e74db5a5SNagarjuna Kristam interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1299e74db5a5SNagarjuna Kristam clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>, 1300e74db5a5SNagarjuna Kristam <&tegra_car TEGRA210_CLK_XUSB_SS>, 1301e74db5a5SNagarjuna Kristam <&tegra_car TEGRA210_CLK_XUSB_SSP_SRC>, 1302e74db5a5SNagarjuna Kristam <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>, 1303e74db5a5SNagarjuna Kristam <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>; 1304e74db5a5SNagarjuna Kristam clock-names = "dev", "ss", "ss_src", "fs_src", "hs_src"; 1305e74db5a5SNagarjuna Kristam power-domains = <&pd_xusbdev>, <&pd_xusbss>; 1306e74db5a5SNagarjuna Kristam power-domain-names = "dev", "ss"; 1307e74db5a5SNagarjuna Kristam nvidia,xusb-padctl = <&padctl>; 1308e74db5a5SNagarjuna Kristam status = "disabled"; 1309e74db5a5SNagarjuna Kristam }; 1310e74db5a5SNagarjuna Kristam 1311be70771dSThierry Reding mipi: mipi@700e3000 { 1312742af7e7SThierry Reding compatible = "nvidia,tegra210-mipi"; 1313742af7e7SThierry Reding reg = <0x0 0x700e3000 0x0 0x100>; 1314742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_MIPI_CAL>; 1315742af7e7SThierry Reding clock-names = "mipi-cal"; 131696d1f078SJon Hunter power-domains = <&pd_sor>; 1317742af7e7SThierry Reding #nvidia,mipi-calibrate-cells = <1>; 1318742af7e7SThierry Reding }; 1319742af7e7SThierry Reding 13202ceed593SJoseph Lo dfll: clock@70110000 { 13212ceed593SJoseph Lo compatible = "nvidia,tegra210-dfll"; 13222ceed593SJoseph Lo reg = <0 0x70110000 0 0x100>, /* DFLL control */ 13232ceed593SJoseph Lo <0 0x70110000 0 0x100>, /* I2C output control */ 13242ceed593SJoseph Lo <0 0x70110100 0 0x100>, /* Integrated I2C controller */ 13252ceed593SJoseph Lo <0 0x70110200 0 0x100>; /* Look-up table RAM */ 13262ceed593SJoseph Lo interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 13272ceed593SJoseph Lo clocks = <&tegra_car TEGRA210_CLK_DFLL_SOC>, 13282ceed593SJoseph Lo <&tegra_car TEGRA210_CLK_DFLL_REF>, 13292ceed593SJoseph Lo <&tegra_car TEGRA210_CLK_I2C5>; 13302ceed593SJoseph Lo clock-names = "soc", "ref", "i2c"; 13312ceed593SJoseph Lo resets = <&tegra_car TEGRA210_RST_DFLL_DVCO>; 13322ceed593SJoseph Lo reset-names = "dvco"; 13332ceed593SJoseph Lo #clock-cells = <0>; 13342ceed593SJoseph Lo clock-output-names = "dfllCPU_out"; 13352ceed593SJoseph Lo status = "disabled"; 13362ceed593SJoseph Lo }; 13372ceed593SJoseph Lo 13380f133090SJon Hunter aconnect@702c0000 { 13390f133090SJon Hunter compatible = "nvidia,tegra210-aconnect"; 13400f133090SJon Hunter clocks = <&tegra_car TEGRA210_CLK_APE>, 13410f133090SJon Hunter <&tegra_car TEGRA210_CLK_APB2APE>; 13420f133090SJon Hunter clock-names = "ape", "apb2ape"; 13430f133090SJon Hunter power-domains = <&pd_audio>; 13440f133090SJon Hunter #address-cells = <1>; 13450f133090SJon Hunter #size-cells = <1>; 13460f133090SJon Hunter ranges = <0x702c0000 0x0 0x702c0000 0x00040000>; 13470f133090SJon Hunter status = "disabled"; 1348bcdbde43SJon Hunter 1349b6e136c7SSameer Pujar adma: dma-controller@702e2000 { 135019e61213SJon Hunter compatible = "nvidia,tegra210-adma"; 135119e61213SJon Hunter reg = <0x702e2000 0x2000>; 135219e61213SJon Hunter interrupt-parent = <&agic>; 135319e61213SJon Hunter interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 135419e61213SJon Hunter <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 135519e61213SJon Hunter <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 135619e61213SJon Hunter <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 135719e61213SJon Hunter <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 135819e61213SJon Hunter <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 135919e61213SJon Hunter <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 136019e61213SJon Hunter <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 136119e61213SJon Hunter <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 136219e61213SJon Hunter <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 136319e61213SJon Hunter <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 136419e61213SJon Hunter <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 136519e61213SJon Hunter <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 136619e61213SJon Hunter <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 136719e61213SJon Hunter <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 136819e61213SJon Hunter <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 136919e61213SJon Hunter <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 137019e61213SJon Hunter <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 137119e61213SJon Hunter <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 137219e61213SJon Hunter <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 137319e61213SJon Hunter <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 137419e61213SJon Hunter <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 137519e61213SJon Hunter #dma-cells = <1>; 137619e61213SJon Hunter clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>; 137719e61213SJon Hunter clock-names = "d_audio"; 137819e61213SJon Hunter status = "disabled"; 137919e61213SJon Hunter }; 138019e61213SJon Hunter 1381df93557bSThierry Reding agic: interrupt-controller@702f9000 { 1382bcdbde43SJon Hunter compatible = "nvidia,tegra210-agic"; 1383bcdbde43SJon Hunter #interrupt-cells = <3>; 1384bcdbde43SJon Hunter interrupt-controller; 1385ba24eee6SJon Hunter reg = <0x702f9000 0x1000>, 1386bcdbde43SJon Hunter <0x702fa000 0x2000>; 1387bcdbde43SJon Hunter interrupts = <GIC_SPI 102 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1388bcdbde43SJon Hunter clocks = <&tegra_car TEGRA210_CLK_APE>; 1389bcdbde43SJon Hunter clock-names = "clk"; 1390bcdbde43SJon Hunter status = "disabled"; 1391bcdbde43SJon Hunter }; 1392177208f7SSameer Pujar 1393177208f7SSameer Pujar tegra_ahub: ahub@702d0800 { 1394177208f7SSameer Pujar compatible = "nvidia,tegra210-ahub"; 1395177208f7SSameer Pujar reg = <0x702d0800 0x800>; 1396177208f7SSameer Pujar clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>; 1397177208f7SSameer Pujar clock-names = "ahub"; 1398177208f7SSameer Pujar assigned-clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>; 1399177208f7SSameer Pujar assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1400177208f7SSameer Pujar #address-cells = <1>; 1401177208f7SSameer Pujar #size-cells = <1>; 1402177208f7SSameer Pujar ranges = <0x702d0000 0x702d0000 0x0000e400>; 1403177208f7SSameer Pujar status = "disabled"; 1404177208f7SSameer Pujar 1405177208f7SSameer Pujar tegra_admaif: admaif@702d0000 { 1406177208f7SSameer Pujar compatible = "nvidia,tegra210-admaif"; 1407177208f7SSameer Pujar reg = <0x702d0000 0x800>; 1408177208f7SSameer Pujar dmas = <&adma 1>, <&adma 1>, 1409177208f7SSameer Pujar <&adma 2>, <&adma 2>, 1410177208f7SSameer Pujar <&adma 3>, <&adma 3>, 1411177208f7SSameer Pujar <&adma 4>, <&adma 4>, 1412177208f7SSameer Pujar <&adma 5>, <&adma 5>, 1413177208f7SSameer Pujar <&adma 6>, <&adma 6>, 1414177208f7SSameer Pujar <&adma 7>, <&adma 7>, 1415177208f7SSameer Pujar <&adma 8>, <&adma 8>, 1416177208f7SSameer Pujar <&adma 9>, <&adma 9>, 1417177208f7SSameer Pujar <&adma 10>, <&adma 10>; 1418177208f7SSameer Pujar dma-names = "rx1", "tx1", 1419177208f7SSameer Pujar "rx2", "tx2", 1420177208f7SSameer Pujar "rx3", "tx3", 1421177208f7SSameer Pujar "rx4", "tx4", 1422177208f7SSameer Pujar "rx5", "tx5", 1423177208f7SSameer Pujar "rx6", "tx6", 1424177208f7SSameer Pujar "rx7", "tx7", 1425177208f7SSameer Pujar "rx8", "tx8", 1426177208f7SSameer Pujar "rx9", "tx9", 1427177208f7SSameer Pujar "rx10", "tx10"; 1428177208f7SSameer Pujar status = "disabled"; 1429177208f7SSameer Pujar }; 1430177208f7SSameer Pujar 1431177208f7SSameer Pujar tegra_i2s1: i2s@702d1000 { 1432177208f7SSameer Pujar compatible = "nvidia,tegra210-i2s"; 1433177208f7SSameer Pujar reg = <0x702d1000 0x100>; 1434177208f7SSameer Pujar clocks = <&tegra_car TEGRA210_CLK_I2S0>, 1435177208f7SSameer Pujar <&tegra_car TEGRA210_CLK_I2S0_SYNC>; 1436177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 1437177208f7SSameer Pujar assigned-clocks = <&tegra_car TEGRA210_CLK_I2S0>; 1438177208f7SSameer Pujar assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1439177208f7SSameer Pujar assigned-clock-rates = <1536000>; 1440177208f7SSameer Pujar sound-name-prefix = "I2S1"; 1441177208f7SSameer Pujar status = "disabled"; 1442177208f7SSameer Pujar }; 1443177208f7SSameer Pujar 1444177208f7SSameer Pujar tegra_i2s2: i2s@702d1100 { 1445177208f7SSameer Pujar compatible = "nvidia,tegra210-i2s"; 1446177208f7SSameer Pujar reg = <0x702d1100 0x100>; 1447177208f7SSameer Pujar clocks = <&tegra_car TEGRA210_CLK_I2S1>, 1448177208f7SSameer Pujar <&tegra_car TEGRA210_CLK_I2S1_SYNC>; 1449177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 1450177208f7SSameer Pujar assigned-clocks = <&tegra_car TEGRA210_CLK_I2S1>; 1451177208f7SSameer Pujar assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1452177208f7SSameer Pujar assigned-clock-rates = <1536000>; 1453177208f7SSameer Pujar sound-name-prefix = "I2S2"; 1454177208f7SSameer Pujar status = "disabled"; 1455177208f7SSameer Pujar }; 1456177208f7SSameer Pujar 1457177208f7SSameer Pujar tegra_i2s3: i2s@702d1200 { 1458177208f7SSameer Pujar compatible = "nvidia,tegra210-i2s"; 1459177208f7SSameer Pujar reg = <0x702d1200 0x100>; 1460177208f7SSameer Pujar clocks = <&tegra_car TEGRA210_CLK_I2S2>, 1461177208f7SSameer Pujar <&tegra_car TEGRA210_CLK_I2S2_SYNC>; 1462177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 1463177208f7SSameer Pujar assigned-clocks = <&tegra_car TEGRA210_CLK_I2S2>; 1464177208f7SSameer Pujar assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1465177208f7SSameer Pujar assigned-clock-rates = <1536000>; 1466177208f7SSameer Pujar sound-name-prefix = "I2S3"; 1467177208f7SSameer Pujar status = "disabled"; 1468177208f7SSameer Pujar }; 1469177208f7SSameer Pujar 1470177208f7SSameer Pujar tegra_i2s4: i2s@702d1300 { 1471177208f7SSameer Pujar compatible = "nvidia,tegra210-i2s"; 1472177208f7SSameer Pujar reg = <0x702d1300 0x100>; 1473177208f7SSameer Pujar clocks = <&tegra_car TEGRA210_CLK_I2S3>, 1474177208f7SSameer Pujar <&tegra_car TEGRA210_CLK_I2S3_SYNC>; 1475177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 1476177208f7SSameer Pujar assigned-clocks = <&tegra_car TEGRA210_CLK_I2S3>; 1477177208f7SSameer Pujar assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1478177208f7SSameer Pujar assigned-clock-rates = <1536000>; 1479177208f7SSameer Pujar sound-name-prefix = "I2S4"; 1480177208f7SSameer Pujar status = "disabled"; 1481177208f7SSameer Pujar }; 1482177208f7SSameer Pujar 1483177208f7SSameer Pujar tegra_i2s5: i2s@702d1400 { 1484177208f7SSameer Pujar compatible = "nvidia,tegra210-i2s"; 1485177208f7SSameer Pujar reg = <0x702d1400 0x100>; 1486177208f7SSameer Pujar clocks = <&tegra_car TEGRA210_CLK_I2S4>, 1487177208f7SSameer Pujar <&tegra_car TEGRA210_CLK_I2S4_SYNC>; 1488177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 1489177208f7SSameer Pujar assigned-clocks = <&tegra_car TEGRA210_CLK_I2S4>; 1490177208f7SSameer Pujar assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1491177208f7SSameer Pujar assigned-clock-rates = <1536000>; 1492177208f7SSameer Pujar sound-name-prefix = "I2S5"; 1493177208f7SSameer Pujar status = "disabled"; 1494177208f7SSameer Pujar }; 1495177208f7SSameer Pujar 1496177208f7SSameer Pujar tegra_dmic1: dmic@702d4000 { 1497177208f7SSameer Pujar compatible = "nvidia,tegra210-dmic"; 1498177208f7SSameer Pujar reg = <0x702d4000 0x100>; 1499177208f7SSameer Pujar clocks = <&tegra_car TEGRA210_CLK_DMIC1>; 1500177208f7SSameer Pujar clock-names = "dmic"; 1501177208f7SSameer Pujar assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC1>; 1502177208f7SSameer Pujar assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1503177208f7SSameer Pujar assigned-clock-rates = <3072000>; 1504177208f7SSameer Pujar sound-name-prefix = "DMIC1"; 1505177208f7SSameer Pujar status = "disabled"; 1506177208f7SSameer Pujar }; 1507177208f7SSameer Pujar 1508177208f7SSameer Pujar tegra_dmic2: dmic@702d4100 { 1509177208f7SSameer Pujar compatible = "nvidia,tegra210-dmic"; 1510177208f7SSameer Pujar reg = <0x702d4100 0x100>; 1511177208f7SSameer Pujar clocks = <&tegra_car TEGRA210_CLK_DMIC2>; 1512177208f7SSameer Pujar clock-names = "dmic"; 1513177208f7SSameer Pujar assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC2>; 1514177208f7SSameer Pujar assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1515177208f7SSameer Pujar assigned-clock-rates = <3072000>; 1516177208f7SSameer Pujar sound-name-prefix = "DMIC2"; 1517177208f7SSameer Pujar status = "disabled"; 1518177208f7SSameer Pujar }; 1519177208f7SSameer Pujar 1520177208f7SSameer Pujar tegra_dmic3: dmic@702d4200 { 1521177208f7SSameer Pujar compatible = "nvidia,tegra210-dmic"; 1522177208f7SSameer Pujar reg = <0x702d4200 0x100>; 1523177208f7SSameer Pujar clocks = <&tegra_car TEGRA210_CLK_DMIC3>; 1524177208f7SSameer Pujar clock-names = "dmic"; 1525177208f7SSameer Pujar assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC3>; 1526177208f7SSameer Pujar assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1527177208f7SSameer Pujar assigned-clock-rates = <3072000>; 1528177208f7SSameer Pujar sound-name-prefix = "DMIC3"; 1529177208f7SSameer Pujar status = "disabled"; 1530177208f7SSameer Pujar }; 1531177208f7SSameer Pujar }; 15320f133090SJon Hunter }; 15330f133090SJon Hunter 1534be70771dSThierry Reding spi@70410000 { 1535742af7e7SThierry Reding compatible = "nvidia,tegra210-qspi"; 1536742af7e7SThierry Reding reg = <0x0 0x70410000 0x0 0x1000>; 1537742af7e7SThierry Reding interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1538742af7e7SThierry Reding #address-cells = <1>; 1539742af7e7SThierry Reding #size-cells = <0>; 1540742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_QSPI>; 1541742af7e7SThierry Reding clock-names = "qspi"; 1542742af7e7SThierry Reding resets = <&tegra_car 211>; 1543742af7e7SThierry Reding reset-names = "qspi"; 1544742af7e7SThierry Reding dmas = <&apbdma 5>, <&apbdma 5>; 1545742af7e7SThierry Reding dma-names = "rx", "tx"; 1546742af7e7SThierry Reding status = "disabled"; 1547742af7e7SThierry Reding }; 1548742af7e7SThierry Reding 1549be70771dSThierry Reding usb@7d000000 { 1550742af7e7SThierry Reding compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 1551742af7e7SThierry Reding reg = <0x0 0x7d000000 0x0 0x4000>; 1552742af7e7SThierry Reding interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1553742af7e7SThierry Reding phy_type = "utmi"; 1554742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_USBD>; 1555742af7e7SThierry Reding clock-names = "usb"; 1556742af7e7SThierry Reding resets = <&tegra_car 22>; 1557742af7e7SThierry Reding reset-names = "usb"; 1558742af7e7SThierry Reding nvidia,phy = <&phy1>; 1559742af7e7SThierry Reding status = "disabled"; 1560742af7e7SThierry Reding }; 1561742af7e7SThierry Reding 1562be70771dSThierry Reding phy1: usb-phy@7d000000 { 1563742af7e7SThierry Reding compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; 1564742af7e7SThierry Reding reg = <0x0 0x7d000000 0x0 0x4000>, 1565742af7e7SThierry Reding <0x0 0x7d000000 0x0 0x4000>; 1566742af7e7SThierry Reding phy_type = "utmi"; 1567742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_USBD>, 1568742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_PLL_U>, 1569742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_USBD>; 1570742af7e7SThierry Reding clock-names = "reg", "pll_u", "utmi-pads"; 1571742af7e7SThierry Reding resets = <&tegra_car 22>, <&tegra_car 22>; 1572742af7e7SThierry Reding reset-names = "usb", "utmi-pads"; 1573742af7e7SThierry Reding nvidia,hssync-start-delay = <0>; 1574742af7e7SThierry Reding nvidia,idle-wait-delay = <17>; 1575742af7e7SThierry Reding nvidia,elastic-limit = <16>; 1576742af7e7SThierry Reding nvidia,term-range-adj = <6>; 1577742af7e7SThierry Reding nvidia,xcvr-setup = <9>; 1578742af7e7SThierry Reding nvidia,xcvr-lsfslew = <0>; 1579742af7e7SThierry Reding nvidia,xcvr-lsrslew = <3>; 1580742af7e7SThierry Reding nvidia,hssquelch-level = <2>; 1581742af7e7SThierry Reding nvidia,hsdiscon-level = <5>; 1582742af7e7SThierry Reding nvidia,xcvr-hsslew = <12>; 1583742af7e7SThierry Reding nvidia,has-utmi-pad-registers; 1584742af7e7SThierry Reding status = "disabled"; 1585742af7e7SThierry Reding }; 1586742af7e7SThierry Reding 1587be70771dSThierry Reding usb@7d004000 { 1588742af7e7SThierry Reding compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 1589742af7e7SThierry Reding reg = <0x0 0x7d004000 0x0 0x4000>; 1590742af7e7SThierry Reding interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1591742af7e7SThierry Reding phy_type = "utmi"; 1592742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_USB2>; 1593742af7e7SThierry Reding clock-names = "usb"; 1594742af7e7SThierry Reding resets = <&tegra_car 58>; 1595742af7e7SThierry Reding reset-names = "usb"; 1596742af7e7SThierry Reding nvidia,phy = <&phy2>; 1597742af7e7SThierry Reding status = "disabled"; 1598742af7e7SThierry Reding }; 1599742af7e7SThierry Reding 1600be70771dSThierry Reding phy2: usb-phy@7d004000 { 1601742af7e7SThierry Reding compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; 1602742af7e7SThierry Reding reg = <0x0 0x7d004000 0x0 0x4000>, 1603742af7e7SThierry Reding <0x0 0x7d000000 0x0 0x4000>; 1604742af7e7SThierry Reding phy_type = "utmi"; 1605742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_USB2>, 1606742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_PLL_U>, 1607742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_USBD>; 1608742af7e7SThierry Reding clock-names = "reg", "pll_u", "utmi-pads"; 1609742af7e7SThierry Reding resets = <&tegra_car 58>, <&tegra_car 22>; 1610742af7e7SThierry Reding reset-names = "usb", "utmi-pads"; 1611742af7e7SThierry Reding nvidia,hssync-start-delay = <0>; 1612742af7e7SThierry Reding nvidia,idle-wait-delay = <17>; 1613742af7e7SThierry Reding nvidia,elastic-limit = <16>; 1614742af7e7SThierry Reding nvidia,term-range-adj = <6>; 1615742af7e7SThierry Reding nvidia,xcvr-setup = <9>; 1616742af7e7SThierry Reding nvidia,xcvr-lsfslew = <0>; 1617742af7e7SThierry Reding nvidia,xcvr-lsrslew = <3>; 1618742af7e7SThierry Reding nvidia,hssquelch-level = <2>; 1619742af7e7SThierry Reding nvidia,hsdiscon-level = <5>; 1620742af7e7SThierry Reding nvidia,xcvr-hsslew = <12>; 1621742af7e7SThierry Reding status = "disabled"; 1622742af7e7SThierry Reding }; 1623742af7e7SThierry Reding 1624742af7e7SThierry Reding cpus { 1625742af7e7SThierry Reding #address-cells = <1>; 1626742af7e7SThierry Reding #size-cells = <0>; 1627742af7e7SThierry Reding 1628742af7e7SThierry Reding cpu@0 { 1629742af7e7SThierry Reding device_type = "cpu"; 1630742af7e7SThierry Reding compatible = "arm,cortex-a57"; 1631742af7e7SThierry Reding reg = <0>; 163243b9b402SJoseph Lo clocks = <&tegra_car TEGRA210_CLK_CCLK_G>, 163343b9b402SJoseph Lo <&tegra_car TEGRA210_CLK_PLL_X>, 163443b9b402SJoseph Lo <&tegra_car TEGRA210_CLK_PLL_P_OUT4>, 163543b9b402SJoseph Lo <&dfll>; 163643b9b402SJoseph Lo clock-names = "cpu_g", "pll_x", "pll_p", "dfll"; 163743b9b402SJoseph Lo clock-latency = <300000>; 1638da77c6d9SJoseph Lo cpu-idle-states = <&CPU_SLEEP>; 16396c00cac1SJoseph Lo next-level-cache = <&L2>; 1640742af7e7SThierry Reding }; 1641742af7e7SThierry Reding 1642742af7e7SThierry Reding cpu@1 { 1643742af7e7SThierry Reding device_type = "cpu"; 1644742af7e7SThierry Reding compatible = "arm,cortex-a57"; 1645742af7e7SThierry Reding reg = <1>; 1646da77c6d9SJoseph Lo cpu-idle-states = <&CPU_SLEEP>; 16476c00cac1SJoseph Lo next-level-cache = <&L2>; 1648742af7e7SThierry Reding }; 1649742af7e7SThierry Reding 1650742af7e7SThierry Reding cpu@2 { 1651742af7e7SThierry Reding device_type = "cpu"; 1652742af7e7SThierry Reding compatible = "arm,cortex-a57"; 1653742af7e7SThierry Reding reg = <2>; 1654da77c6d9SJoseph Lo cpu-idle-states = <&CPU_SLEEP>; 16556c00cac1SJoseph Lo next-level-cache = <&L2>; 1656742af7e7SThierry Reding }; 1657742af7e7SThierry Reding 1658742af7e7SThierry Reding cpu@3 { 1659742af7e7SThierry Reding device_type = "cpu"; 1660742af7e7SThierry Reding compatible = "arm,cortex-a57"; 1661742af7e7SThierry Reding reg = <3>; 1662da77c6d9SJoseph Lo cpu-idle-states = <&CPU_SLEEP>; 16636c00cac1SJoseph Lo next-level-cache = <&L2>; 1664da77c6d9SJoseph Lo }; 1665da77c6d9SJoseph Lo 1666da77c6d9SJoseph Lo idle-states { 1667da77c6d9SJoseph Lo entry-method = "psci"; 1668da77c6d9SJoseph Lo 1669da77c6d9SJoseph Lo CPU_SLEEP: cpu-sleep { 1670da77c6d9SJoseph Lo compatible = "arm,idle-state"; 1671da77c6d9SJoseph Lo arm,psci-suspend-param = <0x40000007>; 1672da77c6d9SJoseph Lo entry-latency-us = <100>; 1673da77c6d9SJoseph Lo exit-latency-us = <30>; 1674da77c6d9SJoseph Lo min-residency-us = <1000>; 1675da77c6d9SJoseph Lo wakeup-latency-us = <130>; 1676da77c6d9SJoseph Lo idle-state-name = "cpu-sleep"; 1677da77c6d9SJoseph Lo status = "disabled"; 1678da77c6d9SJoseph Lo }; 1679742af7e7SThierry Reding }; 16806c00cac1SJoseph Lo 16816c00cac1SJoseph Lo L2: l2-cache { 16826c00cac1SJoseph Lo compatible = "cache"; 16836c00cac1SJoseph Lo }; 1684742af7e7SThierry Reding }; 1685742af7e7SThierry Reding 1686264064abSThierry Reding pmu { 1687264064abSThierry Reding compatible = "arm,armv8-pmuv3"; 1688264064abSThierry Reding interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1689264064abSThierry Reding <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1690264064abSThierry Reding <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1691264064abSThierry Reding <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 1692264064abSThierry Reding interrupt-affinity = <&{/cpus/cpu@0} &{/cpus/cpu@1} 1693264064abSThierry Reding &{/cpus/cpu@2} &{/cpus/cpu@3}>; 1694264064abSThierry Reding }; 1695264064abSThierry Reding 1696742af7e7SThierry Reding timer { 1697742af7e7SThierry Reding compatible = "arm,armv8-timer"; 1698742af7e7SThierry Reding interrupts = <GIC_PPI 13 1699742af7e7SThierry Reding (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1700742af7e7SThierry Reding <GIC_PPI 14 1701742af7e7SThierry Reding (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1702742af7e7SThierry Reding <GIC_PPI 11 1703742af7e7SThierry Reding (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1704742af7e7SThierry Reding <GIC_PPI 10 1705742af7e7SThierry Reding (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1706742af7e7SThierry Reding interrupt-parent = <&gic>; 17076b9e263bSThierry Reding arm,no-tick-in-suspend; 1708742af7e7SThierry Reding }; 1709e2bed1ebSWei Ni 1710e2bed1ebSWei Ni soctherm: thermal-sensor@700e2000 { 1711e2bed1ebSWei Ni compatible = "nvidia,tegra210-soctherm"; 1712644c569dSThierry Reding reg = <0x0 0x700e2000 0x0 0x600>, /* SOC_THERM reg_base */ 1713644c569dSThierry Reding <0x0 0x60006000 0x0 0x400>; /* CAR reg_base */ 1714cbd0f000SWei Ni reg-names = "soctherm-reg", "car-reg"; 171544ff822cSThierry Reding interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 171644ff822cSThierry Reding <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 171744ff822cSThierry Reding interrupt-names = "thermal", "edp"; 1718e2bed1ebSWei Ni clocks = <&tegra_car TEGRA210_CLK_TSENSOR>, 1719e2bed1ebSWei Ni <&tegra_car TEGRA210_CLK_SOC_THERM>; 1720e2bed1ebSWei Ni clock-names = "tsensor", "soctherm"; 1721e2bed1ebSWei Ni resets = <&tegra_car 78>; 1722e2bed1ebSWei Ni reset-names = "soctherm"; 1723e2bed1ebSWei Ni #thermal-sensor-cells = <1>; 1724cbd0f000SWei Ni 1725cbd0f000SWei Ni throttle-cfgs { 1726cbd0f000SWei Ni throttle_heavy: heavy { 1727cbd0f000SWei Ni nvidia,priority = <100>; 1728cbd0f000SWei Ni nvidia,cpu-throt-percent = <85>; 17293146cd55SNicolas Chauvet nvidia,gpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_HIGH>; 1730cbd0f000SWei Ni 1731cbd0f000SWei Ni #cooling-cells = <2>; 1732cbd0f000SWei Ni }; 1733cbd0f000SWei Ni }; 1734e2bed1ebSWei Ni }; 1735e2bed1ebSWei Ni 1736e2bed1ebSWei Ni thermal-zones { 1737e2bed1ebSWei Ni cpu { 1738e2bed1ebSWei Ni polling-delay-passive = <1000>; 1739e2bed1ebSWei Ni polling-delay = <0>; 1740e2bed1ebSWei Ni 1741e2bed1ebSWei Ni thermal-sensors = 1742e2bed1ebSWei Ni <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; 17435e03f663SWei Ni 17445e03f663SWei Ni trips { 17455e03f663SWei Ni cpu-shutdown-trip { 17465e03f663SWei Ni temperature = <102500>; 17475e03f663SWei Ni hysteresis = <0>; 17485e03f663SWei Ni type = "critical"; 17495e03f663SWei Ni }; 1750cbd0f000SWei Ni 1751cbd0f000SWei Ni cpu_throttle_trip: throttle-trip { 1752cbd0f000SWei Ni temperature = <98500>; 1753cbd0f000SWei Ni hysteresis = <1000>; 1754cbd0f000SWei Ni type = "hot"; 1755cbd0f000SWei Ni }; 17565e03f663SWei Ni }; 17575e03f663SWei Ni 17585e03f663SWei Ni cooling-maps { 1759cbd0f000SWei Ni map0 { 1760cbd0f000SWei Ni trip = <&cpu_throttle_trip>; 1761cbd0f000SWei Ni cooling-device = <&throttle_heavy 1 1>; 1762cbd0f000SWei Ni }; 17635e03f663SWei Ni }; 1764e2bed1ebSWei Ni }; 176524fc3363SThierry Reding 1766e2bed1ebSWei Ni mem { 1767e2bed1ebSWei Ni polling-delay-passive = <0>; 1768e2bed1ebSWei Ni polling-delay = <0>; 1769e2bed1ebSWei Ni 1770e2bed1ebSWei Ni thermal-sensors = 1771e2bed1ebSWei Ni <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>; 17725e03f663SWei Ni 17735e03f663SWei Ni trips { 1774e12325f6SThierry Reding dram_nominal: mem-nominal-trip { 1775e12325f6SThierry Reding temperature = <50000>; 1776e12325f6SThierry Reding hysteresis = <1000>; 1777e12325f6SThierry Reding type = "passive"; 1778e12325f6SThierry Reding }; 1779e12325f6SThierry Reding 1780e12325f6SThierry Reding dram_throttle: mem-throttle-trip { 1781e12325f6SThierry Reding temperature = <70000>; 1782e12325f6SThierry Reding hysteresis = <1000>; 1783e12325f6SThierry Reding type = "active"; 1784e12325f6SThierry Reding }; 1785e12325f6SThierry Reding 1786fdf27825SNicolas Chauvet mem-hot-trip { 1787fdf27825SNicolas Chauvet temperature = <100000>; 1788fdf27825SNicolas Chauvet hysteresis = <1000>; 1789fdf27825SNicolas Chauvet type = "hot"; 1790fdf27825SNicolas Chauvet }; 1791fdf27825SNicolas Chauvet 17925e03f663SWei Ni mem-shutdown-trip { 17935e03f663SWei Ni temperature = <103000>; 17945e03f663SWei Ni hysteresis = <0>; 17955e03f663SWei Ni type = "critical"; 17965e03f663SWei Ni }; 17975e03f663SWei Ni }; 17985e03f663SWei Ni 17995e03f663SWei Ni cooling-maps { 1800e12325f6SThierry Reding dram-passive { 1801e12325f6SThierry Reding cooling-device = <&emc 0 0>; 1802e12325f6SThierry Reding trip = <&dram_nominal>; 1803e12325f6SThierry Reding }; 1804e12325f6SThierry Reding 1805e12325f6SThierry Reding dram-active { 1806e12325f6SThierry Reding cooling-device = <&emc 1 1>; 1807e12325f6SThierry Reding trip = <&dram_throttle>; 1808e12325f6SThierry Reding }; 18095e03f663SWei Ni }; 1810e2bed1ebSWei Ni }; 181124fc3363SThierry Reding 1812e2bed1ebSWei Ni gpu { 1813e2bed1ebSWei Ni polling-delay-passive = <1000>; 1814e2bed1ebSWei Ni polling-delay = <0>; 1815e2bed1ebSWei Ni 1816e2bed1ebSWei Ni thermal-sensors = 1817e2bed1ebSWei Ni <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>; 18185e03f663SWei Ni 18195e03f663SWei Ni trips { 18205e03f663SWei Ni gpu-shutdown-trip { 18215e03f663SWei Ni temperature = <103000>; 18225e03f663SWei Ni hysteresis = <0>; 18235e03f663SWei Ni type = "critical"; 18245e03f663SWei Ni }; 1825cbd0f000SWei Ni 1826cbd0f000SWei Ni gpu_throttle_trip: throttle-trip { 1827cbd0f000SWei Ni temperature = <100000>; 1828cbd0f000SWei Ni hysteresis = <1000>; 1829cbd0f000SWei Ni type = "hot"; 1830cbd0f000SWei Ni }; 18315e03f663SWei Ni }; 18325e03f663SWei Ni 18335e03f663SWei Ni cooling-maps { 1834cbd0f000SWei Ni map0 { 1835cbd0f000SWei Ni trip = <&gpu_throttle_trip>; 1836cbd0f000SWei Ni cooling-device = <&throttle_heavy 1 1>; 1837cbd0f000SWei Ni }; 18385e03f663SWei Ni }; 1839e2bed1ebSWei Ni }; 184024fc3363SThierry Reding 1841e2bed1ebSWei Ni pllx { 1842e2bed1ebSWei Ni polling-delay-passive = <0>; 1843e2bed1ebSWei Ni polling-delay = <0>; 1844e2bed1ebSWei Ni 1845e2bed1ebSWei Ni thermal-sensors = 1846e2bed1ebSWei Ni <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>; 18475e03f663SWei Ni 18485e03f663SWei Ni trips { 18495e03f663SWei Ni pllx-shutdown-trip { 18505e03f663SWei Ni temperature = <103000>; 18515e03f663SWei Ni hysteresis = <0>; 18525e03f663SWei Ni type = "critical"; 18535e03f663SWei Ni }; 1854fdf27825SNicolas Chauvet 1855fdf27825SNicolas Chauvet pllx-throttle-trip { 1856fdf27825SNicolas Chauvet temperature = <100000>; 1857fdf27825SNicolas Chauvet hysteresis = <1000>; 1858fdf27825SNicolas Chauvet type = "hot"; 1859fdf27825SNicolas Chauvet }; 18605e03f663SWei Ni }; 18615e03f663SWei Ni 18625e03f663SWei Ni cooling-maps { 18635e03f663SWei Ni /* 18645e03f663SWei Ni * There are currently no cooling maps, 18655e03f663SWei Ni * because there are no cooling devices. 18665e03f663SWei Ni */ 18675e03f663SWei Ni }; 1868e2bed1ebSWei Ni }; 1869e2bed1ebSWei Ni }; 1870742af7e7SThierry Reding}; 1871