1b2441318SGreg Kroah-Hartman// SPDX-License-Identifier: GPL-2.0 2742af7e7SThierry Reding#include <dt-bindings/clock/tegra210-car.h> 3742af7e7SThierry Reding#include <dt-bindings/gpio/tegra-gpio.h> 4742af7e7SThierry Reding#include <dt-bindings/memory/tegra210-mc.h> 5742af7e7SThierry Reding#include <dt-bindings/pinctrl/pinctrl-tegra.h> 66641af7eSAapo Vienamo#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 72ceed593SJoseph Lo#include <dt-bindings/reset/tegra210-car.h> 8742af7e7SThierry Reding#include <dt-bindings/interrupt-controller/arm-gic.h> 9e2bed1ebSWei Ni#include <dt-bindings/thermal/tegra124-soctherm.h> 10359ae651SSowjanya Komatineni#include <dt-bindings/soc/tegra-pmc.h> 11742af7e7SThierry Reding 12742af7e7SThierry Reding/ { 13742af7e7SThierry Reding compatible = "nvidia,tegra210"; 14742af7e7SThierry Reding interrupt-parent = <&lic>; 15742af7e7SThierry Reding #address-cells = <2>; 16742af7e7SThierry Reding #size-cells = <2>; 17742af7e7SThierry Reding 18475d99fcSRob Herring pcie@1003000 { 19589a2d3fSThierry Reding compatible = "nvidia,tegra210-pcie"; 20589a2d3fSThierry Reding device_type = "pci"; 21644c569dSThierry Reding reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */ 22644c569dSThierry Reding <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */ 23644c569dSThierry Reding <0x0 0x02000000 0x0 0x10000000>; /* configuration space */ 24589a2d3fSThierry Reding reg-names = "pads", "afi", "cs"; 25589a2d3fSThierry Reding interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 26589a2d3fSThierry Reding <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 27589a2d3fSThierry Reding interrupt-names = "intr", "msi"; 28589a2d3fSThierry Reding 29589a2d3fSThierry Reding #interrupt-cells = <1>; 30589a2d3fSThierry Reding interrupt-map-mask = <0 0 0 0>; 31589a2d3fSThierry Reding interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 32589a2d3fSThierry Reding 33589a2d3fSThierry Reding bus-range = <0x00 0xff>; 34589a2d3fSThierry Reding #address-cells = <3>; 35589a2d3fSThierry Reding #size-cells = <2>; 36589a2d3fSThierry Reding 37644c569dSThierry Reding ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */ 38644c569dSThierry Reding <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */ 39644c569dSThierry Reding <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */ 40644c569dSThierry Reding <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */ 41644c569dSThierry Reding <0x42000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ 42589a2d3fSThierry Reding 43589a2d3fSThierry Reding clocks = <&tegra_car TEGRA210_CLK_PCIE>, 44589a2d3fSThierry Reding <&tegra_car TEGRA210_CLK_AFI>, 45589a2d3fSThierry Reding <&tegra_car TEGRA210_CLK_PLL_E>, 46589a2d3fSThierry Reding <&tegra_car TEGRA210_CLK_CML0>; 47589a2d3fSThierry Reding clock-names = "pex", "afi", "pll_e", "cml"; 48589a2d3fSThierry Reding resets = <&tegra_car 70>, 49589a2d3fSThierry Reding <&tegra_car 72>, 50589a2d3fSThierry Reding <&tegra_car 74>; 51589a2d3fSThierry Reding reset-names = "pex", "afi", "pcie_x"; 52871be845SManikanta Maddireddy 53871be845SManikanta Maddireddy pinctrl-names = "default", "idle"; 54871be845SManikanta Maddireddy pinctrl-0 = <&pex_dpd_disable>; 55871be845SManikanta Maddireddy pinctrl-1 = <&pex_dpd_enable>; 56871be845SManikanta Maddireddy 57589a2d3fSThierry Reding status = "disabled"; 58589a2d3fSThierry Reding 59589a2d3fSThierry Reding pci@1,0 { 60589a2d3fSThierry Reding device_type = "pci"; 61589a2d3fSThierry Reding assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>; 62589a2d3fSThierry Reding reg = <0x000800 0 0 0 0>; 63475d99fcSRob Herring bus-range = <0x00 0xff>; 64589a2d3fSThierry Reding status = "disabled"; 65589a2d3fSThierry Reding 66589a2d3fSThierry Reding #address-cells = <3>; 67589a2d3fSThierry Reding #size-cells = <2>; 68589a2d3fSThierry Reding ranges; 69589a2d3fSThierry Reding 70589a2d3fSThierry Reding nvidia,num-lanes = <4>; 71589a2d3fSThierry Reding }; 72589a2d3fSThierry Reding 73589a2d3fSThierry Reding pci@2,0 { 74589a2d3fSThierry Reding device_type = "pci"; 75589a2d3fSThierry Reding assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>; 76589a2d3fSThierry Reding reg = <0x001000 0 0 0 0>; 77475d99fcSRob Herring bus-range = <0x00 0xff>; 78589a2d3fSThierry Reding status = "disabled"; 79589a2d3fSThierry Reding 80589a2d3fSThierry Reding #address-cells = <3>; 81589a2d3fSThierry Reding #size-cells = <2>; 82589a2d3fSThierry Reding ranges; 83589a2d3fSThierry Reding 84589a2d3fSThierry Reding nvidia,num-lanes = <1>; 85589a2d3fSThierry Reding }; 86589a2d3fSThierry Reding }; 87589a2d3fSThierry Reding 88be70771dSThierry Reding host1x@50000000 { 89ef126bc4SThierry Reding compatible = "nvidia,tegra210-host1x"; 90742af7e7SThierry Reding reg = <0x0 0x50000000 0x0 0x00034000>; 91742af7e7SThierry Reding interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 92742af7e7SThierry Reding <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ 93052d3f65SThierry Reding interrupt-names = "syncpt", "host1x"; 94742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_HOST1X>; 95742af7e7SThierry Reding clock-names = "host1x"; 96742af7e7SThierry Reding resets = <&tegra_car 28>; 97742af7e7SThierry Reding reset-names = "host1x"; 98742af7e7SThierry Reding 99742af7e7SThierry Reding #address-cells = <2>; 100742af7e7SThierry Reding #size-cells = <2>; 101742af7e7SThierry Reding 102742af7e7SThierry Reding ranges = <0x0 0x54000000 0x0 0x54000000 0x0 0x01000000>; 103742af7e7SThierry Reding 104116503a6SMikko Perttunen iommus = <&mc TEGRA_SWGROUP_HC>; 105116503a6SMikko Perttunen 106be70771dSThierry Reding dpaux1: dpaux@54040000 { 107742af7e7SThierry Reding compatible = "nvidia,tegra210-dpaux"; 108742af7e7SThierry Reding reg = <0x0 0x54040000 0x0 0x00040000>; 109742af7e7SThierry Reding interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 110742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_DPAUX1>, 111742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_PLL_DP>; 112742af7e7SThierry Reding clock-names = "dpaux", "parent"; 113742af7e7SThierry Reding resets = <&tegra_car 207>; 114742af7e7SThierry Reding reset-names = "dpaux"; 11596d1f078SJon Hunter power-domains = <&pd_sor>; 116742af7e7SThierry Reding status = "disabled"; 11766b2d6e9SJon Hunter 11866b2d6e9SJon Hunter state_dpaux1_aux: pinmux-aux { 11966b2d6e9SJon Hunter groups = "dpaux-io"; 12066b2d6e9SJon Hunter function = "aux"; 12166b2d6e9SJon Hunter }; 12266b2d6e9SJon Hunter 12366b2d6e9SJon Hunter state_dpaux1_i2c: pinmux-i2c { 12466b2d6e9SJon Hunter groups = "dpaux-io"; 12566b2d6e9SJon Hunter function = "i2c"; 12666b2d6e9SJon Hunter }; 12766b2d6e9SJon Hunter 12866b2d6e9SJon Hunter state_dpaux1_off: pinmux-off { 12966b2d6e9SJon Hunter groups = "dpaux-io"; 13066b2d6e9SJon Hunter function = "off"; 13166b2d6e9SJon Hunter }; 13266b2d6e9SJon Hunter 13366b2d6e9SJon Hunter i2c-bus { 13466b2d6e9SJon Hunter #address-cells = <1>; 13566b2d6e9SJon Hunter #size-cells = <0>; 13666b2d6e9SJon Hunter }; 137742af7e7SThierry Reding }; 138742af7e7SThierry Reding 139be70771dSThierry Reding vi@54080000 { 140742af7e7SThierry Reding compatible = "nvidia,tegra210-vi"; 141c4153885SSowjanya Komatineni reg = <0x0 0x54080000 0x0 0x700>; 142742af7e7SThierry Reding interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 143742af7e7SThierry Reding status = "disabled"; 144c4153885SSowjanya Komatineni assigned-clocks = <&tegra_car TEGRA210_CLK_VI>; 145c4153885SSowjanya Komatineni assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 146c4153885SSowjanya Komatineni 147c4153885SSowjanya Komatineni clocks = <&tegra_car TEGRA210_CLK_VI>; 148c4153885SSowjanya Komatineni power-domains = <&pd_venc>; 149c4153885SSowjanya Komatineni 150c4153885SSowjanya Komatineni #address-cells = <1>; 151c4153885SSowjanya Komatineni #size-cells = <1>; 152c4153885SSowjanya Komatineni 153c4153885SSowjanya Komatineni ranges = <0x0 0x0 0x54080000 0x2000>; 154c4153885SSowjanya Komatineni 155c4153885SSowjanya Komatineni csi@838 { 156c4153885SSowjanya Komatineni compatible = "nvidia,tegra210-csi"; 157c4153885SSowjanya Komatineni reg = <0x838 0x1300>; 158c4153885SSowjanya Komatineni status = "disabled"; 159c4153885SSowjanya Komatineni assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>, 160c4153885SSowjanya Komatineni <&tegra_car TEGRA210_CLK_CILCD>, 161c4153885SSowjanya Komatineni <&tegra_car TEGRA210_CLK_CILE>, 162c4153885SSowjanya Komatineni <&tegra_car TEGRA210_CLK_CSI_TPG>; 163c4153885SSowjanya Komatineni assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>, 164c4153885SSowjanya Komatineni <&tegra_car TEGRA210_CLK_PLL_P>, 165c4153885SSowjanya Komatineni <&tegra_car TEGRA210_CLK_PLL_P>; 166c4153885SSowjanya Komatineni assigned-clock-rates = <102000000>, 167c4153885SSowjanya Komatineni <102000000>, 168c4153885SSowjanya Komatineni <102000000>, 169c4153885SSowjanya Komatineni <972000000>; 170c4153885SSowjanya Komatineni 171c4153885SSowjanya Komatineni clocks = <&tegra_car TEGRA210_CLK_CSI>, 172c4153885SSowjanya Komatineni <&tegra_car TEGRA210_CLK_CILAB>, 173c4153885SSowjanya Komatineni <&tegra_car TEGRA210_CLK_CILCD>, 174c4153885SSowjanya Komatineni <&tegra_car TEGRA210_CLK_CILE>, 175c4153885SSowjanya Komatineni <&tegra_car TEGRA210_CLK_CSI_TPG>; 176c4153885SSowjanya Komatineni clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg"; 177c4153885SSowjanya Komatineni power-domains = <&pd_sor>; 178c4153885SSowjanya Komatineni }; 179742af7e7SThierry Reding }; 180742af7e7SThierry Reding 181be70771dSThierry Reding tsec@54100000 { 182742af7e7SThierry Reding compatible = "nvidia,tegra210-tsec"; 183742af7e7SThierry Reding reg = <0x0 0x54100000 0x0 0x00040000>; 184742af7e7SThierry Reding }; 185742af7e7SThierry Reding 186be70771dSThierry Reding dc@54200000 { 187742af7e7SThierry Reding compatible = "nvidia,tegra210-dc"; 188742af7e7SThierry Reding reg = <0x0 0x54200000 0x0 0x00040000>; 189742af7e7SThierry Reding interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 190352092b0SThierry Reding clocks = <&tegra_car TEGRA210_CLK_DISP1>; 191352092b0SThierry Reding clock-names = "dc"; 192742af7e7SThierry Reding resets = <&tegra_car 27>; 193742af7e7SThierry Reding reset-names = "dc"; 194742af7e7SThierry Reding 195742af7e7SThierry Reding iommus = <&mc TEGRA_SWGROUP_DC>; 196742af7e7SThierry Reding 197742af7e7SThierry Reding nvidia,head = <0>; 198742af7e7SThierry Reding }; 199742af7e7SThierry Reding 200be70771dSThierry Reding dc@54240000 { 201742af7e7SThierry Reding compatible = "nvidia,tegra210-dc"; 202742af7e7SThierry Reding reg = <0x0 0x54240000 0x0 0x00040000>; 203742af7e7SThierry Reding interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 204352092b0SThierry Reding clocks = <&tegra_car TEGRA210_CLK_DISP2>; 205352092b0SThierry Reding clock-names = "dc"; 206742af7e7SThierry Reding resets = <&tegra_car 26>; 207742af7e7SThierry Reding reset-names = "dc"; 208742af7e7SThierry Reding 209742af7e7SThierry Reding iommus = <&mc TEGRA_SWGROUP_DCB>; 210742af7e7SThierry Reding 211742af7e7SThierry Reding nvidia,head = <1>; 212742af7e7SThierry Reding }; 213742af7e7SThierry Reding 214be70771dSThierry Reding dsi@54300000 { 215742af7e7SThierry Reding compatible = "nvidia,tegra210-dsi"; 216742af7e7SThierry Reding reg = <0x0 0x54300000 0x0 0x00040000>; 217742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_DSIA>, 218742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_DSIALP>, 219742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; 220742af7e7SThierry Reding clock-names = "dsi", "lp", "parent"; 221742af7e7SThierry Reding resets = <&tegra_car 48>; 222742af7e7SThierry Reding reset-names = "dsi"; 22396d1f078SJon Hunter power-domains = <&pd_sor>; 224742af7e7SThierry Reding nvidia,mipi-calibrate = <&mipi 0x0c0>; /* DSIA & DSIB pads */ 225742af7e7SThierry Reding 226742af7e7SThierry Reding status = "disabled"; 227742af7e7SThierry Reding 228742af7e7SThierry Reding #address-cells = <1>; 229742af7e7SThierry Reding #size-cells = <0>; 230742af7e7SThierry Reding }; 231742af7e7SThierry Reding 232be70771dSThierry Reding vic@54340000 { 233742af7e7SThierry Reding compatible = "nvidia,tegra210-vic"; 234742af7e7SThierry Reding reg = <0x0 0x54340000 0x0 0x00040000>; 23524963d1bSMikko Perttunen interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 23624963d1bSMikko Perttunen clocks = <&tegra_car TEGRA210_CLK_VIC03>; 23724963d1bSMikko Perttunen clock-names = "vic"; 23824963d1bSMikko Perttunen resets = <&tegra_car 178>; 23924963d1bSMikko Perttunen reset-names = "vic"; 24024963d1bSMikko Perttunen 24124963d1bSMikko Perttunen iommus = <&mc TEGRA_SWGROUP_VIC>; 24224963d1bSMikko Perttunen power-domains = <&pd_vic>; 243742af7e7SThierry Reding }; 244742af7e7SThierry Reding 245be70771dSThierry Reding nvjpg@54380000 { 246742af7e7SThierry Reding compatible = "nvidia,tegra210-nvjpg"; 247742af7e7SThierry Reding reg = <0x0 0x54380000 0x0 0x00040000>; 248742af7e7SThierry Reding status = "disabled"; 249742af7e7SThierry Reding }; 250742af7e7SThierry Reding 251be70771dSThierry Reding dsi@54400000 { 252742af7e7SThierry Reding compatible = "nvidia,tegra210-dsi"; 253742af7e7SThierry Reding reg = <0x0 0x54400000 0x0 0x00040000>; 254742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_DSIB>, 255742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_DSIBLP>, 256742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; 257742af7e7SThierry Reding clock-names = "dsi", "lp", "parent"; 258742af7e7SThierry Reding resets = <&tegra_car 82>; 259742af7e7SThierry Reding reset-names = "dsi"; 26096d1f078SJon Hunter power-domains = <&pd_sor>; 261742af7e7SThierry Reding nvidia,mipi-calibrate = <&mipi 0x300>; /* DSIC & DSID pads */ 262742af7e7SThierry Reding 263742af7e7SThierry Reding status = "disabled"; 264742af7e7SThierry Reding 265742af7e7SThierry Reding #address-cells = <1>; 266742af7e7SThierry Reding #size-cells = <0>; 267742af7e7SThierry Reding }; 268742af7e7SThierry Reding 269be70771dSThierry Reding nvdec@54480000 { 270742af7e7SThierry Reding compatible = "nvidia,tegra210-nvdec"; 271742af7e7SThierry Reding reg = <0x0 0x54480000 0x0 0x00040000>; 272742af7e7SThierry Reding status = "disabled"; 273742af7e7SThierry Reding }; 274742af7e7SThierry Reding 275be70771dSThierry Reding nvenc@544c0000 { 276742af7e7SThierry Reding compatible = "nvidia,tegra210-nvenc"; 277742af7e7SThierry Reding reg = <0x0 0x544c0000 0x0 0x00040000>; 278742af7e7SThierry Reding status = "disabled"; 279742af7e7SThierry Reding }; 280742af7e7SThierry Reding 281be70771dSThierry Reding tsec@54500000 { 282742af7e7SThierry Reding compatible = "nvidia,tegra210-tsec"; 283742af7e7SThierry Reding reg = <0x0 0x54500000 0x0 0x00040000>; 284742af7e7SThierry Reding status = "disabled"; 285742af7e7SThierry Reding }; 286742af7e7SThierry Reding 287be70771dSThierry Reding sor@54540000 { 288742af7e7SThierry Reding compatible = "nvidia,tegra210-sor"; 289742af7e7SThierry Reding reg = <0x0 0x54540000 0x0 0x00040000>; 290742af7e7SThierry Reding interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 291742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_SOR0>, 292ed93a666SThierry Reding <&tegra_car TEGRA210_CLK_SOR0_OUT>, 293742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_PLL_D_OUT0>, 294742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_PLL_DP>, 295742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_SOR_SAFE>; 296ed93a666SThierry Reding clock-names = "sor", "out", "parent", "dp", "safe"; 297742af7e7SThierry Reding resets = <&tegra_car 182>; 298742af7e7SThierry Reding reset-names = "sor"; 29966b2d6e9SJon Hunter pinctrl-0 = <&state_dpaux_aux>; 30066b2d6e9SJon Hunter pinctrl-1 = <&state_dpaux_i2c>; 30166b2d6e9SJon Hunter pinctrl-2 = <&state_dpaux_off>; 30266b2d6e9SJon Hunter pinctrl-names = "aux", "i2c", "off"; 30396d1f078SJon Hunter power-domains = <&pd_sor>; 304742af7e7SThierry Reding status = "disabled"; 305742af7e7SThierry Reding }; 306742af7e7SThierry Reding 307be70771dSThierry Reding sor@54580000 { 308742af7e7SThierry Reding compatible = "nvidia,tegra210-sor1"; 309742af7e7SThierry Reding reg = <0x0 0x54580000 0x0 0x00040000>; 310742af7e7SThierry Reding interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 311742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_SOR1>, 31250f5b841SThierry Reding <&tegra_car TEGRA210_CLK_SOR1_OUT>, 313742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_PLL_D2_OUT0>, 314742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_PLL_DP>, 315742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_SOR_SAFE>; 31650f5b841SThierry Reding clock-names = "sor", "out", "parent", "dp", "safe"; 317742af7e7SThierry Reding resets = <&tegra_car 183>; 318742af7e7SThierry Reding reset-names = "sor"; 31966b2d6e9SJon Hunter pinctrl-0 = <&state_dpaux1_aux>; 32066b2d6e9SJon Hunter pinctrl-1 = <&state_dpaux1_i2c>; 32166b2d6e9SJon Hunter pinctrl-2 = <&state_dpaux1_off>; 32266b2d6e9SJon Hunter pinctrl-names = "aux", "i2c", "off"; 32396d1f078SJon Hunter power-domains = <&pd_sor>; 324742af7e7SThierry Reding status = "disabled"; 325742af7e7SThierry Reding }; 326742af7e7SThierry Reding 327be70771dSThierry Reding dpaux: dpaux@545c0000 { 328e989992aSThierry Reding compatible = "nvidia,tegra210-dpaux"; 329742af7e7SThierry Reding reg = <0x0 0x545c0000 0x0 0x00040000>; 330742af7e7SThierry Reding interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 331742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_DPAUX>, 332742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_PLL_DP>; 333742af7e7SThierry Reding clock-names = "dpaux", "parent"; 334742af7e7SThierry Reding resets = <&tegra_car 181>; 335742af7e7SThierry Reding reset-names = "dpaux"; 33696d1f078SJon Hunter power-domains = <&pd_sor>; 337742af7e7SThierry Reding status = "disabled"; 33866b2d6e9SJon Hunter 33966b2d6e9SJon Hunter state_dpaux_aux: pinmux-aux { 34066b2d6e9SJon Hunter groups = "dpaux-io"; 34166b2d6e9SJon Hunter function = "aux"; 34266b2d6e9SJon Hunter }; 34366b2d6e9SJon Hunter 34466b2d6e9SJon Hunter state_dpaux_i2c: pinmux-i2c { 34566b2d6e9SJon Hunter groups = "dpaux-io"; 34666b2d6e9SJon Hunter function = "i2c"; 34766b2d6e9SJon Hunter }; 34866b2d6e9SJon Hunter 34966b2d6e9SJon Hunter state_dpaux_off: pinmux-off { 35066b2d6e9SJon Hunter groups = "dpaux-io"; 35166b2d6e9SJon Hunter function = "off"; 35266b2d6e9SJon Hunter }; 35366b2d6e9SJon Hunter 35466b2d6e9SJon Hunter i2c-bus { 35566b2d6e9SJon Hunter #address-cells = <1>; 35666b2d6e9SJon Hunter #size-cells = <0>; 35766b2d6e9SJon Hunter }; 358742af7e7SThierry Reding }; 359742af7e7SThierry Reding 360be70771dSThierry Reding isp@54600000 { 361742af7e7SThierry Reding compatible = "nvidia,tegra210-isp"; 362742af7e7SThierry Reding reg = <0x0 0x54600000 0x0 0x00040000>; 363742af7e7SThierry Reding interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 36497ace1b4SThierry Reding clocks = <&tegra_car TEGRA210_CLK_ISPA>; 36597ace1b4SThierry Reding resets = <&tegra_car 23>; 36697ace1b4SThierry Reding reset-names = "isp"; 367742af7e7SThierry Reding status = "disabled"; 368742af7e7SThierry Reding }; 369742af7e7SThierry Reding 370be70771dSThierry Reding isp@54680000 { 371742af7e7SThierry Reding compatible = "nvidia,tegra210-isp"; 372742af7e7SThierry Reding reg = <0x0 0x54680000 0x0 0x00040000>; 373742af7e7SThierry Reding interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 37497ace1b4SThierry Reding clocks = <&tegra_car TEGRA210_CLK_ISPB>; 37597ace1b4SThierry Reding resets = <&tegra_car 3>; 37697ace1b4SThierry Reding reset-names = "isp"; 377742af7e7SThierry Reding status = "disabled"; 378742af7e7SThierry Reding }; 379742af7e7SThierry Reding 380be70771dSThierry Reding i2c@546c0000 { 381742af7e7SThierry Reding compatible = "nvidia,tegra210-i2c-vi"; 382742af7e7SThierry Reding reg = <0x0 0x546c0000 0x0 0x00040000>; 383742af7e7SThierry Reding interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 384139a390cSSowjanya Komatineni clocks = <&tegra_car TEGRA210_CLK_VI_I2C>, 385139a390cSSowjanya Komatineni <&tegra_car TEGRA210_CLK_I2CSLOW>; 386139a390cSSowjanya Komatineni clock-names = "div-clk", "slow"; 387139a390cSSowjanya Komatineni resets = <&tegra_car 208>; 388139a390cSSowjanya Komatineni reset-names = "i2c"; 389139a390cSSowjanya Komatineni power-domains = <&pd_venc>; 390742af7e7SThierry Reding status = "disabled"; 391742af7e7SThierry Reding }; 392742af7e7SThierry Reding }; 393742af7e7SThierry Reding 394be70771dSThierry Reding gic: interrupt-controller@50041000 { 395742af7e7SThierry Reding compatible = "arm,gic-400"; 396742af7e7SThierry Reding #interrupt-cells = <3>; 397742af7e7SThierry Reding interrupt-controller; 398742af7e7SThierry Reding reg = <0x0 0x50041000 0x0 0x1000>, 399742af7e7SThierry Reding <0x0 0x50042000 0x0 0x2000>, 400742af7e7SThierry Reding <0x0 0x50044000 0x0 0x2000>, 401742af7e7SThierry Reding <0x0 0x50046000 0x0 0x2000>; 402742af7e7SThierry Reding interrupts = <GIC_PPI 9 403742af7e7SThierry Reding (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 404742af7e7SThierry Reding interrupt-parent = <&gic>; 405742af7e7SThierry Reding }; 406742af7e7SThierry Reding 407be70771dSThierry Reding gpu@57000000 { 408742af7e7SThierry Reding compatible = "nvidia,gm20b"; 409742af7e7SThierry Reding reg = <0x0 0x57000000 0x0 0x01000000>, 410742af7e7SThierry Reding <0x0 0x58000000 0x0 0x01000000>; 411742af7e7SThierry Reding interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 412742af7e7SThierry Reding <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 413742af7e7SThierry Reding interrupt-names = "stall", "nonstall"; 414742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_GPU>, 4154a0778e9SAlexandre Courbot <&tegra_car TEGRA210_CLK_PLL_P_OUT5>, 4164a0778e9SAlexandre Courbot <&tegra_car TEGRA210_CLK_PLL_G_REF>; 4174a0778e9SAlexandre Courbot clock-names = "gpu", "pwr", "ref"; 418742af7e7SThierry Reding resets = <&tegra_car 184>; 419742af7e7SThierry Reding reset-names = "gpu"; 42030f949bcSAlexandre Courbot 42130f949bcSAlexandre Courbot iommus = <&mc TEGRA_SWGROUP_GPU>; 42230f949bcSAlexandre Courbot 423742af7e7SThierry Reding status = "disabled"; 424742af7e7SThierry Reding }; 425742af7e7SThierry Reding 426be70771dSThierry Reding lic: interrupt-controller@60004000 { 427742af7e7SThierry Reding compatible = "nvidia,tegra210-ictlr"; 428742af7e7SThierry Reding reg = <0x0 0x60004000 0x0 0x40>, /* primary controller */ 429742af7e7SThierry Reding <0x0 0x60004100 0x0 0x40>, /* secondary controller */ 430742af7e7SThierry Reding <0x0 0x60004200 0x0 0x40>, /* tertiary controller */ 431742af7e7SThierry Reding <0x0 0x60004300 0x0 0x40>, /* quaternary controller */ 432742af7e7SThierry Reding <0x0 0x60004400 0x0 0x40>, /* quinary controller */ 433742af7e7SThierry Reding <0x0 0x60004500 0x0 0x40>; /* senary controller */ 434742af7e7SThierry Reding interrupt-controller; 435742af7e7SThierry Reding #interrupt-cells = <3>; 436742af7e7SThierry Reding interrupt-parent = <&gic>; 437742af7e7SThierry Reding }; 438742af7e7SThierry Reding 439be70771dSThierry Reding timer@60005000 { 440d9931a18SJoseph Lo compatible = "nvidia,tegra210-timer"; 441742af7e7SThierry Reding reg = <0x0 0x60005000 0x0 0x400>; 442d9931a18SJoseph Lo interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 443d9931a18SJoseph Lo <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 444742af7e7SThierry Reding <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 445742af7e7SThierry Reding <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 446742af7e7SThierry Reding <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 447742af7e7SThierry Reding <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 448d9931a18SJoseph Lo <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 449d9931a18SJoseph Lo <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 450d9931a18SJoseph Lo <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 451d9931a18SJoseph Lo <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 452d9931a18SJoseph Lo <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 453d9931a18SJoseph Lo <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 454d9931a18SJoseph Lo <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, 455d9931a18SJoseph Lo <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 456742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_TIMER>; 457742af7e7SThierry Reding clock-names = "timer"; 458742af7e7SThierry Reding }; 459742af7e7SThierry Reding 460be70771dSThierry Reding tegra_car: clock@60006000 { 461742af7e7SThierry Reding compatible = "nvidia,tegra210-car"; 462742af7e7SThierry Reding reg = <0x0 0x60006000 0x0 0x1000>; 463742af7e7SThierry Reding #clock-cells = <1>; 464742af7e7SThierry Reding #reset-cells = <1>; 465742af7e7SThierry Reding }; 466742af7e7SThierry Reding 467be70771dSThierry Reding flow-controller@60007000 { 468742af7e7SThierry Reding compatible = "nvidia,tegra210-flowctrl"; 469742af7e7SThierry Reding reg = <0x0 0x60007000 0x0 0x1000>; 470742af7e7SThierry Reding }; 471742af7e7SThierry Reding 472be70771dSThierry Reding gpio: gpio@6000d000 { 47301665512SStephen Warren compatible = "nvidia,tegra210-gpio", "nvidia,tegra30-gpio"; 474742af7e7SThierry Reding reg = <0x0 0x6000d000 0x0 0x1000>; 475742af7e7SThierry Reding interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 476742af7e7SThierry Reding <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 477742af7e7SThierry Reding <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 478742af7e7SThierry Reding <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 479742af7e7SThierry Reding <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 480742af7e7SThierry Reding <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 481742af7e7SThierry Reding <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 482742af7e7SThierry Reding <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 483742af7e7SThierry Reding #gpio-cells = <2>; 484742af7e7SThierry Reding gpio-controller; 485742af7e7SThierry Reding #interrupt-cells = <2>; 486742af7e7SThierry Reding interrupt-controller; 487742af7e7SThierry Reding }; 488742af7e7SThierry Reding 489be70771dSThierry Reding apbdma: dma@60020000 { 490742af7e7SThierry Reding compatible = "nvidia,tegra210-apbdma", "nvidia,tegra148-apbdma"; 491742af7e7SThierry Reding reg = <0x0 0x60020000 0x0 0x1400>; 492742af7e7SThierry Reding interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 493742af7e7SThierry Reding <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 494742af7e7SThierry Reding <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 495742af7e7SThierry Reding <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 496742af7e7SThierry Reding <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 497742af7e7SThierry Reding <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 498742af7e7SThierry Reding <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 499742af7e7SThierry Reding <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 500742af7e7SThierry Reding <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 501742af7e7SThierry Reding <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 502742af7e7SThierry Reding <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 503742af7e7SThierry Reding <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 504742af7e7SThierry Reding <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 505742af7e7SThierry Reding <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 506742af7e7SThierry Reding <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 507742af7e7SThierry Reding <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 508742af7e7SThierry Reding <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 509742af7e7SThierry Reding <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 510742af7e7SThierry Reding <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 511742af7e7SThierry Reding <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 512742af7e7SThierry Reding <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 513742af7e7SThierry Reding <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 514742af7e7SThierry Reding <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 515742af7e7SThierry Reding <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 516742af7e7SThierry Reding <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 517742af7e7SThierry Reding <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 518742af7e7SThierry Reding <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 519742af7e7SThierry Reding <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 520742af7e7SThierry Reding <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 521742af7e7SThierry Reding <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 522742af7e7SThierry Reding <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 523742af7e7SThierry Reding <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 524742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_APBDMA>; 525742af7e7SThierry Reding clock-names = "dma"; 526742af7e7SThierry Reding resets = <&tegra_car 34>; 527742af7e7SThierry Reding reset-names = "dma"; 528742af7e7SThierry Reding #dma-cells = <1>; 529742af7e7SThierry Reding }; 530742af7e7SThierry Reding 531be70771dSThierry Reding apbmisc@70000800 { 532742af7e7SThierry Reding compatible = "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc"; 533742af7e7SThierry Reding reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */ 53446e4b227SJoseph Lo <0x0 0x70000008 0x0 0x04>; /* Strapping options */ 535742af7e7SThierry Reding }; 536742af7e7SThierry Reding 537be70771dSThierry Reding pinmux: pinmux@700008d4 { 538742af7e7SThierry Reding compatible = "nvidia,tegra210-pinmux"; 539742af7e7SThierry Reding reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */ 540742af7e7SThierry Reding <0x0 0x70003000 0x0 0x294>; /* Mux registers */ 5414e0f1229SSowjanya Komatineni sdmmc1_3v3_drv: sdmmc1-3v3-drv { 5424e0f1229SSowjanya Komatineni sdmmc1 { 5434e0f1229SSowjanya Komatineni nvidia,pins = "drive_sdmmc1"; 5444e0f1229SSowjanya Komatineni nvidia,pull-down-strength = <0x8>; 5454e0f1229SSowjanya Komatineni nvidia,pull-up-strength = <0x8>; 5464e0f1229SSowjanya Komatineni }; 5474e0f1229SSowjanya Komatineni }; 5484e0f1229SSowjanya Komatineni sdmmc1_1v8_drv: sdmmc1-1v8-drv { 5494e0f1229SSowjanya Komatineni sdmmc1 { 5504e0f1229SSowjanya Komatineni nvidia,pins = "drive_sdmmc1"; 5514e0f1229SSowjanya Komatineni nvidia,pull-down-strength = <0x4>; 5524e0f1229SSowjanya Komatineni nvidia,pull-up-strength = <0x3>; 5534e0f1229SSowjanya Komatineni }; 5544e0f1229SSowjanya Komatineni }; 5554e0f1229SSowjanya Komatineni sdmmc2_1v8_drv: sdmmc2-1v8-drv { 5564e0f1229SSowjanya Komatineni sdmmc2 { 5574e0f1229SSowjanya Komatineni nvidia,pins = "drive_sdmmc2"; 5584e0f1229SSowjanya Komatineni nvidia,pull-down-strength = <0x10>; 5594e0f1229SSowjanya Komatineni nvidia,pull-up-strength = <0x10>; 5604e0f1229SSowjanya Komatineni }; 5614e0f1229SSowjanya Komatineni }; 5624e0f1229SSowjanya Komatineni sdmmc3_3v3_drv: sdmmc3-3v3-drv { 5634e0f1229SSowjanya Komatineni sdmmc3 { 5644e0f1229SSowjanya Komatineni nvidia,pins = "drive_sdmmc3"; 5654e0f1229SSowjanya Komatineni nvidia,pull-down-strength = <0x8>; 5664e0f1229SSowjanya Komatineni nvidia,pull-up-strength = <0x8>; 5674e0f1229SSowjanya Komatineni }; 5684e0f1229SSowjanya Komatineni }; 5694e0f1229SSowjanya Komatineni sdmmc3_1v8_drv: sdmmc3-1v8-drv { 5704e0f1229SSowjanya Komatineni sdmmc3 { 5714e0f1229SSowjanya Komatineni nvidia,pins = "drive_sdmmc3"; 5724e0f1229SSowjanya Komatineni nvidia,pull-down-strength = <0x4>; 5734e0f1229SSowjanya Komatineni nvidia,pull-up-strength = <0x3>; 5744e0f1229SSowjanya Komatineni }; 5754e0f1229SSowjanya Komatineni }; 5764e0f1229SSowjanya Komatineni sdmmc4_1v8_drv: sdmmc4-1v8-drv { 5774e0f1229SSowjanya Komatineni sdmmc4 { 5784e0f1229SSowjanya Komatineni nvidia,pins = "drive_sdmmc4"; 5794e0f1229SSowjanya Komatineni nvidia,pull-down-strength = <0x10>; 5804e0f1229SSowjanya Komatineni nvidia,pull-up-strength = <0x10>; 5814e0f1229SSowjanya Komatineni }; 5824e0f1229SSowjanya Komatineni }; 583742af7e7SThierry Reding }; 584742af7e7SThierry Reding 585742af7e7SThierry Reding /* 586742af7e7SThierry Reding * There are two serial driver i.e. 8250 based simple serial 587742af7e7SThierry Reding * driver and APB DMA based serial driver for higher baudrate 588ef769e32SAdam Buchbinder * and performance. To enable the 8250 based driver, the compatible 589742af7e7SThierry Reding * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable 59068cd8b2eSThierry Reding * the APB DMA based serial driver, the compatible is 591742af7e7SThierry Reding * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". 592742af7e7SThierry Reding */ 593be70771dSThierry Reding uarta: serial@70006000 { 594742af7e7SThierry Reding compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 595742af7e7SThierry Reding reg = <0x0 0x70006000 0x0 0x40>; 596742af7e7SThierry Reding reg-shift = <2>; 597742af7e7SThierry Reding interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 598742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_UARTA>; 599742af7e7SThierry Reding clock-names = "serial"; 600742af7e7SThierry Reding resets = <&tegra_car 6>; 601742af7e7SThierry Reding reset-names = "serial"; 602742af7e7SThierry Reding dmas = <&apbdma 8>, <&apbdma 8>; 603742af7e7SThierry Reding dma-names = "rx", "tx"; 604742af7e7SThierry Reding status = "disabled"; 605742af7e7SThierry Reding }; 606742af7e7SThierry Reding 607be70771dSThierry Reding uartb: serial@70006040 { 608742af7e7SThierry Reding compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 609742af7e7SThierry Reding reg = <0x0 0x70006040 0x0 0x40>; 610742af7e7SThierry Reding reg-shift = <2>; 611742af7e7SThierry Reding interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 612742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_UARTB>; 613742af7e7SThierry Reding clock-names = "serial"; 614742af7e7SThierry Reding resets = <&tegra_car 7>; 615742af7e7SThierry Reding reset-names = "serial"; 616742af7e7SThierry Reding dmas = <&apbdma 9>, <&apbdma 9>; 617742af7e7SThierry Reding dma-names = "rx", "tx"; 618742af7e7SThierry Reding status = "disabled"; 619742af7e7SThierry Reding }; 620742af7e7SThierry Reding 621be70771dSThierry Reding uartc: serial@70006200 { 622742af7e7SThierry Reding compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 623742af7e7SThierry Reding reg = <0x0 0x70006200 0x0 0x40>; 624742af7e7SThierry Reding reg-shift = <2>; 625742af7e7SThierry Reding interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 626742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_UARTC>; 627742af7e7SThierry Reding clock-names = "serial"; 628742af7e7SThierry Reding resets = <&tegra_car 55>; 629742af7e7SThierry Reding reset-names = "serial"; 630742af7e7SThierry Reding dmas = <&apbdma 10>, <&apbdma 10>; 631742af7e7SThierry Reding dma-names = "rx", "tx"; 632742af7e7SThierry Reding status = "disabled"; 633742af7e7SThierry Reding }; 634742af7e7SThierry Reding 635be70771dSThierry Reding uartd: serial@70006300 { 636742af7e7SThierry Reding compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 637742af7e7SThierry Reding reg = <0x0 0x70006300 0x0 0x40>; 638742af7e7SThierry Reding reg-shift = <2>; 639742af7e7SThierry Reding interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 640742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_UARTD>; 641742af7e7SThierry Reding clock-names = "serial"; 642742af7e7SThierry Reding resets = <&tegra_car 65>; 643742af7e7SThierry Reding reset-names = "serial"; 644742af7e7SThierry Reding dmas = <&apbdma 19>, <&apbdma 19>; 645742af7e7SThierry Reding dma-names = "rx", "tx"; 646742af7e7SThierry Reding status = "disabled"; 647742af7e7SThierry Reding }; 648742af7e7SThierry Reding 649be70771dSThierry Reding pwm: pwm@7000a000 { 650742af7e7SThierry Reding compatible = "nvidia,tegra210-pwm", "nvidia,tegra20-pwm"; 651742af7e7SThierry Reding reg = <0x0 0x7000a000 0x0 0x100>; 652742af7e7SThierry Reding #pwm-cells = <2>; 653742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_PWM>; 654742af7e7SThierry Reding clock-names = "pwm"; 655742af7e7SThierry Reding resets = <&tegra_car 17>; 656742af7e7SThierry Reding reset-names = "pwm"; 657742af7e7SThierry Reding status = "disabled"; 658742af7e7SThierry Reding }; 659742af7e7SThierry Reding 660be70771dSThierry Reding i2c@7000c000 { 661140723b9SSowjanya Komatineni compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 662742af7e7SThierry Reding reg = <0x0 0x7000c000 0x0 0x100>; 663742af7e7SThierry Reding interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 664742af7e7SThierry Reding #address-cells = <1>; 665742af7e7SThierry Reding #size-cells = <0>; 666742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_I2C1>; 667742af7e7SThierry Reding clock-names = "div-clk"; 668742af7e7SThierry Reding resets = <&tegra_car 12>; 669742af7e7SThierry Reding reset-names = "i2c"; 670742af7e7SThierry Reding dmas = <&apbdma 21>, <&apbdma 21>; 671742af7e7SThierry Reding dma-names = "rx", "tx"; 672742af7e7SThierry Reding status = "disabled"; 673742af7e7SThierry Reding }; 674742af7e7SThierry Reding 675be70771dSThierry Reding i2c@7000c400 { 676140723b9SSowjanya Komatineni compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 677742af7e7SThierry Reding reg = <0x0 0x7000c400 0x0 0x100>; 678742af7e7SThierry Reding interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 679742af7e7SThierry Reding #address-cells = <1>; 680742af7e7SThierry Reding #size-cells = <0>; 681742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_I2C2>; 682742af7e7SThierry Reding clock-names = "div-clk"; 683742af7e7SThierry Reding resets = <&tegra_car 54>; 684742af7e7SThierry Reding reset-names = "i2c"; 685742af7e7SThierry Reding dmas = <&apbdma 22>, <&apbdma 22>; 686742af7e7SThierry Reding dma-names = "rx", "tx"; 687742af7e7SThierry Reding status = "disabled"; 688742af7e7SThierry Reding }; 689742af7e7SThierry Reding 690be70771dSThierry Reding i2c@7000c500 { 691140723b9SSowjanya Komatineni compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 692742af7e7SThierry Reding reg = <0x0 0x7000c500 0x0 0x100>; 693742af7e7SThierry Reding interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 694742af7e7SThierry Reding #address-cells = <1>; 695742af7e7SThierry Reding #size-cells = <0>; 696742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_I2C3>; 697742af7e7SThierry Reding clock-names = "div-clk"; 698742af7e7SThierry Reding resets = <&tegra_car 67>; 699742af7e7SThierry Reding reset-names = "i2c"; 700742af7e7SThierry Reding dmas = <&apbdma 23>, <&apbdma 23>; 701742af7e7SThierry Reding dma-names = "rx", "tx"; 702742af7e7SThierry Reding status = "disabled"; 703742af7e7SThierry Reding }; 704742af7e7SThierry Reding 705be70771dSThierry Reding i2c@7000c700 { 706140723b9SSowjanya Komatineni compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 707742af7e7SThierry Reding reg = <0x0 0x7000c700 0x0 0x100>; 708742af7e7SThierry Reding interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 709742af7e7SThierry Reding #address-cells = <1>; 710742af7e7SThierry Reding #size-cells = <0>; 711742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_I2C4>; 712742af7e7SThierry Reding clock-names = "div-clk"; 713742af7e7SThierry Reding resets = <&tegra_car 103>; 714742af7e7SThierry Reding reset-names = "i2c"; 715742af7e7SThierry Reding dmas = <&apbdma 26>, <&apbdma 26>; 716742af7e7SThierry Reding dma-names = "rx", "tx"; 71766b2d6e9SJon Hunter pinctrl-0 = <&state_dpaux1_i2c>; 71866b2d6e9SJon Hunter pinctrl-1 = <&state_dpaux1_off>; 71966b2d6e9SJon Hunter pinctrl-names = "default", "idle"; 720742af7e7SThierry Reding status = "disabled"; 721742af7e7SThierry Reding }; 722742af7e7SThierry Reding 723be70771dSThierry Reding i2c@7000d000 { 724140723b9SSowjanya Komatineni compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 725742af7e7SThierry Reding reg = <0x0 0x7000d000 0x0 0x100>; 726742af7e7SThierry Reding interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 727742af7e7SThierry Reding #address-cells = <1>; 728742af7e7SThierry Reding #size-cells = <0>; 729742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_I2C5>; 730742af7e7SThierry Reding clock-names = "div-clk"; 731742af7e7SThierry Reding resets = <&tegra_car 47>; 732742af7e7SThierry Reding reset-names = "i2c"; 733742af7e7SThierry Reding dmas = <&apbdma 24>, <&apbdma 24>; 734742af7e7SThierry Reding dma-names = "rx", "tx"; 735742af7e7SThierry Reding status = "disabled"; 736742af7e7SThierry Reding }; 737742af7e7SThierry Reding 738be70771dSThierry Reding i2c@7000d100 { 739140723b9SSowjanya Komatineni compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 740742af7e7SThierry Reding reg = <0x0 0x7000d100 0x0 0x100>; 741742af7e7SThierry Reding interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 742742af7e7SThierry Reding #address-cells = <1>; 743742af7e7SThierry Reding #size-cells = <0>; 744742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_I2C6>; 745742af7e7SThierry Reding clock-names = "div-clk"; 746742af7e7SThierry Reding resets = <&tegra_car 166>; 747742af7e7SThierry Reding reset-names = "i2c"; 748742af7e7SThierry Reding dmas = <&apbdma 30>, <&apbdma 30>; 749742af7e7SThierry Reding dma-names = "rx", "tx"; 75066b2d6e9SJon Hunter pinctrl-0 = <&state_dpaux_i2c>; 75166b2d6e9SJon Hunter pinctrl-1 = <&state_dpaux_off>; 75266b2d6e9SJon Hunter pinctrl-names = "default", "idle"; 753742af7e7SThierry Reding status = "disabled"; 754742af7e7SThierry Reding }; 755742af7e7SThierry Reding 756be70771dSThierry Reding spi@7000d400 { 757742af7e7SThierry Reding compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 758742af7e7SThierry Reding reg = <0x0 0x7000d400 0x0 0x200>; 759742af7e7SThierry Reding interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 760742af7e7SThierry Reding #address-cells = <1>; 761742af7e7SThierry Reding #size-cells = <0>; 762742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_SBC1>; 763742af7e7SThierry Reding clock-names = "spi"; 764742af7e7SThierry Reding resets = <&tegra_car 41>; 765742af7e7SThierry Reding reset-names = "spi"; 766742af7e7SThierry Reding dmas = <&apbdma 15>, <&apbdma 15>; 767742af7e7SThierry Reding dma-names = "rx", "tx"; 768742af7e7SThierry Reding status = "disabled"; 769742af7e7SThierry Reding }; 770742af7e7SThierry Reding 771be70771dSThierry Reding spi@7000d600 { 772742af7e7SThierry Reding compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 773742af7e7SThierry Reding reg = <0x0 0x7000d600 0x0 0x200>; 774742af7e7SThierry Reding interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 775742af7e7SThierry Reding #address-cells = <1>; 776742af7e7SThierry Reding #size-cells = <0>; 777742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_SBC2>; 778742af7e7SThierry Reding clock-names = "spi"; 779742af7e7SThierry Reding resets = <&tegra_car 44>; 780742af7e7SThierry Reding reset-names = "spi"; 781742af7e7SThierry Reding dmas = <&apbdma 16>, <&apbdma 16>; 782742af7e7SThierry Reding dma-names = "rx", "tx"; 783742af7e7SThierry Reding status = "disabled"; 784742af7e7SThierry Reding }; 785742af7e7SThierry Reding 786be70771dSThierry Reding spi@7000d800 { 787742af7e7SThierry Reding compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 788742af7e7SThierry Reding reg = <0x0 0x7000d800 0x0 0x200>; 789742af7e7SThierry Reding interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 790742af7e7SThierry Reding #address-cells = <1>; 791742af7e7SThierry Reding #size-cells = <0>; 792742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_SBC3>; 793742af7e7SThierry Reding clock-names = "spi"; 794742af7e7SThierry Reding resets = <&tegra_car 46>; 795742af7e7SThierry Reding reset-names = "spi"; 796742af7e7SThierry Reding dmas = <&apbdma 17>, <&apbdma 17>; 797742af7e7SThierry Reding dma-names = "rx", "tx"; 798742af7e7SThierry Reding status = "disabled"; 799742af7e7SThierry Reding }; 800742af7e7SThierry Reding 801be70771dSThierry Reding spi@7000da00 { 802742af7e7SThierry Reding compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 803742af7e7SThierry Reding reg = <0x0 0x7000da00 0x0 0x200>; 804742af7e7SThierry Reding interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 805742af7e7SThierry Reding #address-cells = <1>; 806742af7e7SThierry Reding #size-cells = <0>; 807742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_SBC4>; 808742af7e7SThierry Reding clock-names = "spi"; 809742af7e7SThierry Reding resets = <&tegra_car 68>; 810742af7e7SThierry Reding reset-names = "spi"; 811742af7e7SThierry Reding dmas = <&apbdma 18>, <&apbdma 18>; 812742af7e7SThierry Reding dma-names = "rx", "tx"; 813742af7e7SThierry Reding status = "disabled"; 814742af7e7SThierry Reding }; 815742af7e7SThierry Reding 816be70771dSThierry Reding rtc@7000e000 { 817742af7e7SThierry Reding compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc"; 818742af7e7SThierry Reding reg = <0x0 0x7000e000 0x0 0x100>; 819d13c13f4SSowjanya Komatineni interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; 820359ae651SSowjanya Komatineni interrupt-parent = <&tegra_pmc>; 821742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_RTC>; 822742af7e7SThierry Reding clock-names = "rtc"; 823742af7e7SThierry Reding }; 824742af7e7SThierry Reding 825359ae651SSowjanya Komatineni tegra_pmc: pmc@7000e400 { 826742af7e7SThierry Reding compatible = "nvidia,tegra210-pmc"; 827742af7e7SThierry Reding reg = <0x0 0x7000e400 0x0 0x400>; 828742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; 829742af7e7SThierry Reding clock-names = "pclk", "clk32k_in"; 830359ae651SSowjanya Komatineni #clock-cells = <1>; 831d13c13f4SSowjanya Komatineni #interrupt-cells = <2>; 832d13c13f4SSowjanya Komatineni interrupt-controller; 833c2b82445SJon Hunter 834c2b82445SJon Hunter powergates { 835c2b82445SJon Hunter pd_audio: aud { 836c2b82445SJon Hunter clocks = <&tegra_car TEGRA210_CLK_APE>, 837c2b82445SJon Hunter <&tegra_car TEGRA210_CLK_APB2APE>; 838c2b82445SJon Hunter resets = <&tegra_car 198>; 839c2b82445SJon Hunter #power-domain-cells = <0>; 840c2b82445SJon Hunter }; 841241f02baSJon Hunter 84296d1f078SJon Hunter pd_sor: sor { 84396d1f078SJon Hunter clocks = <&tegra_car TEGRA210_CLK_SOR0>, 84496d1f078SJon Hunter <&tegra_car TEGRA210_CLK_SOR1>, 845b4f99176SSowjanya Komatineni <&tegra_car TEGRA210_CLK_CILAB>, 846b4f99176SSowjanya Komatineni <&tegra_car TEGRA210_CLK_CILCD>, 847b4f99176SSowjanya Komatineni <&tegra_car TEGRA210_CLK_CILE>, 84896d1f078SJon Hunter <&tegra_car TEGRA210_CLK_DSIA>, 84996d1f078SJon Hunter <&tegra_car TEGRA210_CLK_DSIB>, 85096d1f078SJon Hunter <&tegra_car TEGRA210_CLK_DPAUX>, 85196d1f078SJon Hunter <&tegra_car TEGRA210_CLK_DPAUX1>, 85296d1f078SJon Hunter <&tegra_car TEGRA210_CLK_MIPI_CAL>; 85396d1f078SJon Hunter resets = <&tegra_car TEGRA210_CLK_SOR0>, 85496d1f078SJon Hunter <&tegra_car TEGRA210_CLK_SOR1>, 85596d1f078SJon Hunter <&tegra_car TEGRA210_CLK_DSIA>, 85696d1f078SJon Hunter <&tegra_car TEGRA210_CLK_DSIB>, 85796d1f078SJon Hunter <&tegra_car TEGRA210_CLK_DPAUX>, 85896d1f078SJon Hunter <&tegra_car TEGRA210_CLK_DPAUX1>, 85996d1f078SJon Hunter <&tegra_car TEGRA210_CLK_MIPI_CAL>; 86096d1f078SJon Hunter #power-domain-cells = <0>; 86196d1f078SJon Hunter }; 86296d1f078SJon Hunter 863241f02baSJon Hunter pd_xusbss: xusba { 864241f02baSJon Hunter clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>; 865241f02baSJon Hunter resets = <&tegra_car TEGRA210_CLK_XUSB_SS>; 866241f02baSJon Hunter #power-domain-cells = <0>; 867241f02baSJon Hunter }; 868241f02baSJon Hunter 869241f02baSJon Hunter pd_xusbdev: xusbb { 870241f02baSJon Hunter clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>; 871241f02baSJon Hunter resets = <&tegra_car 95>; 872241f02baSJon Hunter #power-domain-cells = <0>; 873241f02baSJon Hunter }; 874241f02baSJon Hunter 875241f02baSJon Hunter pd_xusbhost: xusbc { 876241f02baSJon Hunter clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>; 877241f02baSJon Hunter resets = <&tegra_car TEGRA210_CLK_XUSB_HOST>; 878241f02baSJon Hunter #power-domain-cells = <0>; 879241f02baSJon Hunter }; 88024963d1bSMikko Perttunen 88124963d1bSMikko Perttunen pd_vic: vic { 88224963d1bSMikko Perttunen clocks = <&tegra_car TEGRA210_CLK_VIC03>; 88324963d1bSMikko Perttunen clock-names = "vic"; 88424963d1bSMikko Perttunen resets = <&tegra_car 178>; 88524963d1bSMikko Perttunen reset-names = "vic"; 88624963d1bSMikko Perttunen #power-domain-cells = <0>; 88724963d1bSMikko Perttunen }; 888c4153885SSowjanya Komatineni 889c4153885SSowjanya Komatineni pd_venc: venc { 890c4153885SSowjanya Komatineni clocks = <&tegra_car TEGRA210_CLK_VI>, 891c4153885SSowjanya Komatineni <&tegra_car TEGRA210_CLK_CSI>; 892c4153885SSowjanya Komatineni resets = <&mc TEGRA210_MC_RESET_VI>, 893c4153885SSowjanya Komatineni <&tegra_car 20>, 894c4153885SSowjanya Komatineni <&tegra_car 52>; 895c4153885SSowjanya Komatineni #power-domain-cells = <0>; 896c4153885SSowjanya Komatineni }; 897c2b82445SJon Hunter }; 8986641af7eSAapo Vienamo 8996641af7eSAapo Vienamo sdmmc1_3v3: sdmmc1-3v3 { 9006641af7eSAapo Vienamo pins = "sdmmc1"; 9016641af7eSAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 9026641af7eSAapo Vienamo }; 9036641af7eSAapo Vienamo 9046641af7eSAapo Vienamo sdmmc1_1v8: sdmmc1-1v8 { 9056641af7eSAapo Vienamo pins = "sdmmc1"; 9066641af7eSAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 9076641af7eSAapo Vienamo }; 9086641af7eSAapo Vienamo 9096641af7eSAapo Vienamo sdmmc3_3v3: sdmmc3-3v3 { 9106641af7eSAapo Vienamo pins = "sdmmc3"; 9116641af7eSAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 9126641af7eSAapo Vienamo }; 9136641af7eSAapo Vienamo 9146641af7eSAapo Vienamo sdmmc3_1v8: sdmmc3-1v8 { 9156641af7eSAapo Vienamo pins = "sdmmc3"; 9166641af7eSAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 9176641af7eSAapo Vienamo }; 918871be845SManikanta Maddireddy 919871be845SManikanta Maddireddy pex_dpd_disable: pex_en { 920871be845SManikanta Maddireddy pex-dpd-disable { 921871be845SManikanta Maddireddy pins = "pex-bias", "pex-clk1", "pex-clk2"; 922871be845SManikanta Maddireddy low-power-disable; 923871be845SManikanta Maddireddy }; 924871be845SManikanta Maddireddy }; 925871be845SManikanta Maddireddy 926871be845SManikanta Maddireddy pex_dpd_enable: pex_dis { 927871be845SManikanta Maddireddy pex-dpd-enable { 928871be845SManikanta Maddireddy pins = "pex-bias", "pex-clk1", "pex-clk2"; 929871be845SManikanta Maddireddy low-power-enable; 930871be845SManikanta Maddireddy }; 931871be845SManikanta Maddireddy }; 932742af7e7SThierry Reding }; 933742af7e7SThierry Reding 934be70771dSThierry Reding fuse@7000f800 { 935742af7e7SThierry Reding compatible = "nvidia,tegra210-efuse"; 936742af7e7SThierry Reding reg = <0x0 0x7000f800 0x0 0x400>; 937742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_FUSE>; 938742af7e7SThierry Reding clock-names = "fuse"; 939742af7e7SThierry Reding resets = <&tegra_car 39>; 940742af7e7SThierry Reding reset-names = "fuse"; 941742af7e7SThierry Reding }; 942742af7e7SThierry Reding 943be70771dSThierry Reding mc: memory-controller@70019000 { 944742af7e7SThierry Reding compatible = "nvidia,tegra210-mc"; 945742af7e7SThierry Reding reg = <0x0 0x70019000 0x0 0x1000>; 946742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_MC>; 947742af7e7SThierry Reding clock-names = "mc"; 948742af7e7SThierry Reding 949742af7e7SThierry Reding interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 950742af7e7SThierry Reding 951742af7e7SThierry Reding #iommu-cells = <1>; 9522eb8e1a4SSowjanya Komatineni #reset-cells = <1>; 953742af7e7SThierry Reding }; 954742af7e7SThierry Reding 955e12325f6SThierry Reding emc: external-memory-controller@7001b000 { 956cd9350c5SJoseph Lo compatible = "nvidia,tegra210-emc"; 957cd9350c5SJoseph Lo reg = <0x0 0x7001b000 0x0 0x1000>, 958cd9350c5SJoseph Lo <0x0 0x7001e000 0x0 0x1000>, 959cd9350c5SJoseph Lo <0x0 0x7001f000 0x0 0x1000>; 960cd9350c5SJoseph Lo clocks = <&tegra_car TEGRA210_CLK_EMC>; 961cd9350c5SJoseph Lo clock-names = "emc"; 962cd9350c5SJoseph Lo interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 963cd9350c5SJoseph Lo nvidia,memory-controller = <&mc>; 964e12325f6SThierry Reding #cooling-cells = <2>; 965cd9350c5SJoseph Lo }; 966cd9350c5SJoseph Lo 9676cb60ec4SPreetham Ramchandra sata@70020000 { 9686cb60ec4SPreetham Ramchandra compatible = "nvidia,tegra210-ahci"; 9696cb60ec4SPreetham Ramchandra reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */ 9706cb60ec4SPreetham Ramchandra <0x0 0x70020000 0x0 0x7000>, /* SATA */ 9716cb60ec4SPreetham Ramchandra <0x0 0x70001100 0x0 0x1000>; /* SATA AUX */ 9726cb60ec4SPreetham Ramchandra interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 9736cb60ec4SPreetham Ramchandra clocks = <&tegra_car TEGRA210_CLK_SATA>, 9746cb60ec4SPreetham Ramchandra <&tegra_car TEGRA210_CLK_SATA_OOB>; 9756cb60ec4SPreetham Ramchandra clock-names = "sata", "sata-oob"; 9766cb60ec4SPreetham Ramchandra resets = <&tegra_car 124>, 9776cb60ec4SPreetham Ramchandra <&tegra_car 123>, 9786cb60ec4SPreetham Ramchandra <&tegra_car 129>; 9796cb60ec4SPreetham Ramchandra reset-names = "sata", "sata-oob", "sata-cold"; 9806cb60ec4SPreetham Ramchandra status = "disabled"; 9816cb60ec4SPreetham Ramchandra }; 9826cb60ec4SPreetham Ramchandra 983be70771dSThierry Reding hda@70030000 { 984742af7e7SThierry Reding compatible = "nvidia,tegra210-hda", "nvidia,tegra30-hda"; 985742af7e7SThierry Reding reg = <0x0 0x70030000 0x0 0x10000>; 986742af7e7SThierry Reding interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 987742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_HDA>, 988742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_HDA2HDMI>, 989742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_HDA2CODEC_2X>; 990742af7e7SThierry Reding clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 991742af7e7SThierry Reding resets = <&tegra_car 125>, /* hda */ 992742af7e7SThierry Reding <&tegra_car 128>, /* hda2hdmi */ 993742af7e7SThierry Reding <&tegra_car 111>; /* hda2codec_2x */ 994742af7e7SThierry Reding reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 995742af7e7SThierry Reding status = "disabled"; 996742af7e7SThierry Reding }; 997742af7e7SThierry Reding 998e7a99ac2SThierry Reding usb@70090000 { 999e7a99ac2SThierry Reding compatible = "nvidia,tegra210-xusb"; 1000e7a99ac2SThierry Reding reg = <0x0 0x70090000 0x0 0x8000>, 1001e7a99ac2SThierry Reding <0x0 0x70098000 0x0 0x1000>, 1002e7a99ac2SThierry Reding <0x0 0x70099000 0x0 0x1000>; 1003e7a99ac2SThierry Reding reg-names = "hcd", "fpci", "ipfs"; 1004e7a99ac2SThierry Reding 1005e7a99ac2SThierry Reding interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 10069168e1dbSJon Hunter <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 1007e7a99ac2SThierry Reding 1008e7a99ac2SThierry Reding clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>, 1009e7a99ac2SThierry Reding <&tegra_car TEGRA210_CLK_XUSB_HOST_SRC>, 1010e7a99ac2SThierry Reding <&tegra_car TEGRA210_CLK_XUSB_FALCON_SRC>, 1011e7a99ac2SThierry Reding <&tegra_car TEGRA210_CLK_XUSB_SS>, 1012e7a99ac2SThierry Reding <&tegra_car TEGRA210_CLK_XUSB_SS_SRC>, 1013d19532e6SThierry Reding <&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>, 1014e7a99ac2SThierry Reding <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>, 1015e7a99ac2SThierry Reding <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>, 1016e7a99ac2SThierry Reding <&tegra_car TEGRA210_CLK_PLL_U_480M>, 1017e7a99ac2SThierry Reding <&tegra_car TEGRA210_CLK_CLK_M>, 1018e7a99ac2SThierry Reding <&tegra_car TEGRA210_CLK_PLL_E>; 1019e7a99ac2SThierry Reding clock-names = "xusb_host", "xusb_host_src", 1020e7a99ac2SThierry Reding "xusb_falcon_src", "xusb_ss", 1021d19532e6SThierry Reding "xusb_ss_src", "xusb_ss_div2", 1022e7a99ac2SThierry Reding "xusb_hs_src", "xusb_fs_src", 1023e7a99ac2SThierry Reding "pll_u_480m", "clk_m", "pll_e"; 1024e7a99ac2SThierry Reding resets = <&tegra_car 89>, <&tegra_car 156>, 1025e7a99ac2SThierry Reding <&tegra_car 143>; 1026e7a99ac2SThierry Reding reset-names = "xusb_host", "xusb_ss", "xusb_src"; 102736ec29f7SJon Hunter power-domains = <&pd_xusbhost>, <&pd_xusbss>; 102836ec29f7SJon Hunter power-domain-names = "xusb_host", "xusb_ss"; 1029e7a99ac2SThierry Reding 1030e7a99ac2SThierry Reding nvidia,xusb-padctl = <&padctl>; 1031e7a99ac2SThierry Reding 1032e7a99ac2SThierry Reding status = "disabled"; 1033e7a99ac2SThierry Reding }; 1034e7a99ac2SThierry Reding 10354e07ac90SThierry Reding padctl: padctl@7009f000 { 10364e07ac90SThierry Reding compatible = "nvidia,tegra210-xusb-padctl"; 10374e07ac90SThierry Reding reg = <0x0 0x7009f000 0x0 0x1000>; 10384e07ac90SThierry Reding resets = <&tegra_car 142>; 10394e07ac90SThierry Reding reset-names = "padctl"; 10404e07ac90SThierry Reding 10414e07ac90SThierry Reding status = "disabled"; 10424e07ac90SThierry Reding 10434e07ac90SThierry Reding pads { 10444e07ac90SThierry Reding usb2 { 10454e07ac90SThierry Reding clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>; 10464e07ac90SThierry Reding clock-names = "trk"; 10474e07ac90SThierry Reding status = "disabled"; 10484e07ac90SThierry Reding 10494e07ac90SThierry Reding lanes { 10504e07ac90SThierry Reding usb2-0 { 10514e07ac90SThierry Reding status = "disabled"; 10524e07ac90SThierry Reding #phy-cells = <0>; 10534e07ac90SThierry Reding }; 10544e07ac90SThierry Reding 10554e07ac90SThierry Reding usb2-1 { 10564e07ac90SThierry Reding status = "disabled"; 10574e07ac90SThierry Reding #phy-cells = <0>; 10584e07ac90SThierry Reding }; 10594e07ac90SThierry Reding 10604e07ac90SThierry Reding usb2-2 { 10614e07ac90SThierry Reding status = "disabled"; 10624e07ac90SThierry Reding #phy-cells = <0>; 10634e07ac90SThierry Reding }; 10644e07ac90SThierry Reding 10654e07ac90SThierry Reding usb2-3 { 10664e07ac90SThierry Reding status = "disabled"; 10674e07ac90SThierry Reding #phy-cells = <0>; 10684e07ac90SThierry Reding }; 10694e07ac90SThierry Reding }; 10704e07ac90SThierry Reding }; 10714e07ac90SThierry Reding 10724e07ac90SThierry Reding hsic { 10734e07ac90SThierry Reding clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>; 10744e07ac90SThierry Reding clock-names = "trk"; 10754e07ac90SThierry Reding status = "disabled"; 10764e07ac90SThierry Reding 10774e07ac90SThierry Reding lanes { 10784e07ac90SThierry Reding hsic-0 { 10794e07ac90SThierry Reding status = "disabled"; 10804e07ac90SThierry Reding #phy-cells = <0>; 10814e07ac90SThierry Reding }; 10824e07ac90SThierry Reding 10834e07ac90SThierry Reding hsic-1 { 10844e07ac90SThierry Reding status = "disabled"; 10854e07ac90SThierry Reding #phy-cells = <0>; 10864e07ac90SThierry Reding }; 10874e07ac90SThierry Reding }; 10884e07ac90SThierry Reding }; 10894e07ac90SThierry Reding 10904e07ac90SThierry Reding pcie { 10914e07ac90SThierry Reding clocks = <&tegra_car TEGRA210_CLK_PLL_E>; 10924e07ac90SThierry Reding clock-names = "pll"; 10934e07ac90SThierry Reding resets = <&tegra_car 205>; 10944e07ac90SThierry Reding reset-names = "phy"; 10954e07ac90SThierry Reding status = "disabled"; 10964e07ac90SThierry Reding 10974e07ac90SThierry Reding lanes { 10984e07ac90SThierry Reding pcie-0 { 10994e07ac90SThierry Reding status = "disabled"; 11004e07ac90SThierry Reding #phy-cells = <0>; 11014e07ac90SThierry Reding }; 11024e07ac90SThierry Reding 11034e07ac90SThierry Reding pcie-1 { 11044e07ac90SThierry Reding status = "disabled"; 11054e07ac90SThierry Reding #phy-cells = <0>; 11064e07ac90SThierry Reding }; 11074e07ac90SThierry Reding 11084e07ac90SThierry Reding pcie-2 { 11094e07ac90SThierry Reding status = "disabled"; 11104e07ac90SThierry Reding #phy-cells = <0>; 11114e07ac90SThierry Reding }; 11124e07ac90SThierry Reding 11134e07ac90SThierry Reding pcie-3 { 11144e07ac90SThierry Reding status = "disabled"; 11154e07ac90SThierry Reding #phy-cells = <0>; 11164e07ac90SThierry Reding }; 11174e07ac90SThierry Reding 11184e07ac90SThierry Reding pcie-4 { 11194e07ac90SThierry Reding status = "disabled"; 11204e07ac90SThierry Reding #phy-cells = <0>; 11214e07ac90SThierry Reding }; 11224e07ac90SThierry Reding 11234e07ac90SThierry Reding pcie-5 { 11244e07ac90SThierry Reding status = "disabled"; 11254e07ac90SThierry Reding #phy-cells = <0>; 11264e07ac90SThierry Reding }; 11274e07ac90SThierry Reding 11284e07ac90SThierry Reding pcie-6 { 11294e07ac90SThierry Reding status = "disabled"; 11304e07ac90SThierry Reding #phy-cells = <0>; 11314e07ac90SThierry Reding }; 11324e07ac90SThierry Reding }; 11334e07ac90SThierry Reding }; 11344e07ac90SThierry Reding 11354e07ac90SThierry Reding sata { 11364e07ac90SThierry Reding clocks = <&tegra_car TEGRA210_CLK_PLL_E>; 11374e07ac90SThierry Reding clock-names = "pll"; 11384e07ac90SThierry Reding resets = <&tegra_car 204>; 11394e07ac90SThierry Reding reset-names = "phy"; 11404e07ac90SThierry Reding status = "disabled"; 11414e07ac90SThierry Reding 11424e07ac90SThierry Reding lanes { 11434e07ac90SThierry Reding sata-0 { 11444e07ac90SThierry Reding status = "disabled"; 11454e07ac90SThierry Reding #phy-cells = <0>; 11464e07ac90SThierry Reding }; 11474e07ac90SThierry Reding }; 11484e07ac90SThierry Reding }; 11494e07ac90SThierry Reding }; 11504e07ac90SThierry Reding 11514e07ac90SThierry Reding ports { 11524e07ac90SThierry Reding usb2-0 { 11534e07ac90SThierry Reding status = "disabled"; 11544e07ac90SThierry Reding }; 11554e07ac90SThierry Reding 11564e07ac90SThierry Reding usb2-1 { 11574e07ac90SThierry Reding status = "disabled"; 11584e07ac90SThierry Reding }; 11594e07ac90SThierry Reding 11604e07ac90SThierry Reding usb2-2 { 11614e07ac90SThierry Reding status = "disabled"; 11624e07ac90SThierry Reding }; 11634e07ac90SThierry Reding 11644e07ac90SThierry Reding usb2-3 { 11654e07ac90SThierry Reding status = "disabled"; 11664e07ac90SThierry Reding }; 11674e07ac90SThierry Reding 11684e07ac90SThierry Reding hsic-0 { 11694e07ac90SThierry Reding status = "disabled"; 11704e07ac90SThierry Reding }; 11714e07ac90SThierry Reding 11724e07ac90SThierry Reding usb3-0 { 11734e07ac90SThierry Reding status = "disabled"; 11744e07ac90SThierry Reding }; 11754e07ac90SThierry Reding 11764e07ac90SThierry Reding usb3-1 { 11774e07ac90SThierry Reding status = "disabled"; 11784e07ac90SThierry Reding }; 11794e07ac90SThierry Reding 11804e07ac90SThierry Reding usb3-2 { 11814e07ac90SThierry Reding status = "disabled"; 11824e07ac90SThierry Reding }; 11834e07ac90SThierry Reding 11844e07ac90SThierry Reding usb3-3 { 11854e07ac90SThierry Reding status = "disabled"; 11864e07ac90SThierry Reding }; 11874e07ac90SThierry Reding }; 11884e07ac90SThierry Reding }; 11894e07ac90SThierry Reding 119067bb17f6SThierry Reding mmc@700b0000 { 1191b3fa0e03SThierry Reding compatible = "nvidia,tegra210-sdhci"; 1192742af7e7SThierry Reding reg = <0x0 0x700b0000 0x0 0x200>; 1193742af7e7SThierry Reding interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1194742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_SDMMC1>; 1195742af7e7SThierry Reding clock-names = "sdhci"; 1196742af7e7SThierry Reding resets = <&tegra_car 14>; 1197742af7e7SThierry Reding reset-names = "sdhci"; 11984e0f1229SSowjanya Komatineni pinctrl-names = "sdmmc-3v3", "sdmmc-1v8", 11994e0f1229SSowjanya Komatineni "sdmmc-3v3-drv", "sdmmc-1v8-drv"; 12006641af7eSAapo Vienamo pinctrl-0 = <&sdmmc1_3v3>; 12016641af7eSAapo Vienamo pinctrl-1 = <&sdmmc1_1v8>; 12024e0f1229SSowjanya Komatineni pinctrl-2 = <&sdmmc1_3v3_drv>; 12034e0f1229SSowjanya Komatineni pinctrl-3 = <&sdmmc1_1v8_drv>; 12041ea06718SAapo Vienamo nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>; 12051ea06718SAapo Vienamo nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>; 12061ea06718SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>; 12071ea06718SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>; 120863af8bcdSAapo Vienamo nvidia,default-tap = <0x2>; 120963af8bcdSAapo Vienamo nvidia,default-trim = <0x4>; 1210918f9671SAapo Vienamo assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>, 1211918f9671SAapo Vienamo <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>, 1212918f9671SAapo Vienamo <&tegra_car TEGRA210_CLK_PLL_C4>; 1213918f9671SAapo Vienamo assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 1214918f9671SAapo Vienamo assigned-clock-rates = <200000000>, <1000000000>, <1000000000>; 1215742af7e7SThierry Reding status = "disabled"; 1216742af7e7SThierry Reding }; 1217742af7e7SThierry Reding 121867bb17f6SThierry Reding mmc@700b0200 { 1219b3fa0e03SThierry Reding compatible = "nvidia,tegra210-sdhci"; 1220742af7e7SThierry Reding reg = <0x0 0x700b0200 0x0 0x200>; 1221742af7e7SThierry Reding interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 1222742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_SDMMC2>; 1223742af7e7SThierry Reding clock-names = "sdhci"; 1224742af7e7SThierry Reding resets = <&tegra_car 9>; 1225742af7e7SThierry Reding reset-names = "sdhci"; 12264e0f1229SSowjanya Komatineni pinctrl-names = "sdmmc-1v8-drv"; 12274e0f1229SSowjanya Komatineni pinctrl-0 = <&sdmmc2_1v8_drv>; 12281ea06718SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>; 12291ea06718SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>; 123063af8bcdSAapo Vienamo nvidia,default-tap = <0x8>; 123163af8bcdSAapo Vienamo nvidia,default-trim = <0x0>; 1232742af7e7SThierry Reding status = "disabled"; 1233742af7e7SThierry Reding }; 1234742af7e7SThierry Reding 123567bb17f6SThierry Reding mmc@700b0400 { 1236b3fa0e03SThierry Reding compatible = "nvidia,tegra210-sdhci"; 1237742af7e7SThierry Reding reg = <0x0 0x700b0400 0x0 0x200>; 1238742af7e7SThierry Reding interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 1239742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_SDMMC3>; 1240742af7e7SThierry Reding clock-names = "sdhci"; 1241742af7e7SThierry Reding resets = <&tegra_car 69>; 1242742af7e7SThierry Reding reset-names = "sdhci"; 12434e0f1229SSowjanya Komatineni pinctrl-names = "sdmmc-3v3", "sdmmc-1v8", 12444e0f1229SSowjanya Komatineni "sdmmc-3v3-drv", "sdmmc-1v8-drv"; 12456641af7eSAapo Vienamo pinctrl-0 = <&sdmmc3_3v3>; 12466641af7eSAapo Vienamo pinctrl-1 = <&sdmmc3_1v8>; 12474e0f1229SSowjanya Komatineni pinctrl-2 = <&sdmmc3_3v3_drv>; 12484e0f1229SSowjanya Komatineni pinctrl-3 = <&sdmmc3_1v8_drv>; 12491ea06718SAapo Vienamo nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>; 12501ea06718SAapo Vienamo nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>; 12511ea06718SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>; 12521ea06718SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>; 125363af8bcdSAapo Vienamo nvidia,default-tap = <0x3>; 125463af8bcdSAapo Vienamo nvidia,default-trim = <0x3>; 1255742af7e7SThierry Reding status = "disabled"; 1256742af7e7SThierry Reding }; 1257742af7e7SThierry Reding 125867bb17f6SThierry Reding mmc@700b0600 { 1259b3fa0e03SThierry Reding compatible = "nvidia,tegra210-sdhci"; 1260742af7e7SThierry Reding reg = <0x0 0x700b0600 0x0 0x200>; 1261742af7e7SThierry Reding interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1262742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_SDMMC4>; 1263742af7e7SThierry Reding clock-names = "sdhci"; 1264742af7e7SThierry Reding resets = <&tegra_car 15>; 1265742af7e7SThierry Reding reset-names = "sdhci"; 12664e0f1229SSowjanya Komatineni pinctrl-names = "sdmmc-3v3-drv", "sdmmc-1v8-drv"; 12674e0f1229SSowjanya Komatineni pinctrl-0 = <&sdmmc4_1v8_drv>; 12684e0f1229SSowjanya Komatineni pinctrl-1 = <&sdmmc4_1v8_drv>; 12691ea06718SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>; 12701ea06718SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>; 127163af8bcdSAapo Vienamo nvidia,default-tap = <0x8>; 127263af8bcdSAapo Vienamo nvidia,default-trim = <0x0>; 1273918f9671SAapo Vienamo assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>, 1274918f9671SAapo Vienamo <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 1275918f9671SAapo Vienamo assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 12765879600aSAapo Vienamo nvidia,dqs-trim = <40>; 1277d5d6b468SAapo Vienamo mmc-hs400-1_8v; 1278742af7e7SThierry Reding status = "disabled"; 1279742af7e7SThierry Reding }; 1280742af7e7SThierry Reding 1281e74db5a5SNagarjuna Kristam usb@700d0000 { 1282e74db5a5SNagarjuna Kristam compatible = "nvidia,tegra210-xudc"; 1283e74db5a5SNagarjuna Kristam reg = <0x0 0x700d0000 0x0 0x8000>, 1284e74db5a5SNagarjuna Kristam <0x0 0x700d8000 0x0 0x1000>, 1285e74db5a5SNagarjuna Kristam <0x0 0x700d9000 0x0 0x1000>; 1286e74db5a5SNagarjuna Kristam reg-names = "base", "fpci", "ipfs"; 1287e74db5a5SNagarjuna Kristam interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1288e74db5a5SNagarjuna Kristam clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>, 1289e74db5a5SNagarjuna Kristam <&tegra_car TEGRA210_CLK_XUSB_SS>, 1290e74db5a5SNagarjuna Kristam <&tegra_car TEGRA210_CLK_XUSB_SSP_SRC>, 1291e74db5a5SNagarjuna Kristam <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>, 1292e74db5a5SNagarjuna Kristam <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>; 1293e74db5a5SNagarjuna Kristam clock-names = "dev", "ss", "ss_src", "fs_src", "hs_src"; 1294e74db5a5SNagarjuna Kristam power-domains = <&pd_xusbdev>, <&pd_xusbss>; 1295e74db5a5SNagarjuna Kristam power-domain-names = "dev", "ss"; 1296e74db5a5SNagarjuna Kristam nvidia,xusb-padctl = <&padctl>; 1297e74db5a5SNagarjuna Kristam status = "disabled"; 1298e74db5a5SNagarjuna Kristam }; 1299e74db5a5SNagarjuna Kristam 1300be70771dSThierry Reding mipi: mipi@700e3000 { 1301742af7e7SThierry Reding compatible = "nvidia,tegra210-mipi"; 1302742af7e7SThierry Reding reg = <0x0 0x700e3000 0x0 0x100>; 1303742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_MIPI_CAL>; 1304742af7e7SThierry Reding clock-names = "mipi-cal"; 130596d1f078SJon Hunter power-domains = <&pd_sor>; 1306742af7e7SThierry Reding #nvidia,mipi-calibrate-cells = <1>; 1307742af7e7SThierry Reding }; 1308742af7e7SThierry Reding 13092ceed593SJoseph Lo dfll: clock@70110000 { 13102ceed593SJoseph Lo compatible = "nvidia,tegra210-dfll"; 13112ceed593SJoseph Lo reg = <0 0x70110000 0 0x100>, /* DFLL control */ 13122ceed593SJoseph Lo <0 0x70110000 0 0x100>, /* I2C output control */ 13132ceed593SJoseph Lo <0 0x70110100 0 0x100>, /* Integrated I2C controller */ 13142ceed593SJoseph Lo <0 0x70110200 0 0x100>; /* Look-up table RAM */ 13152ceed593SJoseph Lo interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 13162ceed593SJoseph Lo clocks = <&tegra_car TEGRA210_CLK_DFLL_SOC>, 13172ceed593SJoseph Lo <&tegra_car TEGRA210_CLK_DFLL_REF>, 13182ceed593SJoseph Lo <&tegra_car TEGRA210_CLK_I2C5>; 13192ceed593SJoseph Lo clock-names = "soc", "ref", "i2c"; 13202ceed593SJoseph Lo resets = <&tegra_car TEGRA210_RST_DFLL_DVCO>; 13212ceed593SJoseph Lo reset-names = "dvco"; 13222ceed593SJoseph Lo #clock-cells = <0>; 13232ceed593SJoseph Lo clock-output-names = "dfllCPU_out"; 13242ceed593SJoseph Lo status = "disabled"; 13252ceed593SJoseph Lo }; 13262ceed593SJoseph Lo 13270f133090SJon Hunter aconnect@702c0000 { 13280f133090SJon Hunter compatible = "nvidia,tegra210-aconnect"; 13290f133090SJon Hunter clocks = <&tegra_car TEGRA210_CLK_APE>, 13300f133090SJon Hunter <&tegra_car TEGRA210_CLK_APB2APE>; 13310f133090SJon Hunter clock-names = "ape", "apb2ape"; 13320f133090SJon Hunter power-domains = <&pd_audio>; 13330f133090SJon Hunter #address-cells = <1>; 13340f133090SJon Hunter #size-cells = <1>; 13350f133090SJon Hunter ranges = <0x702c0000 0x0 0x702c0000 0x00040000>; 13360f133090SJon Hunter status = "disabled"; 1337bcdbde43SJon Hunter 133819e61213SJon Hunter adma: dma@702e2000 { 133919e61213SJon Hunter compatible = "nvidia,tegra210-adma"; 134019e61213SJon Hunter reg = <0x702e2000 0x2000>; 134119e61213SJon Hunter interrupt-parent = <&agic>; 134219e61213SJon Hunter interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 134319e61213SJon Hunter <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 134419e61213SJon Hunter <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 134519e61213SJon Hunter <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 134619e61213SJon Hunter <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 134719e61213SJon Hunter <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 134819e61213SJon Hunter <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 134919e61213SJon Hunter <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 135019e61213SJon Hunter <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 135119e61213SJon Hunter <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 135219e61213SJon Hunter <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 135319e61213SJon Hunter <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 135419e61213SJon Hunter <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 135519e61213SJon Hunter <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 135619e61213SJon Hunter <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 135719e61213SJon Hunter <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 135819e61213SJon Hunter <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 135919e61213SJon Hunter <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 136019e61213SJon Hunter <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 136119e61213SJon Hunter <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 136219e61213SJon Hunter <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 136319e61213SJon Hunter <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 136419e61213SJon Hunter #dma-cells = <1>; 136519e61213SJon Hunter clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>; 136619e61213SJon Hunter clock-names = "d_audio"; 136719e61213SJon Hunter status = "disabled"; 136819e61213SJon Hunter }; 136919e61213SJon Hunter 1370df93557bSThierry Reding agic: interrupt-controller@702f9000 { 1371bcdbde43SJon Hunter compatible = "nvidia,tegra210-agic"; 1372bcdbde43SJon Hunter #interrupt-cells = <3>; 1373bcdbde43SJon Hunter interrupt-controller; 1374ba24eee6SJon Hunter reg = <0x702f9000 0x1000>, 1375bcdbde43SJon Hunter <0x702fa000 0x2000>; 1376bcdbde43SJon Hunter interrupts = <GIC_SPI 102 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1377bcdbde43SJon Hunter clocks = <&tegra_car TEGRA210_CLK_APE>; 1378bcdbde43SJon Hunter clock-names = "clk"; 1379bcdbde43SJon Hunter status = "disabled"; 1380bcdbde43SJon Hunter }; 13810f133090SJon Hunter }; 13820f133090SJon Hunter 1383be70771dSThierry Reding spi@70410000 { 1384742af7e7SThierry Reding compatible = "nvidia,tegra210-qspi"; 1385742af7e7SThierry Reding reg = <0x0 0x70410000 0x0 0x1000>; 1386742af7e7SThierry Reding interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1387742af7e7SThierry Reding #address-cells = <1>; 1388742af7e7SThierry Reding #size-cells = <0>; 1389742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_QSPI>; 1390742af7e7SThierry Reding clock-names = "qspi"; 1391742af7e7SThierry Reding resets = <&tegra_car 211>; 1392742af7e7SThierry Reding reset-names = "qspi"; 1393742af7e7SThierry Reding dmas = <&apbdma 5>, <&apbdma 5>; 1394742af7e7SThierry Reding dma-names = "rx", "tx"; 1395742af7e7SThierry Reding status = "disabled"; 1396742af7e7SThierry Reding }; 1397742af7e7SThierry Reding 1398be70771dSThierry Reding usb@7d000000 { 1399742af7e7SThierry Reding compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 1400742af7e7SThierry Reding reg = <0x0 0x7d000000 0x0 0x4000>; 1401742af7e7SThierry Reding interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1402742af7e7SThierry Reding phy_type = "utmi"; 1403742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_USBD>; 1404742af7e7SThierry Reding clock-names = "usb"; 1405742af7e7SThierry Reding resets = <&tegra_car 22>; 1406742af7e7SThierry Reding reset-names = "usb"; 1407742af7e7SThierry Reding nvidia,phy = <&phy1>; 1408742af7e7SThierry Reding status = "disabled"; 1409742af7e7SThierry Reding }; 1410742af7e7SThierry Reding 1411be70771dSThierry Reding phy1: usb-phy@7d000000 { 1412742af7e7SThierry Reding compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; 1413742af7e7SThierry Reding reg = <0x0 0x7d000000 0x0 0x4000>, 1414742af7e7SThierry Reding <0x0 0x7d000000 0x0 0x4000>; 1415742af7e7SThierry Reding phy_type = "utmi"; 1416742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_USBD>, 1417742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_PLL_U>, 1418742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_USBD>; 1419742af7e7SThierry Reding clock-names = "reg", "pll_u", "utmi-pads"; 1420742af7e7SThierry Reding resets = <&tegra_car 22>, <&tegra_car 22>; 1421742af7e7SThierry Reding reset-names = "usb", "utmi-pads"; 1422742af7e7SThierry Reding nvidia,hssync-start-delay = <0>; 1423742af7e7SThierry Reding nvidia,idle-wait-delay = <17>; 1424742af7e7SThierry Reding nvidia,elastic-limit = <16>; 1425742af7e7SThierry Reding nvidia,term-range-adj = <6>; 1426742af7e7SThierry Reding nvidia,xcvr-setup = <9>; 1427742af7e7SThierry Reding nvidia,xcvr-lsfslew = <0>; 1428742af7e7SThierry Reding nvidia,xcvr-lsrslew = <3>; 1429742af7e7SThierry Reding nvidia,hssquelch-level = <2>; 1430742af7e7SThierry Reding nvidia,hsdiscon-level = <5>; 1431742af7e7SThierry Reding nvidia,xcvr-hsslew = <12>; 1432742af7e7SThierry Reding nvidia,has-utmi-pad-registers; 1433742af7e7SThierry Reding status = "disabled"; 1434742af7e7SThierry Reding }; 1435742af7e7SThierry Reding 1436be70771dSThierry Reding usb@7d004000 { 1437742af7e7SThierry Reding compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 1438742af7e7SThierry Reding reg = <0x0 0x7d004000 0x0 0x4000>; 1439742af7e7SThierry Reding interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1440742af7e7SThierry Reding phy_type = "utmi"; 1441742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_USB2>; 1442742af7e7SThierry Reding clock-names = "usb"; 1443742af7e7SThierry Reding resets = <&tegra_car 58>; 1444742af7e7SThierry Reding reset-names = "usb"; 1445742af7e7SThierry Reding nvidia,phy = <&phy2>; 1446742af7e7SThierry Reding status = "disabled"; 1447742af7e7SThierry Reding }; 1448742af7e7SThierry Reding 1449be70771dSThierry Reding phy2: usb-phy@7d004000 { 1450742af7e7SThierry Reding compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; 1451742af7e7SThierry Reding reg = <0x0 0x7d004000 0x0 0x4000>, 1452742af7e7SThierry Reding <0x0 0x7d000000 0x0 0x4000>; 1453742af7e7SThierry Reding phy_type = "utmi"; 1454742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_USB2>, 1455742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_PLL_U>, 1456742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_USBD>; 1457742af7e7SThierry Reding clock-names = "reg", "pll_u", "utmi-pads"; 1458742af7e7SThierry Reding resets = <&tegra_car 58>, <&tegra_car 22>; 1459742af7e7SThierry Reding reset-names = "usb", "utmi-pads"; 1460742af7e7SThierry Reding nvidia,hssync-start-delay = <0>; 1461742af7e7SThierry Reding nvidia,idle-wait-delay = <17>; 1462742af7e7SThierry Reding nvidia,elastic-limit = <16>; 1463742af7e7SThierry Reding nvidia,term-range-adj = <6>; 1464742af7e7SThierry Reding nvidia,xcvr-setup = <9>; 1465742af7e7SThierry Reding nvidia,xcvr-lsfslew = <0>; 1466742af7e7SThierry Reding nvidia,xcvr-lsrslew = <3>; 1467742af7e7SThierry Reding nvidia,hssquelch-level = <2>; 1468742af7e7SThierry Reding nvidia,hsdiscon-level = <5>; 1469742af7e7SThierry Reding nvidia,xcvr-hsslew = <12>; 1470742af7e7SThierry Reding status = "disabled"; 1471742af7e7SThierry Reding }; 1472742af7e7SThierry Reding 1473742af7e7SThierry Reding cpus { 1474742af7e7SThierry Reding #address-cells = <1>; 1475742af7e7SThierry Reding #size-cells = <0>; 1476742af7e7SThierry Reding 1477742af7e7SThierry Reding cpu@0 { 1478742af7e7SThierry Reding device_type = "cpu"; 1479742af7e7SThierry Reding compatible = "arm,cortex-a57"; 1480742af7e7SThierry Reding reg = <0>; 148143b9b402SJoseph Lo clocks = <&tegra_car TEGRA210_CLK_CCLK_G>, 148243b9b402SJoseph Lo <&tegra_car TEGRA210_CLK_PLL_X>, 148343b9b402SJoseph Lo <&tegra_car TEGRA210_CLK_PLL_P_OUT4>, 148443b9b402SJoseph Lo <&dfll>; 148543b9b402SJoseph Lo clock-names = "cpu_g", "pll_x", "pll_p", "dfll"; 148643b9b402SJoseph Lo clock-latency = <300000>; 1487da77c6d9SJoseph Lo cpu-idle-states = <&CPU_SLEEP>; 14886c00cac1SJoseph Lo next-level-cache = <&L2>; 1489742af7e7SThierry Reding }; 1490742af7e7SThierry Reding 1491742af7e7SThierry Reding cpu@1 { 1492742af7e7SThierry Reding device_type = "cpu"; 1493742af7e7SThierry Reding compatible = "arm,cortex-a57"; 1494742af7e7SThierry Reding reg = <1>; 1495da77c6d9SJoseph Lo cpu-idle-states = <&CPU_SLEEP>; 14966c00cac1SJoseph Lo next-level-cache = <&L2>; 1497742af7e7SThierry Reding }; 1498742af7e7SThierry Reding 1499742af7e7SThierry Reding cpu@2 { 1500742af7e7SThierry Reding device_type = "cpu"; 1501742af7e7SThierry Reding compatible = "arm,cortex-a57"; 1502742af7e7SThierry Reding reg = <2>; 1503da77c6d9SJoseph Lo cpu-idle-states = <&CPU_SLEEP>; 15046c00cac1SJoseph Lo next-level-cache = <&L2>; 1505742af7e7SThierry Reding }; 1506742af7e7SThierry Reding 1507742af7e7SThierry Reding cpu@3 { 1508742af7e7SThierry Reding device_type = "cpu"; 1509742af7e7SThierry Reding compatible = "arm,cortex-a57"; 1510742af7e7SThierry Reding reg = <3>; 1511da77c6d9SJoseph Lo cpu-idle-states = <&CPU_SLEEP>; 15126c00cac1SJoseph Lo next-level-cache = <&L2>; 1513da77c6d9SJoseph Lo }; 1514da77c6d9SJoseph Lo 1515da77c6d9SJoseph Lo idle-states { 1516da77c6d9SJoseph Lo entry-method = "psci"; 1517da77c6d9SJoseph Lo 1518da77c6d9SJoseph Lo CPU_SLEEP: cpu-sleep { 1519da77c6d9SJoseph Lo compatible = "arm,idle-state"; 1520da77c6d9SJoseph Lo arm,psci-suspend-param = <0x40000007>; 1521da77c6d9SJoseph Lo entry-latency-us = <100>; 1522da77c6d9SJoseph Lo exit-latency-us = <30>; 1523da77c6d9SJoseph Lo min-residency-us = <1000>; 1524da77c6d9SJoseph Lo wakeup-latency-us = <130>; 1525da77c6d9SJoseph Lo idle-state-name = "cpu-sleep"; 1526da77c6d9SJoseph Lo status = "disabled"; 1527da77c6d9SJoseph Lo }; 1528742af7e7SThierry Reding }; 15296c00cac1SJoseph Lo 15306c00cac1SJoseph Lo L2: l2-cache { 15316c00cac1SJoseph Lo compatible = "cache"; 15326c00cac1SJoseph Lo }; 1533742af7e7SThierry Reding }; 1534742af7e7SThierry Reding 1535264064abSThierry Reding pmu { 1536264064abSThierry Reding compatible = "arm,armv8-pmuv3"; 1537264064abSThierry Reding interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1538264064abSThierry Reding <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1539264064abSThierry Reding <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1540264064abSThierry Reding <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 1541264064abSThierry Reding interrupt-affinity = <&{/cpus/cpu@0} &{/cpus/cpu@1} 1542264064abSThierry Reding &{/cpus/cpu@2} &{/cpus/cpu@3}>; 1543264064abSThierry Reding }; 1544264064abSThierry Reding 1545742af7e7SThierry Reding timer { 1546742af7e7SThierry Reding compatible = "arm,armv8-timer"; 1547742af7e7SThierry Reding interrupts = <GIC_PPI 13 1548742af7e7SThierry Reding (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1549742af7e7SThierry Reding <GIC_PPI 14 1550742af7e7SThierry Reding (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1551742af7e7SThierry Reding <GIC_PPI 11 1552742af7e7SThierry Reding (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1553742af7e7SThierry Reding <GIC_PPI 10 1554742af7e7SThierry Reding (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1555742af7e7SThierry Reding interrupt-parent = <&gic>; 15566b9e263bSThierry Reding arm,no-tick-in-suspend; 1557742af7e7SThierry Reding }; 1558e2bed1ebSWei Ni 1559e2bed1ebSWei Ni soctherm: thermal-sensor@700e2000 { 1560e2bed1ebSWei Ni compatible = "nvidia,tegra210-soctherm"; 1561644c569dSThierry Reding reg = <0x0 0x700e2000 0x0 0x600>, /* SOC_THERM reg_base */ 1562644c569dSThierry Reding <0x0 0x60006000 0x0 0x400>; /* CAR reg_base */ 1563cbd0f000SWei Ni reg-names = "soctherm-reg", "car-reg"; 156444ff822cSThierry Reding interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 156544ff822cSThierry Reding <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 156644ff822cSThierry Reding interrupt-names = "thermal", "edp"; 1567e2bed1ebSWei Ni clocks = <&tegra_car TEGRA210_CLK_TSENSOR>, 1568e2bed1ebSWei Ni <&tegra_car TEGRA210_CLK_SOC_THERM>; 1569e2bed1ebSWei Ni clock-names = "tsensor", "soctherm"; 1570e2bed1ebSWei Ni resets = <&tegra_car 78>; 1571e2bed1ebSWei Ni reset-names = "soctherm"; 1572e2bed1ebSWei Ni #thermal-sensor-cells = <1>; 1573cbd0f000SWei Ni 1574cbd0f000SWei Ni throttle-cfgs { 1575cbd0f000SWei Ni throttle_heavy: heavy { 1576cbd0f000SWei Ni nvidia,priority = <100>; 1577cbd0f000SWei Ni nvidia,cpu-throt-percent = <85>; 1578cbd0f000SWei Ni 1579cbd0f000SWei Ni #cooling-cells = <2>; 1580cbd0f000SWei Ni }; 1581cbd0f000SWei Ni }; 1582e2bed1ebSWei Ni }; 1583e2bed1ebSWei Ni 1584e2bed1ebSWei Ni thermal-zones { 1585e2bed1ebSWei Ni cpu { 1586e2bed1ebSWei Ni polling-delay-passive = <1000>; 1587e2bed1ebSWei Ni polling-delay = <0>; 1588e2bed1ebSWei Ni 1589e2bed1ebSWei Ni thermal-sensors = 1590e2bed1ebSWei Ni <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; 15915e03f663SWei Ni 15925e03f663SWei Ni trips { 15935e03f663SWei Ni cpu-shutdown-trip { 15945e03f663SWei Ni temperature = <102500>; 15955e03f663SWei Ni hysteresis = <0>; 15965e03f663SWei Ni type = "critical"; 15975e03f663SWei Ni }; 1598cbd0f000SWei Ni 1599cbd0f000SWei Ni cpu_throttle_trip: throttle-trip { 1600cbd0f000SWei Ni temperature = <98500>; 1601cbd0f000SWei Ni hysteresis = <1000>; 1602cbd0f000SWei Ni type = "hot"; 1603cbd0f000SWei Ni }; 16045e03f663SWei Ni }; 16055e03f663SWei Ni 16065e03f663SWei Ni cooling-maps { 1607cbd0f000SWei Ni map0 { 1608cbd0f000SWei Ni trip = <&cpu_throttle_trip>; 1609cbd0f000SWei Ni cooling-device = <&throttle_heavy 1 1>; 1610cbd0f000SWei Ni }; 16115e03f663SWei Ni }; 1612e2bed1ebSWei Ni }; 161324fc3363SThierry Reding 1614e2bed1ebSWei Ni mem { 1615e2bed1ebSWei Ni polling-delay-passive = <0>; 1616e2bed1ebSWei Ni polling-delay = <0>; 1617e2bed1ebSWei Ni 1618e2bed1ebSWei Ni thermal-sensors = 1619e2bed1ebSWei Ni <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>; 16205e03f663SWei Ni 16215e03f663SWei Ni trips { 1622e12325f6SThierry Reding dram_nominal: mem-nominal-trip { 1623e12325f6SThierry Reding temperature = <50000>; 1624e12325f6SThierry Reding hysteresis = <1000>; 1625e12325f6SThierry Reding type = "passive"; 1626e12325f6SThierry Reding }; 1627e12325f6SThierry Reding 1628e12325f6SThierry Reding dram_throttle: mem-throttle-trip { 1629e12325f6SThierry Reding temperature = <70000>; 1630e12325f6SThierry Reding hysteresis = <1000>; 1631e12325f6SThierry Reding type = "active"; 1632e12325f6SThierry Reding }; 1633e12325f6SThierry Reding 16345e03f663SWei Ni mem-shutdown-trip { 16355e03f663SWei Ni temperature = <103000>; 16365e03f663SWei Ni hysteresis = <0>; 16375e03f663SWei Ni type = "critical"; 16385e03f663SWei Ni }; 16395e03f663SWei Ni }; 16405e03f663SWei Ni 16415e03f663SWei Ni cooling-maps { 1642e12325f6SThierry Reding dram-passive { 1643e12325f6SThierry Reding cooling-device = <&emc 0 0>; 1644e12325f6SThierry Reding trip = <&dram_nominal>; 1645e12325f6SThierry Reding }; 1646e12325f6SThierry Reding 1647e12325f6SThierry Reding dram-active { 1648e12325f6SThierry Reding cooling-device = <&emc 1 1>; 1649e12325f6SThierry Reding trip = <&dram_throttle>; 1650e12325f6SThierry Reding }; 16515e03f663SWei Ni }; 1652e2bed1ebSWei Ni }; 165324fc3363SThierry Reding 1654e2bed1ebSWei Ni gpu { 1655e2bed1ebSWei Ni polling-delay-passive = <1000>; 1656e2bed1ebSWei Ni polling-delay = <0>; 1657e2bed1ebSWei Ni 1658e2bed1ebSWei Ni thermal-sensors = 1659e2bed1ebSWei Ni <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>; 16605e03f663SWei Ni 16615e03f663SWei Ni trips { 16625e03f663SWei Ni gpu-shutdown-trip { 16635e03f663SWei Ni temperature = <103000>; 16645e03f663SWei Ni hysteresis = <0>; 16655e03f663SWei Ni type = "critical"; 16665e03f663SWei Ni }; 1667cbd0f000SWei Ni 1668cbd0f000SWei Ni gpu_throttle_trip: throttle-trip { 1669cbd0f000SWei Ni temperature = <100000>; 1670cbd0f000SWei Ni hysteresis = <1000>; 1671cbd0f000SWei Ni type = "hot"; 1672cbd0f000SWei Ni }; 16735e03f663SWei Ni }; 16745e03f663SWei Ni 16755e03f663SWei Ni cooling-maps { 1676cbd0f000SWei Ni map0 { 1677cbd0f000SWei Ni trip = <&gpu_throttle_trip>; 1678cbd0f000SWei Ni cooling-device = <&throttle_heavy 1 1>; 1679cbd0f000SWei Ni }; 16805e03f663SWei Ni }; 1681e2bed1ebSWei Ni }; 168224fc3363SThierry Reding 1683e2bed1ebSWei Ni pllx { 1684e2bed1ebSWei Ni polling-delay-passive = <0>; 1685e2bed1ebSWei Ni polling-delay = <0>; 1686e2bed1ebSWei Ni 1687e2bed1ebSWei Ni thermal-sensors = 1688e2bed1ebSWei Ni <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>; 16895e03f663SWei Ni 16905e03f663SWei Ni trips { 16915e03f663SWei Ni pllx-shutdown-trip { 16925e03f663SWei Ni temperature = <103000>; 16935e03f663SWei Ni hysteresis = <0>; 16945e03f663SWei Ni type = "critical"; 16955e03f663SWei Ni }; 16965e03f663SWei Ni }; 16975e03f663SWei Ni 16985e03f663SWei Ni cooling-maps { 16995e03f663SWei Ni /* 17005e03f663SWei Ni * There are currently no cooling maps, 17015e03f663SWei Ni * because there are no cooling devices. 17025e03f663SWei Ni */ 17035e03f663SWei Ni }; 1704e2bed1ebSWei Ni }; 1705e2bed1ebSWei Ni }; 1706742af7e7SThierry Reding}; 1707