1b2441318SGreg Kroah-Hartman// SPDX-License-Identifier: GPL-2.0 2742af7e7SThierry Reding#include <dt-bindings/clock/tegra210-car.h> 3742af7e7SThierry Reding#include <dt-bindings/gpio/tegra-gpio.h> 4742af7e7SThierry Reding#include <dt-bindings/memory/tegra210-mc.h> 5742af7e7SThierry Reding#include <dt-bindings/pinctrl/pinctrl-tegra.h> 66641af7eSAapo Vienamo#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 72ceed593SJoseph Lo#include <dt-bindings/reset/tegra210-car.h> 8742af7e7SThierry Reding#include <dt-bindings/interrupt-controller/arm-gic.h> 9e2bed1ebSWei Ni#include <dt-bindings/thermal/tegra124-soctherm.h> 10359ae651SSowjanya Komatineni#include <dt-bindings/soc/tegra-pmc.h> 11742af7e7SThierry Reding 12742af7e7SThierry Reding/ { 13742af7e7SThierry Reding compatible = "nvidia,tegra210"; 14742af7e7SThierry Reding interrupt-parent = <&lic>; 15742af7e7SThierry Reding #address-cells = <2>; 16742af7e7SThierry Reding #size-cells = <2>; 17742af7e7SThierry Reding 18475d99fcSRob Herring pcie@1003000 { 19589a2d3fSThierry Reding compatible = "nvidia,tegra210-pcie"; 20589a2d3fSThierry Reding device_type = "pci"; 21589a2d3fSThierry Reding reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */ 22589a2d3fSThierry Reding 0x0 0x01003800 0x0 0x00000800 /* AFI registers */ 23589a2d3fSThierry Reding 0x0 0x02000000 0x0 0x10000000>; /* configuration space */ 24589a2d3fSThierry Reding reg-names = "pads", "afi", "cs"; 25589a2d3fSThierry Reding interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 26589a2d3fSThierry Reding <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 27589a2d3fSThierry Reding interrupt-names = "intr", "msi"; 28589a2d3fSThierry Reding 29589a2d3fSThierry Reding #interrupt-cells = <1>; 30589a2d3fSThierry Reding interrupt-map-mask = <0 0 0 0>; 31589a2d3fSThierry Reding interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 32589a2d3fSThierry Reding 33589a2d3fSThierry Reding bus-range = <0x00 0xff>; 34589a2d3fSThierry Reding #address-cells = <3>; 35589a2d3fSThierry Reding #size-cells = <2>; 36589a2d3fSThierry Reding 37589a2d3fSThierry Reding ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */ 38589a2d3fSThierry Reding 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */ 39589a2d3fSThierry Reding 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */ 40589a2d3fSThierry Reding 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */ 41589a2d3fSThierry Reding 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ 42589a2d3fSThierry Reding 43589a2d3fSThierry Reding clocks = <&tegra_car TEGRA210_CLK_PCIE>, 44589a2d3fSThierry Reding <&tegra_car TEGRA210_CLK_AFI>, 45589a2d3fSThierry Reding <&tegra_car TEGRA210_CLK_PLL_E>, 46589a2d3fSThierry Reding <&tegra_car TEGRA210_CLK_CML0>; 47589a2d3fSThierry Reding clock-names = "pex", "afi", "pll_e", "cml"; 48589a2d3fSThierry Reding resets = <&tegra_car 70>, 49589a2d3fSThierry Reding <&tegra_car 72>, 50589a2d3fSThierry Reding <&tegra_car 74>; 51589a2d3fSThierry Reding reset-names = "pex", "afi", "pcie_x"; 52871be845SManikanta Maddireddy 53871be845SManikanta Maddireddy pinctrl-names = "default", "idle"; 54871be845SManikanta Maddireddy pinctrl-0 = <&pex_dpd_disable>; 55871be845SManikanta Maddireddy pinctrl-1 = <&pex_dpd_enable>; 56871be845SManikanta Maddireddy 57589a2d3fSThierry Reding status = "disabled"; 58589a2d3fSThierry Reding 59589a2d3fSThierry Reding pci@1,0 { 60589a2d3fSThierry Reding device_type = "pci"; 61589a2d3fSThierry Reding assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>; 62589a2d3fSThierry Reding reg = <0x000800 0 0 0 0>; 63475d99fcSRob Herring bus-range = <0x00 0xff>; 64589a2d3fSThierry Reding status = "disabled"; 65589a2d3fSThierry Reding 66589a2d3fSThierry Reding #address-cells = <3>; 67589a2d3fSThierry Reding #size-cells = <2>; 68589a2d3fSThierry Reding ranges; 69589a2d3fSThierry Reding 70589a2d3fSThierry Reding nvidia,num-lanes = <4>; 71589a2d3fSThierry Reding }; 72589a2d3fSThierry Reding 73589a2d3fSThierry Reding pci@2,0 { 74589a2d3fSThierry Reding device_type = "pci"; 75589a2d3fSThierry Reding assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>; 76589a2d3fSThierry Reding reg = <0x001000 0 0 0 0>; 77475d99fcSRob Herring bus-range = <0x00 0xff>; 78589a2d3fSThierry Reding status = "disabled"; 79589a2d3fSThierry Reding 80589a2d3fSThierry Reding #address-cells = <3>; 81589a2d3fSThierry Reding #size-cells = <2>; 82589a2d3fSThierry Reding ranges; 83589a2d3fSThierry Reding 84589a2d3fSThierry Reding nvidia,num-lanes = <1>; 85589a2d3fSThierry Reding }; 86589a2d3fSThierry Reding }; 87589a2d3fSThierry Reding 88be70771dSThierry Reding host1x@50000000 { 89742af7e7SThierry Reding compatible = "nvidia,tegra210-host1x", "simple-bus"; 90742af7e7SThierry Reding reg = <0x0 0x50000000 0x0 0x00034000>; 91742af7e7SThierry Reding interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 92742af7e7SThierry Reding <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ 93052d3f65SThierry Reding interrupt-names = "syncpt", "host1x"; 94742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_HOST1X>; 95742af7e7SThierry Reding clock-names = "host1x"; 96742af7e7SThierry Reding resets = <&tegra_car 28>; 97742af7e7SThierry Reding reset-names = "host1x"; 98742af7e7SThierry Reding 99742af7e7SThierry Reding #address-cells = <2>; 100742af7e7SThierry Reding #size-cells = <2>; 101742af7e7SThierry Reding 102742af7e7SThierry Reding ranges = <0x0 0x54000000 0x0 0x54000000 0x0 0x01000000>; 103742af7e7SThierry Reding 104116503a6SMikko Perttunen iommus = <&mc TEGRA_SWGROUP_HC>; 105116503a6SMikko Perttunen 106be70771dSThierry Reding dpaux1: dpaux@54040000 { 107742af7e7SThierry Reding compatible = "nvidia,tegra210-dpaux"; 108742af7e7SThierry Reding reg = <0x0 0x54040000 0x0 0x00040000>; 109742af7e7SThierry Reding interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 110742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_DPAUX1>, 111742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_PLL_DP>; 112742af7e7SThierry Reding clock-names = "dpaux", "parent"; 113742af7e7SThierry Reding resets = <&tegra_car 207>; 114742af7e7SThierry Reding reset-names = "dpaux"; 11596d1f078SJon Hunter power-domains = <&pd_sor>; 116742af7e7SThierry Reding status = "disabled"; 11766b2d6e9SJon Hunter 11866b2d6e9SJon Hunter state_dpaux1_aux: pinmux-aux { 11966b2d6e9SJon Hunter groups = "dpaux-io"; 12066b2d6e9SJon Hunter function = "aux"; 12166b2d6e9SJon Hunter }; 12266b2d6e9SJon Hunter 12366b2d6e9SJon Hunter state_dpaux1_i2c: pinmux-i2c { 12466b2d6e9SJon Hunter groups = "dpaux-io"; 12566b2d6e9SJon Hunter function = "i2c"; 12666b2d6e9SJon Hunter }; 12766b2d6e9SJon Hunter 12866b2d6e9SJon Hunter state_dpaux1_off: pinmux-off { 12966b2d6e9SJon Hunter groups = "dpaux-io"; 13066b2d6e9SJon Hunter function = "off"; 13166b2d6e9SJon Hunter }; 13266b2d6e9SJon Hunter 13366b2d6e9SJon Hunter i2c-bus { 13466b2d6e9SJon Hunter #address-cells = <1>; 13566b2d6e9SJon Hunter #size-cells = <0>; 13666b2d6e9SJon Hunter }; 137742af7e7SThierry Reding }; 138742af7e7SThierry Reding 139be70771dSThierry Reding vi@54080000 { 140742af7e7SThierry Reding compatible = "nvidia,tegra210-vi"; 141c4153885SSowjanya Komatineni reg = <0x0 0x54080000 0x0 0x700>; 142742af7e7SThierry Reding interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 143742af7e7SThierry Reding status = "disabled"; 144c4153885SSowjanya Komatineni assigned-clocks = <&tegra_car TEGRA210_CLK_VI>; 145c4153885SSowjanya Komatineni assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 146c4153885SSowjanya Komatineni 147c4153885SSowjanya Komatineni clocks = <&tegra_car TEGRA210_CLK_VI>; 148c4153885SSowjanya Komatineni power-domains = <&pd_venc>; 149c4153885SSowjanya Komatineni 150c4153885SSowjanya Komatineni #address-cells = <1>; 151c4153885SSowjanya Komatineni #size-cells = <1>; 152c4153885SSowjanya Komatineni 153c4153885SSowjanya Komatineni ranges = <0x0 0x0 0x54080000 0x2000>; 154c4153885SSowjanya Komatineni 155c4153885SSowjanya Komatineni csi@838 { 156c4153885SSowjanya Komatineni compatible = "nvidia,tegra210-csi"; 157c4153885SSowjanya Komatineni reg = <0x838 0x1300>; 158c4153885SSowjanya Komatineni status = "disabled"; 159c4153885SSowjanya Komatineni assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>, 160c4153885SSowjanya Komatineni <&tegra_car TEGRA210_CLK_CILCD>, 161c4153885SSowjanya Komatineni <&tegra_car TEGRA210_CLK_CILE>, 162c4153885SSowjanya Komatineni <&tegra_car TEGRA210_CLK_CSI_TPG>; 163c4153885SSowjanya Komatineni assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>, 164c4153885SSowjanya Komatineni <&tegra_car TEGRA210_CLK_PLL_P>, 165c4153885SSowjanya Komatineni <&tegra_car TEGRA210_CLK_PLL_P>; 166c4153885SSowjanya Komatineni assigned-clock-rates = <102000000>, 167c4153885SSowjanya Komatineni <102000000>, 168c4153885SSowjanya Komatineni <102000000>, 169c4153885SSowjanya Komatineni <972000000>; 170c4153885SSowjanya Komatineni 171c4153885SSowjanya Komatineni clocks = <&tegra_car TEGRA210_CLK_CSI>, 172c4153885SSowjanya Komatineni <&tegra_car TEGRA210_CLK_CILAB>, 173c4153885SSowjanya Komatineni <&tegra_car TEGRA210_CLK_CILCD>, 174c4153885SSowjanya Komatineni <&tegra_car TEGRA210_CLK_CILE>, 175c4153885SSowjanya Komatineni <&tegra_car TEGRA210_CLK_CSI_TPG>; 176c4153885SSowjanya Komatineni clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg"; 177c4153885SSowjanya Komatineni power-domains = <&pd_sor>; 178c4153885SSowjanya Komatineni }; 179742af7e7SThierry Reding }; 180742af7e7SThierry Reding 181be70771dSThierry Reding tsec@54100000 { 182742af7e7SThierry Reding compatible = "nvidia,tegra210-tsec"; 183742af7e7SThierry Reding reg = <0x0 0x54100000 0x0 0x00040000>; 184742af7e7SThierry Reding }; 185742af7e7SThierry Reding 186be70771dSThierry Reding dc@54200000 { 187742af7e7SThierry Reding compatible = "nvidia,tegra210-dc"; 188742af7e7SThierry Reding reg = <0x0 0x54200000 0x0 0x00040000>; 189742af7e7SThierry Reding interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 190742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_DISP1>, 191742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_PLL_P>; 192742af7e7SThierry Reding clock-names = "dc", "parent"; 193742af7e7SThierry Reding resets = <&tegra_car 27>; 194742af7e7SThierry Reding reset-names = "dc"; 195742af7e7SThierry Reding 196742af7e7SThierry Reding iommus = <&mc TEGRA_SWGROUP_DC>; 197742af7e7SThierry Reding 198742af7e7SThierry Reding nvidia,head = <0>; 199742af7e7SThierry Reding }; 200742af7e7SThierry Reding 201be70771dSThierry Reding dc@54240000 { 202742af7e7SThierry Reding compatible = "nvidia,tegra210-dc"; 203742af7e7SThierry Reding reg = <0x0 0x54240000 0x0 0x00040000>; 204742af7e7SThierry Reding interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 205742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_DISP2>, 206742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_PLL_P>; 207742af7e7SThierry Reding clock-names = "dc", "parent"; 208742af7e7SThierry Reding resets = <&tegra_car 26>; 209742af7e7SThierry Reding reset-names = "dc"; 210742af7e7SThierry Reding 211742af7e7SThierry Reding iommus = <&mc TEGRA_SWGROUP_DCB>; 212742af7e7SThierry Reding 213742af7e7SThierry Reding nvidia,head = <1>; 214742af7e7SThierry Reding }; 215742af7e7SThierry Reding 216be70771dSThierry Reding dsi@54300000 { 217742af7e7SThierry Reding compatible = "nvidia,tegra210-dsi"; 218742af7e7SThierry Reding reg = <0x0 0x54300000 0x0 0x00040000>; 219742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_DSIA>, 220742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_DSIALP>, 221742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; 222742af7e7SThierry Reding clock-names = "dsi", "lp", "parent"; 223742af7e7SThierry Reding resets = <&tegra_car 48>; 224742af7e7SThierry Reding reset-names = "dsi"; 22596d1f078SJon Hunter power-domains = <&pd_sor>; 226742af7e7SThierry Reding nvidia,mipi-calibrate = <&mipi 0x0c0>; /* DSIA & DSIB pads */ 227742af7e7SThierry Reding 228742af7e7SThierry Reding status = "disabled"; 229742af7e7SThierry Reding 230742af7e7SThierry Reding #address-cells = <1>; 231742af7e7SThierry Reding #size-cells = <0>; 232742af7e7SThierry Reding }; 233742af7e7SThierry Reding 234be70771dSThierry Reding vic@54340000 { 235742af7e7SThierry Reding compatible = "nvidia,tegra210-vic"; 236742af7e7SThierry Reding reg = <0x0 0x54340000 0x0 0x00040000>; 23724963d1bSMikko Perttunen interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 23824963d1bSMikko Perttunen clocks = <&tegra_car TEGRA210_CLK_VIC03>; 23924963d1bSMikko Perttunen clock-names = "vic"; 24024963d1bSMikko Perttunen resets = <&tegra_car 178>; 24124963d1bSMikko Perttunen reset-names = "vic"; 24224963d1bSMikko Perttunen 24324963d1bSMikko Perttunen iommus = <&mc TEGRA_SWGROUP_VIC>; 24424963d1bSMikko Perttunen power-domains = <&pd_vic>; 245742af7e7SThierry Reding }; 246742af7e7SThierry Reding 247be70771dSThierry Reding nvjpg@54380000 { 248742af7e7SThierry Reding compatible = "nvidia,tegra210-nvjpg"; 249742af7e7SThierry Reding reg = <0x0 0x54380000 0x0 0x00040000>; 250742af7e7SThierry Reding status = "disabled"; 251742af7e7SThierry Reding }; 252742af7e7SThierry Reding 253be70771dSThierry Reding dsi@54400000 { 254742af7e7SThierry Reding compatible = "nvidia,tegra210-dsi"; 255742af7e7SThierry Reding reg = <0x0 0x54400000 0x0 0x00040000>; 256742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_DSIB>, 257742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_DSIBLP>, 258742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; 259742af7e7SThierry Reding clock-names = "dsi", "lp", "parent"; 260742af7e7SThierry Reding resets = <&tegra_car 82>; 261742af7e7SThierry Reding reset-names = "dsi"; 26296d1f078SJon Hunter power-domains = <&pd_sor>; 263742af7e7SThierry Reding nvidia,mipi-calibrate = <&mipi 0x300>; /* DSIC & DSID pads */ 264742af7e7SThierry Reding 265742af7e7SThierry Reding status = "disabled"; 266742af7e7SThierry Reding 267742af7e7SThierry Reding #address-cells = <1>; 268742af7e7SThierry Reding #size-cells = <0>; 269742af7e7SThierry Reding }; 270742af7e7SThierry Reding 271be70771dSThierry Reding nvdec@54480000 { 272742af7e7SThierry Reding compatible = "nvidia,tegra210-nvdec"; 273742af7e7SThierry Reding reg = <0x0 0x54480000 0x0 0x00040000>; 274742af7e7SThierry Reding status = "disabled"; 275742af7e7SThierry Reding }; 276742af7e7SThierry Reding 277be70771dSThierry Reding nvenc@544c0000 { 278742af7e7SThierry Reding compatible = "nvidia,tegra210-nvenc"; 279742af7e7SThierry Reding reg = <0x0 0x544c0000 0x0 0x00040000>; 280742af7e7SThierry Reding status = "disabled"; 281742af7e7SThierry Reding }; 282742af7e7SThierry Reding 283be70771dSThierry Reding tsec@54500000 { 284742af7e7SThierry Reding compatible = "nvidia,tegra210-tsec"; 285742af7e7SThierry Reding reg = <0x0 0x54500000 0x0 0x00040000>; 286742af7e7SThierry Reding status = "disabled"; 287742af7e7SThierry Reding }; 288742af7e7SThierry Reding 289be70771dSThierry Reding sor@54540000 { 290742af7e7SThierry Reding compatible = "nvidia,tegra210-sor"; 291742af7e7SThierry Reding reg = <0x0 0x54540000 0x0 0x00040000>; 292742af7e7SThierry Reding interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 293742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_SOR0>, 294ed93a666SThierry Reding <&tegra_car TEGRA210_CLK_SOR0_OUT>, 295742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_PLL_D_OUT0>, 296742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_PLL_DP>, 297742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_SOR_SAFE>; 298ed93a666SThierry Reding clock-names = "sor", "out", "parent", "dp", "safe"; 299742af7e7SThierry Reding resets = <&tegra_car 182>; 300742af7e7SThierry Reding reset-names = "sor"; 30166b2d6e9SJon Hunter pinctrl-0 = <&state_dpaux_aux>; 30266b2d6e9SJon Hunter pinctrl-1 = <&state_dpaux_i2c>; 30366b2d6e9SJon Hunter pinctrl-2 = <&state_dpaux_off>; 30466b2d6e9SJon Hunter pinctrl-names = "aux", "i2c", "off"; 30596d1f078SJon Hunter power-domains = <&pd_sor>; 306742af7e7SThierry Reding status = "disabled"; 307742af7e7SThierry Reding }; 308742af7e7SThierry Reding 309be70771dSThierry Reding sor@54580000 { 310742af7e7SThierry Reding compatible = "nvidia,tegra210-sor1"; 311742af7e7SThierry Reding reg = <0x0 0x54580000 0x0 0x00040000>; 312742af7e7SThierry Reding interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 313742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_SOR1>, 31450f5b841SThierry Reding <&tegra_car TEGRA210_CLK_SOR1_OUT>, 315742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_PLL_D2_OUT0>, 316742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_PLL_DP>, 317742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_SOR_SAFE>; 31850f5b841SThierry Reding clock-names = "sor", "out", "parent", "dp", "safe"; 319742af7e7SThierry Reding resets = <&tegra_car 183>; 320742af7e7SThierry Reding reset-names = "sor"; 32166b2d6e9SJon Hunter pinctrl-0 = <&state_dpaux1_aux>; 32266b2d6e9SJon Hunter pinctrl-1 = <&state_dpaux1_i2c>; 32366b2d6e9SJon Hunter pinctrl-2 = <&state_dpaux1_off>; 32466b2d6e9SJon Hunter pinctrl-names = "aux", "i2c", "off"; 32596d1f078SJon Hunter power-domains = <&pd_sor>; 326742af7e7SThierry Reding status = "disabled"; 327742af7e7SThierry Reding }; 328742af7e7SThierry Reding 329be70771dSThierry Reding dpaux: dpaux@545c0000 { 330742af7e7SThierry Reding compatible = "nvidia,tegra124-dpaux"; 331742af7e7SThierry Reding reg = <0x0 0x545c0000 0x0 0x00040000>; 332742af7e7SThierry Reding interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 333742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_DPAUX>, 334742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_PLL_DP>; 335742af7e7SThierry Reding clock-names = "dpaux", "parent"; 336742af7e7SThierry Reding resets = <&tegra_car 181>; 337742af7e7SThierry Reding reset-names = "dpaux"; 33896d1f078SJon Hunter power-domains = <&pd_sor>; 339742af7e7SThierry Reding status = "disabled"; 34066b2d6e9SJon Hunter 34166b2d6e9SJon Hunter state_dpaux_aux: pinmux-aux { 34266b2d6e9SJon Hunter groups = "dpaux-io"; 34366b2d6e9SJon Hunter function = "aux"; 34466b2d6e9SJon Hunter }; 34566b2d6e9SJon Hunter 34666b2d6e9SJon Hunter state_dpaux_i2c: pinmux-i2c { 34766b2d6e9SJon Hunter groups = "dpaux-io"; 34866b2d6e9SJon Hunter function = "i2c"; 34966b2d6e9SJon Hunter }; 35066b2d6e9SJon Hunter 35166b2d6e9SJon Hunter state_dpaux_off: pinmux-off { 35266b2d6e9SJon Hunter groups = "dpaux-io"; 35366b2d6e9SJon Hunter function = "off"; 35466b2d6e9SJon Hunter }; 35566b2d6e9SJon Hunter 35666b2d6e9SJon Hunter i2c-bus { 35766b2d6e9SJon Hunter #address-cells = <1>; 35866b2d6e9SJon Hunter #size-cells = <0>; 35966b2d6e9SJon Hunter }; 360742af7e7SThierry Reding }; 361742af7e7SThierry Reding 362be70771dSThierry Reding isp@54600000 { 363742af7e7SThierry Reding compatible = "nvidia,tegra210-isp"; 364742af7e7SThierry Reding reg = <0x0 0x54600000 0x0 0x00040000>; 365742af7e7SThierry Reding interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 366742af7e7SThierry Reding status = "disabled"; 367742af7e7SThierry Reding }; 368742af7e7SThierry Reding 369be70771dSThierry Reding isp@54680000 { 370742af7e7SThierry Reding compatible = "nvidia,tegra210-isp"; 371742af7e7SThierry Reding reg = <0x0 0x54680000 0x0 0x00040000>; 372742af7e7SThierry Reding interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 373742af7e7SThierry Reding status = "disabled"; 374742af7e7SThierry Reding }; 375742af7e7SThierry Reding 376be70771dSThierry Reding i2c@546c0000 { 377742af7e7SThierry Reding compatible = "nvidia,tegra210-i2c-vi"; 378742af7e7SThierry Reding reg = <0x0 0x546c0000 0x0 0x00040000>; 379742af7e7SThierry Reding interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 380742af7e7SThierry Reding status = "disabled"; 381742af7e7SThierry Reding }; 382742af7e7SThierry Reding }; 383742af7e7SThierry Reding 384be70771dSThierry Reding gic: interrupt-controller@50041000 { 385742af7e7SThierry Reding compatible = "arm,gic-400"; 386742af7e7SThierry Reding #interrupt-cells = <3>; 387742af7e7SThierry Reding interrupt-controller; 388742af7e7SThierry Reding reg = <0x0 0x50041000 0x0 0x1000>, 389742af7e7SThierry Reding <0x0 0x50042000 0x0 0x2000>, 390742af7e7SThierry Reding <0x0 0x50044000 0x0 0x2000>, 391742af7e7SThierry Reding <0x0 0x50046000 0x0 0x2000>; 392742af7e7SThierry Reding interrupts = <GIC_PPI 9 393742af7e7SThierry Reding (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 394742af7e7SThierry Reding interrupt-parent = <&gic>; 395742af7e7SThierry Reding }; 396742af7e7SThierry Reding 397be70771dSThierry Reding gpu@57000000 { 398742af7e7SThierry Reding compatible = "nvidia,gm20b"; 399742af7e7SThierry Reding reg = <0x0 0x57000000 0x0 0x01000000>, 400742af7e7SThierry Reding <0x0 0x58000000 0x0 0x01000000>; 401742af7e7SThierry Reding interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 402742af7e7SThierry Reding <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 403742af7e7SThierry Reding interrupt-names = "stall", "nonstall"; 404742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_GPU>, 4054a0778e9SAlexandre Courbot <&tegra_car TEGRA210_CLK_PLL_P_OUT5>, 4064a0778e9SAlexandre Courbot <&tegra_car TEGRA210_CLK_PLL_G_REF>; 4074a0778e9SAlexandre Courbot clock-names = "gpu", "pwr", "ref"; 408742af7e7SThierry Reding resets = <&tegra_car 184>; 409742af7e7SThierry Reding reset-names = "gpu"; 41030f949bcSAlexandre Courbot 41130f949bcSAlexandre Courbot iommus = <&mc TEGRA_SWGROUP_GPU>; 41230f949bcSAlexandre Courbot 413742af7e7SThierry Reding status = "disabled"; 414742af7e7SThierry Reding }; 415742af7e7SThierry Reding 416be70771dSThierry Reding lic: interrupt-controller@60004000 { 417742af7e7SThierry Reding compatible = "nvidia,tegra210-ictlr"; 418742af7e7SThierry Reding reg = <0x0 0x60004000 0x0 0x40>, /* primary controller */ 419742af7e7SThierry Reding <0x0 0x60004100 0x0 0x40>, /* secondary controller */ 420742af7e7SThierry Reding <0x0 0x60004200 0x0 0x40>, /* tertiary controller */ 421742af7e7SThierry Reding <0x0 0x60004300 0x0 0x40>, /* quaternary controller */ 422742af7e7SThierry Reding <0x0 0x60004400 0x0 0x40>, /* quinary controller */ 423742af7e7SThierry Reding <0x0 0x60004500 0x0 0x40>; /* senary controller */ 424742af7e7SThierry Reding interrupt-controller; 425742af7e7SThierry Reding #interrupt-cells = <3>; 426742af7e7SThierry Reding interrupt-parent = <&gic>; 427742af7e7SThierry Reding }; 428742af7e7SThierry Reding 429be70771dSThierry Reding timer@60005000 { 430d9931a18SJoseph Lo compatible = "nvidia,tegra210-timer"; 431742af7e7SThierry Reding reg = <0x0 0x60005000 0x0 0x400>; 432d9931a18SJoseph Lo interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 433d9931a18SJoseph Lo <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 434742af7e7SThierry Reding <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 435742af7e7SThierry Reding <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 436742af7e7SThierry Reding <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 437742af7e7SThierry Reding <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 438d9931a18SJoseph Lo <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 439d9931a18SJoseph Lo <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 440d9931a18SJoseph Lo <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 441d9931a18SJoseph Lo <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 442d9931a18SJoseph Lo <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 443d9931a18SJoseph Lo <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 444d9931a18SJoseph Lo <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, 445d9931a18SJoseph Lo <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 446742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_TIMER>; 447742af7e7SThierry Reding clock-names = "timer"; 448742af7e7SThierry Reding }; 449742af7e7SThierry Reding 450be70771dSThierry Reding tegra_car: clock@60006000 { 451742af7e7SThierry Reding compatible = "nvidia,tegra210-car"; 452742af7e7SThierry Reding reg = <0x0 0x60006000 0x0 0x1000>; 453742af7e7SThierry Reding #clock-cells = <1>; 454742af7e7SThierry Reding #reset-cells = <1>; 455742af7e7SThierry Reding }; 456742af7e7SThierry Reding 457be70771dSThierry Reding flow-controller@60007000 { 458742af7e7SThierry Reding compatible = "nvidia,tegra210-flowctrl"; 459742af7e7SThierry Reding reg = <0x0 0x60007000 0x0 0x1000>; 460742af7e7SThierry Reding }; 461742af7e7SThierry Reding 462be70771dSThierry Reding gpio: gpio@6000d000 { 46301665512SStephen Warren compatible = "nvidia,tegra210-gpio", "nvidia,tegra30-gpio"; 464742af7e7SThierry Reding reg = <0x0 0x6000d000 0x0 0x1000>; 465742af7e7SThierry Reding interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 466742af7e7SThierry Reding <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 467742af7e7SThierry Reding <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 468742af7e7SThierry Reding <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 469742af7e7SThierry Reding <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 470742af7e7SThierry Reding <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 471742af7e7SThierry Reding <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 472742af7e7SThierry Reding <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 473742af7e7SThierry Reding #gpio-cells = <2>; 474742af7e7SThierry Reding gpio-controller; 475742af7e7SThierry Reding #interrupt-cells = <2>; 476742af7e7SThierry Reding interrupt-controller; 477742af7e7SThierry Reding }; 478742af7e7SThierry Reding 479be70771dSThierry Reding apbdma: dma@60020000 { 480742af7e7SThierry Reding compatible = "nvidia,tegra210-apbdma", "nvidia,tegra148-apbdma"; 481742af7e7SThierry Reding reg = <0x0 0x60020000 0x0 0x1400>; 482742af7e7SThierry Reding interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 483742af7e7SThierry Reding <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 484742af7e7SThierry Reding <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 485742af7e7SThierry Reding <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 486742af7e7SThierry Reding <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 487742af7e7SThierry Reding <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 488742af7e7SThierry Reding <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 489742af7e7SThierry Reding <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 490742af7e7SThierry Reding <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 491742af7e7SThierry Reding <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 492742af7e7SThierry Reding <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 493742af7e7SThierry Reding <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 494742af7e7SThierry Reding <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 495742af7e7SThierry Reding <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 496742af7e7SThierry Reding <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 497742af7e7SThierry Reding <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 498742af7e7SThierry Reding <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 499742af7e7SThierry Reding <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 500742af7e7SThierry Reding <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 501742af7e7SThierry Reding <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 502742af7e7SThierry Reding <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 503742af7e7SThierry Reding <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 504742af7e7SThierry Reding <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 505742af7e7SThierry Reding <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 506742af7e7SThierry Reding <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 507742af7e7SThierry Reding <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 508742af7e7SThierry Reding <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 509742af7e7SThierry Reding <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 510742af7e7SThierry Reding <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 511742af7e7SThierry Reding <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 512742af7e7SThierry Reding <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 513742af7e7SThierry Reding <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 514742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_APBDMA>; 515742af7e7SThierry Reding clock-names = "dma"; 516742af7e7SThierry Reding resets = <&tegra_car 34>; 517742af7e7SThierry Reding reset-names = "dma"; 518742af7e7SThierry Reding #dma-cells = <1>; 519742af7e7SThierry Reding }; 520742af7e7SThierry Reding 521be70771dSThierry Reding apbmisc@70000800 { 522742af7e7SThierry Reding compatible = "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc"; 523742af7e7SThierry Reding reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */ 52446e4b227SJoseph Lo <0x0 0x70000008 0x0 0x04>; /* Strapping options */ 525742af7e7SThierry Reding }; 526742af7e7SThierry Reding 527be70771dSThierry Reding pinmux: pinmux@700008d4 { 528742af7e7SThierry Reding compatible = "nvidia,tegra210-pinmux"; 529742af7e7SThierry Reding reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */ 530742af7e7SThierry Reding <0x0 0x70003000 0x0 0x294>; /* Mux registers */ 5314e0f1229SSowjanya Komatineni sdmmc1_3v3_drv: sdmmc1-3v3-drv { 5324e0f1229SSowjanya Komatineni sdmmc1 { 5334e0f1229SSowjanya Komatineni nvidia,pins = "drive_sdmmc1"; 5344e0f1229SSowjanya Komatineni nvidia,pull-down-strength = <0x8>; 5354e0f1229SSowjanya Komatineni nvidia,pull-up-strength = <0x8>; 5364e0f1229SSowjanya Komatineni }; 5374e0f1229SSowjanya Komatineni }; 5384e0f1229SSowjanya Komatineni sdmmc1_1v8_drv: sdmmc1-1v8-drv { 5394e0f1229SSowjanya Komatineni sdmmc1 { 5404e0f1229SSowjanya Komatineni nvidia,pins = "drive_sdmmc1"; 5414e0f1229SSowjanya Komatineni nvidia,pull-down-strength = <0x4>; 5424e0f1229SSowjanya Komatineni nvidia,pull-up-strength = <0x3>; 5434e0f1229SSowjanya Komatineni }; 5444e0f1229SSowjanya Komatineni }; 5454e0f1229SSowjanya Komatineni sdmmc2_1v8_drv: sdmmc2-1v8-drv { 5464e0f1229SSowjanya Komatineni sdmmc2 { 5474e0f1229SSowjanya Komatineni nvidia,pins = "drive_sdmmc2"; 5484e0f1229SSowjanya Komatineni nvidia,pull-down-strength = <0x10>; 5494e0f1229SSowjanya Komatineni nvidia,pull-up-strength = <0x10>; 5504e0f1229SSowjanya Komatineni }; 5514e0f1229SSowjanya Komatineni }; 5524e0f1229SSowjanya Komatineni sdmmc3_3v3_drv: sdmmc3-3v3-drv { 5534e0f1229SSowjanya Komatineni sdmmc3 { 5544e0f1229SSowjanya Komatineni nvidia,pins = "drive_sdmmc3"; 5554e0f1229SSowjanya Komatineni nvidia,pull-down-strength = <0x8>; 5564e0f1229SSowjanya Komatineni nvidia,pull-up-strength = <0x8>; 5574e0f1229SSowjanya Komatineni }; 5584e0f1229SSowjanya Komatineni }; 5594e0f1229SSowjanya Komatineni sdmmc3_1v8_drv: sdmmc3-1v8-drv { 5604e0f1229SSowjanya Komatineni sdmmc3 { 5614e0f1229SSowjanya Komatineni nvidia,pins = "drive_sdmmc3"; 5624e0f1229SSowjanya Komatineni nvidia,pull-down-strength = <0x4>; 5634e0f1229SSowjanya Komatineni nvidia,pull-up-strength = <0x3>; 5644e0f1229SSowjanya Komatineni }; 5654e0f1229SSowjanya Komatineni }; 5664e0f1229SSowjanya Komatineni sdmmc4_1v8_drv: sdmmc4-1v8-drv { 5674e0f1229SSowjanya Komatineni sdmmc4 { 5684e0f1229SSowjanya Komatineni nvidia,pins = "drive_sdmmc4"; 5694e0f1229SSowjanya Komatineni nvidia,pull-down-strength = <0x10>; 5704e0f1229SSowjanya Komatineni nvidia,pull-up-strength = <0x10>; 5714e0f1229SSowjanya Komatineni }; 5724e0f1229SSowjanya Komatineni }; 573742af7e7SThierry Reding }; 574742af7e7SThierry Reding 575742af7e7SThierry Reding /* 576742af7e7SThierry Reding * There are two serial driver i.e. 8250 based simple serial 577742af7e7SThierry Reding * driver and APB DMA based serial driver for higher baudrate 578ef769e32SAdam Buchbinder * and performance. To enable the 8250 based driver, the compatible 579742af7e7SThierry Reding * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable 58068cd8b2eSThierry Reding * the APB DMA based serial driver, the compatible is 581742af7e7SThierry Reding * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". 582742af7e7SThierry Reding */ 583be70771dSThierry Reding uarta: serial@70006000 { 584742af7e7SThierry Reding compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 585742af7e7SThierry Reding reg = <0x0 0x70006000 0x0 0x40>; 586742af7e7SThierry Reding reg-shift = <2>; 587742af7e7SThierry Reding interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 588742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_UARTA>; 589742af7e7SThierry Reding clock-names = "serial"; 590742af7e7SThierry Reding resets = <&tegra_car 6>; 591742af7e7SThierry Reding reset-names = "serial"; 592742af7e7SThierry Reding dmas = <&apbdma 8>, <&apbdma 8>; 593742af7e7SThierry Reding dma-names = "rx", "tx"; 594742af7e7SThierry Reding status = "disabled"; 595742af7e7SThierry Reding }; 596742af7e7SThierry Reding 597be70771dSThierry Reding uartb: serial@70006040 { 598742af7e7SThierry Reding compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 599742af7e7SThierry Reding reg = <0x0 0x70006040 0x0 0x40>; 600742af7e7SThierry Reding reg-shift = <2>; 601742af7e7SThierry Reding interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 602742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_UARTB>; 603742af7e7SThierry Reding clock-names = "serial"; 604742af7e7SThierry Reding resets = <&tegra_car 7>; 605742af7e7SThierry Reding reset-names = "serial"; 606742af7e7SThierry Reding dmas = <&apbdma 9>, <&apbdma 9>; 607742af7e7SThierry Reding dma-names = "rx", "tx"; 608742af7e7SThierry Reding status = "disabled"; 609742af7e7SThierry Reding }; 610742af7e7SThierry Reding 611be70771dSThierry Reding uartc: serial@70006200 { 612742af7e7SThierry Reding compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 613742af7e7SThierry Reding reg = <0x0 0x70006200 0x0 0x40>; 614742af7e7SThierry Reding reg-shift = <2>; 615742af7e7SThierry Reding interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 616742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_UARTC>; 617742af7e7SThierry Reding clock-names = "serial"; 618742af7e7SThierry Reding resets = <&tegra_car 55>; 619742af7e7SThierry Reding reset-names = "serial"; 620742af7e7SThierry Reding dmas = <&apbdma 10>, <&apbdma 10>; 621742af7e7SThierry Reding dma-names = "rx", "tx"; 622742af7e7SThierry Reding status = "disabled"; 623742af7e7SThierry Reding }; 624742af7e7SThierry Reding 625be70771dSThierry Reding uartd: serial@70006300 { 626742af7e7SThierry Reding compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 627742af7e7SThierry Reding reg = <0x0 0x70006300 0x0 0x40>; 628742af7e7SThierry Reding reg-shift = <2>; 629742af7e7SThierry Reding interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 630742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_UARTD>; 631742af7e7SThierry Reding clock-names = "serial"; 632742af7e7SThierry Reding resets = <&tegra_car 65>; 633742af7e7SThierry Reding reset-names = "serial"; 634742af7e7SThierry Reding dmas = <&apbdma 19>, <&apbdma 19>; 635742af7e7SThierry Reding dma-names = "rx", "tx"; 636742af7e7SThierry Reding status = "disabled"; 637742af7e7SThierry Reding }; 638742af7e7SThierry Reding 639be70771dSThierry Reding pwm: pwm@7000a000 { 640742af7e7SThierry Reding compatible = "nvidia,tegra210-pwm", "nvidia,tegra20-pwm"; 641742af7e7SThierry Reding reg = <0x0 0x7000a000 0x0 0x100>; 642742af7e7SThierry Reding #pwm-cells = <2>; 643742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_PWM>; 644742af7e7SThierry Reding clock-names = "pwm"; 645742af7e7SThierry Reding resets = <&tegra_car 17>; 646742af7e7SThierry Reding reset-names = "pwm"; 647742af7e7SThierry Reding status = "disabled"; 648742af7e7SThierry Reding }; 649742af7e7SThierry Reding 650be70771dSThierry Reding i2c@7000c000 { 651140723b9SSowjanya Komatineni compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 652742af7e7SThierry Reding reg = <0x0 0x7000c000 0x0 0x100>; 653742af7e7SThierry Reding interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 654742af7e7SThierry Reding #address-cells = <1>; 655742af7e7SThierry Reding #size-cells = <0>; 656742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_I2C1>; 657742af7e7SThierry Reding clock-names = "div-clk"; 658742af7e7SThierry Reding resets = <&tegra_car 12>; 659742af7e7SThierry Reding reset-names = "i2c"; 660742af7e7SThierry Reding dmas = <&apbdma 21>, <&apbdma 21>; 661742af7e7SThierry Reding dma-names = "rx", "tx"; 662742af7e7SThierry Reding status = "disabled"; 663742af7e7SThierry Reding }; 664742af7e7SThierry Reding 665be70771dSThierry Reding i2c@7000c400 { 666140723b9SSowjanya Komatineni compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 667742af7e7SThierry Reding reg = <0x0 0x7000c400 0x0 0x100>; 668742af7e7SThierry Reding interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 669742af7e7SThierry Reding #address-cells = <1>; 670742af7e7SThierry Reding #size-cells = <0>; 671742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_I2C2>; 672742af7e7SThierry Reding clock-names = "div-clk"; 673742af7e7SThierry Reding resets = <&tegra_car 54>; 674742af7e7SThierry Reding reset-names = "i2c"; 675742af7e7SThierry Reding dmas = <&apbdma 22>, <&apbdma 22>; 676742af7e7SThierry Reding dma-names = "rx", "tx"; 677742af7e7SThierry Reding status = "disabled"; 678742af7e7SThierry Reding }; 679742af7e7SThierry Reding 680be70771dSThierry Reding i2c@7000c500 { 681140723b9SSowjanya Komatineni compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 682742af7e7SThierry Reding reg = <0x0 0x7000c500 0x0 0x100>; 683742af7e7SThierry Reding interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 684742af7e7SThierry Reding #address-cells = <1>; 685742af7e7SThierry Reding #size-cells = <0>; 686742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_I2C3>; 687742af7e7SThierry Reding clock-names = "div-clk"; 688742af7e7SThierry Reding resets = <&tegra_car 67>; 689742af7e7SThierry Reding reset-names = "i2c"; 690742af7e7SThierry Reding dmas = <&apbdma 23>, <&apbdma 23>; 691742af7e7SThierry Reding dma-names = "rx", "tx"; 692742af7e7SThierry Reding status = "disabled"; 693742af7e7SThierry Reding }; 694742af7e7SThierry Reding 695be70771dSThierry Reding i2c@7000c700 { 696140723b9SSowjanya Komatineni compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 697742af7e7SThierry Reding reg = <0x0 0x7000c700 0x0 0x100>; 698742af7e7SThierry Reding interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 699742af7e7SThierry Reding #address-cells = <1>; 700742af7e7SThierry Reding #size-cells = <0>; 701742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_I2C4>; 702742af7e7SThierry Reding clock-names = "div-clk"; 703742af7e7SThierry Reding resets = <&tegra_car 103>; 704742af7e7SThierry Reding reset-names = "i2c"; 705742af7e7SThierry Reding dmas = <&apbdma 26>, <&apbdma 26>; 706742af7e7SThierry Reding dma-names = "rx", "tx"; 70766b2d6e9SJon Hunter pinctrl-0 = <&state_dpaux1_i2c>; 70866b2d6e9SJon Hunter pinctrl-1 = <&state_dpaux1_off>; 70966b2d6e9SJon Hunter pinctrl-names = "default", "idle"; 710742af7e7SThierry Reding status = "disabled"; 711742af7e7SThierry Reding }; 712742af7e7SThierry Reding 713be70771dSThierry Reding i2c@7000d000 { 714140723b9SSowjanya Komatineni compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 715742af7e7SThierry Reding reg = <0x0 0x7000d000 0x0 0x100>; 716742af7e7SThierry Reding interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 717742af7e7SThierry Reding #address-cells = <1>; 718742af7e7SThierry Reding #size-cells = <0>; 719742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_I2C5>; 720742af7e7SThierry Reding clock-names = "div-clk"; 721742af7e7SThierry Reding resets = <&tegra_car 47>; 722742af7e7SThierry Reding reset-names = "i2c"; 723742af7e7SThierry Reding dmas = <&apbdma 24>, <&apbdma 24>; 724742af7e7SThierry Reding dma-names = "rx", "tx"; 725742af7e7SThierry Reding status = "disabled"; 726742af7e7SThierry Reding }; 727742af7e7SThierry Reding 728be70771dSThierry Reding i2c@7000d100 { 729140723b9SSowjanya Komatineni compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 730742af7e7SThierry Reding reg = <0x0 0x7000d100 0x0 0x100>; 731742af7e7SThierry Reding interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 732742af7e7SThierry Reding #address-cells = <1>; 733742af7e7SThierry Reding #size-cells = <0>; 734742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_I2C6>; 735742af7e7SThierry Reding clock-names = "div-clk"; 736742af7e7SThierry Reding resets = <&tegra_car 166>; 737742af7e7SThierry Reding reset-names = "i2c"; 738742af7e7SThierry Reding dmas = <&apbdma 30>, <&apbdma 30>; 739742af7e7SThierry Reding dma-names = "rx", "tx"; 74066b2d6e9SJon Hunter pinctrl-0 = <&state_dpaux_i2c>; 74166b2d6e9SJon Hunter pinctrl-1 = <&state_dpaux_off>; 74266b2d6e9SJon Hunter pinctrl-names = "default", "idle"; 743742af7e7SThierry Reding status = "disabled"; 744742af7e7SThierry Reding }; 745742af7e7SThierry Reding 746be70771dSThierry Reding spi@7000d400 { 747742af7e7SThierry Reding compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 748742af7e7SThierry Reding reg = <0x0 0x7000d400 0x0 0x200>; 749742af7e7SThierry Reding interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 750742af7e7SThierry Reding #address-cells = <1>; 751742af7e7SThierry Reding #size-cells = <0>; 752742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_SBC1>; 753742af7e7SThierry Reding clock-names = "spi"; 754742af7e7SThierry Reding resets = <&tegra_car 41>; 755742af7e7SThierry Reding reset-names = "spi"; 756742af7e7SThierry Reding dmas = <&apbdma 15>, <&apbdma 15>; 757742af7e7SThierry Reding dma-names = "rx", "tx"; 758742af7e7SThierry Reding status = "disabled"; 759742af7e7SThierry Reding }; 760742af7e7SThierry Reding 761be70771dSThierry Reding spi@7000d600 { 762742af7e7SThierry Reding compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 763742af7e7SThierry Reding reg = <0x0 0x7000d600 0x0 0x200>; 764742af7e7SThierry Reding interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 765742af7e7SThierry Reding #address-cells = <1>; 766742af7e7SThierry Reding #size-cells = <0>; 767742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_SBC2>; 768742af7e7SThierry Reding clock-names = "spi"; 769742af7e7SThierry Reding resets = <&tegra_car 44>; 770742af7e7SThierry Reding reset-names = "spi"; 771742af7e7SThierry Reding dmas = <&apbdma 16>, <&apbdma 16>; 772742af7e7SThierry Reding dma-names = "rx", "tx"; 773742af7e7SThierry Reding status = "disabled"; 774742af7e7SThierry Reding }; 775742af7e7SThierry Reding 776be70771dSThierry Reding spi@7000d800 { 777742af7e7SThierry Reding compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 778742af7e7SThierry Reding reg = <0x0 0x7000d800 0x0 0x200>; 779742af7e7SThierry Reding interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 780742af7e7SThierry Reding #address-cells = <1>; 781742af7e7SThierry Reding #size-cells = <0>; 782742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_SBC3>; 783742af7e7SThierry Reding clock-names = "spi"; 784742af7e7SThierry Reding resets = <&tegra_car 46>; 785742af7e7SThierry Reding reset-names = "spi"; 786742af7e7SThierry Reding dmas = <&apbdma 17>, <&apbdma 17>; 787742af7e7SThierry Reding dma-names = "rx", "tx"; 788742af7e7SThierry Reding status = "disabled"; 789742af7e7SThierry Reding }; 790742af7e7SThierry Reding 791be70771dSThierry Reding spi@7000da00 { 792742af7e7SThierry Reding compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 793742af7e7SThierry Reding reg = <0x0 0x7000da00 0x0 0x200>; 794742af7e7SThierry Reding interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 795742af7e7SThierry Reding #address-cells = <1>; 796742af7e7SThierry Reding #size-cells = <0>; 797742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_SBC4>; 798742af7e7SThierry Reding clock-names = "spi"; 799742af7e7SThierry Reding resets = <&tegra_car 68>; 800742af7e7SThierry Reding reset-names = "spi"; 801742af7e7SThierry Reding dmas = <&apbdma 18>, <&apbdma 18>; 802742af7e7SThierry Reding dma-names = "rx", "tx"; 803742af7e7SThierry Reding status = "disabled"; 804742af7e7SThierry Reding }; 805742af7e7SThierry Reding 806be70771dSThierry Reding rtc@7000e000 { 807742af7e7SThierry Reding compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc"; 808742af7e7SThierry Reding reg = <0x0 0x7000e000 0x0 0x100>; 809d13c13f4SSowjanya Komatineni interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; 810359ae651SSowjanya Komatineni interrupt-parent = <&tegra_pmc>; 811742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_RTC>; 812742af7e7SThierry Reding clock-names = "rtc"; 813742af7e7SThierry Reding }; 814742af7e7SThierry Reding 815359ae651SSowjanya Komatineni tegra_pmc: pmc@7000e400 { 816742af7e7SThierry Reding compatible = "nvidia,tegra210-pmc"; 817742af7e7SThierry Reding reg = <0x0 0x7000e400 0x0 0x400>; 818742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; 819742af7e7SThierry Reding clock-names = "pclk", "clk32k_in"; 820359ae651SSowjanya Komatineni #clock-cells = <1>; 821d13c13f4SSowjanya Komatineni #interrupt-cells = <2>; 822d13c13f4SSowjanya Komatineni interrupt-controller; 823c2b82445SJon Hunter 824c2b82445SJon Hunter powergates { 825c2b82445SJon Hunter pd_audio: aud { 826c2b82445SJon Hunter clocks = <&tegra_car TEGRA210_CLK_APE>, 827c2b82445SJon Hunter <&tegra_car TEGRA210_CLK_APB2APE>; 828c2b82445SJon Hunter resets = <&tegra_car 198>; 829c2b82445SJon Hunter #power-domain-cells = <0>; 830c2b82445SJon Hunter }; 831241f02baSJon Hunter 83296d1f078SJon Hunter pd_sor: sor { 83396d1f078SJon Hunter clocks = <&tegra_car TEGRA210_CLK_SOR0>, 83496d1f078SJon Hunter <&tegra_car TEGRA210_CLK_SOR1>, 835b4f99176SSowjanya Komatineni <&tegra_car TEGRA210_CLK_CILAB>, 836b4f99176SSowjanya Komatineni <&tegra_car TEGRA210_CLK_CILCD>, 837b4f99176SSowjanya Komatineni <&tegra_car TEGRA210_CLK_CILE>, 83896d1f078SJon Hunter <&tegra_car TEGRA210_CLK_DSIA>, 83996d1f078SJon Hunter <&tegra_car TEGRA210_CLK_DSIB>, 84096d1f078SJon Hunter <&tegra_car TEGRA210_CLK_DPAUX>, 84196d1f078SJon Hunter <&tegra_car TEGRA210_CLK_DPAUX1>, 84296d1f078SJon Hunter <&tegra_car TEGRA210_CLK_MIPI_CAL>; 84396d1f078SJon Hunter resets = <&tegra_car TEGRA210_CLK_SOR0>, 84496d1f078SJon Hunter <&tegra_car TEGRA210_CLK_SOR1>, 84596d1f078SJon Hunter <&tegra_car TEGRA210_CLK_DSIA>, 84696d1f078SJon Hunter <&tegra_car TEGRA210_CLK_DSIB>, 84796d1f078SJon Hunter <&tegra_car TEGRA210_CLK_DPAUX>, 84896d1f078SJon Hunter <&tegra_car TEGRA210_CLK_DPAUX1>, 84996d1f078SJon Hunter <&tegra_car TEGRA210_CLK_MIPI_CAL>; 85096d1f078SJon Hunter #power-domain-cells = <0>; 85196d1f078SJon Hunter }; 85296d1f078SJon Hunter 853241f02baSJon Hunter pd_xusbss: xusba { 854241f02baSJon Hunter clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>; 855241f02baSJon Hunter resets = <&tegra_car TEGRA210_CLK_XUSB_SS>; 856241f02baSJon Hunter #power-domain-cells = <0>; 857241f02baSJon Hunter }; 858241f02baSJon Hunter 859241f02baSJon Hunter pd_xusbdev: xusbb { 860241f02baSJon Hunter clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>; 861241f02baSJon Hunter resets = <&tegra_car 95>; 862241f02baSJon Hunter #power-domain-cells = <0>; 863241f02baSJon Hunter }; 864241f02baSJon Hunter 865241f02baSJon Hunter pd_xusbhost: xusbc { 866241f02baSJon Hunter clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>; 867241f02baSJon Hunter resets = <&tegra_car TEGRA210_CLK_XUSB_HOST>; 868241f02baSJon Hunter #power-domain-cells = <0>; 869241f02baSJon Hunter }; 87024963d1bSMikko Perttunen 87124963d1bSMikko Perttunen pd_vic: vic { 87224963d1bSMikko Perttunen clocks = <&tegra_car TEGRA210_CLK_VIC03>; 87324963d1bSMikko Perttunen clock-names = "vic"; 87424963d1bSMikko Perttunen resets = <&tegra_car 178>; 87524963d1bSMikko Perttunen reset-names = "vic"; 87624963d1bSMikko Perttunen #power-domain-cells = <0>; 87724963d1bSMikko Perttunen }; 878c4153885SSowjanya Komatineni 879c4153885SSowjanya Komatineni pd_venc: venc { 880c4153885SSowjanya Komatineni clocks = <&tegra_car TEGRA210_CLK_VI>, 881c4153885SSowjanya Komatineni <&tegra_car TEGRA210_CLK_CSI>; 882c4153885SSowjanya Komatineni resets = <&mc TEGRA210_MC_RESET_VI>, 883c4153885SSowjanya Komatineni <&tegra_car 20>, 884c4153885SSowjanya Komatineni <&tegra_car 52>; 885c4153885SSowjanya Komatineni #power-domain-cells = <0>; 886c4153885SSowjanya Komatineni }; 887c2b82445SJon Hunter }; 8886641af7eSAapo Vienamo 8896641af7eSAapo Vienamo sdmmc1_3v3: sdmmc1-3v3 { 8906641af7eSAapo Vienamo pins = "sdmmc1"; 8916641af7eSAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 8926641af7eSAapo Vienamo }; 8936641af7eSAapo Vienamo 8946641af7eSAapo Vienamo sdmmc1_1v8: sdmmc1-1v8 { 8956641af7eSAapo Vienamo pins = "sdmmc1"; 8966641af7eSAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 8976641af7eSAapo Vienamo }; 8986641af7eSAapo Vienamo 8996641af7eSAapo Vienamo sdmmc3_3v3: sdmmc3-3v3 { 9006641af7eSAapo Vienamo pins = "sdmmc3"; 9016641af7eSAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 9026641af7eSAapo Vienamo }; 9036641af7eSAapo Vienamo 9046641af7eSAapo Vienamo sdmmc3_1v8: sdmmc3-1v8 { 9056641af7eSAapo Vienamo pins = "sdmmc3"; 9066641af7eSAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 9076641af7eSAapo Vienamo }; 908871be845SManikanta Maddireddy 909871be845SManikanta Maddireddy pex_dpd_disable: pex_en { 910871be845SManikanta Maddireddy pex-dpd-disable { 911871be845SManikanta Maddireddy pins = "pex-bias", "pex-clk1", "pex-clk2"; 912871be845SManikanta Maddireddy low-power-disable; 913871be845SManikanta Maddireddy }; 914871be845SManikanta Maddireddy }; 915871be845SManikanta Maddireddy 916871be845SManikanta Maddireddy pex_dpd_enable: pex_dis { 917871be845SManikanta Maddireddy pex-dpd-enable { 918871be845SManikanta Maddireddy pins = "pex-bias", "pex-clk1", "pex-clk2"; 919871be845SManikanta Maddireddy low-power-enable; 920871be845SManikanta Maddireddy }; 921871be845SManikanta Maddireddy }; 922742af7e7SThierry Reding }; 923742af7e7SThierry Reding 924be70771dSThierry Reding fuse@7000f800 { 925742af7e7SThierry Reding compatible = "nvidia,tegra210-efuse"; 926742af7e7SThierry Reding reg = <0x0 0x7000f800 0x0 0x400>; 927742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_FUSE>; 928742af7e7SThierry Reding clock-names = "fuse"; 929742af7e7SThierry Reding resets = <&tegra_car 39>; 930742af7e7SThierry Reding reset-names = "fuse"; 931742af7e7SThierry Reding }; 932742af7e7SThierry Reding 933be70771dSThierry Reding mc: memory-controller@70019000 { 934742af7e7SThierry Reding compatible = "nvidia,tegra210-mc"; 935742af7e7SThierry Reding reg = <0x0 0x70019000 0x0 0x1000>; 936742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_MC>; 937742af7e7SThierry Reding clock-names = "mc"; 938742af7e7SThierry Reding 939742af7e7SThierry Reding interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 940742af7e7SThierry Reding 941742af7e7SThierry Reding #iommu-cells = <1>; 9422eb8e1a4SSowjanya Komatineni #reset-cells = <1>; 943742af7e7SThierry Reding }; 944742af7e7SThierry Reding 945e12325f6SThierry Reding emc: external-memory-controller@7001b000 { 946cd9350c5SJoseph Lo compatible = "nvidia,tegra210-emc"; 947cd9350c5SJoseph Lo reg = <0x0 0x7001b000 0x0 0x1000>, 948cd9350c5SJoseph Lo <0x0 0x7001e000 0x0 0x1000>, 949cd9350c5SJoseph Lo <0x0 0x7001f000 0x0 0x1000>; 950cd9350c5SJoseph Lo clocks = <&tegra_car TEGRA210_CLK_EMC>; 951cd9350c5SJoseph Lo clock-names = "emc"; 952cd9350c5SJoseph Lo interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 953cd9350c5SJoseph Lo nvidia,memory-controller = <&mc>; 954e12325f6SThierry Reding #cooling-cells = <2>; 955cd9350c5SJoseph Lo }; 956cd9350c5SJoseph Lo 9576cb60ec4SPreetham Ramchandra sata@70020000 { 9586cb60ec4SPreetham Ramchandra compatible = "nvidia,tegra210-ahci"; 9596cb60ec4SPreetham Ramchandra reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */ 9606cb60ec4SPreetham Ramchandra <0x0 0x70020000 0x0 0x7000>, /* SATA */ 9616cb60ec4SPreetham Ramchandra <0x0 0x70001100 0x0 0x1000>; /* SATA AUX */ 9626cb60ec4SPreetham Ramchandra interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 9636cb60ec4SPreetham Ramchandra clocks = <&tegra_car TEGRA210_CLK_SATA>, 9646cb60ec4SPreetham Ramchandra <&tegra_car TEGRA210_CLK_SATA_OOB>; 9656cb60ec4SPreetham Ramchandra clock-names = "sata", "sata-oob"; 9666cb60ec4SPreetham Ramchandra resets = <&tegra_car 124>, 9676cb60ec4SPreetham Ramchandra <&tegra_car 123>, 9686cb60ec4SPreetham Ramchandra <&tegra_car 129>; 9696cb60ec4SPreetham Ramchandra reset-names = "sata", "sata-oob", "sata-cold"; 9706cb60ec4SPreetham Ramchandra status = "disabled"; 9716cb60ec4SPreetham Ramchandra }; 9726cb60ec4SPreetham Ramchandra 973be70771dSThierry Reding hda@70030000 { 974742af7e7SThierry Reding compatible = "nvidia,tegra210-hda", "nvidia,tegra30-hda"; 975742af7e7SThierry Reding reg = <0x0 0x70030000 0x0 0x10000>; 976742af7e7SThierry Reding interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 977742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_HDA>, 978742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_HDA2HDMI>, 979742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_HDA2CODEC_2X>; 980742af7e7SThierry Reding clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 981742af7e7SThierry Reding resets = <&tegra_car 125>, /* hda */ 982742af7e7SThierry Reding <&tegra_car 128>, /* hda2hdmi */ 983742af7e7SThierry Reding <&tegra_car 111>; /* hda2codec_2x */ 984742af7e7SThierry Reding reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 985742af7e7SThierry Reding status = "disabled"; 986742af7e7SThierry Reding }; 987742af7e7SThierry Reding 988e7a99ac2SThierry Reding usb@70090000 { 989e7a99ac2SThierry Reding compatible = "nvidia,tegra210-xusb"; 990e7a99ac2SThierry Reding reg = <0x0 0x70090000 0x0 0x8000>, 991e7a99ac2SThierry Reding <0x0 0x70098000 0x0 0x1000>, 992e7a99ac2SThierry Reding <0x0 0x70099000 0x0 0x1000>; 993e7a99ac2SThierry Reding reg-names = "hcd", "fpci", "ipfs"; 994e7a99ac2SThierry Reding 995e7a99ac2SThierry Reding interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 9969168e1dbSJon Hunter <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 997e7a99ac2SThierry Reding 998e7a99ac2SThierry Reding clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>, 999e7a99ac2SThierry Reding <&tegra_car TEGRA210_CLK_XUSB_HOST_SRC>, 1000e7a99ac2SThierry Reding <&tegra_car TEGRA210_CLK_XUSB_FALCON_SRC>, 1001e7a99ac2SThierry Reding <&tegra_car TEGRA210_CLK_XUSB_SS>, 1002e7a99ac2SThierry Reding <&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>, 1003e7a99ac2SThierry Reding <&tegra_car TEGRA210_CLK_XUSB_SS_SRC>, 1004e7a99ac2SThierry Reding <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>, 1005e7a99ac2SThierry Reding <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>, 1006e7a99ac2SThierry Reding <&tegra_car TEGRA210_CLK_PLL_U_480M>, 1007e7a99ac2SThierry Reding <&tegra_car TEGRA210_CLK_CLK_M>, 1008e7a99ac2SThierry Reding <&tegra_car TEGRA210_CLK_PLL_E>; 1009e7a99ac2SThierry Reding clock-names = "xusb_host", "xusb_host_src", 1010e7a99ac2SThierry Reding "xusb_falcon_src", "xusb_ss", 1011e7a99ac2SThierry Reding "xusb_ss_div2", "xusb_ss_src", 1012e7a99ac2SThierry Reding "xusb_hs_src", "xusb_fs_src", 1013e7a99ac2SThierry Reding "pll_u_480m", "clk_m", "pll_e"; 1014e7a99ac2SThierry Reding resets = <&tegra_car 89>, <&tegra_car 156>, 1015e7a99ac2SThierry Reding <&tegra_car 143>; 1016e7a99ac2SThierry Reding reset-names = "xusb_host", "xusb_ss", "xusb_src"; 101736ec29f7SJon Hunter power-domains = <&pd_xusbhost>, <&pd_xusbss>; 101836ec29f7SJon Hunter power-domain-names = "xusb_host", "xusb_ss"; 1019e7a99ac2SThierry Reding 1020e7a99ac2SThierry Reding nvidia,xusb-padctl = <&padctl>; 1021e7a99ac2SThierry Reding 1022e7a99ac2SThierry Reding status = "disabled"; 1023e7a99ac2SThierry Reding }; 1024e7a99ac2SThierry Reding 10254e07ac90SThierry Reding padctl: padctl@7009f000 { 10264e07ac90SThierry Reding compatible = "nvidia,tegra210-xusb-padctl"; 10274e07ac90SThierry Reding reg = <0x0 0x7009f000 0x0 0x1000>; 10284e07ac90SThierry Reding resets = <&tegra_car 142>; 10294e07ac90SThierry Reding reset-names = "padctl"; 10304e07ac90SThierry Reding 10314e07ac90SThierry Reding status = "disabled"; 10324e07ac90SThierry Reding 10334e07ac90SThierry Reding pads { 10344e07ac90SThierry Reding usb2 { 10354e07ac90SThierry Reding clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>; 10364e07ac90SThierry Reding clock-names = "trk"; 10374e07ac90SThierry Reding status = "disabled"; 10384e07ac90SThierry Reding 10394e07ac90SThierry Reding lanes { 10404e07ac90SThierry Reding usb2-0 { 10414e07ac90SThierry Reding status = "disabled"; 10424e07ac90SThierry Reding #phy-cells = <0>; 10434e07ac90SThierry Reding }; 10444e07ac90SThierry Reding 10454e07ac90SThierry Reding usb2-1 { 10464e07ac90SThierry Reding status = "disabled"; 10474e07ac90SThierry Reding #phy-cells = <0>; 10484e07ac90SThierry Reding }; 10494e07ac90SThierry Reding 10504e07ac90SThierry Reding usb2-2 { 10514e07ac90SThierry Reding status = "disabled"; 10524e07ac90SThierry Reding #phy-cells = <0>; 10534e07ac90SThierry Reding }; 10544e07ac90SThierry Reding 10554e07ac90SThierry Reding usb2-3 { 10564e07ac90SThierry Reding status = "disabled"; 10574e07ac90SThierry Reding #phy-cells = <0>; 10584e07ac90SThierry Reding }; 10594e07ac90SThierry Reding }; 10604e07ac90SThierry Reding }; 10614e07ac90SThierry Reding 10624e07ac90SThierry Reding hsic { 10634e07ac90SThierry Reding clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>; 10644e07ac90SThierry Reding clock-names = "trk"; 10654e07ac90SThierry Reding status = "disabled"; 10664e07ac90SThierry Reding 10674e07ac90SThierry Reding lanes { 10684e07ac90SThierry Reding hsic-0 { 10694e07ac90SThierry Reding status = "disabled"; 10704e07ac90SThierry Reding #phy-cells = <0>; 10714e07ac90SThierry Reding }; 10724e07ac90SThierry Reding 10734e07ac90SThierry Reding hsic-1 { 10744e07ac90SThierry Reding status = "disabled"; 10754e07ac90SThierry Reding #phy-cells = <0>; 10764e07ac90SThierry Reding }; 10774e07ac90SThierry Reding }; 10784e07ac90SThierry Reding }; 10794e07ac90SThierry Reding 10804e07ac90SThierry Reding pcie { 10814e07ac90SThierry Reding clocks = <&tegra_car TEGRA210_CLK_PLL_E>; 10824e07ac90SThierry Reding clock-names = "pll"; 10834e07ac90SThierry Reding resets = <&tegra_car 205>; 10844e07ac90SThierry Reding reset-names = "phy"; 10854e07ac90SThierry Reding status = "disabled"; 10864e07ac90SThierry Reding 10874e07ac90SThierry Reding lanes { 10884e07ac90SThierry Reding pcie-0 { 10894e07ac90SThierry Reding status = "disabled"; 10904e07ac90SThierry Reding #phy-cells = <0>; 10914e07ac90SThierry Reding }; 10924e07ac90SThierry Reding 10934e07ac90SThierry Reding pcie-1 { 10944e07ac90SThierry Reding status = "disabled"; 10954e07ac90SThierry Reding #phy-cells = <0>; 10964e07ac90SThierry Reding }; 10974e07ac90SThierry Reding 10984e07ac90SThierry Reding pcie-2 { 10994e07ac90SThierry Reding status = "disabled"; 11004e07ac90SThierry Reding #phy-cells = <0>; 11014e07ac90SThierry Reding }; 11024e07ac90SThierry Reding 11034e07ac90SThierry Reding pcie-3 { 11044e07ac90SThierry Reding status = "disabled"; 11054e07ac90SThierry Reding #phy-cells = <0>; 11064e07ac90SThierry Reding }; 11074e07ac90SThierry Reding 11084e07ac90SThierry Reding pcie-4 { 11094e07ac90SThierry Reding status = "disabled"; 11104e07ac90SThierry Reding #phy-cells = <0>; 11114e07ac90SThierry Reding }; 11124e07ac90SThierry Reding 11134e07ac90SThierry Reding pcie-5 { 11144e07ac90SThierry Reding status = "disabled"; 11154e07ac90SThierry Reding #phy-cells = <0>; 11164e07ac90SThierry Reding }; 11174e07ac90SThierry Reding 11184e07ac90SThierry Reding pcie-6 { 11194e07ac90SThierry Reding status = "disabled"; 11204e07ac90SThierry Reding #phy-cells = <0>; 11214e07ac90SThierry Reding }; 11224e07ac90SThierry Reding }; 11234e07ac90SThierry Reding }; 11244e07ac90SThierry Reding 11254e07ac90SThierry Reding sata { 11264e07ac90SThierry Reding clocks = <&tegra_car TEGRA210_CLK_PLL_E>; 11274e07ac90SThierry Reding clock-names = "pll"; 11284e07ac90SThierry Reding resets = <&tegra_car 204>; 11294e07ac90SThierry Reding reset-names = "phy"; 11304e07ac90SThierry Reding status = "disabled"; 11314e07ac90SThierry Reding 11324e07ac90SThierry Reding lanes { 11334e07ac90SThierry Reding sata-0 { 11344e07ac90SThierry Reding status = "disabled"; 11354e07ac90SThierry Reding #phy-cells = <0>; 11364e07ac90SThierry Reding }; 11374e07ac90SThierry Reding }; 11384e07ac90SThierry Reding }; 11394e07ac90SThierry Reding }; 11404e07ac90SThierry Reding 11414e07ac90SThierry Reding ports { 11424e07ac90SThierry Reding usb2-0 { 11434e07ac90SThierry Reding status = "disabled"; 11444e07ac90SThierry Reding }; 11454e07ac90SThierry Reding 11464e07ac90SThierry Reding usb2-1 { 11474e07ac90SThierry Reding status = "disabled"; 11484e07ac90SThierry Reding }; 11494e07ac90SThierry Reding 11504e07ac90SThierry Reding usb2-2 { 11514e07ac90SThierry Reding status = "disabled"; 11524e07ac90SThierry Reding }; 11534e07ac90SThierry Reding 11544e07ac90SThierry Reding usb2-3 { 11554e07ac90SThierry Reding status = "disabled"; 11564e07ac90SThierry Reding }; 11574e07ac90SThierry Reding 11584e07ac90SThierry Reding hsic-0 { 11594e07ac90SThierry Reding status = "disabled"; 11604e07ac90SThierry Reding }; 11614e07ac90SThierry Reding 11624e07ac90SThierry Reding usb3-0 { 11634e07ac90SThierry Reding status = "disabled"; 11644e07ac90SThierry Reding }; 11654e07ac90SThierry Reding 11664e07ac90SThierry Reding usb3-1 { 11674e07ac90SThierry Reding status = "disabled"; 11684e07ac90SThierry Reding }; 11694e07ac90SThierry Reding 11704e07ac90SThierry Reding usb3-2 { 11714e07ac90SThierry Reding status = "disabled"; 11724e07ac90SThierry Reding }; 11734e07ac90SThierry Reding 11744e07ac90SThierry Reding usb3-3 { 11754e07ac90SThierry Reding status = "disabled"; 11764e07ac90SThierry Reding }; 11774e07ac90SThierry Reding }; 11784e07ac90SThierry Reding }; 11794e07ac90SThierry Reding 1180be70771dSThierry Reding sdhci@700b0000 { 1181b3fa0e03SThierry Reding compatible = "nvidia,tegra210-sdhci"; 1182742af7e7SThierry Reding reg = <0x0 0x700b0000 0x0 0x200>; 1183742af7e7SThierry Reding interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1184742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_SDMMC1>; 1185742af7e7SThierry Reding clock-names = "sdhci"; 1186742af7e7SThierry Reding resets = <&tegra_car 14>; 1187742af7e7SThierry Reding reset-names = "sdhci"; 11884e0f1229SSowjanya Komatineni pinctrl-names = "sdmmc-3v3", "sdmmc-1v8", 11894e0f1229SSowjanya Komatineni "sdmmc-3v3-drv", "sdmmc-1v8-drv"; 11906641af7eSAapo Vienamo pinctrl-0 = <&sdmmc1_3v3>; 11916641af7eSAapo Vienamo pinctrl-1 = <&sdmmc1_1v8>; 11924e0f1229SSowjanya Komatineni pinctrl-2 = <&sdmmc1_3v3_drv>; 11934e0f1229SSowjanya Komatineni pinctrl-3 = <&sdmmc1_1v8_drv>; 11941ea06718SAapo Vienamo nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>; 11951ea06718SAapo Vienamo nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>; 11961ea06718SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>; 11971ea06718SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>; 119863af8bcdSAapo Vienamo nvidia,default-tap = <0x2>; 119963af8bcdSAapo Vienamo nvidia,default-trim = <0x4>; 1200918f9671SAapo Vienamo assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>, 1201918f9671SAapo Vienamo <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>, 1202918f9671SAapo Vienamo <&tegra_car TEGRA210_CLK_PLL_C4>; 1203918f9671SAapo Vienamo assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 1204918f9671SAapo Vienamo assigned-clock-rates = <200000000>, <1000000000>, <1000000000>; 1205742af7e7SThierry Reding status = "disabled"; 1206742af7e7SThierry Reding }; 1207742af7e7SThierry Reding 1208be70771dSThierry Reding sdhci@700b0200 { 1209b3fa0e03SThierry Reding compatible = "nvidia,tegra210-sdhci"; 1210742af7e7SThierry Reding reg = <0x0 0x700b0200 0x0 0x200>; 1211742af7e7SThierry Reding interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 1212742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_SDMMC2>; 1213742af7e7SThierry Reding clock-names = "sdhci"; 1214742af7e7SThierry Reding resets = <&tegra_car 9>; 1215742af7e7SThierry Reding reset-names = "sdhci"; 12164e0f1229SSowjanya Komatineni pinctrl-names = "sdmmc-1v8-drv"; 12174e0f1229SSowjanya Komatineni pinctrl-0 = <&sdmmc2_1v8_drv>; 12181ea06718SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>; 12191ea06718SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>; 122063af8bcdSAapo Vienamo nvidia,default-tap = <0x8>; 122163af8bcdSAapo Vienamo nvidia,default-trim = <0x0>; 1222742af7e7SThierry Reding status = "disabled"; 1223742af7e7SThierry Reding }; 1224742af7e7SThierry Reding 1225be70771dSThierry Reding sdhci@700b0400 { 1226b3fa0e03SThierry Reding compatible = "nvidia,tegra210-sdhci"; 1227742af7e7SThierry Reding reg = <0x0 0x700b0400 0x0 0x200>; 1228742af7e7SThierry Reding interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 1229742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_SDMMC3>; 1230742af7e7SThierry Reding clock-names = "sdhci"; 1231742af7e7SThierry Reding resets = <&tegra_car 69>; 1232742af7e7SThierry Reding reset-names = "sdhci"; 12334e0f1229SSowjanya Komatineni pinctrl-names = "sdmmc-3v3", "sdmmc-1v8", 12344e0f1229SSowjanya Komatineni "sdmmc-3v3-drv", "sdmmc-1v8-drv"; 12356641af7eSAapo Vienamo pinctrl-0 = <&sdmmc3_3v3>; 12366641af7eSAapo Vienamo pinctrl-1 = <&sdmmc3_1v8>; 12374e0f1229SSowjanya Komatineni pinctrl-2 = <&sdmmc3_3v3_drv>; 12384e0f1229SSowjanya Komatineni pinctrl-3 = <&sdmmc3_1v8_drv>; 12391ea06718SAapo Vienamo nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>; 12401ea06718SAapo Vienamo nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>; 12411ea06718SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>; 12421ea06718SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>; 124363af8bcdSAapo Vienamo nvidia,default-tap = <0x3>; 124463af8bcdSAapo Vienamo nvidia,default-trim = <0x3>; 1245742af7e7SThierry Reding status = "disabled"; 1246742af7e7SThierry Reding }; 1247742af7e7SThierry Reding 1248be70771dSThierry Reding sdhci@700b0600 { 1249b3fa0e03SThierry Reding compatible = "nvidia,tegra210-sdhci"; 1250742af7e7SThierry Reding reg = <0x0 0x700b0600 0x0 0x200>; 1251742af7e7SThierry Reding interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1252742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_SDMMC4>; 1253742af7e7SThierry Reding clock-names = "sdhci"; 1254742af7e7SThierry Reding resets = <&tegra_car 15>; 1255742af7e7SThierry Reding reset-names = "sdhci"; 12564e0f1229SSowjanya Komatineni pinctrl-names = "sdmmc-3v3-drv", "sdmmc-1v8-drv"; 12574e0f1229SSowjanya Komatineni pinctrl-0 = <&sdmmc4_1v8_drv>; 12584e0f1229SSowjanya Komatineni pinctrl-1 = <&sdmmc4_1v8_drv>; 12591ea06718SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>; 12601ea06718SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>; 126163af8bcdSAapo Vienamo nvidia,default-tap = <0x8>; 126263af8bcdSAapo Vienamo nvidia,default-trim = <0x0>; 1263918f9671SAapo Vienamo assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>, 1264918f9671SAapo Vienamo <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 1265918f9671SAapo Vienamo assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 12665879600aSAapo Vienamo nvidia,dqs-trim = <40>; 1267d5d6b468SAapo Vienamo mmc-hs400-1_8v; 1268742af7e7SThierry Reding status = "disabled"; 1269742af7e7SThierry Reding }; 1270742af7e7SThierry Reding 1271e74db5a5SNagarjuna Kristam usb@700d0000 { 1272e74db5a5SNagarjuna Kristam compatible = "nvidia,tegra210-xudc"; 1273e74db5a5SNagarjuna Kristam reg = <0x0 0x700d0000 0x0 0x8000>, 1274e74db5a5SNagarjuna Kristam <0x0 0x700d8000 0x0 0x1000>, 1275e74db5a5SNagarjuna Kristam <0x0 0x700d9000 0x0 0x1000>; 1276e74db5a5SNagarjuna Kristam reg-names = "base", "fpci", "ipfs"; 1277e74db5a5SNagarjuna Kristam interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1278e74db5a5SNagarjuna Kristam clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>, 1279e74db5a5SNagarjuna Kristam <&tegra_car TEGRA210_CLK_XUSB_SS>, 1280e74db5a5SNagarjuna Kristam <&tegra_car TEGRA210_CLK_XUSB_SSP_SRC>, 1281e74db5a5SNagarjuna Kristam <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>, 1282e74db5a5SNagarjuna Kristam <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>; 1283e74db5a5SNagarjuna Kristam clock-names = "dev", "ss", "ss_src", "fs_src", "hs_src"; 1284e74db5a5SNagarjuna Kristam power-domains = <&pd_xusbdev>, <&pd_xusbss>; 1285e74db5a5SNagarjuna Kristam power-domain-names = "dev", "ss"; 1286e74db5a5SNagarjuna Kristam nvidia,xusb-padctl = <&padctl>; 1287e74db5a5SNagarjuna Kristam status = "disabled"; 1288e74db5a5SNagarjuna Kristam }; 1289e74db5a5SNagarjuna Kristam 1290be70771dSThierry Reding mipi: mipi@700e3000 { 1291742af7e7SThierry Reding compatible = "nvidia,tegra210-mipi"; 1292742af7e7SThierry Reding reg = <0x0 0x700e3000 0x0 0x100>; 1293742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_MIPI_CAL>; 1294742af7e7SThierry Reding clock-names = "mipi-cal"; 129596d1f078SJon Hunter power-domains = <&pd_sor>; 1296742af7e7SThierry Reding #nvidia,mipi-calibrate-cells = <1>; 1297742af7e7SThierry Reding }; 1298742af7e7SThierry Reding 12992ceed593SJoseph Lo dfll: clock@70110000 { 13002ceed593SJoseph Lo compatible = "nvidia,tegra210-dfll"; 13012ceed593SJoseph Lo reg = <0 0x70110000 0 0x100>, /* DFLL control */ 13022ceed593SJoseph Lo <0 0x70110000 0 0x100>, /* I2C output control */ 13032ceed593SJoseph Lo <0 0x70110100 0 0x100>, /* Integrated I2C controller */ 13042ceed593SJoseph Lo <0 0x70110200 0 0x100>; /* Look-up table RAM */ 13052ceed593SJoseph Lo interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 13062ceed593SJoseph Lo clocks = <&tegra_car TEGRA210_CLK_DFLL_SOC>, 13072ceed593SJoseph Lo <&tegra_car TEGRA210_CLK_DFLL_REF>, 13082ceed593SJoseph Lo <&tegra_car TEGRA210_CLK_I2C5>; 13092ceed593SJoseph Lo clock-names = "soc", "ref", "i2c"; 13102ceed593SJoseph Lo resets = <&tegra_car TEGRA210_RST_DFLL_DVCO>; 13112ceed593SJoseph Lo reset-names = "dvco"; 13122ceed593SJoseph Lo #clock-cells = <0>; 13132ceed593SJoseph Lo clock-output-names = "dfllCPU_out"; 13142ceed593SJoseph Lo status = "disabled"; 13152ceed593SJoseph Lo }; 13162ceed593SJoseph Lo 13170f133090SJon Hunter aconnect@702c0000 { 13180f133090SJon Hunter compatible = "nvidia,tegra210-aconnect"; 13190f133090SJon Hunter clocks = <&tegra_car TEGRA210_CLK_APE>, 13200f133090SJon Hunter <&tegra_car TEGRA210_CLK_APB2APE>; 13210f133090SJon Hunter clock-names = "ape", "apb2ape"; 13220f133090SJon Hunter power-domains = <&pd_audio>; 13230f133090SJon Hunter #address-cells = <1>; 13240f133090SJon Hunter #size-cells = <1>; 13250f133090SJon Hunter ranges = <0x702c0000 0x0 0x702c0000 0x00040000>; 13260f133090SJon Hunter status = "disabled"; 1327bcdbde43SJon Hunter 132819e61213SJon Hunter adma: dma@702e2000 { 132919e61213SJon Hunter compatible = "nvidia,tegra210-adma"; 133019e61213SJon Hunter reg = <0x702e2000 0x2000>; 133119e61213SJon Hunter interrupt-parent = <&agic>; 133219e61213SJon Hunter interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 133319e61213SJon Hunter <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 133419e61213SJon Hunter <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 133519e61213SJon Hunter <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 133619e61213SJon Hunter <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 133719e61213SJon Hunter <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 133819e61213SJon Hunter <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 133919e61213SJon Hunter <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 134019e61213SJon Hunter <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 134119e61213SJon Hunter <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 134219e61213SJon Hunter <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 134319e61213SJon Hunter <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 134419e61213SJon Hunter <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 134519e61213SJon Hunter <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 134619e61213SJon Hunter <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 134719e61213SJon Hunter <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 134819e61213SJon Hunter <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 134919e61213SJon Hunter <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 135019e61213SJon Hunter <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 135119e61213SJon Hunter <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 135219e61213SJon Hunter <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 135319e61213SJon Hunter <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 135419e61213SJon Hunter #dma-cells = <1>; 135519e61213SJon Hunter clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>; 135619e61213SJon Hunter clock-names = "d_audio"; 135719e61213SJon Hunter status = "disabled"; 135819e61213SJon Hunter }; 135919e61213SJon Hunter 1360bcdbde43SJon Hunter agic: agic@702f9000 { 1361bcdbde43SJon Hunter compatible = "nvidia,tegra210-agic"; 1362bcdbde43SJon Hunter #interrupt-cells = <3>; 1363bcdbde43SJon Hunter interrupt-controller; 1364ba24eee6SJon Hunter reg = <0x702f9000 0x1000>, 1365bcdbde43SJon Hunter <0x702fa000 0x2000>; 1366bcdbde43SJon Hunter interrupts = <GIC_SPI 102 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1367bcdbde43SJon Hunter clocks = <&tegra_car TEGRA210_CLK_APE>; 1368bcdbde43SJon Hunter clock-names = "clk"; 1369bcdbde43SJon Hunter status = "disabled"; 1370bcdbde43SJon Hunter }; 13710f133090SJon Hunter }; 13720f133090SJon Hunter 1373be70771dSThierry Reding spi@70410000 { 1374742af7e7SThierry Reding compatible = "nvidia,tegra210-qspi"; 1375742af7e7SThierry Reding reg = <0x0 0x70410000 0x0 0x1000>; 1376742af7e7SThierry Reding interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1377742af7e7SThierry Reding #address-cells = <1>; 1378742af7e7SThierry Reding #size-cells = <0>; 1379742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_QSPI>; 1380742af7e7SThierry Reding clock-names = "qspi"; 1381742af7e7SThierry Reding resets = <&tegra_car 211>; 1382742af7e7SThierry Reding reset-names = "qspi"; 1383742af7e7SThierry Reding dmas = <&apbdma 5>, <&apbdma 5>; 1384742af7e7SThierry Reding dma-names = "rx", "tx"; 1385742af7e7SThierry Reding status = "disabled"; 1386742af7e7SThierry Reding }; 1387742af7e7SThierry Reding 1388be70771dSThierry Reding usb@7d000000 { 1389742af7e7SThierry Reding compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 1390742af7e7SThierry Reding reg = <0x0 0x7d000000 0x0 0x4000>; 1391742af7e7SThierry Reding interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1392742af7e7SThierry Reding phy_type = "utmi"; 1393742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_USBD>; 1394742af7e7SThierry Reding clock-names = "usb"; 1395742af7e7SThierry Reding resets = <&tegra_car 22>; 1396742af7e7SThierry Reding reset-names = "usb"; 1397742af7e7SThierry Reding nvidia,phy = <&phy1>; 1398742af7e7SThierry Reding status = "disabled"; 1399742af7e7SThierry Reding }; 1400742af7e7SThierry Reding 1401be70771dSThierry Reding phy1: usb-phy@7d000000 { 1402742af7e7SThierry Reding compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; 1403742af7e7SThierry Reding reg = <0x0 0x7d000000 0x0 0x4000>, 1404742af7e7SThierry Reding <0x0 0x7d000000 0x0 0x4000>; 1405742af7e7SThierry Reding phy_type = "utmi"; 1406742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_USBD>, 1407742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_PLL_U>, 1408742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_USBD>; 1409742af7e7SThierry Reding clock-names = "reg", "pll_u", "utmi-pads"; 1410742af7e7SThierry Reding resets = <&tegra_car 22>, <&tegra_car 22>; 1411742af7e7SThierry Reding reset-names = "usb", "utmi-pads"; 1412742af7e7SThierry Reding nvidia,hssync-start-delay = <0>; 1413742af7e7SThierry Reding nvidia,idle-wait-delay = <17>; 1414742af7e7SThierry Reding nvidia,elastic-limit = <16>; 1415742af7e7SThierry Reding nvidia,term-range-adj = <6>; 1416742af7e7SThierry Reding nvidia,xcvr-setup = <9>; 1417742af7e7SThierry Reding nvidia,xcvr-lsfslew = <0>; 1418742af7e7SThierry Reding nvidia,xcvr-lsrslew = <3>; 1419742af7e7SThierry Reding nvidia,hssquelch-level = <2>; 1420742af7e7SThierry Reding nvidia,hsdiscon-level = <5>; 1421742af7e7SThierry Reding nvidia,xcvr-hsslew = <12>; 1422742af7e7SThierry Reding nvidia,has-utmi-pad-registers; 1423742af7e7SThierry Reding status = "disabled"; 1424742af7e7SThierry Reding }; 1425742af7e7SThierry Reding 1426be70771dSThierry Reding usb@7d004000 { 1427742af7e7SThierry Reding compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 1428742af7e7SThierry Reding reg = <0x0 0x7d004000 0x0 0x4000>; 1429742af7e7SThierry Reding interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1430742af7e7SThierry Reding phy_type = "utmi"; 1431742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_USB2>; 1432742af7e7SThierry Reding clock-names = "usb"; 1433742af7e7SThierry Reding resets = <&tegra_car 58>; 1434742af7e7SThierry Reding reset-names = "usb"; 1435742af7e7SThierry Reding nvidia,phy = <&phy2>; 1436742af7e7SThierry Reding status = "disabled"; 1437742af7e7SThierry Reding }; 1438742af7e7SThierry Reding 1439be70771dSThierry Reding phy2: usb-phy@7d004000 { 1440742af7e7SThierry Reding compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; 1441742af7e7SThierry Reding reg = <0x0 0x7d004000 0x0 0x4000>, 1442742af7e7SThierry Reding <0x0 0x7d000000 0x0 0x4000>; 1443742af7e7SThierry Reding phy_type = "utmi"; 1444742af7e7SThierry Reding clocks = <&tegra_car TEGRA210_CLK_USB2>, 1445742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_PLL_U>, 1446742af7e7SThierry Reding <&tegra_car TEGRA210_CLK_USBD>; 1447742af7e7SThierry Reding clock-names = "reg", "pll_u", "utmi-pads"; 1448742af7e7SThierry Reding resets = <&tegra_car 58>, <&tegra_car 22>; 1449742af7e7SThierry Reding reset-names = "usb", "utmi-pads"; 1450742af7e7SThierry Reding nvidia,hssync-start-delay = <0>; 1451742af7e7SThierry Reding nvidia,idle-wait-delay = <17>; 1452742af7e7SThierry Reding nvidia,elastic-limit = <16>; 1453742af7e7SThierry Reding nvidia,term-range-adj = <6>; 1454742af7e7SThierry Reding nvidia,xcvr-setup = <9>; 1455742af7e7SThierry Reding nvidia,xcvr-lsfslew = <0>; 1456742af7e7SThierry Reding nvidia,xcvr-lsrslew = <3>; 1457742af7e7SThierry Reding nvidia,hssquelch-level = <2>; 1458742af7e7SThierry Reding nvidia,hsdiscon-level = <5>; 1459742af7e7SThierry Reding nvidia,xcvr-hsslew = <12>; 1460742af7e7SThierry Reding status = "disabled"; 1461742af7e7SThierry Reding }; 1462742af7e7SThierry Reding 1463742af7e7SThierry Reding cpus { 1464742af7e7SThierry Reding #address-cells = <1>; 1465742af7e7SThierry Reding #size-cells = <0>; 1466742af7e7SThierry Reding 1467742af7e7SThierry Reding cpu@0 { 1468742af7e7SThierry Reding device_type = "cpu"; 1469742af7e7SThierry Reding compatible = "arm,cortex-a57"; 1470742af7e7SThierry Reding reg = <0>; 147143b9b402SJoseph Lo clocks = <&tegra_car TEGRA210_CLK_CCLK_G>, 147243b9b402SJoseph Lo <&tegra_car TEGRA210_CLK_PLL_X>, 147343b9b402SJoseph Lo <&tegra_car TEGRA210_CLK_PLL_P_OUT4>, 147443b9b402SJoseph Lo <&dfll>; 147543b9b402SJoseph Lo clock-names = "cpu_g", "pll_x", "pll_p", "dfll"; 147643b9b402SJoseph Lo clock-latency = <300000>; 1477da77c6d9SJoseph Lo cpu-idle-states = <&CPU_SLEEP>; 14786c00cac1SJoseph Lo next-level-cache = <&L2>; 1479742af7e7SThierry Reding }; 1480742af7e7SThierry Reding 1481742af7e7SThierry Reding cpu@1 { 1482742af7e7SThierry Reding device_type = "cpu"; 1483742af7e7SThierry Reding compatible = "arm,cortex-a57"; 1484742af7e7SThierry Reding reg = <1>; 1485da77c6d9SJoseph Lo cpu-idle-states = <&CPU_SLEEP>; 14866c00cac1SJoseph Lo next-level-cache = <&L2>; 1487742af7e7SThierry Reding }; 1488742af7e7SThierry Reding 1489742af7e7SThierry Reding cpu@2 { 1490742af7e7SThierry Reding device_type = "cpu"; 1491742af7e7SThierry Reding compatible = "arm,cortex-a57"; 1492742af7e7SThierry Reding reg = <2>; 1493da77c6d9SJoseph Lo cpu-idle-states = <&CPU_SLEEP>; 14946c00cac1SJoseph Lo next-level-cache = <&L2>; 1495742af7e7SThierry Reding }; 1496742af7e7SThierry Reding 1497742af7e7SThierry Reding cpu@3 { 1498742af7e7SThierry Reding device_type = "cpu"; 1499742af7e7SThierry Reding compatible = "arm,cortex-a57"; 1500742af7e7SThierry Reding reg = <3>; 1501da77c6d9SJoseph Lo cpu-idle-states = <&CPU_SLEEP>; 15026c00cac1SJoseph Lo next-level-cache = <&L2>; 1503da77c6d9SJoseph Lo }; 1504da77c6d9SJoseph Lo 1505da77c6d9SJoseph Lo idle-states { 1506da77c6d9SJoseph Lo entry-method = "psci"; 1507da77c6d9SJoseph Lo 1508da77c6d9SJoseph Lo CPU_SLEEP: cpu-sleep { 1509da77c6d9SJoseph Lo compatible = "arm,idle-state"; 1510da77c6d9SJoseph Lo arm,psci-suspend-param = <0x40000007>; 1511da77c6d9SJoseph Lo entry-latency-us = <100>; 1512da77c6d9SJoseph Lo exit-latency-us = <30>; 1513da77c6d9SJoseph Lo min-residency-us = <1000>; 1514da77c6d9SJoseph Lo wakeup-latency-us = <130>; 1515da77c6d9SJoseph Lo idle-state-name = "cpu-sleep"; 1516da77c6d9SJoseph Lo status = "disabled"; 1517da77c6d9SJoseph Lo }; 1518742af7e7SThierry Reding }; 15196c00cac1SJoseph Lo 15206c00cac1SJoseph Lo L2: l2-cache { 15216c00cac1SJoseph Lo compatible = "cache"; 15226c00cac1SJoseph Lo }; 1523742af7e7SThierry Reding }; 1524742af7e7SThierry Reding 1525264064abSThierry Reding pmu { 1526264064abSThierry Reding compatible = "arm,armv8-pmuv3"; 1527264064abSThierry Reding interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1528264064abSThierry Reding <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1529264064abSThierry Reding <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1530264064abSThierry Reding <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 1531264064abSThierry Reding interrupt-affinity = <&{/cpus/cpu@0} &{/cpus/cpu@1} 1532264064abSThierry Reding &{/cpus/cpu@2} &{/cpus/cpu@3}>; 1533264064abSThierry Reding }; 1534264064abSThierry Reding 1535742af7e7SThierry Reding timer { 1536742af7e7SThierry Reding compatible = "arm,armv8-timer"; 1537742af7e7SThierry Reding interrupts = <GIC_PPI 13 1538742af7e7SThierry Reding (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1539742af7e7SThierry Reding <GIC_PPI 14 1540742af7e7SThierry Reding (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1541742af7e7SThierry Reding <GIC_PPI 11 1542742af7e7SThierry Reding (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1543742af7e7SThierry Reding <GIC_PPI 10 1544742af7e7SThierry Reding (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1545742af7e7SThierry Reding interrupt-parent = <&gic>; 15466b9e263bSThierry Reding arm,no-tick-in-suspend; 1547742af7e7SThierry Reding }; 1548e2bed1ebSWei Ni 1549e2bed1ebSWei Ni soctherm: thermal-sensor@700e2000 { 1550e2bed1ebSWei Ni compatible = "nvidia,tegra210-soctherm"; 1551cbd0f000SWei Ni reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */ 1552cbd0f000SWei Ni 0x0 0x60006000 0x0 0x400>; /* CAR reg_base */ 1553cbd0f000SWei Ni reg-names = "soctherm-reg", "car-reg"; 155444ff822cSThierry Reding interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 155544ff822cSThierry Reding <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 155644ff822cSThierry Reding interrupt-names = "thermal", "edp"; 1557e2bed1ebSWei Ni clocks = <&tegra_car TEGRA210_CLK_TSENSOR>, 1558e2bed1ebSWei Ni <&tegra_car TEGRA210_CLK_SOC_THERM>; 1559e2bed1ebSWei Ni clock-names = "tsensor", "soctherm"; 1560e2bed1ebSWei Ni resets = <&tegra_car 78>; 1561e2bed1ebSWei Ni reset-names = "soctherm"; 1562e2bed1ebSWei Ni #thermal-sensor-cells = <1>; 1563cbd0f000SWei Ni 1564cbd0f000SWei Ni throttle-cfgs { 1565cbd0f000SWei Ni throttle_heavy: heavy { 1566cbd0f000SWei Ni nvidia,priority = <100>; 1567cbd0f000SWei Ni nvidia,cpu-throt-percent = <85>; 1568cbd0f000SWei Ni 1569cbd0f000SWei Ni #cooling-cells = <2>; 1570cbd0f000SWei Ni }; 1571cbd0f000SWei Ni }; 1572e2bed1ebSWei Ni }; 1573e2bed1ebSWei Ni 1574e2bed1ebSWei Ni thermal-zones { 1575e2bed1ebSWei Ni cpu { 1576e2bed1ebSWei Ni polling-delay-passive = <1000>; 1577e2bed1ebSWei Ni polling-delay = <0>; 1578e2bed1ebSWei Ni 1579e2bed1ebSWei Ni thermal-sensors = 1580e2bed1ebSWei Ni <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; 15815e03f663SWei Ni 15825e03f663SWei Ni trips { 15835e03f663SWei Ni cpu-shutdown-trip { 15845e03f663SWei Ni temperature = <102500>; 15855e03f663SWei Ni hysteresis = <0>; 15865e03f663SWei Ni type = "critical"; 15875e03f663SWei Ni }; 1588cbd0f000SWei Ni 1589cbd0f000SWei Ni cpu_throttle_trip: throttle-trip { 1590cbd0f000SWei Ni temperature = <98500>; 1591cbd0f000SWei Ni hysteresis = <1000>; 1592cbd0f000SWei Ni type = "hot"; 1593cbd0f000SWei Ni }; 15945e03f663SWei Ni }; 15955e03f663SWei Ni 15965e03f663SWei Ni cooling-maps { 1597cbd0f000SWei Ni map0 { 1598cbd0f000SWei Ni trip = <&cpu_throttle_trip>; 1599cbd0f000SWei Ni cooling-device = <&throttle_heavy 1 1>; 1600cbd0f000SWei Ni }; 16015e03f663SWei Ni }; 1602e2bed1ebSWei Ni }; 160324fc3363SThierry Reding 1604e2bed1ebSWei Ni mem { 1605e2bed1ebSWei Ni polling-delay-passive = <0>; 1606e2bed1ebSWei Ni polling-delay = <0>; 1607e2bed1ebSWei Ni 1608e2bed1ebSWei Ni thermal-sensors = 1609e2bed1ebSWei Ni <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>; 16105e03f663SWei Ni 16115e03f663SWei Ni trips { 1612e12325f6SThierry Reding dram_nominal: mem-nominal-trip { 1613e12325f6SThierry Reding temperature = <50000>; 1614e12325f6SThierry Reding hysteresis = <1000>; 1615e12325f6SThierry Reding type = "passive"; 1616e12325f6SThierry Reding }; 1617e12325f6SThierry Reding 1618e12325f6SThierry Reding dram_throttle: mem-throttle-trip { 1619e12325f6SThierry Reding temperature = <70000>; 1620e12325f6SThierry Reding hysteresis = <1000>; 1621e12325f6SThierry Reding type = "active"; 1622e12325f6SThierry Reding }; 1623e12325f6SThierry Reding 16245e03f663SWei Ni mem-shutdown-trip { 16255e03f663SWei Ni temperature = <103000>; 16265e03f663SWei Ni hysteresis = <0>; 16275e03f663SWei Ni type = "critical"; 16285e03f663SWei Ni }; 16295e03f663SWei Ni }; 16305e03f663SWei Ni 16315e03f663SWei Ni cooling-maps { 1632e12325f6SThierry Reding dram-passive { 1633e12325f6SThierry Reding cooling-device = <&emc 0 0>; 1634e12325f6SThierry Reding trip = <&dram_nominal>; 1635e12325f6SThierry Reding }; 1636e12325f6SThierry Reding 1637e12325f6SThierry Reding dram-active { 1638e12325f6SThierry Reding cooling-device = <&emc 1 1>; 1639e12325f6SThierry Reding trip = <&dram_throttle>; 1640e12325f6SThierry Reding }; 16415e03f663SWei Ni }; 1642e2bed1ebSWei Ni }; 164324fc3363SThierry Reding 1644e2bed1ebSWei Ni gpu { 1645e2bed1ebSWei Ni polling-delay-passive = <1000>; 1646e2bed1ebSWei Ni polling-delay = <0>; 1647e2bed1ebSWei Ni 1648e2bed1ebSWei Ni thermal-sensors = 1649e2bed1ebSWei Ni <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>; 16505e03f663SWei Ni 16515e03f663SWei Ni trips { 16525e03f663SWei Ni gpu-shutdown-trip { 16535e03f663SWei Ni temperature = <103000>; 16545e03f663SWei Ni hysteresis = <0>; 16555e03f663SWei Ni type = "critical"; 16565e03f663SWei Ni }; 1657cbd0f000SWei Ni 1658cbd0f000SWei Ni gpu_throttle_trip: throttle-trip { 1659cbd0f000SWei Ni temperature = <100000>; 1660cbd0f000SWei Ni hysteresis = <1000>; 1661cbd0f000SWei Ni type = "hot"; 1662cbd0f000SWei Ni }; 16635e03f663SWei Ni }; 16645e03f663SWei Ni 16655e03f663SWei Ni cooling-maps { 1666cbd0f000SWei Ni map0 { 1667cbd0f000SWei Ni trip = <&gpu_throttle_trip>; 1668cbd0f000SWei Ni cooling-device = <&throttle_heavy 1 1>; 1669cbd0f000SWei Ni }; 16705e03f663SWei Ni }; 1671e2bed1ebSWei Ni }; 167224fc3363SThierry Reding 1673e2bed1ebSWei Ni pllx { 1674e2bed1ebSWei Ni polling-delay-passive = <0>; 1675e2bed1ebSWei Ni polling-delay = <0>; 1676e2bed1ebSWei Ni 1677e2bed1ebSWei Ni thermal-sensors = 1678e2bed1ebSWei Ni <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>; 16795e03f663SWei Ni 16805e03f663SWei Ni trips { 16815e03f663SWei Ni pllx-shutdown-trip { 16825e03f663SWei Ni temperature = <103000>; 16835e03f663SWei Ni hysteresis = <0>; 16845e03f663SWei Ni type = "critical"; 16855e03f663SWei Ni }; 16865e03f663SWei Ni }; 16875e03f663SWei Ni 16885e03f663SWei Ni cooling-maps { 16895e03f663SWei Ni /* 16905e03f663SWei Ni * There are currently no cooling maps, 16915e03f663SWei Ni * because there are no cooling devices. 16925e03f663SWei Ni */ 16935e03f663SWei Ni }; 1694e2bed1ebSWei Ni }; 1695e2bed1ebSWei Ni }; 1696742af7e7SThierry Reding}; 1697