1// SPDX-License-Identifier: GPL-2.0 2/dts-v1/; 3 4#include <dt-bindings/input/gpio-keys.h> 5#include <dt-bindings/input/linux-event-codes.h> 6#include <dt-bindings/mfd/max77620.h> 7 8#include "tegra210.dtsi" 9 10/ { 11 model = "NVIDIA Jetson Nano Developer Kit"; 12 compatible = "nvidia,p3450-0000", "nvidia,tegra210"; 13 14 aliases { 15 ethernet = "/pcie@1003000/pci@2,0/ethernet@0,0"; 16 rtc0 = "/i2c@7000d000/pmic@3c"; 17 rtc1 = "/rtc@7000e000"; 18 serial0 = &uarta; 19 }; 20 21 chosen { 22 stdout-path = "serial0:115200n8"; 23 }; 24 25 memory@80000000 { 26 device_type = "memory"; 27 reg = <0x0 0x80000000 0x1 0x0>; 28 }; 29 30 pcie@1003000 { 31 status = "okay"; 32 33 avdd-pll-uerefe-supply = <&vdd_pex_1v05>; 34 hvddio-pex-supply = <&vdd_1v8>; 35 dvddio-pex-supply = <&vdd_pex_1v05>; 36 dvdd-pex-pll-supply = <&vdd_pex_1v05>; 37 hvdd-pex-pll-e-supply = <&vdd_1v8>; 38 vddio-pex-ctl-supply = <&vdd_1v8>; 39 40 pci@1,0 { 41 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>, 42 <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>, 43 <&{/padctl@7009f000/pads/pcie/lanes/pcie-3}>, 44 <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>; 45 phy-names = "pcie-0", "pcie-1", "pcie-2", "pcie-3"; 46 nvidia,num-lanes = <4>; 47 status = "okay"; 48 }; 49 50 pci@2,0 { 51 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>; 52 phy-names = "pcie-0"; 53 status = "okay"; 54 55 ethernet@0,0 { 56 reg = <0x000000 0 0 0 0>; 57 local-mac-address = [ 00 00 00 00 00 00 ]; 58 }; 59 }; 60 }; 61 62 host1x@50000000 { 63 dpaux@54040000 { 64 status = "okay"; 65 }; 66 67 vi@54080000 { 68 status = "okay"; 69 70 avdd-dsi-csi-supply = <&vdd_sys_1v2>; 71 72 csi@838 { 73 status = "okay"; 74 }; 75 }; 76 77 sor@54540000 { 78 status = "okay"; 79 80 avdd-io-hdmi-dp-supply = <&avdd_io_edp_1v05>; 81 vdd-hdmi-dp-pll-supply = <&vdd_1v8>; 82 83 nvidia,xbar-cfg = <2 1 0 3 4>; 84 nvidia,dpaux = <&dpaux>; 85 }; 86 87 sor@54580000 { 88 status = "okay"; 89 90 avdd-io-hdmi-dp-supply = <&avdd_1v05>; 91 vdd-hdmi-dp-pll-supply = <&vdd_1v8>; 92 hdmi-supply = <&vdd_hdmi>; 93 94 nvidia,ddc-i2c-bus = <&hdmi_ddc>; 95 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(CC, 1) 96 GPIO_ACTIVE_LOW>; 97 nvidia,xbar-cfg = <0 1 2 3 4>; 98 }; 99 100 dpaux@545c0000 { 101 status = "okay"; 102 }; 103 104 i2c@546c0000 { 105 status = "okay"; 106 }; 107 }; 108 109 gpu@57000000 { 110 vdd-supply = <&vdd_gpu>; 111 status = "okay"; 112 }; 113 114 pinmux@700008d4 { 115 dvfs_pwm_active_state: dvfs_pwm_active { 116 dvfs_pwm_pbb1 { 117 nvidia,pins = "dvfs_pwm_pbb1"; 118 nvidia,tristate = <TEGRA_PIN_DISABLE>; 119 }; 120 }; 121 122 dvfs_pwm_inactive_state: dvfs_pwm_inactive { 123 dvfs_pwm_pbb1 { 124 nvidia,pins = "dvfs_pwm_pbb1"; 125 nvidia,tristate = <TEGRA_PIN_ENABLE>; 126 }; 127 }; 128 }; 129 130 /* debug port */ 131 serial@70006000 { 132 status = "okay"; 133 }; 134 135 pwm@7000a000 { 136 status = "okay"; 137 }; 138 139 i2c@7000c500 { 140 status = "okay"; 141 clock-frequency = <100000>; 142 143 eeprom@50 { 144 compatible = "atmel,24c02"; 145 reg = <0x50>; 146 147 label = "module"; 148 vcc-supply = <&vdd_1v8>; 149 address-width = <8>; 150 pagesize = <8>; 151 size = <256>; 152 read-only; 153 }; 154 155 eeprom@57 { 156 compatible = "atmel,24c02"; 157 reg = <0x57>; 158 159 label = "system"; 160 vcc-supply = <&vdd_1v8>; 161 address-width = <8>; 162 pagesize = <8>; 163 size = <256>; 164 read-only; 165 }; 166 }; 167 168 hdmi_ddc: i2c@7000c700 { 169 status = "okay"; 170 clock-frequency = <100000>; 171 }; 172 173 i2c@7000d000 { 174 status = "okay"; 175 clock-frequency = <400000>; 176 177 pmic: pmic@3c { 178 compatible = "maxim,max77620"; 179 reg = <0x3c>; 180 interrupt-parent = <&tegra_pmc>; 181 interrupts = <51 IRQ_TYPE_LEVEL_LOW>; 182 183 #interrupt-cells = <2>; 184 interrupt-controller; 185 186 #gpio-cells = <2>; 187 gpio-controller; 188 189 pinctrl-names = "default"; 190 pinctrl-0 = <&max77620_default>; 191 192 max77620_default: pinmux { 193 gpio0 { 194 pins = "gpio0"; 195 function = "gpio"; 196 }; 197 198 gpio1 { 199 pins = "gpio1"; 200 function = "fps-out"; 201 drive-push-pull = <1>; 202 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; 203 maxim,active-fps-power-up-slot = <0>; 204 maxim,active-fps-power-down-slot = <7>; 205 }; 206 207 gpio2 { 208 pins = "gpio2"; 209 function = "fps-out"; 210 drive-open-drain = <1>; 211 maxim,active-fps-source = <MAX77620_FPS_SRC_0>; 212 maxim,active-fps-power-up-slot = <0>; 213 maxim,active-fps-power-down-slot = <7>; 214 }; 215 216 gpio3 { 217 pins = "gpio3"; 218 function = "fps-out"; 219 drive-open-drain = <1>; 220 maxim,active-fps-source = <MAX77620_FPS_SRC_0>; 221 maxim,active-fps-power-up-slot = <4>; 222 maxim,active-fps-power-down-slot = <3>; 223 }; 224 225 gpio4 { 226 pins = "gpio4"; 227 function = "32k-out1"; 228 }; 229 230 gpio5_6_7 { 231 pins = "gpio5", "gpio6", "gpio7"; 232 function = "gpio"; 233 drive-push-pull = <1>; 234 }; 235 }; 236 237 fps { 238 fps0 { 239 maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; 240 maxim,suspend-fps-time-period-us = <5120>; 241 }; 242 243 fps1 { 244 maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>; 245 maxim,suspend-fps-time-period-us = <5120>; 246 }; 247 248 fps2 { 249 maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; 250 }; 251 }; 252 253 regulators { 254 in-ldo0-1-supply = <&vdd_pre>; 255 in-ldo2-supply = <&vdd_3v3_sys>; 256 in-ldo3-5-supply = <&vdd_1v8>; 257 in-ldo4-6-supply = <&vdd_5v0_sys>; 258 in-ldo7-8-supply = <&vdd_pre>; 259 in-sd0-supply = <&vdd_5v0_sys>; 260 in-sd1-supply = <&vdd_5v0_sys>; 261 in-sd2-supply = <&vdd_5v0_sys>; 262 in-sd3-supply = <&vdd_5v0_sys>; 263 264 vdd_soc: sd0 { 265 regulator-name = "VDD_SOC"; 266 regulator-min-microvolt = <1000000>; 267 regulator-max-microvolt = <1170000>; 268 regulator-enable-ramp-delay = <146>; 269 regulator-ramp-delay = <27500>; 270 regulator-ramp-delay-scale = <300>; 271 regulator-always-on; 272 regulator-boot-on; 273 274 maxim,active-fps-source = <MAX77620_FPS_SRC_1>; 275 maxim,active-fps-power-up-slot = <1>; 276 maxim,active-fps-power-down-slot = <6>; 277 }; 278 279 vdd_ddr: sd1 { 280 regulator-name = "VDD_DDR_1V1_PMIC"; 281 regulator-min-microvolt = <1150000>; 282 regulator-max-microvolt = <1150000>; 283 regulator-enable-ramp-delay = <176>; 284 regulator-ramp-delay = <27500>; 285 regulator-ramp-delay-scale = <300>; 286 regulator-always-on; 287 regulator-boot-on; 288 289 maxim,active-fps-source = <MAX77620_FPS_SRC_0>; 290 maxim,active-fps-power-up-slot = <5>; 291 maxim,active-fps-power-down-slot = <2>; 292 }; 293 294 vdd_pre: sd2 { 295 regulator-name = "VDD_PRE_REG_1V35"; 296 regulator-min-microvolt = <1350000>; 297 regulator-max-microvolt = <1350000>; 298 regulator-enable-ramp-delay = <176>; 299 regulator-ramp-delay = <27500>; 300 regulator-ramp-delay-scale = <350>; 301 regulator-always-on; 302 regulator-boot-on; 303 304 maxim,active-fps-source = <MAX77620_FPS_SRC_1>; 305 maxim,active-fps-power-up-slot = <2>; 306 maxim,active-fps-power-down-slot = <5>; 307 }; 308 309 vdd_1v8: sd3 { 310 regulator-name = "VDD_1V8"; 311 regulator-min-microvolt = <1800000>; 312 regulator-max-microvolt = <1800000>; 313 regulator-enable-ramp-delay = <242>; 314 regulator-ramp-delay = <27500>; 315 regulator-ramp-delay-scale = <360>; 316 regulator-always-on; 317 regulator-boot-on; 318 319 maxim,active-fps-source = <MAX77620_FPS_SRC_0>; 320 maxim,active-fps-power-up-slot = <3>; 321 maxim,active-fps-power-down-slot = <4>; 322 }; 323 324 vdd_sys_1v2: ldo0 { 325 regulator-name = "AVDD_SYS_1V2"; 326 regulator-min-microvolt = <1200000>; 327 regulator-max-microvolt = <1200000>; 328 regulator-enable-ramp-delay = <26>; 329 regulator-ramp-delay = <100000>; 330 regulator-ramp-delay-scale = <200>; 331 regulator-always-on; 332 regulator-boot-on; 333 334 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; 335 maxim,active-fps-power-up-slot = <0>; 336 maxim,active-fps-power-down-slot = <7>; 337 }; 338 339 vdd_pex_1v05: ldo1 { 340 regulator-name = "VDD_PEX_1V05"; 341 regulator-min-microvolt = <1050000>; 342 regulator-max-microvolt = <1050000>; 343 regulator-enable-ramp-delay = <22>; 344 regulator-ramp-delay = <100000>; 345 regulator-ramp-delay-scale = <200>; 346 347 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; 348 maxim,active-fps-power-up-slot = <0>; 349 maxim,active-fps-power-down-slot = <7>; 350 }; 351 352 vddio_sdmmc: ldo2 { 353 regulator-name = "VDDIO_SDMMC"; 354 regulator-min-microvolt = <1800000>; 355 regulator-max-microvolt = <3300000>; 356 regulator-enable-ramp-delay = <62>; 357 regulator-ramp-delay = <100000>; 358 regulator-ramp-delay-scale = <200>; 359 360 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; 361 maxim,active-fps-power-up-slot = <0>; 362 maxim,active-fps-power-down-slot = <7>; 363 }; 364 365 ldo3 { 366 status = "disabled"; 367 }; 368 369 vdd_rtc: ldo4 { 370 regulator-name = "VDD_RTC"; 371 regulator-min-microvolt = <850000>; 372 regulator-max-microvolt = <1100000>; 373 regulator-enable-ramp-delay = <22>; 374 regulator-ramp-delay = <100000>; 375 regulator-ramp-delay-scale = <200>; 376 regulator-disable-active-discharge; 377 regulator-always-on; 378 regulator-boot-on; 379 380 maxim,active-fps-source = <MAX77620_FPS_SRC_0>; 381 maxim,active-fps-power-up-slot = <1>; 382 maxim,active-fps-power-down-slot = <6>; 383 }; 384 385 ldo5 { 386 status = "disabled"; 387 }; 388 389 ldo6 { 390 status = "disabled"; 391 }; 392 393 avdd_1v05_pll: ldo7 { 394 regulator-name = "AVDD_1V05_PLL"; 395 regulator-min-microvolt = <1050000>; 396 regulator-max-microvolt = <1050000>; 397 regulator-enable-ramp-delay = <24>; 398 regulator-ramp-delay = <100000>; 399 regulator-ramp-delay-scale = <200>; 400 401 maxim,active-fps-source = <MAX77620_FPS_SRC_1>; 402 maxim,active-fps-power-up-slot = <3>; 403 maxim,active-fps-power-down-slot = <4>; 404 }; 405 406 avdd_1v05: ldo8 { 407 regulator-name = "AVDD_SATA_HDMI_DP_1V05"; 408 regulator-min-microvolt = <1050000>; 409 regulator-max-microvolt = <1050000>; 410 regulator-enable-ramp-delay = <22>; 411 regulator-ramp-delay = <100000>; 412 regulator-ramp-delay-scale = <200>; 413 414 maxim,active-fps-source = <MAX77620_FPS_SRC_1>; 415 maxim,active-fps-power-up-slot = <6>; 416 maxim,active-fps-power-down-slot = <1>; 417 }; 418 }; 419 }; 420 }; 421 422 pmc@7000e400 { 423 nvidia,invert-interrupt; 424 nvidia,suspend-mode = <0>; 425 nvidia,cpu-pwr-good-time = <0>; 426 nvidia,cpu-pwr-off-time = <0>; 427 nvidia,core-pwr-good-time = <4587 3876>; 428 nvidia,core-pwr-off-time = <39065>; 429 nvidia,core-power-req-active-high; 430 nvidia,sys-clock-req-active-high; 431 }; 432 433 hda@70030000 { 434 nvidia,model = "NVIDIA Jetson Nano HDA"; 435 436 status = "okay"; 437 }; 438 439 usb@70090000 { 440 phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>, 441 <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>, 442 <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>, 443 <&{/padctl@7009f000/pads/pcie/lanes/pcie-6}>; 444 phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0"; 445 446 avdd-usb-supply = <&vdd_3v3_sys>; 447 dvddio-pex-supply = <&vdd_pex_1v05>; 448 hvddio-pex-supply = <&vdd_1v8>; 449 /* these really belong to the XUSB pad controller */ 450 avdd-pll-utmip-supply = <&vdd_1v8>; 451 avdd-pll-uerefe-supply = <&vdd_pex_1v05>; 452 dvdd-usb-ss-pll-supply = <&vdd_pex_1v05>; 453 hvdd-usb-ss-pll-e-supply = <&vdd_1v8>; 454 455 status = "okay"; 456 }; 457 458 padctl@7009f000 { 459 status = "okay"; 460 461 avdd-pll-utmip-supply = <&vdd_1v8>; 462 avdd-pll-uerefe-supply = <&vdd_pex_1v05>; 463 dvdd-pex-pll-supply = <&vdd_pex_1v05>; 464 hvdd-pex-pll-e-supply = <&vdd_1v8>; 465 466 pads { 467 usb2 { 468 status = "okay"; 469 470 lanes { 471 micro_b: usb2-0 { 472 nvidia,function = "xusb"; 473 status = "okay"; 474 }; 475 476 usb2-1 { 477 nvidia,function = "xusb"; 478 status = "okay"; 479 }; 480 481 usb2-2 { 482 nvidia,function = "xusb"; 483 status = "okay"; 484 }; 485 }; 486 }; 487 488 pcie { 489 status = "okay"; 490 491 lanes { 492 pcie-0 { 493 nvidia,function = "pcie-x1"; 494 status = "okay"; 495 }; 496 497 pcie-1 { 498 nvidia,function = "pcie-x4"; 499 status = "okay"; 500 }; 501 502 pcie-2 { 503 nvidia,function = "pcie-x4"; 504 status = "okay"; 505 }; 506 507 pcie-3 { 508 nvidia,function = "pcie-x4"; 509 status = "okay"; 510 }; 511 512 pcie-4 { 513 nvidia,function = "pcie-x4"; 514 status = "okay"; 515 }; 516 517 pcie-5 { 518 nvidia,function = "usb3-ss"; 519 status = "okay"; 520 }; 521 522 pcie-6 { 523 nvidia,function = "usb3-ss"; 524 status = "okay"; 525 }; 526 }; 527 }; 528 }; 529 530 ports { 531 usb2-0 { 532 status = "okay"; 533 mode = "peripheral"; 534 usb-role-switch; 535 536 vbus-supply = <&vdd_5v0_usb>; 537 538 connector { 539 compatible = "gpio-usb-b-connector", 540 "usb-b-connector"; 541 label = "micro-USB"; 542 type = "micro"; 543 vbus-gpios = <&gpio TEGRA_GPIO(CC, 4) 544 GPIO_ACTIVE_LOW>; 545 }; 546 }; 547 548 usb2-1 { 549 status = "okay"; 550 mode = "host"; 551 }; 552 553 usb2-2 { 554 status = "okay"; 555 mode = "host"; 556 }; 557 558 usb3-0 { 559 status = "okay"; 560 nvidia,usb2-companion = <1>; 561 vbus-supply = <&vdd_hub_3v3>; 562 }; 563 }; 564 }; 565 566 mmc@700b0000 { 567 status = "okay"; 568 bus-width = <4>; 569 570 cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>; 571 disable-wp; 572 573 vqmmc-supply = <&vddio_sdmmc>; 574 vmmc-supply = <&vdd_3v3_sd>; 575 }; 576 577 mmc@700b0400 { 578 status = "okay"; 579 bus-width = <4>; 580 581 vqmmc-supply = <&vdd_1v8>; 582 vmmc-supply = <&vdd_3v3_sys>; 583 584 non-removable; 585 cap-sdio-irq; 586 keep-power-in-suspend; 587 wakeup-source; 588 }; 589 590 usb@700d0000 { 591 status = "okay"; 592 phys = <µ_b>; 593 phy-names = "usb2-0"; 594 avddio-usb-supply = <&vdd_3v3_sys>; 595 hvdd-usb-supply = <&vdd_1v8>; 596 }; 597 598 clock@70110000 { 599 status = "okay"; 600 601 nvidia,cf = <6>; 602 nvidia,ci = <0>; 603 nvidia,cg = <2>; 604 nvidia,droop-ctrl = <0x00000f00>; 605 nvidia,force-mode = <1>; 606 nvidia,sample-rate = <25000>; 607 608 nvidia,pwm-min-microvolts = <708000>; 609 nvidia,pwm-period-nanoseconds = <2500>; /* 2.5us */ 610 nvidia,pwm-to-pmic; 611 nvidia,pwm-tristate-microvolts = <1000000>; 612 nvidia,pwm-voltage-step-microvolts = <19200>; 613 614 pinctrl-names = "dvfs_pwm_enable", "dvfs_pwm_disable"; 615 pinctrl-0 = <&dvfs_pwm_active_state>; 616 pinctrl-1 = <&dvfs_pwm_inactive_state>; 617 }; 618 619 aconnect@702c0000 { 620 status = "okay"; 621 622 dma-controller@702e2000 { 623 status = "okay"; 624 }; 625 626 interrupt-controller@702f9000 { 627 status = "okay"; 628 }; 629 630 ahub@702d0800 { 631 status = "okay"; 632 633 admaif@702d0000 { 634 status = "okay"; 635 }; 636 637 i2s@702d1200 { 638 status = "okay"; 639 640 ports { 641 #address-cells = <1>; 642 #size-cells = <0>; 643 644 port@0 { 645 reg = <0>; 646 647 i2s3_cif_ep: endpoint { 648 remote-endpoint = <&xbar_i2s3_ep>; 649 }; 650 }; 651 652 i2s3_port: port@1 { 653 reg = <1>; 654 655 i2s3_dap_ep: endpoint { 656 dai-format = "i2s"; 657 /* Placeholder for external Codec */ 658 }; 659 }; 660 }; 661 }; 662 663 i2s@702d1300 { 664 status = "okay"; 665 666 ports { 667 #address-cells = <1>; 668 #size-cells = <0>; 669 670 port@0 { 671 reg = <0>; 672 673 i2s4_cif_ep: endpoint { 674 remote-endpoint = <&xbar_i2s4_ep>; 675 }; 676 }; 677 678 i2s4_port: port@1 { 679 reg = <1>; 680 681 i2s4_dap_ep: endpoint { 682 dai-format = "i2s"; 683 /* Placeholder for external Codec */ 684 }; 685 }; 686 }; 687 }; 688 689 dmic@702d4000 { 690 status = "okay"; 691 692 ports { 693 #address-cells = <1>; 694 #size-cells = <0>; 695 696 port@0 { 697 reg = <0>; 698 699 dmic1_cif_ep: endpoint { 700 remote-endpoint = <&xbar_dmic1_ep>; 701 }; 702 }; 703 704 dmic1_port: port@1 { 705 reg = <1>; 706 707 dmic1_dap_ep: endpoint { 708 /* Placeholder for external Codec */ 709 }; 710 }; 711 }; 712 }; 713 714 dmic@702d4100 { 715 status = "okay"; 716 717 ports { 718 #address-cells = <1>; 719 #size-cells = <0>; 720 721 port@0 { 722 reg = <0>; 723 724 dmic2_cif_ep: endpoint { 725 remote-endpoint = <&xbar_dmic2_ep>; 726 }; 727 }; 728 729 dmic2_port: port@1 { 730 reg = <1>; 731 732 dmic2_dap_ep: endpoint { 733 /* Placeholder for external Codec */ 734 }; 735 }; 736 }; 737 }; 738 739 sfc@702d2000 { 740 status = "okay"; 741 742 ports { 743 #address-cells = <1>; 744 #size-cells = <0>; 745 746 port@0 { 747 reg = <0>; 748 749 sfc1_cif_in_ep: endpoint { 750 remote-endpoint = <&xbar_sfc1_in_ep>; 751 }; 752 }; 753 754 sfc1_out_port: port@1 { 755 reg = <1>; 756 757 sfc1_cif_out_ep: endpoint { 758 remote-endpoint = <&xbar_sfc1_out_ep>; 759 }; 760 }; 761 }; 762 }; 763 764 sfc@702d2200 { 765 status = "okay"; 766 767 ports { 768 #address-cells = <1>; 769 #size-cells = <0>; 770 771 port@0 { 772 reg = <0>; 773 774 sfc2_cif_in_ep: endpoint { 775 remote-endpoint = <&xbar_sfc2_in_ep>; 776 }; 777 }; 778 779 sfc2_out_port: port@1 { 780 reg = <1>; 781 782 sfc2_cif_out_ep: endpoint { 783 remote-endpoint = <&xbar_sfc2_out_ep>; 784 }; 785 }; 786 }; 787 }; 788 789 sfc@702d2400 { 790 status = "okay"; 791 792 ports { 793 #address-cells = <1>; 794 #size-cells = <0>; 795 796 port@0 { 797 reg = <0>; 798 799 sfc3_cif_in_ep: endpoint { 800 remote-endpoint = <&xbar_sfc3_in_ep>; 801 }; 802 }; 803 804 sfc3_out_port: port@1 { 805 reg = <1>; 806 807 sfc3_cif_out_ep: endpoint { 808 remote-endpoint = <&xbar_sfc3_out_ep>; 809 }; 810 }; 811 }; 812 }; 813 814 sfc@702d2600 { 815 status = "okay"; 816 817 ports { 818 #address-cells = <1>; 819 #size-cells = <0>; 820 821 port@0 { 822 reg = <0>; 823 824 sfc4_cif_in_ep: endpoint { 825 remote-endpoint = <&xbar_sfc4_in_ep>; 826 }; 827 }; 828 829 sfc4_out_port: port@1 { 830 reg = <1>; 831 832 sfc4_cif_out_ep: endpoint { 833 remote-endpoint = <&xbar_sfc4_out_ep>; 834 }; 835 }; 836 }; 837 }; 838 839 mvc@702da000 { 840 status = "okay"; 841 842 ports { 843 #address-cells = <1>; 844 #size-cells = <0>; 845 846 port@0 { 847 reg = <0>; 848 849 mvc1_cif_in_ep: endpoint { 850 remote-endpoint = <&xbar_mvc1_in_ep>; 851 }; 852 }; 853 854 mvc1_out_port: port@1 { 855 reg = <1>; 856 857 mvc1_cif_out_ep: endpoint { 858 remote-endpoint = <&xbar_mvc1_out_ep>; 859 }; 860 }; 861 }; 862 }; 863 864 mvc@702da200 { 865 status = "okay"; 866 867 ports { 868 #address-cells = <1>; 869 #size-cells = <0>; 870 871 port@0 { 872 reg = <0>; 873 874 mvc2_cif_in_ep: endpoint { 875 remote-endpoint = <&xbar_mvc2_in_ep>; 876 }; 877 }; 878 879 mvc2_out_port: port@1 { 880 reg = <1>; 881 882 mvc2_cif_out_ep: endpoint { 883 remote-endpoint = <&xbar_mvc2_out_ep>; 884 }; 885 }; 886 }; 887 }; 888 889 amx@702d3000 { 890 status = "okay"; 891 892 ports { 893 #address-cells = <1>; 894 #size-cells = <0>; 895 896 port@0 { 897 reg = <0>; 898 899 amx1_in1_ep: endpoint { 900 remote-endpoint = <&xbar_amx1_in1_ep>; 901 }; 902 }; 903 904 port@1 { 905 reg = <1>; 906 907 amx1_in2_ep: endpoint { 908 remote-endpoint = <&xbar_amx1_in2_ep>; 909 }; 910 }; 911 912 port@2 { 913 reg = <2>; 914 915 amx1_in3_ep: endpoint { 916 remote-endpoint = <&xbar_amx1_in3_ep>; 917 }; 918 }; 919 920 port@3 { 921 reg = <3>; 922 923 amx1_in4_ep: endpoint { 924 remote-endpoint = <&xbar_amx1_in4_ep>; 925 }; 926 }; 927 928 amx1_out_port: port@4 { 929 reg = <4>; 930 931 amx1_out_ep: endpoint { 932 remote-endpoint = <&xbar_amx1_out_ep>; 933 }; 934 }; 935 }; 936 }; 937 938 amx@702d3100 { 939 status = "okay"; 940 941 ports { 942 #address-cells = <1>; 943 #size-cells = <0>; 944 945 port@0 { 946 reg = <0>; 947 948 amx2_in1_ep: endpoint { 949 remote-endpoint = <&xbar_amx2_in1_ep>; 950 }; 951 }; 952 953 port@1 { 954 reg = <1>; 955 956 amx2_in2_ep: endpoint { 957 remote-endpoint = <&xbar_amx2_in2_ep>; 958 }; 959 }; 960 961 amx2_in3_port: port@2 { 962 reg = <2>; 963 964 amx2_in3_ep: endpoint { 965 remote-endpoint = <&xbar_amx2_in3_ep>; 966 }; 967 }; 968 969 amx2_in4_port: port@3 { 970 reg = <3>; 971 972 amx2_in4_ep: endpoint { 973 remote-endpoint = <&xbar_amx2_in4_ep>; 974 }; 975 }; 976 977 amx2_out_port: port@4 { 978 reg = <4>; 979 980 amx2_out_ep: endpoint { 981 remote-endpoint = <&xbar_amx2_out_ep>; 982 }; 983 }; 984 }; 985 }; 986 987 adx@702d3800 { 988 status = "okay"; 989 990 ports { 991 #address-cells = <1>; 992 #size-cells = <0>; 993 994 port@0 { 995 reg = <0>; 996 997 adx1_in_ep: endpoint { 998 remote-endpoint = <&xbar_adx1_in_ep>; 999 }; 1000 }; 1001 1002 adx1_out1_port: port@1 { 1003 reg = <1>; 1004 1005 adx1_out1_ep: endpoint { 1006 remote-endpoint = <&xbar_adx1_out1_ep>; 1007 }; 1008 }; 1009 1010 adx1_out2_port: port@2 { 1011 reg = <2>; 1012 1013 adx1_out2_ep: endpoint { 1014 remote-endpoint = <&xbar_adx1_out2_ep>; 1015 }; 1016 }; 1017 1018 adx1_out3_port: port@3 { 1019 reg = <3>; 1020 1021 adx1_out3_ep: endpoint { 1022 remote-endpoint = <&xbar_adx1_out3_ep>; 1023 }; 1024 }; 1025 1026 adx1_out4_port: port@4 { 1027 reg = <4>; 1028 1029 adx1_out4_ep: endpoint { 1030 remote-endpoint = <&xbar_adx1_out4_ep>; 1031 }; 1032 }; 1033 }; 1034 }; 1035 1036 adx@702d3900 { 1037 status = "okay"; 1038 1039 ports { 1040 #address-cells = <1>; 1041 #size-cells = <0>; 1042 1043 port@0 { 1044 reg = <0>; 1045 1046 adx2_in_ep: endpoint { 1047 remote-endpoint = <&xbar_adx2_in_ep>; 1048 }; 1049 }; 1050 1051 adx2_out1_port: port@1 { 1052 reg = <1>; 1053 1054 adx2_out1_ep: endpoint { 1055 remote-endpoint = <&xbar_adx2_out1_ep>; 1056 }; 1057 }; 1058 1059 adx2_out2_port: port@2 { 1060 reg = <2>; 1061 1062 adx2_out2_ep: endpoint { 1063 remote-endpoint = <&xbar_adx2_out2_ep>; 1064 }; 1065 }; 1066 1067 adx2_out3_port: port@3 { 1068 reg = <3>; 1069 1070 adx2_out3_ep: endpoint { 1071 remote-endpoint = <&xbar_adx2_out3_ep>; 1072 }; 1073 }; 1074 1075 adx2_out4_port: port@4 { 1076 reg = <4>; 1077 1078 adx2_out4_ep: endpoint { 1079 remote-endpoint = <&xbar_adx2_out4_ep>; 1080 }; 1081 }; 1082 }; 1083 }; 1084 1085 amixer@702dbb00 { 1086 status = "okay"; 1087 1088 ports { 1089 #address-cells = <1>; 1090 #size-cells = <0>; 1091 1092 port@0 { 1093 reg = <0x0>; 1094 1095 mixer_in1_ep: endpoint { 1096 remote-endpoint = <&xbar_mixer_in1_ep>; 1097 }; 1098 }; 1099 1100 port@1 { 1101 reg = <0x1>; 1102 1103 mixer_in2_ep: endpoint { 1104 remote-endpoint = <&xbar_mixer_in2_ep>; 1105 }; 1106 }; 1107 1108 port@2 { 1109 reg = <0x2>; 1110 1111 mixer_in3_ep: endpoint { 1112 remote-endpoint = <&xbar_mixer_in3_ep>; 1113 }; 1114 }; 1115 1116 port@3 { 1117 reg = <0x3>; 1118 1119 mixer_in4_ep: endpoint { 1120 remote-endpoint = <&xbar_mixer_in4_ep>; 1121 }; 1122 }; 1123 1124 port@4 { 1125 reg = <0x4>; 1126 1127 mixer_in5_ep: endpoint { 1128 remote-endpoint = <&xbar_mixer_in5_ep>; 1129 }; 1130 }; 1131 1132 port@5 { 1133 reg = <0x5>; 1134 1135 mixer_in6_ep: endpoint { 1136 remote-endpoint = <&xbar_mixer_in6_ep>; 1137 }; 1138 }; 1139 1140 port@6 { 1141 reg = <0x6>; 1142 1143 mixer_in7_ep: endpoint { 1144 remote-endpoint = <&xbar_mixer_in7_ep>; 1145 }; 1146 }; 1147 1148 port@7 { 1149 reg = <0x7>; 1150 1151 mixer_in8_ep: endpoint { 1152 remote-endpoint = <&xbar_mixer_in8_ep>; 1153 }; 1154 }; 1155 1156 port@8 { 1157 reg = <0x8>; 1158 1159 mixer_in9_ep: endpoint { 1160 remote-endpoint = <&xbar_mixer_in9_ep>; 1161 }; 1162 }; 1163 1164 port@9 { 1165 reg = <0x9>; 1166 1167 mixer_in10_ep: endpoint { 1168 remote-endpoint = <&xbar_mixer_in10_ep>; 1169 }; 1170 }; 1171 1172 mixer_out1_port: port@a { 1173 reg = <0xa>; 1174 1175 mixer_out1_ep: endpoint { 1176 remote-endpoint = <&xbar_mixer_out1_ep>; 1177 }; 1178 }; 1179 1180 mixer_out2_port: port@b { 1181 reg = <0xb>; 1182 1183 mixer_out2_ep: endpoint { 1184 remote-endpoint = <&xbar_mixer_out2_ep>; 1185 }; 1186 }; 1187 1188 mixer_out3_port: port@c { 1189 reg = <0xc>; 1190 1191 mixer_out3_ep: endpoint { 1192 remote-endpoint = <&xbar_mixer_out3_ep>; 1193 }; 1194 }; 1195 1196 mixer_out4_port: port@d { 1197 reg = <0xd>; 1198 1199 mixer_out4_ep: endpoint { 1200 remote-endpoint = <&xbar_mixer_out4_ep>; 1201 }; 1202 }; 1203 1204 mixer_out5_port: port@e { 1205 reg = <0xe>; 1206 1207 mixer_out5_ep: endpoint { 1208 remote-endpoint = <&xbar_mixer_out5_ep>; 1209 }; 1210 }; 1211 }; 1212 }; 1213 1214 ports { 1215 xbar_i2s3_port: port@c { 1216 reg = <0xc>; 1217 1218 xbar_i2s3_ep: endpoint { 1219 remote-endpoint = <&i2s3_cif_ep>; 1220 }; 1221 }; 1222 1223 xbar_i2s4_port: port@d { 1224 reg = <0xd>; 1225 1226 xbar_i2s4_ep: endpoint { 1227 remote-endpoint = <&i2s4_cif_ep>; 1228 }; 1229 }; 1230 1231 xbar_dmic1_port: port@f { 1232 reg = <0xf>; 1233 1234 xbar_dmic1_ep: endpoint { 1235 remote-endpoint = <&dmic1_cif_ep>; 1236 }; 1237 }; 1238 1239 xbar_dmic2_port: port@10 { 1240 reg = <0x10>; 1241 1242 xbar_dmic2_ep: endpoint { 1243 remote-endpoint = <&dmic2_cif_ep>; 1244 }; 1245 }; 1246 1247 xbar_sfc1_in_port: port@12 { 1248 reg = <0x12>; 1249 1250 xbar_sfc1_in_ep: endpoint { 1251 remote-endpoint = <&sfc1_cif_in_ep>; 1252 }; 1253 }; 1254 1255 port@13 { 1256 reg = <0x13>; 1257 1258 xbar_sfc1_out_ep: endpoint { 1259 remote-endpoint = <&sfc1_cif_out_ep>; 1260 }; 1261 }; 1262 1263 xbar_sfc2_in_port: port@14 { 1264 reg = <0x14>; 1265 1266 xbar_sfc2_in_ep: endpoint { 1267 remote-endpoint = <&sfc2_cif_in_ep>; 1268 }; 1269 }; 1270 1271 port@15 { 1272 reg = <0x15>; 1273 1274 xbar_sfc2_out_ep: endpoint { 1275 remote-endpoint = <&sfc2_cif_out_ep>; 1276 }; 1277 }; 1278 1279 xbar_sfc3_in_port: port@16 { 1280 reg = <0x16>; 1281 1282 xbar_sfc3_in_ep: endpoint { 1283 remote-endpoint = <&sfc3_cif_in_ep>; 1284 }; 1285 }; 1286 1287 port@17 { 1288 reg = <0x17>; 1289 1290 xbar_sfc3_out_ep: endpoint { 1291 remote-endpoint = <&sfc3_cif_out_ep>; 1292 }; 1293 }; 1294 1295 xbar_sfc4_in_port: port@18 { 1296 reg = <0x18>; 1297 1298 xbar_sfc4_in_ep: endpoint { 1299 remote-endpoint = <&sfc4_cif_in_ep>; 1300 }; 1301 }; 1302 1303 port@19 { 1304 reg = <0x19>; 1305 1306 xbar_sfc4_out_ep: endpoint { 1307 remote-endpoint = <&sfc4_cif_out_ep>; 1308 }; 1309 }; 1310 1311 xbar_mvc1_in_port: port@1a { 1312 reg = <0x1a>; 1313 1314 xbar_mvc1_in_ep: endpoint { 1315 remote-endpoint = <&mvc1_cif_in_ep>; 1316 }; 1317 }; 1318 1319 port@1b { 1320 reg = <0x1b>; 1321 1322 xbar_mvc1_out_ep: endpoint { 1323 remote-endpoint = <&mvc1_cif_out_ep>; 1324 }; 1325 }; 1326 1327 xbar_mvc2_in_port: port@1c { 1328 reg = <0x1c>; 1329 1330 xbar_mvc2_in_ep: endpoint { 1331 remote-endpoint = <&mvc2_cif_in_ep>; 1332 }; 1333 }; 1334 1335 port@1d { 1336 reg = <0x1d>; 1337 1338 xbar_mvc2_out_ep: endpoint { 1339 remote-endpoint = <&mvc2_cif_out_ep>; 1340 }; 1341 }; 1342 1343 xbar_amx1_in1_port: port@1e { 1344 reg = <0x1e>; 1345 1346 xbar_amx1_in1_ep: endpoint { 1347 remote-endpoint = <&amx1_in1_ep>; 1348 }; 1349 }; 1350 1351 xbar_amx1_in2_port: port@1f { 1352 reg = <0x1f>; 1353 1354 xbar_amx1_in2_ep: endpoint { 1355 remote-endpoint = <&amx1_in2_ep>; 1356 }; 1357 }; 1358 1359 xbar_amx1_in3_port: port@20 { 1360 reg = <0x20>; 1361 1362 xbar_amx1_in3_ep: endpoint { 1363 remote-endpoint = <&amx1_in3_ep>; 1364 }; 1365 }; 1366 1367 xbar_amx1_in4_port: port@21 { 1368 reg = <0x21>; 1369 1370 xbar_amx1_in4_ep: endpoint { 1371 remote-endpoint = <&amx1_in4_ep>; 1372 }; 1373 }; 1374 1375 port@22 { 1376 reg = <0x22>; 1377 1378 xbar_amx1_out_ep: endpoint { 1379 remote-endpoint = <&amx1_out_ep>; 1380 }; 1381 }; 1382 1383 xbar_amx2_in1_port: port@23 { 1384 reg = <0x23>; 1385 1386 xbar_amx2_in1_ep: endpoint { 1387 remote-endpoint = <&amx2_in1_ep>; 1388 }; 1389 }; 1390 1391 xbar_amx2_in2_port: port@24 { 1392 reg = <0x24>; 1393 1394 xbar_amx2_in2_ep: endpoint { 1395 remote-endpoint = <&amx2_in2_ep>; 1396 }; 1397 }; 1398 1399 xbar_amx2_in3_port: port@25 { 1400 reg = <0x25>; 1401 1402 xbar_amx2_in3_ep: endpoint { 1403 remote-endpoint = <&amx2_in3_ep>; 1404 }; 1405 }; 1406 1407 xbar_amx2_in4_port: port@26 { 1408 reg = <0x26>; 1409 1410 xbar_amx2_in4_ep: endpoint { 1411 remote-endpoint = <&amx2_in4_ep>; 1412 }; 1413 }; 1414 1415 port@27 { 1416 reg = <0x27>; 1417 1418 xbar_amx2_out_ep: endpoint { 1419 remote-endpoint = <&amx2_out_ep>; 1420 }; 1421 }; 1422 1423 xbar_adx1_in_port: port@28 { 1424 reg = <0x28>; 1425 1426 xbar_adx1_in_ep: endpoint { 1427 remote-endpoint = <&adx1_in_ep>; 1428 }; 1429 }; 1430 1431 port@29 { 1432 reg = <0x29>; 1433 1434 xbar_adx1_out1_ep: endpoint { 1435 remote-endpoint = <&adx1_out1_ep>; 1436 }; 1437 }; 1438 1439 port@2a { 1440 reg = <0x2a>; 1441 1442 xbar_adx1_out2_ep: endpoint { 1443 remote-endpoint = <&adx1_out2_ep>; 1444 }; 1445 }; 1446 1447 port@2b { 1448 reg = <0x2b>; 1449 1450 xbar_adx1_out3_ep: endpoint { 1451 remote-endpoint = <&adx1_out3_ep>; 1452 }; 1453 }; 1454 1455 port@2c { 1456 reg = <0x2c>; 1457 1458 xbar_adx1_out4_ep: endpoint { 1459 remote-endpoint = <&adx1_out4_ep>; 1460 }; 1461 }; 1462 1463 xbar_adx2_in_port: port@2d { 1464 reg = <0x2d>; 1465 1466 xbar_adx2_in_ep: endpoint { 1467 remote-endpoint = <&adx2_in_ep>; 1468 }; 1469 }; 1470 1471 port@2e { 1472 reg = <0x2e>; 1473 1474 xbar_adx2_out1_ep: endpoint { 1475 remote-endpoint = <&adx2_out1_ep>; 1476 }; 1477 }; 1478 1479 port@2f { 1480 reg = <0x2f>; 1481 1482 xbar_adx2_out2_ep: endpoint { 1483 remote-endpoint = <&adx2_out2_ep>; 1484 }; 1485 }; 1486 1487 port@30 { 1488 reg = <0x30>; 1489 1490 xbar_adx2_out3_ep: endpoint { 1491 remote-endpoint = <&adx2_out3_ep>; 1492 }; 1493 }; 1494 1495 port@31 { 1496 reg = <0x31>; 1497 1498 xbar_adx2_out4_ep: endpoint { 1499 remote-endpoint = <&adx2_out4_ep>; 1500 }; 1501 }; 1502 1503 xbar_mixer_in1_port: port@32 { 1504 reg = <0x32>; 1505 1506 xbar_mixer_in1_ep: endpoint { 1507 remote-endpoint = <&mixer_in1_ep>; 1508 }; 1509 }; 1510 1511 xbar_mixer_in2_port: port@33 { 1512 reg = <0x33>; 1513 1514 xbar_mixer_in2_ep: endpoint { 1515 remote-endpoint = <&mixer_in2_ep>; 1516 }; 1517 }; 1518 1519 xbar_mixer_in3_port: port@34 { 1520 reg = <0x34>; 1521 1522 xbar_mixer_in3_ep: endpoint { 1523 remote-endpoint = <&mixer_in3_ep>; 1524 }; 1525 }; 1526 1527 xbar_mixer_in4_port: port@35 { 1528 reg = <0x35>; 1529 1530 xbar_mixer_in4_ep: endpoint { 1531 remote-endpoint = <&mixer_in4_ep>; 1532 }; 1533 }; 1534 1535 xbar_mixer_in5_port: port@36 { 1536 reg = <0x36>; 1537 1538 xbar_mixer_in5_ep: endpoint { 1539 remote-endpoint = <&mixer_in5_ep>; 1540 }; 1541 }; 1542 1543 xbar_mixer_in6_port: port@37 { 1544 reg = <0x37>; 1545 1546 xbar_mixer_in6_ep: endpoint { 1547 remote-endpoint = <&mixer_in6_ep>; 1548 }; 1549 }; 1550 1551 xbar_mixer_in7_port: port@38 { 1552 reg = <0x38>; 1553 1554 xbar_mixer_in7_ep: endpoint { 1555 remote-endpoint = <&mixer_in7_ep>; 1556 }; 1557 }; 1558 1559 xbar_mixer_in8_port: port@39 { 1560 reg = <0x39>; 1561 1562 xbar_mixer_in8_ep: endpoint { 1563 remote-endpoint = <&mixer_in8_ep>; 1564 }; 1565 }; 1566 1567 xbar_mixer_in9_port: port@3a { 1568 reg = <0x3a>; 1569 1570 xbar_mixer_in9_ep: endpoint { 1571 remote-endpoint = <&mixer_in9_ep>; 1572 }; 1573 }; 1574 1575 xbar_mixer_in10_port: port@3b { 1576 reg = <0x3b>; 1577 1578 xbar_mixer_in10_ep: endpoint { 1579 remote-endpoint = <&mixer_in10_ep>; 1580 }; 1581 }; 1582 1583 port@3c { 1584 reg = <0x3c>; 1585 1586 xbar_mixer_out1_ep: endpoint { 1587 remote-endpoint = <&mixer_out1_ep>; 1588 }; 1589 }; 1590 1591 port@3d { 1592 reg = <0x3d>; 1593 1594 xbar_mixer_out2_ep: endpoint { 1595 remote-endpoint = <&mixer_out2_ep>; 1596 }; 1597 }; 1598 1599 port@3e { 1600 reg = <0x3e>; 1601 1602 xbar_mixer_out3_ep: endpoint { 1603 remote-endpoint = <&mixer_out3_ep>; 1604 }; 1605 }; 1606 1607 port@3f { 1608 reg = <0x3f>; 1609 1610 xbar_mixer_out4_ep: endpoint { 1611 remote-endpoint = <&mixer_out4_ep>; 1612 }; 1613 }; 1614 1615 port@40 { 1616 reg = <0x40>; 1617 1618 xbar_mixer_out5_ep: endpoint { 1619 remote-endpoint = <&mixer_out5_ep>; 1620 }; 1621 }; 1622 }; 1623 }; 1624 }; 1625 1626 spi@70410000 { 1627 status = "okay"; 1628 1629 flash@0 { 1630 compatible = "jedec,spi-nor"; 1631 reg = <0>; 1632 spi-max-frequency = <104000000>; 1633 spi-tx-bus-width = <2>; 1634 spi-rx-bus-width = <2>; 1635 }; 1636 }; 1637 1638 clk32k_in: clock-32k { 1639 compatible = "fixed-clock"; 1640 clock-frequency = <32768>; 1641 #clock-cells = <0>; 1642 }; 1643 1644 cpus { 1645 cpu@0 { 1646 enable-method = "psci"; 1647 }; 1648 1649 cpu@1 { 1650 enable-method = "psci"; 1651 }; 1652 1653 cpu@2 { 1654 enable-method = "psci"; 1655 }; 1656 1657 cpu@3 { 1658 enable-method = "psci"; 1659 }; 1660 1661 idle-states { 1662 cpu-sleep { 1663 status = "okay"; 1664 }; 1665 }; 1666 }; 1667 1668 fan: fan { 1669 compatible = "pwm-fan"; 1670 pwms = <&pwm 3 45334>; 1671 1672 cooling-levels = <0 64 128 255>; 1673 #cooling-cells = <2>; 1674 }; 1675 1676 thermal-zones { 1677 cpu-thermal { 1678 trips { 1679 cpu_trip_critical: critical { 1680 temperature = <96500>; 1681 hysteresis = <0>; 1682 type = "critical"; 1683 }; 1684 1685 cpu_trip_hot: hot { 1686 temperature = <70000>; 1687 hysteresis = <2000>; 1688 type = "hot"; 1689 }; 1690 1691 cpu_trip_active: active { 1692 temperature = <50000>; 1693 hysteresis = <2000>; 1694 type = "active"; 1695 }; 1696 1697 cpu_trip_passive: passive { 1698 temperature = <30000>; 1699 hysteresis = <2000>; 1700 type = "passive"; 1701 }; 1702 }; 1703 1704 cooling-maps { 1705 cpu-critical { 1706 cooling-device = <&fan 3 3>; 1707 trip = <&cpu_trip_critical>; 1708 }; 1709 1710 cpu-hot { 1711 cooling-device = <&fan 2 2>; 1712 trip = <&cpu_trip_hot>; 1713 }; 1714 1715 cpu-active { 1716 cooling-device = <&fan 1 1>; 1717 trip = <&cpu_trip_active>; 1718 }; 1719 1720 cpu-passive { 1721 cooling-device = <&fan 0 0>; 1722 trip = <&cpu_trip_passive>; 1723 }; 1724 }; 1725 }; 1726 }; 1727 1728 gpio-keys { 1729 compatible = "gpio-keys"; 1730 1731 power { 1732 label = "Power"; 1733 gpios = <&gpio TEGRA_GPIO(X, 5) GPIO_ACTIVE_LOW>; 1734 linux,input-type = <EV_KEY>; 1735 linux,code = <KEY_POWER>; 1736 debounce-interval = <30>; 1737 wakeup-event-action = <EV_ACT_ASSERTED>; 1738 wakeup-source; 1739 }; 1740 1741 force-recovery { 1742 label = "Force Recovery"; 1743 gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>; 1744 linux,input-type = <EV_KEY>; 1745 linux,code = <BTN_1>; 1746 debounce-interval = <30>; 1747 }; 1748 }; 1749 1750 psci { 1751 compatible = "arm,psci-1.0"; 1752 method = "smc"; 1753 }; 1754 1755 vdd_5v0_sys: regulator-vdd-5v0-sys { 1756 compatible = "regulator-fixed"; 1757 1758 regulator-name = "VDD_5V0_SYS"; 1759 regulator-min-microvolt = <5000000>; 1760 regulator-max-microvolt = <5000000>; 1761 regulator-always-on; 1762 regulator-boot-on; 1763 }; 1764 1765 vdd_3v3_sys: regulator-vdd-3v3-sys { 1766 compatible = "regulator-fixed"; 1767 1768 regulator-name = "VDD_3V3_SYS"; 1769 regulator-min-microvolt = <3300000>; 1770 regulator-max-microvolt = <3300000>; 1771 regulator-enable-ramp-delay = <240>; 1772 regulator-always-on; 1773 regulator-boot-on; 1774 1775 gpio = <&pmic 3 GPIO_ACTIVE_HIGH>; 1776 enable-active-high; 1777 1778 vin-supply = <&vdd_5v0_sys>; 1779 }; 1780 1781 vdd_3v3_sd: regulator-vdd-3v3-sd { 1782 compatible = "regulator-fixed"; 1783 1784 regulator-name = "VDD_3V3_SD"; 1785 regulator-min-microvolt = <3300000>; 1786 regulator-max-microvolt = <3300000>; 1787 1788 gpio = <&gpio TEGRA_GPIO(Z, 3) GPIO_ACTIVE_HIGH>; 1789 enable-active-high; 1790 1791 vin-supply = <&vdd_3v3_sys>; 1792 }; 1793 1794 vdd_hdmi: regulator-vdd-hdmi-5v0 { 1795 compatible = "regulator-fixed"; 1796 1797 regulator-name = "VDD_HDMI_5V0"; 1798 regulator-min-microvolt = <5000000>; 1799 regulator-max-microvolt = <5000000>; 1800 1801 vin-supply = <&vdd_5v0_sys>; 1802 }; 1803 1804 vdd_hub_3v3: regulator-vdd-hub-3v3 { 1805 compatible = "regulator-fixed"; 1806 1807 regulator-name = "VDD_HUB_3V3"; 1808 regulator-min-microvolt = <3300000>; 1809 regulator-max-microvolt = <3300000>; 1810 1811 gpio = <&gpio TEGRA_GPIO(A, 6) GPIO_ACTIVE_HIGH>; 1812 enable-active-high; 1813 1814 vin-supply = <&vdd_5v0_sys>; 1815 }; 1816 1817 vdd_cpu: regulator-vdd-cpu { 1818 compatible = "regulator-fixed"; 1819 1820 regulator-name = "VDD_CPU"; 1821 regulator-min-microvolt = <5000000>; 1822 regulator-max-microvolt = <5000000>; 1823 regulator-always-on; 1824 regulator-boot-on; 1825 1826 gpio = <&pmic 5 GPIO_ACTIVE_HIGH>; 1827 enable-active-high; 1828 1829 vin-supply = <&vdd_5v0_sys>; 1830 }; 1831 1832 vdd_gpu: regulator-vdd-gpu { 1833 compatible = "pwm-regulator"; 1834 pwms = <&pwm 1 8000>; 1835 1836 regulator-name = "VDD_GPU"; 1837 regulator-min-microvolt = <710000>; 1838 regulator-max-microvolt = <1320000>; 1839 regulator-ramp-delay = <80>; 1840 regulator-enable-ramp-delay = <2000>; 1841 regulator-settling-time-us = <160>; 1842 1843 enable-gpios = <&pmic 6 GPIO_ACTIVE_HIGH>; 1844 vin-supply = <&vdd_5v0_sys>; 1845 }; 1846 1847 avdd_io_edp_1v05: regulator-avdd-io-epd-1v05 { 1848 compatible = "regulator-fixed"; 1849 1850 regulator-name = "AVDD_IO_EDP_1V05"; 1851 regulator-min-microvolt = <1050000>; 1852 regulator-max-microvolt = <1050000>; 1853 1854 gpio = <&pmic 7 GPIO_ACTIVE_HIGH>; 1855 enable-active-high; 1856 1857 vin-supply = <&avdd_1v05_pll>; 1858 }; 1859 1860 vdd_5v0_usb: regulator-vdd-5v-usb { 1861 compatible = "regulator-fixed"; 1862 1863 regulator-name = "VDD_5V_USB"; 1864 regulator-min-microvolt = <50000000>; 1865 regulator-max-microvolt = <50000000>; 1866 1867 vin-supply = <&vdd_5v0_sys>; 1868 }; 1869 1870 sound { 1871 compatible = "nvidia,tegra210-audio-graph-card"; 1872 status = "okay"; 1873 1874 dais = /* FE */ 1875 <&admaif1_port>, <&admaif2_port>, <&admaif3_port>, 1876 <&admaif4_port>, <&admaif5_port>, <&admaif6_port>, 1877 <&admaif7_port>, <&admaif8_port>, <&admaif9_port>, 1878 <&admaif10_port>, 1879 /* Router */ 1880 <&xbar_i2s3_port>, <&xbar_i2s4_port>, 1881 <&xbar_dmic1_port>, <&xbar_dmic2_port>, 1882 <&xbar_sfc1_in_port>, <&xbar_sfc2_in_port>, 1883 <&xbar_sfc3_in_port>, <&xbar_sfc4_in_port>, 1884 <&xbar_mvc1_in_port>, <&xbar_mvc2_in_port>, 1885 <&xbar_amx1_in1_port>, <&xbar_amx1_in2_port>, 1886 <&xbar_amx1_in3_port>, <&xbar_amx1_in4_port>, 1887 <&xbar_amx2_in1_port>, <&xbar_amx2_in2_port>, 1888 <&xbar_amx2_in3_port>, <&xbar_amx2_in4_port>, 1889 <&xbar_adx1_in_port>, <&xbar_adx2_in_port>, 1890 <&xbar_mixer_in1_port>, <&xbar_mixer_in2_port>, 1891 <&xbar_mixer_in3_port>, <&xbar_mixer_in4_port>, 1892 <&xbar_mixer_in5_port>, <&xbar_mixer_in6_port>, 1893 <&xbar_mixer_in7_port>, <&xbar_mixer_in8_port>, 1894 <&xbar_mixer_in9_port>, <&xbar_mixer_in10_port>, 1895 /* HW accelerators */ 1896 <&sfc1_out_port>, <&sfc2_out_port>, 1897 <&sfc3_out_port>, <&sfc4_out_port>, 1898 <&mvc1_out_port>, <&mvc2_out_port>, 1899 <&amx1_out_port>, <&amx2_out_port>, 1900 <&adx1_out1_port>, <&adx1_out2_port>, 1901 <&adx1_out3_port>, <&adx1_out4_port>, 1902 <&adx2_out1_port>, <&adx2_out2_port>, 1903 <&adx2_out3_port>, <&adx2_out4_port>, 1904 <&mixer_out1_port>, <&mixer_out2_port>, 1905 <&mixer_out3_port>, <&mixer_out4_port>, 1906 <&mixer_out5_port>, 1907 /* I/O DAP Ports */ 1908 <&i2s3_port>, <&i2s4_port>, 1909 <&dmic1_port>, <&dmic2_port>; 1910 1911 label = "NVIDIA Jetson Nano APE"; 1912 }; 1913}; 1914