1c552cca3SThierry Reding#include "tegra210.dtsi" 2c552cca3SThierry Reding 3c552cca3SThierry Reding/ { 4c552cca3SThierry Reding model = "NVIDIA Tegra210 P2530 main board"; 5c552cca3SThierry Reding compatible = "nvidia,p2530", "nvidia,tegra210"; 6c552cca3SThierry Reding 7c552cca3SThierry Reding aliases { 8be70771dSThierry Reding rtc1 = "/rtc@7000e000"; 9c552cca3SThierry Reding serial0 = &uarta; 10c552cca3SThierry Reding }; 11c552cca3SThierry Reding 12c552cca3SThierry Reding memory { 13c552cca3SThierry Reding device_type = "memory"; 14c552cca3SThierry Reding reg = <0x0 0x80000000 0x0 0xc0000000>; 15c552cca3SThierry Reding }; 16c552cca3SThierry Reding 17c552cca3SThierry Reding /* debug port */ 18be70771dSThierry Reding serial@70006000 { 19c552cca3SThierry Reding status = "okay"; 20c552cca3SThierry Reding }; 21c552cca3SThierry Reding 22be70771dSThierry Reding i2c@7000d000 { 23c552cca3SThierry Reding status = "okay"; 24c552cca3SThierry Reding clock-frequency = <400000>; 25c552cca3SThierry Reding }; 26c552cca3SThierry Reding 27be70771dSThierry Reding pmc@7000e400 { 28c552cca3SThierry Reding nvidia,invert-interrupt; 29c552cca3SThierry Reding }; 30c552cca3SThierry Reding 31c552cca3SThierry Reding /* eMMC */ 32be70771dSThierry Reding sdhci@700b0600 { 33c552cca3SThierry Reding status = "okay"; 34c552cca3SThierry Reding bus-width = <8>; 35c552cca3SThierry Reding non-removable; 36c552cca3SThierry Reding }; 37c552cca3SThierry Reding 38c552cca3SThierry Reding clocks { 39c552cca3SThierry Reding compatible = "simple-bus"; 40c552cca3SThierry Reding #address-cells = <1>; 41c552cca3SThierry Reding #size-cells = <0>; 42c552cca3SThierry Reding 43c552cca3SThierry Reding clk32k_in: clock@0 { 44c552cca3SThierry Reding compatible = "fixed-clock"; 45c552cca3SThierry Reding reg = <0>; 46c552cca3SThierry Reding #clock-cells = <0>; 47c552cca3SThierry Reding clock-frequency = <32768>; 48c552cca3SThierry Reding }; 49c552cca3SThierry Reding }; 50c552cca3SThierry Reding}; 51