1// SPDX-License-Identifier: GPL-2.0
2
3#include <dt-bindings/input/linux-event-codes.h>
4#include <dt-bindings/input/gpio-keys.h>
5
6/ {
7	bus@0 {
8		aconnect@2900000 {
9			status = "okay";
10
11			dma-controller@2930000 {
12				status = "okay";
13			};
14
15			interrupt-controller@2a40000 {
16				status = "okay";
17			};
18
19			ahub@2900800 {
20				status = "okay";
21
22				ports {
23					#address-cells = <1>;
24					#size-cells = <0>;
25
26					port@0 {
27						reg = <0x0>;
28
29						xbar_admaif0_ep: endpoint {
30							remote-endpoint = <&admaif0_ep>;
31						};
32					};
33
34					port@1 {
35						reg = <0x1>;
36
37						xbar_admaif1_ep: endpoint {
38							remote-endpoint = <&admaif1_ep>;
39						};
40					};
41
42					port@2 {
43						reg = <0x2>;
44
45						xbar_admaif2_ep: endpoint {
46							remote-endpoint = <&admaif2_ep>;
47						};
48					};
49
50					port@3 {
51						reg = <0x3>;
52
53						xbar_admaif3_ep: endpoint {
54							remote-endpoint = <&admaif3_ep>;
55						};
56					};
57
58					port@4 {
59						reg = <0x4>;
60
61						xbar_admaif4_ep: endpoint {
62							remote-endpoint = <&admaif4_ep>;
63						};
64					};
65
66					port@5 {
67						reg = <0x5>;
68
69						xbar_admaif5_ep: endpoint {
70							remote-endpoint = <&admaif5_ep>;
71						};
72					};
73
74					port@6 {
75						reg = <0x6>;
76
77						xbar_admaif6_ep: endpoint {
78							remote-endpoint = <&admaif6_ep>;
79						};
80					};
81
82					port@7 {
83						reg = <0x7>;
84
85						xbar_admaif7_ep: endpoint {
86							remote-endpoint = <&admaif7_ep>;
87						};
88					};
89
90					port@8 {
91						reg = <0x8>;
92
93						xbar_admaif8_ep: endpoint {
94							remote-endpoint = <&admaif8_ep>;
95						};
96					};
97
98					port@9 {
99						reg = <0x9>;
100
101						xbar_admaif9_ep: endpoint {
102							remote-endpoint = <&admaif9_ep>;
103						};
104					};
105
106					port@a {
107						reg = <0xa>;
108
109						xbar_admaif10_ep: endpoint {
110							remote-endpoint = <&admaif10_ep>;
111						};
112					};
113
114					port@b {
115						reg = <0xb>;
116
117						xbar_admaif11_ep: endpoint {
118							remote-endpoint = <&admaif11_ep>;
119						};
120					};
121
122					port@c {
123						reg = <0xc>;
124
125						xbar_admaif12_ep: endpoint {
126							remote-endpoint = <&admaif12_ep>;
127						};
128					};
129
130					port@d {
131						reg = <0xd>;
132
133						xbar_admaif13_ep: endpoint {
134							remote-endpoint = <&admaif13_ep>;
135						};
136					};
137
138					port@e {
139						reg = <0xe>;
140
141						xbar_admaif14_ep: endpoint {
142							remote-endpoint = <&admaif14_ep>;
143						};
144					};
145
146					port@f {
147						reg = <0xf>;
148
149						xbar_admaif15_ep: endpoint {
150							remote-endpoint = <&admaif15_ep>;
151						};
152					};
153
154					port@10 {
155						reg = <0x10>;
156
157						xbar_admaif16_ep: endpoint {
158							remote-endpoint = <&admaif16_ep>;
159						};
160					};
161
162					port@11 {
163						reg = <0x11>;
164
165						xbar_admaif17_ep: endpoint {
166							remote-endpoint = <&admaif17_ep>;
167						};
168					};
169
170					port@12 {
171						reg = <0x12>;
172
173						xbar_admaif18_ep: endpoint {
174							remote-endpoint = <&admaif18_ep>;
175						};
176					};
177
178					port@13 {
179						reg = <0x13>;
180
181						xbar_admaif19_ep: endpoint {
182							remote-endpoint = <&admaif19_ep>;
183						};
184					};
185
186					xbar_i2s3_port: port@16 {
187						reg = <0x16>;
188
189						xbar_i2s3_ep: endpoint {
190							remote-endpoint = <&i2s3_cif_ep>;
191						};
192					};
193
194					xbar_i2s5_port: port@18 {
195						reg = <0x18>;
196
197						xbar_i2s5_ep: endpoint {
198							remote-endpoint = <&i2s5_cif_ep>;
199						};
200					};
201
202					xbar_dmic1_port: port@1a {
203						reg = <0x1a>;
204
205						xbar_dmic1_ep: endpoint {
206							remote-endpoint = <&dmic1_cif_ep>;
207						};
208					};
209
210					xbar_dmic2_port: port@1b {
211						reg = <0x1b>;
212
213						xbar_dmic2_ep: endpoint {
214							remote-endpoint = <&dmic2_cif_ep>;
215						};
216					};
217
218					xbar_dmic4_port: port@1d {
219						reg = <0x1d>;
220
221						xbar_dmic4_ep: endpoint {
222							remote-endpoint = <&dmic4_cif_ep>;
223						};
224					};
225
226					xbar_dspk1_port: port@1e {
227						reg = <0x1e>;
228
229						xbar_dspk1_ep: endpoint {
230							remote-endpoint = <&dspk1_cif_ep>;
231						};
232					};
233
234					xbar_dspk2_port: port@1f {
235						reg = <0x1f>;
236
237						xbar_dspk2_ep: endpoint {
238							remote-endpoint = <&dspk2_cif_ep>;
239						};
240					};
241				};
242
243				admaif@290f000 {
244					status = "okay";
245
246					ports {
247						#address-cells = <1>;
248						#size-cells = <0>;
249
250						admaif0_port: port@0 {
251							reg = <0x0>;
252
253							admaif0_ep: endpoint {
254								remote-endpoint = <&xbar_admaif0_ep>;
255							};
256						};
257
258						admaif1_port: port@1 {
259							reg = <0x1>;
260
261							admaif1_ep: endpoint {
262								remote-endpoint = <&xbar_admaif1_ep>;
263							};
264						};
265
266						admaif2_port: port@2 {
267							reg = <0x2>;
268
269							admaif2_ep: endpoint {
270								remote-endpoint = <&xbar_admaif2_ep>;
271							};
272						};
273
274						admaif3_port: port@3 {
275							reg = <0x3>;
276
277							admaif3_ep: endpoint {
278								remote-endpoint = <&xbar_admaif3_ep>;
279							};
280						};
281
282						admaif4_port: port@4 {
283							reg = <0x4>;
284
285							admaif4_ep: endpoint {
286								remote-endpoint = <&xbar_admaif4_ep>;
287							};
288						};
289
290						admaif5_port: port@5 {
291							reg = <0x5>;
292
293							admaif5_ep: endpoint {
294								remote-endpoint = <&xbar_admaif5_ep>;
295							};
296						};
297
298						admaif6_port: port@6 {
299							reg = <0x6>;
300
301							admaif6_ep: endpoint {
302								remote-endpoint = <&xbar_admaif6_ep>;
303							};
304						};
305
306						admaif7_port: port@7 {
307							reg = <0x7>;
308
309							admaif7_ep: endpoint {
310								remote-endpoint = <&xbar_admaif7_ep>;
311							};
312						};
313
314						admaif8_port: port@8 {
315							reg = <0x8>;
316
317							admaif8_ep: endpoint {
318								remote-endpoint = <&xbar_admaif8_ep>;
319							};
320						};
321
322						admaif9_port: port@9 {
323							reg = <0x9>;
324
325							admaif9_ep: endpoint {
326								remote-endpoint = <&xbar_admaif9_ep>;
327							};
328						};
329
330						admaif10_port: port@a {
331							reg = <0xa>;
332
333							admaif10_ep: endpoint {
334								remote-endpoint = <&xbar_admaif10_ep>;
335							};
336						};
337
338						admaif11_port: port@b {
339							reg = <0xb>;
340
341							admaif11_ep: endpoint {
342								remote-endpoint = <&xbar_admaif11_ep>;
343							};
344						};
345
346						admaif12_port: port@c {
347							reg = <0xc>;
348
349							admaif12_ep: endpoint {
350								remote-endpoint = <&xbar_admaif12_ep>;
351							};
352						};
353
354						admaif13_port: port@d {
355							reg = <0xd>;
356
357							admaif13_ep: endpoint {
358								remote-endpoint = <&xbar_admaif13_ep>;
359							};
360						};
361
362						admaif14_port: port@e {
363							reg = <0xe>;
364
365							admaif14_ep: endpoint {
366								remote-endpoint = <&xbar_admaif14_ep>;
367							};
368						};
369
370						admaif15_port: port@f {
371							reg = <0xf>;
372
373							admaif15_ep: endpoint {
374								remote-endpoint = <&xbar_admaif15_ep>;
375							};
376						};
377
378						admaif16_port: port@10 {
379							reg = <0x10>;
380
381							admaif16_ep: endpoint {
382								remote-endpoint = <&xbar_admaif16_ep>;
383							};
384						};
385
386						admaif17_port: port@11 {
387							reg = <0x11>;
388
389							admaif17_ep: endpoint {
390								remote-endpoint = <&xbar_admaif17_ep>;
391							};
392						};
393
394						admaif18_port: port@12 {
395							reg = <0x12>;
396
397							admaif18_ep: endpoint {
398								remote-endpoint = <&xbar_admaif18_ep>;
399							};
400						};
401
402						admaif19_port: port@13 {
403							reg = <0x13>;
404
405							admaif19_ep: endpoint {
406								remote-endpoint = <&xbar_admaif19_ep>;
407							};
408						};
409					};
410				};
411
412				i2s@2901200 {
413					status = "okay";
414
415					ports {
416						#address-cells = <1>;
417						#size-cells = <0>;
418
419						port@0 {
420							reg = <0>;
421
422							i2s3_cif_ep: endpoint {
423								remote-endpoint = <&xbar_i2s3_ep>;
424							};
425						};
426
427						i2s3_port: port@1 {
428							reg = <1>;
429
430							i2s3_dap_ep: endpoint {
431								dai-format = "i2s";
432								/* Place holder for external Codec */
433							};
434						};
435					};
436				};
437
438				i2s@2901400 {
439					status = "okay";
440
441					ports {
442						#address-cells = <1>;
443						#size-cells = <0>;
444
445						port@0 {
446							reg = <0>;
447
448							i2s5_cif_ep: endpoint {
449								remote-endpoint = <&xbar_i2s5_ep>;
450							};
451						};
452
453						i2s5_port: port@1 {
454							reg = <1>;
455
456							i2s5_dap_ep: endpoint@0 {
457								dai-format = "i2s";
458								/* Place holder for external Codec */
459							};
460						};
461					};
462				};
463
464				dmic@2904000 {
465					status = "okay";
466
467					ports {
468						#address-cells = <1>;
469						#size-cells = <0>;
470
471						port@0 {
472							reg = <0>;
473
474							dmic1_cif_ep: endpoint {
475								remote-endpoint = <&xbar_dmic1_ep>;
476							};
477						};
478
479						dmic1_port: port@1 {
480							reg = <1>;
481
482							dmic1_dap_ep: endpoint {
483								/* Place holder for external Codec */
484							};
485						};
486					};
487				};
488
489				dmic@2904100 {
490					status = "okay";
491
492					ports {
493						#address-cells = <1>;
494						#size-cells = <0>;
495
496						port@0 {
497							reg = <0>;
498
499							dmic2_cif_ep: endpoint {
500								remote-endpoint = <&xbar_dmic2_ep>;
501							};
502						};
503
504						dmic2_port: port@1 {
505							reg = <1>;
506
507							dmic2_dap_ep: endpoint {
508								/* Place holder for external Codec */
509							};
510						};
511					};
512				};
513
514				dmic@2904300 {
515					status = "okay";
516
517					ports {
518						#address-cells = <1>;
519						#size-cells = <0>;
520
521						port@0 {
522							reg = <0>;
523
524							dmic4_cif_ep: endpoint {
525								remote-endpoint = <&xbar_dmic4_ep>;
526							};
527						};
528
529						dmic4_port: port@1 {
530							reg = <1>;
531
532							dmic4_dap_ep: endpoint {
533								/* Place holder for external Codec */
534							};
535						};
536					};
537				};
538
539				dspk@2905000 {
540					status = "okay";
541
542					ports {
543						#address-cells = <1>;
544						#size-cells = <0>;
545
546						port@0 {
547							reg = <0>;
548
549							dspk1_cif_ep: endpoint {
550								remote-endpoint = <&xbar_dspk1_ep>;
551							};
552						};
553
554						dspk1_port: port@1 {
555							reg = <1>;
556
557							dspk1_dap_ep: endpoint {
558								/* Place holder for external Codec */
559							};
560						};
561					};
562				};
563
564				dspk@2905100 {
565					status = "okay";
566
567					ports {
568						#address-cells = <1>;
569						#size-cells = <0>;
570
571						port@0 {
572							reg = <0>;
573
574							dspk2_cif_ep: endpoint {
575								remote-endpoint = <&xbar_dspk2_ep>;
576							};
577						};
578
579						dspk2_port: port@1 {
580							reg = <1>;
581
582							dspk2_dap_ep: endpoint {
583								/* Place holder for external Codec */
584							};
585						};
586					};
587				};
588			};
589		};
590
591		ddc: i2c@3190000 {
592			status = "okay";
593		};
594
595		i2c@3160000 {
596			eeprom@57 {
597				compatible = "atmel,24c02";
598				reg = <0x57>;
599
600				label = "system";
601				vcc-supply = <&vdd_1v8>;
602				address-width = <8>;
603				pagesize = <8>;
604				size = <256>;
605				read-only;
606			};
607		};
608
609		hda@3510000 {
610			nvidia,model = "NVIDIA Jetson Xavier NX HDA";
611			status = "okay";
612		};
613
614		padctl@3520000 {
615			status = "okay";
616
617			pads {
618				usb2 {
619					lanes {
620						usb2-1 {
621							status = "okay";
622						};
623
624						usb2-2 {
625							status = "okay";
626						};
627					};
628				};
629
630				usb3 {
631					lanes {
632						usb3-2 {
633							status = "okay";
634						};
635					};
636				};
637			};
638
639			ports {
640				usb2-1 {
641					mode = "host";
642					status = "okay";
643				};
644
645				usb2-2 {
646					mode = "host";
647					vbus-supply = <&vdd_5v0_sys>;
648					status = "okay";
649				};
650
651				usb3-2 {
652					nvidia,usb2-companion = <1>;
653					vbus-supply = <&vdd_5v0_sys>;
654					status = "okay";
655				};
656			};
657		};
658
659		usb@3610000 {
660			status = "okay";
661
662			phys =	<&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-1}>,
663				<&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-2}>,
664				<&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-2}>;
665			phy-names = "usb2-1", "usb2-2", "usb3-2";
666		};
667
668		spi@3270000 {
669			status = "okay";
670
671			flash@0 {
672				compatible = "spi-nor";
673				reg = <0>;
674				spi-max-frequency = <102000000>;
675				spi-tx-bus-width = <4>;
676				spi-rx-bus-width = <4>;
677			};
678		};
679
680		pwm@32d0000 {
681			status = "okay";
682		};
683
684		host1x@13e00000 {
685			display-hub@15200000 {
686				status = "okay";
687			};
688
689			dpaux@155c0000 {
690				status = "okay";
691			};
692
693			dpaux@155d0000 {
694				status = "okay";
695			};
696
697			/* DP0 */
698			sor@15b00000 {
699				status = "okay";
700
701				avdd-io-hdmi-dp-supply = <&vdd_1v0>;
702				vdd-hdmi-dp-pll-supply = <&vdd_1v8hs>;
703
704				nvidia,dpaux = <&dpaux0>;
705			};
706
707			/* HDMI */
708			sor@15b40000 {
709				status = "okay";
710
711				avdd-io-hdmi-dp-supply = <&vdd_1v0>;
712				vdd-hdmi-dp-pll-supply = <&vdd_1v8hs>;
713				hdmi-supply = <&vdd_hdmi>;
714
715				nvidia,ddc-i2c-bus = <&ddc>;
716				nvidia,hpd-gpio = <&gpio TEGRA194_MAIN_GPIO(M, 1)
717							 GPIO_ACTIVE_LOW>;
718			};
719		};
720	};
721
722	pcie@14160000 {
723		status = "okay";
724
725		vddio-pex-ctl-supply = <&vdd_1v8ao>;
726
727		phys = <&p2u_hsio_11>;
728		phy-names = "p2u-0";
729	};
730
731	pcie@141a0000 {
732		status = "okay";
733
734		vddio-pex-ctl-supply = <&vdd_1v8ao>;
735
736		phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>,
737		       <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>,
738		       <&p2u_nvhs_6>, <&p2u_nvhs_7>;
739
740		phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",
741			    "p2u-5", "p2u-6", "p2u-7";
742	};
743
744	pcie_ep@141a0000 {
745		status = "disabled";
746
747		vddio-pex-ctl-supply = <&vdd_1v8ao>;
748
749		reset-gpios = <&gpio TEGRA194_MAIN_GPIO(GG, 1) GPIO_ACTIVE_LOW>;
750
751		nvidia,refclk-select-gpios = <&gpio_aon TEGRA194_AON_GPIO(AA, 5)
752					      GPIO_ACTIVE_HIGH>;
753
754		phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>,
755		       <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>,
756		       <&p2u_nvhs_6>, <&p2u_nvhs_7>;
757
758		phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",
759			    "p2u-5", "p2u-6", "p2u-7";
760	};
761
762	fan: fan {
763		compatible = "pwm-fan";
764		pwms = <&pwm6 0 45334>;
765
766		cooling-levels = <0 64 128 255>;
767		#cooling-cells = <2>;
768	};
769
770	gpio-keys {
771		compatible = "gpio-keys";
772
773		force-recovery {
774			label = "Force Recovery";
775			gpios = <&gpio TEGRA194_MAIN_GPIO(G, 0)
776				       GPIO_ACTIVE_LOW>;
777			linux,input-type = <EV_KEY>;
778			linux,code = <KEY_SLEEP>;
779			debounce-interval = <10>;
780		};
781
782		power {
783			label = "Power";
784			gpios = <&gpio_aon TEGRA194_AON_GPIO(EE, 4)
785					   GPIO_ACTIVE_LOW>;
786			linux,input-type = <EV_KEY>;
787			linux,code = <KEY_POWER>;
788			debounce-interval = <10>;
789			wakeup-event-action = <EV_ACT_ASSERTED>;
790			wakeup-source;
791		};
792	};
793
794	vdd_5v0_sys: regulator@100 {
795		compatible = "regulator-fixed";
796		regulator-name = "VDD_5V_SYS";
797		regulator-min-microvolt = <5000000>;
798		regulator-max-microvolt = <5000000>;
799		regulator-always-on;
800		regulator-boot-on;
801	};
802
803	vdd_3v3_sys: regulator@101 {
804		compatible = "regulator-fixed";
805		regulator-name = "VDD_3V3_SYS";
806		regulator-min-microvolt = <3300000>;
807		regulator-max-microvolt = <3300000>;
808		regulator-always-on;
809		regulator-boot-on;
810	};
811
812	vdd_3v3_ao: regulator@102 {
813		compatible = "regulator-fixed";
814		regulator-name = "VDD_3V3_AO";
815		regulator-min-microvolt = <3300000>;
816		regulator-max-microvolt = <3300000>;
817		regulator-always-on;
818		regulator-boot-on;
819	};
820
821	vdd_1v8: regulator@103 {
822		compatible = "regulator-fixed";
823		regulator-name = "VDD_1V8";
824		regulator-min-microvolt = <1800000>;
825		regulator-max-microvolt = <1800000>;
826		regulator-always-on;
827		regulator-boot-on;
828	};
829
830	vdd_hdmi: regulator@104 {
831		compatible = "regulator-fixed";
832		regulator-name = "VDD_5V0_HDMI_CON";
833		regulator-min-microvolt = <5000000>;
834		regulator-max-microvolt = <5000000>;
835		regulator-always-on;
836		regulator-boot-on;
837	};
838
839	sound {
840		compatible = "nvidia,tegra186-audio-graph-card";
841		status = "okay";
842
843		dais = /* ADMAIF (FE) Ports */
844		       <&admaif0_port>, <&admaif1_port>, <&admaif2_port>, <&admaif3_port>,
845		       <&admaif4_port>, <&admaif5_port>, <&admaif6_port>, <&admaif7_port>,
846		       <&admaif8_port>, <&admaif9_port>, <&admaif10_port>, <&admaif11_port>,
847		       <&admaif12_port>, <&admaif13_port>, <&admaif14_port>, <&admaif15_port>,
848		       <&admaif16_port>, <&admaif17_port>, <&admaif18_port>, <&admaif19_port>,
849		       /* XBAR Ports */
850		       <&xbar_i2s3_port>, <&xbar_i2s5_port>,
851		       <&xbar_dmic1_port>, <&xbar_dmic2_port>, <&xbar_dmic4_port>,
852		       <&xbar_dspk1_port>, <&xbar_dspk2_port>,
853		       /* BE I/O Ports */
854		       <&i2s3_port>, <&i2s5_port>,
855		       <&dmic1_port>, <&dmic2_port>, <&dmic4_port>,
856		       <&dspk1_port>, <&dspk2_port>;
857
858		label = "NVIDIA Jetson Xavier NX APE";
859	};
860
861	thermal-zones {
862		cpu {
863			polling-delay = <0>;
864			polling-delay-passive = <500>;
865			status = "okay";
866
867			trips {
868				cpu_trip_critical: critical {
869					temperature = <96500>;
870					hysteresis = <0>;
871					type = "critical";
872				};
873
874				cpu_trip_hot: hot {
875					temperature = <70000>;
876					hysteresis = <2000>;
877					type = "hot";
878				};
879
880				cpu_trip_active: active {
881					temperature = <50000>;
882					hysteresis = <2000>;
883					type = "active";
884				};
885
886				cpu_trip_passive: passive {
887					temperature = <30000>;
888					hysteresis = <2000>;
889					type = "passive";
890				};
891			};
892
893			cooling-maps {
894				cpu-critical {
895					cooling-device = <&fan 3 3>;
896					trip = <&cpu_trip_critical>;
897				};
898
899				cpu-hot {
900					cooling-device = <&fan 2 2>;
901					trip = <&cpu_trip_hot>;
902				};
903
904				cpu-active {
905					cooling-device = <&fan 1 1>;
906					trip = <&cpu_trip_active>;
907				};
908
909				cpu-passive {
910					cooling-device = <&fan 0 0>;
911					trip = <&cpu_trip_passive>;
912				};
913			};
914		};
915
916		gpu {
917			polling-delay = <0>;
918			polling-delay-passive = <500>;
919			status = "okay";
920
921			trips {
922				gpu_alert0: critical {
923					temperature = <99000>;
924					hysteresis = <0>;
925					type = "critical";
926				};
927			};
928		};
929
930		aux {
931			polling-delay = <0>;
932			polling-delay-passive = <500>;
933			status = "okay";
934
935			trips {
936				aux_alert0: critical {
937					temperature = <90000>;
938					hysteresis = <0>;
939					type = "critical";
940				};
941			};
942		};
943	};
944};
945