1/dts-v1/;
2
3#include <dt-bindings/input/linux-event-codes.h>
4
5#include "tegra186-p3310.dtsi"
6
7/ {
8	model = "NVIDIA Tegra186 P2771-0000 Development Board";
9	compatible = "nvidia,p2771-0000", "nvidia,tegra186";
10
11	i2c@3160000 {
12		power-monitor@42 {
13			compatible = "ti,ina3221";
14			reg = <0x42>;
15		};
16
17		power-monitor@43 {
18			compatible = "ti,ina3221";
19			reg = <0x43>;
20		};
21
22		exp1: gpio@74 {
23			compatible = "ti,tca9539";
24			reg = <0x74>;
25
26			interrupt-parent = <&gpio>;
27			interrupts = <TEGRA_MAIN_GPIO(Y, 0) GPIO_ACTIVE_LOW>;
28
29			#gpio-cells = <2>;
30			gpio-controller;
31		};
32
33		exp2: gpio@77 {
34			compatible = "ti,tca9539";
35			reg = <0x77>;
36
37			interrupt-parent = <&gpio>;
38			interrupts = <TEGRA_MAIN_GPIO(Y, 6) GPIO_ACTIVE_LOW>;
39
40			#gpio-cells = <2>;
41			gpio-controller;
42		};
43	};
44
45	/* SDMMC1 (SD/MMC) */
46	sdhci@3400000 {
47		status = "okay";
48
49		vmmc-supply = <&vdd_sd>;
50	};
51
52	gpio-keys {
53		compatible = "gpio-keys";
54
55		power {
56			label = "Power";
57			gpios = <&gpio_aon TEGRA_AON_GPIO(FF, 0)
58					   GPIO_ACTIVE_LOW>;
59			linux,input-type = <EV_KEY>;
60			linux,code = <KEY_POWER>;
61			debounce-interval = <10>;
62			wakeup-source;
63		};
64
65		volume-up {
66			label = "Volume Up";
67			gpios = <&gpio_aon TEGRA_AON_GPIO(FF, 1)
68					   GPIO_ACTIVE_LOW>;
69			linux,input-type = <EV_KEY>;
70			linux,code = <KEY_VOLUMEUP>;
71			debounce-interval = <10>;
72		};
73
74		volume-down {
75			label = "Volume Down";
76			gpios = <&gpio_aon TEGRA_AON_GPIO(FF, 2)
77					   GPIO_ACTIVE_LOW>;
78			linux,input-type = <EV_KEY>;
79			linux,code = <KEY_VOLUMEDOWN>;
80			debounce-interval = <10>;
81		};
82	};
83
84	regulators {
85		vdd_sd: regulator@100 {
86			compatible = "regulator-fixed";
87			reg = <100>;
88
89			regulator-name = "SD_CARD_SW_PWR";
90			regulator-min-microvolt = <3300000>;
91			regulator-max-microvolt = <3300000>;
92
93			gpio = <&gpio TEGRA_MAIN_GPIO(P, 6) GPIO_ACTIVE_HIGH>;
94			enable-active-high;
95
96			vin-supply = <&vdd_3v3_sys>;
97		};
98	};
99};
100