1#include <dt-bindings/clock/tegra124-car.h>
2#include <dt-bindings/gpio/tegra-gpio.h>
3#include <dt-bindings/memory/tegra124-mc.h>
4#include <dt-bindings/pinctrl/pinctrl-tegra.h>
5#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
6#include <dt-bindings/interrupt-controller/arm-gic.h>
7#include <dt-bindings/thermal/tegra124-soctherm.h>
8
9/ {
10	compatible = "nvidia,tegra132", "nvidia,tegra124";
11	interrupt-parent = <&lic>;
12	#address-cells = <2>;
13	#size-cells = <2>;
14
15	pcie-controller@01003000 {
16		compatible = "nvidia,tegra124-pcie";
17		device_type = "pci";
18		reg = <0x0 0x01003000 0x0 0x00000800   /* PADS registers */
19		       0x0 0x01003800 0x0 0x00000800   /* AFI registers */
20		       0x0 0x02000000 0x0 0x10000000>; /* configuration space */
21		reg-names = "pads", "afi", "cs";
22		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
23			     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
24		interrupt-names = "intr", "msi";
25
26		#interrupt-cells = <1>;
27		interrupt-map-mask = <0 0 0 0>;
28		interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
29
30		bus-range = <0x00 0xff>;
31		#address-cells = <3>;
32		#size-cells = <2>;
33
34		ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000   /* port 0 configuration space */
35			  0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000   /* port 1 configuration space */
36			  0x81000000 0 0x0        0x0 0x12000000 0 0x00010000   /* downstream I/O (64 KiB) */
37			  0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000   /* non-prefetchable memory (208 MiB) */
38			  0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
39
40		clocks = <&tegra_car TEGRA124_CLK_PCIE>,
41			 <&tegra_car TEGRA124_CLK_AFI>,
42			 <&tegra_car TEGRA124_CLK_PLL_E>,
43			 <&tegra_car TEGRA124_CLK_CML0>;
44		clock-names = "pex", "afi", "pll_e", "cml";
45		resets = <&tegra_car 70>,
46			 <&tegra_car 72>,
47			 <&tegra_car 74>;
48		reset-names = "pex", "afi", "pcie_x";
49		status = "disabled";
50
51		phys = <&padctl TEGRA_XUSB_PADCTL_PCIE>;
52		phy-names = "pcie";
53
54		pci@1,0 {
55			device_type = "pci";
56			assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
57			reg = <0x000800 0 0 0 0>;
58			status = "disabled";
59
60			#address-cells = <3>;
61			#size-cells = <2>;
62			ranges;
63
64			nvidia,num-lanes = <2>;
65		};
66
67		pci@2,0 {
68			device_type = "pci";
69			assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
70			reg = <0x001000 0 0 0 0>;
71			status = "disabled";
72
73			#address-cells = <3>;
74			#size-cells = <2>;
75			ranges;
76
77			nvidia,num-lanes = <1>;
78		};
79	};
80
81	host1x@50000000 {
82		compatible = "nvidia,tegra124-host1x", "simple-bus";
83		reg = <0x0 0x50000000 0x0 0x00034000>;
84		interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
85			     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
86		clocks = <&tegra_car TEGRA124_CLK_HOST1X>;
87		clock-names = "host1x";
88		resets = <&tegra_car 28>;
89		reset-names = "host1x";
90
91		#address-cells = <2>;
92		#size-cells = <2>;
93
94		ranges = <0 0x54000000 0 0x54000000 0 0x01000000>;
95
96		dc@54200000 {
97			compatible = "nvidia,tegra124-dc";
98			reg = <0x0 0x54200000 0x0 0x00040000>;
99			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
100			clocks = <&tegra_car TEGRA124_CLK_DISP1>,
101				 <&tegra_car TEGRA124_CLK_PLL_P>;
102			clock-names = "dc", "parent";
103			resets = <&tegra_car 27>;
104			reset-names = "dc";
105
106			iommus = <&mc TEGRA_SWGROUP_DC>;
107
108			nvidia,head = <0>;
109		};
110
111		dc@54240000 {
112			compatible = "nvidia,tegra124-dc";
113			reg = <0x0 0x54240000 0x0 0x00040000>;
114			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
115			clocks = <&tegra_car TEGRA124_CLK_DISP2>,
116				 <&tegra_car TEGRA124_CLK_PLL_P>;
117			clock-names = "dc", "parent";
118			resets = <&tegra_car 26>;
119			reset-names = "dc";
120
121			iommus = <&mc TEGRA_SWGROUP_DCB>;
122
123			nvidia,head = <1>;
124		};
125
126		hdmi@54280000 {
127			compatible = "nvidia,tegra124-hdmi";
128			reg = <0x0 0x54280000 0x0 0x00040000>;
129			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
130			clocks = <&tegra_car TEGRA124_CLK_HDMI>,
131				 <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>;
132			clock-names = "hdmi", "parent";
133			resets = <&tegra_car 51>;
134			reset-names = "hdmi";
135			status = "disabled";
136		};
137
138		sor@54540000 {
139			compatible = "nvidia,tegra124-sor";
140			reg = <0x0 0x54540000 0x0 0x00040000>;
141			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
142			clocks = <&tegra_car TEGRA124_CLK_SOR0>,
143				 <&tegra_car TEGRA124_CLK_PLL_D_OUT0>,
144				 <&tegra_car TEGRA124_CLK_PLL_DP>,
145				 <&tegra_car TEGRA124_CLK_CLK_M>;
146			clock-names = "sor", "parent", "dp", "safe";
147			resets = <&tegra_car 182>;
148			reset-names = "sor";
149			status = "disabled";
150		};
151
152		dpaux: dpaux@545c0000 {
153			compatible = "nvidia,tegra124-dpaux";
154			reg = <0x0 0x545c0000 0x0 0x00040000>;
155			interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
156			clocks = <&tegra_car TEGRA124_CLK_DPAUX>,
157				 <&tegra_car TEGRA124_CLK_PLL_DP>;
158			clock-names = "dpaux", "parent";
159			resets = <&tegra_car 181>;
160			reset-names = "dpaux";
161			status = "disabled";
162		};
163	};
164
165	gic: interrupt-controller@50041000 {
166		compatible = "arm,cortex-a15-gic";
167		#interrupt-cells = <3>;
168		interrupt-controller;
169		reg = <0x0 0x50041000 0x0 0x1000>,
170		      <0x0 0x50042000 0x0 0x2000>,
171		      <0x0 0x50044000 0x0 0x2000>,
172		      <0x0 0x50046000 0x0 0x2000>;
173		interrupts = <GIC_PPI 9
174			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
175		interrupt-parent = <&gic>;
176	};
177
178	gpu@57000000 {
179		compatible = "nvidia,gk20a";
180		reg = <0x0 0x57000000 0x0 0x01000000>,
181		      <0x0 0x58000000 0x0 0x01000000>;
182		interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
183			     <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
184		interrupt-names = "stall", "nonstall";
185		clocks = <&tegra_car TEGRA124_CLK_GPU>,
186			 <&tegra_car TEGRA124_CLK_PLL_P_OUT5>;
187		clock-names = "gpu", "pwr";
188		resets = <&tegra_car 184>;
189		reset-names = "gpu";
190		status = "disabled";
191	};
192
193	lic: interrupt-controller@60004000 {
194		compatible = "nvidia,tegra124-ictlr", "nvidia,tegra30-ictlr";
195		reg = <0x0 0x60004000 0x0 0x100>,
196		      <0x0 0x60004100 0x0 0x100>,
197		      <0x0 0x60004200 0x0 0x100>,
198		      <0x0 0x60004300 0x0 0x100>,
199		      <0x0 0x60004400 0x0 0x100>;
200		interrupt-controller;
201		#interrupt-cells = <3>;
202		interrupt-parent = <&gic>;
203	};
204
205	timer@60005000 {
206		compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer";
207		reg = <0x0 0x60005000 0x0 0x400>;
208		interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
209			     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
210			     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
211			     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
212			     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
213			     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
214		clocks = <&tegra_car TEGRA124_CLK_TIMER>;
215		clock-names = "timer";
216	};
217
218	tegra_car: clock@60006000 {
219		compatible = "nvidia,tegra132-car";
220		reg = <0x0 0x60006000 0x0 0x1000>;
221		#clock-cells = <1>;
222		#reset-cells = <1>;
223		nvidia,external-memory-controller = <&emc>;
224	};
225
226	flow-controller@60007000 {
227		compatible = "nvidia,tegra124-flowctrl";
228		reg = <0x0 0x60007000 0x0 0x1000>;
229	};
230
231	actmon@6000c800 {
232		compatible = "nvidia,tegra124-actmon";
233		reg = <0x0 0x6000c800 0x0 0x400>;
234		interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
235		clocks = <&tegra_car TEGRA124_CLK_ACTMON>,
236			 <&tegra_car TEGRA124_CLK_EMC>;
237		clock-names = "actmon", "emc";
238		resets = <&tegra_car 119>;
239		reset-names = "actmon";
240	};
241
242	gpio: gpio@6000d000 {
243		compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
244		reg = <0x0 0x6000d000 0x0 0x1000>;
245		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
246			     <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
247			     <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
248			     <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
249			     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
250			     <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
251			     <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
252			     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
253		#gpio-cells = <2>;
254		gpio-controller;
255		#interrupt-cells = <2>;
256		interrupt-controller;
257	};
258
259	apbdma: dma@60020000 {
260		compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma";
261		reg = <0x0 0x60020000 0x0 0x1400>;
262		interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
263			     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
264			     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
265			     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
266			     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
267			     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
268			     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
269			     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
270			     <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
271			     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
272			     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
273			     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
274			     <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
275			     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
276			     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
277			     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
278			     <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
279			     <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
280			     <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
281			     <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
282			     <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
283			     <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
284			     <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
285			     <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
286			     <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
287			     <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
288			     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
289			     <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
290			     <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
291			     <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
292			     <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
293			     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
294		clocks = <&tegra_car TEGRA124_CLK_APBDMA>;
295		clock-names = "dma";
296		resets = <&tegra_car 34>;
297		reset-names = "dma";
298		#dma-cells = <1>;
299	};
300
301	apbmisc@70000800 {
302		compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc";
303		reg = <0x0 0x70000800 0x0 0x64>,   /* Chip revision */
304		      <0x0 0x7000e864 0x0 0x04>;   /* Strapping options */
305	};
306
307	pinmux: pinmux@70000868 {
308		compatible = "nvidia,tegra124-pinmux";
309		reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */
310		      <0x0 0x70003000 0x0 0x434>, /* Mux registers */
311		      <0x0 0x70000820 0x0 0x008>; /* MIPI pad control */
312	};
313
314	/*
315	 * There are two serial driver i.e. 8250 based simple serial
316	 * driver and APB DMA based serial driver for higher baudrate
317	 * and performance. To enable the 8250 based driver, the compatible
318	 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
319	 * the APB DMA based serial driver, the compatible is
320	 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
321	 */
322	uarta: serial@70006000 {
323		compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
324		reg = <0x0 0x70006000 0x0 0x40>;
325		reg-shift = <2>;
326		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
327		clocks = <&tegra_car TEGRA124_CLK_UARTA>;
328		clock-names = "serial";
329		resets = <&tegra_car 6>;
330		reset-names = "serial";
331		dmas = <&apbdma 8>, <&apbdma 8>;
332		dma-names = "rx", "tx";
333		status = "disabled";
334	};
335
336	uartb: serial@70006040 {
337		compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
338		reg = <0x0 0x70006040 0x0 0x40>;
339		reg-shift = <2>;
340		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
341		clocks = <&tegra_car TEGRA124_CLK_UARTB>;
342		clock-names = "serial";
343		resets = <&tegra_car 7>;
344		reset-names = "serial";
345		dmas = <&apbdma 9>, <&apbdma 9>;
346		dma-names = "rx", "tx";
347		status = "disabled";
348	};
349
350	uartc: serial@70006200 {
351		compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
352		reg = <0x0 0x70006200 0x0 0x40>;
353		reg-shift = <2>;
354		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
355		clocks = <&tegra_car TEGRA124_CLK_UARTC>;
356		clock-names = "serial";
357		resets = <&tegra_car 55>;
358		reset-names = "serial";
359		dmas = <&apbdma 10>, <&apbdma 10>;
360		dma-names = "rx", "tx";
361		status = "disabled";
362	};
363
364	uartd: serial@70006300 {
365		compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
366		reg = <0x0 0x70006300 0x0 0x40>;
367		reg-shift = <2>;
368		interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
369		clocks = <&tegra_car TEGRA124_CLK_UARTD>;
370		clock-names = "serial";
371		resets = <&tegra_car 65>;
372		reset-names = "serial";
373		dmas = <&apbdma 19>, <&apbdma 19>;
374		dma-names = "rx", "tx";
375		status = "disabled";
376	};
377
378	pwm: pwm@7000a000 {
379		compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
380		reg = <0x0 0x7000a000 0x0 0x100>;
381		#pwm-cells = <2>;
382		clocks = <&tegra_car TEGRA124_CLK_PWM>;
383		clock-names = "pwm";
384		resets = <&tegra_car 17>;
385		reset-names = "pwm";
386		status = "disabled";
387	};
388
389	i2c@7000c000 {
390		compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
391		reg = <0x0 0x7000c000 0x0 0x100>;
392		interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
393		#address-cells = <1>;
394		#size-cells = <0>;
395		clocks = <&tegra_car TEGRA124_CLK_I2C1>;
396		clock-names = "div-clk";
397		resets = <&tegra_car 12>;
398		reset-names = "i2c";
399		dmas = <&apbdma 21>, <&apbdma 21>;
400		dma-names = "rx", "tx";
401		status = "disabled";
402	};
403
404	i2c@7000c400 {
405		compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
406		reg = <0x0 0x7000c400 0x0 0x100>;
407		interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
408		#address-cells = <1>;
409		#size-cells = <0>;
410		clocks = <&tegra_car TEGRA124_CLK_I2C2>;
411		clock-names = "div-clk";
412		resets = <&tegra_car 54>;
413		reset-names = "i2c";
414		dmas = <&apbdma 22>, <&apbdma 22>;
415		dma-names = "rx", "tx";
416		status = "disabled";
417	};
418
419	i2c@7000c500 {
420		compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
421		reg = <0x0 0x7000c500 0x0 0x100>;
422		interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
423		#address-cells = <1>;
424		#size-cells = <0>;
425		clocks = <&tegra_car TEGRA124_CLK_I2C3>;
426		clock-names = "div-clk";
427		resets = <&tegra_car 67>;
428		reset-names = "i2c";
429		dmas = <&apbdma 23>, <&apbdma 23>;
430		dma-names = "rx", "tx";
431		status = "disabled";
432	};
433
434	i2c@7000c700 {
435		compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
436		reg = <0x0 0x7000c700 0x0 0x100>;
437		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
438		#address-cells = <1>;
439		#size-cells = <0>;
440		clocks = <&tegra_car TEGRA124_CLK_I2C4>;
441		clock-names = "div-clk";
442		resets = <&tegra_car 103>;
443		reset-names = "i2c";
444		dmas = <&apbdma 26>, <&apbdma 26>;
445		dma-names = "rx", "tx";
446		status = "disabled";
447	};
448
449	i2c@7000d000 {
450		compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
451		reg = <0x0 0x7000d000 0x0 0x100>;
452		interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
453		#address-cells = <1>;
454		#size-cells = <0>;
455		clocks = <&tegra_car TEGRA124_CLK_I2C5>;
456		clock-names = "div-clk";
457		resets = <&tegra_car 47>;
458		reset-names = "i2c";
459		dmas = <&apbdma 24>, <&apbdma 24>;
460		dma-names = "rx", "tx";
461		status = "disabled";
462	};
463
464	i2c@7000d100 {
465		compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
466		reg = <0x0 0x7000d100 0x0 0x100>;
467		interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
468		#address-cells = <1>;
469		#size-cells = <0>;
470		clocks = <&tegra_car TEGRA124_CLK_I2C6>;
471		clock-names = "div-clk";
472		resets = <&tegra_car 166>;
473		reset-names = "i2c";
474		dmas = <&apbdma 30>, <&apbdma 30>;
475		dma-names = "rx", "tx";
476		status = "disabled";
477	};
478
479	spi@7000d400 {
480		compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
481		reg = <0x0 0x7000d400 0x0 0x200>;
482		interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
483		#address-cells = <1>;
484		#size-cells = <0>;
485		clocks = <&tegra_car TEGRA124_CLK_SBC1>;
486		clock-names = "spi";
487		resets = <&tegra_car 41>;
488		reset-names = "spi";
489		dmas = <&apbdma 15>, <&apbdma 15>;
490		dma-names = "rx", "tx";
491		status = "disabled";
492	};
493
494	spi@7000d600 {
495		compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
496		reg = <0x0 0x7000d600 0x0 0x200>;
497		interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
498		#address-cells = <1>;
499		#size-cells = <0>;
500		clocks = <&tegra_car TEGRA124_CLK_SBC2>;
501		clock-names = "spi";
502		resets = <&tegra_car 44>;
503		reset-names = "spi";
504		dmas = <&apbdma 16>, <&apbdma 16>;
505		dma-names = "rx", "tx";
506		status = "disabled";
507	};
508
509	spi@7000d800 {
510		compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
511		reg = <0x0 0x7000d800 0x0 0x200>;
512		interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
513		#address-cells = <1>;
514		#size-cells = <0>;
515		clocks = <&tegra_car TEGRA124_CLK_SBC3>;
516		clock-names = "spi";
517		resets = <&tegra_car 46>;
518		reset-names = "spi";
519		dmas = <&apbdma 17>, <&apbdma 17>;
520		dma-names = "rx", "tx";
521		status = "disabled";
522	};
523
524	spi@7000da00 {
525		compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
526		reg = <0x0 0x7000da00 0x0 0x200>;
527		interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
528		#address-cells = <1>;
529		#size-cells = <0>;
530		clocks = <&tegra_car TEGRA124_CLK_SBC4>;
531		clock-names = "spi";
532		resets = <&tegra_car 68>;
533		reset-names = "spi";
534		dmas = <&apbdma 18>, <&apbdma 18>;
535		dma-names = "rx", "tx";
536		status = "disabled";
537	};
538
539	spi@7000dc00 {
540		compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
541		reg = <0x0 0x7000dc00 0x0 0x200>;
542		interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
543		#address-cells = <1>;
544		#size-cells = <0>;
545		clocks = <&tegra_car TEGRA124_CLK_SBC5>;
546		clock-names = "spi";
547		resets = <&tegra_car 104>;
548		reset-names = "spi";
549		dmas = <&apbdma 27>, <&apbdma 27>;
550		dma-names = "rx", "tx";
551		status = "disabled";
552	};
553
554	spi@7000de00 {
555		compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
556		reg = <0x0 0x7000de00 0x0 0x200>;
557		interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
558		#address-cells = <1>;
559		#size-cells = <0>;
560		clocks = <&tegra_car TEGRA124_CLK_SBC6>;
561		clock-names = "spi";
562		resets = <&tegra_car 105>;
563		reset-names = "spi";
564		dmas = <&apbdma 28>, <&apbdma 28>;
565		dma-names = "rx", "tx";
566		status = "disabled";
567	};
568
569	rtc@7000e000 {
570		compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc";
571		reg = <0x0 0x7000e000 0x0 0x100>;
572		interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
573		clocks = <&tegra_car TEGRA124_CLK_RTC>;
574		clock-names = "rtc";
575	};
576
577	pmc@7000e400 {
578		compatible = "nvidia,tegra124-pmc";
579		reg = <0x0 0x7000e400 0x0 0x400>;
580		clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>;
581		clock-names = "pclk", "clk32k_in";
582	};
583
584	fuse@7000f800 {
585		compatible = "nvidia,tegra124-efuse";
586		reg = <0x0 0x7000f800 0x0 0x400>;
587		clocks = <&tegra_car TEGRA124_CLK_FUSE>;
588		clock-names = "fuse";
589		resets = <&tegra_car 39>;
590		reset-names = "fuse";
591	};
592
593	mc: memory-controller@70019000 {
594		compatible = "nvidia,tegra132-mc";
595		reg = <0x0 0x70019000 0x0 0x1000>;
596		clocks = <&tegra_car TEGRA124_CLK_MC>;
597		clock-names = "mc";
598
599		interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
600
601		#iommu-cells = <1>;
602	};
603
604	emc: emc@7001b000 {
605		compatible = "nvidia,tegra132-emc", "nvidia,tegra124-emc";
606		reg = <0x0 0x7001b000 0x0 0x1000>;
607
608		nvidia,memory-controller = <&mc>;
609	};
610
611	sata@70020000 {
612		compatible = "nvidia,tegra124-ahci";
613		reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
614		      <0x0 0x70020000 0x0 0x7000>; /* SATA */
615		interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
616		clocks = <&tegra_car TEGRA124_CLK_SATA>,
617			 <&tegra_car TEGRA124_CLK_SATA_OOB>,
618			 <&tegra_car TEGRA124_CLK_CML1>,
619			 <&tegra_car TEGRA124_CLK_PLL_E>;
620		clock-names = "sata", "sata-oob", "cml1", "pll_e";
621		resets = <&tegra_car 124>,
622			 <&tegra_car 123>,
623			 <&tegra_car 129>;
624		reset-names = "sata", "sata-oob", "sata-cold";
625		phys = <&padctl TEGRA_XUSB_PADCTL_SATA>;
626		phy-names = "sata-phy";
627		status = "disabled";
628	};
629
630	hda@70030000 {
631		compatible = "nvidia,tegra132-hda", "nvidia,tegra124-hda",
632			     "nvidia,tegra30-hda";
633		reg = <0x0 0x70030000 0x0 0x10000>;
634		interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
635		clocks = <&tegra_car TEGRA124_CLK_HDA>,
636		         <&tegra_car TEGRA124_CLK_HDA2HDMI>,
637			 <&tegra_car TEGRA124_CLK_HDA2CODEC_2X>;
638		clock-names = "hda", "hda2hdmi", "hda2codec_2x";
639		resets = <&tegra_car 125>, /* hda */
640			 <&tegra_car 128>, /* hda2hdmi */
641			 <&tegra_car 111>; /* hda2codec_2x */
642		reset-names = "hda", "hda2hdmi", "hda2codec_2x";
643		status = "disabled";
644	};
645
646	padctl: padctl@7009f000 {
647		compatible = "nvidia,tegra132-xusb-padctl",
648			     "nvidia,tegra124-xusb-padctl";
649		reg = <0x0 0x7009f000 0x0 0x1000>;
650		resets = <&tegra_car 142>;
651		reset-names = "padctl";
652
653		#phy-cells = <1>;
654
655		phys {
656			pcie-0 {
657				status = "disabled";
658			};
659
660			sata-0 {
661				status = "disabled";
662			};
663
664			usb3-0 {
665				status = "disabled";
666			};
667
668			usb3-1 {
669				status = "disabled";
670			};
671
672			utmi-0 {
673				status = "disabled";
674			};
675
676			utmi-1 {
677				status = "disabled";
678			};
679
680			utmi-2 {
681				status = "disabled";
682			};
683		};
684	};
685
686	sdhci@700b0000 {
687		compatible = "nvidia,tegra124-sdhci";
688		reg = <0x0 0x700b0000 0x0 0x200>;
689		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
690		clocks = <&tegra_car TEGRA124_CLK_SDMMC1>;
691		clock-names = "sdhci";
692		resets = <&tegra_car 14>;
693		reset-names = "sdhci";
694		status = "disabled";
695	};
696
697	sdhci@700b0200 {
698		compatible = "nvidia,tegra124-sdhci";
699		reg = <0x0 0x700b0200 0x0 0x200>;
700		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
701		clocks = <&tegra_car TEGRA124_CLK_SDMMC2>;
702		clock-names = "sdhci";
703		resets = <&tegra_car 9>;
704		reset-names = "sdhci";
705		status = "disabled";
706	};
707
708	sdhci@700b0400 {
709		compatible = "nvidia,tegra124-sdhci";
710		reg = <0x0 0x700b0400 0x0 0x200>;
711		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
712		clocks = <&tegra_car TEGRA124_CLK_SDMMC3>;
713		clock-names = "sdhci";
714		resets = <&tegra_car 69>;
715		reset-names = "sdhci";
716		status = "disabled";
717	};
718
719	sdhci@700b0600 {
720		compatible = "nvidia,tegra124-sdhci";
721		reg = <0x0 0x700b0600 0x0 0x200>;
722		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
723		clocks = <&tegra_car TEGRA124_CLK_SDMMC4>;
724		clock-names = "sdhci";
725		resets = <&tegra_car 15>;
726		reset-names = "sdhci";
727		status = "disabled";
728	};
729
730	soctherm: thermal-sensor@700e2000 {
731		compatible = "nvidia,tegra132-soctherm";
732		reg = <0x0 0x700e2000 0x0 0x600 /* 0: SOC_THERM reg_base */
733			0x0 0x70040000 0x0 0x200>; /* 2: CCROC reg_base */
734		reg-names = "soctherm-reg", "ccroc-reg";
735		interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
736		clocks = <&tegra_car TEGRA124_CLK_TSENSOR>,
737			<&tegra_car TEGRA124_CLK_SOC_THERM>;
738		clock-names = "tsensor", "soctherm";
739		resets = <&tegra_car 78>;
740		reset-names = "soctherm";
741		#thermal-sensor-cells = <1>;
742
743		throttle-cfgs {
744			throttle_heavy: heavy {
745				nvidia,priority = <100>;
746				nvidia,cpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_HIGH>;
747
748				#cooling-cells = <2>;
749			};
750		};
751	};
752
753	thermal-zones {
754		cpu {
755			polling-delay-passive = <1000>;
756			polling-delay = <0>;
757
758			thermal-sensors =
759				<&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>;
760
761			trips {
762				cpu_shutdown_trip {
763					temperature = <105000>;
764					hysteresis = <1000>;
765					type = "critical";
766				};
767
768				cpu_throttle_trip: throttle-trip {
769					temperature = <102000>;
770					hysteresis = <1000>;
771					type = "hot";
772				};
773			};
774
775			cooling-maps {
776				map0 {
777					trip = <&cpu_throttle_trip>;
778					cooling-device = <&throttle_heavy 1 1>;
779				};
780			};
781		};
782		mem {
783			polling-delay-passive = <0>;
784			polling-delay = <0>;
785
786			thermal-sensors =
787				<&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>;
788
789			trips {
790				mem_shutdown_trip {
791					temperature = <101000>;
792					hysteresis = <1000>;
793					type = "critical";
794				};
795			};
796
797			cooling-maps {
798				/*
799				 * There are currently no cooling maps,
800				 * because there are no cooling devices.
801				 */
802			};
803		};
804		gpu {
805			polling-delay-passive = <1000>;
806			polling-delay = <0>;
807
808			thermal-sensors =
809				<&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>;
810
811			trips {
812				gpu_shutdown_trip {
813					temperature = <101000>;
814					hysteresis = <1000>;
815					type = "critical";
816				};
817
818				gpu_throttle_trip: throttle-trip {
819					temperature = <99000>;
820					hysteresis = <1000>;
821					type = "hot";
822				};
823			};
824
825			cooling-maps {
826				map0 {
827					trip = <&gpu_throttle_trip>;
828					cooling-device = <&throttle_heavy 1 1>;
829				};
830			};
831		};
832		pllx {
833			polling-delay-passive = <0>;
834			polling-delay = <0>;
835
836			thermal-sensors =
837				<&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>;
838
839			trips {
840				pllx_shutdown_trip {
841					temperature = <105000>;
842					hysteresis = <1000>;
843					type = "critical";
844				};
845			};
846
847			cooling-maps {
848				/*
849				 * There are currently no cooling maps,
850				 * because there are no cooling devices.
851				 */
852			};
853		};
854	};
855
856	ahub@70300000 {
857		compatible = "nvidia,tegra124-ahub";
858		reg = <0x0 0x70300000 0x0 0x200>,
859		      <0x0 0x70300800 0x0 0x800>,
860		      <0x0 0x70300200 0x0 0x600>;
861		interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
862		clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>,
863			 <&tegra_car TEGRA124_CLK_APBIF>;
864		clock-names = "d_audio", "apbif";
865		resets = <&tegra_car 106>, /* d_audio */
866			 <&tegra_car 107>, /* apbif */
867			 <&tegra_car 30>,  /* i2s0 */
868			 <&tegra_car 11>,  /* i2s1 */
869			 <&tegra_car 18>,  /* i2s2 */
870			 <&tegra_car 101>, /* i2s3 */
871			 <&tegra_car 102>, /* i2s4 */
872			 <&tegra_car 108>, /* dam0 */
873			 <&tegra_car 109>, /* dam1 */
874			 <&tegra_car 110>, /* dam2 */
875			 <&tegra_car 10>,  /* spdif */
876			 <&tegra_car 153>, /* amx */
877			 <&tegra_car 185>, /* amx1 */
878			 <&tegra_car 154>, /* adx */
879			 <&tegra_car 180>, /* adx1 */
880			 <&tegra_car 186>, /* afc0 */
881			 <&tegra_car 187>, /* afc1 */
882			 <&tegra_car 188>, /* afc2 */
883			 <&tegra_car 189>, /* afc3 */
884			 <&tegra_car 190>, /* afc4 */
885			 <&tegra_car 191>; /* afc5 */
886		reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
887			      "i2s3", "i2s4", "dam0", "dam1", "dam2",
888			      "spdif", "amx", "amx1", "adx", "adx1",
889			      "afc0", "afc1", "afc2", "afc3", "afc4", "afc5";
890		dmas = <&apbdma 1>, <&apbdma 1>,
891		       <&apbdma 2>, <&apbdma 2>,
892		       <&apbdma 3>, <&apbdma 3>,
893		       <&apbdma 4>, <&apbdma 4>,
894		       <&apbdma 6>, <&apbdma 6>,
895		       <&apbdma 7>, <&apbdma 7>,
896		       <&apbdma 12>, <&apbdma 12>,
897		       <&apbdma 13>, <&apbdma 13>,
898		       <&apbdma 14>, <&apbdma 14>,
899		       <&apbdma 29>, <&apbdma 29>;
900		dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
901			    "rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
902			    "rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
903			    "rx9", "tx9";
904		ranges;
905		#address-cells = <2>;
906		#size-cells = <2>;
907
908		tegra_i2s0: i2s@70301000 {
909			compatible = "nvidia,tegra124-i2s";
910			reg = <0x0 0x70301000 0x0 0x100>;
911			nvidia,ahub-cif-ids = <4 4>;
912			clocks = <&tegra_car TEGRA124_CLK_I2S0>;
913			clock-names = "i2s";
914			resets = <&tegra_car 30>;
915			reset-names = "i2s";
916			status = "disabled";
917		};
918
919		tegra_i2s1: i2s@70301100 {
920			compatible = "nvidia,tegra124-i2s";
921			reg = <0x0 0x70301100 0x0 0x100>;
922			nvidia,ahub-cif-ids = <5 5>;
923			clocks = <&tegra_car TEGRA124_CLK_I2S1>;
924			clock-names = "i2s";
925			resets = <&tegra_car 11>;
926			reset-names = "i2s";
927			status = "disabled";
928		};
929
930		tegra_i2s2: i2s@70301200 {
931			compatible = "nvidia,tegra124-i2s";
932			reg = <0x0 0x70301200 0x0 0x100>;
933			nvidia,ahub-cif-ids = <6 6>;
934			clocks = <&tegra_car TEGRA124_CLK_I2S2>;
935			clock-names = "i2s";
936			resets = <&tegra_car 18>;
937			reset-names = "i2s";
938			status = "disabled";
939		};
940
941		tegra_i2s3: i2s@70301300 {
942			compatible = "nvidia,tegra124-i2s";
943			reg = <0x0 0x70301300 0x0 0x100>;
944			nvidia,ahub-cif-ids = <7 7>;
945			clocks = <&tegra_car TEGRA124_CLK_I2S3>;
946			clock-names = "i2s";
947			resets = <&tegra_car 101>;
948			reset-names = "i2s";
949			status = "disabled";
950		};
951
952		tegra_i2s4: i2s@70301400 {
953			compatible = "nvidia,tegra124-i2s";
954			reg = <0x0 0x70301400 0x0 0x100>;
955			nvidia,ahub-cif-ids = <8 8>;
956			clocks = <&tegra_car TEGRA124_CLK_I2S4>;
957			clock-names = "i2s";
958			resets = <&tegra_car 102>;
959			reset-names = "i2s";
960			status = "disabled";
961		};
962	};
963
964	usb@7d000000 {
965		compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
966		reg = <0x0 0x7d000000 0x0 0x4000>;
967		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
968		phy_type = "utmi";
969		clocks = <&tegra_car TEGRA124_CLK_USBD>;
970		clock-names = "usb";
971		resets = <&tegra_car 22>;
972		reset-names = "usb";
973		nvidia,phy = <&phy1>;
974		status = "disabled";
975	};
976
977	phy1: usb-phy@7d000000 {
978		compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
979		reg = <0x0 0x7d000000 0x0 0x4000>,
980		      <0x0 0x7d000000 0x0 0x4000>;
981		phy_type = "utmi";
982		clocks = <&tegra_car TEGRA124_CLK_USBD>,
983			 <&tegra_car TEGRA124_CLK_PLL_U>,
984			 <&tegra_car TEGRA124_CLK_USBD>;
985		clock-names = "reg", "pll_u", "utmi-pads";
986		resets = <&tegra_car 22>, <&tegra_car 22>;
987		reset-names = "usb", "utmi-pads";
988		nvidia,hssync-start-delay = <0>;
989		nvidia,idle-wait-delay = <17>;
990		nvidia,elastic-limit = <16>;
991		nvidia,term-range-adj = <6>;
992		nvidia,xcvr-setup = <9>;
993		nvidia,xcvr-lsfslew = <0>;
994		nvidia,xcvr-lsrslew = <3>;
995		nvidia,hssquelch-level = <2>;
996		nvidia,hsdiscon-level = <5>;
997		nvidia,xcvr-hsslew = <12>;
998		nvidia,has-utmi-pad-registers;
999		status = "disabled";
1000	};
1001
1002	usb@7d004000 {
1003		compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
1004		reg = <0x0 0x7d004000 0x0 0x4000>;
1005		interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1006		phy_type = "utmi";
1007		clocks = <&tegra_car TEGRA124_CLK_USB2>;
1008		clock-names = "usb";
1009		resets = <&tegra_car 58>;
1010		reset-names = "usb";
1011		nvidia,phy = <&phy2>;
1012		status = "disabled";
1013	};
1014
1015	phy2: usb-phy@7d004000 {
1016		compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
1017		reg = <0x0 0x7d004000 0x0 0x4000>,
1018		      <0x0 0x7d000000 0x0 0x4000>;
1019		phy_type = "utmi";
1020		clocks = <&tegra_car TEGRA124_CLK_USB2>,
1021			 <&tegra_car TEGRA124_CLK_PLL_U>,
1022			 <&tegra_car TEGRA124_CLK_USBD>;
1023		clock-names = "reg", "pll_u", "utmi-pads";
1024		resets = <&tegra_car 58>, <&tegra_car 22>;
1025		reset-names = "usb", "utmi-pads";
1026		nvidia,hssync-start-delay = <0>;
1027		nvidia,idle-wait-delay = <17>;
1028		nvidia,elastic-limit = <16>;
1029		nvidia,term-range-adj = <6>;
1030		nvidia,xcvr-setup = <9>;
1031		nvidia,xcvr-lsfslew = <0>;
1032		nvidia,xcvr-lsrslew = <3>;
1033		nvidia,hssquelch-level = <2>;
1034		nvidia,hsdiscon-level = <5>;
1035		nvidia,xcvr-hsslew = <12>;
1036		status = "disabled";
1037	};
1038
1039	usb@7d008000 {
1040		compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
1041		reg = <0x0 0x7d008000 0x0 0x4000>;
1042		interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1043		phy_type = "utmi";
1044		clocks = <&tegra_car TEGRA124_CLK_USB3>;
1045		clock-names = "usb";
1046		resets = <&tegra_car 59>;
1047		reset-names = "usb";
1048		nvidia,phy = <&phy3>;
1049		status = "disabled";
1050	};
1051
1052	phy3: usb-phy@7d008000 {
1053		compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
1054		reg = <0x0 0x7d008000 0x0 0x4000>,
1055		      <0x0 0x7d000000 0x0 0x4000>;
1056		phy_type = "utmi";
1057		clocks = <&tegra_car TEGRA124_CLK_USB3>,
1058			 <&tegra_car TEGRA124_CLK_PLL_U>,
1059			 <&tegra_car TEGRA124_CLK_USBD>;
1060		clock-names = "reg", "pll_u", "utmi-pads";
1061		resets = <&tegra_car 59>, <&tegra_car 22>;
1062		reset-names = "usb", "utmi-pads";
1063		nvidia,hssync-start-delay = <0>;
1064		nvidia,idle-wait-delay = <17>;
1065		nvidia,elastic-limit = <16>;
1066		nvidia,term-range-adj = <6>;
1067		nvidia,xcvr-setup = <9>;
1068		nvidia,xcvr-lsfslew = <0>;
1069		nvidia,xcvr-lsrslew = <3>;
1070		nvidia,hssquelch-level = <2>;
1071		nvidia,hsdiscon-level = <5>;
1072		nvidia,xcvr-hsslew = <12>;
1073		status = "disabled";
1074	};
1075
1076	cpus {
1077		#address-cells = <1>;
1078		#size-cells = <0>;
1079
1080		cpu@0 {
1081			device_type = "cpu";
1082			compatible = "nvidia,denver", "arm,armv8";
1083			reg = <0>;
1084		};
1085
1086		cpu@1 {
1087			device_type = "cpu";
1088			compatible = "nvidia,denver", "arm,armv8";
1089			reg = <1>;
1090		};
1091	};
1092
1093	timer {
1094		compatible = "arm,armv7-timer";
1095		interrupts = <GIC_PPI 13
1096				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1097			     <GIC_PPI 14
1098				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1099			     <GIC_PPI 11
1100				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1101			     <GIC_PPI 10
1102				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
1103		interrupt-parent = <&gic>;
1104	};
1105};
1106