1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra124-car.h> 3#include <dt-bindings/gpio/tegra-gpio.h> 4#include <dt-bindings/memory/tegra124-mc.h> 5#include <dt-bindings/pinctrl/pinctrl-tegra.h> 6#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/thermal/tegra124-soctherm.h> 9#include <dt-bindings/soc/tegra-pmc.h> 10 11/ { 12 compatible = "nvidia,tegra132", "nvidia,tegra124"; 13 interrupt-parent = <&lic>; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 pcie@1003000 { 18 compatible = "nvidia,tegra124-pcie"; 19 device_type = "pci"; 20 reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */ 21 <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */ 22 <0x0 0x02000000 0x0 0x10000000>; /* configuration space */ 23 reg-names = "pads", "afi", "cs"; 24 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 25 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 26 interrupt-names = "intr", "msi"; 27 28 #interrupt-cells = <1>; 29 interrupt-map-mask = <0 0 0 0>; 30 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 31 32 bus-range = <0x00 0xff>; 33 #address-cells = <3>; 34 #size-cells = <2>; 35 36 ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */ 37 <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */ 38 <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */ 39 <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */ 40 <0x42000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ 41 42 clocks = <&tegra_car TEGRA124_CLK_PCIE>, 43 <&tegra_car TEGRA124_CLK_AFI>, 44 <&tegra_car TEGRA124_CLK_PLL_E>, 45 <&tegra_car TEGRA124_CLK_CML0>; 46 clock-names = "pex", "afi", "pll_e", "cml"; 47 resets = <&tegra_car 70>, 48 <&tegra_car 72>, 49 <&tegra_car 74>; 50 reset-names = "pex", "afi", "pcie_x"; 51 status = "disabled"; 52 53 pci@1,0 { 54 device_type = "pci"; 55 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>; 56 reg = <0x000800 0 0 0 0>; 57 bus-range = <0x00 0xff>; 58 status = "disabled"; 59 60 #address-cells = <3>; 61 #size-cells = <2>; 62 ranges; 63 64 nvidia,num-lanes = <2>; 65 }; 66 67 pci@2,0 { 68 device_type = "pci"; 69 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>; 70 reg = <0x001000 0 0 0 0>; 71 bus-range = <0x00 0xff>; 72 status = "disabled"; 73 74 #address-cells = <3>; 75 #size-cells = <2>; 76 ranges; 77 78 nvidia,num-lanes = <1>; 79 }; 80 }; 81 82 host1x@50000000 { 83 compatible = "nvidia,tegra132-host1x", 84 "nvidia,tegra124-host1x"; 85 reg = <0x0 0x50000000 0x0 0x00034000>; 86 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 87 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ 88 interrupt-names = "syncpt", "host1x"; 89 clocks = <&tegra_car TEGRA124_CLK_HOST1X>; 90 clock-names = "host1x"; 91 resets = <&tegra_car 28>; 92 reset-names = "host1x"; 93 94 #address-cells = <2>; 95 #size-cells = <2>; 96 97 ranges = <0 0x54000000 0 0x54000000 0 0x01000000>; 98 99 dc@54200000 { 100 compatible = "nvidia,tegra124-dc"; 101 reg = <0x0 0x54200000 0x0 0x00040000>; 102 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 103 clocks = <&tegra_car TEGRA124_CLK_DISP1>; 104 clock-names = "dc"; 105 resets = <&tegra_car 27>; 106 reset-names = "dc"; 107 108 iommus = <&mc TEGRA_SWGROUP_DC>; 109 110 nvidia,head = <0>; 111 }; 112 113 dc@54240000 { 114 compatible = "nvidia,tegra124-dc"; 115 reg = <0x0 0x54240000 0x0 0x00040000>; 116 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 117 clocks = <&tegra_car TEGRA124_CLK_DISP2>; 118 clock-names = "dc"; 119 resets = <&tegra_car 26>; 120 reset-names = "dc"; 121 122 iommus = <&mc TEGRA_SWGROUP_DCB>; 123 124 nvidia,head = <1>; 125 }; 126 127 hdmi@54280000 { 128 compatible = "nvidia,tegra124-hdmi"; 129 reg = <0x0 0x54280000 0x0 0x00040000>; 130 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 131 clocks = <&tegra_car TEGRA124_CLK_HDMI>, 132 <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>; 133 clock-names = "hdmi", "parent"; 134 resets = <&tegra_car 51>; 135 reset-names = "hdmi"; 136 status = "disabled"; 137 }; 138 139 sor@54540000 { 140 compatible = "nvidia,tegra124-sor"; 141 reg = <0x0 0x54540000 0x0 0x00040000>; 142 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 143 clocks = <&tegra_car TEGRA124_CLK_SOR0>, 144 <&tegra_car TEGRA124_CLK_PLL_D_OUT0>, 145 <&tegra_car TEGRA124_CLK_PLL_DP>, 146 <&tegra_car TEGRA124_CLK_CLK_M>; 147 clock-names = "sor", "parent", "dp", "safe"; 148 resets = <&tegra_car 182>; 149 reset-names = "sor"; 150 status = "disabled"; 151 }; 152 153 dpaux: dpaux@545c0000 { 154 compatible = "nvidia,tegra124-dpaux"; 155 reg = <0x0 0x545c0000 0x0 0x00040000>; 156 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 157 clocks = <&tegra_car TEGRA124_CLK_DPAUX>, 158 <&tegra_car TEGRA124_CLK_PLL_DP>; 159 clock-names = "dpaux", "parent"; 160 resets = <&tegra_car 181>; 161 reset-names = "dpaux"; 162 status = "disabled"; 163 }; 164 }; 165 166 gic: interrupt-controller@50041000 { 167 compatible = "arm,cortex-a15-gic"; 168 #interrupt-cells = <3>; 169 interrupt-controller; 170 reg = <0x0 0x50041000 0x0 0x1000>, 171 <0x0 0x50042000 0x0 0x2000>, 172 <0x0 0x50044000 0x0 0x2000>, 173 <0x0 0x50046000 0x0 0x2000>; 174 interrupts = <GIC_PPI 9 175 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 176 interrupt-parent = <&gic>; 177 }; 178 179 gpu@57000000 { 180 compatible = "nvidia,gk20a"; 181 reg = <0x0 0x57000000 0x0 0x01000000>, 182 <0x0 0x58000000 0x0 0x01000000>; 183 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 184 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 185 interrupt-names = "stall", "nonstall"; 186 clocks = <&tegra_car TEGRA124_CLK_GPU>, 187 <&tegra_car TEGRA124_CLK_PLL_P_OUT5>; 188 clock-names = "gpu", "pwr"; 189 resets = <&tegra_car 184>; 190 reset-names = "gpu"; 191 status = "disabled"; 192 }; 193 194 lic: interrupt-controller@60004000 { 195 compatible = "nvidia,tegra124-ictlr", "nvidia,tegra30-ictlr"; 196 reg = <0x0 0x60004000 0x0 0x100>, 197 <0x0 0x60004100 0x0 0x100>, 198 <0x0 0x60004200 0x0 0x100>, 199 <0x0 0x60004300 0x0 0x100>, 200 <0x0 0x60004400 0x0 0x100>; 201 interrupt-controller; 202 #interrupt-cells = <3>; 203 interrupt-parent = <&gic>; 204 }; 205 206 timer@60005000 { 207 compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer"; 208 reg = <0x0 0x60005000 0x0 0x400>; 209 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 210 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 211 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 212 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 213 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 214 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 215 clocks = <&tegra_car TEGRA124_CLK_TIMER>; 216 clock-names = "timer"; 217 }; 218 219 tegra_car: clock@60006000 { 220 compatible = "nvidia,tegra132-car"; 221 reg = <0x0 0x60006000 0x0 0x1000>; 222 #clock-cells = <1>; 223 #reset-cells = <1>; 224 nvidia,external-memory-controller = <&emc>; 225 }; 226 227 flow-controller@60007000 { 228 compatible = "nvidia,tegra132-flowctrl", "nvidia,tegra124-flowctrl"; 229 reg = <0x0 0x60007000 0x0 0x1000>; 230 }; 231 232 actmon@6000c800 { 233 compatible = "nvidia,tegra124-actmon"; 234 reg = <0x0 0x6000c800 0x0 0x400>; 235 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 236 clocks = <&tegra_car TEGRA124_CLK_ACTMON>, 237 <&tegra_car TEGRA124_CLK_EMC>; 238 clock-names = "actmon", "emc"; 239 resets = <&tegra_car 119>; 240 reset-names = "actmon"; 241 }; 242 243 gpio: gpio@6000d000 { 244 compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio"; 245 reg = <0x0 0x6000d000 0x0 0x1000>; 246 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 247 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 248 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 249 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 250 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 251 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 252 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 253 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 254 #gpio-cells = <2>; 255 gpio-controller; 256 #interrupt-cells = <2>; 257 interrupt-controller; 258 }; 259 260 apbdma: dma@60020000 { 261 compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma"; 262 reg = <0x0 0x60020000 0x0 0x1400>; 263 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 264 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 265 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 266 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 267 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 268 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 269 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 270 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 271 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 272 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 273 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 274 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 275 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 276 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 277 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 278 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 279 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 280 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 281 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 282 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 283 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 284 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 285 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 286 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 287 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 288 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 289 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 290 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 291 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 292 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 293 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 294 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 295 clocks = <&tegra_car TEGRA124_CLK_APBDMA>; 296 clock-names = "dma"; 297 resets = <&tegra_car 34>; 298 reset-names = "dma"; 299 #dma-cells = <1>; 300 }; 301 302 apbmisc@70000800 { 303 compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc"; 304 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */ 305 <0x0 0x7000e864 0x0 0x04>; /* Strapping options */ 306 }; 307 308 pinmux: pinmux@70000868 { 309 compatible = "nvidia,tegra124-pinmux"; 310 reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */ 311 <0x0 0x70003000 0x0 0x434>, /* Mux registers */ 312 <0x0 0x70000820 0x0 0x008>; /* MIPI pad control */ 313 }; 314 315 /* 316 * There are two serial driver i.e. 8250 based simple serial 317 * driver and APB DMA based serial driver for higher baudrate 318 * and performance. To enable the 8250 based driver, the compatible 319 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable 320 * the APB DMA based serial driver, the compatible is 321 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". 322 */ 323 uarta: serial@70006000 { 324 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 325 reg = <0x0 0x70006000 0x0 0x40>; 326 reg-shift = <2>; 327 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 328 clocks = <&tegra_car TEGRA124_CLK_UARTA>; 329 clock-names = "serial"; 330 resets = <&tegra_car 6>; 331 reset-names = "serial"; 332 dmas = <&apbdma 8>, <&apbdma 8>; 333 dma-names = "rx", "tx"; 334 status = "disabled"; 335 }; 336 337 uartb: serial@70006040 { 338 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 339 reg = <0x0 0x70006040 0x0 0x40>; 340 reg-shift = <2>; 341 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 342 clocks = <&tegra_car TEGRA124_CLK_UARTB>; 343 clock-names = "serial"; 344 resets = <&tegra_car 7>; 345 reset-names = "serial"; 346 dmas = <&apbdma 9>, <&apbdma 9>; 347 dma-names = "rx", "tx"; 348 status = "disabled"; 349 }; 350 351 uartc: serial@70006200 { 352 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 353 reg = <0x0 0x70006200 0x0 0x40>; 354 reg-shift = <2>; 355 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 356 clocks = <&tegra_car TEGRA124_CLK_UARTC>; 357 clock-names = "serial"; 358 resets = <&tegra_car 55>; 359 reset-names = "serial"; 360 dmas = <&apbdma 10>, <&apbdma 10>; 361 dma-names = "rx", "tx"; 362 status = "disabled"; 363 }; 364 365 uartd: serial@70006300 { 366 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 367 reg = <0x0 0x70006300 0x0 0x40>; 368 reg-shift = <2>; 369 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 370 clocks = <&tegra_car TEGRA124_CLK_UARTD>; 371 clock-names = "serial"; 372 resets = <&tegra_car 65>; 373 reset-names = "serial"; 374 dmas = <&apbdma 19>, <&apbdma 19>; 375 dma-names = "rx", "tx"; 376 status = "disabled"; 377 }; 378 379 pwm: pwm@7000a000 { 380 compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm"; 381 reg = <0x0 0x7000a000 0x0 0x100>; 382 #pwm-cells = <2>; 383 clocks = <&tegra_car TEGRA124_CLK_PWM>; 384 clock-names = "pwm"; 385 resets = <&tegra_car 17>; 386 reset-names = "pwm"; 387 status = "disabled"; 388 }; 389 390 i2c@7000c000 { 391 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 392 reg = <0x0 0x7000c000 0x0 0x100>; 393 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 394 #address-cells = <1>; 395 #size-cells = <0>; 396 clocks = <&tegra_car TEGRA124_CLK_I2C1>; 397 clock-names = "div-clk"; 398 resets = <&tegra_car 12>; 399 reset-names = "i2c"; 400 dmas = <&apbdma 21>, <&apbdma 21>; 401 dma-names = "rx", "tx"; 402 status = "disabled"; 403 }; 404 405 i2c@7000c400 { 406 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 407 reg = <0x0 0x7000c400 0x0 0x100>; 408 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 409 #address-cells = <1>; 410 #size-cells = <0>; 411 clocks = <&tegra_car TEGRA124_CLK_I2C2>; 412 clock-names = "div-clk"; 413 resets = <&tegra_car 54>; 414 reset-names = "i2c"; 415 dmas = <&apbdma 22>, <&apbdma 22>; 416 dma-names = "rx", "tx"; 417 status = "disabled"; 418 }; 419 420 i2c@7000c500 { 421 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 422 reg = <0x0 0x7000c500 0x0 0x100>; 423 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 424 #address-cells = <1>; 425 #size-cells = <0>; 426 clocks = <&tegra_car TEGRA124_CLK_I2C3>; 427 clock-names = "div-clk"; 428 resets = <&tegra_car 67>; 429 reset-names = "i2c"; 430 dmas = <&apbdma 23>, <&apbdma 23>; 431 dma-names = "rx", "tx"; 432 status = "disabled"; 433 }; 434 435 i2c@7000c700 { 436 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 437 reg = <0x0 0x7000c700 0x0 0x100>; 438 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 439 #address-cells = <1>; 440 #size-cells = <0>; 441 clocks = <&tegra_car TEGRA124_CLK_I2C4>; 442 clock-names = "div-clk"; 443 resets = <&tegra_car 103>; 444 reset-names = "i2c"; 445 dmas = <&apbdma 26>, <&apbdma 26>; 446 dma-names = "rx", "tx"; 447 status = "disabled"; 448 }; 449 450 i2c@7000d000 { 451 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 452 reg = <0x0 0x7000d000 0x0 0x100>; 453 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 454 #address-cells = <1>; 455 #size-cells = <0>; 456 clocks = <&tegra_car TEGRA124_CLK_I2C5>; 457 clock-names = "div-clk"; 458 resets = <&tegra_car 47>; 459 reset-names = "i2c"; 460 dmas = <&apbdma 24>, <&apbdma 24>; 461 dma-names = "rx", "tx"; 462 status = "disabled"; 463 }; 464 465 i2c@7000d100 { 466 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 467 reg = <0x0 0x7000d100 0x0 0x100>; 468 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 469 #address-cells = <1>; 470 #size-cells = <0>; 471 clocks = <&tegra_car TEGRA124_CLK_I2C6>; 472 clock-names = "div-clk"; 473 resets = <&tegra_car 166>; 474 reset-names = "i2c"; 475 dmas = <&apbdma 30>, <&apbdma 30>; 476 dma-names = "rx", "tx"; 477 status = "disabled"; 478 }; 479 480 spi@7000d400 { 481 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 482 reg = <0x0 0x7000d400 0x0 0x200>; 483 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 484 #address-cells = <1>; 485 #size-cells = <0>; 486 clocks = <&tegra_car TEGRA124_CLK_SBC1>; 487 clock-names = "spi"; 488 resets = <&tegra_car 41>; 489 reset-names = "spi"; 490 dmas = <&apbdma 15>, <&apbdma 15>; 491 dma-names = "rx", "tx"; 492 status = "disabled"; 493 }; 494 495 spi@7000d600 { 496 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 497 reg = <0x0 0x7000d600 0x0 0x200>; 498 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 499 #address-cells = <1>; 500 #size-cells = <0>; 501 clocks = <&tegra_car TEGRA124_CLK_SBC2>; 502 clock-names = "spi"; 503 resets = <&tegra_car 44>; 504 reset-names = "spi"; 505 dmas = <&apbdma 16>, <&apbdma 16>; 506 dma-names = "rx", "tx"; 507 status = "disabled"; 508 }; 509 510 spi@7000d800 { 511 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 512 reg = <0x0 0x7000d800 0x0 0x200>; 513 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 514 #address-cells = <1>; 515 #size-cells = <0>; 516 clocks = <&tegra_car TEGRA124_CLK_SBC3>; 517 clock-names = "spi"; 518 resets = <&tegra_car 46>; 519 reset-names = "spi"; 520 dmas = <&apbdma 17>, <&apbdma 17>; 521 dma-names = "rx", "tx"; 522 status = "disabled"; 523 }; 524 525 spi@7000da00 { 526 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 527 reg = <0x0 0x7000da00 0x0 0x200>; 528 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 529 #address-cells = <1>; 530 #size-cells = <0>; 531 clocks = <&tegra_car TEGRA124_CLK_SBC4>; 532 clock-names = "spi"; 533 resets = <&tegra_car 68>; 534 reset-names = "spi"; 535 dmas = <&apbdma 18>, <&apbdma 18>; 536 dma-names = "rx", "tx"; 537 status = "disabled"; 538 }; 539 540 spi@7000dc00 { 541 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 542 reg = <0x0 0x7000dc00 0x0 0x200>; 543 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 544 #address-cells = <1>; 545 #size-cells = <0>; 546 clocks = <&tegra_car TEGRA124_CLK_SBC5>; 547 clock-names = "spi"; 548 resets = <&tegra_car 104>; 549 reset-names = "spi"; 550 dmas = <&apbdma 27>, <&apbdma 27>; 551 dma-names = "rx", "tx"; 552 status = "disabled"; 553 }; 554 555 spi@7000de00 { 556 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 557 reg = <0x0 0x7000de00 0x0 0x200>; 558 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 559 #address-cells = <1>; 560 #size-cells = <0>; 561 clocks = <&tegra_car TEGRA124_CLK_SBC6>; 562 clock-names = "spi"; 563 resets = <&tegra_car 105>; 564 reset-names = "spi"; 565 dmas = <&apbdma 28>, <&apbdma 28>; 566 dma-names = "rx", "tx"; 567 status = "disabled"; 568 }; 569 570 rtc@7000e000 { 571 compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc"; 572 reg = <0x0 0x7000e000 0x0 0x100>; 573 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 574 clocks = <&tegra_car TEGRA124_CLK_RTC>; 575 clock-names = "rtc"; 576 }; 577 578 tegra_pmc: pmc@7000e400 { 579 compatible = "nvidia,tegra124-pmc"; 580 reg = <0x0 0x7000e400 0x0 0x400>; 581 clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>; 582 clock-names = "pclk", "clk32k_in"; 583 #clock-cells = <1>; 584 }; 585 586 fuse@7000f800 { 587 compatible = "nvidia,tegra124-efuse"; 588 reg = <0x0 0x7000f800 0x0 0x400>; 589 clocks = <&tegra_car TEGRA124_CLK_FUSE>; 590 clock-names = "fuse"; 591 resets = <&tegra_car 39>; 592 reset-names = "fuse"; 593 }; 594 595 mc: memory-controller@70019000 { 596 compatible = "nvidia,tegra132-mc"; 597 reg = <0x0 0x70019000 0x0 0x1000>; 598 clocks = <&tegra_car TEGRA124_CLK_MC>; 599 clock-names = "mc"; 600 601 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 602 603 #iommu-cells = <1>; 604 }; 605 606 emc: external-memory-controller@7001b000 { 607 compatible = "nvidia,tegra132-emc", "nvidia,tegra124-emc"; 608 reg = <0x0 0x7001b000 0x0 0x1000>; 609 clocks = <&tegra_car TEGRA124_CLK_EMC>; 610 clock-names = "emc"; 611 612 nvidia,memory-controller = <&mc>; 613 }; 614 615 sata@70020000 { 616 compatible = "nvidia,tegra124-ahci"; 617 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */ 618 <0x0 0x70020000 0x0 0x7000>; /* SATA */ 619 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 620 clocks = <&tegra_car TEGRA124_CLK_SATA>, 621 <&tegra_car TEGRA124_CLK_SATA_OOB>, 622 <&tegra_car TEGRA124_CLK_CML1>, 623 <&tegra_car TEGRA124_CLK_PLL_E>; 624 clock-names = "sata", "sata-oob", "cml1", "pll_e"; 625 resets = <&tegra_car 124>, 626 <&tegra_car 123>, 627 <&tegra_car 129>; 628 reset-names = "sata", "sata-oob", "sata-cold"; 629 status = "disabled"; 630 }; 631 632 hda@70030000 { 633 compatible = "nvidia,tegra132-hda", "nvidia,tegra124-hda", 634 "nvidia,tegra30-hda"; 635 reg = <0x0 0x70030000 0x0 0x10000>; 636 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 637 clocks = <&tegra_car TEGRA124_CLK_HDA>, 638 <&tegra_car TEGRA124_CLK_HDA2HDMI>, 639 <&tegra_car TEGRA124_CLK_HDA2CODEC_2X>; 640 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 641 resets = <&tegra_car 125>, /* hda */ 642 <&tegra_car 128>, /* hda2hdmi */ 643 <&tegra_car 111>; /* hda2codec_2x */ 644 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 645 status = "disabled"; 646 }; 647 648 usb@70090000 { 649 compatible = "nvidia,tegra132-xusb", "nvidia,tegra124-xusb"; 650 reg = <0x0 0x70090000 0x0 0x8000>, 651 <0x0 0x70098000 0x0 0x1000>, 652 <0x0 0x70099000 0x0 0x1000>; 653 reg-names = "hcd", "fpci", "ipfs"; 654 655 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 656 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 657 658 clocks = <&tegra_car TEGRA124_CLK_XUSB_HOST>, 659 <&tegra_car TEGRA124_CLK_XUSB_HOST_SRC>, 660 <&tegra_car TEGRA124_CLK_XUSB_FALCON_SRC>, 661 <&tegra_car TEGRA124_CLK_XUSB_SS>, 662 <&tegra_car TEGRA124_CLK_XUSB_SS_SRC>, 663 <&tegra_car TEGRA124_CLK_XUSB_SS_DIV2>, 664 <&tegra_car TEGRA124_CLK_XUSB_HS_SRC>, 665 <&tegra_car TEGRA124_CLK_XUSB_FS_SRC>, 666 <&tegra_car TEGRA124_CLK_PLL_U_480M>, 667 <&tegra_car TEGRA124_CLK_CLK_M>, 668 <&tegra_car TEGRA124_CLK_PLL_E>; 669 clock-names = "xusb_host", "xusb_host_src", 670 "xusb_falcon_src", "xusb_ss", 671 "xusb_ss_src", "xusb_ss_div2", 672 "xusb_hs_src", "xusb_fs_src", 673 "pll_u_480m", "clk_m", "pll_e"; 674 resets = <&tegra_car 89>, <&tegra_car 156>, 675 <&tegra_car 143>; 676 reset-names = "xusb_host", "xusb_ss", "xusb_src"; 677 678 nvidia,xusb-padctl = <&padctl>; 679 680 status = "disabled"; 681 }; 682 683 padctl: padctl@7009f000 { 684 compatible = "nvidia,tegra132-xusb-padctl", 685 "nvidia,tegra124-xusb-padctl"; 686 reg = <0x0 0x7009f000 0x0 0x1000>; 687 resets = <&tegra_car 142>; 688 reset-names = "padctl"; 689 690 pads { 691 usb2 { 692 status = "disabled"; 693 694 lanes { 695 usb2-0 { 696 status = "disabled"; 697 #phy-cells = <0>; 698 }; 699 700 usb2-1 { 701 status = "disabled"; 702 #phy-cells = <0>; 703 }; 704 705 usb2-2 { 706 status = "disabled"; 707 #phy-cells = <0>; 708 }; 709 }; 710 }; 711 712 ulpi { 713 status = "disabled"; 714 715 lanes { 716 ulpi-0 { 717 status = "disabled"; 718 #phy-cells = <0>; 719 }; 720 }; 721 }; 722 723 hsic { 724 status = "disabled"; 725 726 lanes { 727 hsic-0 { 728 status = "disabled"; 729 #phy-cells = <0>; 730 }; 731 732 hsic-1 { 733 status = "disabled"; 734 #phy-cells = <0>; 735 }; 736 }; 737 }; 738 739 pcie { 740 status = "disabled"; 741 742 lanes { 743 pcie-0 { 744 status = "disabled"; 745 #phy-cells = <0>; 746 }; 747 748 pcie-1 { 749 status = "disabled"; 750 #phy-cells = <0>; 751 }; 752 753 pcie-2 { 754 status = "disabled"; 755 #phy-cells = <0>; 756 }; 757 758 pcie-3 { 759 status = "disabled"; 760 #phy-cells = <0>; 761 }; 762 763 pcie-4 { 764 status = "disabled"; 765 #phy-cells = <0>; 766 }; 767 }; 768 }; 769 770 sata { 771 status = "disabled"; 772 773 lanes { 774 sata-0 { 775 status = "disabled"; 776 #phy-cells = <0>; 777 }; 778 }; 779 }; 780 }; 781 782 ports { 783 usb2-0 { 784 status = "disabled"; 785 }; 786 787 usb2-1 { 788 status = "disabled"; 789 }; 790 791 usb2-2 { 792 status = "disabled"; 793 }; 794 795 hsic-0 { 796 status = "disabled"; 797 }; 798 799 hsic-1 { 800 status = "disabled"; 801 }; 802 803 usb3-0 { 804 status = "disabled"; 805 }; 806 807 usb3-1 { 808 status = "disabled"; 809 }; 810 }; 811 }; 812 813 mmc@700b0000 { 814 compatible = "nvidia,tegra124-sdhci"; 815 reg = <0x0 0x700b0000 0x0 0x200>; 816 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 817 clocks = <&tegra_car TEGRA124_CLK_SDMMC1>; 818 clock-names = "sdhci"; 819 resets = <&tegra_car 14>; 820 reset-names = "sdhci"; 821 status = "disabled"; 822 }; 823 824 mmc@700b0200 { 825 compatible = "nvidia,tegra124-sdhci"; 826 reg = <0x0 0x700b0200 0x0 0x200>; 827 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 828 clocks = <&tegra_car TEGRA124_CLK_SDMMC2>; 829 clock-names = "sdhci"; 830 resets = <&tegra_car 9>; 831 reset-names = "sdhci"; 832 status = "disabled"; 833 }; 834 835 mmc@700b0400 { 836 compatible = "nvidia,tegra124-sdhci"; 837 reg = <0x0 0x700b0400 0x0 0x200>; 838 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 839 clocks = <&tegra_car TEGRA124_CLK_SDMMC3>; 840 clock-names = "sdhci"; 841 resets = <&tegra_car 69>; 842 reset-names = "sdhci"; 843 status = "disabled"; 844 }; 845 846 mmc@700b0600 { 847 compatible = "nvidia,tegra124-sdhci"; 848 reg = <0x0 0x700b0600 0x0 0x200>; 849 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 850 clocks = <&tegra_car TEGRA124_CLK_SDMMC4>; 851 clock-names = "sdhci"; 852 resets = <&tegra_car 15>; 853 reset-names = "sdhci"; 854 status = "disabled"; 855 }; 856 857 soctherm: thermal-sensor@700e2000 { 858 compatible = "nvidia,tegra132-soctherm"; 859 reg = <0x0 0x700e2000 0x0 0x600>, /* 0: SOC_THERM reg_base */ 860 <0x0 0x70040000 0x0 0x200>; /* 2: CCROC reg_base */ 861 reg-names = "soctherm-reg", "ccroc-reg"; 862 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 863 clocks = <&tegra_car TEGRA124_CLK_TSENSOR>, 864 <&tegra_car TEGRA124_CLK_SOC_THERM>; 865 clock-names = "tsensor", "soctherm"; 866 resets = <&tegra_car 78>; 867 reset-names = "soctherm"; 868 #thermal-sensor-cells = <1>; 869 870 throttle-cfgs { 871 throttle_heavy: heavy { 872 nvidia,priority = <100>; 873 nvidia,cpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_HIGH>; 874 875 #cooling-cells = <2>; 876 }; 877 }; 878 }; 879 880 thermal-zones { 881 cpu { 882 polling-delay-passive = <1000>; 883 polling-delay = <0>; 884 885 thermal-sensors = 886 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; 887 888 trips { 889 cpu_shutdown_trip { 890 temperature = <105000>; 891 hysteresis = <1000>; 892 type = "critical"; 893 }; 894 895 cpu_throttle_trip: throttle-trip { 896 temperature = <102000>; 897 hysteresis = <1000>; 898 type = "hot"; 899 }; 900 }; 901 902 cooling-maps { 903 map0 { 904 trip = <&cpu_throttle_trip>; 905 cooling-device = <&throttle_heavy 1 1>; 906 }; 907 }; 908 }; 909 mem { 910 polling-delay-passive = <0>; 911 polling-delay = <0>; 912 913 thermal-sensors = 914 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>; 915 916 trips { 917 mem_shutdown_trip { 918 temperature = <101000>; 919 hysteresis = <1000>; 920 type = "critical"; 921 }; 922 }; 923 924 cooling-maps { 925 /* 926 * There are currently no cooling maps, 927 * because there are no cooling devices. 928 */ 929 }; 930 }; 931 gpu { 932 polling-delay-passive = <1000>; 933 polling-delay = <0>; 934 935 thermal-sensors = 936 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>; 937 938 trips { 939 gpu_shutdown_trip { 940 temperature = <101000>; 941 hysteresis = <1000>; 942 type = "critical"; 943 }; 944 945 gpu_throttle_trip: throttle-trip { 946 temperature = <99000>; 947 hysteresis = <1000>; 948 type = "hot"; 949 }; 950 }; 951 952 cooling-maps { 953 map0 { 954 trip = <&gpu_throttle_trip>; 955 cooling-device = <&throttle_heavy 1 1>; 956 }; 957 }; 958 }; 959 pllx { 960 polling-delay-passive = <0>; 961 polling-delay = <0>; 962 963 thermal-sensors = 964 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>; 965 966 trips { 967 pllx_shutdown_trip { 968 temperature = <105000>; 969 hysteresis = <1000>; 970 type = "critical"; 971 }; 972 }; 973 974 cooling-maps { 975 /* 976 * There are currently no cooling maps, 977 * because there are no cooling devices. 978 */ 979 }; 980 }; 981 }; 982 983 ahub@70300000 { 984 compatible = "nvidia,tegra124-ahub"; 985 reg = <0x0 0x70300000 0x0 0x200>, 986 <0x0 0x70300800 0x0 0x800>, 987 <0x0 0x70300200 0x0 0x600>; 988 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 989 clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>, 990 <&tegra_car TEGRA124_CLK_APBIF>; 991 clock-names = "d_audio", "apbif"; 992 resets = <&tegra_car 106>, /* d_audio */ 993 <&tegra_car 107>, /* apbif */ 994 <&tegra_car 30>, /* i2s0 */ 995 <&tegra_car 11>, /* i2s1 */ 996 <&tegra_car 18>, /* i2s2 */ 997 <&tegra_car 101>, /* i2s3 */ 998 <&tegra_car 102>, /* i2s4 */ 999 <&tegra_car 108>, /* dam0 */ 1000 <&tegra_car 109>, /* dam1 */ 1001 <&tegra_car 110>, /* dam2 */ 1002 <&tegra_car 10>, /* spdif */ 1003 <&tegra_car 153>, /* amx */ 1004 <&tegra_car 185>, /* amx1 */ 1005 <&tegra_car 154>, /* adx */ 1006 <&tegra_car 180>, /* adx1 */ 1007 <&tegra_car 186>, /* afc0 */ 1008 <&tegra_car 187>, /* afc1 */ 1009 <&tegra_car 188>, /* afc2 */ 1010 <&tegra_car 189>, /* afc3 */ 1011 <&tegra_car 190>, /* afc4 */ 1012 <&tegra_car 191>; /* afc5 */ 1013 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", 1014 "i2s3", "i2s4", "dam0", "dam1", "dam2", 1015 "spdif", "amx", "amx1", "adx", "adx1", 1016 "afc0", "afc1", "afc2", "afc3", "afc4", "afc5"; 1017 dmas = <&apbdma 1>, <&apbdma 1>, 1018 <&apbdma 2>, <&apbdma 2>, 1019 <&apbdma 3>, <&apbdma 3>, 1020 <&apbdma 4>, <&apbdma 4>, 1021 <&apbdma 6>, <&apbdma 6>, 1022 <&apbdma 7>, <&apbdma 7>, 1023 <&apbdma 12>, <&apbdma 12>, 1024 <&apbdma 13>, <&apbdma 13>, 1025 <&apbdma 14>, <&apbdma 14>, 1026 <&apbdma 29>, <&apbdma 29>; 1027 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", 1028 "rx3", "tx3", "rx4", "tx4", "rx5", "tx5", 1029 "rx6", "tx6", "rx7", "tx7", "rx8", "tx8", 1030 "rx9", "tx9"; 1031 ranges; 1032 #address-cells = <2>; 1033 #size-cells = <2>; 1034 1035 tegra_i2s0: i2s@70301000 { 1036 compatible = "nvidia,tegra124-i2s"; 1037 reg = <0x0 0x70301000 0x0 0x100>; 1038 nvidia,ahub-cif-ids = <4 4>; 1039 clocks = <&tegra_car TEGRA124_CLK_I2S0>; 1040 clock-names = "i2s"; 1041 resets = <&tegra_car 30>; 1042 reset-names = "i2s"; 1043 status = "disabled"; 1044 }; 1045 1046 tegra_i2s1: i2s@70301100 { 1047 compatible = "nvidia,tegra124-i2s"; 1048 reg = <0x0 0x70301100 0x0 0x100>; 1049 nvidia,ahub-cif-ids = <5 5>; 1050 clocks = <&tegra_car TEGRA124_CLK_I2S1>; 1051 clock-names = "i2s"; 1052 resets = <&tegra_car 11>; 1053 reset-names = "i2s"; 1054 status = "disabled"; 1055 }; 1056 1057 tegra_i2s2: i2s@70301200 { 1058 compatible = "nvidia,tegra124-i2s"; 1059 reg = <0x0 0x70301200 0x0 0x100>; 1060 nvidia,ahub-cif-ids = <6 6>; 1061 clocks = <&tegra_car TEGRA124_CLK_I2S2>; 1062 clock-names = "i2s"; 1063 resets = <&tegra_car 18>; 1064 reset-names = "i2s"; 1065 status = "disabled"; 1066 }; 1067 1068 tegra_i2s3: i2s@70301300 { 1069 compatible = "nvidia,tegra124-i2s"; 1070 reg = <0x0 0x70301300 0x0 0x100>; 1071 nvidia,ahub-cif-ids = <7 7>; 1072 clocks = <&tegra_car TEGRA124_CLK_I2S3>; 1073 clock-names = "i2s"; 1074 resets = <&tegra_car 101>; 1075 reset-names = "i2s"; 1076 status = "disabled"; 1077 }; 1078 1079 tegra_i2s4: i2s@70301400 { 1080 compatible = "nvidia,tegra124-i2s"; 1081 reg = <0x0 0x70301400 0x0 0x100>; 1082 nvidia,ahub-cif-ids = <8 8>; 1083 clocks = <&tegra_car TEGRA124_CLK_I2S4>; 1084 clock-names = "i2s"; 1085 resets = <&tegra_car 102>; 1086 reset-names = "i2s"; 1087 status = "disabled"; 1088 }; 1089 }; 1090 1091 usb@7d000000 { 1092 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 1093 reg = <0x0 0x7d000000 0x0 0x4000>; 1094 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1095 phy_type = "utmi"; 1096 clocks = <&tegra_car TEGRA124_CLK_USBD>; 1097 clock-names = "usb"; 1098 resets = <&tegra_car 22>; 1099 reset-names = "usb"; 1100 nvidia,phy = <&phy1>; 1101 status = "disabled"; 1102 }; 1103 1104 phy1: usb-phy@7d000000 { 1105 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; 1106 reg = <0x0 0x7d000000 0x0 0x4000>, 1107 <0x0 0x7d000000 0x0 0x4000>; 1108 phy_type = "utmi"; 1109 clocks = <&tegra_car TEGRA124_CLK_USBD>, 1110 <&tegra_car TEGRA124_CLK_PLL_U>, 1111 <&tegra_car TEGRA124_CLK_USBD>; 1112 clock-names = "reg", "pll_u", "utmi-pads"; 1113 resets = <&tegra_car 22>, <&tegra_car 22>; 1114 reset-names = "usb", "utmi-pads"; 1115 nvidia,hssync-start-delay = <0>; 1116 nvidia,idle-wait-delay = <17>; 1117 nvidia,elastic-limit = <16>; 1118 nvidia,term-range-adj = <6>; 1119 nvidia,xcvr-setup = <9>; 1120 nvidia,xcvr-lsfslew = <0>; 1121 nvidia,xcvr-lsrslew = <3>; 1122 nvidia,hssquelch-level = <2>; 1123 nvidia,hsdiscon-level = <5>; 1124 nvidia,xcvr-hsslew = <12>; 1125 nvidia,has-utmi-pad-registers; 1126 status = "disabled"; 1127 }; 1128 1129 usb@7d004000 { 1130 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 1131 reg = <0x0 0x7d004000 0x0 0x4000>; 1132 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1133 phy_type = "utmi"; 1134 clocks = <&tegra_car TEGRA124_CLK_USB2>; 1135 clock-names = "usb"; 1136 resets = <&tegra_car 58>; 1137 reset-names = "usb"; 1138 nvidia,phy = <&phy2>; 1139 status = "disabled"; 1140 }; 1141 1142 phy2: usb-phy@7d004000 { 1143 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; 1144 reg = <0x0 0x7d004000 0x0 0x4000>, 1145 <0x0 0x7d000000 0x0 0x4000>; 1146 phy_type = "utmi"; 1147 clocks = <&tegra_car TEGRA124_CLK_USB2>, 1148 <&tegra_car TEGRA124_CLK_PLL_U>, 1149 <&tegra_car TEGRA124_CLK_USBD>; 1150 clock-names = "reg", "pll_u", "utmi-pads"; 1151 resets = <&tegra_car 58>, <&tegra_car 22>; 1152 reset-names = "usb", "utmi-pads"; 1153 nvidia,hssync-start-delay = <0>; 1154 nvidia,idle-wait-delay = <17>; 1155 nvidia,elastic-limit = <16>; 1156 nvidia,term-range-adj = <6>; 1157 nvidia,xcvr-setup = <9>; 1158 nvidia,xcvr-lsfslew = <0>; 1159 nvidia,xcvr-lsrslew = <3>; 1160 nvidia,hssquelch-level = <2>; 1161 nvidia,hsdiscon-level = <5>; 1162 nvidia,xcvr-hsslew = <12>; 1163 status = "disabled"; 1164 }; 1165 1166 usb@7d008000 { 1167 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 1168 reg = <0x0 0x7d008000 0x0 0x4000>; 1169 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1170 phy_type = "utmi"; 1171 clocks = <&tegra_car TEGRA124_CLK_USB3>; 1172 clock-names = "usb"; 1173 resets = <&tegra_car 59>; 1174 reset-names = "usb"; 1175 nvidia,phy = <&phy3>; 1176 status = "disabled"; 1177 }; 1178 1179 phy3: usb-phy@7d008000 { 1180 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; 1181 reg = <0x0 0x7d008000 0x0 0x4000>, 1182 <0x0 0x7d000000 0x0 0x4000>; 1183 phy_type = "utmi"; 1184 clocks = <&tegra_car TEGRA124_CLK_USB3>, 1185 <&tegra_car TEGRA124_CLK_PLL_U>, 1186 <&tegra_car TEGRA124_CLK_USBD>; 1187 clock-names = "reg", "pll_u", "utmi-pads"; 1188 resets = <&tegra_car 59>, <&tegra_car 22>; 1189 reset-names = "usb", "utmi-pads"; 1190 nvidia,hssync-start-delay = <0>; 1191 nvidia,idle-wait-delay = <17>; 1192 nvidia,elastic-limit = <16>; 1193 nvidia,term-range-adj = <6>; 1194 nvidia,xcvr-setup = <9>; 1195 nvidia,xcvr-lsfslew = <0>; 1196 nvidia,xcvr-lsrslew = <3>; 1197 nvidia,hssquelch-level = <2>; 1198 nvidia,hsdiscon-level = <5>; 1199 nvidia,xcvr-hsslew = <12>; 1200 status = "disabled"; 1201 }; 1202 1203 cpus { 1204 #address-cells = <1>; 1205 #size-cells = <0>; 1206 1207 cpu@0 { 1208 device_type = "cpu"; 1209 compatible = "nvidia,denver"; 1210 reg = <0>; 1211 }; 1212 1213 cpu@1 { 1214 device_type = "cpu"; 1215 compatible = "nvidia,denver"; 1216 reg = <1>; 1217 }; 1218 }; 1219 1220 timer { 1221 compatible = "arm,armv7-timer"; 1222 interrupts = <GIC_PPI 13 1223 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1224 <GIC_PPI 14 1225 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1226 <GIC_PPI 11 1227 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1228 <GIC_PPI 10 1229 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1230 interrupt-parent = <&gic>; 1231 }; 1232}; 1233